From a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5 Mon Sep 17 00:00:00 2001 From: matt Date: Mon, 30 Mar 2009 02:54:51 +0000 Subject: new fifos copied over from other project git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10709 221aa14e-8319-0410-a670-987f0aec2ac5 --- control_lib/newfifo/fifo_new_tb.vcd | 5506 +++++++++++++++++++++++++++++++++++ 1 file changed, 5506 insertions(+) create mode 100644 control_lib/newfifo/fifo_new_tb.vcd (limited to 'control_lib/newfifo/fifo_new_tb.vcd') diff --git a/control_lib/newfifo/fifo_new_tb.vcd b/control_lib/newfifo/fifo_new_tb.vcd new file mode 100644 index 000000000..796889e7d --- /dev/null +++ b/control_lib/newfifo/fifo_new_tb.vcd @@ -0,0 +1,5506 @@ +$date + Thu Mar 19 17:21:11 2009 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module fifo_new_tb $end +$var wire 1 ! dst_rdy_f36i $end +$var wire 36 " f36_in [35:0] $end +$var wire 36 # i1 [35:0] $end +$var wire 1 $ i1_dr $end +$var wire 1 % i1_sr $end +$var wire 19 & i2 [18:0] $end +$var wire 1 ' i2_dr $end +$var wire 1 ( i2_sr $end +$var wire 19 ) i3 [18:0] $end +$var wire 1 * i3_dr $end +$var wire 1 + i3_sr $end +$var wire 36 , i4 [35:0] $end +$var wire 1 - i4_sr $end +$var wire 8 . ll_data [7:0] $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 0 ll_eof_n $end +$var wire 1 1 ll_sof_n $end +$var wire 1 2 ll_src_rdy_n $end +$var reg 1 3 clear $end +$var reg 1 4 clk $end +$var reg 16 5 count [15:0] $end +$var reg 1 6 dst_rdy_f36o $end +$var reg 32 7 f36_data [31:0] $end +$var reg 1 8 f36_eof $end +$var reg 2 9 f36_occ [1:0] $end +$var reg 1 : f36_sof $end +$var reg 1 ; i4_dr $end +$var reg 1 < rst $end +$var reg 1 = src_rdy_f36i $end +$scope module fifo_short1 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 36 @ datain [35:0] $end +$var wire 36 A dataout [35:0] $end +$var wire 1 $ dst_rdy_i $end +$var wire 1 ! dst_rdy_o $end +$var wire 1 B read $end +$var wire 1 C reset $end +$var wire 1 D src_rdy_i $end +$var wire 1 % src_rdy_o $end +$var wire 1 E write $end +$var reg 4 F a [3:0] $end +$var reg 1 G empty $end +$var reg 1 H full $end +$var reg 5 I occupied [4:0] $end +$var reg 5 J space [4:0] $end +$scope begin gen_srl16[0] $end +$scope module srl16e $end +$var wire 1 K A0 $end +$var wire 1 L A1 $end +$var wire 1 M A2 $end +$var wire 1 N A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 O D $end +$var wire 1 P Q $end +$var reg 16 Q data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[1] $end +$scope module srl16e $end +$var wire 1 R A0 $end +$var wire 1 S A1 $end +$var wire 1 T A2 $end +$var wire 1 U A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 V D $end +$var wire 1 W Q $end +$var reg 16 X data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[2] $end +$scope module srl16e $end +$var wire 1 Y A0 $end +$var wire 1 Z A1 $end +$var wire 1 [ A2 $end +$var wire 1 \ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ] D $end +$var wire 1 ^ Q $end +$var reg 16 _ data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[3] $end +$scope module srl16e $end +$var wire 1 ` A0 $end +$var wire 1 a A1 $end +$var wire 1 b A2 $end +$var wire 1 c A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 d D $end +$var wire 1 e Q $end +$var reg 16 f data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[4] $end +$scope module srl16e $end +$var wire 1 g A0 $end +$var wire 1 h A1 $end +$var wire 1 i A2 $end +$var wire 1 j A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 k D $end +$var wire 1 l Q $end +$var reg 16 m data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[5] $end +$scope module srl16e $end +$var wire 1 n A0 $end +$var wire 1 o A1 $end +$var wire 1 p A2 $end +$var wire 1 q A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 r D $end +$var wire 1 s Q $end +$var reg 16 t data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[6] $end +$scope module srl16e $end +$var wire 1 u A0 $end +$var wire 1 v A1 $end +$var wire 1 w A2 $end +$var wire 1 x A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 y D $end +$var wire 1 z Q $end +$var reg 16 { data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[7] $end +$scope module srl16e $end +$var wire 1 | A0 $end +$var wire 1 } A1 $end +$var wire 1 ~ A2 $end +$var wire 1 !" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 "" D $end +$var wire 1 #" Q $end +$var reg 16 $" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[8] $end +$scope module srl16e $end +$var wire 1 %" A0 $end +$var wire 1 &" A1 $end +$var wire 1 '" A2 $end +$var wire 1 (" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 )" D $end +$var wire 1 *" Q $end +$var reg 16 +" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[9] $end +$scope module srl16e $end +$var wire 1 ," A0 $end +$var wire 1 -" A1 $end +$var wire 1 ." A2 $end +$var wire 1 /" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 0" D $end +$var wire 1 1" Q $end +$var reg 16 2" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[10] $end +$scope module srl16e $end +$var wire 1 3" A0 $end +$var wire 1 4" A1 $end +$var wire 1 5" A2 $end +$var wire 1 6" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 7" D $end +$var wire 1 8" Q $end +$var reg 16 9" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[11] $end +$scope module srl16e $end +$var wire 1 :" A0 $end +$var wire 1 ;" A1 $end +$var wire 1 <" A2 $end +$var wire 1 =" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 >" D $end +$var wire 1 ?" Q $end +$var reg 16 @" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[12] $end +$scope module srl16e $end +$var wire 1 A" A0 $end +$var wire 1 B" A1 $end +$var wire 1 C" A2 $end +$var wire 1 D" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 E" D $end +$var wire 1 F" Q $end +$var reg 16 G" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[13] $end +$scope module srl16e $end +$var wire 1 H" A0 $end +$var wire 1 I" A1 $end +$var wire 1 J" A2 $end +$var wire 1 K" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 L" D $end +$var wire 1 M" Q $end +$var reg 16 N" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[14] $end +$scope module srl16e $end +$var wire 1 O" A0 $end +$var wire 1 P" A1 $end +$var wire 1 Q" A2 $end +$var wire 1 R" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 S" D $end +$var wire 1 T" Q $end +$var reg 16 U" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[15] $end +$scope module srl16e $end +$var wire 1 V" A0 $end +$var wire 1 W" A1 $end +$var wire 1 X" A2 $end +$var wire 1 Y" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 Z" D $end +$var wire 1 [" Q $end +$var reg 16 \" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[16] $end +$scope module srl16e $end +$var wire 1 ]" A0 $end +$var wire 1 ^" A1 $end +$var wire 1 _" A2 $end +$var wire 1 `" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 a" D $end +$var wire 1 b" Q $end +$var reg 16 c" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[17] $end +$scope module srl16e $end +$var wire 1 d" A0 $end +$var wire 1 e" A1 $end +$var wire 1 f" A2 $end +$var wire 1 g" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 h" D $end +$var wire 1 i" Q $end +$var reg 16 j" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[18] $end +$scope module srl16e $end +$var wire 1 k" A0 $end +$var wire 1 l" A1 $end +$var wire 1 m" A2 $end +$var wire 1 n" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 o" D $end +$var wire 1 p" Q $end +$var reg 16 q" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[19] $end +$scope module srl16e $end +$var wire 1 r" A0 $end +$var wire 1 s" A1 $end +$var wire 1 t" A2 $end +$var wire 1 u" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 v" D $end +$var wire 1 w" Q $end +$var reg 16 x" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[20] $end +$scope module srl16e $end +$var wire 1 y" A0 $end +$var wire 1 z" A1 $end +$var wire 1 {" A2 $end +$var wire 1 |" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 }" D $end +$var wire 1 ~" Q $end +$var reg 16 !# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[21] $end +$scope module srl16e $end +$var wire 1 "# A0 $end +$var wire 1 ## A1 $end +$var wire 1 $# A2 $end +$var wire 1 %# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 &# D $end +$var wire 1 '# Q $end +$var reg 16 (# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[22] $end +$scope module srl16e $end +$var wire 1 )# A0 $end +$var wire 1 *# A1 $end +$var wire 1 +# A2 $end +$var wire 1 ,# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 -# D $end +$var wire 1 .# Q $end +$var reg 16 /# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[23] $end +$scope module srl16e $end +$var wire 1 0# A0 $end +$var wire 1 1# A1 $end +$var wire 1 2# A2 $end +$var wire 1 3# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 4# D $end +$var wire 1 5# Q $end +$var reg 16 6# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[24] $end +$scope module srl16e $end +$var wire 1 7# A0 $end +$var wire 1 8# A1 $end +$var wire 1 9# A2 $end +$var wire 1 :# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ;# D $end +$var wire 1 <# Q $end +$var reg 16 =# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[25] $end +$scope module srl16e $end +$var wire 1 ># A0 $end +$var wire 1 ?# A1 $end +$var wire 1 @# A2 $end +$var wire 1 A# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 B# D $end +$var wire 1 C# Q $end +$var reg 16 D# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[26] $end +$scope module srl16e $end +$var wire 1 E# A0 $end +$var wire 1 F# A1 $end +$var wire 1 G# A2 $end +$var wire 1 H# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 I# D $end +$var wire 1 J# Q $end +$var reg 16 K# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[27] $end +$scope module srl16e $end +$var wire 1 L# A0 $end +$var wire 1 M# A1 $end +$var wire 1 N# A2 $end +$var wire 1 O# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 P# D $end +$var wire 1 Q# Q $end +$var reg 16 R# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[28] $end +$scope module srl16e $end +$var wire 1 S# A0 $end +$var wire 1 T# A1 $end +$var wire 1 U# A2 $end +$var wire 1 V# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 W# D $end +$var wire 1 X# Q $end +$var reg 16 Y# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[29] $end +$scope module srl16e $end +$var wire 1 Z# A0 $end +$var wire 1 [# A1 $end +$var wire 1 \# A2 $end +$var wire 1 ]# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ^# D $end +$var wire 1 _# Q $end +$var reg 16 `# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[30] $end +$scope module srl16e $end +$var wire 1 a# A0 $end +$var wire 1 b# A1 $end +$var wire 1 c# A2 $end +$var wire 1 d# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 e# D $end +$var wire 1 f# Q $end +$var reg 16 g# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[31] $end +$scope module srl16e $end +$var wire 1 h# A0 $end +$var wire 1 i# A1 $end +$var wire 1 j# A2 $end +$var wire 1 k# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 l# D $end +$var wire 1 m# Q $end +$var reg 16 n# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[32] $end +$scope module srl16e $end +$var wire 1 o# A0 $end +$var wire 1 p# A1 $end +$var wire 1 q# A2 $end +$var wire 1 r# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 s# D $end +$var wire 1 t# Q $end +$var reg 16 u# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[33] $end +$scope module srl16e $end +$var wire 1 v# A0 $end +$var wire 1 w# A1 $end +$var wire 1 x# A2 $end +$var wire 1 y# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 z# D $end +$var wire 1 {# Q $end +$var reg 16 |# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[34] $end +$scope module srl16e $end +$var wire 1 }# A0 $end +$var wire 1 ~# A1 $end +$var wire 1 !$ A2 $end +$var wire 1 "$ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 #$ D $end +$var wire 1 $$ Q $end +$var reg 16 %$ data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[35] $end +$scope module srl16e $end +$var wire 1 &$ A0 $end +$var wire 1 '$ A1 $end +$var wire 1 ($ A2 $end +$var wire 1 )$ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 *$ D $end +$var wire 1 +$ Q $end +$var reg 16 ,$ data [15:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module fifo36_to_fifo19 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 -$ f19_dataout [18:0] $end +$var wire 1 ' f19_dst_rdy_i $end +$var wire 1 ( f19_src_rdy_o $end +$var wire 1 .$ f19_xfer $end +$var wire 36 /$ f36_datain [35:0] $end +$var wire 1 $ f36_dst_rdy_o $end +$var wire 1 0$ f36_eof $end +$var wire 1 1$ f36_occ $end +$var wire 1 2$ f36_sof $end +$var wire 1 % f36_src_rdy_i $end +$var wire 1 3$ f36_xfer $end +$var wire 1 4$ half_line $end +$var wire 1 C reset $end +$var reg 1 5$ phase $end +$upscope $end +$scope module fifo19_to_ll8 $end +$var wire 1 6$ advance $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 7$ f19_data [18:0] $end +$var wire 1 ' f19_dst_rdy_o $end +$var wire 1 8$ f19_eof $end +$var wire 1 9$ f19_occ $end +$var wire 1 :$ f19_sof $end +$var wire 1 ( f19_src_rdy_i $end +$var wire 1 ;$ ll_dst_rdy $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 <$ ll_eof $end +$var wire 1 0 ll_eof_n $end +$var wire 1 =$ ll_sof $end +$var wire 1 1 ll_sof_n $end +$var wire 1 >$ ll_src_rdy $end +$var wire 1 2 ll_src_rdy_n $end +$var wire 1 C reset $end +$var reg 8 ?$ ll_data [7:0] $end +$var reg 1 @$ state $end +$upscope $end +$scope module ll8_to_fifo19 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 A$ f19_data [18:0] $end +$var wire 1 * f19_dst_rdy_i $end +$var wire 1 + f19_src_rdy_o $end +$var wire 8 B$ ll_data [7:0] $end +$var wire 1 C$ ll_dst_rdy $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 D$ ll_eof $end +$var wire 1 0 ll_eof_n $end +$var wire 1 E$ ll_sof $end +$var wire 1 1 ll_sof_n $end +$var wire 1 F$ ll_src_rdy $end +$var wire 1 2 ll_src_rdy_n $end +$var wire 1 C reset $end +$var wire 1 G$ xfer_out $end +$var reg 8 H$ dat0 [7:0] $end +$var reg 8 I$ dat1 [7:0] $end +$var reg 1 J$ f19_eof $end +$var reg 1 K$ f19_occ $end +$var reg 1 L$ f19_sof $end +$var reg 2 M$ state [1:0] $end +$upscope $end +$scope module fifo19_to_fifo36 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 N$ f19_datain [18:0] $end +$var wire 1 * f19_dst_rdy_o $end +$var wire 1 O$ f19_eof $end +$var wire 1 P$ f19_occ $end +$var wire 1 Q$ f19_sof $end +$var wire 1 + f19_src_rdy_i $end +$var wire 36 R$ f36_dataout [35:0] $end +$var wire 1 S$ f36_dst_rdy_i $end +$var wire 1 - f36_src_rdy_o $end +$var wire 1 C reset $end +$var wire 1 T$ xfer_out $end +$var reg 16 U$ dat0 [15:0] $end +$var reg 16 V$ dat1 [15:0] $end +$var reg 1 W$ f36_eof $end +$var reg 1 X$ f36_occ $end +$var reg 1 Y$ f36_sof $end +$var reg 2 Z$ state [1:0] $end +$upscope $end +$scope task PutPacketInFIFO36 $end +$var reg 32 [$ data_len [31:0] $end +$var reg 32 \$ data_start [31:0] $end +$upscope $end +$scope task ReadFromFIFO36 $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx \$ +bx [$ +bx Z$ +xY$ +xX$ +xW$ +bx V$ +bx U$ +0T$ +0S$ +b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$ +xQ$ +xP$ +xO$ +bx N$ +bx M$ +xL$ +xK$ +xJ$ +bx I$ +bx H$ +xG$ +xF$ +xE$ +xD$ +xC$ +bx B$ +bx A$ +x@$ +bx ?$ +x>$ +x=$ +x<$ +x;$ +x:$ +x9$ +x8$ +bx 7$ +x6$ +x5$ +x4$ +x3$ +x2$ +x1$ +x0$ +bx /$ +x.$ +bx -$ +b0 ,$ +x+$ +0*$ +x)$ +x($ +x'$ +x&$ +b0 %$ +x$$ +0#$ +x"$ +x!$ +x~# +x}# +b0 |# +x{# +0z# +xy# +xx# +xw# +xv# +b0 u# +xt# +0s# +xr# +xq# +xp# +xo# +b0 n# +xm# +0l# +xk# +xj# +xi# +xh# +b0 g# +xf# +0e# +xd# +xc# +xb# +xa# +b0 `# +x_# +0^# +x]# +x\# +x[# +xZ# +b0 Y# +xX# +0W# +xV# +xU# +xT# +xS# +b0 R# +xQ# +0P# +xO# +xN# +xM# +xL# +b0 K# +xJ# +0I# +xH# +xG# +xF# +xE# +b0 D# +xC# +0B# +xA# +x@# +x?# +x># +b0 =# +x<# +0;# +x:# +x9# +x8# +x7# +b0 6# +x5# +04# +x3# +x2# +x1# +x0# +b0 /# +x.# +0-# +x,# +x+# +x*# +x)# +b0 (# +x'# +0&# +x%# +x$# +x## +x"# +b0 !# +x~" +0}" +x|" +x{" +xz" +xy" +b0 x" +xw" +0v" +xu" +xt" +xs" +xr" +b0 q" +xp" +0o" +xn" +xm" +xl" +xk" +b0 j" +xi" +0h" +xg" +xf" +xe" +xd" +b0 c" +xb" +0a" +x`" +x_" +x^" +x]" +b0 \" +x[" +0Z" +xY" +xX" +xW" +xV" +b0 U" +xT" +0S" +xR" +xQ" +xP" +xO" +b0 N" +xM" +0L" +xK" +xJ" +xI" +xH" +b0 G" +xF" +0E" +xD" +xC" +xB" +xA" +b0 @" +x?" +0>" +x=" +x<" +x;" +x:" +b0 9" +x8" +07" +x6" +x5" +x4" +x3" +b0 2" +x1" +00" +x/" +x." +x-" +x," +b0 +" +x*" +0)" +x(" +x'" +x&" +x%" +b0 $" +x#" +0"" +x!" +x~ +x} +x| +b0 { +xz +0y +xx +xw +xv +xu +b0 t +xs +0r +xq +xp +xo +xn +b0 m +xl +0k +xj +xi +xh +xg +b0 f +xe +0d +xc +xb +xa +x` +b0 _ +x^ +0] +x\ +x[ +xZ +xY +b0 X +xW +0V +xU +xT +xS +xR +b0 Q +xP +0O +xN +xM +xL +xK +bx J +bx I +xH +xG +bx F +0E +0D +1C +xB +bx A +b0 @ +0? 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