From fd4bdced70e5089434ec736b5938456219bda068 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 11 May 2010 17:20:06 -0700
Subject: reverting logic clean up which should have made timing better, but
made it worse instead
---
usrp2/control_lib/settings_bus.v | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v
index aec179516..fc960e456 100644
--- a/usrp2/control_lib/settings_bus.v
+++ b/usrp2/control_lib/settings_bus.v
@@ -10,7 +10,7 @@ module settings_bus
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
- output reg strobe,
+ output strobe,
output reg [7:0] addr,
output reg [31:0] data);
@@ -19,18 +19,18 @@ module settings_bus
always @(posedge wb_clk)
if(wb_rst)
begin
- strobe <= 1'b0;
+ stb_int <= 1'b0;
addr <= 8'd0;
data <= 32'd0;
end
- else if(wb_we_i & wb_stb_i & ~wb_ack_o)
+ else if(wb_we_i & wb_stb_i)
begin
- strobe <= 1'b1;
+ stb_int <= 1'b1;
addr <= wb_adr_i[9:2];
data <= wb_dat_i;
end
else
- strobe <= 1'b0;
+ stb_int <= 1'b0;
always @(posedge wb_clk)
if(wb_rst)
@@ -38,4 +38,11 @@ module settings_bus
else
wb_ack_o <= wb_stb_i & ~wb_ack_o;
+ always @(posedge wb_clk)
+ stb_int_d1 <= stb_int;
+
+ //assign strobe = stb_int & ~stb_int_d1;
+ assign strobe = stb_int & wb_ack_o;
+
endmodule // settings_bus
+
--
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