From f852876884b9c7954419ef1fe85be03ef91bc73a Mon Sep 17 00:00:00 2001
From: matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5>
Date: Thu, 26 Feb 2009 04:42:33 +0000
Subject: timing fix, delays the ethernet flow control by a cycle to get it
 across the chip.  Seems ok in testing.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10523 221aa14e-8319-0410-a670-987f0aec2ac5
---
 eth/rtl/verilog/MAC_tx.v             |  9 +++++++--
 eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v | 10 +++++++++-
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/eth/rtl/verilog/MAC_tx.v b/eth/rtl/verilog/MAC_tx.v
index 50b08dffb..bbf331022 100644
--- a/eth/rtl/verilog/MAC_tx.v
+++ b/eth/rtl/verilog/MAC_tx.v
@@ -127,6 +127,11 @@ wire            MAC_tx_addr_init    ;
 wire            MAC_tx_addr_rd      ;
 wire[7:0]       MAC_tx_addr_data    ;
 
+
+   reg 		xon_gen_d1, xoff_gen_d1;
+   always @(posedge Clk) xon_gen_d1 <= xon_gen;
+   always @(posedge Clk) xoff_gen_d1 <= xoff_gen;
+   
 //******************************************************************************        
 //instantiation                                                              
 //****************************************************************************** 
@@ -147,9 +152,9 @@ MAC_tx_ctrl U_MAC_tx_ctrl(
  //flow control           (//flow control         ),           
 .pause_apply              (pause_apply            ),            
 .pause_quanta_sub         (pause_quanta_sub       ),        
-.xoff_gen                 (xoff_gen               ),        
+.xoff_gen                 (xoff_gen_d1            ),        
 .xoff_gen_complete        (xoff_gen_complete      ),            
-.xon_gen                  (xon_gen                ),            
+.xon_gen                  (xon_gen_d1             ),            
 .xon_gen_complete         (xon_gen_complete       ),        
  //MAC_tx_FF              (//MAC_tx_FF            ),           
 .Fifo_data                (Fifo_data              ),            
diff --git a/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v b/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
index 0fd7c603e..8da2e253c 100644
--- a/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
+++ b/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
@@ -627,7 +627,15 @@ always @ (posedge Clk or posedge Reset)
         pause_quanta_sub    <=0;
 
 // FIXME  The below probably won't work if the pause request comes when we are in the wrong state
-   wire clear_xonxoff = (Current_state==StateSendPauseFrame) & (IPLengthCounter==17);
+   reg clear_xonxoff;
+   always @(posedge Clk or posedge Reset)
+     if(Reset)
+       clear_xonxoff <= 0;
+     else if((Current_state==StateSendPauseFrame) & (IPLengthCounter==17))
+       clear_xonxoff <= 1;
+     else if(~xon_gen & ~xoff_gen)
+       clear_xonxoff <= 0;
+   
 always @ (posedge Clk or posedge Reset)
     if (Reset) 
         xoff_gen_complete   <=0;
-- 
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