From f6f43baa0012a24ed5a8cdf49240e0cb4a1f7d04 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Mon, 15 Feb 2021 17:13:42 -0600 Subject: fpga: lib: Add PHASE parameter to sim_clk_gen --- fpga/usrp3/sim/rfnoc/sim_clock_gen.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv b/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv index ce7d4880a..fbe6497f6 100644 --- a/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv +++ b/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv @@ -15,7 +15,8 @@ module sim_clock_gen #( parameter realtime PERIOD = 10.0, // Period in ns parameter real DUTY_CYCLE = 0.5, // Duty cycle, in the range (0.0, 1.0) - parameter bit AUTOSTART = 1 // Start clock automatically at time 0 + parameter bit AUTOSTART = 1, // Start clock automatically at time 0 + parameter realtime PHASE = 0.0 // Phase offset ) ( output bit clk, output bit rst @@ -112,6 +113,7 @@ module sim_clock_gen #( //-------------------------- initial begin : clock_block + if (PHASE != 0.0) #(PHASE); // Toggle the clock in a loop forever begin : clock_loop #(low_time); -- cgit v1.2.3