From f41f050ef89fc977ba5accbaa26b2175f2de4a5e Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Thu, 26 May 2022 15:15:16 -0500 Subject: fpga: Fix first arg in calls to $fatal() This fixes warnings regarding the first argument to $fatal(), which is supposed to be a number indicating what diagnostics to display. 1 corresponds to "Prints simulation time and location". --- fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv | 10 ++++---- fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv | 10 ++++---- fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv | 12 ++++----- fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv | 14 +++++----- fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv | 9 +++---- fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv | 22 ++++++++-------- .../rfnoc/xport_sv/eth_interface_tb/eth_ifc_tb.sv | 22 ++++++++-------- fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv | 6 ++--- fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g.sv | 30 +++++++++++----------- 9 files changed, 67 insertions(+), 68 deletions(-) diff --git a/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv b/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv index cfba6d2eb..de7a82ae8 100644 --- a/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv +++ b/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv @@ -186,7 +186,7 @@ interface AxiStreamPacketIf #( end end end - + //--------------------------------------- // Packing functions //--------------------------------------- @@ -292,9 +292,9 @@ interface AxiStreamPacketIf #( localparam USER_TRAILING_WIDTH = USER_WIDTH >= TRAILING_WIDTH ? TRAILING_WIDTH : USER_WIDTH; assert (TUSER) else - $fatal("Can't get trailing if TUSER doesn't exist"); + $fatal(1, "Can't get trailing if TUSER doesn't exist"); assert (USER_WIDTH >= TRAILING_WIDTH) else - $fatal("USER_WIDTH is to narrow to contain trailing"); + $fatal(1, "USER_WIDTH is to narrow to contain trailing"); return trailing2keep(tuser[USER_TRAILING_WIDTH-1:0]); endfunction : get_trailing_bytes @@ -302,9 +302,9 @@ interface AxiStreamPacketIf #( localparam USER_TRAILING_WIDTH = USER_WIDTH >= TRAILING_WIDTH ? TRAILING_WIDTH : USER_WIDTH; assert (TUSER) else - $fatal("Can't set trailing if TUSER doesn't exist"); + $fatal(1, "Can't set trailing if TUSER doesn't exist"); assert (USER_WIDTH >= TRAILING_WIDTH) else - $fatal("USER_WIDTH is to narrow to set trailing"); + $fatal(1, "USER_WIDTH is to narrow to set trailing"); tuser[USER_TRAILING_WIDTH-1:0] = keep2trailing(keep); endtask : set_trailing_bytes diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv index 57124a0b5..cb56a68e2 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv @@ -57,15 +57,15 @@ module axi4s_add_bytes #( // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); assert (i.USER_WIDTH == o.USER_WIDTH) else - $fatal("USER_WIDTH mismatch"); + $fatal(1, "USER_WIDTH mismatch"); assert (i.USER_WIDTH >= UWIDTH) else - $fatal("i.USER_WIDTH is to small"); + $fatal(1, "i.USER_WIDTH is to small"); assert (o.USER_WIDTH >= UWIDTH) else - $fatal("o.USER_WIDTH is to small"); + $fatal(1, "o.USER_WIDTH is to small"); assert (ADD_START == 0) else - $fatal("Only tested for ADD_START = 0"); + $fatal(1, "Only tested for ADD_START = 0"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv index c3c71999d..3a434ceb0 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv @@ -27,17 +27,17 @@ module axi4s_fifo #( // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); assert (i.USER_WIDTH == o.USER_WIDTH) else - $fatal("USER_WIDTH mismatch"); + $fatal(1, "USER_WIDTH mismatch"); assert (i.TDATA == o.TDATA) else - $fatal("TDATA present mismatch"); + $fatal(1, "TDATA present mismatch"); assert (i.TUSER == o.TUSER) else - $fatal("TUSER present mismatch"); + $fatal(1, "TUSER present mismatch"); assert (i.TKEEP == o.TKEEP) else - $fatal("TKEEP present mismatch"); + $fatal(1, "TKEEP present mismatch"); assert (i.TLAST == o.TLAST) else - $fatal("TLAST present mismatch"); + $fatal(1, "TLAST present mismatch"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv index a1b744adf..a6d190d92 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv @@ -35,19 +35,19 @@ module axi4s_packet_gate #( // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); assert (i.USER_WIDTH == o.USER_WIDTH) else - $fatal("USER_WIDTH mismatch"); + $fatal(1, "USER_WIDTH mismatch"); assert (i.TDATA == o.TDATA) else - $fatal("TDATA present mismatch"); + $fatal(1, "TDATA present mismatch"); assert (i.TUSER == o.TUSER) else - $fatal("TUSER present mismatch"); + $fatal(1, "TUSER present mismatch"); assert (i.TKEEP == o.TKEEP) else - $fatal("TKEEP present mismatch"); + $fatal(1, "TKEEP present mismatch"); assert (i.TLAST == 1) else - $fatal("i.TLAST not present"); + $fatal(1, "i.TLAST not present"); assert (o.TLAST == 1) else - $fatal("o.TLAST not present"); + $fatal(1, "o.TLAST not present"); end localparam WIDTH = i.DWIDTH + i.UWIDTH + i.KWIDTH; diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv index 382cdb13b..9522a356a 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv @@ -69,11 +69,11 @@ module axi4s_remove_bytes #( localparam MIDDLE = END_BYTE >= START_BYTE; `include "axi4s.vh" - + // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), @@ -162,7 +162,7 @@ module axi4s_remove_bytes #( //----------------------------------------------------------------------- function automatic logic [START_BYTE*8-1:0] start_part([s0.DATA_WIDTH-1:0] data); begin - // workaround :: modelsim optimizer can fail if there is aposibility of a 0+:0 + // workaround :: modelsim optimizer can fail if there is a possibility of a 0+:0 localparam MY_START_BYTE = START_BYTE ? START_BYTE : 1; return data[0+:MY_START_BYTE*8]; end @@ -468,7 +468,6 @@ module axi4s_remove_bytes #( // the WRAP case leans forward one word since it bridges to // the next word so it needs to reach end_plus early - // REMOVE statemachine always_comb begin : reached_end_comb if (MCASE==MS_WRAP) begin reached_end = s0.reached_packet_byte(REM_END); @@ -487,7 +486,7 @@ module axi4s_remove_bytes #( logic s0_tready; always_comb s0.tready = s0_tready; - // Remove Statemachine + // Remove State Machine always_comb begin : remove_next_state // default assignment of next_state next_remove_state = remove_state; diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv index 0660ee961..d146539b2 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv @@ -37,34 +37,34 @@ module axi4s_width_conv #( initial begin if(i.TKEEP) begin assert (!I_USER_TRAILING_BYTES) else - $fatal("I_USER_TRAILING_BYTE set at the same time as TKEEP"); + $fatal(1, "I_USER_TRAILING_BYTE set at the same time as TKEEP"); assert (!i.TUSER) else - $fatal("i.TUSER set- This module does not pass user"); + $fatal(1, "i.TUSER set- This module does not pass user"); end else if(I_USER_TRAILING_BYTES) begin assert (i.USER_WIDTH >= i.TRAILING_WIDTH ) else - $fatal("i.USER_WIDTH does not match TRAILING_WIDTH"); + $fatal(1, "i.USER_WIDTH does not match TRAILING_WIDTH"); end else begin assert (!i.TUSER) else - $fatal("This module does not pass generic user_data"); + $fatal(1, "This module does not pass generic user_data"); end if(o.TKEEP) begin assert (!O_USER_TRAILING_BYTES) else - $fatal("O_USER_TRAILING_BYTE set at the same time as TKEEP"); + $fatal(1, "O_USER_TRAILING_BYTE set at the same time as TKEEP"); assert (!o.TUSER) else - $fatal("O.TUSER set- This module does not pass user"); + $fatal(1, "O.TUSER set- This module does not pass user"); end else if(O_USER_TRAILING_BYTES) begin assert (o.USER_WIDTH >= o.TRAILING_WIDTH) else - $fatal("o.USER_WIDTH does not match TRAILING_WIDTH"); + $fatal(1, "o.USER_WIDTH does not match TRAILING_WIDTH"); end else begin assert (!o.TUSER) else - $fatal("This module does not pass generic user_data"); + $fatal(1, "This module does not pass generic user_data"); end assert (i.TLAST == 1) else - $fatal("i.TLAST not present"); + $fatal(1, "i.TLAST not present"); assert (o.TLAST == 1) else - $fatal("o.TLAST not present"); + $fatal(1, "o.TLAST not present"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), @@ -105,7 +105,7 @@ module axi4s_width_conv #( always_comb s1.tkeep = 'X; always_comb begin : assign_s1_tuser s1.tuser = 0; - // MODELSIM_BUG - deleting the s1_bytes assignment causes modelsim failures. + // MODELSIM_BUG - deleting the s1_bytes assignment causes ModelSim failures. s1_bytes = s1.keep2trailing(s1_tkeep); s1.set_trailing_bytes(s1_tkeep); end diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/eth_ifc_tb.sv b/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/eth_ifc_tb.sv index 2b83ac90e..5a3eb1261 100644 --- a/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/eth_ifc_tb.sv +++ b/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/eth_ifc_tb.sv @@ -42,7 +42,7 @@ module eth_ifc_tb #( localparam SYNC = (ENET_W==512) ? 0:1; localparam ETH_PERIOD = (ENET_W==512) ? 3.1:5.0; // can set PREAMBLE_BYTES to 0 or 6 if SV_ETH_IFC, but otherwise - // it's hardcoded to 6. (0 is normal for 100G)(6 is normal for old Xge) + // it's hard-coded to 6. (0 is normal for 100G)(6 is normal for old Xge) localparam PREAMBLE_BYTES = SV_ETH_IFC ? 0 : 6; // Include for register offsets `include "../eth_regs.vh" @@ -381,7 +381,7 @@ module eth_ifc_tb #( if (PREAMBLE_BYTES == 6) preamble = NORMAL_PREAMBLE; else if (PREAMBLE_BYTES == 0) preamble = NO_PREAMBLE; - else $fatal("Invalid PREAMBLE_BYTES"); + else $fatal(1, "Invalid PREAMBLE_BYTES"); expected[i] = new; send[i] = new; @@ -516,7 +516,7 @@ module eth_ifc_tb #( if (PREAMBLE_BYTES == 6) preamble = ZERO_PREAMBLE; else if (PREAMBLE_BYTES == 0) preamble = NO_PREAMBLE; - else $fatal("Invalid PREAMBLE_BYTES"); + else $fatal(1, "Invalid PREAMBLE_BYTES"); get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256), .ramp_inc(1),.pkt(pay),.SWIDTH(8)); @@ -646,7 +646,7 @@ module eth_ifc_tb #( if (PREAMBLE_BYTES == 6) preamble = NORMAL_PREAMBLE; else if (PREAMBLE_BYTES == 0) preamble = NO_PREAMBLE; - else $fatal("Invalid PREAMBLE_BYTES"); + else $fatal(1, "Invalid PREAMBLE_BYTES"); // build a payload get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256), @@ -715,7 +715,7 @@ module eth_ifc_tb #( void'(expected.pop_front()); ++drop_count; ++pkt_num; - $display("Droped packet %d",pkt_num); + $display("Dropped packet %d",pkt_num); `ASSERT_ERROR(drop_count < EXPECT_DROPS,"Exceeded anticipated number of dropped packets e2v"); end if (expected.size() > 0) begin @@ -785,7 +785,7 @@ module eth_ifc_tb #( if (PREAMBLE_BYTES == 6) preamble = ZERO_PREAMBLE; else if (PREAMBLE_BYTES == 0) preamble = NO_PREAMBLE; - else $fatal("Invalid PREAMBLE_BYTES"); + else $fatal(1, "Invalid PREAMBLE_BYTES"); // build a payload get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256), @@ -917,7 +917,7 @@ module eth_ifc_tb #( if (PREAMBLE_BYTES == 6) preamble = NORMAL_PREAMBLE; else if (PREAMBLE_BYTES == 0) preamble = NO_PREAMBLE; - else $fatal("Invalid PREAMBLE_BYTES"); + else $fatal(1, "Invalid PREAMBLE_BYTES"); // Generic management header mgmt_pl.header = '{ @@ -947,7 +947,7 @@ module eth_ifc_tb #( // Generic management header if (PREAMBLE_BYTES == 6) preamble = ZERO_PREAMBLE; else if (PREAMBLE_BYTES == 0) preamble = NO_PREAMBLE; - else $fatal("Invalid PREAMBLE_BYTES"); + else $fatal(1, "Invalid PREAMBLE_BYTES"); mgmt_pl.header = '{ default:'0, prot_ver:PROTOVER, chdr_width:translate_chdr_w(CHDR_W), src_epid:0 @@ -1065,7 +1065,7 @@ module eth_ifc_tb #( // This can happen in matched bandwidth cases // if there is hold off from upstream // Dropped packets exceed the drop count cause an error - // The actual droped count is compared versus the real count + // The actual dropped count is compared versus the real count test.start_test({TEST_NAME,"::Input overrun"}, 200us); eth.set_master_stall_prob(0); @@ -1081,10 +1081,10 @@ module eth_ifc_tb #( // The actual number of expected drops depends on the // bus width difference between ENET_W and CHDR/CPU_W - // in this SIM unlimited etherent bandwidth is coming in at over 300 MHZ + // in this SIM unlimited Ethernet bandwidth is coming in at over 300 MHZ // and output runs at 200 MHZ. This causes excess BW on transmitter even when matched. expected_drops = 9; - + test_ethchdr(num_samples,.EXPECT_DROPS(expected_drops),.ERROR_PROB(0)); test_ethcpu(num_samples,.EXPECT_DROPS(expected_drops),.ERROR_PROB(0)); test.end_test(); diff --git a/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv b/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv index 14fcbc531..7b04f3109 100644 --- a/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv +++ b/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv @@ -69,7 +69,7 @@ package PkgAxiStreamBfm; bit queue_match; queue_match = 1; // check each element of the queue and clear queue_match if they don't match. - // workaround for vivado bug - could be a==b + // workaround for Vivado bug - could be a==b foreach(a[i]) queue_match = queue_match && a[i] == b[i]; return ((a.size() == b.size()) && queue_match); @@ -242,7 +242,7 @@ package PkgAxiStreamBfm; keep_t my_keep; raw_pkt_t raw; assert (data.size == keep.size) else - $fatal("data and keep have different sizes!"); + $fatal(1, "data and keep have different sizes!"); foreach (data[i]) begin my_keep = this.keep[i]; word = this.data[i]; @@ -312,7 +312,7 @@ package PkgAxiStreamBfm; protected int master_stall_prob = DEF_STALL_PROB; protected int slave_stall_prob = DEF_STALL_PROB; - // Number of clocks betwen packets + // Number of clocks between packets int inter_packet_gap = 0; //--------- diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g.sv index 456db06d9..2cd7fa550 100644 --- a/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g.sv +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g.sv @@ -54,7 +54,7 @@ module eth_100g #( logic usr_tx_reset; logic usr_rx_reset; - // Heirarchical refference (xilinx says it will synthesize) + // Hierarchical reference (Xilinx says it will synthesize) // eth_100g_bd_i/cmac_usplus_0/gt_rxrecclkout} assign rx_rec_clk_out = eth_100g_bd_i.cmac_usplus_0.gt_rxrecclkout[0]; //status registers @@ -98,31 +98,31 @@ module eth_100g #( initial begin assert (mgt_tx.DATA_WIDTH == 512) else - $fatal("mgt_rx.DATA_WIDTH must be 512"); + $fatal(1, "mgt_rx.DATA_WIDTH must be 512"); // $clog2(512/8)+1 assert (mgt_rx.USER_WIDTH == 7) else - $fatal("mgt_rx.USER_WIDTH must be 7"); + $fatal(1, "mgt_rx.USER_WIDTH must be 7"); assert (mgt_tx.TDATA == 1) else - $fatal("mgt_tx.TDATA must be enabled"); + $fatal(1, "mgt_tx.TDATA must be enabled"); assert (mgt_tx.TUSER == 1) else - $fatal("mgt_tx.TUSER must be enabled"); + $fatal(1, "mgt_tx.TUSER must be enabled"); assert (mgt_tx.TKEEP == 1) else - $fatal("mgt_tx.TKEEP must be enabled"); + $fatal(1, "mgt_tx.TKEEP must be enabled"); assert (mgt_tx.TLAST == 1) else - $fatal("mgt_tx.TLAST must be enabled"); + $fatal(1, "mgt_tx.TLAST must be enabled"); assert (mgt_rx.DATA_WIDTH == 512) else - $fatal("mgt_rx.DATA_WIDTH must be 512"); + $fatal(1, "mgt_rx.DATA_WIDTH must be 512"); // $clog2(512/8)+1 assert (mgt_rx.USER_WIDTH == 7) else - $fatal("mgt_rx.DATA_WIDTH must be 7"); + $fatal(1, "mgt_rx.DATA_WIDTH must be 7"); assert (mgt_rx.TDATA == 1) else - $fatal("mgt_rx.TDATA must be enabled"); + $fatal(1, "mgt_rx.TDATA must be enabled"); assert (mgt_rx.TUSER == 1) else - $fatal("mgt_rx.TUSER must be enabled"); + $fatal(1, "mgt_rx.TUSER must be enabled"); assert (mgt_rx.TKEEP == 0) else - $fatal("mgt_rx.TKEEP must not be enabled"); + $fatal(1, "mgt_rx.TKEEP must not be enabled"); assert (mgt_rx.TLAST == 1) else - $fatal("mgt_rx.TLAST must be enabled"); + $fatal(1, "mgt_rx.TLAST must be enabled"); end AxiStreamIf #(.DATA_WIDTH(512),.TUSER(0),.TKEEP(0)) @@ -166,7 +166,7 @@ module eth_100g #( // 0-7 map to PCP codes 0-7. 8 is a global pause request logic [8:0] stat_rx_pause_req ; logic [8:0] ctl_tx_pause_req ; // drive for at least 16 clocks - logic ctl_tx_resend_pause; // resend the pause request (tieing this high forces a spam of resend requests) + logic ctl_tx_resend_pause; // resend the pause request (tying this high forces a spam of resend requests) // QuantaPeriod is 512 bit times or 5.12 ns // resend pause requests so (quanta*QuantaPeriod)/(refresh*QuantaPeriod) is the percentage of BW that gets through. @@ -243,7 +243,7 @@ module eth_100g #( // The sequence of writes was taken from the CMAC example, without any deep knowledge // of what the standard Ethernet connection protocol is. - // Inject writes to perform connection inbetween other SW writes to read the mac. + // Inject writes to perform connection in between other SW writes to read the mac. if (AUTO_CONNECT) begin : yes_auto_connect // defined in https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf // pg 187 -- cgit v1.2.3