From 87ab0dce6f96216d72d4be7b0a5d4a26a7dba598 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 16 May 2010 18:40:53 -0700 Subject: settings bus to dsp_clk now uses clock crossing fifo --- usrp2/top/u2_core/u2_core.v | 20 ++++++++++++-------- usrp2/top/u2_rev3/Makefile | 3 +++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 78922fb4f..dea18b737 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -136,9 +136,9 @@ module u2_core input [3:0] clock_divider ); - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; wire ram_loader_done; wire ram_loader_rst, wb_rst, dsp_rst; @@ -339,7 +339,7 @@ module u2_core .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), .status(status),.sys_int_o(buffer_int), .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), @@ -435,6 +435,10 @@ module u2_core assign s7_dat_i = 32'd0; + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + // Output control lines wire [7:0] clock_outs, serdes_outs, adc_outs; assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; @@ -553,7 +557,7 @@ module u2_core rx_control #(.FIFOSIZE(10)) rx_control (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .master_time(master_time),.overrun(overrun), .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), @@ -563,14 +567,14 @@ module u2_core // dummy_rx dsp_core_rx dsp_core_rx dsp_core_rx (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), .debug(debug_rx_dsp) ); tx_control #(.FIFOSIZE(10)) tx_control (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .master_time(master_time),.underrun(underrun), .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), @@ -579,7 +583,7 @@ module u2_core dsp_core_tx dsp_core_tx (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .dac_a(dac_a),.dac_b(dac_b), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 81d787566..80d09acb7 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -70,6 +70,7 @@ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ control_lib/settings_bus.v \ +control_lib/settings_bus_crossclock.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ @@ -119,6 +120,8 @@ coregen/fifo_xlnx_512x36_2clk.v \ coregen/fifo_xlnx_512x36_2clk.xco \ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ +coregen/fifo_xlnx_16x40_2clk.v \ +coregen/fifo_xlnx_16x40_2clk.xco \ extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ -- cgit v1.2.3 From ac32c1fef042a3041a37a8c68e505156cba31484 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 18 May 2010 00:05:54 -0700 Subject: ignores --- usrp2/top/u2_rev3/.gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/.gitignore b/usrp2/top/u2_rev3/.gitignore index 432f8fd58..f50a2b7e5 100644 --- a/usrp2/top/u2_rev3/.gitignore +++ b/usrp2/top/u2_rev3/.gitignore @@ -54,4 +54,4 @@ /*.rpt /*.cel /*.restore -/build +/build* -- cgit v1.2.3 From 5b449a1ca7aabd5b0201aca069ef088cdca25da7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 18 May 2010 12:16:43 -0700 Subject: get rid of old CVS linkage --- usrp2/opencores/aemb/CVS/.gitignore | 1 - usrp2/opencores/aemb/CVS/Entries | 4 --- usrp2/opencores/aemb/CVS/Repository | 1 - usrp2/opencores/aemb/CVS/Root | 1 - usrp2/opencores/aemb/CVS/Template | 0 usrp2/opencores/aemb/doc/CVS/Entries | 2 -- usrp2/opencores/aemb/doc/CVS/Repository | 1 - usrp2/opencores/aemb/doc/CVS/Root | 1 - usrp2/opencores/aemb/doc/CVS/Template | 0 usrp2/opencores/aemb/rtl/CVS/Entries | 1 - usrp2/opencores/aemb/rtl/CVS/Repository | 1 - usrp2/opencores/aemb/rtl/CVS/Root | 1 - usrp2/opencores/aemb/rtl/CVS/Template | 0 usrp2/opencores/aemb/rtl/verilog/CVS/Entries | 38 ---------------------- usrp2/opencores/aemb/rtl/verilog/CVS/Repository | 1 - usrp2/opencores/aemb/rtl/verilog/CVS/Root | 1 - usrp2/opencores/aemb/rtl/verilog/CVS/Template | 0 usrp2/opencores/aemb/sim/CVS/Entries | 3 -- usrp2/opencores/aemb/sim/CVS/Repository | 1 - usrp2/opencores/aemb/sim/CVS/Root | 1 - usrp2/opencores/aemb/sim/CVS/Template | 0 usrp2/opencores/aemb/sim/verilog/CVS/Entries | 3 -- usrp2/opencores/aemb/sim/verilog/CVS/Repository | 1 - usrp2/opencores/aemb/sim/verilog/CVS/Root | 1 - usrp2/opencores/aemb/sim/verilog/CVS/Template | 0 usrp2/opencores/aemb/sw/CVS/Entries | 2 -- usrp2/opencores/aemb/sw/CVS/Repository | 1 - usrp2/opencores/aemb/sw/CVS/Root | 1 - usrp2/opencores/aemb/sw/CVS/Template | 0 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usrp2/opencores/wb_zbt/CVS/Template diff --git a/usrp2/opencores/aemb/CVS/.gitignore b/usrp2/opencores/aemb/CVS/.gitignore deleted file mode 100644 index b693d7c72..000000000 --- a/usrp2/opencores/aemb/CVS/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/Entries.Log diff --git a/usrp2/opencores/aemb/CVS/Entries b/usrp2/opencores/aemb/CVS/Entries deleted file mode 100644 index 093a9a86a..000000000 --- a/usrp2/opencores/aemb/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -D/rtl//// -D/sim//// -D/sw//// -D/doc//// diff --git a/usrp2/opencores/aemb/CVS/Repository b/usrp2/opencores/aemb/CVS/Repository deleted file mode 100644 index 967f2cedf..000000000 --- a/usrp2/opencores/aemb/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb diff --git a/usrp2/opencores/aemb/CVS/Root b/usrp2/opencores/aemb/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/aemb/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/CVS/Template b/usrp2/opencores/aemb/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/aemb/doc/CVS/Entries b/usrp2/opencores/aemb/doc/CVS/Entries deleted file mode 100644 index 16bb46ac6..000000000 --- a/usrp2/opencores/aemb/doc/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/aeMB_datasheet.pdf/1.3/Tue Jan 15 18:38:57 2008/-kb/ -D diff --git a/usrp2/opencores/aemb/doc/CVS/Repository b/usrp2/opencores/aemb/doc/CVS/Repository deleted file mode 100644 index 41df302a9..000000000 --- a/usrp2/opencores/aemb/doc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/doc diff --git a/usrp2/opencores/aemb/doc/CVS/Root b/usrp2/opencores/aemb/doc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/aemb/doc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/doc/CVS/Template b/usrp2/opencores/aemb/doc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/aemb/rtl/CVS/Entries b/usrp2/opencores/aemb/rtl/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/usrp2/opencores/aemb/rtl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/usrp2/opencores/aemb/rtl/CVS/Repository b/usrp2/opencores/aemb/rtl/CVS/Repository deleted file mode 100644 index e2c1eab77..000000000 --- a/usrp2/opencores/aemb/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/rtl diff --git a/usrp2/opencores/aemb/rtl/CVS/Root b/usrp2/opencores/aemb/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/aemb/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/rtl/CVS/Template b/usrp2/opencores/aemb/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Entries b/usrp2/opencores/aemb/rtl/verilog/CVS/Entries deleted file mode 100644 index f17d70235..000000000 --- a/usrp2/opencores/aemb/rtl/verilog/CVS/Entries +++ /dev/null @@ -1,38 +0,0 @@ -/aeMB2_aslu.v/1.10/Tue May 20 18:13:50 2008// -/aeMB2_bpcu.v/1.5/Tue May 20 18:13:50 2008// -/aeMB2_brcc.v/1.3/Tue May 20 18:13:50 2008// -/aeMB2_bsft.v/1.3/Tue May 20 18:13:50 2008// -/aeMB2_ctrl.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_dparam.v/1.1/Tue May 20 18:13:51 2008// -/aeMB2_dwbif.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_edk32.v/1.8/Tue May 20 18:13:51 2008// -/aeMB2_edk62.v/1.8/Tue May 20 18:13:51 2008// -/aeMB2_exec.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_gprf.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_iche.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_idmx.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_intu.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_iwbif.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_memif.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_mult.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_ofid.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_opmx.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_pipe.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_regf.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_regs.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_sfrf.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_sim.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_sparam.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_spsram.v/1.1/Tue May 20 18:13:51 2008// -/aeMB2_sysc.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_tpsram.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_xslif.v/1.7/Tue May 20 18:13:52 2008// -/aeMB_bpcu.v/1.4/Thu Sep 11 02:11:12 2008// -/aeMB_core.v/1.9/Thu Sep 11 02:11:12 2008// -/aeMB_ctrl.v/1.10/Thu Sep 11 02:11:12 2008// -/aeMB_edk32.v/1.14/Thu Sep 11 02:11:12 2008// -/aeMB_ibuf.v/1.10/Thu Sep 11 02:11:12 2008// -/aeMB_regf.v/1.3/Thu Sep 11 02:11:12 2008// -/aeMB_sim.v/1.2/Thu Jan 22 05:50:30 2009// -/aeMB_xecu.v/1.12/Thu Sep 11 02:11:12 2008// -D diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Repository b/usrp2/opencores/aemb/rtl/verilog/CVS/Repository deleted file mode 100644 index a9de19556..000000000 --- a/usrp2/opencores/aemb/rtl/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/rtl/verilog diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Root b/usrp2/opencores/aemb/rtl/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/aemb/rtl/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Template b/usrp2/opencores/aemb/rtl/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/aemb/sim/CVS/Entries b/usrp2/opencores/aemb/sim/CVS/Entries deleted file mode 100644 index bf457ae67..000000000 --- a/usrp2/opencores/aemb/sim/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -D/verilog//// -/cversim/1.5/Tue Jan 15 18:38:57 2008// -/iversim/1.5/Tue Jan 15 18:38:57 2008// diff --git a/usrp2/opencores/aemb/sim/CVS/Repository b/usrp2/opencores/aemb/sim/CVS/Repository deleted file mode 100644 index c6bd1aa80..000000000 --- a/usrp2/opencores/aemb/sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/sim diff --git a/usrp2/opencores/aemb/sim/CVS/Root b/usrp2/opencores/aemb/sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/aemb/sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/sim/CVS/Template b/usrp2/opencores/aemb/sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/aemb/sim/verilog/CVS/Entries b/usrp2/opencores/aemb/sim/verilog/CVS/Entries deleted file mode 100644 index 34e896e80..000000000 --- a/usrp2/opencores/aemb/sim/verilog/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/aemb2.v/1.3/Tue Jan 15 18:38:57 2008// -/edk32.v/1.12/Tue Jan 15 18:38:57 2008// -D diff --git a/usrp2/opencores/aemb/sim/verilog/CVS/Repository b/usrp2/opencores/aemb/sim/verilog/CVS/Repository deleted file mode 100644 index ff3eabf2d..000000000 --- a/usrp2/opencores/aemb/sim/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/sim/verilog diff --git a/usrp2/opencores/aemb/sim/verilog/CVS/Root b/usrp2/opencores/aemb/sim/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/aemb/sim/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/sim/verilog/CVS/Template b/usrp2/opencores/aemb/sim/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/aemb/sw/CVS/Entries b/usrp2/opencores/aemb/sw/CVS/Entries deleted file mode 100644 index 45725bed9..000000000 --- a/usrp2/opencores/aemb/sw/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -D/c//// -/gccrom/1.13/Sun Jan 20 19:47:57 2008// diff --git a/usrp2/opencores/aemb/sw/CVS/Repository b/usrp2/opencores/aemb/sw/CVS/Repository deleted file mode 100644 index 6de31b8b0..000000000 --- a/usrp2/opencores/aemb/sw/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/sw diff --git a/usrp2/opencores/aemb/sw/CVS/Root b/usrp2/opencores/aemb/sw/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/aemb/sw/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/sw/CVS/Template b/usrp2/opencores/aemb/sw/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/aemb/sw/c/CVS/Entries b/usrp2/opencores/aemb/sw/c/CVS/Entries deleted file mode 100644 index 4867b6318..000000000 --- a/usrp2/opencores/aemb/sw/c/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/aeMB_testbench.c/1.14/Tue Jan 15 18:38:57 2008// -/libaemb.h/1.3/Tue Jan 15 18:38:57 2008// -D diff --git a/usrp2/opencores/aemb/sw/c/CVS/Repository b/usrp2/opencores/aemb/sw/c/CVS/Repository deleted file mode 100644 index 86c411d03..000000000 --- a/usrp2/opencores/aemb/sw/c/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/sw/c diff --git a/usrp2/opencores/aemb/sw/c/CVS/Root b/usrp2/opencores/aemb/sw/c/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/aemb/sw/c/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/sw/c/CVS/Template b/usrp2/opencores/aemb/sw/c/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/CVS/Entries b/usrp2/opencores/i2c/CVS/Entries deleted file mode 100644 index d6947544a..000000000 --- a/usrp2/opencores/i2c/CVS/Entries +++ /dev/null @@ -1,8 +0,0 @@ -D/bench//// -D/doc//// -D/documentation//// -D/rtl//// -D/sim//// -D/software//// -D/verilog//// -D/vhdl//// diff --git a/usrp2/opencores/i2c/CVS/Repository b/usrp2/opencores/i2c/CVS/Repository deleted file mode 100644 index 1a9fe8960..000000000 --- a/usrp2/opencores/i2c/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c diff --git a/usrp2/opencores/i2c/CVS/Root b/usrp2/opencores/i2c/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/CVS/Template b/usrp2/opencores/i2c/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/bench/CVS/Entries b/usrp2/opencores/i2c/bench/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/usrp2/opencores/i2c/bench/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/usrp2/opencores/i2c/bench/CVS/Repository b/usrp2/opencores/i2c/bench/CVS/Repository deleted file mode 100644 index 5597c8aac..000000000 --- a/usrp2/opencores/i2c/bench/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/bench diff --git a/usrp2/opencores/i2c/bench/CVS/Root b/usrp2/opencores/i2c/bench/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/bench/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/bench/CVS/Template b/usrp2/opencores/i2c/bench/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/bench/verilog/CVS/Entries b/usrp2/opencores/i2c/bench/verilog/CVS/Entries deleted file mode 100644 index 2dd779100..000000000 --- a/usrp2/opencores/i2c/bench/verilog/CVS/Entries +++ /dev/null @@ -1,5 +0,0 @@ -/i2c_slave_model.v/1.7/Mon Sep 4 09:08:51 2006// -/spi_slave_model.v/1.1/Sat Feb 28 15:32:54 2004// -/tst_bench_top.v/1.8/Mon Sep 4 09:08:51 2006// -/wb_master_model.v/1.4/Sat Feb 28 15:40:42 2004// -D diff --git a/usrp2/opencores/i2c/bench/verilog/CVS/Repository b/usrp2/opencores/i2c/bench/verilog/CVS/Repository deleted file mode 100644 index b37c379e9..000000000 --- a/usrp2/opencores/i2c/bench/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/bench/verilog diff --git a/usrp2/opencores/i2c/bench/verilog/CVS/Root b/usrp2/opencores/i2c/bench/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/bench/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/bench/verilog/CVS/Template b/usrp2/opencores/i2c/bench/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/doc/CVS/Entries b/usrp2/opencores/i2c/doc/CVS/Entries deleted file mode 100644 index ec323c90b..000000000 --- a/usrp2/opencores/i2c/doc/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/i2c_specs.pdf/1.3/Thu Jul 3 15:20:47 2003/-kb/ -D/src//// diff --git a/usrp2/opencores/i2c/doc/CVS/Repository b/usrp2/opencores/i2c/doc/CVS/Repository deleted file mode 100644 index 2ee10951a..000000000 --- a/usrp2/opencores/i2c/doc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/doc diff --git a/usrp2/opencores/i2c/doc/CVS/Root b/usrp2/opencores/i2c/doc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/doc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/doc/CVS/Template b/usrp2/opencores/i2c/doc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/doc/src/CVS/Entries b/usrp2/opencores/i2c/doc/src/CVS/Entries deleted file mode 100644 index 5eeda5738..000000000 --- a/usrp2/opencores/i2c/doc/src/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/I2C_specs.doc/1.7/Thu Jul 3 15:21:23 2003/-kb/ -D diff --git a/usrp2/opencores/i2c/doc/src/CVS/Repository b/usrp2/opencores/i2c/doc/src/CVS/Repository deleted file mode 100644 index 74dd64858..000000000 --- a/usrp2/opencores/i2c/doc/src/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/doc/src diff --git a/usrp2/opencores/i2c/doc/src/CVS/Root b/usrp2/opencores/i2c/doc/src/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/doc/src/CVS/Root +++ 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b/usrp2/opencores/i2c/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/rtl/verilog/CVS/Entries b/usrp2/opencores/i2c/rtl/verilog/CVS/Entries deleted file mode 100644 index 441bd81af..000000000 --- a/usrp2/opencores/i2c/rtl/verilog/CVS/Entries +++ /dev/null @@ -1,6 +0,0 @@ -/i2c_master_bit_ctrl.v/1.12/Mon Sep 4 09:08:13 2006// -/i2c_master_byte_ctrl.v/1.7/Wed Feb 18 11:40:46 2004// -/i2c_master_defines.v/1.3/Mon Nov 5 11:59:25 2001// -/i2c_master_top.v/1.11/Sun Feb 27 09:26:24 2005// -/timescale.v/1.1/Mon Sep 24 12:21:50 2001// -D diff --git a/usrp2/opencores/i2c/rtl/verilog/CVS/Repository b/usrp2/opencores/i2c/rtl/verilog/CVS/Repository deleted file mode 100644 index 49cc6cce0..000000000 --- a/usrp2/opencores/i2c/rtl/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/rtl/verilog diff --git a/usrp2/opencores/i2c/rtl/verilog/CVS/Root b/usrp2/opencores/i2c/rtl/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- 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a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository deleted file mode 100644 index 94d106eb0..000000000 --- a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/sim/i2c_verilog/run/waves diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/software/CVS/Entries b/usrp2/opencores/i2c/software/CVS/Entries deleted file mode 100644 index 934613477..000000000 --- a/usrp2/opencores/i2c/software/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -D/drivers//// -D/include//// diff --git a/usrp2/opencores/i2c/software/CVS/Repository b/usrp2/opencores/i2c/software/CVS/Repository deleted file mode 100644 index 1b4c9f0bb..000000000 --- a/usrp2/opencores/i2c/software/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/software diff --git a/usrp2/opencores/i2c/software/CVS/Root b/usrp2/opencores/i2c/software/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/software/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/software/CVS/Template b/usrp2/opencores/i2c/software/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/software/drivers/CVS/Entries b/usrp2/opencores/i2c/software/drivers/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/usrp2/opencores/i2c/software/drivers/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/usrp2/opencores/i2c/software/drivers/CVS/Repository b/usrp2/opencores/i2c/software/drivers/CVS/Repository deleted file mode 100644 index 260d7873c..000000000 --- a/usrp2/opencores/i2c/software/drivers/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/software/drivers diff --git a/usrp2/opencores/i2c/software/drivers/CVS/Root b/usrp2/opencores/i2c/software/drivers/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/software/drivers/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/software/drivers/CVS/Template b/usrp2/opencores/i2c/software/drivers/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/software/include/CVS/Entries b/usrp2/opencores/i2c/software/include/CVS/Entries deleted file mode 100644 index ef11b0c73..000000000 --- a/usrp2/opencores/i2c/software/include/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/oc_i2c_master.h/1.1/Thu Nov 22 10:02:19 2001// -D diff --git a/usrp2/opencores/i2c/software/include/CVS/Repository b/usrp2/opencores/i2c/software/include/CVS/Repository deleted file mode 100644 index 2ea08eeec..000000000 --- a/usrp2/opencores/i2c/software/include/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/software/include diff --git a/usrp2/opencores/i2c/software/include/CVS/Root b/usrp2/opencores/i2c/software/include/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/software/include/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/software/include/CVS/Template b/usrp2/opencores/i2c/software/include/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/verilog/CVS/Entries b/usrp2/opencores/i2c/verilog/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/usrp2/opencores/i2c/verilog/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/usrp2/opencores/i2c/verilog/CVS/Repository b/usrp2/opencores/i2c/verilog/CVS/Repository deleted file mode 100644 index acc23265f..000000000 --- a/usrp2/opencores/i2c/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/verilog diff --git a/usrp2/opencores/i2c/verilog/CVS/Root b/usrp2/opencores/i2c/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/verilog/CVS/Template b/usrp2/opencores/i2c/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/i2c/vhdl/CVS/Entries b/usrp2/opencores/i2c/vhdl/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/usrp2/opencores/i2c/vhdl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/usrp2/opencores/i2c/vhdl/CVS/Repository b/usrp2/opencores/i2c/vhdl/CVS/Repository deleted file mode 100644 index 8ee00a788..000000000 --- a/usrp2/opencores/i2c/vhdl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/vhdl diff --git a/usrp2/opencores/i2c/vhdl/CVS/Root b/usrp2/opencores/i2c/vhdl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/i2c/vhdl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/vhdl/CVS/Template b/usrp2/opencores/i2c/vhdl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/simple_gpio/CVS/Entries b/usrp2/opencores/simple_gpio/CVS/Entries deleted file mode 100644 index df1462bb9..000000000 --- a/usrp2/opencores/simple_gpio/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/rtl//// diff --git a/usrp2/opencores/simple_gpio/CVS/Repository b/usrp2/opencores/simple_gpio/CVS/Repository deleted file mode 100644 index b869a0de8..000000000 --- a/usrp2/opencores/simple_gpio/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -simple_gpio diff --git a/usrp2/opencores/simple_gpio/CVS/Root b/usrp2/opencores/simple_gpio/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/simple_gpio/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/simple_gpio/CVS/Template b/usrp2/opencores/simple_gpio/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/simple_gpio/rtl/CVS/Entries b/usrp2/opencores/simple_gpio/rtl/CVS/Entries deleted file mode 100644 index 8c6258130..000000000 --- a/usrp2/opencores/simple_gpio/rtl/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/simple_gpio.v/1.2/Sun Dec 22 16:10:17 2002// -D diff --git a/usrp2/opencores/simple_gpio/rtl/CVS/Repository b/usrp2/opencores/simple_gpio/rtl/CVS/Repository deleted file mode 100644 index 955303d8a..000000000 --- a/usrp2/opencores/simple_gpio/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -simple_gpio/rtl diff --git a/usrp2/opencores/simple_gpio/rtl/CVS/Root b/usrp2/opencores/simple_gpio/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/simple_gpio/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/simple_gpio/rtl/CVS/Template b/usrp2/opencores/simple_gpio/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/simple_pic/CVS/Entries b/usrp2/opencores/simple_pic/CVS/Entries deleted file mode 100644 index df1462bb9..000000000 --- a/usrp2/opencores/simple_pic/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/rtl//// diff --git a/usrp2/opencores/simple_pic/CVS/Repository b/usrp2/opencores/simple_pic/CVS/Repository deleted file mode 100644 index 73de5bf2b..000000000 --- a/usrp2/opencores/simple_pic/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -simple_pic diff --git a/usrp2/opencores/simple_pic/CVS/Root b/usrp2/opencores/simple_pic/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/simple_pic/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/simple_pic/CVS/Template b/usrp2/opencores/simple_pic/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/simple_pic/rtl/CVS/Entries b/usrp2/opencores/simple_pic/rtl/CVS/Entries deleted file mode 100644 index e5e641097..000000000 --- a/usrp2/opencores/simple_pic/rtl/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/simple_pic.v/1.3/Tue Dec 24 10:26:51 2002// -D diff --git a/usrp2/opencores/simple_pic/rtl/CVS/Repository b/usrp2/opencores/simple_pic/rtl/CVS/Repository deleted file mode 100644 index 2639a29e2..000000000 --- a/usrp2/opencores/simple_pic/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -simple_pic/rtl diff --git a/usrp2/opencores/simple_pic/rtl/CVS/Root b/usrp2/opencores/simple_pic/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/simple_pic/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/simple_pic/rtl/CVS/Template b/usrp2/opencores/simple_pic/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/CVS/Entries b/usrp2/opencores/spi/CVS/Entries deleted file mode 100644 index 62011c465..000000000 --- a/usrp2/opencores/spi/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -D/bench//// -D/doc//// -D/rtl//// -D/sim//// diff --git a/usrp2/opencores/spi/CVS/Repository b/usrp2/opencores/spi/CVS/Repository deleted file mode 100644 index c928c4b77..000000000 --- a/usrp2/opencores/spi/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi diff --git a/usrp2/opencores/spi/CVS/Root b/usrp2/opencores/spi/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/CVS/Template b/usrp2/opencores/spi/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/bench/CVS/Entries b/usrp2/opencores/spi/bench/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/usrp2/opencores/spi/bench/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/usrp2/opencores/spi/bench/CVS/Repository b/usrp2/opencores/spi/bench/CVS/Repository deleted file mode 100644 index f45728d0f..000000000 --- a/usrp2/opencores/spi/bench/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/bench diff --git a/usrp2/opencores/spi/bench/CVS/Root b/usrp2/opencores/spi/bench/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/bench/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/bench/CVS/Template b/usrp2/opencores/spi/bench/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Entries b/usrp2/opencores/spi/bench/verilog/CVS/Entries deleted file mode 100644 index 68404f871..000000000 --- a/usrp2/opencores/spi/bench/verilog/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -/spi_slave_model.v/1.2/Wed Mar 26 16:00:03 2003// -/tb_spi_top.v/1.6/Mon Mar 15 17:46:04 2004// -/wb_master_model.v/1.1.1.1/Wed Jun 12 15:45:23 2002// -D diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Repository b/usrp2/opencores/spi/bench/verilog/CVS/Repository deleted file mode 100644 index 78a3c4a9f..000000000 --- a/usrp2/opencores/spi/bench/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/bench/verilog diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Root b/usrp2/opencores/spi/bench/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/bench/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Template b/usrp2/opencores/spi/bench/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/doc/CVS/Entries b/usrp2/opencores/spi/doc/CVS/Entries deleted file mode 100644 index ff33fa590..000000000 --- a/usrp2/opencores/spi/doc/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/spi.pdf/1.5/Mon Mar 15 17:46:05 2004/-kb/ -D/src//// diff --git a/usrp2/opencores/spi/doc/CVS/Repository b/usrp2/opencores/spi/doc/CVS/Repository deleted file mode 100644 index 772adcef5..000000000 --- a/usrp2/opencores/spi/doc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/doc diff --git a/usrp2/opencores/spi/doc/CVS/Root b/usrp2/opencores/spi/doc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/doc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/doc/CVS/Template b/usrp2/opencores/spi/doc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/doc/src/CVS/Entries b/usrp2/opencores/spi/doc/src/CVS/Entries deleted file mode 100644 index adcbf083d..000000000 --- a/usrp2/opencores/spi/doc/src/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/spi.doc/1.7/Mon Mar 15 17:46:06 2004/-kb/ -D diff --git a/usrp2/opencores/spi/doc/src/CVS/Repository b/usrp2/opencores/spi/doc/src/CVS/Repository deleted file mode 100644 index 09b1f4a98..000000000 --- a/usrp2/opencores/spi/doc/src/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/doc/src diff --git a/usrp2/opencores/spi/doc/src/CVS/Root b/usrp2/opencores/spi/doc/src/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/doc/src/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/doc/src/CVS/Template b/usrp2/opencores/spi/doc/src/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/rtl/CVS/Entries b/usrp2/opencores/spi/rtl/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/usrp2/opencores/spi/rtl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/usrp2/opencores/spi/rtl/CVS/Repository b/usrp2/opencores/spi/rtl/CVS/Repository deleted file mode 100644 index 5fd79b19b..000000000 --- a/usrp2/opencores/spi/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/rtl diff --git a/usrp2/opencores/spi/rtl/CVS/Root b/usrp2/opencores/spi/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/rtl/CVS/Template b/usrp2/opencores/spi/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Entries b/usrp2/opencores/spi/rtl/verilog/CVS/Entries deleted file mode 100644 index d125a1657..000000000 --- a/usrp2/opencores/spi/rtl/verilog/CVS/Entries +++ /dev/null @@ -1,6 +0,0 @@ -/spi_clgen.v/1.3/Thu Jul 3 17:32:15 2003// -/spi_defines.v/1.8/Mon Mar 15 17:46:08 2004// -/spi_shift.v/1.7/Tue Jul 8 15:36:37 2003// -/spi_top.v/1.8/Tue Jul 8 15:36:37 2003// -/timescale.v/1.1.1.1/Wed Jun 12 15:45:23 2002// -D diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Repository b/usrp2/opencores/spi/rtl/verilog/CVS/Repository deleted file mode 100644 index 361b93bf8..000000000 --- a/usrp2/opencores/spi/rtl/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/rtl/verilog diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Root b/usrp2/opencores/spi/rtl/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/rtl/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Template b/usrp2/opencores/spi/rtl/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/sim/CVS/Entries b/usrp2/opencores/spi/sim/CVS/Entries deleted file mode 100644 index 545533337..000000000 --- a/usrp2/opencores/spi/sim/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -D/rtl_sim//// -D/run//// diff --git a/usrp2/opencores/spi/sim/CVS/Repository b/usrp2/opencores/spi/sim/CVS/Repository deleted file mode 100644 index 9ec769309..000000000 --- a/usrp2/opencores/spi/sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/sim diff --git a/usrp2/opencores/spi/sim/CVS/Root b/usrp2/opencores/spi/sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/sim/CVS/Template b/usrp2/opencores/spi/sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries b/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries deleted file mode 100644 index 8ab9f73a7..000000000 --- a/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/run//// diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository b/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository deleted file mode 100644 index c8c6a94c6..000000000 --- a/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/sim/rtl_sim diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Root b/usrp2/opencores/spi/sim/rtl_sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/sim/rtl_sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Template b/usrp2/opencores/spi/sim/rtl_sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries deleted file mode 100644 index 8947f64a0..000000000 --- a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -/rtl.fl/1.1/Mon Mar 15 17:46:08 2004// -/run_sim/1.1/Mon Mar 15 17:46:08 2004// -/sim.fl/1.1/Mon Mar 15 17:46:08 2004// -D diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository deleted file mode 100644 index 5200bb196..000000000 --- a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/sim/rtl_sim/run diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi/sim/run/CVS/Entries b/usrp2/opencores/spi/sim/run/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/usrp2/opencores/spi/sim/run/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/usrp2/opencores/spi/sim/run/CVS/Repository b/usrp2/opencores/spi/sim/run/CVS/Repository deleted file mode 100644 index e8646e70d..000000000 --- a/usrp2/opencores/spi/sim/run/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/sim/run diff --git a/usrp2/opencores/spi/sim/run/CVS/Root b/usrp2/opencores/spi/sim/run/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi/sim/run/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/sim/run/CVS/Template b/usrp2/opencores/spi/sim/run/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/CVS/Entries b/usrp2/opencores/spi_boot/CVS/Entries deleted file mode 100644 index d339433f3..000000000 --- a/usrp2/opencores/spi_boot/CVS/Entries +++ /dev/null @@ -1,9 +0,0 @@ -/COMPILE_LIST/1.2/Thu Apr 14 21:26:22 2005// -/COPYING/1.1/Tue Feb 8 20:14:49 2005// -/KNOWN_BUGS/1.1/Sun Feb 13 18:28:35 2005// -/README/1.12/Thu Apr 14 21:32:58 2005// -D/bench//// -D/doc//// -D/rtl//// -D/sim//// -D/sw//// diff --git a/usrp2/opencores/spi_boot/CVS/Repository b/usrp2/opencores/spi_boot/CVS/Repository deleted file mode 100644 index 6aa579d49..000000000 --- a/usrp2/opencores/spi_boot/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot diff --git a/usrp2/opencores/spi_boot/CVS/Root b/usrp2/opencores/spi_boot/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/CVS/Template b/usrp2/opencores/spi_boot/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/bench/CVS/Entries b/usrp2/opencores/spi_boot/bench/CVS/Entries deleted file mode 100644 index a4756ee6f..000000000 --- a/usrp2/opencores/spi_boot/bench/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/vhdl//// diff --git a/usrp2/opencores/spi_boot/bench/CVS/Repository b/usrp2/opencores/spi_boot/bench/CVS/Repository deleted file mode 100644 index ac45542a6..000000000 --- a/usrp2/opencores/spi_boot/bench/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/bench diff --git a/usrp2/opencores/spi_boot/bench/CVS/Root b/usrp2/opencores/spi_boot/bench/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/bench/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/bench/CVS/Template b/usrp2/opencores/spi_boot/bench/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries deleted file mode 100644 index 8649c9f90..000000000 --- a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries +++ /dev/null @@ -1,13 +0,0 @@ -/card-c.vhd/1.1/Tue Feb 8 21:09:18 2005// -/card.vhd/1.2/Sun Feb 13 17:06:22 2005// -/tb-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem-full-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem-minimal-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem-mmc-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem-sd-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem.vhd/1.7/Thu Apr 7 20:43:36 2005// -/tb_pack-p.vhd/1.2/Tue Mar 8 22:06:39 2005// -/tb_rl-c.vhd/1.1/Sun Apr 10 18:07:26 2005// -/tb_rl.vhd/1.1/Sun Apr 10 18:07:25 2005// -D diff --git a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository deleted file mode 100644 index ce62c2b8e..000000000 --- a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/bench/vhdl diff --git a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/doc/CVS/Entries b/usrp2/opencores/spi_boot/doc/CVS/Entries deleted file mode 100644 index 630615f41..000000000 --- a/usrp2/opencores/spi_boot/doc/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/spi_boot.pdf/1.6/Thu Mar 16 17:09:56 2006/-kb/ -/spi_boot_schematic.pdf/1.3/Thu Apr 14 21:20:35 2005/-kb/ -D/src//// diff --git a/usrp2/opencores/spi_boot/doc/CVS/Repository b/usrp2/opencores/spi_boot/doc/CVS/Repository deleted file mode 100644 index 07fb78846..000000000 --- a/usrp2/opencores/spi_boot/doc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/doc diff --git a/usrp2/opencores/spi_boot/doc/CVS/Root b/usrp2/opencores/spi_boot/doc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/doc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/doc/CVS/Template b/usrp2/opencores/spi_boot/doc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/doc/src/CVS/Entries b/usrp2/opencores/spi_boot/doc/src/CVS/Entries deleted file mode 100644 index b2d32af23..000000000 --- a/usrp2/opencores/spi_boot/doc/src/CVS/Entries +++ /dev/null @@ -1,10 +0,0 @@ -/architecture.eps/1.4/Thu Apr 14 21:18:11 2005/-kb/ -/architecture.fig/1.4/Thu Apr 14 21:18:11 2005/-kb/ -/initialization.eps/1.2/Thu Mar 16 15:41:16 2006/-kb/ -/initialization.fig/1.2/Thu Mar 16 15:41:16 2006/-kb/ -/memory_organization.eps/1.2/Thu Mar 16 16:50:57 2006/-kb/ -/memory_organization.fig/1.2/Thu Mar 16 16:50:57 2006/-kb/ -/spi_boot.sxw/1.6/Thu Mar 16 17:09:31 2006/-kb/ -/transfer.eps/1.1/Sun Feb 27 19:24:30 2005/-kb/ -/transfer.fig/1.1/Sun Feb 27 19:24:35 2005/-kb/ -D diff --git a/usrp2/opencores/spi_boot/doc/src/CVS/Repository b/usrp2/opencores/spi_boot/doc/src/CVS/Repository deleted file mode 100644 index 5f8aafef8..000000000 --- a/usrp2/opencores/spi_boot/doc/src/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/doc/src diff --git a/usrp2/opencores/spi_boot/doc/src/CVS/Root b/usrp2/opencores/spi_boot/doc/src/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/doc/src/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/doc/src/CVS/Template b/usrp2/opencores/spi_boot/doc/src/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/rtl/CVS/Entries b/usrp2/opencores/spi_boot/rtl/CVS/Entries deleted file mode 100644 index a4756ee6f..000000000 --- a/usrp2/opencores/spi_boot/rtl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/vhdl//// diff --git a/usrp2/opencores/spi_boot/rtl/CVS/Repository b/usrp2/opencores/spi_boot/rtl/CVS/Repository deleted file mode 100644 index dcb0a69bc..000000000 --- a/usrp2/opencores/spi_boot/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/rtl diff --git a/usrp2/opencores/spi_boot/rtl/CVS/Root b/usrp2/opencores/spi_boot/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/rtl/CVS/Template b/usrp2/opencores/spi_boot/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries deleted file mode 100644 index 880f353ca..000000000 --- a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries +++ /dev/null @@ -1,15 +0,0 @@ -/chip-e.vhd/1.3/Thu Apr 7 20:44:23 2005// -/chip-full-a.vhd/1.6/Thu Apr 7 20:44:23 2005// -/chip-full-c.vhd/1.1/Tue Feb 8 20:41:31 2005// -/chip-minimal-a.vhd/1.6/Thu Apr 7 20:44:23 2005// -/chip-minimal-c.vhd/1.1/Tue Feb 8 20:41:32 2005// -/chip-mmc-a.vhd/1.6/Thu Apr 7 20:44:23 2005// -/chip-mmc-c.vhd/1.1/Tue Feb 8 20:41:32 2005// -/chip-sd-a.vhd/1.6/Thu Apr 7 20:44:23 2005// -/chip-sd-c.vhd/1.1/Tue Feb 8 20:41:33 2005// -/spi_boot-c.vhd/1.2/Fri Feb 18 06:42:11 2005// -/spi_boot.vhd/1.9/Sun Feb 25 18:24:12 2007// -/spi_boot_pack-p.vhd/1.1/Tue Feb 8 20:41:33 2005// -/spi_counter-c.vhd/1.1/Tue Feb 8 20:41:33 2005// -/spi_counter.vhd/1.2/Sun Feb 25 18:24:12 2007// -D/sample//// diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository deleted file mode 100644 index a09f391ea..000000000 --- a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/rtl/vhdl diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries deleted file mode 100644 index 552a7baad..000000000 --- a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/ram_loader-c.vhd/1.1/Sun Apr 10 18:02:32 2005// -/ram_loader.vhd/1.2/Sun Apr 10 17:17:23 2005// -D diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository deleted file mode 100644 index 026a73983..000000000 --- a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/rtl/vhdl/sample diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/sim/CVS/Entries b/usrp2/opencores/spi_boot/sim/CVS/Entries deleted file mode 100644 index 9487498ad..000000000 --- a/usrp2/opencores/spi_boot/sim/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/rtl_sim//// diff --git a/usrp2/opencores/spi_boot/sim/CVS/Repository b/usrp2/opencores/spi_boot/sim/CVS/Repository deleted file mode 100644 index 4e2e09740..000000000 --- a/usrp2/opencores/spi_boot/sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/sim diff --git a/usrp2/opencores/spi_boot/sim/CVS/Root b/usrp2/opencores/spi_boot/sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/sim/CVS/Template b/usrp2/opencores/spi_boot/sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries deleted file mode 100644 index e3d0dc145..000000000 --- a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile/1.2/Sun Apr 10 18:14:19 2005// -D diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository deleted file mode 100644 index 114ab862f..000000000 --- a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/sim/rtl_sim diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/sw/CVS/Entries b/usrp2/opencores/spi_boot/sw/CVS/Entries deleted file mode 100644 index 0f2bd88d4..000000000 --- a/usrp2/opencores/spi_boot/sw/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/misc//// diff --git a/usrp2/opencores/spi_boot/sw/CVS/Repository b/usrp2/opencores/spi_boot/sw/CVS/Repository deleted file mode 100644 index 98d181ecb..000000000 --- a/usrp2/opencores/spi_boot/sw/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/sw diff --git a/usrp2/opencores/spi_boot/sw/CVS/Root b/usrp2/opencores/spi_boot/sw/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/sw/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/sw/CVS/Template b/usrp2/opencores/spi_boot/sw/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/spi_boot/sw/misc/CVS/Entries b/usrp2/opencores/spi_boot/sw/misc/CVS/Entries deleted file mode 100644 index e46425fde..000000000 --- a/usrp2/opencores/spi_boot/sw/misc/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/bit_reverse.c/1.1/Sun May 21 11:58:00 2006/-ko/ -D diff --git a/usrp2/opencores/spi_boot/sw/misc/CVS/Repository b/usrp2/opencores/spi_boot/sw/misc/CVS/Repository deleted file mode 100644 index 0519f4b59..000000000 --- a/usrp2/opencores/spi_boot/sw/misc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/sw/misc diff --git a/usrp2/opencores/spi_boot/sw/misc/CVS/Root b/usrp2/opencores/spi_boot/sw/misc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/spi_boot/sw/misc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/sw/misc/CVS/Template b/usrp2/opencores/spi_boot/sw/misc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/opencores/wb_zbt/CVS/Entries b/usrp2/opencores/wb_zbt/CVS/Entries deleted file mode 100644 index ef78b4f27..000000000 --- a/usrp2/opencores/wb_zbt/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/wb_zbt.v/1.1/Tue Feb 5 22:31:22 2008// -D diff --git a/usrp2/opencores/wb_zbt/CVS/Repository b/usrp2/opencores/wb_zbt/CVS/Repository deleted file mode 100644 index ca9c641d0..000000000 --- a/usrp2/opencores/wb_zbt/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -wb_zbt diff --git a/usrp2/opencores/wb_zbt/CVS/Root b/usrp2/opencores/wb_zbt/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/usrp2/opencores/wb_zbt/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/wb_zbt/CVS/Template b/usrp2/opencores/wb_zbt/CVS/Template deleted file mode 100644 index e69de29bb..000000000 -- cgit v1.2.3 From b9257e64be63429099186cdb1a3eaff0a325ffb7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 18 May 2010 12:18:31 -0700 Subject: added pragmas suggested by Ian Buckley to help ISE12 synthesis --- usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v index 9ac45299b..7fe108957 100644 --- a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v @@ -146,9 +146,12 @@ module aeMB_regf (/*AUTOARG*/ // LUT RAM implementation is smaller and faster. R0 gets written // during reset with 0x00 and doesn't change after. - reg [31:0] mARAM[0:31], - mBRAM[0:31], - mDRAM[0:31]; + //synthesis attribute ram_style of mARAM is distributed + reg [31:0] mARAM[0:31]; + //synthesis attribute ram_style of mBRAM is distributed + reg [31:0] mBRAM[0:31]; + //synthesis attribute ram_style of mDRAM is distributed + reg [31:0] mDRAM[0:31]; wire [31:0] rREGW = mDRAM[rRW]; wire [31:0] rREGD = mDRAM[rRD]; -- cgit v1.2.3 From 8214a30d10bbe30d04f74acca4bd683dc084f5df Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 18 May 2010 12:36:19 -0700 Subject: added width parameter to avoid warnings (thanks IJB) and default value parameter --- usrp2/control_lib/setting_reg.v | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v index ccbaa3d2e..3d3bb65e5 100644 --- a/usrp2/control_lib/setting_reg.v +++ b/usrp2/control_lib/setting_reg.v @@ -1,14 +1,16 @@ module setting_reg - #(parameter my_addr = 0) + #(parameter my_addr = 0, + parameter width = 32, + parameter at_reset=32'd0) (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); + input wire [31:0] in, output reg [width-1:0] out, output reg changed); always @(posedge clk) if(rst) begin - out <= 32'd0; + out <= at_reset; changed <= 1'b0; end else -- cgit v1.2.3 From 621ad7cc9e68b4e304b616d8f840d3a03a047c8b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 18 May 2010 14:48:42 -0700 Subject: get rid of some warnings by declaring setting reg width --- usrp2/top/u2_core/u2_core.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index dea18b737..df74c7dba 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -448,13 +448,13 @@ module u2_core wire phy_reset; assign PHY_RESETn = ~phy_reset; - setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phy_reset),.changed()); // ///////////////////////////////////////////////////////////////////////// @@ -466,9 +466,9 @@ module u2_core wire [7:0] led_src, led_sw; wire [7:0] led_hw = {clk_status,serdes_link_up}; - setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); @@ -481,7 +481,7 @@ module u2_core {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), .irq(irq) ); @@ -614,7 +614,7 @@ module u2_core wire [19:0] page; wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(page),.changed()); wb_bridge_16_32 bridge -- cgit v1.2.3 From bc6968c3e33cd496c740bfd508c6d2e74d986019 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 19 May 2010 23:52:54 -0700 Subject: fix typo, no functionality difference --- usrp2/vrt/vita_tx_deframer.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 49428ead5..220d3b061 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -28,7 +28,7 @@ module vita_tx_deframer reg [3:0] vita_state; wire has_streamid, has_classid, has_secs, has_tics, has_trailer; - assign has_streamid = (data_i[31:28]==4'b001); + assign has_streamid = (data_i[31:28]==4'b0001); assign has_classid = data_i[27]; assign has_secs = ~(data_i[23:22]==2'b00); assign has_tics = ~(data_i[21:20]==2'b00); -- cgit v1.2.3 From b38d2424b1ac3242146fc9305d9e4ae80e21dede Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 19 May 2010 23:53:13 -0700 Subject: better test program for just the tx side --- usrp2/vrt/vita_tx_tb.v | 226 ++++++++++++++----------------------------------- 1 file changed, 63 insertions(+), 163 deletions(-) diff --git a/usrp2/vrt/vita_tx_tb.v b/usrp2/vrt/vita_tx_tb.v index 90986a35f..0223d6850 100644 --- a/usrp2/vrt/vita_tx_tb.v +++ b/usrp2/vrt/vita_tx_tb.v @@ -5,7 +5,7 @@ module vita_tx_tb; localparam DECIM = 8'd4; localparam INTERP = 8'd4; - localparam MAXCHAN=4; + localparam MAXCHAN=1; localparam NUMCHAN=1; reg clk = 0; @@ -19,9 +19,9 @@ module vita_tx_tb; wire [(MAXCHAN*32)-1:0] sample, sample_tx; wire strobe, run; - wire [35:0] data_o; - wire src_rdy; - wire dst_rdy; + reg [35:0] data_o = 36'h0; + reg src_rdy = 0; + wire dst_rdy; wire [63:0] vita_time; @@ -32,42 +32,13 @@ module vita_tx_tb; wire [7:0] set_addr_dsp; wire [31:0] set_data_dsp; - /* - settings_bus_crossclock settings_bus_xclk_dsp - (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - */ - wire sample_dst_rdy, sample_src_rdy; - //wire [99:0] sample_data_o; wire [64+4+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx; time_64bit #(.TICKS_PER_SEC(100000000), .BASE(0)) time_64bit (.clk(clk), .rst(reset), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(0), .vita_time(vita_time)); - - rx_dsp_model rx_dsp_model - (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0])); - - generate - if(MAXCHAN>1) - assign sample[(MAXCHAN*32)-1:32] = 0; - endgenerate - - vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control - (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .vita_time(vita_time), .overrun(overrun), - .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy), - .sample(sample), .run(run), .strobe(strobe)); - - vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer - (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy), - .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty() ); wire [35:0] data_tx; wire src_rdy_tx, dst_rdy_tx; @@ -89,7 +60,7 @@ module vita_tx_tb; vita_tx_control #(.BASE(16), .WIDTH(MAXCHAN*32)) vita_tx_control (.clk(clk), .reset(reset), .clear(0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .vita_time(vita_time-100), .underrun(underrun), + .vita_time(vita_time), .underrun(underrun), .sample_fifo_i(sample_data_tx), .sample_fifo_dst_rdy_o(sample_dst_rdy_tx), .sample_fifo_src_rdy_i(sample_src_rdy_tx), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx)); @@ -97,28 +68,20 @@ module vita_tx_tb; tx_dsp_model tx_dsp_model (.clk(clk), .reset(reset), .run(run_tx), .interp(INTERP), .strobe(strobe_tx), .sample(sample_tx[31:0] )); - always @(posedge clk) - if(src_rdy & dst_rdy) - begin - if(data_o[32] & ~data_o[33]) - begin - $display("RX-PKT-START %d",$time); - $display(" RX-PKT-DAT %x",data_o[31:0]); - end - else if(data_o[32] & data_o[33]) - begin - $display(" RX-PKT-DAT %x -- With ERR",data_o[31:0]); - $display("RX-PKT-ERR %d",$time); - end - else if(~data_o[32] & data_o[33]) - begin - $display(" RX-PKT-DAT %x",data_o[31:0]); - $display("RX-PKT-END %d",$time); - end - else - $display(" RX-PKT DAT %x",data_o[31:0]); - end - + task write_setting; + input [7:0] addr; + input [31:0] data; + begin + set_stb <= 0; + @(posedge clk); + set_addr <= addr; + set_data <= data; + set_stb <= 1; + @(posedge clk); + set_stb <= 0; + end + endtask // write_setting + initial begin @(negedge reset); @@ -129,124 +92,61 @@ module vita_tx_tb; write_setting(7,8); // Samples per VITA packet write_setting(8,NUMCHAN); // Samples per VITA packet #10000; + queue_vita_packets(32'h300, 106, 32'hF00D_1234, 32'h55AA_AA55); + //queue_vita_packets(32'h300, 6, 32'hF00D_1234, 32'h0); + queue_vita_packets(32'h600, 9, 32'h9876_ABCD, 32'h0); - queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet -/* - queue_rx_cmd(1,0,16,32'h0,32'h0); // send imm, 2 packets worth - queue_rx_cmd(1,0,7,32'h0,32'h0); // send imm, 1 short packet worth - queue_rx_cmd(1,0,9,32'h0,32'h0); // send imm, just longer than 1 packet - - queue_rx_cmd(1,1,16,32'h0,32'h0); // chained - queue_rx_cmd(0,0,8,32'h0,32'h0); // 2nd in chain - - queue_rx_cmd(1,1,17,32'h0,32'h0); // chained, odd length - queue_rx_cmd(0,0,9,32'h0,32'h0); // 2nd in chain, also odd length - - queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time - queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late - - queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain - #100000; - $display("\nEnd chain with zero samples, shouldn't error\n"); - queue_rx_cmd(1,1,8,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error - #100000; - - $display("\nEnd chain with zero samples on odd-length, shouldn't error\n"); - queue_rx_cmd(1,1,14,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error - #100000; - $display("Should have gotten 14 samples and EOF by now\n"); - - queue_rx_cmd(1,1,9,32'h0,32'h0); // chained, but break chain, odd length - #100000; - //dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,0,100,32'h0,32'h0); // long enough to fill the fifos - queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent - #100000; - //dst_rdy <= 1; // restart the reads so we can see what we got - #100000; - //dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,1,100,32'h0,32'h0); // long enough to fill the fifos - //queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent - #100000; - @(posedge clk); - //dst_rdy <= 1; - */ - #100000 $finish; + #300000 $finish; end - task write_setting; - input [7:0] addr; - input [31:0] data; + task queue_vita_packets; + input [31:0] sendtime; + input [15:0] samples; + input [15:0] word; + input [31:0] trailer; + + reg [15:0] i; + begin - set_stb <= 0; @(posedge clk); - set_addr <= addr; - set_data <= data; - set_stb <= 1; + src_rdy <= 1; + data_o <= {4'b0001,4'h1,1'b0,|trailer,2'h3,8'hF0,(16'd5+samples+|trailer)}; // header @(posedge clk); - set_stb <= 0; - end - endtask // write_setting - - task queue_rx_cmd; - input send_imm; - input chain; - input [29:0] lines; - input [31:0] secs; - input [31:0] tics; - begin - write_setting(0,{send_imm,chain,lines}); - write_setting(1,secs); - write_setting(2,tics); + data_o <= {4'b0000,32'h0}; // streamid + @(posedge clk); + data_o <= {4'b0000,32'h0}; // SECS + @(posedge clk); + data_o <= {4'b0000,32'h0}; // TICS + @(posedge clk); + data_o <= {4'b0000,sendtime}; // TICS + @(posedge clk); + + for(i=0;i Date: Thu, 27 May 2010 17:41:50 -0700 Subject: new files from udp branch added to main Makefile --- usrp2/top/u2_rev3/Makefile | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 80d09acb7..7eedf5e7f 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -85,7 +85,16 @@ control_lib/wb_bridge_16_32.v \ control_lib/reset_sync.v \ control_lib/priority_enc.v \ control_lib/pic.v \ +vrt/vita_rx_control.v \ +vrt/vita_rx_framer.v \ +vrt/vita_tx_control.v \ +vrt/vita_tx_deframer.v \ +udp/udp_wrapper.v \ +udp/fifo19_rxrealign.v \ +udp/prot_eng_tx.v \ +udp/add_onescomp.v \ simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac_wrapper19.v \ simple_gemac/simple_gemac.v \ simple_gemac/simple_gemac_wb.v \ simple_gemac/simple_gemac_tx.v \ @@ -106,11 +115,15 @@ control_lib/newfifo/buffer_pool.v \ control_lib/newfifo/fifo_2clock.v \ control_lib/newfifo/fifo_2clock_cascade.v \ control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo19_to_ll8.v \ +control_lib/newfifo/ll8_to_fifo19.v \ +control_lib/newfifo/fifo36_to_fifo19.v \ +control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ @@ -120,6 +133,8 @@ coregen/fifo_xlnx_512x36_2clk.v \ coregen/fifo_xlnx_512x36_2clk.xco \ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ +coregen/fifo_xlnx_16x19_2clk.v \ +coregen/fifo_xlnx_16x19_2clk.xco \ coregen/fifo_xlnx_16x40_2clk.v \ coregen/fifo_xlnx_16x40_2clk.xco \ extram/wb_zbt16_b.v \ @@ -174,10 +189,13 @@ serdes/serdes_fc_rx.v \ serdes/serdes_fc_tx.v \ serdes/serdes_rx.v \ serdes/serdes_tx.v \ +timing/time_64bit.v \ +timing/time_compare.v \ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ +timing/simple_timer.v \ top/u2_core/u2_core.v \ top/u2_rev3/u2_rev3.ucf \ top/u2_rev3/u2_rev3.v -- cgit v1.2.3 From 79ab35283db81f30a4c57ff7b0701cd166d075d6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 27 May 2010 17:57:44 -0700 Subject: ignore output files --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index b275f0e49..872a7824c 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,5 @@ *~ \#*\# a.out +*.vcd +*.lxt -- cgit v1.2.3 From 1b69702c6e5165e887bded5efe9f6d96065b6a74 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 27 May 2010 18:07:00 -0700 Subject: from UDP branch, changed names because I want these separate from the non-udp versions --- usrp2/sdr_lib/dsp_core_rx_udp.v | 183 +++++++++ usrp2/top/u2_core/u2_core_udp.v | 871 ++++++++++++++++++++++++++++++++++++++++ usrp2/top/u2_rev3/Makefile.udp | 267 ++++++++++++ 3 files changed, 1321 insertions(+) create mode 100644 usrp2/sdr_lib/dsp_core_rx_udp.v create mode 100644 usrp2/top/u2_core/u2_core_udp.v create mode 100644 usrp2/top/u2_rev3/Makefile.udp diff --git a/usrp2/sdr_lib/dsp_core_rx_udp.v b/usrp2/sdr_lib/dsp_core_rx_udp.v new file mode 100644 index 000000000..1e689fc7f --- /dev/null +++ b/usrp2/sdr_lib/dsp_core_rx_udp.v @@ -0,0 +1,183 @@ + +module dsp_core_rx + #(parameter BASE = 160) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [13:0] adc_a, input adc_ovf_a, + input [13:0] adc_b, input adc_ovf_b, + + input [15:0] io_rx, + + output [31:0] sample, + input run, + output strobe, + output [31:0] debug + ); + + wire [15:0] scale_i, scale_q; + wire [13:0] adc_a_ofs, adc_b_ofs; + reg [13:0] adc_i, adc_q; + wire [31:0] phase_inc; + reg [31:0] phase; + + wire [35:0] prod_i, prod_q; + wire [23:0] i_cordic, q_cordic; + wire [23:0] i_cic, q_cic; + wire [17:0] i_cic_scaled, q_cic_scaled; + wire [17:0] i_hb1, q_hb1; + wire [17:0] i_hb2, q_hb2; + wire [15:0] i_out, q_out; + + wire strobe_cic, strobe_hb1, strobe_hb2; + wire enable_hb1, enable_hb2; + wire [7:0] cic_decim_rate; + + wire [31:10] UNUSED_1; + wire [31:4] UNUSED_2; + wire [31:2] UNUSED_3; + + setting_reg #(.my_addr(BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed()); + + rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_a),.adc_out(adc_a_ofs)); + + rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_b),.adc_out(adc_b_ofs)); + + wire [3:0] muxctrl; + setting_reg #(.my_addr(BASE+5)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({UNUSED_2,muxctrl}),.changed()); + + wire [1:0] gpio_ena; + setting_reg #(.my_addr(BASE+6)) sr_9 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({UNUSED_3,gpio_ena}),.changed()); + + // The TVRX connects to what is called adc_b, thus A and B are + // swapped throughout the design. + // + // In the interest of expediency and keeping the s/w sane, we just remap them here. + // The I & Q fields are mapped the same: + // 0 -> "the real A" (as determined by the TVRX) + // 1 -> "the real B" + // 2 -> const zero + + always @(posedge clk) + case(muxctrl[1:0]) // The I mapping + 0: adc_i <= adc_b_ofs; // "the real A" + 1: adc_i <= adc_a_ofs; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case(muxctrl[1:0]) + + always @(posedge clk) + case(muxctrl[3:2]) // The Q mapping + 0: adc_q <= adc_b_ofs; // "the real A" + 1: adc_q <= adc_a_ofs; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case(muxctrl[3:2]) + + always @(posedge clk) + if(rst) + phase <= 0; + else if(~run) + phase <= 0; + else + phase <= phase + phase_inc; + + MULT18X18S mult_i + (.P(prod_i), // 36-bit multiplier output + .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + MULT18X18S mult_q + (.P(prod_q), // 36-bit multiplier output + .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + + cordic_z24 #(.bitwidth(24)) + cordic(.clock(clk), .reset(rst), .enable(run), + .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]), + .xo(i_cordic),.yo(q_cordic),.zo() ); + + cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate), + .strobe_fast(1),.strobe_slow(strobe_cic) ); + + cic_decim #(.bw(24)) + decim_i (.clock(clk),.reset(rst),.enable(run), + .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), + .signal_in(i_cordic),.signal_out(i_cic)); + + cic_decim #(.bw(24)) + decim_q (.clock(clk),.reset(rst),.enable(run), + .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), + .signal_in(q_cordic),.signal_out(q_cic)); + + round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled)); + round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled)); + reg strobe_cic_d1; + always @(posedge clk) strobe_cic_d1 <= strobe_cic; + + small_hb_dec #(.WIDTH(18)) small_hb_i + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), + .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1)); + + small_hb_dec #(.WIDTH(18)) small_hb_q + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), + .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1)); + + wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate}; + hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), + .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2)); + + hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), + .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); + + round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); + round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); + + // Streaming GPIO + // + // io_rx[15] => I channel LSB if gpio_ena[0] high + // io_rx[14] => Q channel LSB if gpio_ena[1] high + + reg [31:0] sample_reg; + always @(posedge clk) + begin + sample_reg[31:17] <= i_out[15:1]; + sample_reg[15:1] <= q_out[15:1]; + sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; + sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; + end + + assign sample = sample_reg; + assign strobe = strobe_hb2; + assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; + +endmodule // dsp_core_rx diff --git a/usrp2/top/u2_core/u2_core_udp.v b/usrp2/top/u2_core/u2_core_udp.v new file mode 100644 index 000000000..428a40ad2 --- /dev/null +++ b/usrp2/top/u2_core/u2_core_udp.v @@ -0,0 +1,871 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + #(parameter RAM_SIZE=32768) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_UDP_SM = 96; // 64 regs + localparam SR_RX_DSP = 160; // 16 + localparam SR_RX_CTRL = 176; // 16 + localparam SR_TIME64 = 192; // 3 + localparam SR_SIMTIMER = 198; // 2 + localparam SR_TX_DSP = 208; // 16 + localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), + // Read Interfaces + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + ); + + wire [31:0] status_enc; + priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + wire [35:0] udp_tx_data, udp_rx_data; + wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; + + udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), + .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), + .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), + .debug(debug_udp) ); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {clk_status,serdes_link_up}; + + setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {8'b0}, + {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + /* + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + */ + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + sd_spi_wb sd_spi_wb + (.clk(wb_clk),.rst(wb_rst), + .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), + .wb_ack_o(sd_ack) ); + + assign sd_dat_i[31:8] = 0; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + wire [31:0] vrc_debug; + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); + + wire [3:0] vita_state; + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), + .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire [99:0] tx1_data; + wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; + + wire [31:0] debug_vtc, debug_vtd, debug_vt; + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + assign debug_vt = debug_vtc | debug_vtd; + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(dac_a),.dac_b(dac_b), + .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // External RAM Interface + + localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes + + wire [15:0] bus2ram, ram2bus; + wire [15:0] bridge_adr; + wire [1:0] bridge_sel; + wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; + + wire [19:0] page; + wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; + setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(page),.changed()); + + wb_bridge_16_32 bridge + (.wb_clk(wb_clk),.wb_rst(wb_rst), + .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), + .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), + .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), + .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); + + wb_zbt16_b wb_zbt16_b + (.clk(wb_clk),.rst(wb_rst), + .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), + .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), + .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), + .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), + .sram_mode(),.sram_zz() ); + + assign RAM_CE1n = 0; + assign RAM_D[17:16] = 2'bzz; + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // FIFO Level Debugging + reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; + + always @(posedge dsp_clk) + serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, + {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; + + assign debug_clk[0] = GMII_RX_CLK; // wb_clk; + assign debug_clk[1] = dsp_clk; + +/* + + wire mdio_cpy = MDIO; + assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, + { s6_adr[15:8] }, + { s6_adr[7:0] }, + { 6'd0, mdio_cpy, MDC } }; +*/ +/* + assign debug = { { GMII_TXD }, + { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, + { wr2_flags, rd2_flags }, + { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + assign debug = { { GMII_RXD }, + { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { wr2_flags, rd2_flags }, + { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + */ + +// assign debug = debug_udp; + assign debug = vrc_debug; + assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, + {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, + {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , + {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; + + assign debug_gpio_1 = {vita_time[63:32] }; + +/* + assign debug_gpio_1 = { { tx_f19_data[15:8] }, + { tx_f19_data[7:0] }, + { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, + { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; + */ + +endmodule // u2_core + +// wire debug_mux; +// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), +// .in(set_data),.out(debug_mux),.changed()); + +//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; +//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; + +//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, +// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; + +//assign debug = debug_tx_dsp; +//assign debug = debug_serdes0; + +//assign debug_gpio_0 = 0; //debug_serdes0; +//assign debug_gpio_1 = 0; //debug_serdes1; + +// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, +// {8'b0}, +// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, +// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; + +//assign debug = {dac_a,dac_b}; + +/* + assign debug = {{ram_loader_done, takeover, 6'd0}, + {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, + {8'd0}, + {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ + +/*assign debug = host_to_dsp_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; + */ +// Assign various commonly used debug buses. +/* + wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, + irq[7:0], + GMII_RXD, + GMII_TXD}; + + wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; + + wire [31:0] debug_time = {uart_tx_o, 7'b0, + irq[7:0], + 6'b0, GMII_RX_DV, GMII_TX_EN, + 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; + + wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, + irq[7:0], + proc_int, 7'b0 }; + + wire [31:0] debug_eth = + {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, + {8'd0}, + {8'd0}, + {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; + + assign debug_serdes0 = { { rd0_dat[7:0] }, + { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, + { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, + { ser_r[15:8] }, + { ser_r[7:0] } }; + + assign debug_gpio_1 = {uart_tx_o,7'd0, + 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, + debug_txc[15:0]}; + assign debug_gpio_1 = debug_rx; + assign debug_gpio_1 = debug_serdes1; + assign debug_gpio_1 = debug_eth; + + */ + diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp new file mode 100644 index 000000000..e445fe3b2 --- /dev/null +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -0,0 +1,267 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build-udp/ +export TOP_MODULE := u2_rev3 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/settings_bus_crossclock.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +control_lib/priority_enc.v \ +control_lib/pic.v \ +vrt/vita_rx_control.v \ +vrt/vita_rx_framer.v \ +vrt/vita_tx_control.v \ +vrt/vita_tx_deframer.v \ +udp/udp_wrapper.v \ +udp/fifo19_rxrealign.v \ +udp/prot_eng_tx.v \ +udp/add_onescomp.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac_wrapper19.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo19_to_ll8.v \ +control_lib/newfifo/ll8_to_fifo19.v \ +control_lib/newfifo/fifo36_to_fifo19.v \ +control_lib/newfifo/fifo19_to_fifo36.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +coregen/fifo_xlnx_16x19_2clk.v \ +coregen/fifo_xlnx_16x19_2clk.xco \ +coregen/fifo_xlnx_16x40_2clk.v \ +coregen/fifo_xlnx_16x40_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx_udp.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_64bit.v \ +timing/time_compare.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +timing/simple_timer.v \ +top/u2_core/u2_core_udp.v \ +top/u2_rev3/u2_rev3.ucf \ +top/u2_rev3/u2_rev3.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + -- cgit v1.2.3 From 1ee094eeef57295e5e2e5727c4a01a31aaf30cb3 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 27 May 2010 18:26:17 -0700 Subject: manual merge to use localparams from udp version --- usrp2/top/u2_core/u2_core.v | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index df74c7dba..937b5343c 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -135,6 +135,24 @@ module u2_core input sim_mode, input [3:0] clock_divider ); + + localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_UDP_SM = 96; // 64 regs + localparam SR_RX_DSP = 160; // 16 + localparam SR_RX_CTRL = 176; // 16 + localparam SR_TIME64 = 192; // 3 + localparam SR_SIMTIMER = 198; // 2 + localparam SR_TX_DSP = 208; // 16 + localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? wire [7:0] set_addr, set_addr_dsp; wire [31:0] set_data, set_data_dsp; @@ -333,7 +351,7 @@ module u2_core wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), @@ -581,18 +599,19 @@ module u2_core .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), .debug(debug_txc) ); - dsp_core_tx dsp_core_tx + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .dac_a(dac_a),.dac_b(dac_b), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); + .debug(debug_tx_dsp) ); assign dsp_rst = wb_rst; // /////////////////////////////////////////////////////////////////////////////////// // SERDES - serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes (.clk(dsp_clk),.rst(dsp_rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), -- cgit v1.2.3 From d488c6b2cc40221d395f053891c1c89c1305fae5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 27 May 2010 21:02:53 -0700 Subject: non-udp uses a different address for the tx dsp core --- usrp2/top/u2_core/u2_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 937b5343c..c2e1bab63 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -142,7 +142,7 @@ module u2_core localparam SR_RX_CTRL = 176; // 16 localparam SR_TIME64 = 192; // 3 localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 208; // 16 + localparam SR_TX_DSP = 128; // 16 localparam SR_TX_CTRL = 224; // 16 // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 -- cgit v1.2.3 From 893a1350cf5b930f019f10f71f2e1acbc1354927 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 7 Jun 2010 15:26:25 -0700 Subject: name build directory with ISE version name --- usrp2/top/u2_rev3/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 7eedf5e7f..bc3933415 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -29,7 +29,7 @@ ISE_HELPER := ../tcl/ise_helper.tcl ################################################## # Project Setup ################################################## -BUILD_DIR := build/ +BUILD_DIR := build-ISE$(XIL)/ export TOP_MODULE := u2_rev3 export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise -- cgit v1.2.3 From 31d5fac152ad342b40b8d9f2676cfdf749cfd20e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 7 Jun 2010 15:32:04 -0700 Subject: proper name for directory --- usrp2/top/u2_rev3/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index bc3933415..5eb9d9420 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -29,7 +29,7 @@ ISE_HELPER := ../tcl/ise_helper.tcl ################################################## # Project Setup ################################################## -BUILD_DIR := build-ISE$(XIL)/ +BUILD_DIR := build$(ISE)/ export TOP_MODULE := u2_rev3 export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise -- cgit v1.2.3 From 6713a56cb6a927140505cb5c8464b23362348c9c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 7 Jun 2010 15:37:25 -0700 Subject: report ise version in build --- usrp2/top/u2_rev3/Makefile.udp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp index e445fe3b2..3be4203a8 100644 --- a/usrp2/top/u2_rev3/Makefile.udp +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -29,7 +29,7 @@ ISE_HELPER := ../tcl/ise_helper.tcl ################################################## # Project Setup ################################################## -BUILD_DIR := build-udp/ +BUILD_DIR := build-udp$(ISE)/ export TOP_MODULE := u2_rev3 export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise -- cgit v1.2.3 From 9560e541c641e42222d8856add3ff3409b243f17 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 8 Jun 2010 10:34:17 -0700 Subject: allow other clock rates in vita time --- usrp2/timing/time_64bit.v | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index 8ccde3f54..51c006962 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -13,21 +13,17 @@ module time_64bit localparam NEXT_TICKS = 1; localparam PPS_POLSRC = 2; localparam PPS_IMM = 3; + localparam TPS = 4; - localparam ROLLOVER = TICKS_PER_SEC - 1; - - reg [31:0] seconds; - reg [31:0] ticks; + reg [31:0] seconds, ticks; wire end_of_second; assign vita_time = {seconds,ticks}; - wire [31:0] next_ticks_preset; - wire [31:0] next_seconds_preset; + wire [31:0] next_ticks_preset, next_seconds_preset; + wire [31:0] ticks_per_sec_reg; wire set_on_pps_trig; reg set_on_next_pps; - wire pps_polarity; - wire set_imm; - wire pps_source; + wire pps_polarity, pps_source, set_imm; setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -37,14 +33,18 @@ module time_64bit (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig)); - setting_reg #(.my_addr(BASE+PPS_POLSRC)) sr_pps_polsrc + setting_reg #(.my_addr(BASE+PPS_POLSRC), .width(2)) sr_pps_polsrc (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({pps_source,pps_polarity}),.changed()); - setting_reg #(.my_addr(BASE+PPS_IMM)) sr_pps_imm + setting_reg #(.my_addr(BASE+PPS_IMM), .width(1)) sr_pps_imm (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(set_imm),.changed()); + setting_reg #(.my_addr(BASE+TPS), .at_reset(TICKS_PER_SEC)) sr_tps + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(ticks_per_sec_reg),.changed()); + reg [1:0] pps_del; reg pps_reg_p, pps_reg_n, pps_reg; wire pps_edge; @@ -68,6 +68,8 @@ module time_64bit set_on_next_pps <= 1; else if(set_imm | pps_edge) set_on_next_pps <= 0; + + wire [31:0] ticks_plus_one = ticks + 1; always @(posedge clk) if(rst) @@ -80,13 +82,13 @@ module time_64bit seconds <= next_seconds_preset; ticks <= next_ticks_preset; end - else if(ticks == ROLLOVER) + else if(ticks_plus_one == ticks_per_sec_reg) begin seconds <= seconds + 1; ticks <= 0; end else - ticks <= ticks + 1; + ticks <= ticks_plus_one; assign pps_int = pps_edge; -- cgit v1.2.3 From b06bf11eed367ce0cfd4250954ea8b9a6c3b2d06 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 8 Jun 2010 15:15:20 -0700 Subject: move u2_core into u2_rev3 directory to simplify directory structure and save headaches --- usrp2/top/u2_core/.gitignore | 44 -- usrp2/top/u2_core/u2_core.v | 784 ------------------------------------ usrp2/top/u2_core/u2_core_udp.v | 871 ---------------------------------------- usrp2/top/u2_rev3/Makefile | 2 +- usrp2/top/u2_rev3/Makefile.udp | 2 +- usrp2/top/u2_rev3/u2_core.v | 784 ++++++++++++++++++++++++++++++++++++ usrp2/top/u2_rev3/u2_core_udp.v | 871 ++++++++++++++++++++++++++++++++++++++++ 7 files changed, 1657 insertions(+), 1701 deletions(-) delete mode 100644 usrp2/top/u2_core/.gitignore delete mode 100755 usrp2/top/u2_core/u2_core.v delete mode 100644 usrp2/top/u2_core/u2_core_udp.v create mode 100755 usrp2/top/u2_rev3/u2_core.v create mode 100644 usrp2/top/u2_rev3/u2_core_udp.v diff --git a/usrp2/top/u2_core/.gitignore b/usrp2/top/u2_core/.gitignore deleted file mode 100644 index 9728395c1..000000000 --- a/usrp2/top/u2_core/.gitignore +++ /dev/null @@ -1,44 +0,0 @@ -*~ -/xst -/_ngo -/_xmsgs -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*_log -/*.lfp -/*.bit -/*.bin -/*.vcd -/*.unroutes -/*.drc -/*_map.* -/*_guide.* -/*.twr -/*.twx -/a.out -/*.xpi -/*_pad.txt -/*.bgn -/*.par diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v deleted file mode 100755 index c2e1bab63..000000000 --- a/usrp2/top/u2_core/u2_core.v +++ /dev/null @@ -1,784 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=32768) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - localparam SR_BUF_POOL = 64; // Uses 1 reg - localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP = 160; // 16 - localparam SR_RX_CTRL = 176; // 16 - localparam SR_TIME64 = 192; // 3 - localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 128; // 16 - localparam SR_TX_CTRL = 224; // 16 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - localparam DSP_TX_FIFOSIZE = 10; - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 10; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; - - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) - ); - - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - settings_bus_crossclock settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; - - setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - assign irq= {{8'b0}, - {8'b0}, - {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps_in; - always @(posedge dsp_clk) pps_posedge <= pps_in; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), - .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), - .wb_ack_o(sd_ack) ); - - assign sd_dat_i[31:8] = 0; - - // ///////////////////////////////////////////////////////////////////////// - // DSP - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); - - // dummy_rx dsp_core_rx - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), - .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = 0; // wb_clk; - assign debug_clk[1] = clk_to_mac; -/* - - wire mdio_cpy = MDIO; - assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, - { s6_adr[15:8] }, - { s6_adr[7:0] }, - { 6'd0, mdio_cpy, MDC } }; -*/ -/* - assign debug = { { GMII_TXD }, - { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, - { wr2_flags, rd2_flags }, - { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - */ - assign debug = { { GMII_RXD }, - { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, - { wr2_flags, rd2_flags }, - { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - - assign debug_gpio_0 = debug_mac; //eth_mac_debug; - assign debug_gpio_1 = 0; - -endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/usrp2/top/u2_core/u2_core_udp.v b/usrp2/top/u2_core/u2_core_udp.v deleted file mode 100644 index 428a40ad2..000000000 --- a/usrp2/top/u2_core/u2_core_udp.v +++ /dev/null @@ -1,871 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=32768) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - localparam SR_BUF_POOL = 64; // Uses 1 reg - localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP = 160; // 16 - localparam SR_RX_CTRL = 176; // 16 - localparam SR_TIME64 = 192; // 3 - localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 208; // 16 - localparam SR_TX_CTRL = 224; // 16 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - localparam DSP_TX_FIFOSIZE = 10; - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 10; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - wire [63:0] vita_time; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; - - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) - ); - - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; - - simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - wire [35:0] udp_tx_data, udp_rx_data; - wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; - - udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), - .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), - .debug(debug_udp) ); - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), - .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - settings_bus_crossclock settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; - - setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - assign irq= {{8'b0}, - {8'b0}, - {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - // No longer used, replaced with simple_timer below - /* - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - */ - assign s9_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Simple Timer interrupts - - simple_timer #(.BASE(SR_SIMTIMER)) simple_timer - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .onetime_int(onetime_int), .periodic_int(periodic_int)); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - // No longer used, see time_64bit. Still need to handle mimo time, though - assign sc_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), - .wb_ack_o(sd_ack) ); - - assign sd_dat_i[31:8] = 0; - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx_data; - wire [35:0] rx1_data; - - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - wire [31:0] vrc_debug; - - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), - .debug_rx(vrc_debug)); - - wire [3:0] vita_state; - - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), - .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty(), - .debug_rx(vita_state) ); - - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), - .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [35:0] tx_data; - wire [99:0] tx1_data; - wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; - - wire [31:0] debug_vtc, debug_vtd, debug_vt; - - fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time),.underrun(underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); - - assign debug_vt = debug_vtc | debug_vtd; - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), - .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = GMII_RX_CLK; // wb_clk; - assign debug_clk[1] = dsp_clk; - -/* - - wire mdio_cpy = MDIO; - assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, - { s6_adr[15:8] }, - { s6_adr[7:0] }, - { 6'd0, mdio_cpy, MDC } }; -*/ -/* - assign debug = { { GMII_TXD }, - { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, - { wr2_flags, rd2_flags }, - { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - assign debug = { { GMII_RXD }, - { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, - { wr2_flags, rd2_flags }, - { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - */ - -// assign debug = debug_udp; - assign debug = vrc_debug; - assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, - {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, - {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , - {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; - - assign debug_gpio_1 = {vita_time[63:32] }; - -/* - assign debug_gpio_1 = { { tx_f19_data[15:8] }, - { tx_f19_data[7:0] }, - { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, - { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; - */ - -endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 5eb9d9420..3a8edc9ac 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -196,7 +196,7 @@ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ timing/simple_timer.v \ -top/u2_core/u2_core.v \ +top/u2_rev3/u2_core.v \ top/u2_rev3/u2_rev3.ucf \ top/u2_rev3/u2_rev3.v diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp index 3be4203a8..f6e6e5b15 100644 --- a/usrp2/top/u2_rev3/Makefile.udp +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -196,7 +196,7 @@ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ timing/simple_timer.v \ -top/u2_core/u2_core_udp.v \ +top/u2_rev3/u2_core_udp.v \ top/u2_rev3/u2_rev3.ucf \ top/u2_rev3/u2_rev3.v diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v new file mode 100755 index 000000000..c2e1bab63 --- /dev/null +++ b/usrp2/top/u2_rev3/u2_core.v @@ -0,0 +1,784 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + #(parameter RAM_SIZE=32768) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_UDP_SM = 96; // 64 regs + localparam SR_RX_DSP = 160; // 16 + localparam SR_RX_CTRL = 176; // 16 + localparam SR_TIME64 = 192; // 3 + localparam SR_SIMTIMER = 198; // 2 + localparam SR_TX_DSP = 128; // 16 + localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), + // Read Interfaces + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + ); + + wire [31:0] status_enc; + priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), + .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {clk_status,serdes_link_up}; + + setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {8'b0}, + {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; + always @(negedge dsp_clk) pps_negedge <= pps_in; + always @(posedge dsp_clk) pps_posedge <= pps_in; + always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; + always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; + + wire pps_o; + time_sync time_sync + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), + .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), + .sys_clk_i(dsp_clk),.master_time_o(master_time), + .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), + .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), + .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + sd_spi_wb sd_spi_wb + (.clk(wb_clk),.rst(wb_rst), + .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), + .wb_ack_o(sd_ack) ); + + assign sd_dat_i[31:8] = 0; + + // ///////////////////////////////////////////////////////////////////////// + // DSP + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + + rx_control #(.FIFOSIZE(10)) rx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .master_time(master_time),.overrun(overrun), + .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), + .debug_rx(debug_rx) ); + + // dummy_rx dsp_core_rx + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + tx_control #(.FIFOSIZE(10)) tx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .master_time(master_time),.underrun(underrun), + .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), + .debug(debug_txc) ); + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(dac_a),.dac_b(dac_b), + .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // External RAM Interface + + localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes + + wire [15:0] bus2ram, ram2bus; + wire [15:0] bridge_adr; + wire [1:0] bridge_sel; + wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; + + wire [19:0] page; + wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; + setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(page),.changed()); + + wb_bridge_16_32 bridge + (.wb_clk(wb_clk),.wb_rst(wb_rst), + .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), + .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), + .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), + .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); + + wb_zbt16_b wb_zbt16_b + (.clk(wb_clk),.rst(wb_rst), + .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), + .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), + .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), + .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), + .sram_mode(),.sram_zz() ); + + assign RAM_CE1n = 0; + assign RAM_D[17:16] = 2'bzz; + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // FIFO Level Debugging + reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; + + always @(posedge dsp_clk) + serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, + {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; + + assign debug_clk[0] = 0; // wb_clk; + assign debug_clk[1] = clk_to_mac; +/* + + wire mdio_cpy = MDIO; + assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, + { s6_adr[15:8] }, + { s6_adr[7:0] }, + { 6'd0, mdio_cpy, MDC } }; +*/ +/* + assign debug = { { GMII_TXD }, + { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, + { wr2_flags, rd2_flags }, + { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + */ + assign debug = { { GMII_RXD }, + { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { wr2_flags, rd2_flags }, + { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + + assign debug_gpio_0 = debug_mac; //eth_mac_debug; + assign debug_gpio_1 = 0; + +endmodule // u2_core + +// wire debug_mux; +// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), +// .in(set_data),.out(debug_mux),.changed()); + +//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; +//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; + +//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, +// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; + +//assign debug = debug_tx_dsp; +//assign debug = debug_serdes0; + +//assign debug_gpio_0 = 0; //debug_serdes0; +//assign debug_gpio_1 = 0; //debug_serdes1; + +// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, +// {8'b0}, +// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, +// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; + +//assign debug = {dac_a,dac_b}; + +/* + assign debug = {{ram_loader_done, takeover, 6'd0}, + {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, + {8'd0}, + {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ + +/*assign debug = host_to_dsp_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; + */ +// Assign various commonly used debug buses. +/* + wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, + irq[7:0], + GMII_RXD, + GMII_TXD}; + + wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; + + wire [31:0] debug_time = {uart_tx_o, 7'b0, + irq[7:0], + 6'b0, GMII_RX_DV, GMII_TX_EN, + 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; + + wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, + irq[7:0], + proc_int, 7'b0 }; + + wire [31:0] debug_eth = + {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, + {8'd0}, + {8'd0}, + {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; + + assign debug_serdes0 = { { rd0_dat[7:0] }, + { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, + { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, + { ser_r[15:8] }, + { ser_r[7:0] } }; + + assign debug_gpio_1 = {uart_tx_o,7'd0, + 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, + debug_txc[15:0]}; + assign debug_gpio_1 = debug_rx; + assign debug_gpio_1 = debug_serdes1; + assign debug_gpio_1 = debug_eth; + + */ + diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v new file mode 100644 index 000000000..428a40ad2 --- /dev/null +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -0,0 +1,871 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + #(parameter RAM_SIZE=32768) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_UDP_SM = 96; // 64 regs + localparam SR_RX_DSP = 160; // 16 + localparam SR_RX_CTRL = 176; // 16 + localparam SR_TIME64 = 192; // 3 + localparam SR_SIMTIMER = 198; // 2 + localparam SR_TX_DSP = 208; // 16 + localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), + // Read Interfaces + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + ); + + wire [31:0] status_enc; + priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + wire [35:0] udp_tx_data, udp_rx_data; + wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; + + udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), + .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), + .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), + .debug(debug_udp) ); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {clk_status,serdes_link_up}; + + setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {8'b0}, + {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + /* + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + */ + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + sd_spi_wb sd_spi_wb + (.clk(wb_clk),.rst(wb_rst), + .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), + .wb_ack_o(sd_ack) ); + + assign sd_dat_i[31:8] = 0; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + wire [31:0] vrc_debug; + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); + + wire [3:0] vita_state; + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), + .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire [99:0] tx1_data; + wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; + + wire [31:0] debug_vtc, debug_vtd, debug_vt; + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + assign debug_vt = debug_vtc | debug_vtd; + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(dac_a),.dac_b(dac_b), + .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // External RAM Interface + + localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes + + wire [15:0] bus2ram, ram2bus; + wire [15:0] bridge_adr; + wire [1:0] bridge_sel; + wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; + + wire [19:0] page; + wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; + setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(page),.changed()); + + wb_bridge_16_32 bridge + (.wb_clk(wb_clk),.wb_rst(wb_rst), + .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), + .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), + .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), + .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); + + wb_zbt16_b wb_zbt16_b + (.clk(wb_clk),.rst(wb_rst), + .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), + .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), + .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), + .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), + .sram_mode(),.sram_zz() ); + + assign RAM_CE1n = 0; + assign RAM_D[17:16] = 2'bzz; + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // FIFO Level Debugging + reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; + + always @(posedge dsp_clk) + serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, + {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; + + assign debug_clk[0] = GMII_RX_CLK; // wb_clk; + assign debug_clk[1] = dsp_clk; + +/* + + wire mdio_cpy = MDIO; + assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, + { s6_adr[15:8] }, + { s6_adr[7:0] }, + { 6'd0, mdio_cpy, MDC } }; +*/ +/* + assign debug = { { GMII_TXD }, + { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, + { wr2_flags, rd2_flags }, + { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + assign debug = { { GMII_RXD }, + { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { wr2_flags, rd2_flags }, + { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + */ + +// assign debug = debug_udp; + assign debug = vrc_debug; + assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, + {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, + {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , + {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; + + assign debug_gpio_1 = {vita_time[63:32] }; + +/* + assign debug_gpio_1 = { { tx_f19_data[15:8] }, + { tx_f19_data[7:0] }, + { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, + { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; + */ + +endmodule // u2_core + +// wire debug_mux; +// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), +// .in(set_data),.out(debug_mux),.changed()); + +//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; +//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; + +//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, +// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; + +//assign debug = debug_tx_dsp; +//assign debug = debug_serdes0; + +//assign debug_gpio_0 = 0; //debug_serdes0; +//assign debug_gpio_1 = 0; //debug_serdes1; + +// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, +// {8'b0}, +// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, +// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; + +//assign debug = {dac_a,dac_b}; + +/* + assign debug = {{ram_loader_done, takeover, 6'd0}, + {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, + {8'd0}, + {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ + +/*assign debug = host_to_dsp_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; + */ +// Assign various commonly used debug buses. +/* + wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, + irq[7:0], + GMII_RXD, + GMII_TXD}; + + wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; + + wire [31:0] debug_time = {uart_tx_o, 7'b0, + irq[7:0], + 6'b0, GMII_RX_DV, GMII_TX_EN, + 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; + + wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, + irq[7:0], + proc_int, 7'b0 }; + + wire [31:0] debug_eth = + {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, + {8'd0}, + {8'd0}, + {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; + + assign debug_serdes0 = { { rd0_dat[7:0] }, + { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, + { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, + { ser_r[15:8] }, + { ser_r[7:0] } }; + + assign debug_gpio_1 = {uart_tx_o,7'd0, + 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, + debug_txc[15:0]}; + assign debug_gpio_1 = debug_rx; + assign debug_gpio_1 = debug_serdes1; + assign debug_gpio_1 = debug_eth; + + */ + -- cgit v1.2.3 From 8dbe0a6f5c4cb4d3d888d94287e788153762d14b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 8 Jun 2010 15:56:31 -0700 Subject: get rid of debug stuff to help timing --- usrp2/top/u2_rev3/u2_core_udp.v | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 428a40ad2..cb0ed78c7 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -690,6 +690,7 @@ module u2_core // /////////////////////////////////////////////////////////////////////////////////// // External RAM Interface + /* localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes wire [15:0] bus2ram, ram2bus; @@ -719,6 +720,7 @@ module u2_core assign RAM_CE1n = 0; assign RAM_D[17:16] = 2'bzz; + */ // ///////////////////////////////////////////////////////////////////////// // VITA Timing @@ -729,7 +731,15 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins + + assign debug_clk = 2'b00; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; +endmodule // u2_core + +/* // FIFO Level Debugging reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; @@ -755,7 +765,7 @@ module u2_core assign debug_clk[0] = GMII_RX_CLK; // wb_clk; assign debug_clk[1] = dsp_clk; - +*/ /* wire mdio_cpy = MDIO; @@ -776,13 +786,14 @@ module u2_core */ // assign debug = debug_udp; - assign debug = vrc_debug; - assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, + // assign debug = vrc_debug; +/* + assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; - - assign debug_gpio_1 = {vita_time[63:32] }; +*/ +// assign debug_gpio_1 = {vita_time[63:32] }; /* assign debug_gpio_1 = { { tx_f19_data[15:8] }, @@ -791,8 +802,6 @@ module u2_core { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; */ -endmodule // u2_core - // wire debug_mux; // setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), // .in(set_data),.out(debug_mux),.changed()); -- cgit v1.2.3 From 45e5589ed9c555c604fb66be9f314c02ff5fb9e4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 11:34:18 -0700 Subject: first attempt at cleaning up the build system --- usrp2/control_lib/Makefile.srcs | 44 + usrp2/control_lib/newfifo/.gitignore | 1 - usrp2/control_lib/newfifo/buffer_int.v | 168 - usrp2/control_lib/newfifo/buffer_int_tb.v | 418 -- usrp2/control_lib/newfifo/buffer_pool.v | 283 -- usrp2/control_lib/newfifo/buffer_pool_tb.v | 58 - usrp2/control_lib/newfifo/fifo19_to_fifo36.v | 76 - usrp2/control_lib/newfifo/fifo19_to_ll8.v | 53 - usrp2/control_lib/newfifo/fifo36_to_fifo18.v | 40 - usrp2/control_lib/newfifo/fifo36_to_fifo19.v | 41 - usrp2/control_lib/newfifo/fifo36_to_ll8.v | 60 - usrp2/control_lib/newfifo/fifo_2clock.v | 117 - usrp2/control_lib/newfifo/fifo_2clock_cascade.v | 35 - usrp2/control_lib/newfifo/fifo_cascade.v | 52 - usrp2/control_lib/newfifo/fifo_long.v | 148 - usrp2/control_lib/newfifo/fifo_new_tb.vcd | 5506 ----------------------- usrp2/control_lib/newfifo/fifo_short.v | 95 - usrp2/control_lib/newfifo/fifo_spec.txt | 36 - usrp2/control_lib/newfifo/fifo_tb.v | 158 - usrp2/control_lib/newfifo/ll8_shortfifo.v | 13 - usrp2/control_lib/newfifo/ll8_to_fifo19.v | 73 - usrp2/control_lib/newfifo/ll8_to_fifo36.v | 97 - usrp2/coregen/Makefile.srcs | 19 + usrp2/extram/Makefile.srcs | 10 + usrp2/fifo/.gitignore | 1 + usrp2/fifo/Makefile.srcs | 23 + usrp2/fifo/buffer_int.v | 168 + usrp2/fifo/buffer_int_tb.v | 418 ++ usrp2/fifo/buffer_pool.v | 283 ++ usrp2/fifo/buffer_pool_tb.v | 58 + usrp2/fifo/fifo19_to_fifo36.v | 76 + usrp2/fifo/fifo19_to_ll8.v | 53 + usrp2/fifo/fifo36_to_fifo18.v | 40 + usrp2/fifo/fifo36_to_fifo19.v | 41 + usrp2/fifo/fifo36_to_ll8.v | 60 + usrp2/fifo/fifo_2clock.v | 117 + usrp2/fifo/fifo_2clock_cascade.v | 35 + usrp2/fifo/fifo_cascade.v | 52 + usrp2/fifo/fifo_long.v | 148 + usrp2/fifo/fifo_new_tb.vcd | 5506 +++++++++++++++++++++++ usrp2/fifo/fifo_short.v | 95 + usrp2/fifo/fifo_spec.txt | 36 + usrp2/fifo/fifo_tb.v | 158 + usrp2/fifo/ll8_shortfifo.v | 13 + usrp2/fifo/ll8_to_fifo19.v | 73 + usrp2/fifo/ll8_to_fifo36.v | 97 + usrp2/opencores/Makefile.srcs | 28 + usrp2/sdr_lib/Makefile.srcs | 37 + usrp2/sdr_lib/dsp_core_rx.v | 16 +- usrp2/sdr_lib/dsp_core_rx_old.v | 183 + usrp2/serdes/Makefile.srcs | 14 + usrp2/simple_gemac/Makefile.srcs | 26 + usrp2/timing/Makefile.srcs | 16 + usrp2/top/Makefile.common | 84 + usrp2/top/u2_rev3/Makefile | 238 +- usrp2/top/u2_rev3/Makefile.udp | 238 +- usrp2/top/u2_rev3/u2_core.v | 3 +- usrp2/udp/Makefile.srcs | 13 + usrp2/vrt/Makefile.srcs | 13 + 59 files changed, 8111 insertions(+), 7950 deletions(-) create mode 100644 usrp2/control_lib/Makefile.srcs delete mode 100644 usrp2/control_lib/newfifo/.gitignore delete mode 100644 usrp2/control_lib/newfifo/buffer_int.v delete mode 100644 usrp2/control_lib/newfifo/buffer_int_tb.v delete mode 100644 usrp2/control_lib/newfifo/buffer_pool.v delete mode 100644 usrp2/control_lib/newfifo/buffer_pool_tb.v delete mode 100644 usrp2/control_lib/newfifo/fifo19_to_fifo36.v delete mode 100644 usrp2/control_lib/newfifo/fifo19_to_ll8.v delete mode 100644 usrp2/control_lib/newfifo/fifo36_to_fifo18.v delete mode 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mode 100644 usrp2/fifo/buffer_int_tb.v create mode 100644 usrp2/fifo/buffer_pool.v create mode 100644 usrp2/fifo/buffer_pool_tb.v create mode 100644 usrp2/fifo/fifo19_to_fifo36.v create mode 100644 usrp2/fifo/fifo19_to_ll8.v create mode 100644 usrp2/fifo/fifo36_to_fifo18.v create mode 100644 usrp2/fifo/fifo36_to_fifo19.v create mode 100644 usrp2/fifo/fifo36_to_ll8.v create mode 100644 usrp2/fifo/fifo_2clock.v create mode 100644 usrp2/fifo/fifo_2clock_cascade.v create mode 100644 usrp2/fifo/fifo_cascade.v create mode 100644 usrp2/fifo/fifo_long.v create mode 100644 usrp2/fifo/fifo_new_tb.vcd create mode 100644 usrp2/fifo/fifo_short.v create mode 100644 usrp2/fifo/fifo_spec.txt create mode 100644 usrp2/fifo/fifo_tb.v create mode 100644 usrp2/fifo/ll8_shortfifo.v create mode 100644 usrp2/fifo/ll8_to_fifo19.v create mode 100644 usrp2/fifo/ll8_to_fifo36.v create mode 100644 usrp2/opencores/Makefile.srcs create mode 100644 usrp2/sdr_lib/Makefile.srcs create mode 100644 usrp2/sdr_lib/dsp_core_rx_old.v create mode 100644 usrp2/serdes/Makefile.srcs create mode 100644 usrp2/simple_gemac/Makefile.srcs create mode 100644 usrp2/timing/Makefile.srcs create mode 100644 usrp2/top/Makefile.common mode change 100755 => 100644 usrp2/top/u2_rev3/u2_core.v create mode 100644 usrp2/udp/Makefile.srcs create mode 100644 usrp2/vrt/Makefile.srcs diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs new file mode 100644 index 000000000..5e2a96a53 --- /dev/null +++ b/usrp2/control_lib/Makefile.srcs @@ -0,0 +1,44 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Control Lib Sources +################################################## +CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../control_lib/, \ +CRC16_D16.v \ +atr_controller.v \ +bin2gray.v \ +dcache.v \ +decoder_3_8.v \ +dpram32.v \ +gray2bin.v \ +gray_send.v \ +icache.v \ +mux4.v \ +mux8.v \ +nsgpio.v \ +ram_2port.v \ +ram_harv_cache.v \ +ram_loader.v \ +setting_reg.v \ +settings_bus.v \ +settings_bus_crossclock.v \ +srl.v \ +system_control.v \ +wb_1master.v \ +wb_readback_mux.v \ +simple_uart.v \ +simple_uart_tx.v \ +simple_uart_rx.v \ +oneshot_2clk.v \ +sd_spi.v \ +sd_spi_wb.v \ +wb_bridge_16_32.v \ +reset_sync.v \ +priority_enc.v \ +pic.v \ +longfifo.v \ +shortfifo.v \ +medfifo.v \ +)) diff --git a/usrp2/control_lib/newfifo/.gitignore b/usrp2/control_lib/newfifo/.gitignore deleted file mode 100644 index cba7efc8e..000000000 --- a/usrp2/control_lib/newfifo/.gitignore +++ /dev/null @@ -1 +0,0 @@ -a.out diff --git a/usrp2/control_lib/newfifo/buffer_int.v b/usrp2/control_lib/newfifo/buffer_int.v deleted file mode 100644 index b45ed3532..000000000 --- a/usrp2/control_lib/newfifo/buffer_int.v +++ /dev/null @@ -1,168 +0,0 @@ - -// FIFO Interface to the 2K buffer RAMs -// Read port is read-acknowledge -// FIXME do we want to be able to interleave reads and writes? - -module buffer_int - #(parameter BUF_NUM = 0, - parameter BUF_SIZE = 9) - (// Control Interface - input clk, - input rst, - input [31:0] ctrl_word, - input go, - output done, - output error, - output idle, - output [1:0] flag, - - // Buffer Interface - output en_o, - output we_o, - output reg [BUF_SIZE-1:0] addr_o, - output [31:0] dat_to_buf, - input [31:0] dat_from_buf, - - // Write FIFO Interface - input [31:0] wr_data_i, - input [3:0] wr_flags_i, - input wr_ready_i, - output wr_ready_o, - - // Read FIFO Interface - output [31:0] rd_data_o, - output [3:0] rd_flags_o, - output rd_ready_o, - input rd_ready_i - ); - - reg [31:0] ctrl_reg; - reg go_reg; - - always @(posedge clk) - go_reg <= go; - - always @(posedge clk) - if(rst) - ctrl_reg <= 0; - else - if(go & (ctrl_word[31:28] == BUF_NUM)) - ctrl_reg <= ctrl_word; - - wire [BUF_SIZE-1:0] firstline = ctrl_reg[BUF_SIZE-1:0]; - wire [BUF_SIZE-1:0] lastline = ctrl_reg[2*BUF_SIZE-1:BUF_SIZE]; - - wire read = ctrl_reg[22]; - wire write = ctrl_reg[23]; - wire clear = ctrl_reg[24]; - //wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block - //wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ? - - localparam IDLE = 3'd0; - localparam PRE_READ = 3'd1; - localparam READING = 3'd2; - localparam WRITING = 3'd3; - localparam ERROR = 3'd4; - localparam DONE = 3'd5; - - reg [2:0] state; - reg rd_sop, rd_eop; - wire wr_sop, wr_eop, wr_error; - reg [1:0] rd_occ; - wire [1:0] wr_occ; - - always @(posedge clk) - if(rst) - begin - state <= IDLE; - rd_sop <= 0; - rd_eop <= 0; - rd_occ <= 0; - end - else - if(clear) - begin - state <= IDLE; - rd_sop <= 0; - rd_eop <= 0; - rd_occ <= 0; - end - else - case(state) - IDLE : - if(go_reg & read) - begin - addr_o <= firstline; - state <= PRE_READ; - end - else if(go_reg & write) - begin - addr_o <= firstline; - state <= WRITING; - end - - PRE_READ : - begin - state <= READING; - addr_o <= addr_o + 1; - rd_occ <= 2'b00; - rd_sop <= 1; - rd_eop <= 0; - end - - READING : - if(rd_ready_i) - begin - rd_sop <= 0; - addr_o <= addr_o + 1; - if(addr_o == lastline) - begin - rd_eop <= 1; - // FIXME assign occ here - rd_occ <= 0; - end - else - rd_eop <= 0; - if(rd_eop) - state <= DONE; - end - - WRITING : - begin - if(wr_ready_i) - begin - addr_o <= addr_o + 1; - if(wr_error) - begin - state <= ERROR; - // Save OCC flags here - end - else if((addr_o == lastline)||wr_eop) - state <= DONE; - end // if (wr_ready_i) - end // case: WRITING - - endcase // case(state) - - assign dat_to_buf = wr_data_i; - assign rd_data_o = dat_from_buf; - - assign rd_flags_o = { rd_occ[1:0], rd_eop, rd_sop }; - assign rd_ready_o = (state == READING); - - assign wr_sop = wr_flags_i[0]; - assign wr_eop = wr_flags_i[1]; - assign wr_occ = wr_flags_i[3:2]; - assign wr_error = wr_sop & wr_eop; - assign wr_ready_o = (state == WRITING); - - assign we_o = (state == WRITING); - //assign we_o = (state == WRITING) && wr_ready_i; // always write to avoid timing issue - - assign en_o = ~((state==READING)& ~rd_ready_i); // FIXME potential critical path - - assign done = (state == DONE); - assign error = (state == ERROR); - assign idle = (state == IDLE); - -endmodule // buffer_int diff --git a/usrp2/control_lib/newfifo/buffer_int_tb.v b/usrp2/control_lib/newfifo/buffer_int_tb.v deleted file mode 100644 index df54dcc0b..000000000 --- a/usrp2/control_lib/newfifo/buffer_int_tb.v +++ /dev/null @@ -1,418 +0,0 @@ - -module buffer_int_tb (); - - reg clk = 0; - reg rst = 1; - - initial #100 rst = 0; - always #5 clk = ~clk; - - wire en, we; - wire [8:0] addr; - wire [31:0] fifo2buf, buf2fifo; - - wire [31:0] rd_data_o; - wire [3:0] rd_flags_o; - wire rd_sop_o, rd_eop_o; - reg rd_error_i = 0, rd_read_i = 0; - - reg [31:0] wr_data_i = 0; - wire [3:0] wr_flags_i; - reg wr_eop_i = 0, wr_sop_i = 0; - reg wr_write_i = 0; - wire wr_ready_o, wr_full_o; - - reg clear = 0, write = 0, read = 0; - reg [8:0] firstline = 0, lastline = 0; - wire [3:0] step = 1; - wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline}; - reg go = 0; - wire done, error; - - assign wr_flags_i = {2'b00, wr_eop_i, wr_sop_i}; - assign rd_sop_o = rd_flags_o[0]; - assign rd_eop_o = rd_flags_o[1]; - - buffer_int buffer_int - (.clk(clk),.rst(rst), - .ctrl_word(ctrl_word),.go(go), - .done(done),.error(error), - - // Buffer Interface - .en_o(en),.we_o(we),.addr_o(addr), - .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo), - - // Write FIFO Interface - .wr_data_i(wr_data_i), .wr_flags_i(wr_flags_i), .wr_write_i(wr_write_i), .wr_ready_o(wr_ready_o), - - // Read FIFO Interface - .rd_data_o(rd_data_o), .rd_flags_o(rd_flags_o), .rd_ready_o(rd_ready_o), .rd_read_i(rd_read_i) - ); - - reg ram_en = 0, ram_we = 0; - reg [8:0] ram_addr = 0; - reg [31:0] ram_data = 0; - - ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port - (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(), - .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) ); - - initial - begin - @(negedge rst); - @(posedge clk); - FillRAM; - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing full read, no wait states."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(6,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing full read, 2 wait states."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(6,2); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 0 wait states, then nothing after last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(3,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 0 wait states, then done at same time as last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(2,0); - ReadALine; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 3 wait states, then error at same time as last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(2,3); - rd_error_i <= 1; - ReadALine; - rd_error_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(500,511); - $display("Testing full read, to the end of the buffer."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(12,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,511); - $display("Testing full read, start to end of the buffer."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(512,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(505,3); - $display("Testing full read, wraparound"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(11,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(10,15); - $display("Testing Full Write, no wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,72); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(18,23); - $display("Testing Full Write, 1 wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,1,101); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(27,40); - $display("Testing Partial Write, 0 wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,201); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(45,200); - $display("Testing Partial Write, 0 wait states, then done and write simultaneously"); - while(!wr_ready_o) - @(posedge clk); - wr_sop_i <= 1; wr_eop_i <= 0; - WriteLines(6,0,301); - wr_sop_i <= 0; wr_eop_i <= 1; - WriteALine(400); - wr_sop_i <= 0; wr_eop_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(55,200); - $display("Testing Partial Write, 0 wait states, then error"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,501); - wr_sop_i <= 1; wr_eop_i <= 1; - WriteALine(400); - @(posedge clk); - repeat (10) - @(posedge clk); - wr_sop_i <= 0; wr_eop_i <= 0; - - ResetBuffer; - SetBufferRead(0,82); - $display("Testing read after all the writes"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(83,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(508,4); - $display("Testing wraparound write"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(9,0,601); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(506,10); - $display("Reading wraparound write"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(17,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(0,511); - $display("Testing Whole Buffer write"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(512,0,1000); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,511); - $display("Reading Whole Buffer write"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(512,0); - repeat (10) - @(posedge clk); - - /* - ResetBuffer; - SetBufferWrite(5,10); - $display("Testing Write Too Many"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(12,0,2000); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,15); - $display("Reading back Write Too Many"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(16,0); - repeat (10) - @(posedge clk); - */ - ResetBuffer; - SetBufferWrite(15,20); - $display("Testing Write One Less Than Full"); - while(!wr_ready_o) - @(posedge clk); - wr_sop_i <= 1; wr_eop_i <= 0; - WriteALine(400); - wr_sop_i <= 0; wr_eop_i <= 0; - WriteLines(3,0,2000); - wr_sop_i <= 0; wr_eop_i <= 1; - WriteALine(400); - wr_sop_i <= 0; wr_eop_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(13,22); - $display("Reading back Write One Less Than Full"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(10,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - repeat(100) - @(posedge clk); - $finish; - end - - always @(posedge clk) - if(rd_read_i == 1'd1) - $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_data_o, rd_sop_o, rd_eop_o); - - always @(posedge clk) - if(wr_write_i == 1'd1) - $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_data_i, wr_ready_o, wr_full_o); - - initial begin - $dumpfile("buffer_int_tb.lxt"); - $dumpvars(0,buffer_int_tb); - end - - task FillRAM; - begin - ram_addr <= 0; - ram_data <= 0; - @(posedge clk); - ram_en <= 1; - ram_we <= 1; - @(posedge clk); - repeat (511) - begin - ram_addr <= ram_addr + 1; - ram_data <= ram_data + 1; - ram_en <= 1; - ram_we <= 1; - @(posedge clk); - end - ram_en <= 0; - ram_we <= 0; - @(posedge clk); - $display("Filled the RAM"); - end - endtask // FillRAM - - task ResetBuffer; - begin - clear <= 1; read <= 0; write <= 0; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Reset"); - end - endtask // ClearBuffer - - task SetBufferWrite; - input [8:0] start; - input [8:0] stop; - begin - clear <= 0; read <= 0; write <= 1; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Write"); - end - endtask // SetBufferWrite - - task SetBufferRead; - input [8:0] start; - input [8:0] stop; - begin - clear <= 0; read <= 1; write <= 0; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Read"); - end - endtask // SetBufferRead - - task ReadALine; - begin - while(~rd_ready_o) - @(posedge clk); - #1 rd_read_i <= 1; - @(posedge clk); - rd_read_i <= 0; - end - endtask // ReadALine - - task ReadLines; - input [9:0] lines; - input [7:0] wait_states; - begin - $display("Read Lines: Number %d, Wait States %d",lines,wait_states); - repeat (lines) - begin - ReadALine; - repeat (wait_states) - @(posedge clk); - end - end - endtask // ReadLines - - task WriteALine; - input [31:0] value; - begin - while(~wr_ready_o) - @(posedge clk); - #1 wr_write_i <= 1; - wr_data_i <= value; - @(posedge clk); - wr_write_i <= 0; - end - endtask // WriteALine - - task WriteLines; - input [9:0] lines; - input [7:0] wait_states; - input [31:0] value; - begin - $display("Write Lines: Number %d, Wait States %d",lines,wait_states); - repeat(lines) - begin - value <= value + 1; - WriteALine(value); - repeat(wait_states) - @(posedge clk); - end - end - endtask // WriteLines - -endmodule // buffer_int_tb diff --git a/usrp2/control_lib/newfifo/buffer_pool.v b/usrp2/control_lib/newfifo/buffer_pool.v deleted file mode 100644 index 41ac1deb3..000000000 --- a/usrp2/control_lib/newfifo/buffer_pool.v +++ /dev/null @@ -1,283 +0,0 @@ - -// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer -// is a dual-ported RAM. Port A on each of them is indirectly connected -// to the wishbone bus by a bridge. Port B may be connected any one of the -// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The wishbone bus -// provides access to all 8 buffers, and also controls the connections -// between the ports and the buffers, allocating them as needed. - -// wb_adr is 16 bits -- -// bits 13:11 select which buffer -// bits 10:2 select line in buffer -// bits 1:0 are unused (32-bit access only) - -// BUF_SIZE is in address lines (i.e. log2 of number of lines). -// For S3 it should be 9 (512 words, 2KB) -// For V5 it should be at least 10 (1024 words, 4KB) or 11 (2048 words, 8KB) - -module buffer_pool - #(parameter BUF_SIZE = 9, - parameter SET_ADDR = 64) - (input wb_clk_i, - input wb_rst_i, - input wb_we_i, - input wb_stb_i, - input [15:0] wb_adr_i, - input [31:0] wb_dat_i, - output [31:0] wb_dat_o, - output reg wb_ack_o, - output wb_err_o, - output wb_rty_o, - - input stream_clk, - input stream_rst, - - input set_stb, input [7:0] set_addr, input [31:0] set_data, - output [31:0] status, - output sys_int_o, - - output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3, - output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7, - - // Write Interfaces - input [31:0] wr0_data_i, input [3:0] wr0_flags_i, input wr0_ready_i, output wr0_ready_o, - input [31:0] wr1_data_i, input [3:0] wr1_flags_i, input wr1_ready_i, output wr1_ready_o, - input [31:0] wr2_data_i, input [3:0] wr2_flags_i, input wr2_ready_i, output wr2_ready_o, - input [31:0] wr3_data_i, input [3:0] wr3_flags_i, input wr3_ready_i, output wr3_ready_o, - - // Read Interfaces - output [31:0] rd0_data_o, output [3:0] rd0_flags_o, output rd0_ready_o, input rd0_ready_i, - output [31:0] rd1_data_o, output [3:0] rd1_flags_o, output rd1_ready_o, input rd1_ready_i, - output [31:0] rd2_data_o, output [3:0] rd2_flags_o, output rd2_ready_o, input rd2_ready_i, - output [31:0] rd3_data_o, output [3:0] rd3_flags_o, output rd3_ready_o, input rd3_ready_i - ); - - wire [7:0] sel_a; - - wire [BUF_SIZE-1:0] buf_addra = wb_adr_i[BUF_SIZE+1:2]; // ignore address 1:0, 32-bit access only - wire [2:0] which_buf = wb_adr_i[BUF_SIZE+4:BUF_SIZE+2]; // address 15:14 selects the buffer pool - - decoder_3_8 dec(.sel(which_buf),.res(sel_a)); - - genvar i; - - wire go; - - reg [2:0] port[0:7]; - reg [3:0] read_src[0:3]; - reg [3:0] write_src[0:3]; - - wire [7:0] done; - wire [7:0] error; - wire [7:0] idle; - - wire [31:0] buf_doa[0:7]; - - wire [7:0] buf_enb; - wire [7:0] buf_web; - wire [BUF_SIZE-1:0] buf_addrb[0:7]; - wire [31:0] buf_dib[0:7]; - wire [31:0] buf_dob[0:7]; - - wire [31:0] wr_data_i[0:7]; - wire [3:0] wr_flags_i[0:7]; - wire [7:0] wr_ready_i; - wire [7:0] wr_ready_o; - - wire [31:0] rd_data_o[0:7]; - wire [3:0] rd_flags_o[0:7]; - wire [7:0] rd_ready_o; - wire [7:0] rd_ready_i; - - assign status = {8'd0,idle[7:0],error[7:0],done[7:0]}; - - assign s0 = buf_addrb[0]; - assign s1 = buf_addrb[1]; - assign s2 = buf_addrb[2]; - assign s3 = buf_addrb[3]; - assign s4 = buf_addrb[4]; - assign s5 = buf_addrb[5]; - assign s6 = buf_addrb[6]; - assign s7 = buf_addrb[7]; - - wire [31:0] fifo_ctrl; - setting_reg #(.my_addr(SET_ADDR)) - sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out(fifo_ctrl),.changed(go)); - - integer k; - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<8;k=k+1) - port[k] <= 4; // disabled - else - for(k=0;k<8;k=k+1) - if(go & (fifo_ctrl[31:28]==k)) - port[k] <= fifo_ctrl[27:25]; - - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<4;k=k+1) - read_src[k] <= 8; // disabled - else - for(k=0;k<4;k=k+1) - if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k)) - read_src[k] <= fifo_ctrl[31:28]; - - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<4;k=k+1) - write_src[k] <= 8; // disabled - else - for(k=0;k<4;k=k+1) - if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k)) - write_src[k] <= fifo_ctrl[31:28]; - - generate - for(i=0;i<8;i=i+1) - begin : gen_buffer - RAMB16_S36_S36 dpram - (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), - .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i), - .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0), - .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) ); - -/* - ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer - (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i), - .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]), - .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]), - .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); - - */ - - buffer_int #(.BUF_NUM(i),.BUF_SIZE(BUF_SIZE)) buffer_int - (.clk(stream_clk),.rst(stream_rst), - .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)), - .done(done[i]),.error(error[i]),.idle(idle[i]), - .en_o(buf_enb[i]), - .we_o(buf_web[i]), - .addr_o(buf_addrb[i]), - .dat_to_buf(buf_dib[i]), - .dat_from_buf(buf_dob[i]), - .wr_data_i(wr_data_i[i]), - .wr_flags_i(wr_flags_i[i]), - .wr_ready_i(wr_ready_i[i]), - .wr_ready_o(wr_ready_o[i]), - .rd_data_o(rd_data_o[i]), - .rd_flags_o(rd_flags_o[i]), - .rd_ready_o(rd_ready_o[i]), - .rd_ready_i(rd_ready_i[i]) ); - mux4 #(.WIDTH(37)) - mux4_wr (.en(~port[i][2]),.sel(port[i][1:0]), - .i0({wr0_data_i,wr0_flags_i,wr0_ready_i}), - .i1({wr1_data_i,wr1_flags_i,wr1_ready_i}), - .i2({wr2_data_i,wr2_flags_i,wr2_ready_i}), - .i3({wr3_data_i,wr3_flags_i,wr3_ready_i}), - .o({wr_data_i[i],wr_flags_i[i],wr_ready_i[i]}) ); - mux4 #(.WIDTH(1)) - mux4_rd (.en(~port[i][2]),.sel(port[i][1:0]), - .i0(rd0_ready_i),.i1(rd1_ready_i),.i2(rd2_ready_i),.i3(rd3_ready_i), - .o(rd_ready_i[i])); - end // block: gen_buffer - endgenerate - - //---------------------------------------------------------------------- - // Wishbone Outputs - - // Use the following lines if ram output and mux can be made fast enough - - assign wb_err_o = 1'b0; // Unused for now - assign wb_rty_o = 1'b0; // Unused for now - - always @(posedge wb_clk_i) - wb_ack_o <= wb_stb_i & ~wb_ack_o; - assign wb_dat_o = buf_doa[which_buf]; - - // Use this if we can't make the RAM+MUX fast enough - // reg [31:0] wb_dat_o_reg; - // reg stb_d1; - - // always @(posedge wb_clk_i) - // begin - // wb_dat_o_reg <= buf_doa[which_buf]; - // stb_d1 <= wb_stb_i; - // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i); - // end - //assign wb_dat_o = wb_dat_o_reg; - - mux8 #(.WIDTH(1)) - mux8_wr0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), - .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), - .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), - .o(wr0_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), - .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), - .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), - .o(wr1_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), - .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), - .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), - .o(wr2_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), - .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), - .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), - .o(wr3_ready_o)); - - mux8 #(.WIDTH(37)) - mux8_rd0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), - .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), - .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), - .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), - .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), - .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), - .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), - .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), - .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), - .o({rd0_data_o,rd0_flags_o,rd0_ready_o})); - - mux8 #(.WIDTH(37)) - mux8_rd1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), - .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), - .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), - .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), - .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), - .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), - .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), - .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), - .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), - .o({rd1_data_o,rd1_flags_o,rd1_ready_o})); - - mux8 #(.WIDTH(37)) - mux8_rd2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), - .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), - .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), - .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), - .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), - .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), - .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), - .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), - .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), - .o({rd2_data_o,rd2_flags_o,rd2_ready_o})); - - mux8 #(.WIDTH(37)) - mux8_rd3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), - .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), - .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), - .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), - .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), - .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), - .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), - .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), - .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), - .o({rd3_data_o,rd3_flags_o,rd3_ready_o})); - - assign sys_int_o = (|error) | (|done); - -endmodule // buffer_pool diff --git a/usrp2/control_lib/newfifo/buffer_pool_tb.v b/usrp2/control_lib/newfifo/buffer_pool_tb.v deleted file mode 100644 index 91a01d268..000000000 --- a/usrp2/control_lib/newfifo/buffer_pool_tb.v +++ /dev/null @@ -1,58 +0,0 @@ - -module buffer_pool_tb(); - - wire wb_clk_i; - wire wb_rst_i; - wire wb_we_i; - wire wb_stb_i; - wire [15:0] wb_adr_i; - wire [31:0] wb_dat_i; - wire [31:0] wb_dat_o; - wire wb_ack_o; - wire wb_err_o; - wire wb_rty_o; - - wire stream_clk, stream_rst; - - wire set_stb; - wire [7:0] set_addr; - wire [31:0] set_data; - - wire [31:0] wr0_data, wr1_data, wr2_data, wr3_data; - wire [31:0] rd0_data, rd1_data, rd2_data, rd3_data; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire wr0_ready, wr1_ready, wr2_ready, wr3_ready; - wire rd0_ready, rd1_ready, rd2_ready, rd3_ready; - wire wr0_write, wr1_write, wr2_write, wr3_write; - wire rd0_read, rd1_read, rd2_read, rd3_read; - - buffer_pool dut - (.wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - .wb_we_i(wb_we_i), - .wb_stb_i(wb_stb_i), - .wb_adr_i(wb_adr_i), - .wb_dat_i(wb_dat_i), - .wb_dat_o(wb_dat_o), - .wb_ack_o(wb_ack_o), - .wb_err_o(wb_err_o), - .wb_rty_o(wb_rty_o), - - .stream_clk(stream_clk), - .stream_rst(stream_rst), - - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - - .wr0_data_i(wr0_data), .wr0_write_i(wr0_write), .wr0_flags_i(wr0_flags), .wr0_ready_o(wr0_ready), - .wr1_data_i(wr1_data), .wr1_write_i(wr1_write), .wr1_flags_i(wr1_flags), .wr1_ready_o(wr1_ready), - .wr2_data_i(wr2_data), .wr2_write_i(wr2_write), .wr2_flags_i(wr2_flags), .wr2_ready_o(wr2_ready), - .wr3_data_i(wr3_data), .wr3_write_i(wr3_write), .wr3_flags_i(wr3_flags), .wr3_ready_o(wr3_ready), - - .rd0_data_o(rd0_data), .rd0_read_i(rd0_read), .rd0_flags_o(rd0_flags), .rd0_ready_o(rd0_ready), - .rd1_data_o(rd1_data), .rd1_read_i(rd1_read), .rd1_flags_o(rd1_flags), .rd1_ready_o(rd1_ready), - .rd2_data_o(rd2_data), .rd2_read_i(rd2_read), .rd2_flags_o(rd2_flags), .rd2_ready_o(rd2_ready), - .rd3_data_o(rd3_data), .rd3_read_i(rd3_read), .rd3_flags_o(rd3_flags), .rd3_ready_o(rd3_ready) - ); - -endmodule // buffer_pool_tb diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v deleted file mode 100644 index 5f9aeff9b..000000000 --- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v +++ /dev/null @@ -1,76 +0,0 @@ - -module fifo19_to_fifo36 - (input clk, input reset, input clear, - input [18:0] f19_datain, - input f19_src_rdy_i, - output f19_dst_rdy_o, - - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i, - output [31:0] debug - ); - - reg f36_sof, f36_eof, f36_occ; - - reg [1:0] state; - reg [15:0] dat0, dat1; - - wire f19_sof = f19_datain[16]; - wire f19_eof = f19_datain[17]; - wire f19_occ = f19_datain[18]; - - wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; - - always @(posedge clk) - if(f19_src_rdy_i & ((state==0)|xfer_out)) - f36_sof <= f19_sof; - - always @(posedge clk) - if(f19_src_rdy_i & ((state != 2)|xfer_out)) - f36_eof <= f19_eof; - - always @(posedge clk) // FIXME check this - if(f19_eof) - f36_occ <= {state[0],f19_occ}; - else - f36_occ <= 0; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(f19_src_rdy_i) - case(state) - 0 : - if(f19_eof) - state <= 2; - else - state <= 1; - 1 : - state <= 2; - 2 : - if(xfer_out) - if(~f19_eof) - state <= 1; - // remain in state 2 if we are at eof - endcase // case(state) - else - if(xfer_out) - state <= 0; - - always @(posedge clk) - if(f19_src_rdy_i & (state==1)) - dat1 <= f19_datain; - - always @(posedge clk) - if(f19_src_rdy_i & ((state==0) | xfer_out)) - dat0 <= f19_datain; - - assign f19_dst_rdy_o = xfer_out | (state != 2); - assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; - assign f36_src_rdy_o = (state == 2); - - assign debug = state; - -endmodule // fifo19_to_fifo36 diff --git a/usrp2/control_lib/newfifo/fifo19_to_ll8.v b/usrp2/control_lib/newfifo/fifo19_to_ll8.v deleted file mode 100644 index 4707f7523..000000000 --- a/usrp2/control_lib/newfifo/fifo19_to_ll8.v +++ /dev/null @@ -1,53 +0,0 @@ - -module fifo19_to_ll8 - (input clk, input reset, input clear, - input [18:0] f19_data, - input f19_src_rdy_i, - output f19_dst_rdy_o, - - output reg [7:0] ll_data, - output ll_sof_n, - output ll_eof_n, - output ll_src_rdy_n, - input ll_dst_rdy_n); - - wire ll_sof, ll_eof, ll_src_rdy; - assign ll_sof_n = ~ll_sof; - assign ll_eof_n = ~ll_eof; - assign ll_src_rdy_n = ~ll_src_rdy; - wire ll_dst_rdy = ~ll_dst_rdy_n; - - wire f19_sof = f19_data[16]; - wire f19_eof = f19_data[17]; - wire f19_occ = f19_data[18]; - - wire advance, end_early; - reg state; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(advance) - if(ll_eof) - state <= 0; - else - state <= state + 1; - - always @* - case(state) - 0 : ll_data = f19_data[15:8]; - 1 : ll_data = f19_data[7:0]; - default : ll_data = f19_data[15:8]; - endcase // case (state) - - assign ll_sof = (state==0) & f19_sof; - assign ll_eof = f19_eof & ((f19_occ==1)|(state==1)); - - assign ll_src_rdy = f19_src_rdy_i; - - assign advance = ll_src_rdy & ll_dst_rdy; - assign f19_dst_rdy_o = advance & ((state==1)|ll_eof); - -endmodule // fifo19_to_ll8 - diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo18.v b/usrp2/control_lib/newfifo/fifo36_to_fifo18.v deleted file mode 100644 index b636ab9ca..000000000 --- a/usrp2/control_lib/newfifo/fifo36_to_fifo18.v +++ /dev/null @@ -1,40 +0,0 @@ - -module fifo36_to_fifo18 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [17:0] f18_dataout, - output f18_src_rdy_o, - input f18_dst_rdy_i ); - - wire f36_sof = f36_datain[32]; - wire f36_eof = f36_datain[33]; - wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - - assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; - assign f18_dataout[16] = phase ? 0 : f36_sof; - assign f18_dataout[17] = phase ? f36_eof : half_line; - - assign f18_src_rdy_o = f36_src_rdy_i; - assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i; - - wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - - always @(posedge clk) - if(reset) - phase <= 0; - else if(f36_xfer) - phase <= 0; - else if(f18_xfer) - phase <= 1; - - -endmodule // fifo36_to_fifo18 - diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v deleted file mode 100644 index de249aaeb..000000000 --- a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v +++ /dev/null @@ -1,41 +0,0 @@ - -module fifo36_to_fifo19 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [18:0] f19_dataout, - output f19_src_rdy_o, - input f19_dst_rdy_i ); - - wire f36_sof = f36_datain[32]; - wire f36_eof = f36_datain[33]; - wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - - assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; - assign f19_dataout[16] = phase ? 0 : f36_sof; - assign f19_dataout[17] = phase ? f36_eof : half_line; - assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); - - assign f19_src_rdy_o = f36_src_rdy_i; - assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; - - wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - - always @(posedge clk) - if(reset) - phase <= 0; - else if(f36_xfer) - phase <= 0; - else if(f19_xfer) - phase <= 1; - - -endmodule // fifo36_to_fifo19 - diff --git a/usrp2/control_lib/newfifo/fifo36_to_ll8.v b/usrp2/control_lib/newfifo/fifo36_to_ll8.v deleted file mode 100644 index 0dee1dfc6..000000000 --- a/usrp2/control_lib/newfifo/fifo36_to_ll8.v +++ /dev/null @@ -1,60 +0,0 @@ - -module fifo36_to_ll8 - (input clk, input reset, input clear, - input [35:0] f36_data, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output reg [7:0] ll_data, - output ll_sof_n, - output ll_eof_n, - output ll_src_rdy_n, - input ll_dst_rdy_n, - - output [31:0] debug); - - wire ll_sof, ll_eof, ll_src_rdy; - assign ll_sof_n = ~ll_sof; - assign ll_eof_n = ~ll_eof; - assign ll_src_rdy_n = ~ll_src_rdy; - wire ll_dst_rdy = ~ll_dst_rdy_n; - - wire f36_sof = f36_data[32]; - wire f36_eof = f36_data[33]; - wire f36_occ = f36_data[35:34]; - wire advance, end_early; - reg [1:0] state; - assign debug = {29'b0,state}; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(advance) - if(ll_eof) - state <= 0; - else - state <= state + 1; - - always @* - case(state) - 0 : ll_data = f36_data[31:24]; - 1 : ll_data = f36_data[23:16]; - 2 : ll_data = f36_data[15:8]; - 3 : ll_data = f36_data[7:0]; - default : ll_data = f36_data[31:24]; - endcase // case (state) - - assign ll_sof = (state==0) & f36_sof; - assign ll_eof = f36_eof & (((state==0)&(f36_occ==1)) | - ((state==1)&(f36_occ==2)) | - ((state==2)&(f36_occ==3)) | - (state==3)); - - assign ll_src_rdy = f36_src_rdy_i; - - assign advance = ll_src_rdy & ll_dst_rdy; - assign f36_dst_rdy_o = advance & ((state==3)|ll_eof); - assign debug = state; - -endmodule // ll8_to_fifo36 diff --git a/usrp2/control_lib/newfifo/fifo_2clock.v b/usrp2/control_lib/newfifo/fifo_2clock.v deleted file mode 100644 index 34c85ccb4..000000000 --- a/usrp2/control_lib/newfifo/fifo_2clock.v +++ /dev/null @@ -1,117 +0,0 @@ - -// FIXME ignores the AWIDTH (fifo size) parameter - -module fifo_2clock - #(parameter WIDTH=36, SIZE=6) - (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, - input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, - input arst); - - wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels - wire full, empty, write, read; - - assign dst_rdy_o = ~full; - assign src_rdy_o = ~empty; - assign write = src_rdy_i & dst_rdy_o; - assign read = src_rdy_o & dst_rdy_i; - - generate - if(WIDTH==36) - if(SIZE==9) - fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if(SIZE==11) - fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if(SIZE==6) - fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else - fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if((WIDTH==19)|(WIDTH==18)) - if(SIZE==4) - fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - endgenerate - - assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; - assign space = ((1< clear $end -$var wire 1 ? clk $end -$var wire 36 @ datain [35:0] $end -$var wire 36 A dataout [35:0] $end -$var wire 1 $ dst_rdy_i $end -$var wire 1 ! dst_rdy_o $end -$var wire 1 B read $end -$var wire 1 C reset $end -$var wire 1 D src_rdy_i $end -$var wire 1 % src_rdy_o $end -$var wire 1 E write $end -$var reg 4 F a [3:0] $end -$var reg 1 G empty $end -$var reg 1 H full $end -$var reg 5 I occupied [4:0] $end -$var reg 5 J space [4:0] $end -$scope begin gen_srl16[0] $end -$scope module srl16e $end -$var wire 1 K A0 $end -$var wire 1 L A1 $end -$var wire 1 M A2 $end -$var wire 1 N A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 O D $end -$var wire 1 P Q $end -$var reg 16 Q data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[1] $end -$scope module srl16e $end -$var wire 1 R A0 $end -$var wire 1 S A1 $end -$var wire 1 T A2 $end -$var wire 1 U A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 V D $end -$var wire 1 W Q $end -$var reg 16 X data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[2] $end -$scope module srl16e $end -$var wire 1 Y A0 $end -$var wire 1 Z A1 $end -$var wire 1 [ A2 $end -$var wire 1 \ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ] D $end -$var wire 1 ^ Q $end -$var reg 16 _ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[3] $end -$scope module srl16e $end -$var wire 1 ` A0 $end -$var wire 1 a A1 $end -$var wire 1 b A2 $end -$var wire 1 c A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 d D $end -$var wire 1 e Q $end -$var reg 16 f data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[4] $end -$scope module srl16e $end -$var wire 1 g A0 $end -$var wire 1 h A1 $end -$var wire 1 i A2 $end -$var wire 1 j A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 k D $end -$var wire 1 l Q $end -$var reg 16 m data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[5] $end -$scope module srl16e $end -$var wire 1 n A0 $end -$var wire 1 o A1 $end -$var wire 1 p A2 $end -$var wire 1 q A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 r D $end -$var wire 1 s Q $end -$var reg 16 t data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[6] $end -$scope module srl16e $end -$var wire 1 u A0 $end -$var wire 1 v A1 $end -$var wire 1 w A2 $end -$var wire 1 x A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 y D $end -$var wire 1 z Q $end -$var reg 16 { data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[7] $end -$scope module srl16e $end -$var wire 1 | A0 $end -$var wire 1 } A1 $end -$var wire 1 ~ A2 $end -$var wire 1 !" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 "" D $end -$var wire 1 #" Q $end -$var reg 16 $" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[8] $end -$scope module srl16e $end -$var wire 1 %" A0 $end -$var wire 1 &" A1 $end -$var wire 1 '" A2 $end -$var wire 1 (" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 )" D $end -$var wire 1 *" Q $end -$var reg 16 +" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[9] $end -$scope module srl16e $end -$var wire 1 ," A0 $end -$var wire 1 -" A1 $end -$var wire 1 ." A2 $end -$var wire 1 /" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 0" D $end -$var wire 1 1" Q $end -$var reg 16 2" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[10] $end -$scope module srl16e $end -$var wire 1 3" A0 $end -$var wire 1 4" A1 $end -$var wire 1 5" A2 $end -$var wire 1 6" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 7" D $end -$var wire 1 8" Q $end -$var reg 16 9" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[11] $end -$scope module srl16e $end -$var wire 1 :" A0 $end -$var wire 1 ;" A1 $end -$var wire 1 <" A2 $end -$var wire 1 =" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 >" D $end -$var wire 1 ?" Q $end -$var reg 16 @" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[12] $end -$scope module srl16e $end -$var wire 1 A" A0 $end -$var wire 1 B" A1 $end -$var wire 1 C" A2 $end -$var wire 1 D" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 E" D $end -$var wire 1 F" Q $end -$var reg 16 G" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[13] $end -$scope module srl16e $end -$var wire 1 H" A0 $end -$var wire 1 I" A1 $end -$var wire 1 J" A2 $end -$var wire 1 K" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 L" D $end -$var wire 1 M" Q $end -$var reg 16 N" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[14] $end -$scope module srl16e $end -$var wire 1 O" A0 $end -$var wire 1 P" A1 $end -$var wire 1 Q" A2 $end -$var wire 1 R" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 S" D $end -$var wire 1 T" Q $end -$var reg 16 U" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[15] $end -$scope module srl16e $end -$var wire 1 V" A0 $end -$var wire 1 W" A1 $end -$var wire 1 X" A2 $end -$var wire 1 Y" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 Z" D $end -$var wire 1 [" Q $end -$var reg 16 \" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[16] $end -$scope module srl16e $end -$var wire 1 ]" A0 $end -$var wire 1 ^" A1 $end -$var wire 1 _" A2 $end -$var wire 1 `" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 a" D $end -$var wire 1 b" Q $end -$var reg 16 c" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[17] $end -$scope module srl16e $end -$var wire 1 d" A0 $end -$var wire 1 e" A1 $end -$var wire 1 f" A2 $end -$var wire 1 g" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 h" D $end -$var wire 1 i" Q $end -$var reg 16 j" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[18] $end -$scope module srl16e $end -$var wire 1 k" A0 $end -$var wire 1 l" A1 $end -$var wire 1 m" A2 $end -$var wire 1 n" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 o" D $end -$var wire 1 p" Q $end -$var reg 16 q" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[19] $end -$scope module srl16e $end -$var wire 1 r" A0 $end -$var wire 1 s" A1 $end -$var wire 1 t" A2 $end -$var wire 1 u" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 v" D $end -$var wire 1 w" Q $end -$var reg 16 x" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[20] $end -$scope module srl16e $end -$var wire 1 y" A0 $end -$var wire 1 z" A1 $end -$var wire 1 {" A2 $end -$var wire 1 |" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 }" D $end -$var wire 1 ~" Q $end -$var reg 16 !# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[21] $end -$scope module srl16e $end -$var wire 1 "# A0 $end -$var wire 1 ## A1 $end -$var wire 1 $# A2 $end -$var wire 1 %# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 &# D $end -$var wire 1 '# Q $end -$var reg 16 (# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[22] $end -$scope module srl16e $end -$var wire 1 )# A0 $end -$var wire 1 *# A1 $end -$var wire 1 +# A2 $end -$var wire 1 ,# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 -# D $end -$var wire 1 .# Q $end -$var reg 16 /# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[23] $end -$scope module srl16e $end -$var wire 1 0# A0 $end -$var wire 1 1# A1 $end -$var wire 1 2# A2 $end -$var wire 1 3# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 4# D $end -$var wire 1 5# Q $end -$var reg 16 6# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[24] $end -$scope module srl16e $end -$var wire 1 7# A0 $end -$var wire 1 8# A1 $end -$var wire 1 9# A2 $end -$var wire 1 :# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ;# D $end -$var wire 1 <# Q $end -$var reg 16 =# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[25] $end -$scope module srl16e $end -$var wire 1 ># A0 $end -$var wire 1 ?# A1 $end -$var wire 1 @# A2 $end -$var wire 1 A# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 B# D $end -$var wire 1 C# Q $end -$var reg 16 D# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[26] $end -$scope module srl16e $end -$var wire 1 E# A0 $end -$var wire 1 F# A1 $end -$var wire 1 G# A2 $end -$var wire 1 H# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 I# D $end -$var wire 1 J# Q $end -$var reg 16 K# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[27] $end -$scope module srl16e $end -$var wire 1 L# A0 $end -$var wire 1 M# A1 $end -$var wire 1 N# A2 $end -$var wire 1 O# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 P# D $end -$var wire 1 Q# Q $end -$var reg 16 R# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[28] $end -$scope module srl16e $end -$var wire 1 S# A0 $end -$var wire 1 T# A1 $end -$var wire 1 U# A2 $end -$var wire 1 V# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 W# D $end -$var wire 1 X# Q $end -$var reg 16 Y# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[29] $end -$scope module srl16e $end -$var wire 1 Z# A0 $end -$var wire 1 [# A1 $end -$var wire 1 \# A2 $end -$var wire 1 ]# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ^# D $end -$var wire 1 _# Q $end -$var reg 16 `# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[30] $end -$scope module srl16e $end -$var wire 1 a# A0 $end -$var wire 1 b# A1 $end -$var wire 1 c# A2 $end -$var wire 1 d# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 e# D $end -$var wire 1 f# Q $end -$var reg 16 g# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[31] $end -$scope module srl16e $end -$var wire 1 h# A0 $end -$var wire 1 i# A1 $end -$var wire 1 j# A2 $end -$var wire 1 k# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 l# D $end -$var wire 1 m# Q $end -$var reg 16 n# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[32] $end -$scope module srl16e $end -$var wire 1 o# A0 $end -$var wire 1 p# A1 $end -$var wire 1 q# A2 $end -$var wire 1 r# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 s# D $end -$var wire 1 t# Q $end -$var reg 16 u# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[33] $end -$scope module srl16e $end -$var wire 1 v# A0 $end -$var wire 1 w# A1 $end -$var wire 1 x# A2 $end -$var wire 1 y# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 z# D $end -$var wire 1 {# Q $end -$var reg 16 |# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[34] $end -$scope module srl16e $end -$var wire 1 }# A0 $end -$var wire 1 ~# A1 $end -$var wire 1 !$ A2 $end -$var wire 1 "$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 #$ D $end -$var wire 1 $$ Q $end -$var reg 16 %$ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[35] $end -$scope module srl16e $end -$var wire 1 &$ A0 $end -$var wire 1 '$ A1 $end -$var wire 1 ($ A2 $end -$var wire 1 )$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 *$ D $end -$var wire 1 +$ Q $end -$var reg 16 ,$ data [15:0] $end -$upscope $end -$upscope $end -$upscope $end -$scope module fifo36_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 -$ f19_dataout [18:0] $end -$var wire 1 ' f19_dst_rdy_i $end -$var wire 1 ( f19_src_rdy_o $end -$var wire 1 .$ f19_xfer $end -$var wire 36 /$ f36_datain [35:0] $end -$var wire 1 $ f36_dst_rdy_o $end -$var wire 1 0$ f36_eof $end -$var wire 1 1$ f36_occ $end -$var wire 1 2$ f36_sof $end -$var wire 1 % f36_src_rdy_i $end -$var wire 1 3$ f36_xfer $end -$var wire 1 4$ half_line $end -$var wire 1 C reset $end -$var reg 1 5$ phase $end -$upscope $end -$scope module fifo19_to_ll8 $end -$var wire 1 6$ advance $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 7$ f19_data [18:0] $end -$var wire 1 ' f19_dst_rdy_o $end -$var wire 1 8$ f19_eof $end -$var wire 1 9$ f19_occ $end -$var wire 1 :$ f19_sof $end -$var wire 1 ( f19_src_rdy_i $end -$var wire 1 ;$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 <$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 =$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 >$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var reg 8 ?$ ll_data [7:0] $end -$var reg 1 @$ state $end -$upscope $end -$scope module ll8_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 A$ f19_data [18:0] $end -$var wire 1 * f19_dst_rdy_i $end -$var wire 1 + f19_src_rdy_o $end -$var wire 8 B$ ll_data [7:0] $end -$var wire 1 C$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 D$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 E$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 F$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var wire 1 G$ xfer_out $end -$var reg 8 H$ dat0 [7:0] $end -$var reg 8 I$ dat1 [7:0] $end -$var reg 1 J$ f19_eof $end -$var reg 1 K$ f19_occ $end -$var reg 1 L$ f19_sof $end -$var reg 2 M$ state [1:0] $end -$upscope $end -$scope module fifo19_to_fifo36 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 N$ f19_datain [18:0] $end -$var wire 1 * f19_dst_rdy_o $end -$var wire 1 O$ f19_eof $end -$var wire 1 P$ f19_occ $end -$var wire 1 Q$ f19_sof $end -$var wire 1 + f19_src_rdy_i $end -$var wire 36 R$ f36_dataout [35:0] $end -$var wire 1 S$ f36_dst_rdy_i $end -$var wire 1 - f36_src_rdy_o $end -$var wire 1 C reset $end -$var wire 1 T$ xfer_out $end -$var reg 16 U$ dat0 [15:0] $end -$var reg 16 V$ dat1 [15:0] $end -$var reg 1 W$ f36_eof $end -$var reg 1 X$ f36_occ $end -$var reg 1 Y$ f36_sof $end -$var reg 2 Z$ state [1:0] $end -$upscope $end -$scope task PutPacketInFIFO36 $end -$var reg 32 [$ data_len [31:0] $end -$var reg 32 \$ data_start [31:0] $end -$upscope $end -$scope task ReadFromFIFO36 $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx \$ -bx [$ -bx Z$ -xY$ -xX$ -xW$ -bx V$ -bx U$ -0T$ -0S$ -b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$ -xQ$ -xP$ -xO$ -bx N$ -bx M$ -xL$ -xK$ -xJ$ -bx I$ -bx H$ -xG$ -xF$ -xE$ -xD$ -xC$ -bx B$ -bx A$ -x@$ -bx ?$ -x>$ -x=$ -x<$ -x;$ -x:$ -x9$ -x8$ -bx 7$ -x6$ -x5$ -x4$ -x3$ -x2$ -x1$ -x0$ -bx /$ -x.$ -bx -$ -b0 ,$ -x+$ -0*$ -x)$ -x($ -x'$ -x&$ -b0 %$ -x$$ -0#$ -x"$ -x!$ -x~# -x}# -b0 |# -x{# -0z# -xy# -xx# -xw# -xv# -b0 u# -xt# -0s# -xr# -xq# -xp# -xo# -b0 n# -xm# -0l# -xk# -xj# -xi# -xh# -b0 g# -xf# -0e# -xd# -xc# -xb# -xa# -b0 `# -x_# -0^# -x]# -x\# -x[# -xZ# -b0 Y# -xX# -0W# -xV# -xU# -xT# -xS# -b0 R# -xQ# -0P# -xO# -xN# -xM# -xL# -b0 K# -xJ# -0I# -xH# -xG# -xF# -xE# -b0 D# -xC# -0B# -xA# -x@# -x?# -x># -b0 =# -x<# -0;# -x:# -x9# -x8# -x7# -b0 6# -x5# -04# -x3# -x2# -x1# -x0# -b0 /# -x.# -0-# -x,# -x+# -x*# -x)# -b0 (# -x'# -0&# -x%# -x$# -x## -x"# -b0 !# -x~" -0}" -x|" -x{" -xz" -xy" -b0 x" -xw" -0v" -xu" -xt" -xs" -xr" -b0 q" -xp" -0o" -xn" -xm" -xl" -xk" -b0 j" -xi" -0h" -xg" -xf" -xe" -xd" -b0 c" -xb" -0a" -x`" -x_" -x^" -x]" -b0 \" -x[" -0Z" -xY" -xX" -xW" -xV" -b0 U" -xT" -0S" -xR" -xQ" -xP" -xO" -b0 N" -xM" -0L" -xK" -xJ" -xI" -xH" -b0 G" -xF" -0E" -xD" -xC" -xB" -xA" -b0 @" -x?" -0>" -x=" -x<" -x;" -x:" -b0 9" -x8" -07" -x6" -x5" -x4" -x3" -b0 2" -x1" -00" -x/" -x." -x-" -x," -b0 +" -x*" -0)" -x(" -x'" -x&" -x%" -b0 $" -x#" -0"" -x!" -x~ -x} -x| -b0 { -xz -0y -xx -xw -xv -xu -b0 t -xs -0r -xq -xp -xo -xn -b0 m -xl -0k -xj -xi -xh -xg -b0 f -xe -0d -xc -xb -xa -x` -b0 _ -x^ -0] -x\ -x[ -xZ -xY -b0 X -xW -0V -xU -xT -xS -xR -b0 Q -xP -0O -xN -xM -xL -xK -bx J -bx I -xH -xG -bx F -0E -0D -1C -xB -bx A -b0 @ -0? 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-#19900000000000000 -04 -0? -#19950000000000000 -14 -1? -#20000000000000000 -04 -0? diff --git a/usrp2/control_lib/newfifo/fifo_short.v b/usrp2/control_lib/newfifo/fifo_short.v deleted file mode 100644 index 53a7603c7..000000000 --- a/usrp2/control_lib/newfifo/fifo_short.v +++ /dev/null @@ -1,95 +0,0 @@ - -module fifo_short - #(parameter WIDTH=32) - (input clk, input reset, input clear, - input [WIDTH-1:0] datain, - input src_rdy_i, - output dst_rdy_o, - output [WIDTH-1:0] dataout, - output src_rdy_o, - input dst_rdy_i, - - output reg [4:0] space, - output reg [4:0] occupied); - - reg full, empty; - wire write = src_rdy_i & dst_rdy_o; - wire read = dst_rdy_i & src_rdy_o; - - assign dst_rdy_o = ~full; - assign src_rdy_o = ~empty; - - reg [3:0] a; - genvar i; - - generate - for (i=0;i 00 = all 4 bytes - 01 = 1 byte - 10 = 2 bytes - 11 = 3 bytes - -fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]} - OCC same as buffer interface - -fifo19 --> {OCC,EOP,SOP,DATA[15:0]} - Doesn't fit well into BRAM, dist RAM ok - OCC = 1 means last word is half full - = 0 means last word is full - -fifo18 --> {EOP,SOP,DATA[15:0]} - No half-word capability? Should we drop sop instead? - -Control Wires - Data into FIFO - SRC_RDY_i Upstream has data for me - DST_RDY_o I have space - Transfer occurs if SRC_RDI_i && DST_RDY_o - -Control Wires - Data out of FIFO - SRC_RDY_o I have data for downstream - DST_RDY_i Downstream has space - Transfer occurs if SRC_RDI_o && DST_RDY_i - diff --git a/usrp2/control_lib/newfifo/fifo_tb.v b/usrp2/control_lib/newfifo/fifo_tb.v deleted file mode 100644 index f561df7fa..000000000 --- a/usrp2/control_lib/newfifo/fifo_tb.v +++ /dev/null @@ -1,158 +0,0 @@ -module fifo_new_tb(); - - reg clk = 0; - reg rst = 1; - reg clear = 0; - initial #1000 rst = 0; - always #50 clk = ~clk; - - reg [31:0] f36_data = 0; - reg [1:0] f36_occ = 0; - reg f36_sof = 0, f36_eof = 0; - - wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; - reg src_rdy_f36i = 0; - wire dst_rdy_f36i; - - wire [35:0] f36_out, f36_out2; - wire src_rdy_f36o; - reg dst_rdy_f36o = 0; - - //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36 - //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 - - wire i1_sr, i1_dr; - wire i2_sr, i2_dr; - wire i3_sr, i3_dr; - reg i4_dr = 0; - wire i4_sr; - - wire [35:0] i1, i4; - wire [18:0] i2, i3; - - wire [7:0] ll_data; - wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n; - - fifo_short #(.WIDTH(36)) fifo_short1 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), - .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) ); - - fifo36_to_fifo19 fifo36_to_fifo19 - (.clk(clk),.reset(rst),.clear(clear), - .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr), - .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) ); - - fifo19_to_ll8 fifo19_to_ll8 - (.clk(clk),.reset(rst),.clear(clear), - .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr), - .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n)); - - ll8_to_fifo19 ll8_to_fifo19 - (.clk(clk),.reset(rst),.clear(clear), - .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n), - .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) ); - - fifo19_to_fifo36 fifo19_to_fifo36 - (.clk(clk),.reset(rst),.clear(clear), - .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr), - .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) ); - - task ReadFromFIFO36; - begin - $display("Read from FIFO36"); - #1 i4_dr <= 1; - while(1) - begin - while(~i4_sr) - @(posedge clk); - $display("Read: %h",i4); - @(posedge clk); - end - end - endtask // ReadFromFIFO36 - - reg [15:0] count; - task PutPacketInFIFO36; - input [31:0] data_start; - input [31:0] data_len; - begin - count <= 4; - src_rdy_f36i <= 1; - f36_data <= data_start; - f36_sof <= 1; - f36_eof <= 0; - f36_occ <= 0; - - $display("Put Packet in FIFO36"); - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - $display("PPI_FIFO36: Entered First Line"); - f36_sof <= 0; - while(count+4 < data_len) - begin - f36_data <= f36_data + 32'h01010101; - count <= count + 4; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - $display("PPI_FIFO36: Entered New Line"); - end - f36_data <= f36_data + 32'h01010101; - f36_eof <= 1; - if(count + 4 == data_len) - f36_occ <= 0; - else if(count + 3 == data_len) - f36_occ <= 3; - else if(count + 2 == data_len) - f36_occ <= 2; - else - f36_occ <= 1; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - f36_occ <= 0; - f36_eof <= 0; - f36_data <= 0; - src_rdy_f36i <= 0; - $display("PPI_FIFO36: Entered Last Line"); - end - endtask // PutPacketInFIFO36 - - initial $dumpfile("fifo_new_tb.vcd"); - initial $dumpvars(0,fifo_new_tb); - - initial - begin - @(negedge rst); - //#10000; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - ReadFromFIFO36; - end - - initial - begin - @(negedge rst); - @(posedge clk); - @(posedge clk); - PutPacketInFIFO36(32'hA0B0C0D0,12); - @(posedge clk); - @(posedge clk); - #10000; - @(posedge clk); - PutPacketInFIFO36(32'hE0F0A0B0,36); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end - - initial #20000 $finish; -endmodule // longfifo_tb diff --git a/usrp2/control_lib/newfifo/ll8_shortfifo.v b/usrp2/control_lib/newfifo/ll8_shortfifo.v deleted file mode 100644 index 39ada9a4f..000000000 --- a/usrp2/control_lib/newfifo/ll8_shortfifo.v +++ /dev/null @@ -1,13 +0,0 @@ - - -module ll8_shortfifo - (input clk, input reset, input clear, - input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o, - output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i); - - fifo_short #(.WIDTH(11)) fifo_short - (.clk(clk), .reset(reset), .clear(clear), - .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - -endmodule // ll8_shortfifo diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo19.v b/usrp2/control_lib/newfifo/ll8_to_fifo19.v deleted file mode 100644 index af3b91afb..000000000 --- a/usrp2/control_lib/newfifo/ll8_to_fifo19.v +++ /dev/null @@ -1,73 +0,0 @@ - -module ll8_to_fifo19 - (input clk, input reset, input clear, - input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, - - output [18:0] f19_data, - output f19_src_rdy_o, - input f19_dst_rdy_i ); - - localparam XFER_EMPTY = 0; - localparam XFER_HALF = 1; - localparam XFER_HALF_WRITE = 3; - - // Why anybody would use active low in an FPGA is beyond me... - wire ll_sof = ~ll_sof_n; - wire ll_eof = ~ll_eof_n; - wire ll_src_rdy = ~ll_src_rdy_n; - wire ll_dst_rdy; - assign ll_dst_rdy_n = ~ll_dst_rdy; - - wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i; - wire xfer_in = ll_src_rdy & ll_dst_rdy; - - reg hold_sof; - wire f19_sof, f19_eof, f19_occ; - - reg [1:0] state; - reg [7:0] hold_reg; - - always @(posedge clk) - if(ll_src_rdy & (state==XFER_EMPTY)) - hold_reg <= ll_data; - - always @(posedge clk) - if(ll_sof & (state==XFER_EMPTY)) - hold_sof <= 1; - else if(xfer_out) - hold_sof <= 0; - - always @(posedge clk) - if(reset | clear) - state <= XFER_EMPTY; - else - case(state) - XFER_EMPTY : - if(ll_src_rdy) - if(ll_eof) - state <= XFER_HALF_WRITE; - else - state <= XFER_HALF; - XFER_HALF : - if(ll_src_rdy & f19_dst_rdy_i) - state <= XFER_EMPTY; - XFER_HALF_WRITE : - if(f19_dst_rdy_i) - state <= XFER_EMPTY; - endcase // case (state) - - assign ll_dst_rdy = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i); - assign f19_src_rdy_o = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy); - - assign f19_sof = hold_sof | (ll_sof & (state==XFER_HALF)); - assign f19_eof = (state == XFER_HALF_WRITE) | ll_eof; - assign f19_occ = (state == XFER_HALF_WRITE); - - assign f19_data = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data}; - -endmodule // ll8_to_fifo19 - diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo36.v b/usrp2/control_lib/newfifo/ll8_to_fifo36.v deleted file mode 100644 index 108daa903..000000000 --- a/usrp2/control_lib/newfifo/ll8_to_fifo36.v +++ /dev/null @@ -1,97 +0,0 @@ - -module ll8_to_fifo36 - (input clk, input reset, input clear, - input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, - - output [35:0] f36_data, - output f36_src_rdy_o, - input f36_dst_rdy_i ); - - wire f36_write = f36_src_rdy_o & f36_dst_rdy_i; - - // Why anybody would use active low in an FPGA is beyond me... - wire ll_sof = ~ll_sof_n; - wire ll_eof = ~ll_eof_n; - wire ll_src_rdy = ~ll_src_rdy_n; - wire ll_dst_rdy; - assign ll_dst_rdy_n = ~ll_dst_rdy; - - reg f36_sof, f36_eof; - reg [1:0] f36_occ; - - - reg [2:0] state; - reg [7:0] dat0, dat1, dat2, dat3; - - always @(posedge clk) - if(ll_src_rdy & ((state==0)|f36_write)) - f36_sof <= ll_sof; - - always @(posedge clk) - if(ll_src_rdy & ((state !=4)|f36_write)) - f36_eof <= ll_eof; - - always @(posedge clk) - if(ll_eof) - f36_occ <= state[1:0] + 1; - else - f36_occ <= 0; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(ll_src_rdy) - case(state) - 0 : - if(ll_eof) - state <= 4; - else - state <= 1; - 1 : - if(ll_eof) - state <= 4; - else - state <= 2; - 2 : - if(ll_eof) - state <= 4; - else - state <= 3; - 3 : state <= 4; - 4 : - if(f36_dst_rdy_i) - if(ll_eof) - state <= 4; - else - state <= 1; - endcase // case(state) - else - if(f36_write) - state <= 0; - - always @(posedge clk) - if(ll_src_rdy & (state==3)) - dat3 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & (state==2)) - dat2 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & (state==1)) - dat1 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & ((state==0) | f36_write)) - dat0 <= ll_data; - - assign ll_dst_rdy = f36_dst_rdy_i | (state != 4); - assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess - assign f36_src_rdy_o = (state == 4); - -endmodule // ll8_to_fifo36 diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs new file mode 100644 index 000000000..7b29225ca --- /dev/null +++ b/usrp2/coregen/Makefile.srcs @@ -0,0 +1,19 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## +COREGEN_SRCS = $(abspath $(addprefix $(BASE_DIR)/../coregen/, \ +fifo_xlnx_2Kx36_2clk.v \ +fifo_xlnx_2Kx36_2clk.xco \ +fifo_xlnx_512x36_2clk.v \ +fifo_xlnx_512x36_2clk.xco \ +fifo_xlnx_64x36_2clk.v \ +fifo_xlnx_64x36_2clk.xco \ +fifo_xlnx_16x19_2clk.v \ +fifo_xlnx_16x19_2clk.xco \ +fifo_xlnx_16x40_2clk.v \ +fifo_xlnx_16x40_2clk.xco \ +)) diff --git a/usrp2/extram/Makefile.srcs b/usrp2/extram/Makefile.srcs new file mode 100644 index 000000000..90be02142 --- /dev/null +++ b/usrp2/extram/Makefile.srcs @@ -0,0 +1,10 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Extram Sources +################################################## +EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extram/, \ +wb_zbt16_b.v \ +)) diff --git a/usrp2/fifo/.gitignore b/usrp2/fifo/.gitignore new file mode 100644 index 000000000..cba7efc8e --- /dev/null +++ b/usrp2/fifo/.gitignore @@ -0,0 +1 @@ +a.out diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs new file mode 100644 index 000000000..22867da7e --- /dev/null +++ b/usrp2/fifo/Makefile.srcs @@ -0,0 +1,23 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# FIFO Sources +################################################## +FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \ +buffer_int.v \ +buffer_pool.v \ +fifo_2clock.v \ +fifo_2clock_cascade.v \ +ll8_shortfifo.v \ +fifo_short.v \ +fifo_long.v \ +fifo_cascade.v \ +fifo36_to_ll8.v \ +ll8_to_fifo36.v \ +fifo19_to_ll8.v \ +ll8_to_fifo19.v \ +fifo36_to_fifo19.v \ +fifo19_to_fifo36.v \ +)) diff --git a/usrp2/fifo/buffer_int.v b/usrp2/fifo/buffer_int.v new file mode 100644 index 000000000..b45ed3532 --- /dev/null +++ b/usrp2/fifo/buffer_int.v @@ -0,0 +1,168 @@ + +// FIFO Interface to the 2K buffer RAMs +// Read port is read-acknowledge +// FIXME do we want to be able to interleave reads and writes? + +module buffer_int + #(parameter BUF_NUM = 0, + parameter BUF_SIZE = 9) + (// Control Interface + input clk, + input rst, + input [31:0] ctrl_word, + input go, + output done, + output error, + output idle, + output [1:0] flag, + + // Buffer Interface + output en_o, + output we_o, + output reg [BUF_SIZE-1:0] addr_o, + output [31:0] dat_to_buf, + input [31:0] dat_from_buf, + + // Write FIFO Interface + input [31:0] wr_data_i, + input [3:0] wr_flags_i, + input wr_ready_i, + output wr_ready_o, + + // Read FIFO Interface + output [31:0] rd_data_o, + output [3:0] rd_flags_o, + output rd_ready_o, + input rd_ready_i + ); + + reg [31:0] ctrl_reg; + reg go_reg; + + always @(posedge clk) + go_reg <= go; + + always @(posedge clk) + if(rst) + ctrl_reg <= 0; + else + if(go & (ctrl_word[31:28] == BUF_NUM)) + ctrl_reg <= ctrl_word; + + wire [BUF_SIZE-1:0] firstline = ctrl_reg[BUF_SIZE-1:0]; + wire [BUF_SIZE-1:0] lastline = ctrl_reg[2*BUF_SIZE-1:BUF_SIZE]; + + wire read = ctrl_reg[22]; + wire write = ctrl_reg[23]; + wire clear = ctrl_reg[24]; + //wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block + //wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ? + + localparam IDLE = 3'd0; + localparam PRE_READ = 3'd1; + localparam READING = 3'd2; + localparam WRITING = 3'd3; + localparam ERROR = 3'd4; + localparam DONE = 3'd5; + + reg [2:0] state; + reg rd_sop, rd_eop; + wire wr_sop, wr_eop, wr_error; + reg [1:0] rd_occ; + wire [1:0] wr_occ; + + always @(posedge clk) + if(rst) + begin + state <= IDLE; + rd_sop <= 0; + rd_eop <= 0; + rd_occ <= 0; + end + else + if(clear) + begin + state <= IDLE; + rd_sop <= 0; + rd_eop <= 0; + rd_occ <= 0; + end + else + case(state) + IDLE : + if(go_reg & read) + begin + addr_o <= firstline; + state <= PRE_READ; + end + else if(go_reg & write) + begin + addr_o <= firstline; + state <= WRITING; + end + + PRE_READ : + begin + state <= READING; + addr_o <= addr_o + 1; + rd_occ <= 2'b00; + rd_sop <= 1; + rd_eop <= 0; + end + + READING : + if(rd_ready_i) + begin + rd_sop <= 0; + addr_o <= addr_o + 1; + if(addr_o == lastline) + begin + rd_eop <= 1; + // FIXME assign occ here + rd_occ <= 0; + end + else + rd_eop <= 0; + if(rd_eop) + state <= DONE; + end + + WRITING : + begin + if(wr_ready_i) + begin + addr_o <= addr_o + 1; + if(wr_error) + begin + state <= ERROR; + // Save OCC flags here + end + else if((addr_o == lastline)||wr_eop) + state <= DONE; + end // if (wr_ready_i) + end // case: WRITING + + endcase // case(state) + + assign dat_to_buf = wr_data_i; + assign rd_data_o = dat_from_buf; + + assign rd_flags_o = { rd_occ[1:0], rd_eop, rd_sop }; + assign rd_ready_o = (state == READING); + + assign wr_sop = wr_flags_i[0]; + assign wr_eop = wr_flags_i[1]; + assign wr_occ = wr_flags_i[3:2]; + assign wr_error = wr_sop & wr_eop; + assign wr_ready_o = (state == WRITING); + + assign we_o = (state == WRITING); + //assign we_o = (state == WRITING) && wr_ready_i; // always write to avoid timing issue + + assign en_o = ~((state==READING)& ~rd_ready_i); // FIXME potential critical path + + assign done = (state == DONE); + assign error = (state == ERROR); + assign idle = (state == IDLE); + +endmodule // buffer_int diff --git a/usrp2/fifo/buffer_int_tb.v b/usrp2/fifo/buffer_int_tb.v new file mode 100644 index 000000000..df54dcc0b --- /dev/null +++ b/usrp2/fifo/buffer_int_tb.v @@ -0,0 +1,418 @@ + +module buffer_int_tb (); + + reg clk = 0; + reg rst = 1; + + initial #100 rst = 0; + always #5 clk = ~clk; + + wire en, we; + wire [8:0] addr; + wire [31:0] fifo2buf, buf2fifo; + + wire [31:0] rd_data_o; + wire [3:0] rd_flags_o; + wire rd_sop_o, rd_eop_o; + reg rd_error_i = 0, rd_read_i = 0; + + reg [31:0] wr_data_i = 0; + wire [3:0] wr_flags_i; + reg wr_eop_i = 0, wr_sop_i = 0; + reg wr_write_i = 0; + wire wr_ready_o, wr_full_o; + + reg clear = 0, write = 0, read = 0; + reg [8:0] firstline = 0, lastline = 0; + wire [3:0] step = 1; + wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline}; + reg go = 0; + wire done, error; + + assign wr_flags_i = {2'b00, wr_eop_i, wr_sop_i}; + assign rd_sop_o = rd_flags_o[0]; + assign rd_eop_o = rd_flags_o[1]; + + buffer_int buffer_int + (.clk(clk),.rst(rst), + .ctrl_word(ctrl_word),.go(go), + .done(done),.error(error), + + // Buffer Interface + .en_o(en),.we_o(we),.addr_o(addr), + .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo), + + // Write FIFO Interface + .wr_data_i(wr_data_i), .wr_flags_i(wr_flags_i), .wr_write_i(wr_write_i), .wr_ready_o(wr_ready_o), + + // Read FIFO Interface + .rd_data_o(rd_data_o), .rd_flags_o(rd_flags_o), .rd_ready_o(rd_ready_o), .rd_read_i(rd_read_i) + ); + + reg ram_en = 0, ram_we = 0; + reg [8:0] ram_addr = 0; + reg [31:0] ram_data = 0; + + ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port + (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(), + .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) ); + + initial + begin + @(negedge rst); + @(posedge clk); + FillRAM; + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing full read, no wait states."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(6,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing full read, 2 wait states."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(6,2); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 0 wait states, then nothing after last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(3,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 0 wait states, then done at same time as last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(2,0); + ReadALine; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 3 wait states, then error at same time as last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(2,3); + rd_error_i <= 1; + ReadALine; + rd_error_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(500,511); + $display("Testing full read, to the end of the buffer."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(12,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,511); + $display("Testing full read, start to end of the buffer."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(512,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(505,3); + $display("Testing full read, wraparound"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(11,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(10,15); + $display("Testing Full Write, no wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,72); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(18,23); + $display("Testing Full Write, 1 wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,1,101); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(27,40); + $display("Testing Partial Write, 0 wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,201); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(45,200); + $display("Testing Partial Write, 0 wait states, then done and write simultaneously"); + while(!wr_ready_o) + @(posedge clk); + wr_sop_i <= 1; wr_eop_i <= 0; + WriteLines(6,0,301); + wr_sop_i <= 0; wr_eop_i <= 1; + WriteALine(400); + wr_sop_i <= 0; wr_eop_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(55,200); + $display("Testing Partial Write, 0 wait states, then error"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,501); + wr_sop_i <= 1; wr_eop_i <= 1; + WriteALine(400); + @(posedge clk); + repeat (10) + @(posedge clk); + wr_sop_i <= 0; wr_eop_i <= 0; + + ResetBuffer; + SetBufferRead(0,82); + $display("Testing read after all the writes"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(83,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(508,4); + $display("Testing wraparound write"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(9,0,601); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(506,10); + $display("Reading wraparound write"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(17,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(0,511); + $display("Testing Whole Buffer write"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(512,0,1000); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,511); + $display("Reading Whole Buffer write"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(512,0); + repeat (10) + @(posedge clk); + + /* + ResetBuffer; + SetBufferWrite(5,10); + $display("Testing Write Too Many"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(12,0,2000); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,15); + $display("Reading back Write Too Many"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(16,0); + repeat (10) + @(posedge clk); + */ + ResetBuffer; + SetBufferWrite(15,20); + $display("Testing Write One Less Than Full"); + while(!wr_ready_o) + @(posedge clk); + wr_sop_i <= 1; wr_eop_i <= 0; + WriteALine(400); + wr_sop_i <= 0; wr_eop_i <= 0; + WriteLines(3,0,2000); + wr_sop_i <= 0; wr_eop_i <= 1; + WriteALine(400); + wr_sop_i <= 0; wr_eop_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(13,22); + $display("Reading back Write One Less Than Full"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(10,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + repeat(100) + @(posedge clk); + $finish; + end + + always @(posedge clk) + if(rd_read_i == 1'd1) + $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_data_o, rd_sop_o, rd_eop_o); + + always @(posedge clk) + if(wr_write_i == 1'd1) + $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_data_i, wr_ready_o, wr_full_o); + + initial begin + $dumpfile("buffer_int_tb.lxt"); + $dumpvars(0,buffer_int_tb); + end + + task FillRAM; + begin + ram_addr <= 0; + ram_data <= 0; + @(posedge clk); + ram_en <= 1; + ram_we <= 1; + @(posedge clk); + repeat (511) + begin + ram_addr <= ram_addr + 1; + ram_data <= ram_data + 1; + ram_en <= 1; + ram_we <= 1; + @(posedge clk); + end + ram_en <= 0; + ram_we <= 0; + @(posedge clk); + $display("Filled the RAM"); + end + endtask // FillRAM + + task ResetBuffer; + begin + clear <= 1; read <= 0; write <= 0; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Reset"); + end + endtask // ClearBuffer + + task SetBufferWrite; + input [8:0] start; + input [8:0] stop; + begin + clear <= 0; read <= 0; write <= 1; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Write"); + end + endtask // SetBufferWrite + + task SetBufferRead; + input [8:0] start; + input [8:0] stop; + begin + clear <= 0; read <= 1; write <= 0; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Read"); + end + endtask // SetBufferRead + + task ReadALine; + begin + while(~rd_ready_o) + @(posedge clk); + #1 rd_read_i <= 1; + @(posedge clk); + rd_read_i <= 0; + end + endtask // ReadALine + + task ReadLines; + input [9:0] lines; + input [7:0] wait_states; + begin + $display("Read Lines: Number %d, Wait States %d",lines,wait_states); + repeat (lines) + begin + ReadALine; + repeat (wait_states) + @(posedge clk); + end + end + endtask // ReadLines + + task WriteALine; + input [31:0] value; + begin + while(~wr_ready_o) + @(posedge clk); + #1 wr_write_i <= 1; + wr_data_i <= value; + @(posedge clk); + wr_write_i <= 0; + end + endtask // WriteALine + + task WriteLines; + input [9:0] lines; + input [7:0] wait_states; + input [31:0] value; + begin + $display("Write Lines: Number %d, Wait States %d",lines,wait_states); + repeat(lines) + begin + value <= value + 1; + WriteALine(value); + repeat(wait_states) + @(posedge clk); + end + end + endtask // WriteLines + +endmodule // buffer_int_tb diff --git a/usrp2/fifo/buffer_pool.v b/usrp2/fifo/buffer_pool.v new file mode 100644 index 000000000..41ac1deb3 --- /dev/null +++ b/usrp2/fifo/buffer_pool.v @@ -0,0 +1,283 @@ + +// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer +// is a dual-ported RAM. Port A on each of them is indirectly connected +// to the wishbone bus by a bridge. Port B may be connected any one of the +// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The wishbone bus +// provides access to all 8 buffers, and also controls the connections +// between the ports and the buffers, allocating them as needed. + +// wb_adr is 16 bits -- +// bits 13:11 select which buffer +// bits 10:2 select line in buffer +// bits 1:0 are unused (32-bit access only) + +// BUF_SIZE is in address lines (i.e. log2 of number of lines). +// For S3 it should be 9 (512 words, 2KB) +// For V5 it should be at least 10 (1024 words, 4KB) or 11 (2048 words, 8KB) + +module buffer_pool + #(parameter BUF_SIZE = 9, + parameter SET_ADDR = 64) + (input wb_clk_i, + input wb_rst_i, + input wb_we_i, + input wb_stb_i, + input [15:0] wb_adr_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output reg wb_ack_o, + output wb_err_o, + output wb_rty_o, + + input stream_clk, + input stream_rst, + + input set_stb, input [7:0] set_addr, input [31:0] set_data, + output [31:0] status, + output sys_int_o, + + output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3, + output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7, + + // Write Interfaces + input [31:0] wr0_data_i, input [3:0] wr0_flags_i, input wr0_ready_i, output wr0_ready_o, + input [31:0] wr1_data_i, input [3:0] wr1_flags_i, input wr1_ready_i, output wr1_ready_o, + input [31:0] wr2_data_i, input [3:0] wr2_flags_i, input wr2_ready_i, output wr2_ready_o, + input [31:0] wr3_data_i, input [3:0] wr3_flags_i, input wr3_ready_i, output wr3_ready_o, + + // Read Interfaces + output [31:0] rd0_data_o, output [3:0] rd0_flags_o, output rd0_ready_o, input rd0_ready_i, + output [31:0] rd1_data_o, output [3:0] rd1_flags_o, output rd1_ready_o, input rd1_ready_i, + output [31:0] rd2_data_o, output [3:0] rd2_flags_o, output rd2_ready_o, input rd2_ready_i, + output [31:0] rd3_data_o, output [3:0] rd3_flags_o, output rd3_ready_o, input rd3_ready_i + ); + + wire [7:0] sel_a; + + wire [BUF_SIZE-1:0] buf_addra = wb_adr_i[BUF_SIZE+1:2]; // ignore address 1:0, 32-bit access only + wire [2:0] which_buf = wb_adr_i[BUF_SIZE+4:BUF_SIZE+2]; // address 15:14 selects the buffer pool + + decoder_3_8 dec(.sel(which_buf),.res(sel_a)); + + genvar i; + + wire go; + + reg [2:0] port[0:7]; + reg [3:0] read_src[0:3]; + reg [3:0] write_src[0:3]; + + wire [7:0] done; + wire [7:0] error; + wire [7:0] idle; + + wire [31:0] buf_doa[0:7]; + + wire [7:0] buf_enb; + wire [7:0] buf_web; + wire [BUF_SIZE-1:0] buf_addrb[0:7]; + wire [31:0] buf_dib[0:7]; + wire [31:0] buf_dob[0:7]; + + wire [31:0] wr_data_i[0:7]; + wire [3:0] wr_flags_i[0:7]; + wire [7:0] wr_ready_i; + wire [7:0] wr_ready_o; + + wire [31:0] rd_data_o[0:7]; + wire [3:0] rd_flags_o[0:7]; + wire [7:0] rd_ready_o; + wire [7:0] rd_ready_i; + + assign status = {8'd0,idle[7:0],error[7:0],done[7:0]}; + + assign s0 = buf_addrb[0]; + assign s1 = buf_addrb[1]; + assign s2 = buf_addrb[2]; + assign s3 = buf_addrb[3]; + assign s4 = buf_addrb[4]; + assign s5 = buf_addrb[5]; + assign s6 = buf_addrb[6]; + assign s7 = buf_addrb[7]; + + wire [31:0] fifo_ctrl; + setting_reg #(.my_addr(SET_ADDR)) + sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data), + .out(fifo_ctrl),.changed(go)); + + integer k; + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<8;k=k+1) + port[k] <= 4; // disabled + else + for(k=0;k<8;k=k+1) + if(go & (fifo_ctrl[31:28]==k)) + port[k] <= fifo_ctrl[27:25]; + + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<4;k=k+1) + read_src[k] <= 8; // disabled + else + for(k=0;k<4;k=k+1) + if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k)) + read_src[k] <= fifo_ctrl[31:28]; + + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<4;k=k+1) + write_src[k] <= 8; // disabled + else + for(k=0;k<4;k=k+1) + if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k)) + write_src[k] <= fifo_ctrl[31:28]; + + generate + for(i=0;i<8;i=i+1) + begin : gen_buffer + RAMB16_S36_S36 dpram + (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), + .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i), + .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0), + .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) ); + +/* + ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer + (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i), + .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]), + .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]), + .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); + + */ + + buffer_int #(.BUF_NUM(i),.BUF_SIZE(BUF_SIZE)) buffer_int + (.clk(stream_clk),.rst(stream_rst), + .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)), + .done(done[i]),.error(error[i]),.idle(idle[i]), + .en_o(buf_enb[i]), + .we_o(buf_web[i]), + .addr_o(buf_addrb[i]), + .dat_to_buf(buf_dib[i]), + .dat_from_buf(buf_dob[i]), + .wr_data_i(wr_data_i[i]), + .wr_flags_i(wr_flags_i[i]), + .wr_ready_i(wr_ready_i[i]), + .wr_ready_o(wr_ready_o[i]), + .rd_data_o(rd_data_o[i]), + .rd_flags_o(rd_flags_o[i]), + .rd_ready_o(rd_ready_o[i]), + .rd_ready_i(rd_ready_i[i]) ); + mux4 #(.WIDTH(37)) + mux4_wr (.en(~port[i][2]),.sel(port[i][1:0]), + .i0({wr0_data_i,wr0_flags_i,wr0_ready_i}), + .i1({wr1_data_i,wr1_flags_i,wr1_ready_i}), + .i2({wr2_data_i,wr2_flags_i,wr2_ready_i}), + .i3({wr3_data_i,wr3_flags_i,wr3_ready_i}), + .o({wr_data_i[i],wr_flags_i[i],wr_ready_i[i]}) ); + mux4 #(.WIDTH(1)) + mux4_rd (.en(~port[i][2]),.sel(port[i][1:0]), + .i0(rd0_ready_i),.i1(rd1_ready_i),.i2(rd2_ready_i),.i3(rd3_ready_i), + .o(rd_ready_i[i])); + end // block: gen_buffer + endgenerate + + //---------------------------------------------------------------------- + // Wishbone Outputs + + // Use the following lines if ram output and mux can be made fast enough + + assign wb_err_o = 1'b0; // Unused for now + assign wb_rty_o = 1'b0; // Unused for now + + always @(posedge wb_clk_i) + wb_ack_o <= wb_stb_i & ~wb_ack_o; + assign wb_dat_o = buf_doa[which_buf]; + + // Use this if we can't make the RAM+MUX fast enough + // reg [31:0] wb_dat_o_reg; + // reg stb_d1; + + // always @(posedge wb_clk_i) + // begin + // wb_dat_o_reg <= buf_doa[which_buf]; + // stb_d1 <= wb_stb_i; + // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i); + // end + //assign wb_dat_o = wb_dat_o_reg; + + mux8 #(.WIDTH(1)) + mux8_wr0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), + .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), + .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), + .o(wr0_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), + .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), + .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), + .o(wr1_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), + .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), + .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), + .o(wr2_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), + .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), + .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]), + .o(wr3_ready_o)); + + mux8 #(.WIDTH(37)) + mux8_rd0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), + .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), + .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), + .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), + .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), + .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), + .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), + .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), + .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), + .o({rd0_data_o,rd0_flags_o,rd0_ready_o})); + + mux8 #(.WIDTH(37)) + mux8_rd1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), + .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), + .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), + .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), + .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), + .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), + .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), + .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), + .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), + .o({rd1_data_o,rd1_flags_o,rd1_ready_o})); + + mux8 #(.WIDTH(37)) + mux8_rd2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), + .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), + .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), + .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), + .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), + .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), + .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), + .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), + .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), + .o({rd2_data_o,rd2_flags_o,rd2_ready_o})); + + mux8 #(.WIDTH(37)) + mux8_rd3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), + .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}), + .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}), + .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}), + .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}), + .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}), + .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}), + .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}), + .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}), + .o({rd3_data_o,rd3_flags_o,rd3_ready_o})); + + assign sys_int_o = (|error) | (|done); + +endmodule // buffer_pool diff --git a/usrp2/fifo/buffer_pool_tb.v b/usrp2/fifo/buffer_pool_tb.v new file mode 100644 index 000000000..91a01d268 --- /dev/null +++ b/usrp2/fifo/buffer_pool_tb.v @@ -0,0 +1,58 @@ + +module buffer_pool_tb(); + + wire wb_clk_i; + wire wb_rst_i; + wire wb_we_i; + wire wb_stb_i; + wire [15:0] wb_adr_i; + wire [31:0] wb_dat_i; + wire [31:0] wb_dat_o; + wire wb_ack_o; + wire wb_err_o; + wire wb_rty_o; + + wire stream_clk, stream_rst; + + wire set_stb; + wire [7:0] set_addr; + wire [31:0] set_data; + + wire [31:0] wr0_data, wr1_data, wr2_data, wr3_data; + wire [31:0] rd0_data, rd1_data, rd2_data, rd3_data; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire wr0_ready, wr1_ready, wr2_ready, wr3_ready; + wire rd0_ready, rd1_ready, rd2_ready, rd3_ready; + wire wr0_write, wr1_write, wr2_write, wr3_write; + wire rd0_read, rd1_read, rd2_read, rd3_read; + + buffer_pool dut + (.wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wb_we_i(wb_we_i), + .wb_stb_i(wb_stb_i), + .wb_adr_i(wb_adr_i), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_ack_o(wb_ack_o), + .wb_err_o(wb_err_o), + .wb_rty_o(wb_rty_o), + + .stream_clk(stream_clk), + .stream_rst(stream_rst), + + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + + .wr0_data_i(wr0_data), .wr0_write_i(wr0_write), .wr0_flags_i(wr0_flags), .wr0_ready_o(wr0_ready), + .wr1_data_i(wr1_data), .wr1_write_i(wr1_write), .wr1_flags_i(wr1_flags), .wr1_ready_o(wr1_ready), + .wr2_data_i(wr2_data), .wr2_write_i(wr2_write), .wr2_flags_i(wr2_flags), .wr2_ready_o(wr2_ready), + .wr3_data_i(wr3_data), .wr3_write_i(wr3_write), .wr3_flags_i(wr3_flags), .wr3_ready_o(wr3_ready), + + .rd0_data_o(rd0_data), .rd0_read_i(rd0_read), .rd0_flags_o(rd0_flags), .rd0_ready_o(rd0_ready), + .rd1_data_o(rd1_data), .rd1_read_i(rd1_read), .rd1_flags_o(rd1_flags), .rd1_ready_o(rd1_ready), + .rd2_data_o(rd2_data), .rd2_read_i(rd2_read), .rd2_flags_o(rd2_flags), .rd2_ready_o(rd2_ready), + .rd3_data_o(rd3_data), .rd3_read_i(rd3_read), .rd3_flags_o(rd3_flags), .rd3_ready_o(rd3_ready) + ); + +endmodule // buffer_pool_tb diff --git a/usrp2/fifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v new file mode 100644 index 000000000..5f9aeff9b --- /dev/null +++ b/usrp2/fifo/fifo19_to_fifo36.v @@ -0,0 +1,76 @@ + +module fifo19_to_fifo36 + (input clk, input reset, input clear, + input [18:0] f19_datain, + input f19_src_rdy_i, + output f19_dst_rdy_o, + + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i, + output [31:0] debug + ); + + reg f36_sof, f36_eof, f36_occ; + + reg [1:0] state; + reg [15:0] dat0, dat1; + + wire f19_sof = f19_datain[16]; + wire f19_eof = f19_datain[17]; + wire f19_occ = f19_datain[18]; + + wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; + + always @(posedge clk) + if(f19_src_rdy_i & ((state==0)|xfer_out)) + f36_sof <= f19_sof; + + always @(posedge clk) + if(f19_src_rdy_i & ((state != 2)|xfer_out)) + f36_eof <= f19_eof; + + always @(posedge clk) // FIXME check this + if(f19_eof) + f36_occ <= {state[0],f19_occ}; + else + f36_occ <= 0; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(f19_src_rdy_i) + case(state) + 0 : + if(f19_eof) + state <= 2; + else + state <= 1; + 1 : + state <= 2; + 2 : + if(xfer_out) + if(~f19_eof) + state <= 1; + // remain in state 2 if we are at eof + endcase // case(state) + else + if(xfer_out) + state <= 0; + + always @(posedge clk) + if(f19_src_rdy_i & (state==1)) + dat1 <= f19_datain; + + always @(posedge clk) + if(f19_src_rdy_i & ((state==0) | xfer_out)) + dat0 <= f19_datain; + + assign f19_dst_rdy_o = xfer_out | (state != 2); + assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; + assign f36_src_rdy_o = (state == 2); + + assign debug = state; + +endmodule // fifo19_to_fifo36 diff --git a/usrp2/fifo/fifo19_to_ll8.v b/usrp2/fifo/fifo19_to_ll8.v new file mode 100644 index 000000000..4707f7523 --- /dev/null +++ b/usrp2/fifo/fifo19_to_ll8.v @@ -0,0 +1,53 @@ + +module fifo19_to_ll8 + (input clk, input reset, input clear, + input [18:0] f19_data, + input f19_src_rdy_i, + output f19_dst_rdy_o, + + output reg [7:0] ll_data, + output ll_sof_n, + output ll_eof_n, + output ll_src_rdy_n, + input ll_dst_rdy_n); + + wire ll_sof, ll_eof, ll_src_rdy; + assign ll_sof_n = ~ll_sof; + assign ll_eof_n = ~ll_eof; + assign ll_src_rdy_n = ~ll_src_rdy; + wire ll_dst_rdy = ~ll_dst_rdy_n; + + wire f19_sof = f19_data[16]; + wire f19_eof = f19_data[17]; + wire f19_occ = f19_data[18]; + + wire advance, end_early; + reg state; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(advance) + if(ll_eof) + state <= 0; + else + state <= state + 1; + + always @* + case(state) + 0 : ll_data = f19_data[15:8]; + 1 : ll_data = f19_data[7:0]; + default : ll_data = f19_data[15:8]; + endcase // case (state) + + assign ll_sof = (state==0) & f19_sof; + assign ll_eof = f19_eof & ((f19_occ==1)|(state==1)); + + assign ll_src_rdy = f19_src_rdy_i; + + assign advance = ll_src_rdy & ll_dst_rdy; + assign f19_dst_rdy_o = advance & ((state==1)|ll_eof); + +endmodule // fifo19_to_ll8 + diff --git a/usrp2/fifo/fifo36_to_fifo18.v b/usrp2/fifo/fifo36_to_fifo18.v new file mode 100644 index 000000000..b636ab9ca --- /dev/null +++ b/usrp2/fifo/fifo36_to_fifo18.v @@ -0,0 +1,40 @@ + +module fifo36_to_fifo18 + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [17:0] f18_dataout, + output f18_src_rdy_o, + input f18_dst_rdy_i ); + + wire f36_sof = f36_datain[32]; + wire f36_eof = f36_datain[33]; + wire f36_occ = f36_datain[35:34]; + + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + assign f18_dataout[16] = phase ? 0 : f36_sof; + assign f18_dataout[17] = phase ? f36_eof : half_line; + + assign f18_src_rdy_o = f36_src_rdy_i; + assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i; + + wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + + always @(posedge clk) + if(reset) + phase <= 0; + else if(f36_xfer) + phase <= 0; + else if(f18_xfer) + phase <= 1; + + +endmodule // fifo36_to_fifo18 + diff --git a/usrp2/fifo/fifo36_to_fifo19.v b/usrp2/fifo/fifo36_to_fifo19.v new file mode 100644 index 000000000..de249aaeb --- /dev/null +++ b/usrp2/fifo/fifo36_to_fifo19.v @@ -0,0 +1,41 @@ + +module fifo36_to_fifo19 + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [18:0] f19_dataout, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + + wire f36_sof = f36_datain[32]; + wire f36_eof = f36_datain[33]; + wire f36_occ = f36_datain[35:34]; + + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + assign f19_dataout[16] = phase ? 0 : f36_sof; + assign f19_dataout[17] = phase ? f36_eof : half_line; + assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); + + assign f19_src_rdy_o = f36_src_rdy_i; + assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; + + wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + + always @(posedge clk) + if(reset) + phase <= 0; + else if(f36_xfer) + phase <= 0; + else if(f19_xfer) + phase <= 1; + + +endmodule // fifo36_to_fifo19 + diff --git a/usrp2/fifo/fifo36_to_ll8.v b/usrp2/fifo/fifo36_to_ll8.v new file mode 100644 index 000000000..0dee1dfc6 --- /dev/null +++ b/usrp2/fifo/fifo36_to_ll8.v @@ -0,0 +1,60 @@ + +module fifo36_to_ll8 + (input clk, input reset, input clear, + input [35:0] f36_data, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output reg [7:0] ll_data, + output ll_sof_n, + output ll_eof_n, + output ll_src_rdy_n, + input ll_dst_rdy_n, + + output [31:0] debug); + + wire ll_sof, ll_eof, ll_src_rdy; + assign ll_sof_n = ~ll_sof; + assign ll_eof_n = ~ll_eof; + assign ll_src_rdy_n = ~ll_src_rdy; + wire ll_dst_rdy = ~ll_dst_rdy_n; + + wire f36_sof = f36_data[32]; + wire f36_eof = f36_data[33]; + wire f36_occ = f36_data[35:34]; + wire advance, end_early; + reg [1:0] state; + assign debug = {29'b0,state}; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(advance) + if(ll_eof) + state <= 0; + else + state <= state + 1; + + always @* + case(state) + 0 : ll_data = f36_data[31:24]; + 1 : ll_data = f36_data[23:16]; + 2 : ll_data = f36_data[15:8]; + 3 : ll_data = f36_data[7:0]; + default : ll_data = f36_data[31:24]; + endcase // case (state) + + assign ll_sof = (state==0) & f36_sof; + assign ll_eof = f36_eof & (((state==0)&(f36_occ==1)) | + ((state==1)&(f36_occ==2)) | + ((state==2)&(f36_occ==3)) | + (state==3)); + + assign ll_src_rdy = f36_src_rdy_i; + + assign advance = ll_src_rdy & ll_dst_rdy; + assign f36_dst_rdy_o = advance & ((state==3)|ll_eof); + assign debug = state; + +endmodule // ll8_to_fifo36 diff --git a/usrp2/fifo/fifo_2clock.v b/usrp2/fifo/fifo_2clock.v new file mode 100644 index 000000000..34c85ccb4 --- /dev/null +++ b/usrp2/fifo/fifo_2clock.v @@ -0,0 +1,117 @@ + +// FIXME ignores the AWIDTH (fifo size) parameter + +module fifo_2clock + #(parameter WIDTH=36, SIZE=6) + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + input arst); + + wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels + wire full, empty, write, read; + + assign dst_rdy_o = ~full; + assign src_rdy_o = ~empty; + assign write = src_rdy_i & dst_rdy_o; + assign read = src_rdy_o & dst_rdy_i; + + generate + if(WIDTH==36) + if(SIZE==9) + fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==11) + fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==6) + fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else + fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==19)|(WIDTH==18)) + if(SIZE==4) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + endgenerate + + assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; + assign space = ((1< clear $end +$var wire 1 ? clk $end +$var wire 36 @ datain [35:0] $end +$var wire 36 A dataout [35:0] $end +$var wire 1 $ dst_rdy_i $end +$var wire 1 ! dst_rdy_o $end +$var wire 1 B read $end +$var wire 1 C reset $end +$var wire 1 D src_rdy_i $end +$var wire 1 % src_rdy_o $end +$var wire 1 E write $end +$var reg 4 F a [3:0] $end +$var reg 1 G empty $end +$var reg 1 H full $end +$var reg 5 I occupied [4:0] $end +$var reg 5 J space [4:0] $end +$scope begin gen_srl16[0] $end +$scope module srl16e $end +$var wire 1 K A0 $end +$var wire 1 L A1 $end +$var wire 1 M A2 $end +$var wire 1 N A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 O D $end +$var wire 1 P Q $end +$var reg 16 Q data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[1] $end +$scope module srl16e $end +$var wire 1 R A0 $end +$var wire 1 S A1 $end +$var wire 1 T A2 $end +$var wire 1 U A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 V D $end +$var wire 1 W Q $end +$var reg 16 X data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[2] $end +$scope module srl16e $end +$var wire 1 Y A0 $end +$var wire 1 Z A1 $end +$var wire 1 [ A2 $end +$var wire 1 \ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ] D $end +$var wire 1 ^ Q $end +$var reg 16 _ data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[3] $end +$scope module srl16e $end +$var wire 1 ` A0 $end +$var wire 1 a A1 $end +$var wire 1 b A2 $end +$var wire 1 c A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 d D $end +$var wire 1 e Q $end +$var reg 16 f data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[4] $end +$scope module srl16e $end +$var wire 1 g A0 $end +$var wire 1 h A1 $end +$var wire 1 i A2 $end +$var wire 1 j A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 k D $end +$var wire 1 l Q $end +$var reg 16 m data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[5] $end +$scope module srl16e $end +$var wire 1 n A0 $end +$var wire 1 o A1 $end +$var wire 1 p A2 $end +$var wire 1 q A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 r D $end +$var wire 1 s Q $end +$var reg 16 t data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[6] $end +$scope module srl16e $end +$var wire 1 u A0 $end +$var wire 1 v A1 $end +$var wire 1 w A2 $end +$var wire 1 x A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 y D $end +$var wire 1 z Q $end +$var reg 16 { data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[7] $end +$scope module srl16e $end +$var wire 1 | A0 $end +$var wire 1 } A1 $end +$var wire 1 ~ A2 $end +$var wire 1 !" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 "" D $end +$var wire 1 #" Q $end +$var reg 16 $" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[8] $end +$scope module srl16e $end +$var wire 1 %" A0 $end +$var wire 1 &" A1 $end +$var wire 1 '" A2 $end +$var wire 1 (" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 )" D $end +$var wire 1 *" Q $end +$var reg 16 +" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[9] $end +$scope module srl16e $end +$var wire 1 ," A0 $end +$var wire 1 -" A1 $end +$var wire 1 ." A2 $end +$var wire 1 /" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 0" D $end +$var wire 1 1" Q $end +$var reg 16 2" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[10] $end +$scope module srl16e $end +$var wire 1 3" A0 $end +$var wire 1 4" A1 $end +$var wire 1 5" A2 $end +$var wire 1 6" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 7" D $end +$var wire 1 8" Q $end +$var reg 16 9" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[11] $end +$scope module srl16e $end +$var wire 1 :" A0 $end +$var wire 1 ;" A1 $end +$var wire 1 <" A2 $end +$var wire 1 =" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 >" D $end +$var wire 1 ?" Q $end +$var reg 16 @" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[12] $end +$scope module srl16e $end +$var wire 1 A" A0 $end +$var wire 1 B" A1 $end +$var wire 1 C" A2 $end +$var wire 1 D" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 E" D $end +$var wire 1 F" Q $end +$var reg 16 G" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[13] $end +$scope module srl16e $end +$var wire 1 H" A0 $end +$var wire 1 I" A1 $end +$var wire 1 J" A2 $end +$var wire 1 K" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 L" D $end +$var wire 1 M" Q $end +$var reg 16 N" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[14] $end +$scope module srl16e $end +$var wire 1 O" A0 $end +$var wire 1 P" A1 $end +$var wire 1 Q" A2 $end +$var wire 1 R" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 S" D $end +$var wire 1 T" Q $end +$var reg 16 U" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[15] $end +$scope module srl16e $end +$var wire 1 V" A0 $end +$var wire 1 W" A1 $end +$var wire 1 X" A2 $end +$var wire 1 Y" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 Z" D $end +$var wire 1 [" Q $end +$var reg 16 \" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[16] $end +$scope module srl16e $end +$var wire 1 ]" A0 $end +$var wire 1 ^" A1 $end +$var wire 1 _" A2 $end +$var wire 1 `" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 a" D $end +$var wire 1 b" Q $end +$var reg 16 c" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[17] $end +$scope module srl16e $end +$var wire 1 d" A0 $end +$var wire 1 e" A1 $end +$var wire 1 f" A2 $end +$var wire 1 g" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 h" D $end +$var wire 1 i" Q $end +$var reg 16 j" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[18] $end +$scope module srl16e $end +$var wire 1 k" A0 $end +$var wire 1 l" A1 $end +$var wire 1 m" A2 $end +$var wire 1 n" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 o" D $end +$var wire 1 p" Q $end +$var reg 16 q" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[19] $end +$scope module srl16e $end +$var wire 1 r" A0 $end +$var wire 1 s" A1 $end +$var wire 1 t" A2 $end +$var wire 1 u" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 v" D $end +$var wire 1 w" Q $end +$var reg 16 x" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[20] $end +$scope module srl16e $end +$var wire 1 y" A0 $end +$var wire 1 z" A1 $end +$var wire 1 {" A2 $end +$var wire 1 |" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 }" D $end +$var wire 1 ~" Q $end +$var reg 16 !# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[21] $end +$scope module srl16e $end +$var wire 1 "# A0 $end +$var wire 1 ## A1 $end +$var wire 1 $# A2 $end +$var wire 1 %# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 &# D $end +$var wire 1 '# Q $end +$var reg 16 (# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[22] $end +$scope module srl16e $end +$var wire 1 )# A0 $end +$var wire 1 *# A1 $end +$var wire 1 +# A2 $end +$var wire 1 ,# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 -# D $end +$var wire 1 .# Q $end +$var reg 16 /# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[23] $end +$scope module srl16e $end +$var wire 1 0# A0 $end +$var wire 1 1# A1 $end +$var wire 1 2# A2 $end +$var wire 1 3# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 4# D $end +$var wire 1 5# Q $end +$var reg 16 6# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[24] $end +$scope module srl16e $end +$var wire 1 7# A0 $end +$var wire 1 8# A1 $end +$var wire 1 9# A2 $end +$var wire 1 :# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ;# D $end +$var wire 1 <# Q $end +$var reg 16 =# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[25] $end +$scope module srl16e $end +$var wire 1 ># A0 $end +$var wire 1 ?# A1 $end +$var wire 1 @# A2 $end +$var wire 1 A# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 B# D $end +$var wire 1 C# Q $end +$var reg 16 D# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[26] $end +$scope module srl16e $end +$var wire 1 E# A0 $end +$var wire 1 F# A1 $end +$var wire 1 G# A2 $end +$var wire 1 H# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 I# D $end +$var wire 1 J# Q $end +$var reg 16 K# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[27] $end +$scope module srl16e $end +$var wire 1 L# A0 $end +$var wire 1 M# A1 $end +$var wire 1 N# A2 $end +$var wire 1 O# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 P# D $end +$var wire 1 Q# Q $end +$var reg 16 R# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[28] $end +$scope module srl16e $end +$var wire 1 S# A0 $end +$var wire 1 T# A1 $end +$var wire 1 U# A2 $end +$var wire 1 V# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 W# D $end +$var wire 1 X# Q $end +$var reg 16 Y# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[29] $end +$scope module srl16e $end +$var wire 1 Z# A0 $end +$var wire 1 [# A1 $end +$var wire 1 \# A2 $end +$var wire 1 ]# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ^# D $end +$var wire 1 _# Q $end +$var reg 16 `# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[30] $end +$scope module srl16e $end +$var wire 1 a# A0 $end +$var wire 1 b# A1 $end +$var wire 1 c# A2 $end +$var wire 1 d# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 e# D $end +$var wire 1 f# Q $end +$var reg 16 g# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[31] $end +$scope module srl16e $end +$var wire 1 h# A0 $end +$var wire 1 i# A1 $end +$var wire 1 j# A2 $end +$var wire 1 k# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 l# D $end +$var wire 1 m# Q $end +$var reg 16 n# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[32] $end +$scope module srl16e $end +$var wire 1 o# A0 $end +$var wire 1 p# A1 $end +$var wire 1 q# A2 $end +$var wire 1 r# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 s# D $end +$var wire 1 t# Q $end +$var reg 16 u# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[33] $end +$scope module srl16e $end +$var wire 1 v# A0 $end +$var wire 1 w# A1 $end +$var wire 1 x# A2 $end +$var wire 1 y# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 z# D $end +$var wire 1 {# Q $end +$var reg 16 |# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[34] $end +$scope module srl16e $end +$var wire 1 }# A0 $end +$var wire 1 ~# A1 $end +$var wire 1 !$ A2 $end +$var wire 1 "$ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 #$ D $end +$var wire 1 $$ Q $end +$var reg 16 %$ data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[35] $end +$scope module srl16e $end +$var wire 1 &$ A0 $end +$var wire 1 '$ A1 $end +$var wire 1 ($ A2 $end +$var wire 1 )$ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 *$ D $end +$var wire 1 +$ Q $end +$var reg 16 ,$ data [15:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module fifo36_to_fifo19 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 -$ f19_dataout [18:0] $end +$var wire 1 ' f19_dst_rdy_i $end +$var wire 1 ( f19_src_rdy_o $end +$var wire 1 .$ f19_xfer $end +$var wire 36 /$ f36_datain [35:0] $end +$var wire 1 $ f36_dst_rdy_o $end +$var wire 1 0$ f36_eof $end +$var wire 1 1$ f36_occ $end +$var wire 1 2$ f36_sof $end +$var wire 1 % f36_src_rdy_i $end +$var wire 1 3$ f36_xfer $end +$var wire 1 4$ half_line $end +$var wire 1 C reset $end +$var reg 1 5$ phase $end +$upscope $end +$scope module fifo19_to_ll8 $end +$var wire 1 6$ advance $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 7$ f19_data [18:0] $end +$var wire 1 ' f19_dst_rdy_o $end +$var wire 1 8$ f19_eof $end +$var wire 1 9$ f19_occ $end +$var wire 1 :$ f19_sof $end +$var wire 1 ( f19_src_rdy_i $end +$var wire 1 ;$ ll_dst_rdy $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 <$ ll_eof $end +$var wire 1 0 ll_eof_n $end +$var wire 1 =$ ll_sof $end +$var wire 1 1 ll_sof_n $end +$var wire 1 >$ ll_src_rdy $end +$var wire 1 2 ll_src_rdy_n $end +$var wire 1 C reset $end +$var reg 8 ?$ ll_data [7:0] $end +$var reg 1 @$ state $end +$upscope $end +$scope module ll8_to_fifo19 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 A$ f19_data [18:0] $end +$var wire 1 * f19_dst_rdy_i $end +$var wire 1 + f19_src_rdy_o $end +$var wire 8 B$ ll_data [7:0] $end +$var wire 1 C$ ll_dst_rdy $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 D$ ll_eof $end +$var wire 1 0 ll_eof_n $end +$var wire 1 E$ ll_sof $end +$var wire 1 1 ll_sof_n $end +$var wire 1 F$ ll_src_rdy $end +$var wire 1 2 ll_src_rdy_n $end +$var wire 1 C reset $end +$var wire 1 G$ xfer_out $end +$var reg 8 H$ dat0 [7:0] $end +$var reg 8 I$ dat1 [7:0] $end +$var reg 1 J$ f19_eof $end +$var reg 1 K$ f19_occ $end +$var reg 1 L$ f19_sof $end +$var reg 2 M$ state [1:0] $end +$upscope $end +$scope module fifo19_to_fifo36 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 N$ f19_datain [18:0] $end +$var wire 1 * f19_dst_rdy_o $end +$var wire 1 O$ f19_eof $end +$var wire 1 P$ f19_occ $end +$var wire 1 Q$ f19_sof $end +$var wire 1 + f19_src_rdy_i $end +$var wire 36 R$ f36_dataout [35:0] $end +$var wire 1 S$ f36_dst_rdy_i $end +$var wire 1 - f36_src_rdy_o $end +$var wire 1 C reset $end +$var wire 1 T$ xfer_out $end +$var reg 16 U$ dat0 [15:0] $end +$var reg 16 V$ dat1 [15:0] $end +$var reg 1 W$ f36_eof $end +$var reg 1 X$ f36_occ $end +$var reg 1 Y$ f36_sof $end +$var reg 2 Z$ state [1:0] $end +$upscope $end +$scope task PutPacketInFIFO36 $end +$var reg 32 [$ data_len [31:0] $end +$var reg 32 \$ data_start [31:0] $end +$upscope $end +$scope task ReadFromFIFO36 $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx \$ +bx [$ +bx Z$ +xY$ +xX$ +xW$ +bx V$ +bx U$ +0T$ +0S$ +b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$ +xQ$ +xP$ +xO$ +bx N$ +bx M$ +xL$ +xK$ +xJ$ +bx I$ +bx H$ +xG$ +xF$ +xE$ +xD$ +xC$ +bx B$ +bx A$ +x@$ +bx ?$ +x>$ +x=$ +x<$ +x;$ +x:$ +x9$ +x8$ +bx 7$ +x6$ +x5$ +x4$ +x3$ +x2$ +x1$ +x0$ +bx /$ +x.$ +bx -$ +b0 ,$ +x+$ +0*$ +x)$ +x($ +x'$ +x&$ +b0 %$ +x$$ +0#$ +x"$ +x!$ +x~# +x}# +b0 |# +x{# +0z# +xy# +xx# +xw# +xv# +b0 u# +xt# +0s# +xr# +xq# +xp# +xo# +b0 n# +xm# +0l# +xk# +xj# +xi# +xh# +b0 g# +xf# +0e# +xd# +xc# +xb# +xa# +b0 `# +x_# +0^# +x]# +x\# +x[# +xZ# +b0 Y# +xX# +0W# +xV# +xU# +xT# +xS# +b0 R# +xQ# +0P# +xO# +xN# +xM# +xL# +b0 K# +xJ# +0I# +xH# +xG# +xF# +xE# +b0 D# +xC# +0B# +xA# +x@# +x?# +x># +b0 =# +x<# +0;# +x:# +x9# +x8# +x7# +b0 6# +x5# +04# +x3# +x2# +x1# +x0# +b0 /# +x.# +0-# +x,# +x+# +x*# +x)# +b0 (# +x'# +0&# +x%# +x$# +x## +x"# +b0 !# +x~" +0}" +x|" +x{" +xz" +xy" +b0 x" +xw" +0v" +xu" +xt" +xs" +xr" +b0 q" +xp" +0o" +xn" +xm" +xl" +xk" +b0 j" +xi" +0h" +xg" +xf" +xe" +xd" +b0 c" +xb" +0a" +x`" +x_" +x^" +x]" +b0 \" +x[" +0Z" +xY" +xX" +xW" +xV" +b0 U" +xT" +0S" +xR" +xQ" +xP" +xO" +b0 N" +xM" +0L" +xK" +xJ" +xI" +xH" +b0 G" +xF" +0E" +xD" +xC" +xB" +xA" +b0 @" +x?" +0>" +x=" +x<" +x;" +x:" +b0 9" +x8" +07" +x6" +x5" +x4" +x3" +b0 2" +x1" +00" +x/" +x." +x-" +x," +b0 +" +x*" +0)" +x(" +x'" +x&" +x%" +b0 $" +x#" +0"" +x!" +x~ +x} +x| +b0 { +xz +0y +xx +xw +xv +xu +b0 t +xs +0r +xq +xp +xo +xn +b0 m +xl +0k +xj +xi +xh +xg +b0 f +xe +0d +xc +xb +xa +x` +b0 _ +x^ +0] +x\ +x[ +xZ +xY +b0 X +xW +0V +xU +xT +xS +xR +b0 Q +xP +0O +xN +xM +xL +xK +bx J +bx I +xH +xG +bx F +0E +0D +1C +xB +bx A +b0 @ +0? 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+#19900000000000000 +04 +0? +#19950000000000000 +14 +1? +#20000000000000000 +04 +0? diff --git a/usrp2/fifo/fifo_short.v b/usrp2/fifo/fifo_short.v new file mode 100644 index 000000000..53a7603c7 --- /dev/null +++ b/usrp2/fifo/fifo_short.v @@ -0,0 +1,95 @@ + +module fifo_short + #(parameter WIDTH=32) + (input clk, input reset, input clear, + input [WIDTH-1:0] datain, + input src_rdy_i, + output dst_rdy_o, + output [WIDTH-1:0] dataout, + output src_rdy_o, + input dst_rdy_i, + + output reg [4:0] space, + output reg [4:0] occupied); + + reg full, empty; + wire write = src_rdy_i & dst_rdy_o; + wire read = dst_rdy_i & src_rdy_o; + + assign dst_rdy_o = ~full; + assign src_rdy_o = ~empty; + + reg [3:0] a; + genvar i; + + generate + for (i=0;i 00 = all 4 bytes + 01 = 1 byte + 10 = 2 bytes + 11 = 3 bytes + +fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]} + OCC same as buffer interface + +fifo19 --> {OCC,EOP,SOP,DATA[15:0]} + Doesn't fit well into BRAM, dist RAM ok + OCC = 1 means last word is half full + = 0 means last word is full + +fifo18 --> {EOP,SOP,DATA[15:0]} + No half-word capability? Should we drop sop instead? + +Control Wires - Data into FIFO + SRC_RDY_i Upstream has data for me + DST_RDY_o I have space + Transfer occurs if SRC_RDI_i && DST_RDY_o + +Control Wires - Data out of FIFO + SRC_RDY_o I have data for downstream + DST_RDY_i Downstream has space + Transfer occurs if SRC_RDI_o && DST_RDY_i + diff --git a/usrp2/fifo/fifo_tb.v b/usrp2/fifo/fifo_tb.v new file mode 100644 index 000000000..f561df7fa --- /dev/null +++ b/usrp2/fifo/fifo_tb.v @@ -0,0 +1,158 @@ +module fifo_new_tb(); + + reg clk = 0; + reg rst = 1; + reg clear = 0; + initial #1000 rst = 0; + always #50 clk = ~clk; + + reg [31:0] f36_data = 0; + reg [1:0] f36_occ = 0; + reg f36_sof = 0, f36_eof = 0; + + wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; + reg src_rdy_f36i = 0; + wire dst_rdy_f36i; + + wire [35:0] f36_out, f36_out2; + wire src_rdy_f36o; + reg dst_rdy_f36o = 0; + + //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36 + //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 + + wire i1_sr, i1_dr; + wire i2_sr, i2_dr; + wire i3_sr, i3_dr; + reg i4_dr = 0; + wire i4_sr; + + wire [35:0] i1, i4; + wire [18:0] i2, i3; + + wire [7:0] ll_data; + wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n; + + fifo_short #(.WIDTH(36)) fifo_short1 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), + .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) ); + + fifo36_to_fifo19 fifo36_to_fifo19 + (.clk(clk),.reset(rst),.clear(clear), + .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr), + .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) ); + + fifo19_to_ll8 fifo19_to_ll8 + (.clk(clk),.reset(rst),.clear(clear), + .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr), + .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n)); + + ll8_to_fifo19 ll8_to_fifo19 + (.clk(clk),.reset(rst),.clear(clear), + .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n), + .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk),.reset(rst),.clear(clear), + .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr), + .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) ); + + task ReadFromFIFO36; + begin + $display("Read from FIFO36"); + #1 i4_dr <= 1; + while(1) + begin + while(~i4_sr) + @(posedge clk); + $display("Read: %h",i4); + @(posedge clk); + end + end + endtask // ReadFromFIFO36 + + reg [15:0] count; + task PutPacketInFIFO36; + input [31:0] data_start; + input [31:0] data_len; + begin + count <= 4; + src_rdy_f36i <= 1; + f36_data <= data_start; + f36_sof <= 1; + f36_eof <= 0; + f36_occ <= 0; + + $display("Put Packet in FIFO36"); + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + $display("PPI_FIFO36: Entered First Line"); + f36_sof <= 0; + while(count+4 < data_len) + begin + f36_data <= f36_data + 32'h01010101; + count <= count + 4; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + $display("PPI_FIFO36: Entered New Line"); + end + f36_data <= f36_data + 32'h01010101; + f36_eof <= 1; + if(count + 4 == data_len) + f36_occ <= 0; + else if(count + 3 == data_len) + f36_occ <= 3; + else if(count + 2 == data_len) + f36_occ <= 2; + else + f36_occ <= 1; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + f36_occ <= 0; + f36_eof <= 0; + f36_data <= 0; + src_rdy_f36i <= 0; + $display("PPI_FIFO36: Entered Last Line"); + end + endtask // PutPacketInFIFO36 + + initial $dumpfile("fifo_new_tb.vcd"); + initial $dumpvars(0,fifo_new_tb); + + initial + begin + @(negedge rst); + //#10000; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + ReadFromFIFO36; + end + + initial + begin + @(negedge rst); + @(posedge clk); + @(posedge clk); + PutPacketInFIFO36(32'hA0B0C0D0,12); + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); + PutPacketInFIFO36(32'hE0F0A0B0,36); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + + initial #20000 $finish; +endmodule // longfifo_tb diff --git a/usrp2/fifo/ll8_shortfifo.v b/usrp2/fifo/ll8_shortfifo.v new file mode 100644 index 000000000..39ada9a4f --- /dev/null +++ b/usrp2/fifo/ll8_shortfifo.v @@ -0,0 +1,13 @@ + + +module ll8_shortfifo + (input clk, input reset, input clear, + input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o, + output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i); + + fifo_short #(.WIDTH(11)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + +endmodule // ll8_shortfifo diff --git a/usrp2/fifo/ll8_to_fifo19.v b/usrp2/fifo/ll8_to_fifo19.v new file mode 100644 index 000000000..af3b91afb --- /dev/null +++ b/usrp2/fifo/ll8_to_fifo19.v @@ -0,0 +1,73 @@ + +module ll8_to_fifo19 + (input clk, input reset, input clear, + input [7:0] ll_data, + input ll_sof_n, + input ll_eof_n, + input ll_src_rdy_n, + output ll_dst_rdy_n, + + output [18:0] f19_data, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + + localparam XFER_EMPTY = 0; + localparam XFER_HALF = 1; + localparam XFER_HALF_WRITE = 3; + + // Why anybody would use active low in an FPGA is beyond me... + wire ll_sof = ~ll_sof_n; + wire ll_eof = ~ll_eof_n; + wire ll_src_rdy = ~ll_src_rdy_n; + wire ll_dst_rdy; + assign ll_dst_rdy_n = ~ll_dst_rdy; + + wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i; + wire xfer_in = ll_src_rdy & ll_dst_rdy; + + reg hold_sof; + wire f19_sof, f19_eof, f19_occ; + + reg [1:0] state; + reg [7:0] hold_reg; + + always @(posedge clk) + if(ll_src_rdy & (state==XFER_EMPTY)) + hold_reg <= ll_data; + + always @(posedge clk) + if(ll_sof & (state==XFER_EMPTY)) + hold_sof <= 1; + else if(xfer_out) + hold_sof <= 0; + + always @(posedge clk) + if(reset | clear) + state <= XFER_EMPTY; + else + case(state) + XFER_EMPTY : + if(ll_src_rdy) + if(ll_eof) + state <= XFER_HALF_WRITE; + else + state <= XFER_HALF; + XFER_HALF : + if(ll_src_rdy & f19_dst_rdy_i) + state <= XFER_EMPTY; + XFER_HALF_WRITE : + if(f19_dst_rdy_i) + state <= XFER_EMPTY; + endcase // case (state) + + assign ll_dst_rdy = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i); + assign f19_src_rdy_o = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy); + + assign f19_sof = hold_sof | (ll_sof & (state==XFER_HALF)); + assign f19_eof = (state == XFER_HALF_WRITE) | ll_eof; + assign f19_occ = (state == XFER_HALF_WRITE); + + assign f19_data = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data}; + +endmodule // ll8_to_fifo19 + diff --git a/usrp2/fifo/ll8_to_fifo36.v b/usrp2/fifo/ll8_to_fifo36.v new file mode 100644 index 000000000..108daa903 --- /dev/null +++ b/usrp2/fifo/ll8_to_fifo36.v @@ -0,0 +1,97 @@ + +module ll8_to_fifo36 + (input clk, input reset, input clear, + input [7:0] ll_data, + input ll_sof_n, + input ll_eof_n, + input ll_src_rdy_n, + output ll_dst_rdy_n, + + output [35:0] f36_data, + output f36_src_rdy_o, + input f36_dst_rdy_i ); + + wire f36_write = f36_src_rdy_o & f36_dst_rdy_i; + + // Why anybody would use active low in an FPGA is beyond me... + wire ll_sof = ~ll_sof_n; + wire ll_eof = ~ll_eof_n; + wire ll_src_rdy = ~ll_src_rdy_n; + wire ll_dst_rdy; + assign ll_dst_rdy_n = ~ll_dst_rdy; + + reg f36_sof, f36_eof; + reg [1:0] f36_occ; + + + reg [2:0] state; + reg [7:0] dat0, dat1, dat2, dat3; + + always @(posedge clk) + if(ll_src_rdy & ((state==0)|f36_write)) + f36_sof <= ll_sof; + + always @(posedge clk) + if(ll_src_rdy & ((state !=4)|f36_write)) + f36_eof <= ll_eof; + + always @(posedge clk) + if(ll_eof) + f36_occ <= state[1:0] + 1; + else + f36_occ <= 0; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(ll_src_rdy) + case(state) + 0 : + if(ll_eof) + state <= 4; + else + state <= 1; + 1 : + if(ll_eof) + state <= 4; + else + state <= 2; + 2 : + if(ll_eof) + state <= 4; + else + state <= 3; + 3 : state <= 4; + 4 : + if(f36_dst_rdy_i) + if(ll_eof) + state <= 4; + else + state <= 1; + endcase // case(state) + else + if(f36_write) + state <= 0; + + always @(posedge clk) + if(ll_src_rdy & (state==3)) + dat3 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & (state==2)) + dat2 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & (state==1)) + dat1 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & ((state==0) | f36_write)) + dat0 <= ll_data; + + assign ll_dst_rdy = f36_dst_rdy_i | (state != 4); + assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess + assign f36_src_rdy_o = (state == 4); + +endmodule // ll8_to_fifo36 diff --git a/usrp2/opencores/Makefile.srcs b/usrp2/opencores/Makefile.srcs new file mode 100644 index 000000000..30360a17d --- /dev/null +++ b/usrp2/opencores/Makefile.srcs @@ -0,0 +1,28 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Open Cores Sources +################################################## +OPENCORES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../opencores/, \ +8b10b/decode_8b10b.v \ +8b10b/encode_8b10b.v \ +aemb/rtl/verilog/aeMB_bpcu.v \ +aemb/rtl/verilog/aeMB_core_BE.v \ +aemb/rtl/verilog/aeMB_ctrl.v \ +aemb/rtl/verilog/aeMB_edk32.v \ +aemb/rtl/verilog/aeMB_ibuf.v \ +aemb/rtl/verilog/aeMB_regf.v \ +aemb/rtl/verilog/aeMB_xecu.v \ +i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +i2c/rtl/verilog/i2c_master_defines.v \ +i2c/rtl/verilog/i2c_master_top.v \ +i2c/rtl/verilog/timescale.v \ +spi/rtl/verilog/spi_clgen.v \ +spi/rtl/verilog/spi_defines.v \ +spi/rtl/verilog/spi_shift.v \ +spi/rtl/verilog/spi_top.v \ +spi/rtl/verilog/timescale.v \ +)) diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs new file mode 100644 index 000000000..90eede20f --- /dev/null +++ b/usrp2/sdr_lib/Makefile.srcs @@ -0,0 +1,37 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# FIFO Sources +################################################## +SDR_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../sdr_lib/, \ +acc.v \ +add2.v \ +add2_and_round.v \ +add2_and_round_reg.v \ +add2_reg.v \ +cic_dec_shifter.v \ +cic_decim.v \ +cic_int_shifter.v \ +cic_interp.v \ +cic_strober.v \ +clip.v \ +clip_reg.v \ +cordic.v \ +cordic_z24.v \ +cordic_stage.v \ +dsp_core_rx.v \ +dsp_core_rx_old.v \ +dsp_core_tx.v \ +hb_dec.v \ +hb_interp.v \ +round.v \ +round_reg.v \ +rx_control.v \ +rx_dcoffset.v \ +sign_extend.v \ +small_hb_dec.v \ +small_hb_int.v \ +tx_control.v \ +)) diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index aba18fccb..1e689fc7f 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -1,6 +1,6 @@ -`define DSP_CORE_RX_BASE 160 module dsp_core_rx + #(parameter BASE = 160) (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, @@ -37,33 +37,33 @@ module dsp_core_rx wire [31:4] UNUSED_2; wire [31:2] UNUSED_3; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 + setting_reg #(.my_addr(BASE+0)) sr_0 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_inc),.changed()); - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 + setting_reg #(.my_addr(BASE+1)) sr_1 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({scale_i,scale_q}),.changed()); - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 + setting_reg #(.my_addr(BASE+2)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed()); - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a + rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_in(adc_a),.adc_out(adc_a_ofs)); - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b + rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_in(adc_b),.adc_out(adc_b_ofs)); wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 + setting_reg #(.my_addr(BASE+5)) sr_8 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({UNUSED_2,muxctrl}),.changed()); wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 + setting_reg #(.my_addr(BASE+6)) sr_9 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({UNUSED_3,gpio_ena}),.changed()); diff --git a/usrp2/sdr_lib/dsp_core_rx_old.v b/usrp2/sdr_lib/dsp_core_rx_old.v new file mode 100644 index 000000000..ba301e91b --- /dev/null +++ b/usrp2/sdr_lib/dsp_core_rx_old.v @@ -0,0 +1,183 @@ + +`define DSP_CORE_RX_BASE 160 +module dsp_core_rx_old + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [13:0] adc_a, input adc_ovf_a, + input [13:0] adc_b, input adc_ovf_b, + + input [15:0] io_rx, + + output [31:0] sample, + input run, + output strobe, + output [31:0] debug + ); + + wire [15:0] scale_i, scale_q; + wire [13:0] adc_a_ofs, adc_b_ofs; + reg [13:0] adc_i, adc_q; + wire [31:0] phase_inc; + reg [31:0] phase; + + wire [35:0] prod_i, prod_q; + wire [23:0] i_cordic, q_cordic; + wire [23:0] i_cic, q_cic; + wire [17:0] i_cic_scaled, q_cic_scaled; + wire [17:0] i_hb1, q_hb1; + wire [17:0] i_hb2, q_hb2; + wire [15:0] i_out, q_out; + + wire strobe_cic, strobe_hb1, strobe_hb2; + wire enable_hb1, enable_hb2; + wire [7:0] cic_decim_rate; + + wire [31:10] UNUSED_1; + wire [31:4] UNUSED_2; + wire [31:2] UNUSED_3; + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed()); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_a),.adc_out(adc_a_ofs)); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_b),.adc_out(adc_b_ofs)); + + wire [3:0] muxctrl; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({UNUSED_2,muxctrl}),.changed()); + + wire [1:0] gpio_ena; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({UNUSED_3,gpio_ena}),.changed()); + + // The TVRX connects to what is called adc_b, thus A and B are + // swapped throughout the design. + // + // In the interest of expediency and keeping the s/w sane, we just remap them here. + // The I & Q fields are mapped the same: + // 0 -> "the real A" (as determined by the TVRX) + // 1 -> "the real B" + // 2 -> const zero + + always @(posedge clk) + case(muxctrl[1:0]) // The I mapping + 0: adc_i <= adc_b_ofs; // "the real A" + 1: adc_i <= adc_a_ofs; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case(muxctrl[1:0]) + + always @(posedge clk) + case(muxctrl[3:2]) // The Q mapping + 0: adc_q <= adc_b_ofs; // "the real A" + 1: adc_q <= adc_a_ofs; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case(muxctrl[3:2]) + + always @(posedge clk) + if(rst) + phase <= 0; + else if(~run) + phase <= 0; + else + phase <= phase + phase_inc; + + MULT18X18S mult_i + (.P(prod_i), // 36-bit multiplier output + .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + MULT18X18S mult_q + (.P(prod_q), // 36-bit multiplier output + .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + + cordic_z24 #(.bitwidth(24)) + cordic(.clock(clk), .reset(rst), .enable(run), + .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]), + .xo(i_cordic),.yo(q_cordic),.zo() ); + + cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate), + .strobe_fast(1),.strobe_slow(strobe_cic) ); + + cic_decim #(.bw(24)) + decim_i (.clock(clk),.reset(rst),.enable(run), + .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), + .signal_in(i_cordic),.signal_out(i_cic)); + + cic_decim #(.bw(24)) + decim_q (.clock(clk),.reset(rst),.enable(run), + .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), + .signal_in(q_cordic),.signal_out(q_cic)); + + round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled)); + round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled)); + reg strobe_cic_d1; + always @(posedge clk) strobe_cic_d1 <= strobe_cic; + + small_hb_dec #(.WIDTH(18)) small_hb_i + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), + .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1)); + + small_hb_dec #(.WIDTH(18)) small_hb_q + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), + .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1)); + + wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate}; + hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), + .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2)); + + hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), + .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); + + round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); + round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); + + // Streaming GPIO + // + // io_rx[15] => I channel LSB if gpio_ena[0] high + // io_rx[14] => Q channel LSB if gpio_ena[1] high + + reg [31:0] sample_reg; + always @(posedge clk) + begin + sample_reg[31:17] <= i_out[15:1]; + sample_reg[15:1] <= q_out[15:1]; + sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; + sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; + end + + assign sample = sample_reg; + assign strobe = strobe_hb2; + assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; + +endmodule // dsp_core_rx diff --git a/usrp2/serdes/Makefile.srcs b/usrp2/serdes/Makefile.srcs new file mode 100644 index 000000000..bade46ad1 --- /dev/null +++ b/usrp2/serdes/Makefile.srcs @@ -0,0 +1,14 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# SERDES Sources +################################################## +SERDES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../serdes/, \ +serdes.v \ +serdes_fc_rx.v \ +serdes_fc_tx.v \ +serdes_rx.v \ +serdes_tx.v \ +)) diff --git a/usrp2/simple_gemac/Makefile.srcs b/usrp2/simple_gemac/Makefile.srcs new file mode 100644 index 000000000..6480cd5a4 --- /dev/null +++ b/usrp2/simple_gemac/Makefile.srcs @@ -0,0 +1,26 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Simple GEMAC Sources +################################################## +SIMPLE_GEMAC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../simple_gemac/, \ +simple_gemac_wrapper.v \ +simple_gemac_wrapper19.v \ +simple_gemac.v \ +simple_gemac_wb.v \ +simple_gemac_tx.v \ +simple_gemac_rx.v \ +crc.v \ +delay_line.v \ +flow_ctrl_tx.v \ +flow_ctrl_rx.v \ +address_filter.v \ +ll8_to_txmac.v \ +rxmac_to_ll8.v \ +miim/eth_miim.v \ +miim/eth_clockgen.v \ +miim/eth_outputcontrol.v \ +miim/eth_shiftreg.v \ +)) diff --git a/usrp2/timing/Makefile.srcs b/usrp2/timing/Makefile.srcs new file mode 100644 index 000000000..0cf9372d3 --- /dev/null +++ b/usrp2/timing/Makefile.srcs @@ -0,0 +1,16 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Timing Sources +################################################## +TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../timing/, \ +time_64bit.v \ +time_compare.v \ +time_receiver.v \ +time_sender.v \ +time_sync.v \ +timer.v \ +simple_timer.v \ +)) diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common new file mode 100644 index 000000000..25c48d31a --- /dev/null +++ b/usrp2/top/Makefile.common @@ -0,0 +1,84 @@ +# +# Copyright 2008, 2009, 2010 Ettus Research LLC +# + +################################################## +# Constants +################################################## +BASE_DIR = $(abspath ..) +ISE_HELPER = xtclsh /home/matt/sourcerepo/mobfleet/system_board/fpga/scripts/ise_helper.tcl +#ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl +ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).ise +BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit +MAKE_ACE = $(BUILD_DIR)/make_ace.cmd +ACE_FILE = $(BUILD_DIR)/xilinx.sys +MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs +IMPACT_CMD = $(BUILD_DIR)/impact.cmd +IMPACT_CDF = $(BUILD_DIR)/impact.cdf + +################################################## +# Global Targets +################################################## +all: bin + +proj: $(ISE_FILE) + +check: $(ISE_FILE) + $(ISE_HELPER) "Check Syntax" + +synth: $(ISE_FILE) + $(ISE_HELPER) "Synthesize - XST" + +bin: $(BIN_FILE) + +ace: $(ACE_FILE) + +mcs: $(MCS_FILE) + +clean: + $(RM) -r $(BUILD_DIR) + +XIL_IMPACT_USE_LIBUSB=1 +jtag-install: $(IMPACT_CMD) + impact -batch $< + +.PHONY: all proj check synth bin ace mcs clean jtag-install + +################################################## +# Dependency Targets +################################################## +$(ISE_FILE): $(SOURCES) + @echo $@ + $(ISE_HELPER) "" + +$(BIN_FILE): $(ISE_FILE) + @echo $@ + $(ISE_HELPER) "Generate Programming File" + touch $@ + +$(MAKE_ACE): $(BASE_DIR)/scripts/make_ace.cmd.in + sed \ + -e 's|@BUILD_DIR[@]|$(BUILD_DIR)|g' \ + -e 's|@TOP_MODULE[@]|$(TOP_MODULE)|g' \ + -e 's|@BIN_FILE[@]|$(BIN_FILE)|g' \ + $< > $@ + +$(ACE_FILE): $(BIN_FILE) $(MAKE_ACE) + @echo $@ + impact -batch $(MAKE_ACE) + +$(MCS_FILE): $(BIN_FILE) + promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE) + +$(IMPACT_CDF): $(BASE_DIR)/scripts/impact.cdf.in + sed \ + -e 's|@BIN_FILE[@]|$(BIN_FILE)|g' \ + $< > $@ + +$(IMPACT_CMD): $(BASE_DIR)/scripts/impact.cmd.in $(IMPACT_CDF) + sed \ + -e 's|@PART_NAME[@]|xc5vsx50t|g' \ + -e 's|@CDF_FILE[@]|$(IMPACT_CDF)|g' \ + $< > $@ + +.EXPORT_ALL_VARIABLES: diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 3a8edc9ac..86e5bf979 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -1,42 +1,30 @@ # # Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# +# -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs ################################################## # Project Setup ################################################## -BUILD_DIR := build$(ISE)/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise +TOP_MODULE = u2_rev3 +BUILD_DIR = $(abspath build$(ISE)) ################################################## # Project Properties ################################################## -export PROJECT_PROPERTIES := \ +PROJECT_PROPERTIES = \ family Spartan3 \ device xc3s2000 \ package fg456 \ @@ -51,159 +39,20 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## # Sources ################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/settings_bus_crossclock.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -control_lib/priority_enc.v \ -control_lib/pic.v \ -vrt/vita_rx_control.v \ -vrt/vita_rx_framer.v \ -vrt/vita_tx_control.v \ -vrt/vita_tx_deframer.v \ -udp/udp_wrapper.v \ -udp/fifo19_rxrealign.v \ -udp/prot_eng_tx.v \ -udp/add_onescomp.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac_wrapper19.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo19_to_ll8.v \ -control_lib/newfifo/ll8_to_fifo19.v \ -control_lib/newfifo/fifo36_to_fifo19.v \ -control_lib/newfifo/fifo19_to_fifo36.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -coregen/fifo_xlnx_16x19_2clk.v \ -coregen/fifo_xlnx_16x19_2clk.xco \ -coregen/fifo_xlnx_16x40_2clk.v \ -coregen/fifo_xlnx_16x40_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_64bit.v \ -timing/time_compare.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -timing/simple_timer.v \ -top/u2_rev3/u2_core.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v +TOP_SRCS = \ +u2_core.v \ +u2_rev3.v \ +u2_rev3.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) ################################################## # Process Properties ################################################## -export SYNTHESIZE_PROPERTIES := \ +SYNTHESIZE_PROPERTIES = \ "Number of Clock Buffers" 8 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ @@ -213,10 +62,10 @@ export SYNTHESIZE_PROPERTIES := \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto -export TRANSLATE_PROPERTIES := \ +TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" -export MAP_PROPERTIES := \ +MAP_PROPERTIES = \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ @@ -227,41 +76,18 @@ export MAP_PROPERTIES := \ "Combinatorial Logic Optimization" TRUE \ "Register Duplication" TRUE -export PLACE_ROUTE_PROPERTIES := \ +PLACE_ROUTE_PROPERTIES = \ "Place & Route Effort Level (Overall)" High -export STATIC_TIMING_PROPERTIES := \ +STATIC_TIMING_PROPERTIES = \ "Number of Paths in Error/Verbose Report" 10 \ "Report Type" "Error Report" -export GEN_PROG_FILE_PROPERTIES := \ +GEN_PROG_FILE_PROPERTIES = \ "Configuration Rate" 6 \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ "Enable Outputs (Output Events)" 6 -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp index f6e6e5b15..90a5d88be 100644 --- a/usrp2/top/u2_rev3/Makefile.udp +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -1,42 +1,30 @@ # # Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# +# -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs ################################################## # Project Setup ################################################## -BUILD_DIR := build-udp$(ISE)/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise +TOP_MODULE = u2_rev3 +BUILD_DIR = $(abspath build-udp$(ISE)) ################################################## # Project Properties ################################################## -export PROJECT_PROPERTIES := \ +PROJECT_PROPERTIES = \ family Spartan3 \ device xc3s2000 \ package fg456 \ @@ -51,159 +39,20 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## # Sources ################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/settings_bus_crossclock.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -control_lib/priority_enc.v \ -control_lib/pic.v \ -vrt/vita_rx_control.v \ -vrt/vita_rx_framer.v \ -vrt/vita_tx_control.v \ -vrt/vita_tx_deframer.v \ -udp/udp_wrapper.v \ -udp/fifo19_rxrealign.v \ -udp/prot_eng_tx.v \ -udp/add_onescomp.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac_wrapper19.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo19_to_ll8.v \ -control_lib/newfifo/ll8_to_fifo19.v \ -control_lib/newfifo/fifo36_to_fifo19.v \ -control_lib/newfifo/fifo19_to_fifo36.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -coregen/fifo_xlnx_16x19_2clk.v \ -coregen/fifo_xlnx_16x19_2clk.xco \ -coregen/fifo_xlnx_16x40_2clk.v \ -coregen/fifo_xlnx_16x40_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx_udp.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_64bit.v \ -timing/time_compare.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -timing/simple_timer.v \ -top/u2_rev3/u2_core_udp.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v +TOP_SRCS = \ +u2_core_udp.v \ +u2_rev3.v \ +u2_rev3.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) ################################################## # Process Properties ################################################## -export SYNTHESIZE_PROPERTIES := \ +SYNTHESIZE_PROPERTIES = \ "Number of Clock Buffers" 8 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ @@ -213,10 +62,10 @@ export SYNTHESIZE_PROPERTIES := \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto -export TRANSLATE_PROPERTIES := \ +TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" -export MAP_PROPERTIES := \ +MAP_PROPERTIES = \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ @@ -227,41 +76,18 @@ export MAP_PROPERTIES := \ "Combinatorial Logic Optimization" TRUE \ "Register Duplication" TRUE -export PLACE_ROUTE_PROPERTIES := \ +PLACE_ROUTE_PROPERTIES = \ "Place & Route Effort Level (Overall)" High -export STATIC_TIMING_PROPERTIES := \ +STATIC_TIMING_PROPERTIES = \ "Number of Paths in Error/Verbose Report" 10 \ "Report Type" "Error Report" -export GEN_PROG_FILE_PROPERTIES := \ +GEN_PROG_FILE_PROPERTIES = \ "Configuration Rate" 6 \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ "Enable Outputs (Output Events)" 6 -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v old mode 100755 new mode 100644 index c2e1bab63..b67d8edd6 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -582,8 +582,7 @@ module u2_core .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), .debug_rx(debug_rx) ); - // dummy_rx dsp_core_rx - dsp_core_rx dsp_core_rx + dsp_core_rx_old dsp_core_rx_old (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), diff --git a/usrp2/udp/Makefile.srcs b/usrp2/udp/Makefile.srcs new file mode 100644 index 000000000..293094abe --- /dev/null +++ b/usrp2/udp/Makefile.srcs @@ -0,0 +1,13 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# UDP Sources +################################################## +UDP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../udp/, \ +udp_wrapper.v \ +fifo19_rxrealign.v \ +prot_eng_tx.v \ +add_onescomp.v \ +)) diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs new file mode 100644 index 000000000..07c62224b --- /dev/null +++ b/usrp2/vrt/Makefile.srcs @@ -0,0 +1,13 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# VRT Sources +################################################## +VRT_SRCS = $(abspath $(addprefix $(BASE_DIR)/../vrt/, \ +vita_rx_control.v \ +vita_rx_framer.v \ +vita_tx_control.v \ +vita_tx_deframer.v \ +)) -- cgit v1.2.3 From 1935f2a4ed0d0abc90bb3fe7fed745ff84ab6d7c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 11 Jun 2010 17:23:34 -0700 Subject: produces good bin files --- usrp2/top/Makefile.common | 39 +++------------------------------------ usrp2/top/tcl/ise_helper.tcl | 17 ++++++++--------- usrp2/top/u2_rev3/Makefile | 16 ++++++++++------ usrp2/top/u2_rev3/Makefile.udp | 16 ++++++++++------ 4 files changed, 31 insertions(+), 57 deletions(-) diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index 25c48d31a..02b1b9529 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -6,15 +6,10 @@ # Constants ################################################## BASE_DIR = $(abspath ..) -ISE_HELPER = xtclsh /home/matt/sourcerepo/mobfleet/system_board/fpga/scripts/ise_helper.tcl -#ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl +ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).ise -BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit -MAKE_ACE = $(BUILD_DIR)/make_ace.cmd -ACE_FILE = $(BUILD_DIR)/xilinx.sys +BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs -IMPACT_CMD = $(BUILD_DIR)/impact.cmd -IMPACT_CDF = $(BUILD_DIR)/impact.cdf ################################################## # Global Targets @@ -31,18 +26,12 @@ synth: $(ISE_FILE) bin: $(BIN_FILE) -ace: $(ACE_FILE) - mcs: $(MCS_FILE) clean: $(RM) -r $(BUILD_DIR) -XIL_IMPACT_USE_LIBUSB=1 -jtag-install: $(IMPACT_CMD) - impact -batch $< - -.PHONY: all proj check synth bin ace mcs clean jtag-install +.PHONY: all proj check synth bin mcs clean ################################################## # Dependency Targets @@ -56,29 +45,7 @@ $(BIN_FILE): $(ISE_FILE) $(ISE_HELPER) "Generate Programming File" touch $@ -$(MAKE_ACE): $(BASE_DIR)/scripts/make_ace.cmd.in - sed \ - -e 's|@BUILD_DIR[@]|$(BUILD_DIR)|g' \ - -e 's|@TOP_MODULE[@]|$(TOP_MODULE)|g' \ - -e 's|@BIN_FILE[@]|$(BIN_FILE)|g' \ - $< > $@ - -$(ACE_FILE): $(BIN_FILE) $(MAKE_ACE) - @echo $@ - impact -batch $(MAKE_ACE) - $(MCS_FILE): $(BIN_FILE) promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE) -$(IMPACT_CDF): $(BASE_DIR)/scripts/impact.cdf.in - sed \ - -e 's|@BIN_FILE[@]|$(BIN_FILE)|g' \ - $< > $@ - -$(IMPACT_CMD): $(BASE_DIR)/scripts/impact.cmd.in $(IMPACT_CDF) - sed \ - -e 's|@PART_NAME[@]|xc5vsx50t|g' \ - -e 's|@CDF_FILE[@]|$(IMPACT_CDF)|g' \ - $< > $@ - .EXPORT_ALL_VARIABLES: diff --git a/usrp2/top/tcl/ise_helper.tcl b/usrp2/top/tcl/ise_helper.tcl index fe9db87af..a4bee76b8 100644 --- a/usrp2/top/tcl/ise_helper.tcl +++ b/usrp2/top/tcl/ise_helper.tcl @@ -40,12 +40,12 @@ proc set_props {process options} { } } -if [file isfile $env(PROJ_FILE)] { - puts ">>> Opening project: $env(PROJ_FILE)" - project open $env(PROJ_FILE) +if [file isfile $env(ISE_FILE)] { + puts ">>> Opening project: $env(ISE_FILE)" + project open $env(ISE_FILE) } else { - puts ">>> Creating project: $env(PROJ_FILE)" - project new $env(PROJ_FILE) + puts ">>> Creating project: $env(ISE_FILE)" + project new $env(ISE_FILE) ################################################## # Set the project properties @@ -56,7 +56,6 @@ if [file isfile $env(PROJ_FILE)] { # Add the sources ################################################## foreach source $env(SOURCES) { - set source $env(SOURCE_ROOT)$source puts ">>> Adding source to project: $source" xfile add $source } @@ -78,9 +77,9 @@ if [file isfile $env(PROJ_FILE)] { set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES) } -if [string compare $env(PROCESS_RUN) ""] { - puts ">>> Running Process: $env(PROCESS_RUN)" - process run $env(PROCESS_RUN) +if [string compare [lindex $argv 0] ""] { + puts ">>> Running Process: [lindex $argv 0]" + process run [lindex $argv 0] } project close diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 86e5bf979..68c296b9b 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -2,6 +2,16 @@ # Copyright 2008 Ettus Research LLC # +################################################## +# Project Setup +################################################## +TOP_MODULE = u2_rev3 +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + include ../Makefile.common include ../../fifo/Makefile.srcs include ../../control_lib/Makefile.srcs @@ -15,12 +25,6 @@ include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extram/Makefile.srcs -################################################## -# Project Setup -################################################## -TOP_MODULE = u2_rev3 -BUILD_DIR = $(abspath build$(ISE)) - ################################################## # Project Properties ################################################## diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp index 90a5d88be..9962887d4 100644 --- a/usrp2/top/u2_rev3/Makefile.udp +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -2,6 +2,16 @@ # Copyright 2008 Ettus Research LLC # +################################################## +# Project Setup +################################################## +TOP_MODULE = u2_rev3 +BUILD_DIR = $(abspath build-udp$(ISE)) + +################################################## +# Include other makefiles +################################################## + include ../Makefile.common include ../../fifo/Makefile.srcs include ../../control_lib/Makefile.srcs @@ -15,12 +25,6 @@ include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extram/Makefile.srcs -################################################## -# Project Setup -################################################## -TOP_MODULE = u2_rev3 -BUILD_DIR = $(abspath build-udp$(ISE)) - ################################################## # Project Properties ################################################## -- cgit v1.2.3 From 9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 14 Jun 2010 12:23:52 -0700 Subject: new make works on ise12 --- usrp2/top/Makefile.common | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index 02b1b9529..d1c89fdfb 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -5,9 +5,15 @@ ################################################## # Constants ################################################## +ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.) +ifeq ($(ISE_VER),10) + ISE_EXT = ise +else + ISE_EXT = xise +endif BASE_DIR = $(abspath ..) ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl -ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).ise +ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs -- cgit v1.2.3