From ed2882e600832f6cb46d05bde7aa49d045e63895 Mon Sep 17 00:00:00 2001
From: Nick Foster <nick@nerdnetworks.org>
Date: Wed, 28 Jul 2010 15:52:00 -0700
Subject: Fix for SPI SS > 8 bits wide

---
 usrp2/opencores/spi/rtl/verilog/spi_defines.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index a6925918e..25c08214b 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -102,8 +102,8 @@
 // Number of device select signals. Use SPI_SS_NB for fine tuning the 
 // exact number.
 //
-`define SPI_SS_NB_8
-//`define SPI_SS_NB_16
+//`define SPI_SS_NB_8
+`define SPI_SS_NB_16
 //`define SPI_SS_NB_24
 //`define SPI_SS_NB_32
 
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