From ecdb22b449e13d1ded69b82e5736d4c09c7db23a Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Wed, 24 Nov 2010 20:26:38 -0800
Subject: packet_router: added cpu input and output control registers, modified
 control code

---
 firmware/microblaze/lib/pkt_ctrl.c      | 54 +++++++++++----------------------
 firmware/microblaze/usrp2/memory_map.h  |  4 ++-
 firmware/microblaze/usrp2p/memory_map.h |  4 ++-
 3 files changed, 23 insertions(+), 39 deletions(-)

diff --git a/firmware/microblaze/lib/pkt_ctrl.c b/firmware/microblaze/lib/pkt_ctrl.c
index f4b4b7825..d2bfc339d 100644
--- a/firmware/microblaze/lib/pkt_ctrl.c
+++ b/firmware/microblaze/lib/pkt_ctrl.c
@@ -19,32 +19,6 @@
 #include "memory_map.h"
 #include <nonstdio.h>
 
-static void set_control(uint32_t value, uint32_t mask){
-    static uint32_t ctrl_shadow = 0;
-
-    ctrl_shadow &= ~mask;
-    ctrl_shadow |= value & mask;
-
-    buffer_pool_ctrl->ctrl = ctrl_shadow;
-}
-
-static void set_control_bit(int bit){
-    set_control(1 << bit, 1 << bit);
-}
-
-static void clr_control_bit(int bit){
-    set_control(0 << bit, 1 << bit);
-}
-
-static bool is_status_bit_set(int bit){
-    return buffer_pool_status->status & (1 << bit);
-}
-
-#define INP_HS_BIT 0 //CPU out in packet_router.v
-#define OUT_HS_BIT 1 //CPU inp in packet_router.v
-#define MODE_BIT 2
-#define CLR_BIT 8
-
 void pkt_ctrl_program_inspector(
     const struct ip_addr *ip_addr, uint16_t dsp_udp_port
 ){
@@ -55,34 +29,40 @@ void pkt_ctrl_program_inspector(
 void pkt_ctrl_set_routing_mode(pkt_ctrl_routing_mode_t mode){
     switch(mode){
     case PKT_CTRL_ROUTING_MODE_SLAVE:
-        clr_control_bit(MODE_BIT);
+        buffer_pool_ctrl->misc_ctrl = 0;
         break;
     case PKT_CTRL_ROUTING_MODE_MASTER:
-        set_control_bit(MODE_BIT);
+        buffer_pool_ctrl->misc_ctrl = 1;
         break;
     }
 }
 
+static inline bool is_status_bit_set(int bit){
+    return buffer_pool_status->status & (1 << bit);
+}
+
+#define CPU_OUT_HS_BIT 0 //from packet router to CPU
+#define CPU_INP_HS_BIT 1 //from CPU to packet router
+
 void *pkt_ctrl_claim_incoming_buffer(size_t *num_lines){
-    if (!is_status_bit_set(INP_HS_BIT)) return NULL;
+    if (!is_status_bit_set(CPU_OUT_HS_BIT)) return NULL;
     *num_lines = (buffer_pool_status->status >> 16) & 0xffff;
     return buffer_ram(0);
 }
 
 void pkt_ctrl_release_incoming_buffer(void){
-    set_control_bit(INP_HS_BIT);
-    while (is_status_bit_set(INP_HS_BIT)){}
-    clr_control_bit(INP_HS_BIT);
+    buffer_pool_ctrl->cpu_out_ctrl = 1;
+    while (is_status_bit_set(CPU_OUT_HS_BIT)){}
+    buffer_pool_ctrl->cpu_out_ctrl = 0;
 }
 
 void *pkt_ctrl_claim_outgoing_buffer(void){
-    while (!is_status_bit_set(OUT_HS_BIT)){}
+    while (!is_status_bit_set(CPU_INP_HS_BIT)){}
     return buffer_ram(1);
 }
 
 void pkt_ctrl_commit_outgoing_buffer(size_t num_lines){
-    set_control(num_lines << 16, 0xffff << 16);
-    set_control_bit(OUT_HS_BIT);
-    while (is_status_bit_set(OUT_HS_BIT)){}
-    clr_control_bit(OUT_HS_BIT);
+    buffer_pool_ctrl->cpu_inp_ctrl = ((num_lines & 0xffff) << 16) | 1;
+    while (is_status_bit_set(CPU_INP_HS_BIT)){}
+    buffer_pool_ctrl->cpu_inp_ctrl = 0;
 }
diff --git a/firmware/microblaze/usrp2/memory_map.h b/firmware/microblaze/usrp2/memory_map.h
index 25c800893..09aef643e 100644
--- a/firmware/microblaze/usrp2/memory_map.h
+++ b/firmware/microblaze/usrp2/memory_map.h
@@ -246,9 +246,11 @@ hwconfig_wishbone_divisor(void)
 // --- buffer pool control regs ---
 
 typedef struct {
-  volatile uint32_t ctrl;
+  volatile uint32_t misc_ctrl;
   volatile uint32_t ip_addr;
   volatile uint32_t udp_ports; //dsp0 (low 16) dsp1 (high 16)
+  volatile uint32_t cpu_out_ctrl;
+  volatile uint32_t cpu_inp_ctrl;
 } buffer_pool_ctrl_t;
 
 #define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE)
diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h
index dedfdac8b..277f433c5 100644
--- a/firmware/microblaze/usrp2p/memory_map.h
+++ b/firmware/microblaze/usrp2p/memory_map.h
@@ -273,9 +273,11 @@ hwconfig_wishbone_divisor(void)
 // --- buffer pool control regs ---
 
 typedef struct {
-  volatile uint32_t ctrl;
+  volatile uint32_t misc_ctrl;
   volatile uint32_t ip_addr;
   volatile uint32_t udp_ports; //dsp0 (low 16) dsp1 (high 16)
+  volatile uint32_t cpu_out_ctrl;
+  volatile uint32_t cpu_inp_ctrl;
 } buffer_pool_ctrl_t;
 
 #define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE)
-- 
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