From e86bfa1ba5f05269924d02238f92a50b6438770f Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 9 Sep 2020 14:38:23 -0500 Subject: docs: Updated register maps for UHD 4.0 Updates e3xx and n3xx register map documentation. - Add new RFNoC registers - Remove depreicated RFNoC registers - Add other missing registers - Correct formatting --- host/docs/usrp_e3xx.dox | 25 ++++++++++--------------- host/docs/usrp_n3xx.dox | 38 ++++++++++++++++++-------------------- 2 files changed, 28 insertions(+), 35 deletions(-) diff --git a/host/docs/usrp_e3xx.dox b/host/docs/usrp_e3xx.dox index 3b3b3c7ce..6597e7446 100644 --- a/host/docs/usrp_e3xx.dox +++ b/host/docs/usrp_e3xx.dox @@ -1396,15 +1396,16 @@ Slave 3 | 4001_4000 - 4001_41ff | dboard-regs | Daughterboard control 4000_7000 onwards REMOTE_DST_IP W Destination IP, MAC, UDP for Outgoing Packet for 16 local addrs 4000_7400 onwards REMOTE_DST_UDP_MAC_HIW Destination MAC (MSB) 4000_7800 onwards REMOTE_DST_MAC_LOW Destination MAC (LSB) - -Slave 2 e320_core 4001_0000 COMPAT_NUM R FPGA Compat Number +Slave 2 e3xx_core 4001_0000 COMPAT_NUM R FPGA Compat Number [31:16] Major RO - [15:0] Minor RO - 4001_0004 DATESTAMP RO - 4001_0008 GIT_HASH RO - 4001_000C SCRATCH RO - - 4001_0010 NUM_CE RO Number of Computation Engines (RFNoC Blocks) - 4001_0014 NUM_IO_CE RO Number of fixed IO CEs - Radios + DMA Fifo + 4001_0010 REG_DEVICE_ID RW RFNoC Device ID + 4001_0014 REG_RFNOC_INFO RO RFNoC Information + [31:16] CHDR_W RO RFNoC CHDR Width in Bits + [15:0] RFNOC_PROTOVER RO RFNoC Protocol Version 4001_0018 CLOCK_CTRL - [0] pps select (internal 10 MHz)RWOne-hot encoded pps_select to use the internal PPS from GPSDO [1] pps select (external 10 MHz)RWOne-hot encoded pps_select to use the external PPS. @@ -1415,13 +1416,13 @@ Slave 3 | 4001_4000 - 4001_41ff | dboard-regs | Daughterboard control 4001_0024 BUS_CLK_COUNT RO - 4001_0028 SFP_PORT_INFO RO Same as port_info register 0x4000_4000 4001_002C FP_GPIO_CTRL RW - - 4001_0030 FP_GPIO_MASTER RW - - 4001_0034 FP_GPIO_RADIO_SRC RW - - 4001_0038 GPS_CTRL RW - + 4001_0030 FP_GPIO_MASTER RW GPIO master select bits. One bit per GPIO. LSB is for GPIO 0. Set bit to 0 for Radio, 1 for PS. + 4001_0034 FP_GPIO_RADIO_SRC RW Radio channel source select bits. Two bits per GPIO. Bits [1:0] are for GPIO 0. Set to 00 for channel 0, 01 for channel 1, etc. + 4001_0038 GPS_CTRL RW E320 Only [0] GPS_PWR_EN RW Power on GPSDO [1] GPS_RST_N RW - [2] GPS_INITSURV_N RW - - 4001_003C GPS_STATUS RO GPSDO Status + 4001_003C GPS_STATUS RO GPSDO Status, E320 Only [0] GPS_LOCK RO Returns 1 if GPSDO is locked [1] GPS_ALARM RO - [2] GPS_PHASELOCK RO - @@ -1429,13 +1430,7 @@ Slave 3 | 4001_4000 - 4001_41ff | dboard-regs | Daughterboard control [4] GPS_WARMUP RO - 4001_0040 DBOARD_CTRL RO - 4001_0044 DBOARD_STATUS RO - - - axi_crossbar 4001_1010 XBAR_VERSION RO See crossbar kernel driver - 4001_1014 XBAR_NUM_PORTS RO See crossbar kernel driver - 4001_1018 LOCAL_ADDR RW See crossbar kernel driver - 4001_1020 remote_offset WO XBAR settings reg - 4001_1420 local_offset WO XBAR settings reg - + 4001_0048 NUM_TIMEKEEPERS RO Number of radio timekeepers Slave 4 4001_40004001_41FFDaughterboard Registers- Don't exist now. TBD diff --git a/host/docs/usrp_n3xx.dox b/host/docs/usrp_n3xx.dox index 7d3a714f1..bb4a99228 100644 --- a/host/docs/usrp_n3xx.dox +++ b/host/docs/usrp_n3xx.dox @@ -1193,9 +1193,9 @@ Slave 6 | 4001_8000 - 4001_bfff | dboard-regs1 | Daughterboard control, sl Slave 0 axi_eth_dma0 4000_0000 - 4000_4fff Ethernet DMA RW See Linux Driver Slave 1 n3xx_mgt_io_core 4000_4000 PORT_INFO RO SFP port information [31:24] COMPAT_NUM RO - - [23:18] 6'h0 RO - + [23:18] 6'h0 RO - [17] activity RO - - [16] link_up RO - + [16] link_up RO - [15:8] mgt_protocol RO 0 - None, 1 - 1G, 2 - XG, 3 - Aurora [7:0] PORTNUM RO - n3xx_mgt_io_core 4000_4004 MAC_CTRL_STATUS RW Control 10gE and Aurora mac @@ -1235,21 +1235,20 @@ Slave 6 | 4001_8000 - 4001_bfff | dboard-regs1 | Daughterboard control, sl 4000_7000 onwards REMOTE_DST_IP W Destination IP, MAC, UDP for Outgoing Packet for 16 local addrs 4000_7400 onwards REMOTE_DST_UDP_MAC_HIW Destination MAC (MSB) 4000_7800 onwards REMOTE_DST_MAC_LOW Destination MAC (LSB) - Slave 2 axi_eth_dma1 4000_8000 - Same as Slave 0, different base address - Slave 3 n3xx_mgt_io_core 4000_c001 - 4000_cfff - - Same as Slave 1, different base address eth_dispatch 4000_d000 - 4000_dfff - - Same as Slave 1, different base address eth_switch 4000_e000 - 4000_efff - - Same as Slave 1, different base address - -Slave 4 n310_core 4001_0000 COMPAT_NUM R FPGA Compat Number +Slave 4 n3xx_core 4001_0000 COMPAT_NUM R FPGA Compat Number [31:16] Major RO - [15:0] Minor RO - 4001_0004 DATESTAMP RO - 4001_0008 GIT_HASH RO - 4001_000C SCRATCH RO - - 4001_0010 NUM_CE RO Number of Computation Engines (RFNoC Blocks) - 4001_0014 NUM_IO_CE RO Number of fixed IO CEs - Radios + DMA Fifo + 4001_0010 REG_DEVICE_ID RW RFNoC Device ID + 4001_0014 REG_RFNOC_INFO RO RFNoC Information + [31:16] CHDR_W RO RFNoC CHDR Width in Bits + [15:0] RFNOC_PROTOVER RO RFNoC Protocol Version 4001_0018 CLOCK_CTRL [0] pps select (internal 10 MHz)RWOne-hot encoded pps_select to use the external PPS input. [1] pps select (internal 25 MHz)RWOne-hot encoded pps_select to use the internally generated PPS with a 10 MHz ref_clk. @@ -1264,54 +1263,53 @@ Slave 6 | 4001_8000 - 4001_bfff | dboard-regs1 | Daughterboard control, sl [11:0] FPGA temperatureRO 4001_0020 BUS_CLK_RATE RO - 4001_0024 BUS_CLK_COUNT RO - - axi_crossbar 4001_1010 XBAR_VERSION RO See crossbar kernel driver - 4001_1014 XBAR_NUM_PORTS RO See crossbar kernel driver - 4001_1018 LOCAL_ADDR RW See crossbar kernel driver - 4001_1020 remote_offset WO XBAR settings reg - 4001_1420 local_offset WO XBAR settings reg - n3xx_mgt_io_core (NPIO0) 4001_0200 PORT_INFO RO + 4001_0028 SFP_PORT0_INFO RO - + 4001_002C SFP_PORT1_INFO RO - + 4001_0030 FP_GPIO_MASTER RO GPIO master select bits. One bit per GPIO. LSB is for GPIO 0. Set bit to 0 for Radio, 1 for PS. + 4001_0034 FP_GPIO_RADIO_SRC RO Radio channel source select bits. Two bits per GPIO. Bits [1:0] are for GPIO 0. Set to 00 for channel 0, 01 for channel 1, etc. + 4001_0048 NUM_TIMEKEEPERS RO Number of radio timekeepers + n3xx_mgt_io_core (NPIO0) 4001_0200 PORT_INFO RO 4001_0204 MAC_CTRL_STATUS RW 4001_0208 PHY_CTRL_STATUS RW 4001_0220 AURORA_OVERUNS RO 4001_0224 AURORA_CHECKSUM_ERRORSRO 4001_0228 AURORA_BIST_CHECKER_SAMPSRO 4001_022c AURORA_BIST_CHECKER_ERRORSRO - n3xx_mgt_io_core (NPIO1) 4001_0240 PORT_INFO RO + n3xx_mgt_io_core (NPIO1) 4001_0240 PORT_INFO RO 4001_0244 MAC_CTRL_STATUS RW 4001_0248 PHY_CTRL_STATUS RW 4001_0260 AURORA_OVERUNS RO 4001_0264 AURORA_CHECKSUM_ERRORSRO 4001_0268 AURORA_BIST_CHECKER_SAMPSRO 4001_026c AURORA_BIST_CHECKER_ERRORSRO - n3xx_mgt_io_core (QSFP0) 4001_0280 PORT_INFORO + n3xx_mgt_io_core (QSFP0) 4001_0280 PORT_INFORO 4001_0284 MAC_CTRL_STATUSRW 4001_0288 PHY_CTRL_STATUSRW 4001_02a0 AURORA_OVERUNSRO 4001_02a4 AURORA_CHECKSUM_ERRORSRO 4001_02a8 AURORA_BIST_CHECKER_SAMPSRO 4001_02ac AURORA_BIST_CHECKER_ERRORSRO - n3xx_mgt_io_core (QSFP1) 4001_02c0 PORT_INFORO + n3xx_mgt_io_core (QSFP1) 4001_02c0 PORT_INFORO 4001_02c4 MAC_CTRL_STATUSRW 4001_02c8 PHY_CTRL_STATUSRW 4001_02e0 AURORA_OVERUNSRO 4001_02e4 AURORA_CHECKSUM_ERRORSRO 4001_02e8 AURORA_BIST_CHECKER_SAMPSRO 4001_02ec AURORA_BIST_CHECKER_ERRORSRO - n3xx_mgt_io_core (QSFP2) 4001_0300 PORT_INFORO + n3xx_mgt_io_core (QSFP2) 4001_0300 PORT_INFORO 4001_0304 MAC_CTRL_STATUSRW 4001_0308 PHY_CTRL_STATUSRW 4001_0320 AURORA_OVERUNSRO 4001_0324 AURORA_CHECKSUM_ERRORSRO 4001_0328 AURORA_BIST_CHECKER_SAMPSRO 4001_032c AURORA_BIST_CHECKER_ERRORSRO - n3xx_mgt_io_core (QSFP3) 4001_0340 PORT_INFORO + n3xx_mgt_io_core (QSFP3) 4001_0340 PORT_INFORO 4001_0344 MAC_CTRL_STATUSRW 4001_0348 PHY_CTRL_STATUSRW 4001_0360 AURORA_OVERUNSRO 4001_0364 AURORA_CHECKSUM_ERRORSRO 4001_0368 AURORA_BIST_CHECKER_SAMPSRO 4001_036C AURORA_BIST_CHECKER_ERRORSRO - Slave 5 4001_40004001_41FFClockingsee Clocking regmap 4001_42004001_43FFSyncsee Sync regmap 4001_44004001_45FFopenopenopen -- cgit v1.2.3