From d8d7c89ec3e08c1af31d343f0e5c1f2cfe36a205 Mon Sep 17 00:00:00 2001 From: Vidush Date: Mon, 14 May 2018 11:41:39 -0700 Subject: Docs: Update phase testing commands & instructions. --- host/docs/rd_testing.dox | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/host/docs/rd_testing.dox b/host/docs/rd_testing.dox index a9251cffd..0ee78b9e3 100644 --- a/host/docs/rd_testing.dox +++ b/host/docs/rd_testing.dox @@ -476,14 +476,7 @@ Software Required 7. Set Signal Generator output power at -30 dBm. 8. From the top of the UHD source, run the command: - ./tools/gr-usrptest/apps/usrp_phasealignment.py - --spec "A:0 A:1 B:0 B:1" --channels 0,1,2,3 \ - --sync pps --time-source external --clock-source external \ - -s 5e6 -g 75 -f 10e6 \ - --freq-bands 12 --start-freq 10e6 --stop-freq 6e9 \ - --duration 2.0 --auto \ - --lo-export True,False,False,False \ - --lo-source internal,companion,external,external + - `./tools/gr-usrptest/apps/usrp_phasealignment.py --spec "A:0 A:1 B:0 B:1" --channels 0,1,2,3 --sync pps --time-source external --clock-source external -s 5e6 -g 75 -f 10e6 --freq-bands 12 --start-freq 10e6 --stop-freq 6e9 --duration 2.0 --auto --lo-export True,False,False,False --lo-source internal,companion,external,external` 9. At each frequency step, tune Signal Generator to the displayed frequency + 1 MHz and increase output power by 3 dB. 10. Analyze terminal output. The "run avg" across all runs should not deviate more than 1 degree and the "stddev" for any run should not deviate more than 1 degree. @@ -497,14 +490,7 @@ Software Required 6. Set Signal Generator output power at -30 dBm. 7. From the top of the UHD source, run the command: - ./tools/gr-usrptest/apps/usrp_phasealignment.py - --args "addr0=,addr1=,dboard_clock_rate=25e6" \ - --clock-source external --time-source external --sync pps \ - --spec "A:0" --channels 0,1 \ - -s 10e6 -g 25 -f \ \ - --freq-bands \<# frequency bands> \ - --start-freq \ --stop-freq \ \ - --duration 2.0 --auto + - `./tools/gr-usrptest/apps/usrp_phasealignment.py --args "addr0=,addr1=,dboard_clock_rate=25e6" --clock-source external --time-source external --sync pps --spec "A:0" --channels 0,1 -s 10e6 -g 25 -f \ --freq-bands \<# frequency bands\> --start-freq \ --stop-freq \ --duration 2.0 --auto` 8. At each frequency step, tune Signal Generator to the displayed frequency + 1 MHz and increase output power by 3 dB. 9. Analyze terminal output. The "run avg" across all runs should not deviate more than 2 degrees and the "stddev" for any run should not deviate more than 2 degrees. @@ -515,17 +501,12 @@ Software Required 3. Connect host to master device via 1 GbE. 4. Connect 10 MHz and PPS from Octoclock-G to master device only. 5. Connect Signal Generator to input of splitter and outputs of the splitter to the RX2 port on each daughterboard. -6. Set Signal Generator output power at -30 dBm. +6. Set Signal Generator output power at -36 dBm. 7. From the top of the UHD source, run the command: - ./tools/gr-usrptest/apps/usrp_phasealignment.py - --args "addr0=\,addr1=\" \ - --clock-source external,mimo --time-source external,mimo --sync pps \ - --channels 0,1 -s 10e6 -f 400e6 -g 31.5 \ - --freq-bands 7 --start-freq 400e6 --stop-freq 4400e6 \ - --duration 2.0 --auto + - `./tools/gr-usrptest/apps/usrp_phasealignment.py --args "addr0=,addr1=" --clock-source external,mimo --time-source external,mimo --sync pps --channels 0,1 -s 10e6 -f 400e6 -g 31.5 --freq-bands 7 --start-freq 400e6 --stop-freq 4400e6 --duration 2.0 --auto` -8. At each frequency step, tune Signal Generator to the displayed frequency + 1 MHz and increase output power by 3 dB. +8. At each frequency step, tune Signal Generator to the displayed frequency + 1 MHz and increase output power by 2 dB. 9. Analyze terminal output. The "run avg" across all runs should not deviate more than 2 degrees and the "stddev" for any run should not deviate more than 5 degrees. \subsection rdtesting_phase_rx_auto Automatic phase alignment testing (Receiver) -- cgit v1.2.3