From bd455159a0b60eb2c496322d0f80c3ca77d838f6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Jul 2010 16:46:01 -0700 Subject: moved forward from the old branch --- usrp2/extramfifo/fifo_extram.v | 188 +++++++++++++ usrp2/extramfifo/fifo_extram36.v | 47 ++++ usrp2/extramfifo/fifo_extram36_tb.build | 1 + usrp2/extramfifo/fifo_extram36_tb.v | 475 ++++++++++++++++++++++++++++++++ usrp2/extramfifo/fifo_extram_tb.build | 1 + usrp2/extramfifo/fifo_extram_tb.v | 134 +++++++++ usrp2/fifo/fifo18_to_fifo36.v | 20 ++ usrp2/fifo/fifo_2clock_cascade.v | 14 +- 8 files changed, 876 insertions(+), 4 deletions(-) create mode 100644 usrp2/extramfifo/fifo_extram.v create mode 100644 usrp2/extramfifo/fifo_extram36.v create mode 100644 usrp2/extramfifo/fifo_extram36_tb.build create mode 100644 usrp2/extramfifo/fifo_extram36_tb.v create mode 100644 usrp2/extramfifo/fifo_extram_tb.build create mode 100644 usrp2/extramfifo/fifo_extram_tb.v create mode 100644 usrp2/fifo/fifo18_to_fifo36.v diff --git a/usrp2/extramfifo/fifo_extram.v b/usrp2/extramfifo/fifo_extram.v new file mode 100644 index 000000000..4e1f40371 --- /dev/null +++ b/usrp2/extramfifo/fifo_extram.v @@ -0,0 +1,188 @@ + +// Everything on sram_clk + +module fifo_extram + (input reset, input clear, + input [17:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input [15:0] occ_in, + output [17:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input [15:0] space_in, + input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we, + output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, + output sram_mode, output sram_zz); + + localparam AWIDTH = 19; // 1 MB in x18 + localparam RAMSIZE = ((1< 1); + else + can_store <= (occ_in > 2); + + reg can_retrieve; + always @* + if(empty | ~dst_rdy_i) + can_retrieve <= 0; + else if(do_retr_del == 0) + can_retrieve <= 1; + else if((do_retr_del == 1) || (do_retr_del == 2)) + can_retrieve <= (space_in > 1); + else + can_retrieve <= (space_in > 2); + + reg [1:0] state; + localparam IDLE_STORE_NEXT = 0; + localparam STORE = 1; + localparam IDLE_RETR_NEXT = 2; + localparam RETRIEVE = 3; + + reg [7:0] countdown; + wire countdown_done = (countdown == 0); + + localparam CYCLE_SIZE = 6; + + assign do_store = can_store & (state == STORE); + assign do_retrieve = can_retrieve & (state == RETRIEVE); + always @(posedge sram_clk) + if(reset) + do_store_del <= 0; + else + do_store_del <= {do_store_del[0],do_store}; + + always @(posedge sram_clk) + if(reset) + do_retr_del <= 0; + else + do_retr_del <= {do_retr_del[0],do_retrieve}; + + always @(posedge sram_clk) + if(reset | clear) + begin + state <= IDLE_STORE_NEXT; + countdown <= 0; + end + else + case(state) + IDLE_STORE_NEXT : + if(can_store) + begin + state <= STORE; + countdown <= CYCLE_SIZE; + end + else if(can_retrieve) + begin + state <= RETRIEVE; + countdown <= CYCLE_SIZE; + end + STORE : + if(~can_store | (can_retrieve & countdown_done)) + state <= IDLE_RETR_NEXT; + else if(~countdown_done) + countdown <= countdown - 1; + IDLE_RETR_NEXT : + if(can_retrieve) + begin + state <= RETRIEVE; + countdown <= CYCLE_SIZE; + end + else if(can_store) + begin + state <= STORE; + countdown <= CYCLE_SIZE; + end + RETRIEVE : + if(~can_retrieve | (can_store & countdown_done)) + state <= IDLE_STORE_NEXT; + else if(~countdown_done) + countdown <= countdown - 1; + endcase // case (state) + + // RAM wires + assign sram_bw = 0; + assign sram_adv = 0; + assign sram_mode = 0; + assign sram_zz = 0; + assign sram_ce = 0; + + assign sram_a = (state==STORE) ? addr_store : addr_retrieve; + assign sram_we = ~do_store; + assign sram_oe = ~do_retr_del[1]; + assign my_oe = do_store_del[1] & sram_oe; + assign sram_d = my_oe ? datain : 18'bz; + + // FIFO wires + assign dataout = sram_d; + assign src_rdy_o = do_retr_del[1]; + assign dst_rdy_o = do_store_del[1]; + +endmodule // fifo_extram + + + //wire have_1 = (fullness == 1); + //wire have_2 = (fullness == 2); + //wire have_atleast_1 = ~empty; + //wire have_atleast_2 = ~(empty | have_1); + //wire have_atleast_3 = ~(empty | have_1 | have_2); + //wire full_minus_1 = (fullness == (RAMSIZE-1)); // 19'h7FE); + //wire full_minus_2 = (fullness == (RAMSIZE-2)); // 19'h7FD); + //wire spacefor_atleast_1 = ~full; + //wire spacefor_atleast_2 = ~(full | full_minus_1); + //wire spacefor_atleast_3 = ~(full | full_minus_1 | full_minus_2); diff --git a/usrp2/extramfifo/fifo_extram36.v b/usrp2/extramfifo/fifo_extram36.v new file mode 100644 index 000000000..29342fdc4 --- /dev/null +++ b/usrp2/extramfifo/fifo_extram36.v @@ -0,0 +1,47 @@ + +// 18 bit interface means we either can't handle errors or can't handle odd lengths +// unless we go to heroic measures + +module fifo_extram36 + (input clk, input reset, input clear, + input [35:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we, + output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, output sram_mode, + output sram_zz); + + wire [17:0] f18_data_1, f18_data_2, f18_data_3, f18_data_4; + wire f18_src_rdy_1, f18_dst_rdy_1, f18_src_rdy_2, f18_dst_rdy_2; + wire f18_src_rdy_3, f18_dst_rdy_3, f18_src_rdy_4, f18_dst_rdy_4; + + fifo36_to_fifo18 f36_to_f18 + (.clk(clk), .reset(reset), .clear(clear), + .f36_datain(datain), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .f18_dataout(f18_data_1), .f18_src_rdy_o(f18_src_rdy_1), .f18_dst_rdy_i(f18_dst_rdy_1) ); + + wire [15:0] f1_occ, f2_space; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_in + (.wclk(clk), .datain(f18_data_1), .src_rdy_i(f18_src_rdy_1), .dst_rdy_o(f18_dst_rdy_1), .space(), + .rclk(sram_clk), .dataout(f18_data_2), .src_rdy_o(f18_src_rdy_2), .dst_rdy_i(f18_dst_rdy_2), .short_occupied(f1_occ), + .arst(reset) ); + + fifo_extram fifo_extram + (.reset(reset), .clear(clear), + .datain(f18_data_2), .src_rdy_i(f18_src_rdy_2), .dst_rdy_o(f18_dst_rdy_2), .space(), .occ_in(f1_occ), + .dataout(f18_data_3), .src_rdy_o(f18_src_rdy_3), .dst_rdy_i(f18_dst_rdy_3), .occupied(), .space_in(f2_space), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_out + (.wclk(sram_clk), .datain(f18_data_3), .src_rdy_i(f18_src_rdy_3), .dst_rdy_o(f18_dst_rdy_3), .short_space(f2_space), + .rclk(clk), .dataout(f18_data_4), .src_rdy_o(f18_src_rdy_4), .dst_rdy_i(f18_dst_rdy_4), .occupied(), + .arst(reset) ); + + fifo18_to_fifo36 f18_to_f36 + (.clk(clk), .reset(reset), .clear(clear), + .f18_datain(f18_data_4), .f18_src_rdy_i(f18_src_rdy_4), .f18_dst_rdy_o(f18_dst_rdy_4), + .f36_dataout(dataout), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i) ); + +endmodule // fifo_extram36 diff --git a/usrp2/extramfifo/fifo_extram36_tb.build b/usrp2/extramfifo/fifo_extram36_tb.build new file mode 100644 index 000000000..699591889 --- /dev/null +++ b/usrp2/extramfifo/fifo_extram36_tb.build @@ -0,0 +1 @@ +iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v diff --git a/usrp2/extramfifo/fifo_extram36_tb.v b/usrp2/extramfifo/fifo_extram36_tb.v new file mode 100644 index 000000000..f28c35e4f --- /dev/null +++ b/usrp2/extramfifo/fifo_extram36_tb.v @@ -0,0 +1,475 @@ +`timescale 1ns/1ns + +module fifo_extram36_tb(); + + reg clk = 0; + reg sram_clk = 0; + reg rst = 1; + reg clear = 0; + + reg Verbose = 0; // + integer ErrorCount = 0; + + initial #1000 rst = 0; +// always #125 clk = ~clk; + task task_CLK; + reg [7:0] ran; + begin + while (1) begin + ran = $random; + if (ran[1]) + #62 clk = ~clk; + else + #63 clk = !clk; + end + end + endtask // task_CLK + initial task_CLK; + +// always #100 sram_clk = ~sram_clk; + task task_SSRAM_clk; + reg [7:0] ran; + begin + while (1) begin + ran = $random; + if (ran[0]) + #49 sram_clk = ~sram_clk; + else + #51 sram_clk = ~sram_clk; + end + end + endtask // task_SSRAM_clk + initial task_SSRAM_clk; + + reg [31:0] f36_data = 32'hX; + reg [1:0] f36_occ = 0; + reg f36_sof = 0, f36_eof = 0; + + wire [35:0] f36_in = {1'b0,f36_occ,f36_eof,f36_sof,f36_data}; + reg src_rdy_f36i = 0; + wire dst_rdy_f36i; + + wire [35:0] f36_out; + wire src_rdy_f36o; + reg dst_rdy_f36o = 0; + + wire [17:0] sram_d; + wire [18:0] sram_a; + wire [1:0] sram_bw; + wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz; + + reg [31:0] ScoreBoard [524288:0]; + reg [18:0] put_index = 0; + reg [18:0] get_index = 0; + +// integer put_index = 0; +// integer get_index = 0; + + wire [15:0] DUT_space, DUT_occupied; + + fifo_extram36 fifo_extram36 + (.clk(clk), .reset(rst), .clear(clear), + .datain(f36_in), .src_rdy_i(src_rdy_f36i), .dst_rdy_o(dst_rdy_f36i), .space(DUT_space), + .dataout(f36_out), .src_rdy_o(src_rdy_f36o), .dst_rdy_i(dst_rdy_f36o), .occupied(DUT_occupied), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + +`define idt 1 +`ifdef idt + wire [15:0] dummy16; + wire [1:0] dummy2; + + idt71v65603s150 + ram_model(.A(sram_a[17:0]), + .adv_ld_(sram_adv), // advance (high) / load (low) + .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low) + .ce1_(0), .ce2(1), .ce2_(0), // chip enables + .cen_(sram_ce), // clock enable (low) + .clk(sram_clk), // clock + .IO({dummy16,sram_d[15:0]}), + .IOP({dummy2,sram_d[17:16]}), // data bus + .lbo_(sram_mode), // linear burst order (low) + .oe_(sram_oe), // output enable (low) + .r_w_(sram_we)); // read (high) / write (low) +`else + cy1356 ram_model(.d(sram_d),.clk(~sram_clk),.a(sram_a), + .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv), + .ce1b(0),.ce2(1),.ce3b(0), + .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) ); +`endif + + task task_SSRAMMonitor; + reg last_mode; + reg last_clock; + reg last_load; + reg [18:0] sram_addr; + + begin + last_mode = 1'bX; + last_clock = 1'bX; + last_load = 1'bX; + + @ (posedge Verbose); + $dumpvars(0,fifo_extram36_tb); + + $display("%t:%m\t*** Task Started",$time); + while (1) @ (posedge sram_clk) begin + if (sram_mode !== last_mode) begin + $display("%t:%m\tSSRAM mode: %b",$time,sram_mode); + last_mode = sram_mode; + end + if (sram_adv !== last_load) begin + $display("%t:%m\tSSRAM adv/load: %b",$time,sram_adv); + last_load = sram_adv; + end + if (sram_ce !== last_clock) begin + $display("%t:%m\tSSRAM clock enable: %b",$time,sram_ce); + last_clock = sram_ce; + end + if (sram_ce == 1'b0) begin + if (sram_adv == 1'b0) begin +// $display("%t:%m\tSSRAM Address Load A=%h",$time,sram_a); + sram_addr = sram_a; + end else begin + sram_addr = sram_addr + 1; + end + if (sram_oe == 1'b0) begin + $display("%t:%m\tSSRAM Read Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d); + end + if (sram_we == 1'b0) begin + $display("%t:%m\tSSRAM Write Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d); + end + if ((sram_we == 1'b0) && (sram_oe == 1'b0)) begin + $display("%t:%m\t*** ERROR: _oe and _we both active",$time); + end + + end // if (sram_ce == 1'b0) + + end // always @ (posedge sram_clk) + end + endtask // task_SSRAMMonitor + + task ReadFromFIFO36; + begin + $display("%t: Read from FIFO36",$time); + #1 dst_rdy_f36o <= 1; + while(1) + begin + while(~src_rdy_f36o) + @(posedge clk); + $display("%t: Read: %h>",$time,f36_out); + @(posedge clk); + end + end + endtask // ReadFromFIFO36 + + initial dst_rdy_f36o = 0; + + task task_ReadFIFO36; + reg [7:0] ran; + begin + $display("%t:%m\t*** Task Started",$time); + while (1) begin + // Read on one of four clocks + #5 dst_rdy_f36o <= 1; + @(posedge clk); + if (src_rdy_f36o) begin + if (f36_out[31:0] != ScoreBoard[get_index]) begin + $display("%t:%m\tFIFO Get Error: R:%h, E:%h (%h)",$time,f36_out[31:0],ScoreBoard[get_index],get_index); + ErrorCount = ErrorCount + 1; + end else begin + if (Verbose) + $display("%t:%m\t(%5h) %o>",$time,get_index,f36_out); + end + get_index = get_index+1; + end else begin + if (ErrorCount >= 192) + $finish; + end // else: !if(src_rdy_f36o) + + #10; + ran = $random; + if (ran[2:0] != 3'b000) begin + dst_rdy_f36o <= 0; + if (ran[2] != 1'b0) begin + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + if (ran[1] != 1'b0) begin + @(posedge clk); + @(posedge clk); + end + if (ran[0] != 1'b0) begin + @(posedge clk); + end + end + end // while (1) + end + + endtask // task_ReadFIFO36 + + + reg [15:0] count; + + task PutPacketInFIFO36; + input [31:0] data_start; + input [31:0] data_len; + + begin + count = 4; + src_rdy_f36i = 1; + f36_data = data_start; + f36_sof = 1; + f36_eof = 0; + f36_occ = 0; + + $display("%t: Put Packet in FIFO36",$time); + while(~dst_rdy_f36i) + #1; //@(posedge clk); + @(posedge clk); + + $display("%t: <%h PPI_FIFO36: Entered First Line",$time,f36_data); + f36_sof <= 0; + while(count+4 < data_len) + begin + f36_data = f36_data + 32'h01010101; + count = count + 4; + while(~dst_rdy_f36i) + #1; //@(posedge clk); + @(posedge clk); + $display("%t: <%h PPI_FIFO36: Entered New Line",$time,f36_data); + end + f36_data <= f36_data + 32'h01010101; + f36_eof <= 1; + if(count + 4 == data_len) + f36_occ <= 0; + else if(count + 3 == data_len) + f36_occ <= 3; + else if(count + 2 == data_len) + f36_occ <= 2; + else + f36_occ <= 1; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + f36_occ <= 0; + f36_eof <= 0; + f36_data <= 0; + src_rdy_f36i <= 0; + $display("%t: <%h PPI_FIFO36: Entered Last Line",$time,f36_data); + end + endtask // PutPacketInFIFO36 + + task task_WriteFIFO36; + integer i; + reg [7:0] ran; + + begin + f36_data = 32'bX; + if (rst != 1'b0) + @ (negedge rst); + $display("%t:%m\t*** Task Started",$time); + #10; + src_rdy_f36i = 1; + f36_data = $random; + for (i=0; i<64; i=i+0 ) begin + @ (posedge clk) ; + if (dst_rdy_f36i) begin + if (Verbose) + $display("%t:%m\t(%5h) %o<",$time,put_index,f36_in); + ScoreBoard[put_index] = f36_in[31:0]; + put_index = put_index + 1; + #5; + f36_data = $random; + i = i + 1; + end + ran = $random; + if (ran[1:0] != 2'b00) begin + @ (negedge clk); + src_rdy_f36i = 0; + #5; + @ (negedge clk) ; + src_rdy_f36i = 1; + end + end + src_rdy_f36i = 0; + f36_data = 32'bX; +//* if (put_index > 19'h3ff00) +//* Verbose = 1'b1; + + end + endtask // task_WriteFIFO36 + + initial $dumpfile("fifo_extram36_tb.vcd"); +// initial $dumpvars(0,fifo_extram36_tb); + initial $timeformat(-9, 0, " ns", 10); + initial task_SSRAMMonitor; + + initial + begin + @(negedge rst); + #40000; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); +// ReadFromFIFO36; + task_ReadFIFO36; + + end + + integer i; + + initial + begin + @(negedge rst); + @(posedge clk); + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + @(posedge clk); + @(posedge clk); +// PutPacketInFIFO36(32'hA0B0C0D0,12); + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); +// PutPacketInFIFO36(32'hE0F0A0B0,36); + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + for (i=0; i<8192; i = i+1) begin + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + end + +// $dumpvars(0,fifo_extram36_tb); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + + #100000000; + $finish; + + end + */ + + initial + begin + @(negedge rst); + f36_occ <= 0; + repeat (100) + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= 32'h10203040; + f36_sof <= 1; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= 32'h1F2F3F4F; + f36_sof <= 0; + f36_eof <= 1; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 0; + + + + end + +// initial #500000 $finish; +endmodule // fifo_extram_tb diff --git a/usrp2/extramfifo/fifo_extram_tb.build b/usrp2/extramfifo/fifo_extram_tb.build new file mode 100644 index 000000000..e87217e5c --- /dev/null +++ b/usrp2/extramfifo/fifo_extram_tb.build @@ -0,0 +1 @@ +iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v diff --git a/usrp2/extramfifo/fifo_extram_tb.v b/usrp2/extramfifo/fifo_extram_tb.v new file mode 100644 index 000000000..73550d9ca --- /dev/null +++ b/usrp2/extramfifo/fifo_extram_tb.v @@ -0,0 +1,134 @@ +module fifo_extram_tb(); + + reg clk = 0; + reg sram_clk = 0; + reg reset = 1; + reg clear = 0; + + initial #1000 reset = 0; + always #125 clk = ~clk; + always #100 sram_clk = ~sram_clk; + + reg [15:0] f18_data = 0; + reg f18_sof = 0, f18_eof = 0; + + wire [17:0] f18_in = {f18_eof,f18_sof,f18_data}; + reg src_rdy_f18i = 0; + wire dst_rdy_f18i; + + wire [17:0] f18_out; + wire src_rdy_f18o; + reg dst_rdy_f18o = 0; + + wire [17:0] f18_int; + wire src_rdy_f18int, dst_rdy_f18int; + + wire [17:0] sram_d; + wire [18:0] sram_a; + wire [1:0] sram_bw; + wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz; + wire [15:0] f1_occ; + + fifo_short #(.WIDTH(18)) fifo_short + (.clk(sram_clk), .reset(reset), .clear(clear), + .datain(f18_in), .src_rdy_i(src_rdy_f18i), .dst_rdy_o(dst_rdy_f18i), .space(), + .dataout(f18_int), .src_rdy_o(src_rdy_f18int), .dst_rdy_i(dst_rdy_f18int), .occupied(f1_occ[4:0]) ); + + assign f1_occ[15:5] = 0; + + fifo_extram fifo_extram + (.reset(reset), .clear(clear), + .datain(f18_int), .src_rdy_i(src_rdy_f18int), .dst_rdy_o(dst_rdy_f18int), .space(), .occ_in(f1_occ), + .dataout(f18_out), .src_rdy_o(src_rdy_f18o), .dst_rdy_i(dst_rdy_f18o), .occupied(), .space_in(7), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + +`define idt 1 +`ifdef idt + wire [15:0] dummy16; + wire [1:0] dummy2; + + idt71v65603s150 + ram_model(.A(sram_a[17:0]), + .adv_ld_(sram_adv), // advance (high) / load (low) + .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low) + .ce1_(0), .ce2(1), .ce2_(0), // chip enables + .cen_(sram_ce), // clock enable (low) + .clk(sram_clk), // clock + .IO({dummy16,sram_d[15:0]}), + .IOP({dummy2,sram_d[17:16]}), // data bus + .lbo_(sram_mode), // linear burst order (low) + .oe_(sram_oe), // output enable (low) + .r_w_(sram_we)); // read (high) / write (low) +`else + cy1356 ram_model(.d(sram_d),.clk(sram_clk),.a(sram_a), + .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv), + .ce1b(0),.ce2(1),.ce3b(0), + .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) ); +`endif // !`ifdef idt + + always @(posedge sram_clk) + if(dst_rdy_f18o & src_rdy_f18o) + $display("Read: %h",f18_out); + + always @(posedge sram_clk) + if(dst_rdy_f18int & src_rdy_f18int) + $display("Write: %h",f18_int); + + initial $dumpfile("fifo_extram_tb.vcd"); + initial $dumpvars(0,fifo_extram_tb); + + task SendPkt; + input [15:0] data_start; + input [31:0] data_len; + begin + @(posedge sram_clk); + f18_data = data_start; + f18_sof = 1; + f18_eof = 0; + src_rdy_f18i = 1; + while(~dst_rdy_f18i) + #1; + @(posedge sram_clk); + repeat(data_len - 2) + begin + f18_data = f18_data + 16'h0101; + f18_sof = 0; + while(~dst_rdy_f18i) + @(posedge sram_clk); + + @(posedge sram_clk); + end + f18_data = f18_data + 16'h0101; + f18_eof = 1; + while(~dst_rdy_f18i) + #1; + @(posedge sram_clk); + src_rdy_f18i = 0; + f18_data = 0; + f18_eof = 0; + end + endtask // SendPkt + + initial + begin + @(negedge reset); + @(posedge sram_clk); + @(posedge sram_clk); + #10000; + @(posedge sram_clk); + SendPkt(16'hA0B0, 100); + #10000; + //SendPkt(16'hC0D0, 220); + end + + initial + begin + #20000; + dst_rdy_f18o = 1; + end + + initial #200000 $finish; +endmodule // fifo_extram_tb + diff --git a/usrp2/fifo/fifo18_to_fifo36.v b/usrp2/fifo/fifo18_to_fifo36.v new file mode 100644 index 000000000..25bb215a1 --- /dev/null +++ b/usrp2/fifo/fifo18_to_fifo36.v @@ -0,0 +1,20 @@ + +// For now just assume FIFO18 is same as FIFO19 without occupancy bit + +module fifo18_to_fifo36 + (input clk, input reset, input clear, + input [17:0] f18_datain, + input f18_src_rdy_i, + output f18_dst_rdy_o, + + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i + ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk), .reset(reset), .clear(clear), + .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o), + .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) ); + +endmodule // fifo18_to_fifo36 diff --git a/usrp2/fifo/fifo_2clock_cascade.v b/usrp2/fifo/fifo_2clock_cascade.v index 5ce726977..4e8c244c2 100644 --- a/usrp2/fifo/fifo_2clock_cascade.v +++ b/usrp2/fifo/fifo_2clock_cascade.v @@ -1,8 +1,10 @@ module fifo_2clock_cascade #(parameter WIDTH=32, SIZE=9) - (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, - input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, + output [15:0] space, output [15:0] short_space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, + output [15:0] occupied, output [15:0] short_occupied, input arst); wire [WIDTH-1:0] data_int1, data_int2; @@ -29,7 +31,11 @@ module fifo_2clock_cascade .space(s2_space), .occupied(s2_occupied)); // Be conservative -- Only advertise space from input side of fifo, occupied from output side - assign space = {11'b0,s1_space} + l_space; - assign occupied = {11'b0,s2_occupied} + l_occupied; + assign space = {11'b0,s1_space} + l_space; + assign occupied = {11'b0,s2_occupied} + l_occupied; + + // For the fifo_extram, we only want to know the immediately adjacent space + assign short_space = {11'b0,s1_space}; + assign short_occupied = {11'b0,s2_occupied}; endmodule // fifo_2clock_cascade -- cgit v1.2.3 From 886606f55da066b66d214e512a2226b19a1073df Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Jul 2010 17:01:25 -0700 Subject: get it to build --- usrp2/extramfifo/.gitignore | 3 + usrp2/extramfifo/fifo_extram36_tb.build | 2 +- usrp2/extramfifo/fifo_extram36_tb.v | 6 +- usrp2/extramfifo/fifo_extram_tb.build | 2 +- usrp2/models/idt71v65603s150.v | 301 ++++++++++++++++++++++++++++++++ 5 files changed, 309 insertions(+), 5 deletions(-) create mode 100644 usrp2/extramfifo/.gitignore mode change 100644 => 100755 usrp2/extramfifo/fifo_extram36_tb.build mode change 100644 => 100755 usrp2/extramfifo/fifo_extram_tb.build create mode 100755 usrp2/models/idt71v65603s150.v diff --git a/usrp2/extramfifo/.gitignore b/usrp2/extramfifo/.gitignore new file mode 100644 index 000000000..94bbf6dcc --- /dev/null +++ b/usrp2/extramfifo/.gitignore @@ -0,0 +1,3 @@ +fifo_extram36_tb +fifo_extram_tb +*.vcd diff --git a/usrp2/extramfifo/fifo_extram36_tb.build b/usrp2/extramfifo/fifo_extram36_tb.build old mode 100644 new mode 100755 index 699591889..ac9369758 --- a/usrp2/extramfifo/fifo_extram36_tb.build +++ b/usrp2/extramfifo/fifo_extram36_tb.build @@ -1 +1 @@ -iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v diff --git a/usrp2/extramfifo/fifo_extram36_tb.v b/usrp2/extramfifo/fifo_extram36_tb.v index f28c35e4f..e5f8cef4c 100644 --- a/usrp2/extramfifo/fifo_extram36_tb.v +++ b/usrp2/extramfifo/fifo_extram36_tb.v @@ -296,8 +296,8 @@ module fifo_extram36_tb(); end src_rdy_f36i = 0; f36_data = 32'bX; -//* if (put_index > 19'h3ff00) -//* Verbose = 1'b1; +// if (put_index > 19'h3ff00) +// Verbose = 1'b1; end endtask // task_WriteFIFO36 @@ -385,7 +385,7 @@ module fifo_extram36_tb(); $finish; end - */ + initial begin diff --git a/usrp2/extramfifo/fifo_extram_tb.build b/usrp2/extramfifo/fifo_extram_tb.build old mode 100644 new mode 100755 index e87217e5c..5607c8691 --- a/usrp2/extramfifo/fifo_extram_tb.build +++ b/usrp2/extramfifo/fifo_extram_tb.build @@ -1 +1 @@ -iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v diff --git a/usrp2/models/idt71v65603s150.v b/usrp2/models/idt71v65603s150.v new file mode 100755 index 000000000..457dfa6dd --- /dev/null +++ b/usrp2/models/idt71v65603s150.v @@ -0,0 +1,301 @@ +/******************************************************************************* + * + * File Name : idt71v65603s150.v + * Product : IDT71V65603 + * Function : 256K x 36 pipeline ZBT Static RAM + * Simulation Tool/Version : Verilog-XL 2.5 + * Date : 07/19/00 + * + * Copyright 1999 Integrated Device Technology, Inc. + * + * Revision Notes: 07/19/00 Rev00 + * + ******************************************************************************/ +/******************************************************************************* + * Module Name: idt71v65603s150 + * + * Notes : This model is believed to be functionally + * accurate. Please direct any inquiries to + * IDT SRAM Applications at: sramhelp@idt.com + * + *******************************************************************************/ + + /*************************************************************** + * + * Integrated Device Technology, Inc. ("IDT") hereby grants the + * user of this Verilog/VCS model a non-exclusive, nontransferable + * license to use this Verilog/VCS model under the following terms. + * The user is granted this license only to use the Verilog/VCS + * model and is not granted rights to sell, copy (except as needed + * to run the IBIS model), rent, lease or sub-license the Verilog/VCS + * model in whole or in part, or in modified form to anyone. The User + * may modify the Verilog/VCS model to suit its specific applications, + * but rights to derivative works and such modifications shall belong + * to IDT. + * + * This Verilog/VCS model is provided on an "AS IS" basis and + * IDT makes absolutely no warranty with respect to the information + * contained herein. IDT DISCLAIMS AND CUSTOMER WAIVES ALL + * WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE + * ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE + * USER ACCORDINGLY, IN NO EVENT SHALL IDT BE LIABLE + * FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN CONTRACT OR + * TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, + * CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF + * THE USE OR APPLICATION OF THE VERILOG/VCS model. Further, + * IDT reserves the right to make changes without notice to any + * product herein to improve reliability, function, or design. + * IDT does not convey any license under patent rights or + * any other intellectual property rights, including those of + * third parties. IDT is not obligated to provide maintenance + * or support for the licensed Verilog/VCS model. + * + ***************************************************************/ + + `timescale 1ns/100ps + +module idt71v65603s150 (A, + adv_ld_, // advance (high) / load (low) + bw1_, bw2_, bw3_, bw4_, // byte write enables (low) + ce1_, ce2, ce2_, // chip enables + cen_, // clock enable (low) + clk, // clock + IO, IOP, // data bus + lbo_, // linear burst order (low) + oe_, // output enable (low) + r_w_); // read (high) / write (low) + +initial +begin + $write("\n********************************************************\n"); + $write(" idt71v65603s150, 256K x 36 Pipelined burst ZBT SRAM \n"); + $write(" Rev: 00 July 2000 \n"); + $write(" copyright 1997,1998,1999,2000 by IDT, Inc. \n"); + $write("********************************************************\n\n"); +end + +input [17:0] A; +inout [31:0] IO; +inout [4:1] IOP; +input adv_ld_, bw1_, bw2_, bw3_, bw4_, ce1_, ce2, ce2_, + cen_, clk, lbo_, oe_, r_w_; + + +//internal registers for data, address, etc +reg [8:0] mem1[0:262143]; //memory array +reg [8:0] mem2[0:262143]; //memory array +reg [8:0] mem3[0:262143]; //memory array +reg [8:0] mem4[0:262143]; //memory array + +reg [35:0] dout; +reg [17:0] addr_a, + addr_b; +reg wren_a, wren_b; +reg cs_a, cs_b; +reg bw_a1, bw_b1; +reg bw_a2, bw_b2; +reg bw_a3, bw_b3; +reg bw_a4, bw_b4; +reg [1:0] brst_cnt; + +wire[35:0] data_out; +wire doe; +wire cs = (~ce1_ & ce2 & ~ce2_); +wire baddr0, baddr1; + + +parameter regdelay = 0.2; +parameter outdly = 0.2; + +specify +specparam +//Clock Parameters + tCYC = 6.7, //clock cycle time + tCH = 2.0, //clock high time + tCL = 2.0, //clock low time + +//Output Parameters + tCD = 3.8, //clk to data valid + tCLZ = 1.5, //clk to output Low-Z + tCHZ = 3.0, //clk to data Hi-Z + tOE = 3.8, //OE to output valid + tOLZ = 0.0, //OE to output Hi-Z + tOHZ = 3.8, //OE to output Hi-Z + +//Set up times + tSE = 1.5, //clock enable set-up + tSA = 1.5, //address set-up + tSD = 1.5, //data set-up + tSW = 1.5, //Read/Write set-up + tSADV = 1.5, //Advance/Load set-up + tSC = 1.5, //Chip enable set-up + tSB = 1.5, //Byte write enable set-up + +//Hold times + tHE = 0.5, //clock enable hold + tHA = 0.5, //address hold + tHD = 0.5, //data hold + tHW = 0.5, //Read/Write hold + tHADV = 0.5, //Advance/Load hold + tHC = 0.5, //Chip enable hold + tHB = 0.5; //Byte write enable hold + + + (oe_ *> IO) = (tOE,tOE,tOHZ,tOLZ,tOHZ,tOLZ); //(01,10,0z,z1,1z,z0) + (clk *> IO) = (tCD,tCD,tCHZ,tCLZ,tCHZ,tCLZ); //(01,10,0z,z1,1z,z0) + + (oe_ *> IOP) = (tOE,tOE,tOHZ,tOLZ,tOHZ,tOLZ); //(01,10,0z,z1,1z,z0) + (clk *> IOP) = (tCD,tCD,tCHZ,tCLZ,tCHZ,tCLZ); //(01,10,0z,z1,1z,z0) + +//timing checks + + $period(posedge clk, tCYC ); + $width (posedge clk, tCH ); + $width (negedge clk, tCL ); + + + $setuphold(posedge clk, A, tSA, tHA); + $setuphold(posedge clk, IO, tSD, tHD); + $setuphold(posedge clk, IOP, tSD, tHD); + $setuphold(posedge clk, adv_ld_, tSADV, tHADV); + $setuphold(posedge clk, bw1_, tSB, tHB); + $setuphold(posedge clk, bw2_, tSB, tHB); + $setuphold(posedge clk, bw3_, tSB, tHB); + $setuphold(posedge clk, bw4_, tSB, tHB); + $setuphold(posedge clk, ce1_, tSC, tHC); + $setuphold(posedge clk, ce2, tSC, tHC); + $setuphold(posedge clk, ce2_, tSC, tHC); + $setuphold(posedge clk, cen_, tSE, tHE); + $setuphold(posedge clk, r_w_, tSW, tHW); + +endspecify + +initial begin + cs_a = 0; + cs_b = 0; +end + + +///////////////////////////////////////////////////////////////////////// +//input registers +//-------------------- +always @(posedge clk) +begin + if ( ~cen_ & ~adv_ld_ ) cs_a <= #regdelay cs; + if ( ~cen_ ) cs_b <= #regdelay cs_a; + + if ( ~cen_ & ~adv_ld_ ) wren_a <= #regdelay (cs & ~r_w_); + if ( ~cen_ ) wren_b <= #regdelay wren_a; + + if ( ~cen_ ) bw_a1 <= #regdelay ~bw1_; + if ( ~cen_ ) bw_a2 <= #regdelay ~bw2_; + if ( ~cen_ ) bw_a3 <= #regdelay ~bw3_; + if ( ~cen_ ) bw_a4 <= #regdelay ~bw4_; + + if ( ~cen_ ) bw_b1 <= #regdelay bw_a1; + if ( ~cen_ ) bw_b2 <= #regdelay bw_a2; + if ( ~cen_ ) bw_b3 <= #regdelay bw_a3; + if ( ~cen_ ) bw_b4 <= #regdelay bw_a4; + + if ( ~cen_ & ~adv_ld_ ) addr_a[17:0] <= #regdelay A[17:0]; + if ( ~cen_ ) addr_b[17:0] <= #regdelay {addr_a[17:2], baddr1, baddr0}; +end + + +///////////////////////////////////////////////////////////////////////// +//burst counter +//-------------------- +always @(posedge clk) +begin + if ( lbo_ & ~cen_ & ~adv_ld_) brst_cnt <= #regdelay 0; + else if (~lbo_ & ~cen_ & ~adv_ld_) brst_cnt <= #regdelay A[1:0]; + else if ( ~cen_ & adv_ld_) brst_cnt <= #regdelay brst_cnt + 1; +end + + +///////////////////////////////////////////////////////////////////////// +//address logic +//-------------------- +assign baddr1 = lbo_ ? (brst_cnt[1] ^ addr_a[1]) : brst_cnt[1]; +assign baddr0 = lbo_ ? (brst_cnt[0] ^ addr_a[0]) : brst_cnt[0]; + + +///////////////////////////////////////////////////////////////////////// +//data output register +//-------------------- +always @(posedge clk) +begin + #regdelay; + #regdelay; + dout[8:0] = mem1[addr_b]; + dout[17:9] = mem2[addr_b]; + dout[26:18] = mem3[addr_b]; + dout[35:27] = mem4[addr_b]; +end + +assign data_out = dout; + + +///////////////////////////////////////////////////////////////////////// +//Output buffers: using a bufif1 has the same effect as... +// +// assign D = doe ? data_out : 36'hz; +// +//It was coded this way to support SPECIFY delays in the specparam section. +//-------------------- +bufif1 #outdly (IO[0],data_out[0],doe); +bufif1 #outdly (IO[1],data_out[1],doe); +bufif1 #outdly (IO[2],data_out[2],doe); +bufif1 #outdly (IO[3],data_out[3],doe); +bufif1 #outdly (IO[4],data_out[4],doe); +bufif1 #outdly (IO[5],data_out[5],doe); +bufif1 #outdly (IO[6],data_out[6],doe); +bufif1 #outdly (IO[7],data_out[7],doe); +bufif1 #outdly (IOP[1],data_out[8],doe); + +bufif1 #outdly (IO[8],data_out[9],doe); +bufif1 #outdly (IO[9],data_out[10],doe); +bufif1 #outdly (IO[10],data_out[11],doe); +bufif1 #outdly (IO[11],data_out[12],doe); +bufif1 #outdly (IO[12],data_out[13],doe); +bufif1 #outdly (IO[13],data_out[14],doe); +bufif1 #outdly (IO[14],data_out[15],doe); +bufif1 #outdly (IO[15],data_out[16],doe); +bufif1 #outdly (IOP[2],data_out[17],doe); + +bufif1 #outdly (IO[16],data_out[18],doe); +bufif1 #outdly (IO[17],data_out[19],doe); +bufif1 #outdly (IO[18],data_out[20],doe); +bufif1 #outdly (IO[19],data_out[21],doe); +bufif1 #outdly (IO[20],data_out[22],doe); +bufif1 #outdly (IO[21],data_out[23],doe); +bufif1 #outdly (IO[22],data_out[24],doe); +bufif1 #outdly (IO[23],data_out[25],doe); +bufif1 #outdly (IOP[3],data_out[26],doe); + +bufif1 #outdly (IO[24],data_out[27],doe); +bufif1 #outdly (IO[25],data_out[28],doe); +bufif1 #outdly (IO[26],data_out[29],doe); +bufif1 #outdly (IO[27],data_out[30],doe); +bufif1 #outdly (IO[28],data_out[31],doe); +bufif1 #outdly (IO[29],data_out[32],doe); +bufif1 #outdly (IO[30],data_out[33],doe); +bufif1 #outdly (IO[31],data_out[34],doe); +bufif1 #outdly (IOP[4],data_out[35],doe); + +assign doe = cs_b & ~wren_b & ~oe_ ; + + +///////////////////////////////////////////////////////////////////////// +// write to ram +//------------- +always @(posedge clk) +begin + if (wren_b & bw_b1 & ~cen_) mem1[addr_b] = {IOP[1], IO[7:0]}; + if (wren_b & bw_b2 & ~cen_) mem2[addr_b] = {IOP[2], IO[15:8]}; + if (wren_b & bw_b3 & ~cen_) mem3[addr_b] = {IOP[3], IO[23:16]}; + if (wren_b & bw_b4 & ~cen_) mem4[addr_b] = {IOP[4], IO[31:24]}; +end + +endmodule -- cgit v1.2.3 From 8cd762bdbcbd6a43a2fcc1c0b523cc14bfd7ab69 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 29 Jul 2010 21:25:26 -0700 Subject: Checkpoint checkin. Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet. --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 165 ++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 82 +++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v | 165 ++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco | 82 +++++++ usrp2/extramfifo/Makefile.srcs | 16 ++ usrp2/extramfifo/ext_fifo.v | 120 +++++++++++ usrp2/extramfifo/ext_fifo_tb.cmd | 11 + usrp2/extramfifo/ext_fifo_tb.prj | 9 + usrp2/extramfifo/ext_fifo_tb.sh | 1 + usrp2/extramfifo/ext_fifo_tb.v | 285 +++++++++++++++++++++++++ usrp2/extramfifo/nobl_fifo.v | 264 +++++++++++++++++++++++ usrp2/extramfifo/nobl_if.v | 136 ++++++++++++ usrp2/extramfifo/test_sram_if.v | 171 +++++++++++++++ 13 files changed, 1507 insertions(+) create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco create mode 100644 usrp2/extramfifo/Makefile.srcs create mode 100644 usrp2/extramfifo/ext_fifo.v create mode 100644 usrp2/extramfifo/ext_fifo_tb.cmd create mode 100644 usrp2/extramfifo/ext_fifo_tb.prj create mode 100644 usrp2/extramfifo/ext_fifo_tb.sh create mode 100644 usrp2/extramfifo/ext_fifo_tb.v create mode 100644 usrp2/extramfifo/nobl_fifo.v create mode 100644 usrp2/extramfifo/nobl_if.v create mode 100644 usrp2/extramfifo/test_sram_if.v diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v new file mode 100644 index 000000000..1d7a5ca2a --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v @@ -0,0 +1,165 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating +// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_18to36( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full); + + +input [17 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; + +// synthesis translate_off + + FIFO_GENERATOR_V4_4 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(10), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(18), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(0), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("1kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(1022), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(1024), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(10), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .RD_DATA_COUNT(), + .UNDERFLOW(), + .WR_ACK(), + .WR_DATA_COUNT(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco new file mode 100644 index 000000000..df97fd0e0 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Jul 29 23:02:41 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk_18to36 +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=1023 +CSET full_threshold_negate_value=1022 +CSET input_data_width=18 +CSET input_depth=1024 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=10 +# END Parameters +GENERATE +# CRC: 117ae77f + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v new file mode 100644 index 000000000..f7f6e7e9f --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v @@ -0,0 +1,165 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating +// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_36to18( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [17 : 0] dout; +output empty; +output full; + +// synthesis translate_off + + FIFO_GENERATOR_V4_4 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(18), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(0), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(509), + .C_PROG_FULL_THRESH_NEGATE_VAL(508), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(1024), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(10), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .RD_DATA_COUNT(), + .UNDERFLOW(), + .WR_ACK(), + .WR_DATA_COUNT(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco new file mode 100644 index 000000000..a1c75dc39 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Jul 29 18:10:59 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk_36to18 +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=509 +CSET full_threshold_negate_value=508 +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=18 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: 392ad537 + diff --git a/usrp2/extramfifo/Makefile.srcs b/usrp2/extramfifo/Makefile.srcs new file mode 100644 index 000000000..7cd49f4f6 --- /dev/null +++ b/usrp2/extramfifo/Makefile.srcs @@ -0,0 +1,16 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Extram Sources +################################################## +EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extramfifo/, \ +ext_fifo.v \ +nobl_if.v \ +nobl_fifo.v \ +icon.v \ +icon.xco \ +ila.v \ +ila.xco \ +)) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v new file mode 100644 index 000000000..55935146a --- /dev/null +++ b/usrp2/extramfifo/ext_fifo.v @@ -0,0 +1,120 @@ +module ext_fifo + #(parameter INT_WIDTH=36,EXT_WIDTH=18,DEPTH=19) + ( + input int_clk, + input ext_clk, + input rst, + input [EXT_WIDTH-1:0] RAM_D_pi, + output [EXT_WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + input [INT_WIDTH-1:0] datain, + input src_rdy_i, // WRITE + output dst_rdy_o, // not FULL + output [INT_WIDTH-1:0] dataout, + output src_rdy_o, // not EMPTY + input dst_rdy_i // READ + ); + + wire [EXT_WIDTH-1:0] write_data; + wire [EXT_WIDTH-1:0] read_data; + wire full1, empty1; + wire full2, empty2; + + + // FIFO buffers data from UDP engine into external FIFO clock domain. + fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( + .rst(rst), + .wr_clk(int_clk), + .rd_clk(ext_clk), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(space_avail&~empty1), + // .rd_en(~full2&~empty1), + .dout(write_data), // Bus [17 : 0] + .full(full1), + .empty(empty1)); + assign dst_rdy_o = ~full1; + + + + // External FIFO running at ext clock rate and 18 bit width. + nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH)) + nobl_fifo_i1 + ( + .clk(ext_clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .write_data(write_data), + .write_strobe(space_avail & ~empty1 ), + .space_avail(space_avail), + .read_data(read_data), + .read_strobe(data_avail & ~full2), + .data_avail(data_avail) + ); + + + + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. + fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [17 : 0] + // .din(write_data), // Bus [17 : 0] + .wr_en(data_avail & ~full2 ), + // .wr_en(~full2&~empty1), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .empty(empty2)); + assign src_rdy_o = ~empty2; + + + + wire [35:0] CONTROL0; + reg [7:0] datain_reg,write_data_reg,read_data_reg ; + reg space_avail_reg,data_avail_reg,empty1_reg,full2_reg ; + + always @(posedge ext_clk) + begin + //datain_reg <= datain[7:0]; + write_data_reg <= write_data[7:0]; + read_data_reg <= read_data[7:0]; + space_avail_reg <= space_avail; + data_avail_reg <= data_avail; + empty1_reg <= empty1; + full2_reg <= full2; + end + + + icon icon_i1 + ( + .CONTROL0(CONTROL0) + ); + + ila ila_i1 + ( + .CLK(ext_clk), + .CONTROL(CONTROL0), + // .TRIG0(address_reg), + .TRIG0(write_data_reg[7:0]), + .TRIG1(read_data_reg[7:0]), + .TRIG2(0), + .TRIG3({space_avail_reg,data_avail_reg,empty1_reg,full2_reg}) + ); + +endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.cmd b/usrp2/extramfifo/ext_fifo_tb.cmd new file mode 100644 index 000000000..b0ab830dc --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.cmd @@ -0,0 +1,11 @@ +/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v +-y . +-y ../coregen/ +-y ../models +-y /home/ianb/usrp-fpga/usrp2/sdr_lib +-y /home/ianb/usrp-fpga/usrp2/control_lib +-y /home/ianb/usrp-fpga/usrp2/models +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib + diff --git a/usrp2/extramfifo/ext_fifo_tb.prj b/usrp2/extramfifo/ext_fifo_tb.prj new file mode 100644 index 000000000..a11a15b2f --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.prj @@ -0,0 +1,9 @@ +verilog work "./ext_fifo_tb.v" +verilog work "./ext_fifo.v" +verilog work "./nobl_fifo.v" +verilog work "./nobl_if.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v" +verilog work "../models/CY7C1356C/cy1356.v" +verilog work "../models/idt71v65603s150.v" +verilog work "$XILINX/verilog/src/glbl.v" diff --git a/usrp2/extramfifo/ext_fifo_tb.sh b/usrp2/extramfifo/ext_fifo_tb.sh new file mode 100644 index 000000000..a56574102 --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.sh @@ -0,0 +1 @@ +fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v new file mode 100644 index 000000000..aa1fd6e3c --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -0,0 +1,285 @@ +`timescale 1ns / 1ps +`define INT_WIDTH 36 +`define EXT_WIDTH 18 +`define DEPTH 19 +`define DUMP_VCD_FULL + +module ext_fifo_tb(); + + + reg int_clk; + reg ext_clk; + reg rst; + + + + wire [`EXT_WIDTH-1:0] RAM_D_pi; + wire [`EXT_WIDTH-1:0] RAM_D_po; + wire [`EXT_WIDTH-1:0] RAM_D; + wire RAM_D_poe; + wire [`DEPTH-1:0] RAM_A; + wire RAM_WEn; + wire RAM_CENn; + wire RAM_LDn; + wire RAM_OEn; + wire RAM_CE1n; + reg [`INT_WIDTH-1:0] datain; + reg src_rdy_i; // WRITE + wire dst_rdy_o; // not FULL + wire [`INT_WIDTH-1:0] dataout; + reg [`INT_WIDTH-1:0] ref_dataout; + wire src_rdy_o; // not EMPTY + reg dst_rdy_i; + + + // Clocks + // Int clock is 100MHz + // Ext clock is 125MHz + initial + begin + int_clk <= 0; + ext_clk <= 0; + datain <= 0; + ref_dataout <= 1; + src_rdy_i <= 0; + dst_rdy_i <= 0; + end + + always + #5 int_clk <= ~int_clk; + + always + #4 ext_clk <= ~ext_clk; + + + initial + begin + rst <= 1; + repeat (5) @(negedge int_clk); + rst <= 0; + @(negedge int_clk); + repeat (1000) + begin + @(negedge int_clk); + datain <= datain + 1; + src_rdy_i <= 1; + @(negedge int_clk); + src_rdy_i <= 0; +// @(negedge int_clk); +// dst_rdy_i <= src_rdy_o; +// @(negedge int_clk); +// dst_rdy_i <= 0; + repeat (2) @(negedge int_clk); + end // repeat (1000) + // Fall through fifo, first output already valid + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + repeat (1000) + begin + @(negedge int_clk); + datain <= datain + 1; + src_rdy_i <= 1; + @(negedge int_clk); + src_rdy_i <= 0; + @(negedge int_clk); + ref_dataout <= ref_dataout + 1; + dst_rdy_i <= src_rdy_o; + @(negedge int_clk); + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + dst_rdy_i <= 0; +// repeat (2) @(negedge int_clk); + end // repeat (1000) + repeat (1000) + begin +// @(negedge int_clk); +// datain <= datain + 1; +// src_rdy_i <= 1; +// @(negedge int_clk); +// src_rdy_i <= 0; + @(negedge int_clk); + ref_dataout <= ref_dataout + 1; + dst_rdy_i <= src_rdy_o; + @(negedge int_clk); + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + dst_rdy_i <= 0; +// repeat (2) @(negedge int_clk); + end // repeat (1000) + + $finish; + + end // initial begin + + + /////////////////////////////////////////////////////////////////////////////////// + // Simulation control // + /////////////////////////////////////////////////////////////////////////////////// + `ifdef DUMP_LX2_TOP + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.lx2"); + $dumpvars(1,ext_fifo_tb); + end + `endif + + `ifdef DUMP_LX2_FULL + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.lx2"); + $dumpvars(0,ext_fifo_tb); + end + `endif + + `ifdef DUMP_VCD_TOP + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(1,ext_fifo_tb); + end + `endif + + `ifdef DUMP_VCD_TOP_PLUS_NEXT + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(2,ext_fifo_tb); + end + `endif + + + `ifdef DUMP_VCD_FULL + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(0,ext_fifo_tb); + end + `endif + + // Update display every 10 us + always #10000 $monitor("Time in uS ",$time/1000); + + wire [`EXT_WIDTH-1:0] RAM_D_pi_ext; + wire [`EXT_WIDTH-1:0] RAM_D_po_ext; + wire [`EXT_WIDTH-1:0] RAM_D_ext; + wire RAM_D_poe_ext; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi_ext[i]), + .I(RAM_D_po_ext[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe_ext) + ); + end // block: gen_RAM_D_IO + + endgenerate + + wire [`DEPTH-1:0] RAM_A_ext; + wire RAM_WEn_ext,RAM_LDn_ext,RAM_CE1n_ext,RAM_OEn_ext,RAM_CENn_ext; + + assign #1 RAM_D_pi = RAM_D_pi_ext; + + assign #1 RAM_D_po_ext = RAM_D_po; + + assign #1 RAM_D_poe_ext = RAM_D_poe; + + assign #2 RAM_WEn_ext = RAM_WEn; + + assign #2 RAM_LDn_ext = RAM_LDn; + + assign #2 RAM_CE1n_ext = RAM_CE1n; + + assign #2 RAM_OEn_ext = RAM_OEn; + + assign #2 RAM_CENn_ext = RAM_CENn; + + assign #2 RAM_A_ext = RAM_A; + +/* -----\/----- EXCLUDED -----\/----- + wire [13:0] temp1; + assign temp1 = 14'h0; + wire [3:0] temp2; + assign temp2 = 4'h0; + -----/\----- EXCLUDED -----/\----- */ + + + idt71v65603s150 idt71v65603s150_i1 + ( + .A(RAM_A_ext[17:0]), + .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) + .bw1_(1'b0), + .bw2_(1'b0), + .bw3_(1'b1), + .bw4_(1'b1), // byte write enables (low) + .ce1_(RAM_CE1n_ext), + .ce2(1'b1), + .ce2_(1'b0), // chip enables + .cen_(RAM_CENn_ext), // clock enable (low) + .clk(ext_clk), // clock + .IO({RAM_D[16:9],RAM_D[7:0]}), + .IOP({RAM_D[17],RAM_D[8]}), // data bus + .lbo_(1'b0), // linear burst order (low) + .oe_(RAM_OEn_ext), // output enable (low) + .r_w_(RAM_WEn_ext) + ); // read (high) / write (low) + +/* -----\/----- EXCLUDED -----\/----- + + + cy1356 cy1356_i1 + ( .d(RAM_D), + .clk(ext_clk), + .a(RAM_A_ext), + .bws(2'b00), + .we_b(RAM_WEn_ext), + .adv_lb(RAM_LDn_ext), + .ce1b(RAM_CE1n_ext), + .ce2(1'b1), + .ce3b(1'b0), + .oeb(RAM_OEn_ext), + .cenb(RAM_CENn_ext), + .mode(1'b0) + ); + -----/\----- EXCLUDED -----/\----- */ + + + ext_fifo + #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.DEPTH(`DEPTH)) + ext_fifo_i1 + ( + .int_clk(int_clk), + .ext_clk(ext_clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain(datain), + .src_rdy_i(src_rdy_i), // WRITE + .dst_rdy_o(dst_rdy_o), // not FULL + .dataout(dataout), + .src_rdy_o(src_rdy_o), // not EMPTY + .dst_rdy_i(dst_rdy_i) + ); + +endmodule // ext_fifo_tb diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v new file mode 100644 index 000000000..1bd7439ad --- /dev/null +++ b/usrp2/extramfifo/nobl_fifo.v @@ -0,0 +1,264 @@ +module nobl_fifo + #(parameter WIDTH=18,DEPTH=19) + ( + input clk, + input rst, + input [WIDTH-1:0] RAM_D_pi, + output [WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + input [WIDTH-1:0] write_data, + input write_strobe, + output reg space_avail, + output reg [WIDTH-1:0] read_data, + input read_strobe, + output reg data_avail + ); + + reg [DEPTH-1:0] capacity; + reg [DEPTH-1:0] wr_pointer; + reg [DEPTH-1:0] rd_pointer; + wire [DEPTH-1:0] address; + + reg supress; + reg data_avail_int; // Data available with high latency from ext FIFO flag + wire [WIDTH-1:0] data_in; + wire data_in_valid; + reg [WIDTH-1:0] read_data_pending; + reg pending_avail; + wire read_strobe_int; + + + + assign read = read_strobe_int && data_avail_int; + assign write = write_strobe && space_avail; + + // When a read and write collision occur, supress availability flags next cycle + // and complete write followed by read over 2 cycles. This forces balanced arbitration + // and makes for a simple logic design. + + always @(posedge clk) + if (rst) + begin + capacity <= 1 << (DEPTH-1); + wr_pointer <= 0; + rd_pointer <= 0; + space_avail <= 0; + data_avail_int <= 0; + supress <= 0; + end + else + begin + space_avail <= ~((capacity == 0) || (read&&write) || (capacity == 1 && write) ); + // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. + data_avail_int <= ~((capacity == (1 << (DEPTH-1))) || (read&&write) || (capacity == ((1 << (DEPTH-1))-1) && read) ); + supress <= read && write; + wr_pointer <= wr_pointer + write; + rd_pointer <= rd_pointer + ((~write && read) || supress); + capacity <= capacity - write + ((~write && read) || supress); // REVISIT + end // else: !if(rst) + + assign address = write ? wr_pointer : rd_pointer; + assign enable = write || read || supress; + + // + // Need to have first item in external FIFO moved into local registers for single cycle latency and throughput on read. + // 2 local registers are provided so that a read every other clock cycle can be sustained. + // No fowarding logic is provided to bypass the external FIFO as latency is of no concern. + // + always @(posedge clk) + if (rst) + begin + read_data <= 0; + data_avail <= 0; + read_data_pending <= 0; + pending_avail <= 0; + end + else + begin + case({read_strobe,data_in_valid}) + // No read externally, no new data arriving from external FIFO + 2'b00: begin + case({data_avail,pending_avail}) + // Start Data empty, Pending empty. + // + // End Data full, Pending empty + 2'b00: begin + read_data <= read_data; + data_avail <= data_avail; + read_data_pending <= read_data_pending ; + pending_avail <= pending_avail; + end + // Start Data empty, Pending full. + // Data <= Pending, + // End Data full, Penidng empty. + 2'b01: begin + read_data <= read_data_pending; + data_avail <= 1'b1; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + // Start Data full, Pending empty. + // + // End Data full, Pending empty + 2'b10: begin + read_data <= read_data; + data_avail <= data_avail; + read_data_pending <= read_data_pending ; + pending_avail <= pending_avail; + end + // Start Data full, Pending full. + // + // End Data full, Pending full. + 2'b11: begin + read_data <= read_data; + data_avail <= data_avail; + read_data_pending <= read_data_pending ; + pending_avail <= pending_avail; + end + endcase + end + // No read externally, new data arriving from external FIFO + 2'b01: begin + case({data_avail,pending_avail}) + // Start Data empty, Pending empty. + // Data <= FIFO + // End Data full, Pending empty + 2'b00: begin + read_data <= data_in; + data_avail <= 1'b1; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + // Start Data empty, Pending full. + // Data <= Pending, Pending <= FIFO + // End Data full, Penidng full. + 2'b01: begin + read_data <= read_data_pending; + data_avail <= 1'b1; + read_data_pending <= data_in ; + pending_avail <= 1'b1; + end + // Start Data full, Pending empty. + // Pending <= FIFO + // End Data full, Pending full + 2'b10: begin + read_data <= read_data; + data_avail <= 1'b1; + read_data_pending <= data_in ; + pending_avail <= 1'b1; + end + // Data full, Pending full. + // *ILLEGAL STATE* + 2'b11: begin + + end + endcase + end + // Read externally, no new data arriving from external FIFO + 2'b10: begin + case({data_avail,pending_avail}) + // Start Data empty, Pending empty. + // *ILLEGAL STATE* + 2'b00: begin + + end + // Start Data empty, Pending full. + // *ILLEGAL STATE* + 2'b01: begin + + end + // Start Data full, Pending empty. + // Out <= Data + // End Data empty, Pending empty. + 2'b10: begin + read_data <= read_data; + data_avail <= 1'b0; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + // Start Data full, Pending full. + // Out <= Data, + // End Data full, Pending empty + 2'b11: begin + read_data <= read_data_pending; + data_avail <= 1'b1; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + endcase + end + // Read externally, new data arriving from external FIFO + 2'b11: begin + case({data_avail,pending_avail}) + // Start Data empty, Pending empty. + // *ILLEGAL STATE* + 2'b00: begin + + end + // Start Data empty, Pending full. + // *ILLEGAL STATE* + 2'b01: begin + + end + // Start Data full, Pending empty. + // Out <= Data, Data <= FIFO + // End Data full, Pending empty. + 2'b10: begin + read_data <= data_in; + data_avail <= 1'b1; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + // Start Data full, Pending full. + // Out <= Data, Data <= Pending, Pending <= FIFO + // End Data full, Pending full + 2'b11: begin + read_data <= read_data_pending; + data_avail <= 1'b1; + read_data_pending <= data_in ; + pending_avail <= 1'b1; + end + endcase + end + endcase + end + + // Start an external FIFO read as soon as a read of the buffer reg is strobed to minimise refill latency. + // If the buffer reg or the pending buffer reg is already empty also pre-emptively start a read. + // However there must be something in ext FIFO to read. + // This means that there can be 2 outstanding reads to the ext FIFO active at any time helping to hide latency. + assign read_strobe_int = (read_strobe & data_avail & ~pending_avail) || (~data_avail && ~pending_avail); + + + // + // Simple NoBL SRAM interface, 4 cycle read latency. + // Read/Write arbitration via temprary application of empty/full flags. + // + nobl_if nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(write_data), + .data_in(data_in), + .data_in_valid(data_in_valid), + .write(write), + .enable(enable) + ); + +endmodule // nobl_fifo diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v new file mode 100644 index 000000000..3143ce5ba --- /dev/null +++ b/usrp2/extramfifo/nobl_if.v @@ -0,0 +1,136 @@ +module nobl_if + #(parameter WIDTH=18,DEPTH=19) + ( + input clk, + input rst, + input [WIDTH-1:0] RAM_D_pi, + output [WIDTH-1:0] RAM_D_po, + output reg RAM_D_poe, + output [DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + input [DEPTH-1:0] address, + input [WIDTH-1:0] data_out, + output reg [WIDTH-1:0] data_in, + output reg data_in_valid, + input write, + input enable + ); + + + reg enable_pipe1; + reg [DEPTH-1:0] address_pipe1; + reg write_pipe1; + reg [WIDTH-1:0] data_out_pipe1; + + reg enable_pipe2; + reg write_pipe2; + reg [WIDTH-1:0] data_out_pipe2; + + reg enable_pipe3; + reg write_pipe3; + reg [WIDTH-1:0] data_out_pipe3; + + assign RAM_LDn = 0; + assign RAM_OEn = 0; + + + // + // Pipeline stage 1 + // + always @(posedge clk) + if (rst) + begin + enable_pipe1 <= 0; + address_pipe1 <= 0; + write_pipe1 <= 0; + data_out_pipe1 <= 0; + end + else + begin + enable_pipe1 <= enable; + + if (enable) + begin + address_pipe1 <= address; + write_pipe1 <= write; + + if (write) + data_out_pipe1 <= data_out; + end + end // always @ (posedge clk) + + // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM + assign RAM_A = address_pipe1; + assign RAM_CENn = 1'b0; + assign RAM_WEn = ~write_pipe1; + assign RAM_CE1n = ~enable_pipe1; + + // + // Pipeline stage2 + // + always @(posedge clk) + if (rst) + begin + enable_pipe2 <= 0; + data_out_pipe2 <= 0; + write_pipe2 <= 0; + end + else + begin + data_out_pipe2 <= data_out_pipe1; + write_pipe2 <= write_pipe1; + enable_pipe2 <= enable_pipe1; + end + + // + // Pipeline stage3 + // + always @(posedge clk) + if (rst) + begin + enable_pipe3 <= 0; + data_out_pipe3 <= 0; + write_pipe3 <= 0; + RAM_D_poe <= 0; + end + else + begin + data_out_pipe3 <= data_out_pipe2; + write_pipe3 <= write_pipe2; + enable_pipe3 <= enable_pipe2; + RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx. + end + + // Pipeline 3 drives write data on NoBL SRAM + assign RAM_D_po = data_out_pipe3; + + + // + // Pipeline stage4 + // + always @(posedge clk) + if (rst) + begin + data_in_valid <= 0; + data_in <= 0; + end + else + begin + data_in <= RAM_D_pi; + if (enable_pipe3 & ~write_pipe3) + begin + // Read data now available to be registered. + data_in_valid <= 1'b1; + end + else + data_in_valid <= 1'b0; + end // always @ (posedge clk) + + + + +endmodule // nobl_if diff --git a/usrp2/extramfifo/test_sram_if.v b/usrp2/extramfifo/test_sram_if.v new file mode 100644 index 000000000..9f36b409c --- /dev/null +++ b/usrp2/extramfifo/test_sram_if.v @@ -0,0 +1,171 @@ +`define WIDTH 18 +`define DEPTH 19 + +module test_sram_if + ( + input clk, + input rst, + input [`WIDTH-1:0] RAM_D_pi, + output [`WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [`DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + output reg correct + ); + + reg [`DEPTH-1:0] write_count; + reg [`DEPTH-1:0] read_count; + reg enable; + reg write; + reg write_cycle; + reg read_cycle; + reg enable_reads; + reg [18:0] address; + reg [17:0] data_out; + wire [17:0] data_in; + wire data_in_valid; + + reg [17:0] check_data; + reg [17:0] check_data_old; + reg [17:0] check_data_old2; + + // + // Create counter that generates both external modulo 2^19 address and modulo 2^18 data to test RAM. + // + + always @(posedge clk) + if (rst) + begin + write_count <= 19'h0; + read_count <= 19'h0; + end + else if (write_cycle) // Write cycle + if (write_count == 19'h7FFFF) + begin + write_count <= 19'h0; + end + else + begin + write_count <= write_count + 1'b1; + end + else if (read_cycle) // Read cycle + if (read_count == 19'h7FFFF) + begin + read_count <= 19'h0; + end + else + begin + read_count <= read_count + 1'b1; + end + + always @(posedge clk) + if (rst) + begin + enable_reads <= 0; + read_cycle <= 0; + write_cycle <= 0; + end + else + begin + write_cycle <= ~write_cycle; + if (enable_reads) + read_cycle <= write_cycle; + if (write_count == 15) // Enable reads 15 writes after reset terminates. + enable_reads <= 1; + end // else: !if(rst) + + always @(posedge clk) + if (rst) + begin + enable <= 0; + end + else if (write_cycle) + begin + address <= write_count; + data_out <= write_count[17:0]; + enable <= 1; + write <= 1; + end + else if (read_cycle) + begin + address <= read_count; + check_data <= read_count[17:0]; + check_data_old <= check_data; + check_data_old2 <= check_data_old; + enable <= 1; + write <= 0; + end + else + enable <= 0; + + always @(posedge clk) + if (data_in_valid) + begin + correct <= (data_in == check_data_old2); + end + + + nobl_if nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(data_out), + .data_in(data_in), + .data_in_valid(data_in_valid), + .write(write), + .enable(enable) + ); + + + wire [35:0] CONTROL0; + reg [7:0] data_in_reg, data_out_reg, address_reg; + reg data_in_valid_reg,write_reg,enable_reg,correct_reg; + + always @(posedge clk) + begin + data_in_reg <= data_in[7:0]; + data_out_reg <= data_out[7:0]; + data_in_valid_reg <= data_in_valid; + write_reg <= write; + enable_reg <= enable; + correct_reg <= correct; + address_reg <= address; + + end + + + icon icon_i1 + ( + .CONTROL0(CONTROL0) + ); + + ila ila_i1 + ( + .CLK(clk), + .CONTROL(CONTROL0), + // .TRIG0(address_reg), + .TRIG0(data_in_reg[7:0]), + .TRIG1(data_out_reg[7:0]), + .TRIG2(address_reg[7:0]), + .TRIG3({data_in_valid_reg,write_reg,enable_reg,correct_reg}) + ); + + + +endmodule // test_sram_if + + \ No newline at end of file -- cgit v1.2.3 From 2e5effd0b664413c4d3cbbe08d3d841eee051dcc Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Sat, 31 Jul 2010 00:15:16 -0700 Subject: External FIFO tested in simulation and on USRP2 from decimation 64->8 with current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched. --- usrp2/coregen/Makefile.srcs | 4 + usrp2/coregen/coregen.cgp | 22 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 6 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 6 +- usrp2/extramfifo/ext_fifo.v | 76 +- usrp2/extramfifo/ext_fifo_tb.v | 36 +- usrp2/extramfifo/icon.v | 1286 ++++++ usrp2/extramfifo/icon.xco | 47 + usrp2/extramfifo/ila.v | 5544 ++++++++++++++++++++++++ usrp2/extramfifo/ila.xco | 130 + usrp2/extramfifo/nobl_fifo.v | 20 +- usrp2/extramfifo/nobl_if.v | 9 +- usrp2/extramfifo/test_sram_if.v | 4 + usrp2/fifo/fifo_cascade.v | 8 +- usrp2/top/Makefile.common | 1 + usrp2/top/u2_rev3/Makefile.udp | 2 + usrp2/top/u2_rev3/u2_core_udp.v | 57 +- usrp2/top/u2_rev3/u2_rev3.ucf | 86 +- usrp2/top/u2_rev3/u2_rev3.v | 221 +- 19 files changed, 7327 insertions(+), 238 deletions(-) create mode 100644 usrp2/extramfifo/icon.v create mode 100644 usrp2/extramfifo/icon.xco create mode 100644 usrp2/extramfifo/ila.v create mode 100644 usrp2/extramfifo/ila.xco diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs index 7b29225ca..a59696d15 100644 --- a/usrp2/coregen/Makefile.srcs +++ b/usrp2/coregen/Makefile.srcs @@ -16,4 +16,8 @@ fifo_xlnx_16x19_2clk.v \ fifo_xlnx_16x19_2clk.xco \ fifo_xlnx_16x40_2clk.v \ fifo_xlnx_16x40_2clk.xco \ +fifo_xlnx_512x36_2clk_36to18.v \ +fifo_xlnx_512x36_2clk_36to18.xco \ +fifo_xlnx_512x36_2clk_18to36.v \ +fifo_xlnx_512x36_2clk_18to36.xco \ )) diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp index 810d64dac..4c9201aff 100644 --- a/usrp2/coregen/coregen.cgp +++ b/usrp2/coregen/coregen.cgp @@ -1,20 +1,22 @@ -# Date: Thu Sep 3 17:40:48 2009 -SET addpads = False -SET asysymbol = False +# Date: Mon Jul 26 21:55:33 2010 + +SET addpads = false +SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False +SET createndf = false SET designentry = Verilog SET device = xc3s2000 SET devicefamily = spartan3 SET flowvendor = Other -SET formalverification = False -SET foundationsym = False +SET formalverification = false +SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 -SET removerpms = False +SET removerpms = false SET simulationfiles = Behavioral SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/matt/coregen/tmp +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = /tmp/ +# CRC: 394da717 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v index 1d7a5ca2a..32de19e8a 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v @@ -44,6 +44,7 @@ module fifo_xlnx_512x36_2clk_18to36( rst, wr_clk, wr_en, + almost_full, dout, empty, full); @@ -55,6 +56,7 @@ input rd_en; input rst; input wr_clk; input wr_en; +output almost_full; output [35 : 0] dout; output empty; output full; @@ -73,7 +75,7 @@ output full; .C_FAMILY("spartan3"), .C_FULL_FLAGS_RST_VAL(0), .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), + .C_HAS_ALMOST_FULL(1), .C_HAS_BACKUP(0), .C_HAS_DATA_COUNT(0), .C_HAS_INT_CLK(0), @@ -128,6 +130,7 @@ output full; .RST(rst), .WR_CLK(wr_clk), .WR_EN(wr_en), + .ALMOST_FULL(almost_full), .DOUT(dout), .EMPTY(empty), .FULL(full), @@ -145,7 +148,6 @@ output full; .SRST(), .WR_RST(), .ALMOST_EMPTY(), - .ALMOST_FULL(), .DATA_COUNT(), .OVERFLOW(), .PROG_EMPTY(), diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco index df97fd0e0..05ceffbe9 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version K.39 -# Date: Thu Jul 29 23:02:41 2010 +# Date: Fri Jul 30 20:43:00 2010 # ############################################################## # @@ -36,7 +36,7 @@ SELECT Fifo_Generator family Xilinx,_Inc. 4.4 # END Select # BEGIN Parameters CSET almost_empty_flag=false -CSET almost_full_flag=false +CSET almost_full_flag=true CSET component_name=fifo_xlnx_512x36_2clk_18to36 CSET data_count=false CSET data_count_width=10 @@ -78,5 +78,5 @@ CSET write_data_count=false CSET write_data_count_width=10 # END Parameters GENERATE -# CRC: 117ae77f +# CRC: 9b689ee4 diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 55935146a..a506d71e2 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -1,3 +1,20 @@ +// +// FIFO backed by an off chip ZBT/NoBL SRAM. +// +// This module and its sub-hierarchy implment a FIFO capable of sustaining +// a data throughput rate of at least int_clk/2 * 36bits and bursts of int_clk * 36bits. +// +// This has been designed and tested for an int_clk of 100MHz and an ext_clk of 125MHz, +// your milage may vary with other clock ratio's especially those where int_clk < ext_clk. +// Testing has also exclusively used a rst signal synchronized to int_clk. +// +// Interface operation mimics a Xilinx FIFO configured as "First Word Fall Through", +// though signal naming differs. +// +// For FPGA use registers interfacing directly with signals prefixed "RAM_*" should be +// packed into the IO ring. +// + module ext_fifo #(parameter INT_WIDTH=36,EXT_WIDTH=18,DEPTH=19) ( @@ -24,25 +41,24 @@ module ext_fifo wire [EXT_WIDTH-1:0] write_data; wire [EXT_WIDTH-1:0] read_data; wire full1, empty1; - wire full2, empty2; - + wire almost_full2, full2, empty2; + wire [INT_WIDTH-1:0] data_to_fifo; + wire [INT_WIDTH-1:0] data_from_fifo; + // FIFO buffers data from UDP engine into external FIFO clock domain. fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( .rst(rst), .wr_clk(int_clk), .rd_clk(ext_clk), - .din(datain), // Bus [35 : 0] - .wr_en(src_rdy_i), - .rd_en(space_avail&~empty1), - // .rd_en(~full2&~empty1), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(space_avail&~empty1), .dout(write_data), // Bus [17 : 0] .full(full1), .empty(empty1)); assign dst_rdy_o = ~full1; - - // External FIFO running at ext clock rate and 18 bit width. nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH)) nobl_fifo_i1 @@ -63,10 +79,10 @@ module ext_fifo .space_avail(space_avail), .read_data(read_data), .read_strobe(data_avail & ~full2), - .data_avail(data_avail) + .data_avail(data_avail), + .upstream_full(almost_full2) ); - - + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( @@ -74,47 +90,13 @@ module ext_fifo .wr_clk(ext_clk), .rd_clk(int_clk), .din(read_data), // Bus [17 : 0] - // .din(write_data), // Bus [17 : 0] .wr_en(data_avail & ~full2 ), - // .wr_en(~full2&~empty1), .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] + .dout(dataout), // Bus [35 : 0] .full(full2), + .almost_full(almost_full2), .empty(empty2)); assign src_rdy_o = ~empty2; - - wire [35:0] CONTROL0; - reg [7:0] datain_reg,write_data_reg,read_data_reg ; - reg space_avail_reg,data_avail_reg,empty1_reg,full2_reg ; - - always @(posedge ext_clk) - begin - //datain_reg <= datain[7:0]; - write_data_reg <= write_data[7:0]; - read_data_reg <= read_data[7:0]; - space_avail_reg <= space_avail; - data_avail_reg <= data_avail; - empty1_reg <= empty1; - full2_reg <= full2; - end - - - icon icon_i1 - ( - .CONTROL0(CONTROL0) - ); - - ila ila_i1 - ( - .CLK(ext_clk), - .CONTROL(CONTROL0), - // .TRIG0(address_reg), - .TRIG0(write_data_reg[7:0]), - .TRIG1(read_data_reg[7:0]), - .TRIG2(0), - .TRIG3({space_avail_reg,data_avail_reg,empty1_reg,full2_reg}) - ); - endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index aa1fd6e3c..38df4a285 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -58,18 +58,18 @@ module ext_fifo_tb(); repeat (5) @(negedge int_clk); rst <= 0; @(negedge int_clk); - repeat (1000) + repeat (4000) begin @(negedge int_clk); - datain <= datain + 1; - src_rdy_i <= 1; - @(negedge int_clk); - src_rdy_i <= 0; + datain <= datain + dst_rdy_o; + src_rdy_i <= dst_rdy_o; +// @(negedge int_clk); +// src_rdy_i <= 0; // @(negedge int_clk); // dst_rdy_i <= src_rdy_o; // @(negedge int_clk); // dst_rdy_i <= 0; - repeat (2) @(negedge int_clk); +// repeat (2) @(negedge int_clk); end // repeat (1000) // Fall through fifo, first output already valid if (dataout !== ref_dataout) @@ -77,16 +77,16 @@ module ext_fifo_tb(); repeat (1000) begin @(negedge int_clk); - datain <= datain + 1; - src_rdy_i <= 1; + datain <= datain + dst_rdy_o ; + src_rdy_i <= dst_rdy_o; @(negedge int_clk); src_rdy_i <= 0; @(negedge int_clk); - ref_dataout <= ref_dataout + 1; + ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; - @(negedge int_clk); - if (dataout !== ref_dataout) + if ((dataout !== ref_dataout) && src_rdy_o) $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); dst_rdy_i <= 0; // repeat (2) @(negedge int_clk); end // repeat (1000) @@ -98,11 +98,11 @@ module ext_fifo_tb(); // @(negedge int_clk); // src_rdy_i <= 0; @(negedge int_clk); - ref_dataout <= ref_dataout + 1; + ref_dataout <= ref_dataout + src_rdy_o; dst_rdy_i <= src_rdy_o; - @(negedge int_clk); - if (dataout !== ref_dataout) + if ((dataout !== ref_dataout) && src_rdy_o) $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); dst_rdy_i <= 0; // repeat (2) @(negedge int_clk); end // repeat (1000) @@ -210,13 +210,7 @@ module ext_fifo_tb(); assign #2 RAM_A_ext = RAM_A; -/* -----\/----- EXCLUDED -----\/----- - wire [13:0] temp1; - assign temp1 = 14'h0; - wire [3:0] temp2; - assign temp2 = 4'h0; - -----/\----- EXCLUDED -----/\----- */ - + idt71v65603s150 idt71v65603s150_i1 ( diff --git a/usrp2/extramfifo/icon.v b/usrp2/extramfifo/icon.v new file mode 100644 index 000000000..6537e9340 --- /dev/null +++ b/usrp2/extramfifo/icon.v @@ -0,0 +1,1286 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.53d +// \ \ Application: netgen +// / / Filename: icon.v +// /___/ /\ Timestamp: Tue Jul 20 20:31:15 2010 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v +// Device : xc3s2000-fg456-5 +// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc +// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v +// # of Modules : 1 +// Design Name : icon +// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module icon ( +CONTROL0 +)/* synthesis syn_black_box syn_noprune=1 */; + inout [35 : 0] CONTROL0; + + // synthesis translate_off + + wire N1; + wire \U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ; + wire \U0/U_ICON/U_CMD/iSEL_n ; + wire \U0/U_ICON/U_CMD/iTARGET_CE ; + wire \U0/U_ICON/U_CTRL_OUT/iDATA_VALID ; + wire \U0/U_ICON/U_STAT/iCMD_GRP0_SEL ; + wire \U0/U_ICON/U_STAT/iDATA_VALID ; + wire \U0/U_ICON/U_STAT/iSTATCMD_CE ; + wire \U0/U_ICON/U_STAT/iSTATCMD_CE_n ; + wire \U0/U_ICON/U_STAT/iSTAT_HIGH ; + wire \U0/U_ICON/U_STAT/iSTAT_LOW ; + wire \U0/U_ICON/U_STAT/iTDO_next ; + wire \U0/U_ICON/U_SYNC/iDATA_CMD_n ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ; + wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ; + wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ; + wire \U0/U_ICON/iCORE_ID_SEL[0] ; + wire \U0/U_ICON/iCORE_ID_SEL[15] ; + wire \U0/U_ICON/iDATA_CMD ; + wire \U0/U_ICON/iDATA_CMD_n ; + wire \U0/U_ICON/iSEL ; + wire \U0/U_ICON/iSEL_n ; + wire \U0/U_ICON/iSYNC ; + wire \U0/U_ICON/iTDI ; + wire \U0/U_ICON/iTDO ; + wire \U0/U_ICON/iTDO_next ; + wire \U0/iSHIFT_OUT ; + wire \U0/iUPDATE_OUT ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ; + wire [11 : 8] \U0/U_ICON/U_CMD/iTARGET ; + wire [1 : 0] \U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL ; + wire [5 : 1] \U0/U_ICON/U_STAT/U_STAT_CNT/CI ; + wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/D ; + wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/S ; + wire [3 : 0] \U0/U_ICON/U_STAT/iSTAT ; + wire [5 : 0] \U0/U_ICON/U_STAT/iSTAT_CNT ; + wire [6 : 0] \U0/U_ICON/U_SYNC/iSYNC_WORD ; + wire [1 : 0] \U0/U_ICON/iCOMMAND_GRP ; + wire [15 : 0] \U0/U_ICON/iCOMMAND_SEL ; + wire [3 : 0] \U0/U_ICON/iCORE_ID ; + wire [15 : 15] \U0/U_ICON/iTDO_VEC ; + GND XST_GND ( + .G(CONTROL0[2]) + ); + VCC XST_VCC ( + .P(N1) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_TDI_reg ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/iTDI ), + .Q(CONTROL0[1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_TDO_reg ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/iTDO_next ), + .Q(\U0/U_ICON/iTDO ) + ); + FDC #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_iDATA_CMD ( + .C(\U0/iUPDATE_OUT ), + .CLR(\U0/U_ICON/iSEL_n ), + .D(\U0/U_ICON/iDATA_CMD_n ), + .Q(\U0/U_ICON/iDATA_CMD ) + ); + MUXF5 \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5 ( + .I0(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ), + .I1(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ), + .S(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iTDO_next ) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4 ( + .I0(CONTROL0[3]), + .I1(\U0/U_ICON/iCORE_ID [0]), + .I2(\U0/U_ICON/iCORE_ID [1]), + .I3(\U0/U_ICON/iCORE_ID [2]), + .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3 ( + .I0(\U0/U_ICON/iTDO_VEC [15]), + .I1(\U0/U_ICON/iCORE_ID [0]), + .I2(\U0/U_ICON/iCORE_ID [1]), + .I3(\U0/U_ICON/iCORE_ID [2]), + .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ) + ); + INV \U0/U_ICON/U_iSEL_n ( + .I(\U0/U_ICON/iSEL ), + .O(\U0/U_ICON/iSEL_n ) + ); + INV \U0/U_ICON/U_iDATA_CMD_n ( + .I(\U0/U_ICON/iDATA_CMD ), + .O(\U0/U_ICON/iDATA_CMD_n ) + ); + BSCAN_SPARTAN3 \U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS ( + .TDI(\U0/U_ICON/iTDI ), + .SHIFT(\U0/iSHIFT_OUT ), + .DRCK1(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ), + .DRCK2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ), + .RESET(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ), + .UPDATE(\U0/iUPDATE_OUT ), + .TDO1(\U0/U_ICON/iTDO ), + .TDO2(CONTROL0[2]), + .CAPTURE(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ), + .SEL1(\U0/U_ICON/iSEL ), + .SEL2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ) + ); + icon_bscan_bufg \U0/U_ICON/I_YES_BSCAN.U_BS/I_USE_SOFTBSCAN_EQ0.I_USE_XST_TCK_WORKAROUND_EQ1.U_ICON_BSCAN_BUFG ( + .DRCK_LOCAL_I(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ), + .DRCK_LOCAL_O(CONTROL0[0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC ( + .I0(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ), + .I1(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC ) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC_L ( + .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]), + .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]), + .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]), + .I3(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC_H ( + .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]), + .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]), + .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]), + .I3(CONTROL0[1]), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ) + ); + INV \U0/U_ICON/U_SYNC/U_iDATA_CMD_n ( + .I(\U0/U_ICON/iDATA_CMD ), + .O(\U0/U_ICON/U_SYNC/iDATA_CMD_n ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/U_SYNC ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_SYNC/iGOT_SYNC ), + .D(N1), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/iSYNC ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[2].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR ( + .C(CONTROL0[0]), + .D(CONTROL0[1]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[20]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[4]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [1]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[21]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [1]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[5]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [2]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[22]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [2]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [3]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[23]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [3]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[7]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [4]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[24]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [4]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[8]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [5]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[25]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [5]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[9]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [6]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[26]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [6]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[10]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [7]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[27]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [7]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[11]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [8]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[28]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [8]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[12]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [9]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[29]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [9]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[13]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [10]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[30]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [10]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[14]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [11]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[31]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [11]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[15]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [12]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[32]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [12]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[16]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [13]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[33]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [13]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[17]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [14]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[34]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [14]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[18]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [15]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[35]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [15]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[19]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/U_ICON/U_CTRL_OUT/U_CMDGRP1 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]) + ); + LUT2 #( + .INIT ( 4'h1 )) + \U0/U_ICON/U_CTRL_OUT/U_CMDGRP0 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_CTRL_OUT/U_DATA_VALID ( + .I0(\U0/U_ICON/iSYNC ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iCORE_ID_SEL[0] ) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0008 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0010 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0020 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0040 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0080 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0100 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h2000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h4000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[15].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iCORE_ID_SEL[15] ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[0].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [0]) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[1].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [1]) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[2].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [2]) + ); + LUT4 #( + .INIT ( 16'h0008 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[3].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [3]) + ); + LUT4 #( + .INIT ( 16'h0010 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[4].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [4]) + ); + LUT4 #( + .INIT ( 16'h0020 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[5].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [5]) + ); + LUT4 #( + .INIT ( 16'h0040 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[6].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [6]) + ); + LUT4 #( + .INIT ( 16'h0080 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[7].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [7]) + ); + LUT4 #( + .INIT ( 16'h0100 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[8].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [8]) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [9]) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[10].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [10]) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[11].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [11]) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[12].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [12]) + ); + LUT4 #( + .INIT ( 16'h2000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[13].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [13]) + ); + LUT4 #( + .INIT ( 16'h4000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[14].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [14]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[15].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [15]) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/U_ICON/U_CMD/U_TARGET_CE ( + .I0(\U0/U_ICON/iDATA_CMD ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_CMD/iTARGET_CE ) + ); + INV \U0/U_ICON/U_CMD/U_SEL_n ( + .I(\U0/U_ICON/iSEL ), + .O(\U0/U_ICON/U_CMD/iSEL_n ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCOMMAND_GRP [1]), + .Q(\U0/U_ICON/iCOMMAND_GRP [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [8]), + .Q(\U0/U_ICON/iCOMMAND_GRP [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [9]), + .Q(\U0/U_ICON/U_CMD/iTARGET [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [10]), + .Q(\U0/U_ICON/U_CMD/iTARGET [9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [11]), + .Q(\U0/U_ICON/U_CMD/iTARGET [10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [0]), + .Q(\U0/U_ICON/U_CMD/iTARGET [11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [1]), + .Q(\U0/U_ICON/iCORE_ID [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [2]), + .Q(\U0/U_ICON/iCORE_ID [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [3]), + .Q(\U0/U_ICON/iCORE_ID [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(CONTROL0[1]), + .Q(\U0/U_ICON/iCORE_ID [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [5]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]) + ); + MUXF6 \U0/U_ICON/U_STAT/U_TDO_next ( + .I0(\U0/U_ICON/U_STAT/iSTAT_LOW ), + .I1(\U0/U_ICON/U_STAT/iSTAT_HIGH ), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [5]), + .O(\U0/U_ICON/U_STAT/iTDO_next ) + ); + MUXF5 \U0/U_ICON/U_STAT/U_STAT_LOW ( + .I0(\U0/U_ICON/U_STAT/iSTAT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT [1]), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/iSTAT_LOW ) + ); + MUXF5 \U0/U_ICON/U_STAT/U_STAT_HIGH ( + .I0(\U0/U_ICON/U_STAT/iSTAT [2]), + .I1(\U0/U_ICON/U_STAT/iSTAT [3]), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/iSTAT_HIGH ) + ); + LUT4 #( + .INIT ( 16'h0101 )) + \U0/U_ICON/U_STAT/F_STAT[0].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [0]) + ); + LUT4 #( + .INIT ( 16'hC101 )) + \U0/U_ICON/U_STAT/F_STAT[1].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [1]) + ); + LUT4 #( + .INIT ( 16'h2100 )) + \U0/U_ICON/U_STAT/F_STAT[2].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [2]) + ); + LUT4 #( + .INIT ( 16'h1610 )) + \U0/U_ICON/U_STAT/F_STAT[3].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [3]) + ); + INV \U0/U_ICON/U_STAT/U_STATCMD_n ( + .I(\U0/U_ICON/U_STAT/iSTATCMD_CE ), + .O(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_STAT/U_STATCMD ( + .I0(\U0/U_ICON/U_STAT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[15] ), + .I3(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ), + .O(\U0/U_ICON/U_STAT/iSTATCMD_CE ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \U0/U_ICON/U_STAT/U_CMDGRP0 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_STAT/U_DATA_VALID ( + .I0(\U0/U_ICON/iSYNC ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_STAT/iDATA_VALID ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_TDO ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/iTDO_next ), + .Q(\U0/U_ICON/iTDO_VEC [15]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/usrp2/extramfifo/icon.xco b/usrp2/extramfifo/icon.xco new file mode 100644 index 000000000..fda273149 --- /dev/null +++ b/usrp2/extramfifo/icon.xco @@ -0,0 +1,47 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Wed Jul 21 03:31:19 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a +# END Select +# BEGIN Parameters +CSET component_name=icon +CSET enable_jtag_bufg=true +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +GENERATE +# CRC: 799ba5a1 diff --git a/usrp2/extramfifo/ila.v b/usrp2/extramfifo/ila.v new file mode 100644 index 000000000..b0d8f8d0c --- /dev/null +++ b/usrp2/extramfifo/ila.v @@ -0,0 +1,5544 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.53d +// \ \ Application: netgen +// / / Filename: ila.v +// /___/ /\ Timestamp: Wed Jul 21 11:51:09 2010 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v +// Device : xc3s2000-fg456-5 +// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc +// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v +// # of Modules : 1 +// Design Name : ila +// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module ila ( + CLK, CONTROL, TRIG0, TRIG1, TRIG2, TRIG3 +)/* synthesis syn_black_box syn_noprune=1 */; + input CLK; + inout [35 : 0] CONTROL; + input [7 : 0] TRIG0; + input [7 : 0] TRIG1; + input [7 : 0] TRIG2; + input [3 : 0] TRIG3; + + // synthesis translate_off + + wire N0; + wire N1; + wire N38; + wire N39; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ; + wire \U0/I_NO_D.U_ILA/U_RST/HALT_pulse ; + wire \U0/I_NO_D.U_ILA/U_RST/POR ; + wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ; + wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ; + wire \U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ; + wire \U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ; + wire \U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/NS_load ; + wire \U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/TDO_next ; + wire \U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ; + wire \U0/I_NO_D.U_ILA/iARM ; + wire \U0/I_NO_D.U_ILA/iCAPTURE ; + wire \U0/I_NO_D.U_ILA/iCAP_DONE ; + wire \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ; + wire \U0/I_NO_D.U_ILA/iCAP_WR_EN ; + wire \U0/I_NO_D.U_ILA/iDATA_DOUT ; + wire \U0/I_NO_D.U_ILA/iSTAT_DOUT ; + wire \U0/I_NO_D.U_ILA/iTRIGGER ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED ; + wire [27 : 0] \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp ; + wire [13 : 1] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO ; + wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO ; + wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next ; + wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S ; + wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [4 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data ; + wire [16 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN ; + wire [0 : 0] \U0/I_NO_D.U_ILA/U_RST/iRESET ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_STAT/NS_dstat ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/STATE_dstat ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT ; + wire [9 : 1] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S ; + wire [16 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_TRIG/trigCondIn ; + wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES ; + wire [1 : 0] \U0/I_NO_D.U_ILA/iCAP_STATE ; + wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_WR_ADDR ; + wire [27 : 0] \U0/I_NO_D.U_ILA/iDATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/iRESET ; + wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy ; + wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut ; + wire [27 : 0] \U0/iTRIG_IN ; + GND XST_GND ( + .G(N0) + ); + VCC XST_VCC ( + .P(N1) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_HCMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_LCMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_SCNT_CMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE0 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ), + .R(\U0/I_NO_D.U_ILA/iRESET [7]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_EN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG0 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG1 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [7]), + .Q(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [1]) + ); + LUT3 #( + .INIT ( 8'h20 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG ( + .I0(\U0/I_NO_D.U_ILA/iTRIGGER ), + .I1(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .I2(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]), + .Q15(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ), + .R(N0), + .Q(\U0/I_NO_D.U_ILA/iCAP_DONE ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ) +, + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ) +, + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK1 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK0 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[14].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[13].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[12].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[10].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[9].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[7].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[4].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[1].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL2 ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL3 ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_CR ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[8].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[6].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[5].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[4].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[3].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[2].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATE1 ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATE0 ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_ARM ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ), + .R(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_TRIGGER ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ), + .R(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_FULL ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ), + .R(\U0/I_NO_D.U_ILA/iARM ), + .S(\U0/I_NO_D.U_ILA/iCAP_DONE ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_ECR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ), + .R(\U0/I_NO_D.U_ILA/iARM ), + .S(N1), + .Q(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE ( + .C(CONTROL[0]), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/iARM ), + .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .PRE(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ) + ); + LDC #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC ( + .CLR(\U0/I_NO_D.U_ILA/iARM ), + .D(N1), + .G(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RISING ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ), + .D(N1), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_TDO ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ), + .Q(\U0/I_NO_D.U_ILA/iSTAT_DOUT ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[5]), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(CONTROL[5]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/I_H2L.U_DOUT ( + .C(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]), + .R(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT1 ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT0 ( + .C(CONTROL[0]), + .CE(N1), + .D(CONTROL[5]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ) + ); + LUT4 #( + .INIT ( 16'hFBEA )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ) + ); + MUXF7 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_0 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD ( + .I0(CONTROL[4]), + .I1(CONTROL[5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ) + ); + INV \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD_n ( + .I(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSR ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .O(\NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0F22 )) + \U0/I_NO_D.U_ILA/U_STAT/U_NSL ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ), + .I3(\U0/I_NO_D.U_ILA/iRESET [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/NS_load ) + ); + LUT4 #( + .INIT ( 16'h0030 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[16].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]) + ); + LUT4 #( + .INIT ( 16'h1030 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[15].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[14].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]) + ); + LUT4 #( + .INIT ( 16'h1020 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[13].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[12].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]) + ); + LUT4 #( + .INIT ( 16'h1010 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[11].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[10].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]) + ); + LUT4 #( + .INIT ( 16'h100F )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[9].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]) + ); + LUT4 #( + .INIT ( 16'hFFF0 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[8].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[7].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]) + ); + LUT4 #( + .INIT ( 16'h3000 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[6].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]) + ); + LUT4 #( + .INIT ( 16'h001F )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[5].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]) + ); + LUT4 #( + .INIT ( 16'hF001 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[4].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]) + ); + LUT4 #( + .INIT ( 16'hB610 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[3].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]) + ); + LUT4 #( + .INIT ( 16'h2100 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[2].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]) + ); + LUT4 #( + .INIT ( 16'hC102 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[1].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]) + ); + LUT4 #( + .INIT ( 16'h0101 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[0].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]), + .I1(CONTROL[5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/U_POR ( + .C(CLK), + .D(N0), + .PRE(N0), + .Q(\U0/I_NO_D.U_ILA/U_RST/POR ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [0]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[1].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [1]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[2].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [1]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [2]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[3].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [2]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [3]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[4].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [3]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [4]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[5].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [4]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [5]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[6].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [5]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [6]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[7].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [6]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [7]) + ); + LUT3 #( + .INIT ( 8'hEF )) + \U0/I_NO_D.U_ILA/U_RST/U_PRST1 ( + .I0(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ), + .I1(\U0/I_NO_D.U_ILA/U_RST/POR ), + .I2(N1), + .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ) + ); + LUT4 #( + .INIT ( 16'hFFFE )) + \U0/I_NO_D.U_ILA/U_RST/U_PRST0 ( + .I0(N0), + .I1(\U0/I_NO_D.U_ILA/iCAP_DONE ), + .I2(N0), + .I3(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ), + .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/I_NO_D.U_ILA/U_RST/U_RST0 ( + .I0(\U0/I_NO_D.U_ILA/iARM ), + .I1(\U0/I_NO_D.U_ILA/iRESET [0]), + .O(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ), + .I1(CONTROL[13]), + .O(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[2].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[13]), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ), + .I1(CONTROL[12]), + .O(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[4].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ), + .Q(\U0/I_NO_D.U_ILA/iARM ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[2].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[12]), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(CONTROL[12]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [24]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [25]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [26]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [27]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[23]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[23]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_YES_MUXH.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [0]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [1]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [2]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [3]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [4]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [5]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [6]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [7]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[20]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[20]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [8]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [9]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [10]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [11]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [12]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [13]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [14]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [15]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[21]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[21]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [16]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [17]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [18]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [19]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [20]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [21]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [22]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [23]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[22]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[22]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]), + .Q(\U0/I_NO_D.U_ILA/iDATA [0]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]), + .Q(\U0/I_NO_D.U_ILA/iDATA [1]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]), + .Q(\U0/I_NO_D.U_ILA/iDATA [2]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]), + .Q(\U0/I_NO_D.U_ILA/iDATA [3]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]), + .Q(\U0/I_NO_D.U_ILA/iDATA [4]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]), + .Q(\U0/I_NO_D.U_ILA/iDATA [5]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]), + .Q(\U0/I_NO_D.U_ILA/iDATA [6]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]), + .Q(\U0/I_NO_D.U_ILA/iDATA [7]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]), + .Q(\U0/I_NO_D.U_ILA/iDATA [8]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]), + .Q(\U0/I_NO_D.U_ILA/iDATA [9]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]), + .Q(\U0/I_NO_D.U_ILA/iDATA [10]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]), + .Q(\U0/I_NO_D.U_ILA/iDATA [11]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]), + .Q(\U0/I_NO_D.U_ILA/iDATA [12]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]), + .Q(\U0/I_NO_D.U_ILA/iDATA [13]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]), + .Q(\U0/I_NO_D.U_ILA/iDATA [14]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]), + .Q(\U0/I_NO_D.U_ILA/iDATA [15]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]), + .Q(\U0/I_NO_D.U_ILA/iDATA [16]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]), + .Q(\U0/I_NO_D.U_ILA/iDATA [17]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]), + .Q(\U0/I_NO_D.U_ILA/iDATA [18]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]), + .Q(\U0/I_NO_D.U_ILA/iDATA [19]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]), + .Q(\U0/I_NO_D.U_ILA/iDATA [20]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]), + .Q(\U0/I_NO_D.U_ILA/iDATA [21]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]), + .Q(\U0/I_NO_D.U_ILA/iDATA [22]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]), + .Q(\U0/I_NO_D.U_ILA/iDATA [23]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]), + .Q(\U0/I_NO_D.U_ILA/iDATA [24]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]), + .Q(\U0/I_NO_D.U_ILA/iDATA [25]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]), + .Q(\U0/I_NO_D.U_ILA/iDATA [26]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]), + .Q(\U0/I_NO_D.U_ILA/iDATA [27]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [0]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [1]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [2]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [3]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [4]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [5]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [6]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [7]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [8]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [9]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [10]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [11]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [12]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [13]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [14]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [15]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [16]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [17]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [18]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [19]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [20]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [21]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [22]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [23]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [24]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [25]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [26]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [27]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_DOUT ( + .I0(\U0/I_NO_D.U_ILA/iSTAT_DOUT ), + .I1(\U0/I_NO_D.U_ILA/iDATA_DOUT ), + .I2(CONTROL[6]), + .O(CONTROL[3]) + ); + LUT1 #( + .INIT ( 2'h1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B ( + .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ), + .O(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]), + .CE(CONTROL[8]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ) + + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]), + .I1(CONTROL[8]), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]), + .CE(CONTROL[8]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(CONTROL[1]), + .I1(CONTROL[8]), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_DLY ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/iCAPTURE ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ), + .R(\U0/I_NO_D.U_ILA/iRESET [4]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ), + .R(\U0/I_NO_D.U_ILA/iRESET [4]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/F_NO_TCMC.U_FDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ), + .R(\U0/I_NO_D.U_ILA/iRESET [5]), + .Q(\U0/I_NO_D.U_ILA/iTRIGGER ) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG3[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [27]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG3[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [26]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG3[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [25]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG3[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [24]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG2[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [23]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG2[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [22]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG2[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [21]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG2[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [20]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG2[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [19]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG2[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [18]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG2[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [17]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG2[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [16]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG1[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [15]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG1[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [14]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG1[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [13]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG1[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [12]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG1[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [11]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG1[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [10]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG1[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [9]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG1[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [8]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG0[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [7]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG0[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [6]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG0[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [5]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG0[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [4]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG0[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [3]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG0[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [2]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG0[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG0[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<0> ( + .I0(CONTROL[10]), + .I1(CONTROL[11]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<0> ( + .CI(N1), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1> ( + .I0(CONTROL[12]), + .I1(CONTROL[13]), + .I2(CONTROL[9]), + .I3(CONTROL[14]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<2> ( + .I0(CONTROL[15]), + .I1(CONTROL[16]), + .I2(CONTROL[8]), + .I3(CONTROL[17]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3> ( + .I0(CONTROL[18]), + .I1(CONTROL[21]), + .I2(CONTROL[7]), + .I3(CONTROL[19]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<4> ( + .I0(CONTROL[20]), + .I1(CONTROL[22]), + .I2(CONTROL[6]), + .I3(CONTROL[23]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<5> ( + .I0(CONTROL[24]), + .I1(CONTROL[25]), + .I2(CONTROL[5]), + .I3(CONTROL[26]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<6> ( + .I0(CONTROL[27]), + .I1(CONTROL[28]), + .I2(CONTROL[2]), + .I3(CONTROL[29]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<7> ( + .I0(CONTROL[30]), + .I1(CONTROL[31]), + .I2(CONTROL[1]), + .I3(CONTROL[32]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<8> ( + .I0(CONTROL[33]), + .I1(CONTROL[34]), + .I2(CONTROL[4]), + .I3(CONTROL[35]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]) + ); + LUT4 #( + .INIT ( 16'hFEFF )) + \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ) + ); + LUT4 #( + .INIT ( 16'hFFFE )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ) + ); + LUT4 #( + .INIT ( 16'hF222 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ), + .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ) + ); + LUT4 #( + .INIT ( 16'hAF8D )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O129 ( + .I0(CONTROL[4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91 ( + .I0(N38), + .I1(N39), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ) + ); + LUT3 #( + .INIT ( 8'h15 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .O(N38) + ); + LUT4 #( + .INIT ( 16'h0145 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_G ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ), + .O(N39) + ); + LUT4_L #( + .INIT ( 16'h3F50 )) + \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ) + ); + LUT4_L #( + .INIT ( 16'h3120 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ) + ); + RAMB16_S1_S36 #( + .INIT_B ( 36'h000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_A ( 1'h0 ), + .SIM_COLLISION_CHECK ( "ALL" ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .SRVAL_A ( 1'h0 ), + .WRITE_MODE_A ( "WRITE_FIRST" ), + .WRITE_MODE_B ( "WRITE_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i ( + .CLKA(CONTROL[0]), + .CLKB(CLK), + .ENA(CONTROL[6]), + .ENB(N1), + .WEB(\U0/I_NO_D.U_ILA/iCAP_WR_EN ), + .SSRA(N0), + .SSRB(N0), + .WEA(N0), + .DIPB({N0, N0, N0, N0}), + .ADDRA({\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]}), + .ADDRB({\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5] +, \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1], +\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]}), + .DIB({N0, N0, N0, \U0/I_NO_D.U_ILA/iDATA [27], \U0/I_NO_D.U_ILA/iDATA [26], \U0/I_NO_D.U_ILA/iDATA [25], \U0/I_NO_D.U_ILA/iDATA [24], +\U0/I_NO_D.U_ILA/iDATA [23], \U0/I_NO_D.U_ILA/iDATA [22], \U0/I_NO_D.U_ILA/iDATA [21], \U0/I_NO_D.U_ILA/iDATA [20], \U0/I_NO_D.U_ILA/iDATA [19], +\U0/I_NO_D.U_ILA/iDATA [18], \U0/I_NO_D.U_ILA/iDATA [17], \U0/I_NO_D.U_ILA/iDATA [16], \U0/I_NO_D.U_ILA/iDATA [15], \U0/I_NO_D.U_ILA/iDATA [14], +\U0/I_NO_D.U_ILA/iDATA [13], \U0/I_NO_D.U_ILA/iDATA [12], \U0/I_NO_D.U_ILA/iDATA [11], \U0/I_NO_D.U_ILA/iDATA [10], \U0/I_NO_D.U_ILA/iDATA [9], +\U0/I_NO_D.U_ILA/iDATA [8], \U0/I_NO_D.U_ILA/iDATA [7], \U0/I_NO_D.U_ILA/iDATA [6], \U0/I_NO_D.U_ILA/iDATA [5], \U0/I_NO_D.U_ILA/iDATA [4], +\U0/I_NO_D.U_ILA/iDATA [3], \U0/I_NO_D.U_ILA/iDATA [2], \U0/I_NO_D.U_ILA/iDATA [1], \U0/I_NO_D.U_ILA/iDATA [0], \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT }), + .DOA({\U0/I_NO_D.U_ILA/iDATA_DOUT }), + .DIA({N0}), + .DOB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED }), + .DOPB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED }) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/usrp2/extramfifo/ila.xco b/usrp2/extramfifo/ila.xco new file mode 100644 index 000000000..c8d4d2f75 --- /dev/null +++ b/usrp2/extramfifo/ila.xco @@ -0,0 +1,130 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Wed Jul 21 18:51:14 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a +# END Select +# BEGIN Parameters +CSET component_name=ila +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic +CSET match_type_10=basic +CSET match_type_11=basic +CSET match_type_12=basic +CSET match_type_13=basic +CSET match_type_14=basic +CSET match_type_15=basic +CSET match_type_16=basic +CSET match_type_2=basic +CSET match_type_3=basic +CSET match_type_4=basic +CSET match_type_5=basic +CSET match_type_6=basic +CSET match_type_7=basic +CSET match_type_8=basic +CSET match_type_9=basic +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=4 +CSET sample_data_depth=512 +CSET sample_on=Rising +CSET trigger_port_width_1=8 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=4 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=true +# END Parameters +GENERATE +# CRC: 66151c7c diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 1bd7439ad..7ddb517c7 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -1,3 +1,9 @@ +// Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port +// device it can only sustain data throughput at half the RAM clock rate. +// Fair arbitration to ensure this occurs is included in this logic and +// requests for transactions that can not be completed are held off by (re)using the +// "full" and "empty" flags. + module nobl_fifo #(parameter WIDTH=18,DEPTH=19) ( @@ -17,14 +23,14 @@ module nobl_fifo output reg space_avail, output reg [WIDTH-1:0] read_data, input read_strobe, - output reg data_avail + output reg data_avail, + input upstream_full // (Connect to almost full flag upstream) ); reg [DEPTH-1:0] capacity; reg [DEPTH-1:0] wr_pointer; reg [DEPTH-1:0] rd_pointer; wire [DEPTH-1:0] address; - reg supress; reg data_avail_int; // Data available with high latency from ext FIFO flag wire [WIDTH-1:0] data_in; @@ -38,7 +44,7 @@ module nobl_fifo assign read = read_strobe_int && data_avail_int; assign write = write_strobe && space_avail; - // When a read and write collision occur, supress availability flags next cycle + // When a read and write collision occur, supress the availability flags next cycle // and complete write followed by read over 2 cycles. This forces balanced arbitration // and makes for a simple logic design. @@ -231,9 +237,11 @@ module nobl_fifo // Start an external FIFO read as soon as a read of the buffer reg is strobed to minimise refill latency. // If the buffer reg or the pending buffer reg is already empty also pre-emptively start a read. - // However there must be something in ext FIFO to read. - // This means that there can be 2 outstanding reads to the ext FIFO active at any time helping to hide latency. - assign read_strobe_int = (read_strobe & data_avail & ~pending_avail) || (~data_avail && ~pending_avail); + // However there must be something in the main external FIFO to read for this to occur!. + // Pay special attention to upstream devices signalling full due to the number of potential in-flight reads\ that need + // to be stalled and stored somewhere. + // This means that there can be 3 outstanding reads to the ext FIFO active at any time helping to hide latency. + assign read_strobe_int = (read_strobe && data_avail && ~pending_avail && ~upstream_full) || (~data_avail && ~pending_avail && ~upstream_full); // diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index 3143ce5ba..24d463b1e 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -1,3 +1,5 @@ +// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world. + module nobl_if #(parameter WIDTH=18,DEPTH=19) ( @@ -35,9 +37,9 @@ module nobl_if reg [WIDTH-1:0] data_out_pipe3; assign RAM_LDn = 0; + // ZBT/NoBL RAM actually manages its own output enables very well. assign RAM_OEn = 0; - // // Pipeline stage 1 // @@ -129,8 +131,5 @@ module nobl_if else data_in_valid <= 1'b0; end // always @ (posedge clk) - - - - + endmodule // nobl_if diff --git a/usrp2/extramfifo/test_sram_if.v b/usrp2/extramfifo/test_sram_if.v index 9f36b409c..0e74b49eb 100644 --- a/usrp2/extramfifo/test_sram_if.v +++ b/usrp2/extramfifo/test_sram_if.v @@ -1,3 +1,7 @@ +// Instantiate this block at the core level to conduct closed +// loop testing of the AC performance of the USRP2 SRAM interface + + `define WIDTH 18 `define DEPTH 19 diff --git a/usrp2/fifo/fifo_cascade.v b/usrp2/fifo/fifo_cascade.v index fdd8449bc..ff2993ed5 100644 --- a/usrp2/fifo/fifo_cascade.v +++ b/usrp2/fifo/fifo_cascade.v @@ -10,11 +10,11 @@ module fifo_cascade #(parameter WIDTH=32, SIZE=9) (input clk, input reset, input clear, input [WIDTH-1:0] datain, - input src_rdy_i, - output dst_rdy_o, + input src_rdy_i, // WRITE + output dst_rdy_o, // not FULL output [WIDTH-1:0] dataout, - output src_rdy_o, - input dst_rdy_i, + output src_rdy_o, // not EMPTY + input dst_rdy_i, // READ output [15:0] space, output [15:0] occupied); diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index d0435fa1e..754471221 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -31,6 +31,7 @@ synth: $(ISE_FILE) $(ISE_HELPER) "Synthesize - XST" bin: $(BIN_FILE) + $(ISE_HELPER) "Generate Programming File" mcs: $(MCS_FILE) diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp index 9962887d4..99effb038 100644 --- a/usrp2/top/u2_rev3/Makefile.udp +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + ################################################## # Project Properties diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 798022adc..33e9dbcd9 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -119,7 +119,9 @@ module u2_core inout [15:0] io_rx, // External RAM - inout [17:0] RAM_D, + input [17:0] RAM_D_pi, + output [17:0] RAM_D_po, + output RAM_D_poe, output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, @@ -642,11 +644,37 @@ module u2_core wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; wire [31:0] debug_vtc, debug_vtd, debug_vt; - + + // FIFO cascade draws from buffer pool, feeds vita tx deframer +/* -----\/----- EXCLUDED -----\/----- fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); + -----/\----- EXCLUDED -----/\----- */ + + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.DEPTH(19)) + ext_fifo_i1 + ( + .int_clk(dsp_clk), + .ext_clk(clk_to_mac), + .rst(dsp_rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain({rd1_flags,rd1_dat}), + .src_rdy_i(rd1_ready_o), // WRITE + .dst_rdy_o(rd1_ready_i), // not FULL + .dataout(tx_data), + .src_rdy_o(tx_src_rdy), // not EMPTY + .dst_rdy_i(tx_dst_rdy) + ); vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer (.clk(dsp_clk), .reset(dsp_rst), .clear(0), @@ -720,7 +748,30 @@ module u2_core assign RAM_CE1n = 0; assign RAM_D[17:16] = 2'bzz; - */ +/* -----\/----- EXCLUDED -----\/----- + *-/ + + test_sram_if test_sram_if_i1 + ( + // .clk(wb_clk), + .clk(clk_to_mac), + .rst(wb_rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .correct() + ); + -----/\----- EXCLUDED -----/\----- */ + + //assign RAM_CLK = wb_clk; + assign RAM_CLK = clk_to_mac; + // ///////////////////////////////////////////////////////////////////////// // VITA Timing diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 6aa699d2a..82d879446 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -74,49 +74,49 @@ NET "MDC" LOC = "V18" ; NET "PHY_INTn" LOC = "AB13" ; NET "PHY_RESETn" LOC = "AA19" ; NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" ; -NET "RAM_D[1]" LOC = "N21" ; -NET "RAM_D[2]" LOC = "N22" ; -NET "RAM_D[3]" LOC = "M17" ; -NET "RAM_D[4]" LOC = "M18" ; -NET "RAM_D[5]" LOC = "M19" ; -NET "RAM_D[6]" LOC = "M20" ; -NET "RAM_D[7]" LOC = "M21" ; -NET "RAM_D[8]" LOC = "M22" ; -NET "RAM_D[9]" LOC = "Y22" ; -NET "RAM_D[10]" LOC = "Y21" ; -NET "RAM_D[11]" LOC = "Y20" ; -NET "RAM_D[12]" LOC = "Y19" ; -NET "RAM_D[13]" LOC = "W22" ; -NET "RAM_D[14]" LOC = "W21" ; -NET "RAM_D[15]" LOC = "W20" ; -NET "RAM_D[16]" LOC = "W19" ; -NET "RAM_D[17]" LOC = "V22" ; -NET "RAM_A[0]" LOC = "U21" ; -NET "RAM_A[1]" LOC = "T19" ; -NET "RAM_A[2]" LOC = "V21" ; -NET "RAM_A[3]" LOC = "V20" ; -NET "RAM_A[4]" LOC = "T20" ; -NET "RAM_A[5]" LOC = "T21" ; -NET "RAM_A[6]" LOC = "T22" ; -NET "RAM_A[7]" LOC = "T18" ; -NET "RAM_A[8]" LOC = "R18" ; -NET "RAM_A[9]" LOC = "P19" ; -NET "RAM_A[10]" LOC = "P21" ; -NET "RAM_A[11]" LOC = "P22" ; -NET "RAM_A[12]" LOC = "N19" ; -NET "RAM_A[13]" LOC = "N17" ; -NET "RAM_A[14]" LOC = "N18" ; -NET "RAM_A[15]" LOC = "T17" ; -NET "RAM_A[16]" LOC = "U19" ; -NET "RAM_A[17]" LOC = "U18" ; -NET "RAM_A[18]" LOC = "V19" ; -NET "RAM_CE1n" LOC = "U20" ; -NET "RAM_CENn" LOC = "P18" ; -NET "RAM_CLK" LOC = "P17" ; -NET "RAM_WEn" LOC = "R22" ; -NET "RAM_OEn" LOC = "R21" ; -NET "RAM_LDn" LOC = "R19" ; +NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; NET "ser_enable" LOC = "W11" ; NET "ser_prbsen" LOC = "AA3" ; NET "ser_loopen" LOC = "Y4" ; diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 3a43e4ffe..8d9a18345 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -342,100 +342,133 @@ module u2_rev3 .S(0) // Synchronous preset input ); */ + + wire [17:0] RAM_D_pi; + wire [17:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + + u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk_buf), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_misc (cpld_misc), - .cpld_init_b (cpld_init_b), - .por (~POR), - .config_success (config_success), - .adc_a (adc_a_reg2), - .adc_ovf_a (adc_ovf_a_reg2), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b_reg2), - .adc_ovf_b (adc_ovf_b_reg2), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a_int), - .dac_b (dac_b_int), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk_buf), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_pi (RAM_D_pi), + .RAM_D_po (RAM_D_po), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); endmodule // u2_rev2 -- cgit v1.2.3 From 298b5c2dfd6aabcb89c769a8a1b54181f5dc4273 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 11 Aug 2010 13:59:06 -0700 Subject: checkin of generated coregen files --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 3 + usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo | 52 +++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 6 +- ...12x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso | 3 + ...k_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 102 +++++++++++++++++++++ .../coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt | 8 ++ .../fifo_xlnx_512x36_2clk_18to36_readme.txt | 39 ++++++++ .../coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl | 68 ++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc | 3 + usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo | 51 +++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco | 6 +- ...12x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso | 3 + ...k_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 101 ++++++++++++++++++++ .../coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt | 8 ++ .../fifo_xlnx_512x36_2clk_36to18_readme.txt | 39 ++++++++ .../coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl | 68 ++++++++++++++ 18 files changed, 556 insertions(+), 8 deletions(-) create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc new file mode 100644 index 000000000..376e18c57 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$4264g<,[o}e~g`n;"2*413&;$>"9 > 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v index 32de19e8a..531d56c08 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v @@ -63,7 +63,7 @@ output full; // synthesis translate_off - FIFO_GENERATOR_V4_4 #( + FIFO_GENERATOR_V4_3 #( .C_COMMON_CLOCK(0), .C_COUNT_TYPE(0), .C_DATA_COUNT_WIDTH(10), diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo new file mode 100644 index 000000000..cd949ccaa --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo @@ -0,0 +1,52 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_18to36 YourInstanceName ( + .din(din), // Bus [17 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .almost_full(almost_full), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating +// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco index 05ceffbe9..12b88da39 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version K.39 -# Date: Fri Jul 30 20:43:00 2010 +# Date: Tue Aug 10 23:12:53 2010 # ############################################################## # @@ -32,7 +32,7 @@ SET verilogsim = true SET vhdlsim = false # END Project Options # BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 # END Select # BEGIN Parameters CSET almost_empty_flag=false @@ -78,5 +78,5 @@ CSET write_data_count=false CSET write_data_count_width=10 # END Parameters GENERATE -# CRC: 9b689ee4 +# CRC: 6866170 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..f718bb394 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,102 @@ + + + + + + +
+ + + + + + + + + + + + + + + +
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+ + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt new file mode 100644 index 000000000..18ba3e664 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_512x36_2clk_18to36.ngc +fifo_xlnx_512x36_2clk_18to36.v +fifo_xlnx_512x36_2clk_18to36.veo +fifo_xlnx_512x36_2clk_18to36.xco +fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_18to36_flist.txt +fifo_xlnx_512x36_2clk_18to36_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt new file mode 100644 index 000000000..e0d45849d --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory +/home/matt/fpgapriv/usrp2/coregen/: + +fifo_xlnx_512x36_2clk_18to36.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_18to36.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_18to36.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_18to36.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_18to36_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_512x36_2clk_18to36_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_18to36_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl new file mode 100644 index 000000000..f20d53f64 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_18to36_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_18to36_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_18to36 +} +# ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_18to36 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc new file mode 100644 index 000000000..d76e4c3db --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$5ca4g<,[o}e~g`n;"2*413&;$>"9 > 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v index f7f6e7e9f..6f849b24c 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v @@ -61,7 +61,7 @@ output full; // synthesis translate_off - FIFO_GENERATOR_V4_4 #( + FIFO_GENERATOR_V4_3 #( .C_COMMON_CLOCK(0), .C_COUNT_TYPE(0), .C_DATA_COUNT_WIDTH(9), diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo new file mode 100644 index 000000000..5c2da4b97 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo @@ -0,0 +1,51 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_36to18 YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [17 : 0] + .empty(empty), + .full(full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating +// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco index a1c75dc39..9f47c073c 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version K.39 -# Date: Thu Jul 29 18:10:59 2010 +# Date: Tue Aug 10 23:09:39 2010 # ############################################################## # @@ -32,7 +32,7 @@ SET verilogsim = true SET vhdlsim = false # END Project Options # BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 # END Select # BEGIN Parameters CSET almost_empty_flag=false @@ -78,5 +78,5 @@ CSET write_data_count=false CSET write_data_count_width=9 # END Parameters GENERATE -# CRC: 392ad537 +# CRC: b2f58113 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..3abf04253 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,101 @@ + + + + + + +
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+
+ + + +
+ + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt new file mode 100644 index 000000000..aadac46c0 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_512x36_2clk_36to18.ngc +fifo_xlnx_512x36_2clk_36to18.v +fifo_xlnx_512x36_2clk_36to18.veo +fifo_xlnx_512x36_2clk_36to18.xco +fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_36to18_flist.txt +fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt new file mode 100644 index 000000000..568c757ec --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory +/home/matt/fpgapriv/usrp2/coregen/: + +fifo_xlnx_512x36_2clk_36to18.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_36to18.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_36to18.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_36to18.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_36to18_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_512x36_2clk_36to18_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_36to18_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl new file mode 100644 index 000000000..09248b321 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_36to18_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_36to18_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_36to18 +} +# ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_36to18 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams -- cgit v1.2.3 From 6e0d78f4cbf6f0d6cda6007f11b4fb4dd4edaee9 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 12:00:01 -0700 Subject: Found bug due to not accounting for the correct number of possible in flight READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 3 ++ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 68 ++++++++++++++------------ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 18 ++++--- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc | 3 ++ usrp2/extramfifo/ext_fifo.v | 15 ++++-- usrp2/extramfifo/ext_fifo_tb.v | 39 +++++++++++++++ usrp2/extramfifo/nobl_fifo.v | 16 +++--- 7 files changed, 113 insertions(+), 49 deletions(-) create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc new file mode 100644 index 000000000..01deeab91 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index a506d71e2..c7e8f6cfb 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -57,10 +57,18 @@ module ext_fifo .dout(write_data), // Bus [17 : 0] .full(full1), .empty(empty1)); - assign dst_rdy_o = ~full1; + + assign dst_rdy_o = ~full1; + +/* -----\/----- EXCLUDED -----\/----- + assign space_avail = ~full2; + assign data_avail = ~empty1; + assign read_data = write_data; + -----/\----- EXCLUDED -----/\----- */ + // External FIFO running at ext clock rate and 18 bit width. - nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH)) + nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH),.FDEPTH(DEPTH)) nobl_fifo_i1 ( .clk(ext_clk), @@ -94,7 +102,8 @@ module ext_fifo .rd_en(dst_rdy_i), .dout(dataout), // Bus [35 : 0] .full(full2), - .almost_full(almost_full2), + .almost_full(), + .prog_full(almost_full2), .empty(empty2)); assign src_rdy_o = ~empty2; diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index 38df4a285..a93d524d5 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -51,6 +51,44 @@ module ext_fifo_tb(); always #4 ext_clk <= ~ext_clk; + initial + begin + rst <= 1; + repeat (5) @(negedge int_clk); + rst <= 0; + @(negedge int_clk); + while (datain < 10000) + begin + @(negedge int_clk); + datain <= datain + dst_rdy_o; + src_rdy_i <= dst_rdy_o; + end + end // initial begin + + + initial + begin + repeat (20) @(negedge int_clk); + + // Fall through fifo, first output already valid + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + + while (ref_dataout < 10000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(6) @(negedge int_clk); + end + end + + +/* -----\/----- EXCLUDED -----\/----- initial begin @@ -112,6 +150,7 @@ module ext_fifo_tb(); end // initial begin + -----/\----- EXCLUDED -----/\----- */ /////////////////////////////////////////////////////////////////////////////////// // Simulation control // /////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 7ddb517c7..03e3f5223 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -5,7 +5,7 @@ // "full" and "empty" flags. module nobl_fifo - #(parameter WIDTH=18,DEPTH=19) + #(parameter WIDTH=18,DEPTH=19,FDEPTH=10) ( input clk, input rst, @@ -27,9 +27,9 @@ module nobl_fifo input upstream_full // (Connect to almost full flag upstream) ); - reg [DEPTH-1:0] capacity; - reg [DEPTH-1:0] wr_pointer; - reg [DEPTH-1:0] rd_pointer; + reg [FDEPTH-1:0] capacity; + reg [FDEPTH-1:0] wr_pointer; + reg [FDEPTH-1:0] rd_pointer; wire [DEPTH-1:0] address; reg supress; reg data_avail_int; // Data available with high latency from ext FIFO flag @@ -51,7 +51,7 @@ module nobl_fifo always @(posedge clk) if (rst) begin - capacity <= 1 << (DEPTH-1); + capacity <= 1 << (FDEPTH-1); wr_pointer <= 0; rd_pointer <= 0; space_avail <= 0; @@ -60,9 +60,11 @@ module nobl_fifo end else begin - space_avail <= ~((capacity == 0) || (read&&write) || (capacity == 1 && write) ); + // No space available if: + // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) + space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == (1 << (DEPTH-1))) || (read&&write) || (capacity == ((1 << (DEPTH-1))-1) && read) ); + data_avail_int <= ~((capacity == (1 << (FDEPTH-1))) || (read&&write) || ((capacity == ((1 << (FDEPTH-1))-1)) && read) ); supress <= read && write; wr_pointer <= wr_pointer + write; rd_pointer <= rd_pointer + ((~write && read) || supress); -- cgit v1.2.3 From fe79353d6a4cc395dc78bb55159815c9233d1eff Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 12:28:13 -0700 Subject: Bringing all coregen files checked in into sync --- usrp2/coregen/fifo_generator_ug175.pdf | Bin 1069823 -> 2895895 bytes usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo | 12 +-- .../coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt | 6 +- .../fifo_xlnx_512x36_2clk_18to36_readme.txt | 22 +++-- .../coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl | 8 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo | 12 +-- ...k_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 101 --------------------- .../coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt | 6 +- .../fifo_xlnx_512x36_2clk_36to18_readme.txt | 22 +++-- .../coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl | 8 +- 10 files changed, 60 insertions(+), 137 deletions(-) delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt diff --git a/usrp2/coregen/fifo_generator_ug175.pdf b/usrp2/coregen/fifo_generator_ug175.pdf index 2c3e3c200..5fba6029c 100644 Binary files a/usrp2/coregen/fifo_generator_ug175.pdf and b/usrp2/coregen/fifo_generator_ug175.pdf differ diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo index cd949ccaa..c962fddfa 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo @@ -23,7 +23,7 @@ * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * -* (c) Copyright 1995-2007 Xilinx, Inc. * +* (c) Copyright 1995-2009 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // The following must be inserted into your Verilog file for this @@ -32,16 +32,16 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG fifo_xlnx_512x36_2clk_18to36 YourInstanceName ( - .din(din), // Bus [17 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [17 : 0] .wr_en(wr_en), - .almost_full(almost_full), + .rd_en(rd_en), .dout(dout), // Bus [35 : 0] + .full(full), .empty(empty), - .full(full)); + .prog_full(prog_full)); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt index 18ba3e664..2f8d522f6 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt @@ -1,8 +1,12 @@ # Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_18to36.gise fifo_xlnx_512x36_2clk_18to36.ngc fifo_xlnx_512x36_2clk_18to36.v fifo_xlnx_512x36_2clk_18to36.veo fifo_xlnx_512x36_2clk_18to36.xco -fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_18to36.xise fifo_xlnx_512x36_2clk_18to36_flist.txt +fifo_xlnx_512x36_2clk_18to36_readme.txt fifo_xlnx_512x36_2clk_18to36_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt index e0d45849d..03829e876 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt @@ -1,5 +1,12 @@ The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory -/home/matt/fpgapriv/usrp2/coregen/: +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_18to36.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. fifo_xlnx_512x36_2clk_18to36.ngc: Binary Xilinx implementation netlist file containing the information @@ -18,12 +25,9 @@ fifo_xlnx_512x36_2clk_18to36.xco: CORE Generator input file containing the parameters used to regenerate a core. -fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_18to36_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. +fifo_xlnx_512x36_2clk_18to36.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. fifo_xlnx_512x36_2clk_18to36_readme.txt: Text file indicating the files generated and how they are used. @@ -33,6 +37,10 @@ fifo_xlnx_512x36_2clk_18to36_xmdf.tcl: how the files output by CORE Generator for the core can be integrated into your ISE project. +fifo_xlnx_512x36_2clk_18to36_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + Please see the Xilinx CORE Generator online help for further details on generated files and how to use them. diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl index f20d53f64..9b9b1f37a 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl @@ -36,6 +36,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim incr fcount +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc incr fcount @@ -52,10 +56,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_51 utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView incr fcount diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo index 5c2da4b97..e93be1591 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo @@ -23,7 +23,7 @@ * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * -* (c) Copyright 1995-2007 Xilinx, Inc. * +* (c) Copyright 1995-2009 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // The following must be inserted into your Verilog file for this @@ -32,15 +32,15 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG fifo_xlnx_512x36_2clk_36to18 YourInstanceName ( - .din(din), // Bus [35 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] .wr_en(wr_en), + .rd_en(rd_en), .dout(dout), // Bus [17 : 0] - .empty(empty), - .full(full)); + .full(full), + .empty(empty)); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index 3abf04253..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,101 +0,0 @@ - - - - - - -

- - - - - - - - - - - - - - -
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- - - diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt index aadac46c0..54c85b15e 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt @@ -1,8 +1,12 @@ # Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_36to18.gise fifo_xlnx_512x36_2clk_36to18.ngc fifo_xlnx_512x36_2clk_36to18.v fifo_xlnx_512x36_2clk_36to18.veo fifo_xlnx_512x36_2clk_36to18.xco -fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_36to18.xise fifo_xlnx_512x36_2clk_36to18_flist.txt +fifo_xlnx_512x36_2clk_36to18_readme.txt fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt index 568c757ec..3efc586bf 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt @@ -1,5 +1,12 @@ The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory -/home/matt/fpgapriv/usrp2/coregen/: +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_36to18.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. fifo_xlnx_512x36_2clk_36to18.ngc: Binary Xilinx implementation netlist file containing the information @@ -18,12 +25,9 @@ fifo_xlnx_512x36_2clk_36to18.xco: CORE Generator input file containing the parameters used to regenerate a core. -fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_36to18_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. +fifo_xlnx_512x36_2clk_36to18.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. fifo_xlnx_512x36_2clk_36to18_readme.txt: Text file indicating the files generated and how they are used. @@ -33,6 +37,10 @@ fifo_xlnx_512x36_2clk_36to18_xmdf.tcl: how the files output by CORE Generator for the core can be integrated into your ISE project. +fifo_xlnx_512x36_2clk_36to18_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + Please see the Xilinx CORE Generator online help for further details on generated files and how to use them. diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl index 09248b321..5161c1826 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl @@ -36,6 +36,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim incr fcount +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc incr fcount @@ -52,10 +56,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_51 utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView incr fcount -- cgit v1.2.3 From ac0ce6f558baf9c2b55df3fbe21a8b1f596d8f72 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 12:57:02 -0700 Subject: Adding in files that probably didn;t exist in the ISE10.1 version of coregen --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise | 30 ++ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf | 0 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise | 374 ++++++++++++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise | 30 ++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise | 374 ++++++++++++++++++++++++ 5 files changed, 808 insertions(+) create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise new file mode 100644 index 000000000..c18cf3bf0 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise new file mode 100644 index 000000000..05048a43b --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise @@ -0,0 +1,374 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise new file mode 100644 index 000000000..d0c862319 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise new file mode 100644 index 000000000..d9013a131 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise @@ -0,0 +1,374 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3 From 030d98cef5133072ca53dddbb62669c57810c387 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 13:05:55 -0700 Subject: Edited FIFO instance to delete port that was not regenerated after reconfiguration --- usrp2/extramfifo/ext_fifo.v | 1 - 1 file changed, 1 deletion(-) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index c7e8f6cfb..398e5ef81 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -102,7 +102,6 @@ module ext_fifo .rd_en(dst_rdy_i), .dout(dataout), // Bus [35 : 0] .full(full2), - .almost_full(), .prog_full(almost_full2), .empty(empty2)); assign src_rdy_o = ~empty2; -- cgit v1.2.3 From bbe1965c18bb97d4a4d7b3cde1c343d147c23278 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 14:35:06 -0700 Subject: Regenerated FIFO's for extfifo. There are problems with certain configurations it seems. It is important that the fifo_xlnx_512x36_2clk_18to36 is generated with the "almost_full" pin even though it is not used in the application. if this pin is omitted the FPGA image doesn't work correctly --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf | 0 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 6 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo | 1 + usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 6 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise | 310 +-------------------- ...12x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso | 3 - ...k_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 102 ------- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise | 310 +-------------------- ...12x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso | 3 - 12 files changed, 19 insertions(+), 728 deletions(-) delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc index 27be491b9..3b3a07ee7 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index f718bb394..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,102 +0,0 @@ - - - - - - -

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- - - diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc index fa0753211..00814f02e 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco index b5bfdf3e8..d3115e7d5 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version 12.1 -# Date: Thu Aug 12 19:15:42 2010 +# Date: Thu Aug 12 21:06:13 2010 # ############################################################## # diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise index d9013a131..cfe983130 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise @@ -29,331 +29,29 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 -- cgit v1.2.3 From 12755e4e822441b73aad4ca3fdfbb157a3a86477 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 19 Aug 2010 12:46:04 -0700 Subject: Regenerated FIFO with lower trigger level for almost full flag to reflect logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code. --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 4 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 8 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise | 4 +- usrp2/extramfifo/ext_fifo.v | 29 +-- usrp2/extramfifo/ext_fifo_tb.v | 70 +++++++- usrp2/extramfifo/nobl_fifo.v | 229 +++--------------------- usrp2/top/u2_rev3/u2_core_udp.v | 3 +- usrp2/vrt/vita_tx_deframer.v | 4 +- 9 files changed, 115 insertions(+), 238 deletions(-) diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc index 3b3a07ee7..d9277b0c3 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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- - + + diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 398e5ef81..c6a64fc65 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -15,8 +15,10 @@ // packed into the IO ring. // + //`define NO_EXT_FIFO + module ext_fifo - #(parameter INT_WIDTH=36,EXT_WIDTH=18,DEPTH=19) + #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) ( input int_clk, input ext_clk, @@ -24,7 +26,7 @@ module ext_fifo input [EXT_WIDTH-1:0] RAM_D_pi, output [EXT_WIDTH-1:0] RAM_D_po, output RAM_D_poe, - output [DEPTH-1:0] RAM_A, + output [RAM_DEPTH-1:0] RAM_A, output RAM_WEn, output RAM_CENn, output RAM_LDn, @@ -59,16 +61,15 @@ module ext_fifo .empty(empty1)); assign dst_rdy_o = ~full1; - -/* -----\/----- EXCLUDED -----\/----- + +`ifdef NO_EXT_FIFO assign space_avail = ~full2; assign data_avail = ~empty1; assign read_data = write_data; - -----/\----- EXCLUDED -----/\----- */ +`else - // External FIFO running at ext clock rate and 18 bit width. - nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH),.FDEPTH(DEPTH)) + nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH)) nobl_fifo_i1 ( .clk(ext_clk), @@ -83,14 +84,14 @@ module ext_fifo .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), .write_data(write_data), - .write_strobe(space_avail & ~empty1 ), + .write_strobe(~empty1 ), .space_avail(space_avail), .read_data(read_data), - .read_strobe(data_avail & ~full2), - .data_avail(data_avail), - .upstream_full(almost_full2) + .read_strobe(~almost_full2), + .data_avail(data_avail) ); - +`endif // !`ifdef NO_EXT_FIFO + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( @@ -98,7 +99,7 @@ module ext_fifo .wr_clk(ext_clk), .rd_clk(int_clk), .din(read_data), // Bus [17 : 0] - .wr_en(data_avail & ~full2 ), + .wr_en(data_avail), .rd_en(dst_rdy_i), .dout(dataout), // Bus [35 : 0] .full(full2), @@ -106,5 +107,5 @@ module ext_fifo .empty(empty2)); assign src_rdy_o = ~empty2; - + endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index a93d524d5..db5f31a9d 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -1,7 +1,8 @@ `timescale 1ns / 1ps `define INT_WIDTH 36 `define EXT_WIDTH 18 -`define DEPTH 19 +`define RAM_DEPTH 19 +`define FIFO_DEPTH 8 `define DUMP_VCD_FULL module ext_fifo_tb(); @@ -17,7 +18,7 @@ module ext_fifo_tb(); wire [`EXT_WIDTH-1:0] RAM_D_po; wire [`EXT_WIDTH-1:0] RAM_D; wire RAM_D_poe; - wire [`DEPTH-1:0] RAM_A; + wire [`RAM_DEPTH-1:0] RAM_A; wire RAM_WEn; wire RAM_CENn; wire RAM_LDn; @@ -30,6 +31,7 @@ module ext_fifo_tb(); reg [`INT_WIDTH-1:0] ref_dataout; wire src_rdy_o; // not EMPTY reg dst_rdy_i; + integer ether_frame; // Clocks @@ -39,7 +41,6 @@ module ext_fifo_tb(); begin int_clk <= 0; ext_clk <= 0; - datain <= 0; ref_dataout <= 1; src_rdy_i <= 0; dst_rdy_i <= 0; @@ -53,6 +54,9 @@ module ext_fifo_tb(); initial begin + datain <= 0; + ether_frame <= 0; + rst <= 1; repeat (5) @(negedge int_clk); rst <= 0; @@ -62,6 +66,18 @@ module ext_fifo_tb(); @(negedge int_clk); datain <= datain + dst_rdy_o; src_rdy_i <= dst_rdy_o; + // Simulate inter-frame time + if (ether_frame == 1500) + begin + ether_frame <= 0; + repeat(1600) + begin + @(negedge int_clk); + src_rdy_i <= 0; + end + end + else + ether_frame <= ether_frame + dst_rdy_o; end end // initial begin @@ -73,8 +89,20 @@ module ext_fifo_tb(); // Fall through fifo, first output already valid if (dataout !== ref_dataout) $display("Error: Expected %x, got %x",ref_dataout, dataout); - - while (ref_dataout < 10000) + // Decimate by 16 rate + while (ref_dataout < 2000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(14) @(negedge int_clk); + end // while (ref_dataout < 10000) + // Decimate by 8 rate + while (ref_dataout < 4000) begin @(negedge int_clk); ref_dataout <= ref_dataout + src_rdy_o ; @@ -84,7 +112,33 @@ module ext_fifo_tb(); @(negedge int_clk); dst_rdy_i <= 0; repeat(6) @(negedge int_clk); - end + end // while (ref_dataout < 10000) + // Decimate by 4 rate + while (ref_dataout < 6000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(2) @(negedge int_clk); + end // while (ref_dataout < 10000) + // Max rate + while (ref_dataout < 10000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + + end // while (ref_dataout < 10000) + + @(negedge int_clk); + $finish; + end @@ -228,7 +282,7 @@ module ext_fifo_tb(); endgenerate - wire [`DEPTH-1:0] RAM_A_ext; + wire [`RAM_DEPTH-1:0] RAM_A_ext; wire RAM_WEn_ext,RAM_LDn_ext,RAM_CE1n_ext,RAM_OEn_ext,RAM_CENn_ext; assign #1 RAM_D_pi = RAM_D_pi_ext; @@ -292,7 +346,7 @@ module ext_fifo_tb(); ext_fifo - #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.DEPTH(`DEPTH)) + #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.RAM_DEPTH(`RAM_DEPTH),.FIFO_DEPTH(`FIFO_DEPTH)) ext_fifo_i1 ( .int_clk(int_clk), diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 03e3f5223..19f5fb84e 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -1,18 +1,19 @@ // Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port // device it can only sustain data throughput at half the RAM clock rate. // Fair arbitration to ensure this occurs is included in this logic and -// requests for transactions that can not be completed are held off by (re)using the -// "full" and "empty" flags. +// requests for transactions that can not be completed are held off. +// This FIFO requires a an external signal driving read_strobe that assures space for at least 6 +// reads since this the theopretical maximum number in flight due to pipeling. module nobl_fifo - #(parameter WIDTH=18,DEPTH=19,FDEPTH=10) + #(parameter WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) ( input clk, input rst, input [WIDTH-1:0] RAM_D_pi, output [WIDTH-1:0] RAM_D_po, output RAM_D_poe, - output [DEPTH-1:0] RAM_A, + output [RAM_DEPTH-1:0] RAM_A, output RAM_WEn, output RAM_CENn, output RAM_LDn, @@ -21,42 +22,32 @@ module nobl_fifo input [WIDTH-1:0] write_data, input write_strobe, output reg space_avail, - output reg [WIDTH-1:0] read_data, - input read_strobe, - output reg data_avail, - input upstream_full // (Connect to almost full flag upstream) + output [WIDTH-1:0] read_data, + input read_strobe, // Triggers a read, result in approximately 6 cycles. + output data_avail // Qulaifys read data available this cycle on read_data. ); - reg [FDEPTH-1:0] capacity; - reg [FDEPTH-1:0] wr_pointer; - reg [FDEPTH-1:0] rd_pointer; - wire [DEPTH-1:0] address; - reg supress; - reg data_avail_int; // Data available with high latency from ext FIFO flag - wire [WIDTH-1:0] data_in; - wire data_in_valid; - reg [WIDTH-1:0] read_data_pending; - reg pending_avail; - wire read_strobe_int; + reg [FIFO_DEPTH-1:0] capacity; + reg [FIFO_DEPTH-1:0] wr_pointer; + reg [FIFO_DEPTH-1:0] rd_pointer; + wire [RAM_DEPTH-1:0] address; + reg data_avail_int; // Internal not empty flag. - - - assign read = read_strobe_int && data_avail_int; - assign write = write_strobe && space_avail; + assign read = read_strobe && data_avail_int; + assign write = write_strobe && space_avail; - // When a read and write collision occur, supress the availability flags next cycle + // When a read and write collision occur, supress the space_avail flag next cycle // and complete write followed by read over 2 cycles. This forces balanced arbitration // and makes for a simple logic design. always @(posedge clk) if (rst) begin - capacity <= 1 << (FDEPTH-1); + capacity <= 1 << (FIFO_DEPTH-1); wr_pointer <= 0; rd_pointer <= 0; space_avail <= 0; data_avail_int <= 0; - supress <= 0; end else begin @@ -64,187 +55,15 @@ module nobl_fifo // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == (1 << (FDEPTH-1))) || (read&&write) || ((capacity == ((1 << (FDEPTH-1))-1)) && read) ); - supress <= read && write; + data_avail_int <= ~((capacity == (1 << (FIFO_DEPTH-1))) || ((capacity == ((1 << (FIFO_DEPTH-1))-1)) && read) ); wr_pointer <= wr_pointer + write; - rd_pointer <= rd_pointer + ((~write && read) || supress); - capacity <= capacity - write + ((~write && read) || supress); // REVISIT + rd_pointer <= rd_pointer + (~write && read); + capacity <= capacity - write + (~write && read) ; end // else: !if(rst) assign address = write ? wr_pointer : rd_pointer; - assign enable = write || read || supress; - - // - // Need to have first item in external FIFO moved into local registers for single cycle latency and throughput on read. - // 2 local registers are provided so that a read every other clock cycle can be sustained. - // No fowarding logic is provided to bypass the external FIFO as latency is of no concern. - // - always @(posedge clk) - if (rst) - begin - read_data <= 0; - data_avail <= 0; - read_data_pending <= 0; - pending_avail <= 0; - end - else - begin - case({read_strobe,data_in_valid}) - // No read externally, no new data arriving from external FIFO - 2'b00: begin - case({data_avail,pending_avail}) - // Start Data empty, Pending empty. - // - // End Data full, Pending empty - 2'b00: begin - read_data <= read_data; - data_avail <= data_avail; - read_data_pending <= read_data_pending ; - pending_avail <= pending_avail; - end - // Start Data empty, Pending full. - // Data <= Pending, - // End Data full, Penidng empty. - 2'b01: begin - read_data <= read_data_pending; - data_avail <= 1'b1; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - // Start Data full, Pending empty. - // - // End Data full, Pending empty - 2'b10: begin - read_data <= read_data; - data_avail <= data_avail; - read_data_pending <= read_data_pending ; - pending_avail <= pending_avail; - end - // Start Data full, Pending full. - // - // End Data full, Pending full. - 2'b11: begin - read_data <= read_data; - data_avail <= data_avail; - read_data_pending <= read_data_pending ; - pending_avail <= pending_avail; - end - endcase - end - // No read externally, new data arriving from external FIFO - 2'b01: begin - case({data_avail,pending_avail}) - // Start Data empty, Pending empty. - // Data <= FIFO - // End Data full, Pending empty - 2'b00: begin - read_data <= data_in; - data_avail <= 1'b1; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - // Start Data empty, Pending full. - // Data <= Pending, Pending <= FIFO - // End Data full, Penidng full. - 2'b01: begin - read_data <= read_data_pending; - data_avail <= 1'b1; - read_data_pending <= data_in ; - pending_avail <= 1'b1; - end - // Start Data full, Pending empty. - // Pending <= FIFO - // End Data full, Pending full - 2'b10: begin - read_data <= read_data; - data_avail <= 1'b1; - read_data_pending <= data_in ; - pending_avail <= 1'b1; - end - // Data full, Pending full. - // *ILLEGAL STATE* - 2'b11: begin - - end - endcase - end - // Read externally, no new data arriving from external FIFO - 2'b10: begin - case({data_avail,pending_avail}) - // Start Data empty, Pending empty. - // *ILLEGAL STATE* - 2'b00: begin - - end - // Start Data empty, Pending full. - // *ILLEGAL STATE* - 2'b01: begin - - end - // Start Data full, Pending empty. - // Out <= Data - // End Data empty, Pending empty. - 2'b10: begin - read_data <= read_data; - data_avail <= 1'b0; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - // Start Data full, Pending full. - // Out <= Data, - // End Data full, Pending empty - 2'b11: begin - read_data <= read_data_pending; - data_avail <= 1'b1; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - endcase - end - // Read externally, new data arriving from external FIFO - 2'b11: begin - case({data_avail,pending_avail}) - // Start Data empty, Pending empty. - // *ILLEGAL STATE* - 2'b00: begin - - end - // Start Data empty, Pending full. - // *ILLEGAL STATE* - 2'b01: begin - - end - // Start Data full, Pending empty. - // Out <= Data, Data <= FIFO - // End Data full, Pending empty. - 2'b10: begin - read_data <= data_in; - data_avail <= 1'b1; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - // Start Data full, Pending full. - // Out <= Data, Data <= Pending, Pending <= FIFO - // End Data full, Pending full - 2'b11: begin - read_data <= read_data_pending; - data_avail <= 1'b1; - read_data_pending <= data_in ; - pending_avail <= 1'b1; - end - endcase - end - endcase - end + assign enable = write || read; - // Start an external FIFO read as soon as a read of the buffer reg is strobed to minimise refill latency. - // If the buffer reg or the pending buffer reg is already empty also pre-emptively start a read. - // However there must be something in the main external FIFO to read for this to occur!. - // Pay special attention to upstream devices signalling full due to the number of potential in-flight reads\ that need - // to be stalled and stored somewhere. - // This means that there can be 3 outstanding reads to the ext FIFO active at any time helping to hide latency. - assign read_strobe_int = (read_strobe && data_avail && ~pending_avail && ~upstream_full) || (~data_avail && ~pending_avail && ~upstream_full); - // // Simple NoBL SRAM interface, 4 cycle read latency. @@ -265,10 +84,12 @@ module nobl_fifo .RAM_CE1n(RAM_CE1n), .address(address), .data_out(write_data), - .data_in(data_in), - .data_in_valid(data_in_valid), + .data_in(read_data), + .data_in_valid(data_avail), .write(write), .enable(enable) ); + + endmodule // nobl_fifo diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 33e9dbcd9..eba64c66b 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -653,11 +653,12 @@ module u2_core .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); -----/\----- EXCLUDED -----/\----- */ - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.DEPTH(19)) + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(8)) ext_fifo_i1 ( .int_clk(dsp_clk), .ext_clk(clk_to_mac), +// .ext_clk(wb_clk), .rst(dsp_rst), .RAM_D_pi(RAM_D_pi), .RAM_D_po(RAM_D_po), diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 220d3b061..4d5913b2a 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -70,7 +70,7 @@ module vita_tx_deframer <= 0; end else - if((vita_state == VITA_STORE) & fifo_space) + if((vita_state == VITA_STORE) & fifo_space /* IJB & src_rdy_i*/) if(eop) if(has_trailer_reg) vita_state <= VITA_TRAILER; @@ -168,7 +168,7 @@ module vita_tx_deframer 3: sample_d <= data_i[31:0]; endcase // case (vector_phase) - wire store = (vita_state == VITA_STORE); + wire store = (vita_state == VITA_STORE) /* IJB */ && fifo_space; fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), -- cgit v1.2.3 From 0e8a978c90c5793374861f29f72517f0070e596a Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 19 Aug 2010 17:28:07 -0700 Subject: Added a bunch of debug signals. --- usrp2/extramfifo/ext_fifo.v | 14 +++++++++++--- usrp2/extramfifo/ext_fifo_tb.cmd | 1 + usrp2/top/u2_rev3/u2_core_udp.v | 9 +++++---- usrp2/vrt/vita_tx_deframer.v | 4 ++-- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index c6a64fc65..b17fde10b 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -37,7 +37,8 @@ module ext_fifo output dst_rdy_o, // not FULL output [INT_WIDTH-1:0] dataout, output src_rdy_o, // not EMPTY - input dst_rdy_i // READ + input dst_rdy_i, // READ + output reg [31:0] debug ); wire [EXT_WIDTH-1:0] write_data; @@ -46,7 +47,8 @@ module ext_fifo wire almost_full2, full2, empty2; wire [INT_WIDTH-1:0] data_to_fifo; wire [INT_WIDTH-1:0] data_from_fifo; - + wire [FIFO_DEPTH-1:0] capacity; + // FIFO buffers data from UDP engine into external FIFO clock domain. fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( @@ -88,7 +90,8 @@ module ext_fifo .space_avail(space_avail), .read_data(read_data), .read_strobe(~almost_full2), - .data_avail(data_avail) + .data_avail(data_avail), + .capacity(capacity) ); `endif // !`ifdef NO_EXT_FIFO @@ -107,5 +110,10 @@ module ext_fifo .empty(empty2)); assign src_rdy_o = ~empty2; + always @ (posedge int_clk) + debug[31:16] = {12'h0,empty2,full1,dst_rdy_i,src_rdy_i }; + + always @ (posedge ext_clk) + debug[15:0] = {3'h0,empty1,space_avail,data_avail,full2,almost_full2,capacity[7:0] }; endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.cmd b/usrp2/extramfifo/ext_fifo_tb.cmd index b0ab830dc..521f88f21 100644 --- a/usrp2/extramfifo/ext_fifo_tb.cmd +++ b/usrp2/extramfifo/ext_fifo_tb.cmd @@ -1,6 +1,7 @@ /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v -y . -y ../coregen/ +-y ../fifo -y ../models -y /home/ianb/usrp-fpga/usrp2/sdr_lib -y /home/ianb/usrp-fpga/usrp2/control_lib diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 291a8e74e..ced67072e 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -171,7 +171,7 @@ module u2_core wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -686,7 +686,8 @@ module u2_core .dst_rdy_o(rd1_ready_i), // not FULL .dataout(tx_data), .src_rdy_o(tx_src_rdy), // not EMPTY - .dst_rdy_i(tx_dst_rdy) + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo) ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), @@ -784,8 +785,8 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = 2'b00; - assign debug = 32'd0; + assign debug_clk = {dsp_clk, clk_to_mac}; + assign debug = debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index f9cd7d00d..b62507092 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -84,7 +84,7 @@ module vita_tx_deframer seqnum_err <= 0; end else - if((vita_state == VITA_STORE) & fifo_space) + if((vita_state == VITA_STORE) & fifo_space ) //& src_rdy_i) if(eop) if(has_trailer_reg) vita_state <= VITA_TRAILER; @@ -183,7 +183,7 @@ module vita_tx_deframer 3: sample_d <= data_i[31:0]; endcase // case (vector_phase) - wire store = (vita_state == VITA_STORE); + wire store = (vita_state == VITA_STORE) ; //& src_rdy_i; fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), -- cgit v1.2.3 From 620d22dc6ad3ca1d9343eb7535ec2e0694be36b1 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 19 Aug 2010 17:30:31 -0700 Subject: Added capacity to the module pinout --- usrp2/extramfifo/nobl_fifo.v | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 19f5fb84e..cec2a5c4b 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -24,10 +24,11 @@ module nobl_fifo output reg space_avail, output [WIDTH-1:0] read_data, input read_strobe, // Triggers a read, result in approximately 6 cycles. - output data_avail // Qulaifys read data available this cycle on read_data. + output data_avail, // Qulaifys read data available this cycle on read_data. + output reg [FIFO_DEPTH-1:0] capacity ); - reg [FIFO_DEPTH-1:0] capacity; + //reg [FIFO_DEPTH-1:0] capacity; reg [FIFO_DEPTH-1:0] wr_pointer; reg [FIFO_DEPTH-1:0] rd_pointer; wire [RAM_DEPTH-1:0] address; @@ -43,7 +44,7 @@ module nobl_fifo always @(posedge clk) if (rst) begin - capacity <= 1 << (FIFO_DEPTH-1); + capacity <= (1 << FIFO_DEPTH) - 1; wr_pointer <= 0; rd_pointer <= 0; space_avail <= 0; -- cgit v1.2.3 From 492c5d53c31dd403817a27c6b25c30f8e089693b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 19 Aug 2010 20:25:15 -0700 Subject: capacity logic fix --- usrp2/extramfifo/nobl_fifo.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index cec2a5c4b..62229e6c2 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -56,7 +56,7 @@ module nobl_fifo // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == (1 << (FIFO_DEPTH-1))) || ((capacity == ((1 << (FIFO_DEPTH-1))-1)) && read) ); + data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && read) ); wr_pointer <= wr_pointer + write; rd_pointer <= rd_pointer + (~write && read); capacity <= capacity - write + (~write && read) ; -- cgit v1.2.3 From 8cd377d7195fae6b5dcd04318c992231fa633999 Mon Sep 17 00:00:00 2001 From: ianb Date: Wed, 25 Aug 2010 16:32:43 -0700 Subject: Corrected extfifo code so that all registers that are on SRAM signals are packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly --- usrp2/extramfifo/ext_fifo.v | 10 +++++-- usrp2/extramfifo/nobl_fifo.v | 4 +-- usrp2/extramfifo/nobl_if.v | 12 +++++--- usrp2/top/u2_rev3/u2_core_udp.v | 15 ++++++---- usrp2/top/u2_rev3/u2_rev3.ucf | 64 ++++++++++++++++++++--------------------- 5 files changed, 59 insertions(+), 46 deletions(-) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index b17fde10b..2af59a75d 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -38,7 +38,8 @@ module ext_fifo output [INT_WIDTH-1:0] dataout, output src_rdy_o, // not EMPTY input dst_rdy_i, // READ - output reg [31:0] debug + output reg [31:0] debug, + output reg [31:0] debug2 ); wire [EXT_WIDTH-1:0] write_data; @@ -111,9 +112,12 @@ module ext_fifo assign src_rdy_o = ~empty2; always @ (posedge int_clk) - debug[31:16] = {12'h0,empty2,full1,dst_rdy_i,src_rdy_i }; + debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; always @ (posedge ext_clk) - debug[15:0] = {3'h0,empty1,space_avail,data_avail,full2,almost_full2,capacity[7:0] }; + debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; + always@ (posedge ext_clk) +// debug2[31:0] <= {write_data[15:0],read_data[15:0]}; + debug2[31:0] <= 0; endmodule // ext_fifo diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 62229e6c2..4c009d980 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -47,7 +47,7 @@ module nobl_fifo capacity <= (1 << FIFO_DEPTH) - 1; wr_pointer <= 0; rd_pointer <= 0; - space_avail <= 0; + space_avail <= 1; data_avail_int <= 0; end else @@ -56,7 +56,7 @@ module nobl_fifo // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && read) ); + data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read)) ); wr_pointer <= wr_pointer + write; rd_pointer <= rd_pointer + (~write && read); capacity <= capacity - write + (~write && read) ; diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index 24d463b1e..391a841e8 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -9,11 +9,11 @@ module nobl_if output [WIDTH-1:0] RAM_D_po, output reg RAM_D_poe, output [DEPTH-1:0] RAM_A, - output RAM_WEn, + output reg RAM_WEn, output RAM_CENn, output RAM_LDn, output RAM_OEn, - output RAM_CE1n, + output reg RAM_CE1n, input [DEPTH-1:0] address, input [WIDTH-1:0] data_out, output reg [WIDTH-1:0] data_in, @@ -54,11 +54,15 @@ module nobl_if else begin enable_pipe1 <= enable; + RAM_CE1n <= ~enable; // Creates IOB flob + if (enable) begin address_pipe1 <= address; write_pipe1 <= write; + RAM_WEn <= ~write; // Creates IOB flob + if (write) data_out_pipe1 <= data_out; @@ -68,8 +72,8 @@ module nobl_if // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM assign RAM_A = address_pipe1; assign RAM_CENn = 1'b0; - assign RAM_WEn = ~write_pipe1; - assign RAM_CE1n = ~enable_pipe1; + // assign RAM_WEn = ~write_pipe1; +// assign RAM_CE1n = ~enable_pipe1; // // Pipeline stage2 diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index ced67072e..b2e540aad 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -171,7 +171,7 @@ module u2_core wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo; + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -414,7 +414,7 @@ module u2_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .gpio(/* {io_tx,io_rx}*/ ) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -681,13 +681,16 @@ module u2_core .RAM_LDn(RAM_LDn), .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), - .datain({rd1_flags,rd1_dat}), +// .datain({rd1_flags,rd1_dat}), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), .src_rdy_i(rd1_ready_o), // WRITE .dst_rdy_o(rd1_ready_i), // not FULL - .dataout(tx_data), +// .dataout(tx_data), + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), .src_rdy_o(tx_src_rdy), // not EMPTY .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo) + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), @@ -789,6 +792,8 @@ module u2_core assign debug = debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; + assign {io_tx,io_rx} = debug_extfifo2; + endmodule // u2_core diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 82d879446..bf9569fe4 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -264,22 +264,22 @@ NET "sdi_tx_adc" LOC = "J4" ; NET "sen_tx_dac" LOC = "H4" ; NET "sclk_tx_dac" LOC = "J5" ; NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" ; -NET "io_tx[1]" LOC = "K3" ; -NET "io_tx[2]" LOC = "G1" ; -NET "io_tx[3]" LOC = "G5" ; -NET "io_tx[4]" LOC = "H5" ; -NET "io_tx[5]" LOC = "F3" ; -NET "io_tx[6]" LOC = "F2" ; -NET "io_tx[7]" LOC = "F5" ; -NET "io_tx[8]" LOC = "G6" ; -NET "io_tx[9]" LOC = "E2" ; -NET "io_tx[10]" LOC = "E1" ; -NET "io_tx[11]" LOC = "E3" ; -NET "io_tx[12]" LOC = "F4" ; -NET "io_tx[13]" LOC = "D2" ; -NET "io_tx[14]" LOC = "D4" ; -NET "io_tx[15]" LOC = "E4" ; +NET "io_tx[0]" LOC = "K4" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[1]" LOC = "K3" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[2]" LOC = "G1" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[3]" LOC = "G5" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[4]" LOC = "H5" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[5]" LOC = "F3" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[6]" LOC = "F2" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[7]" LOC = "F5" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[8]" LOC = "G6" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[9]" LOC = "E2" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[10]" LOC = "E1" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[11]" LOC = "E3" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[12]" LOC = "F4" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[13]" LOC = "D2" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[14]" LOC = "D4" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[15]" LOC = "E4" |DRIVE = 12 |SLEW = FAST ; NET "sen_rx_db" LOC = "D22" ; NET "sclk_rx_db" LOC = "F19" ; NET "sdo_rx_db" LOC = "G20" ; @@ -291,22 +291,22 @@ NET "sdi_rx_adc" LOC = "H22" ; NET "sen_rx_dac" LOC = "J18" ; NET "sclk_rx_dac" LOC = "J19" ; NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" ; -NET "io_rx[1]" LOC = "L20" ; -NET "io_rx[2]" LOC = "L19" ; -NET "io_rx[3]" LOC = "L18" ; -NET "io_rx[4]" LOC = "L17" ; -NET "io_rx[5]" LOC = "K22" ; -NET "io_rx[6]" LOC = "K21" ; -NET "io_rx[7]" LOC = "K20" ; -NET "io_rx[8]" LOC = "G22" ; -NET "io_rx[9]" LOC = "G21" ; -NET "io_rx[10]" LOC = "F21" ; -NET "io_rx[11]" LOC = "F20" ; -NET "io_rx[12]" LOC = "G19" ; -NET "io_rx[13]" LOC = "G18" ; -NET "io_rx[14]" LOC = "G17" ; -NET "io_rx[15]" LOC = "E22" ; +NET "io_rx[0]" LOC = "L21" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[1]" LOC = "L20" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[2]" LOC = "L19" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[3]" LOC = "L18" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[4]" LOC = "L17" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[5]" LOC = "K22" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[6]" LOC = "K21" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[7]" LOC = "K20" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[8]" LOC = "G22" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[9]" LOC = "G21" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[10]" LOC = "F21" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[11]" LOC = "F20" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[12]" LOC = "G19" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[13]" LOC = "G18" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[14]" LOC = "G17" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[15]" LOC = "E22" |DRIVE = 12 |SLEW = FAST ; NET "clk_to_mac" TNM_NET = "clk_to_mac"; TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; -- cgit v1.2.3 From 596fc8d80ed2200f6d4bb597cb7185b63cf0be77 Mon Sep 17 00:00:00 2001 From: ianb Date: Wed, 25 Aug 2010 18:54:51 -0700 Subject: hangedddddddextrnal fifo size to use full NoBL SRAM --- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b2e540aad..2682926f6 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -665,7 +665,7 @@ module u2_core .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); -----/\----- EXCLUDED -----/\----- */ - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(8)) + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) ext_fifo_i1 ( .int_clk(dsp_clk), -- cgit v1.2.3 From f18bf439ad1456452532285eedd131c54065213c Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Wed, 1 Sep 2010 00:44:39 -0700 Subject: Enhanced test bench to be more like real world application --- usrp2/extramfifo/ext_fifo_tb.sh | 3 ++- usrp2/extramfifo/ext_fifo_tb.v | 18 ++++++++++++------ 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/usrp2/extramfifo/ext_fifo_tb.sh b/usrp2/extramfifo/ext_fifo_tb.sh index a56574102..dcfede37a 100644 --- a/usrp2/extramfifo/ext_fifo_tb.sh +++ b/usrp2/extramfifo/ext_fifo_tb.sh @@ -1 +1,2 @@ -fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb +#fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb +iverilog -c ext_fifo_tb.cmd -o ext_fifo_tb ext_fifo_tb.v diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index db5f31a9d..0eda89769 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -84,11 +84,17 @@ module ext_fifo_tb(); initial begin - repeat (20) @(negedge int_clk); + repeat (5) @(negedge int_clk); + dst_rdy_i <= 1; + + while (src_rdy_o !== 1) + @(negedge int_clk); // Fall through fifo, first output already valid if (dataout !== ref_dataout) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); + ref_dataout <= ref_dataout + src_rdy_o ; + // Decimate by 16 rate while (ref_dataout < 2000) begin @@ -96,7 +102,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(14) @(negedge int_clk); @@ -108,7 +114,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(6) @(negedge int_clk); @@ -120,7 +126,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(2) @(negedge int_clk); @@ -132,7 +138,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); end // while (ref_dataout < 10000) -- cgit v1.2.3 From c5295159e9f6eeb9ea72edab18ff97eb55d84692 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Wed, 1 Sep 2010 03:08:11 -0700 Subject: Added to DCM's and some BUFG's to align the internal 125MHz clock edge with its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet. --- usrp2/top/u2_rev3/u2_core.v | 2 +- usrp2/top/u2_rev3/u2_core_udp.v | 4 +- usrp2/top/u2_rev3/u2_rev3.ucf | 1 + usrp2/top/u2_rev3/u2_rev3.v | 99 ++++++++++++++++++++++++++++++++++++++++- 4 files changed, 101 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 9ba3cc136..a5963f6b1 100755 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -123,7 +123,7 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - output RAM_CLK, + // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 2682926f6..bcbaa1f30 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -125,7 +125,7 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - output RAM_CLK, + // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -775,7 +775,7 @@ module u2_core -----/\----- EXCLUDED -----/\----- */ //assign RAM_CLK = wb_clk; - assign RAM_CLK = clk_to_mac; + //assign RAM_CLK = clk_to_mac; // ///////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index bf9569fe4..175fbec8d 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -324,6 +324,7 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 8d9a18345..e9f8d76eb 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -370,14 +370,109 @@ module u2_rev3 ); end // block: gen_RAM_D_IO endgenerate + + // + // DCM edits start here + // + + + wire RAM_CLK_buf; + wire clk_to_mac_buf; + wire clk125_ext_clk0; + wire clk125_ext_clk180; + wire clk125_ext_clk0_buf; + wire clk125_ext_clk180_buf; + wire clk125_int_buf; + wire clk125_int; + + IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), + .O(clk_to_mac_buf)); + DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(clk125_ext_RST_IN), + .CLK0(clk125_ext_clk0), + .CLK180(clk125_ext_clk180) ); + defparam DCM_INST1.CLK_FEEDBACK = "1X"; + defparam DCM_INST1.CLKDV_DIVIDE = 2.0; + defparam DCM_INST1.CLKFX_DIVIDE = 1; + defparam DCM_INST1.CLKFX_MULTIPLY = 4; + defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST1.CLKIN_PERIOD = 8.000; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST1.FACTORY_JF = 16'h8080; + defparam DCM_INST1.PHASE_SHIFT = 0; + defparam DCM_INST1.STARTUP_WAIT = "FALSE"; + + IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), + .O(RAM_CLK_buf)); + BUFG clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), + .O(clk125_ext_clk0_buf)); + BUFG clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), + .O(clk125_ext_clk180_buf)); + + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk125_ext_clk0_buf), + .C1(clk125_ext_clk180_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + + SRL16 dcm2_rst_i1 (.D(1'b0), + .CLK(clk_to_mac_buf), + .Q(dcm2_rst), + .A0(1'b1), + .A1(1'b1), + .A2(1'b1), + .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i2 is "000F"; + + DCM DCM_INST2 (.CLKFB(clk125_int_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(clk125_int_RST_IN), + .CLK0(clk125_int)); + defparam DCM_INST2.CLK_FEEDBACK = "1X"; + defparam DCM_INST2.CLKDV_DIVIDE = 2.0; + defparam DCM_INST2.CLKFX_DIVIDE = 1; + defparam DCM_INST2.CLKFX_MULTIPLY = 4; + defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST2.CLKIN_PERIOD = 8.000; + defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST2.FACTORY_JF = 16'h8080; + defparam DCM_INST2.PHASE_SHIFT = 0; + defparam DCM_INST2.STARTUP_WAIT = "FALSE"; + + BUFG clk125_int_buf_i1 (.I(clk125_int), + .O(clk125_int_buf)); + + // + // DCM edits end here + // u2_core #(.RAM_SIZE(32768)) u2_core(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), + .clk_to_mac (clk125_int_buf), .pps_in (pps_in), .leds (leds_int), .debug (debug[31:0]), @@ -460,7 +555,7 @@ module u2_rev3 .RAM_A (RAM_A), .RAM_CE1n (RAM_CE1n), .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), + // .RAM_CLK (RAM_CLK), .RAM_WEn (RAM_WEn), .RAM_OEn (RAM_OEn), .RAM_LDn (RAM_LDn), -- cgit v1.2.3 From 7ffe28ccc6059ae3caa500e35b76718ae6ff100a Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Tue, 14 Sep 2010 11:46:58 -0700 Subject: Enabled phase offset adjustment on DCM_INST1 which drives the external Fast SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions. --- usrp2/top/u2_rev3/u2_rev3.v | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index e9f8d76eb..079a5cc4c 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -394,7 +394,7 @@ module u2_rev3 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), - .RST(clk125_ext_RST_IN), + .RST(1'b0), .CLK0(clk125_ext_clk0), .CLK180(clk125_ext_clk180) ); defparam DCM_INST1.CLK_FEEDBACK = "1X"; @@ -403,13 +403,13 @@ module u2_rev3 defparam DCM_INST1.CLKFX_MULTIPLY = 4; defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM_INST1.CLKIN_PERIOD = 8.000; - defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = 0; + defparam DCM_INST1.PHASE_SHIFT = -12; defparam DCM_INST1.STARTUP_WAIT = "FALSE"; IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), @@ -428,14 +428,14 @@ module u2_rev3 .R(1'b0), .S(1'b0)); - SRL16 dcm2_rst_i1 (.D(1'b0), - .CLK(clk_to_mac_buf), - .Q(dcm2_rst), - .A0(1'b1), - .A1(1'b1), - .A2(1'b1), - .A3(1'b1)); - // synthesis attribute init of dcm2_rst_i2 is "000F"; +// SRL16 dcm2_rst_i1 (.D(1'b0), +// .CLK(clk_to_mac_buf), +// .Q(dcm2_rst), +// .A0(1'b1), +// .A1(1'b1), +// .A2(1'b1), +// .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i1 is "000F"; DCM DCM_INST2 (.CLKFB(clk125_int_buf), .CLKIN(clk_to_mac_buf), @@ -443,7 +443,7 @@ module u2_rev3 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), - .RST(clk125_int_RST_IN), + .RST(1'b0), .CLK0(clk125_int)); defparam DCM_INST2.CLK_FEEDBACK = "1X"; defparam DCM_INST2.CLKDV_DIVIDE = 2.0; -- cgit v1.2.3 From 1c3dfe21f8bacbf762b440a23ce652a879288615 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 30 Sep 2010 15:54:03 -0700 Subject: Modified phase shift of DCM1 to -64 which is intended to give more timing margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock. --- usrp2/top/u2_rev3/u2_rev3.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 079a5cc4c..53f1e0a14 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -409,7 +409,7 @@ module u2_rev3 defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = -12; + defparam DCM_INST1.PHASE_SHIFT = -64; defparam DCM_INST1.STARTUP_WAIT = "FALSE"; IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), -- cgit v1.2.3 From c07bc03b4f0fe6210f3bfc6ecdc079487d882f7d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 1 Oct 2010 15:18:26 -0700 Subject: fix timing problem on DAC output bus --- usrp2/top/u2_rev3/u2_rev3.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 4daa66212..bab5a7706 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -330,8 +330,8 @@ module u2_rev3 wire [15:0] dac_a_int, dac_b_int; // DAC A and B are swapped in schematic to facilitate clean layout // DAC A is also inverted in schematic to facilitate clean layout - always @(negedge dsp_clk) dac_a <= ~dac_b_int; - always @(negedge dsp_clk) dac_b <= dac_a_int; + always @(posedge dsp_clk) dac_a <= ~dac_b_int; + always @(posedge dsp_clk) dac_b <= dac_a_int; /* OFDDRRSE OFDDRRSE_serdes_inst -- cgit v1.2.3 From 8d1214d5a0279fec2dcd2e2c2b97ea60250cc6d4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 6 Oct 2010 18:15:17 -0700 Subject: reconnect GPIOs, remove debug pins, meets timing now --- usrp2/top/u2_rev3/u2_core_udp.v | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 2cf7fe5ee..4879cfc6b 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -414,7 +414,7 @@ module u2_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio(/* {io_tx,io_rx}*/ ) ); + .gpio({io_tx,io_rx}) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -788,12 +788,10 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = {dsp_clk, clk_to_mac}; - assign debug = debug_extfifo; + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; - assign {io_tx,io_rx} = debug_extfifo2; - endmodule // u2_core -- cgit v1.2.3 From 26ada69153c8db487dda81ca63a5ea9c7ac6ba88 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 7 Oct 2010 11:10:00 -0700 Subject: revert unneeded changes and incorrect comments --- usrp2/fifo/fifo_cascade.v | 8 +++--- usrp2/top/u2_rev3/u2_rev3.ucf | 64 +++++++++++++++++++++---------------------- usrp2/vrt/vita_tx_deframer.v | 4 +-- 3 files changed, 38 insertions(+), 38 deletions(-) diff --git a/usrp2/fifo/fifo_cascade.v b/usrp2/fifo/fifo_cascade.v index ff2993ed5..fdd8449bc 100644 --- a/usrp2/fifo/fifo_cascade.v +++ b/usrp2/fifo/fifo_cascade.v @@ -10,11 +10,11 @@ module fifo_cascade #(parameter WIDTH=32, SIZE=9) (input clk, input reset, input clear, input [WIDTH-1:0] datain, - input src_rdy_i, // WRITE - output dst_rdy_o, // not FULL + input src_rdy_i, + output dst_rdy_o, output [WIDTH-1:0] dataout, - output src_rdy_o, // not EMPTY - input dst_rdy_i, // READ + output src_rdy_o, + input dst_rdy_i, output [15:0] space, output [15:0] occupied); diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 175fbec8d..6e0caedd5 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -264,22 +264,22 @@ NET "sdi_tx_adc" LOC = "J4" ; NET "sen_tx_dac" LOC = "H4" ; NET "sclk_tx_dac" LOC = "J5" ; NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[1]" LOC = "K3" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[2]" LOC = "G1" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[3]" LOC = "G5" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[4]" LOC = "H5" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[5]" LOC = "F3" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[6]" LOC = "F2" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[7]" LOC = "F5" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[8]" LOC = "G6" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[9]" LOC = "E2" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[10]" LOC = "E1" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[11]" LOC = "E3" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[12]" LOC = "F4" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[13]" LOC = "D2" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[14]" LOC = "D4" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[15]" LOC = "E4" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; NET "sen_rx_db" LOC = "D22" ; NET "sclk_rx_db" LOC = "F19" ; NET "sdo_rx_db" LOC = "G20" ; @@ -291,22 +291,22 @@ NET "sdi_rx_adc" LOC = "H22" ; NET "sen_rx_dac" LOC = "J18" ; NET "sclk_rx_dac" LOC = "J19" ; NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[1]" LOC = "L20" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[2]" LOC = "L19" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[3]" LOC = "L18" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[4]" LOC = "L17" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[5]" LOC = "K22" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[6]" LOC = "K21" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[7]" LOC = "K20" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[8]" LOC = "G22" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[9]" LOC = "G21" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[10]" LOC = "F21" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[11]" LOC = "F20" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[12]" LOC = "G19" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[13]" LOC = "G18" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[14]" LOC = "G17" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[15]" LOC = "E22" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; NET "clk_to_mac" TNM_NET = "clk_to_mac"; TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index b62507092..f9cd7d00d 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -84,7 +84,7 @@ module vita_tx_deframer seqnum_err <= 0; end else - if((vita_state == VITA_STORE) & fifo_space ) //& src_rdy_i) + if((vita_state == VITA_STORE) & fifo_space) if(eop) if(has_trailer_reg) vita_state <= VITA_TRAILER; @@ -183,7 +183,7 @@ module vita_tx_deframer 3: sample_d <= data_i[31:0]; endcase // case (vector_phase) - wire store = (vita_state == VITA_STORE) ; //& src_rdy_i; + wire store = (vita_state == VITA_STORE); fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), -- cgit v1.2.3 From 37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 14:01:33 -0700 Subject: checkpoint in flow control packet generation --- usrp2/vrt/gen_context_pkt.v | 37 +++++++++++++++++------- usrp2/vrt/trigger_context_pkt.v | 52 ++++++++++++++++++++++++++++++++++ usrp2/vrt/vita_tx_chain.v | 28 +++++++++++++------ usrp2/vrt/vita_tx_control.v | 10 +++++-- usrp2/vrt/vita_tx_deframer.v | 62 +++++++++++++++++++++++++++-------------- 5 files changed, 147 insertions(+), 42 deletions(-) create mode 100644 usrp2/vrt/trigger_context_pkt.v diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 780a027ba..f840ec6e1 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -3,10 +3,12 @@ module gen_context_pkt #(parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, - input trigger, output sent, + input trigger, input error, output sent, input [31:0] streamid, input [63:0] vita_time, input [31:0] message, + input [15:0] seqnum0, + input [15:0] seqnum1, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); localparam CTXT_IDLE = 0; @@ -17,17 +19,30 @@ module gen_context_pkt localparam CTXT_TICS = 5; localparam CTXT_TICS2 = 6; localparam CTXT_MESSAGE = 7; - localparam CTXT_DONE = 8; + localparam CTXT_FLOWCTRL = 8; + localparam CTXT_DONE = 9; reg [33:0] data_int; wire src_rdy_int, dst_rdy_int; - wire [3:0] seqno = 0; + reg [3:0] seqno; reg [3:0] ctxt_state; reg [63:0] err_time; + + always @(posedge clk) + if(reset | clear) + stored_message <= 0; + else + if(error) + stored_message <= message; + else if(state == CTXT_FLOWCTRL) + stored_message <= 0; always @(posedge clk) if(reset | clear) - ctxt_state <= CTXT_IDLE; + begin + ctxt_state <= CTXT_IDLE; + seqno <= 0; + end else case(ctxt_state) CTXT_IDLE : @@ -41,9 +56,10 @@ module gen_context_pkt end CTXT_DONE : - if(~trigger) - ctxt_state <= CTXT_IDLE; - + begin + ctxt_state <= CTXT_IDLE; + seqno <= seqno + 4'd1; + end default : if(dst_rdy_int) ctxt_state <= ctxt_state + 1; @@ -53,13 +69,14 @@ module gen_context_pkt always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd24 }; - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd6 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; - CTXT_MESSAGE : data_int <= { 2'b10, message }; + CTXT_MESSAGE : data_int <= { 2'b00, message }; + CTXT_FLOWCTRL : data_int <= { 2'b10, {seqnum1,seqnum0} }; default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) diff --git a/usrp2/vrt/trigger_context_pkt.v b/usrp2/vrt/trigger_context_pkt.v new file mode 100644 index 000000000..51790dfae --- /dev/null +++ b/usrp2/vrt/trigger_context_pkt.v @@ -0,0 +1,52 @@ + + +module trigger_context_pkt + #(parameter BASE=0) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input packet_consumed, output reg trigger); + + wire [23:0] cycles; + wire [15:0] packets; + wire [6:0] dummy1; + wire [14:0] dummy2; + wire enable_timed, enable_consumed; + reg [30:0] cycle_count, packet_count; + + + setting_reg #(.my_addr(BASE_CTRL+X), .at_reset(0)) sr_settings + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_cycle,dummy1,cycles}),.changed()); + + setting_reg #(.my_addr(BASE_CTRL+X), .at_reset(0)) sr_settings + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_consumed,dummy2,packets}),.changed()); + + always @(posedge clk) + if(reset | clear) + cycle_count <= 0; + else + if(trigger) + cycle_count <= 0; + else if(enable_cycle) + cycle_count <= cycle_count + 1; + + always @(posedge clk) + if(reset | clear) + packet_count <= 0; + else + if(trigger) + packet_count <= 0; + else if(packet_consumed & enable_consumed) + packet_count <= packet_count + 1; + + always @(posedge clk) + if(reset | clear) + trigger <= 0; + else + if((cycle_count > cycles)|(packet_count > packets)) + trigger <= 1; + else + trigger <= 0; + +endmodule // trigger_context_pkt diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 662cdca62..12e94b1a8 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -24,9 +24,10 @@ module vita_tx_chain wire trigger, sent; wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire error; + wire error, packet_consumed; wire [31:0] error_code; wire clear_seqnum; + wire [15:0] current_seqnum; assign underrun = error; assign message = error_code; @@ -40,6 +41,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .current_seqnum(current_seqnum), .debug(debug_vtd) ); vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control @@ -47,7 +49,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time),.error(error),.error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run), .strobe(strobe_tx), + .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed), .debug(debug_vtc) ); dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx @@ -59,13 +61,21 @@ module vita_tx_chain generate if(REPORT_ERROR==1) - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt - (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(error), .sent(), - .streamid(streamid), .vita_time(vita_time), .message(message), - .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + begin + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(trigger),.error(error), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .seqnum0(current_seqnum), .seqnum1(16'd0), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .packet_consumed(packet_consumed), .trigger(trigger)); + end endgenerate - - assign debug = debug_vtc | debug_vtd; + + //assign debug = debug_vtc | debug_vtd; + assign debug = { debug_vtd[15:0], current_seqnum }; endmodule // vita_tx_chain diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index d0516bec8..61cd9edb5 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -8,7 +8,8 @@ module vita_tx_control input [63:0] vita_time, output error, output reg [31:0] error_code, - + output reg packet_consumed, + // From vita_tx_deframer input [5+64+16+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, @@ -154,9 +155,14 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - //assign error = (ibs_state == IBS_ERROR_DONE); assign error = send_error; + always @(posedge clk) + if(reset) + packet_consumed <= 0; + else + packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; + assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index f9cd7d00d..f7902e645 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -13,6 +13,8 @@ module vita_tx_deframer output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, + + output [15:0] current_seqnum, // FIFO Levels output [15:0] fifo_occupied, @@ -45,23 +47,29 @@ module vita_tx_deframer reg [1:0] vector_phase; wire line_done; - reg seqnum_err; - reg [3:0] seqnum_reg; - wire [3:0] seqnum = data_i[19:16]; - wire [3:0] next_seqnum = seqnum_reg + 4'd1; + wire [15:0] seqnum = data_i[15:0]; + reg [15:0] seqnum_reg; + wire [15:0] next_seqnum = seqnum_reg + 16'd1; + wire [3:0] vita_seqnum = data_i[19:16]; + reg [3:0] vita_seqnum_reg; + wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; + reg seqnum_err; + + assign curren_seqnum = seqnum_reg; // Output FIFO for packetized data - localparam VITA_HEADER = 0; - localparam VITA_STREAMID = 1; - localparam VITA_CLASSID = 2; - localparam VITA_CLASSID2 = 3; - localparam VITA_SECS = 4; - localparam VITA_TICS = 5; - localparam VITA_TICS2 = 6; - localparam VITA_PAYLOAD = 7; - localparam VITA_STORE = 8; - localparam VITA_TRAILER = 9; - + localparam VITA_TRANS_HEADER = 0; + localparam VITA_HEADER = 1; + localparam VITA_STREAMID = 2; + localparam VITA_CLASSID = 3; + localparam VITA_CLASSID2 = 4; + localparam VITA_SECS = 5; + localparam VITA_TICS = 6; + localparam VITA_TICS2 = 7; + localparam VITA_PAYLOAD = 8; + localparam VITA_STORE = 9; + localparam VITA_TRAILER = 10; + wire [15:0] hdr_len = 2 + has_streamid_reg + has_classid_reg + has_classid_reg + has_secs_reg + has_tics_reg + has_tics_reg + has_trailer_reg; @@ -70,15 +78,22 @@ module vita_tx_deframer always @(posedge clk) if(reset | clear_seqnum) - seqnum_reg <= 4'hF; + begin + seqnum_reg <= 16'hFFFF; + vita_seqnum_reg <= 4'hF; + end else - if((vita_state==VITA_HEADER) & src_rdy_i) - seqnum_reg <= seqnum; + begin + if((vita_state==VITA_TRANS_HEADER) & src_rdy_i) + seqnum_reg <= seqnum; + if((vita_state==VITA_HEADER) & src_rdy_i) + vita_seqnum_reg <= vita_seqnum; + end // else: !if(reset | clear_seqnum) always @(posedge clk) if(reset | clear) begin - vita_state <= VITA_HEADER; + vita_state <= VITA_TRANS_HEADER; {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; seqnum_err <= 0; @@ -97,6 +112,11 @@ module vita_tx_deframer end else if(src_rdy_i) case(vita_state) + VITA_TRANS_HEADER : + begin + seqnum_err <= ~(seqnum == next_seqnum); + vita_state <= VITA_HEADER; + end VITA_HEADER : begin {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} @@ -113,7 +133,7 @@ module vita_tx_deframer vita_state <= VITA_TICS; else vita_state <= VITA_PAYLOAD; - seqnum_err <= ~(seqnum == next_seqnum); + seqnum_err <= seqnum_err | ~(vita_seqnum == next_vita_seqnum); end // case: VITA_HEADER VITA_STREAMID : if(has_classid_reg) @@ -191,7 +211,7 @@ module vita_tx_deframer // sob, eob, has_secs (send_at) ignored on all lines except first assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop, - 12'd0,seqnum_reg,send_time}; + 12'd0,seqnum_reg[3:0],send_time}; assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; -- cgit v1.2.3 From ecadee9c605c65849856d56cf842dd65e27181f6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 14:07:26 -0700 Subject: declarations --- usrp2/vrt/gen_context_pkt.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index f840ec6e1..0ea2797ec 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -27,14 +27,15 @@ module gen_context_pkt reg [3:0] seqno; reg [3:0] ctxt_state; reg [63:0] err_time; - + reg [31:0] stored_message; + always @(posedge clk) if(reset | clear) stored_message <= 0; else if(error) stored_message <= message; - else if(state == CTXT_FLOWCTRL) + else if(ctxt_state == CTXT_FLOWCTRL) stored_message <= 0; always @(posedge clk) -- cgit v1.2.3 From d8d5158e6d20d86689807c887102f684ec80cea8 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 14:33:06 -0700 Subject: assign setting reg addresses --- usrp2/vrt/trigger_context_pkt.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/vrt/trigger_context_pkt.v b/usrp2/vrt/trigger_context_pkt.v index 51790dfae..226ec45f2 100644 --- a/usrp2/vrt/trigger_context_pkt.v +++ b/usrp2/vrt/trigger_context_pkt.v @@ -14,11 +14,11 @@ module trigger_context_pkt reg [30:0] cycle_count, packet_count; - setting_reg #(.my_addr(BASE_CTRL+X), .at_reset(0)) sr_settings + setting_reg #(.my_addr(BASE+4), .at_reset(0)) sr_cycles (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_cycle,dummy1,cycles}),.changed()); - setting_reg #(.my_addr(BASE_CTRL+X), .at_reset(0)) sr_settings + setting_reg #(.my_addr(BASE+5), .at_reset(0)) sr_packets (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_consumed,dummy2,packets}),.changed()); -- cgit v1.2.3 From 8d20d691531c582e51affd734020daa27317de38 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 15:17:49 -0700 Subject: add trigger to makefile --- usrp2/vrt/Makefile.srcs | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs index dc4bd8c96..aa1356d82 100644 --- a/usrp2/vrt/Makefile.srcs +++ b/usrp2/vrt/Makefile.srcs @@ -12,4 +12,5 @@ vita_tx_control.v \ vita_tx_deframer.v \ vita_tx_chain.v \ gen_context_pkt.v \ +trigger_context_pkt.v \ )) -- cgit v1.2.3 From b32c3729f847c1e7fc064d9306f814f99214c78c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 16:01:42 -0700 Subject: add a fifo to the end of the mux to help in timing. --- usrp2/fifo/fifo36_mux.v | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 92bf13ff9..c6fd40f27 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -20,6 +20,9 @@ module fifo36_mux wire eof0 = data0_i[33]; wire eof1 = data1_i[33]; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + always @(posedge clk) if(reset | clear) state <= MUX_IDLE0; @@ -32,7 +35,7 @@ module fifo36_mux state <= MUX_DATA1; MUX_DATA0 : - if(src0_rdy_i & dst_rdy_i & eof0) + if(src0_rdy_i & dst_rdy_int & eof0) state <= prio ? MUX_IDLE0 : MUX_IDLE1; MUX_IDLE1 : @@ -42,16 +45,20 @@ module fifo36_mux state <= MUX_DATA0; MUX_DATA1 : - if(src1_rdy_i & dst_rdy_i & eof1) + if(src1_rdy_i & dst_rdy_int & eof1) state <= MUX_IDLE0; default : state <= MUX_IDLE0; endcase // case (state) - assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; - assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; - assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; + assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; + assign data_int = (state==MUX_DATA0) ? data0_i : data1_i; + fifo_short #(.WIDTH(36)) mux_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); endmodule // fifo36_demux -- cgit v1.2.3 From e16fbb404322cb75a7b8abe8abe8afd594464d8a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 18:01:10 -0700 Subject: go to the correct state --- usrp2/vrt/vita_tx_deframer.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index f7902e645..e12747cd5 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -104,7 +104,7 @@ module vita_tx_deframer if(has_trailer_reg) vita_state <= VITA_TRAILER; else - vita_state <= VITA_HEADER; + vita_state <= VITA_TRANS_HEADER; else begin vita_state <= VITA_PAYLOAD; @@ -171,11 +171,11 @@ module vita_tx_deframer else vector_phase <= vector_phase + 1; VITA_TRAILER : - vita_state <= VITA_HEADER; + vita_state <= VITA_TRANS_HEADER; VITA_STORE : ; default : - vita_state <= VITA_HEADER; + vita_state <= VITA_TRANS_HEADER; endcase // case (vita_state) assign line_done = (vector_phase == numchan); -- cgit v1.2.3 From a3cf4ea0fca439b91a299eee782ee7858c3a9468 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 10 Oct 2010 23:38:56 -0700 Subject: separated flow control and error reporting on tx path. should work with and without flow control --- usrp2/top/u2_rev3/u2_core_udp.v | 3 ++- usrp2/vrt/gen_context_pkt.v | 4 ++-- usrp2/vrt/vita_tx_chain.v | 50 +++++++++++++++++++++++++++-------------- usrp2/vrt/vita_tx_deframer.v | 11 ++++----- 4 files changed, 43 insertions(+), 25 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 4879cfc6b..809218a75 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -694,7 +694,8 @@ module u2_core ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 0ea2797ec..31c2a53e1 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -3,7 +3,7 @@ module gen_context_pkt #(parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, - input trigger, input error, output sent, + input trigger, output sent, input [31:0] streamid, input [63:0] vita_time, input [31:0] message, @@ -33,7 +33,7 @@ module gen_context_pkt if(reset | clear) stored_message <= 0; else - if(error) + if(trigger) stored_message <= message; else if(ctxt_state == CTXT_FLOWCTRL) stored_message <= 0; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 12e94b1a8..09da377f8 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -3,7 +3,9 @@ module vita_tx_chain #(parameter BASE_CTRL=0, parameter BASE_DSP=0, parameter REPORT_ERROR=0, - parameter PROT_ENG_FLAGS=0) + parameter DO_FLOW_CONTROL=0, + parameter PROT_ENG_FLAGS=0, + parameter USE_TRANS_HEADER=0) (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, @@ -36,7 +38,10 @@ module vita_tx_chain (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed(clear_seqnum)); - vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer + vita_tx_deframer #(.BASE(BASE_CTRL), + .MAXCHAN(MAXCHAN), + .USE_TRANS_HEADER(USE_TRANS_HEADER)) + vita_tx_deframer (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), @@ -59,23 +64,34 @@ module vita_tx_chain .dac_a(dac_a),.dac_b(dac_b), .debug(debug_tx_dsp) ); - generate - if(REPORT_ERROR==1) - begin - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt - (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(trigger),.error(error), .sent(), - .streamid(streamid), .vita_time(vita_time), .message(message), - .seqnum0(current_seqnum), .seqnum1(16'd0), - .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); - trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt - (.clk(clk), .reset(reset), .clear(clear_vita), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .packet_consumed(packet_consumed), .trigger(trigger)); - end - endgenerate + wire [35:0] flow_data, err_data_int; + wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int; + + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(32'd0), + .seqnum0(current_seqnum), .seqnum1(16'd0), + .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy)); + trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .packet_consumed(packet_consumed), .trigger(trigger)); + + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(error & (REPORT_ERROR==1)), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .seqnum0(current_seqnum), .seqnum1(16'd0), + .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); //assign debug = debug_vtc | debug_vtd; assign debug = { debug_vtd[15:0], current_seqnum }; + fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages + (.clk(clk), .reset(reset), .clear(clear_vita), + .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int), + .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + endmodule // vita_tx_chain diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index e12747cd5..c55f43373 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -1,7 +1,8 @@ module vita_tx_deframer #(parameter BASE=0, - parameter MAXCHAN=1) + parameter MAXCHAN=1, + parameter USE_TRANS_HEADER=0) (input clk, input reset, input clear, input clear_seqnum, input set_stb, input [7:0] set_addr, input [31:0] set_data, @@ -93,7 +94,7 @@ module vita_tx_deframer always @(posedge clk) if(reset | clear) begin - vita_state <= VITA_TRANS_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; seqnum_err <= 0; @@ -104,7 +105,7 @@ module vita_tx_deframer if(has_trailer_reg) vita_state <= VITA_TRAILER; else - vita_state <= VITA_TRANS_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; else begin vita_state <= VITA_PAYLOAD; @@ -171,11 +172,11 @@ module vita_tx_deframer else vector_phase <= vector_phase + 1; VITA_TRAILER : - vita_state <= VITA_TRANS_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; VITA_STORE : ; default : - vita_state <= VITA_TRANS_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; endcase // case (vita_state) assign line_done = (vector_phase == numchan); -- cgit v1.2.3 From 369c0e1dbc1518bd0fe2f81bec5e197d0c3bfe41 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 8 Oct 2010 17:41:19 -0700 Subject: usrp2: implement fc seq number on tx header packing --- host/lib/usrp/usrp2/io_impl.cpp | 54 ++++++++++++++++++++++++-------------- host/lib/usrp/usrp2/usrp2_impl.cpp | 6 ++--- host/lib/usrp/usrp2/usrp2_impl.hpp | 6 ++--- 3 files changed, 41 insertions(+), 25 deletions(-) diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index eba704059..b7585afe9 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -18,11 +18,11 @@ #include "../../transport/vrt_packet_handler.hpp" #include "usrp2_impl.hpp" #include "usrp2_regs.hpp" +#include #include #include #include #include -#include //htonl and ntohl #include #include #include @@ -32,7 +32,12 @@ using namespace uhd::usrp; using namespace uhd::transport; namespace asio = boost::asio; -static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; +static const int underflow_flags = 0 + | async_metadata_t::EVENT_CODE_UNDERFLOW + | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET +; + +static const size_t vrt_send_header_offset_words32 = 1; /*********************************************************************** * io impl details (internal to this file) @@ -63,6 +68,27 @@ struct usrp2_impl::io_impl{ return recv_pirate_booty->pop_elems_with_timed_wait(buffs, timeout); } + bool get_send_buffs( + const std::vector &trans, + vrt_packet_handler::managed_send_buffs_t &buffs, + double timeout + ){ + UHD_ASSERT_THROW(trans.size() == buffs.size()); + + //calculate the 16-bit sequence number for the special header + const boost::uint32_t next_seq = uhd::htonx(boost::uint32_t( + packet_handler_send_state.next_packet_seq & 0xffff + )); + + //grab a managed buffer for each index + for (size_t i = 0; i < buffs.size(); i++){ + buffs[i] = trans[i]->get_send_buff(timeout); + if (not buffs[i].get()) return false; + buffs[i]->cast()[0] = next_seq; + } + return true; + } + //state management for the vrt packet handler code vrt_packet_handler::recv_state packet_handler_recv_state; vrt_packet_handler::send_state packet_handler_send_state; @@ -146,7 +172,9 @@ void usrp2_impl::io_init(void){ //send a small data packet so the usrp2 knows the udp source port BOOST_FOREACH(zero_copy_if::sptr data_transport, _data_transports){ managed_send_buffer::sptr send_buff = data_transport->get_send_buff(); - static const boost::uint32_t data = htonl(USRP2_INVALID_VRT_HEADER); + static const boost::uint32_t data = uhd::htonx( + boost::uint32_t(USRP2_INVALID_VRT_HEADER) + ); std::memcpy(send_buff->cast(), &data, sizeof(data)); send_buff->commit(sizeof(data)); //drain the recv buffers (may have junk) @@ -183,23 +211,10 @@ bool usrp2_impl::recv_async_msg( /*********************************************************************** * Send Data **********************************************************************/ -static bool get_send_buffs( - const std::vector &trans, - vrt_packet_handler::managed_send_buffs_t &buffs, - double timeout -){ - UHD_ASSERT_THROW(trans.size() == buffs.size()); - bool good = true; - for (size_t i = 0; i < buffs.size(); i++){ - buffs[i] = trans[i]->get_send_buff(timeout); - good = good and (buffs[i].get() != NULL); - } - return good; -} - size_t usrp2_impl::get_max_send_samps_per_packet(void) const{ static const size_t hdr_size = 0 + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + + vrt_send_header_offset_words32*sizeof(boost::uint32_t) - sizeof(vrt::if_packet_info_t().cid) //no class id ever used ; const size_t bpp = _data_transports.front()->get_send_frame_size() - hdr_size; @@ -218,8 +233,9 @@ size_t usrp2_impl::send( io_type, _tx_otw_type, //input and output types to convert _mboards.front()->get_master_clock_freq(), //master clock tick rate uhd::transport::vrt::if_hdr_pack_be, - boost::bind(&get_send_buffs, _data_transports, _1, timeout), - get_max_send_samps_per_packet() + boost::bind(&usrp2_impl::io_impl::get_send_buffs, _io_impl.get(), _data_transports, _1, timeout), + get_max_send_samps_per_packet(), + vrt_send_header_offset_words32 ); } diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index a680708ad..8429a2593 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -17,7 +17,7 @@ #include "usrp2_impl.hpp" #include -#include +#include #include #include #include @@ -128,7 +128,7 @@ static device::sptr usrp2_make(const device_addr_t &device_addr){ //create a ctrl and data transport for each address std::vector ctrl_transports; - std::vector data_transports; + std::vector data_transports; BOOST_FOREACH(const std::string &addr, std::split_string(device_addr["addr"])){ ctrl_transports.push_back(udp_simple::make_connected( @@ -154,7 +154,7 @@ UHD_STATIC_BLOCK(register_usrp2_device){ **********************************************************************/ usrp2_impl::usrp2_impl( std::vector ctrl_transports, - std::vector data_transports + std::vector data_transports ): _data_transports(data_transports) { diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index 558726a2b..6d35e925d 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -33,7 +33,7 @@ #include #include #include //mtu -#include +#include #include #include @@ -178,7 +178,7 @@ public: */ usrp2_impl( std::vector ctrl_transports, - std::vector data_transports + std::vector data_transports ); ~usrp2_impl(void); @@ -208,7 +208,7 @@ private: uhd::dict _mboard_dict; //io impl methods and members - std::vector _data_transports; + std::vector _data_transports; uhd::otw_type_t _rx_otw_type, _tx_otw_type; UHD_PIMPL_DECL(io_impl) _io_impl; void io_init(void); -- cgit v1.2.3 From 37f1f1451f65aace9ca978ac3edcaa31d16e8c0d Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 8 Oct 2010 18:04:37 -0700 Subject: usrp2: add fc control registers, use small timeout for control packets again --- host/lib/usrp/usrp2/usrp2_iface.cpp | 12 +----------- host/lib/usrp/usrp2/usrp2_regs.hpp | 5 +++++ 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/host/lib/usrp/usrp2/usrp2_iface.cpp b/host/lib/usrp/usrp2/usrp2_iface.cpp index 2d450bfc6..6fdde7b2e 100644 --- a/host/lib/usrp/usrp2/usrp2_iface.cpp +++ b/host/lib/usrp/usrp2/usrp2_iface.cpp @@ -30,17 +30,7 @@ using namespace uhd; using namespace uhd::transport; -/*! - * FIXME: large timeout, ethernet pause frames... - * - * Use a large timeout to work-around the fact that - * flow-control may throttle outgoing control packets - * due to its use of ethernet pause frames. - * - * This will be fixed when host-based flow control is implemented, - * along with larger incoming send buffers using the on-board SRAM. - */ -static const size_t CONTROL_TIMEOUT_MS = 3000; //3 seconds +static const size_t CONTROL_TIMEOUT_MS = 200; class usrp2_iface_impl : public usrp2_iface{ public: diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 064ad4e95..bdd5194f9 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -193,9 +193,14 @@ #define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) #define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) #define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3) +#define U2_REG_TX_CTRL_CYCLES_PER_ACK _SR_ADDR(SR_TX_CTRL + 4) +#define U2_REG_TX_CTRL_PACKETS_PER_ACK _SR_ADDR(SR_TX_CTRL + 5) #define U2_FLAG_TX_CTRL_POLICY_WAIT (0x1 << 0) #define U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET (0x1 << 1) #define U2_FLAG_TX_CTRL_POLICY_NEXT_BURST (0x1 << 2) +//enable flag for registers: cycles and packets per ack +#define U2_FLAG_TX_CTRL_ACK_ENB (1ul << 31) + #endif /* INCLUDED_USRP2_REGS_HPP */ -- cgit v1.2.3 From b338398599e915a66e6d329bffa45b955992b491 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 13:57:17 -0700 Subject: typo which isn't caught by xilinx --- usrp2/vrt/vita_tx_deframer.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index c55f43373..d8575b745 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -56,7 +56,7 @@ module vita_tx_deframer wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; reg seqnum_err; - assign curren_seqnum = seqnum_reg; + assign current_seqnum = seqnum_reg; // Output FIFO for packetized data localparam VITA_TRANS_HEADER = 0; -- cgit v1.2.3 From e45ee09da1f064e58e49d126b3144df198b11fc2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 15:53:24 -0700 Subject: send message on eob to ack the end of transmission --- usrp2/vrt/vita_tx_control.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 61cd9edb5..ed470418b 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -49,6 +49,7 @@ module vita_tx_control localparam IBS_ERROR_DONE = 4; localparam IBS_ERROR_WAIT = 5; + wire [31:0] CODE_EOB_ACK = {seqnum,16'd1}; wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8}; @@ -107,7 +108,11 @@ module vita_tx_control end else if(eop) if(eob) - ibs_state <= IBS_IDLE; + begin + ibs_state <= IBS_ERROR; // Not really an error + error_code <= CODE_EOB_ACK; + send_error <= 1; + end else ibs_state <= IBS_CONT_BURST; -- cgit v1.2.3 From 453b450aa2f40f1ab3689855654fd2167f554ccc Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 11 Oct 2010 16:31:51 -0700 Subject: usrp2: implemented flow control monitor set registers in mboard impl to enable asyn fc packets modified microblaze code to handle dummy data packet offset --- firmware/microblaze/apps/txrx_uhd.c | 2 +- host/lib/usrp/usrp2/fw_common.h | 2 +- host/lib/usrp/usrp2/io_impl.cpp | 103 +++++++++++++++++++++++++++++++----- host/lib/usrp/usrp2/mboard_impl.cpp | 14 +++-- host/lib/usrp/usrp2/usrp2_impl.cpp | 4 +- host/lib/usrp/usrp2/usrp2_impl.hpp | 7 ++- 6 files changed, 110 insertions(+), 22 deletions(-) diff --git a/firmware/microblaze/apps/txrx_uhd.c b/firmware/microblaze/apps/txrx_uhd.c index 1dd6e80ac..e38eb621d 100644 --- a/firmware/microblaze/apps/txrx_uhd.c +++ b/firmware/microblaze/apps/txrx_uhd.c @@ -372,7 +372,7 @@ eth_pkt_inspector(dbsm_t *sm, int bufno) // In the future, a hardware state machine will do this... if ( //warning! magic numbers approaching.... (((buff + ((2 + 14 + 20)/sizeof(uint32_t)))[0] & 0xffff) == USRP2_UDP_DATA_PORT) && - ((buff + ((2 + 14 + 20 + 8)/sizeof(uint32_t)))[0] != USRP2_INVALID_VRT_HEADER) + ((buff + ((2 + 14 + 20 + 8)/sizeof(uint32_t)))[1] != USRP2_INVALID_VRT_HEADER) ) return false; //test if its an ip recovery packet diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h index e812e1221..783e5c772 100644 --- a/host/lib/usrp/usrp2/fw_common.h +++ b/host/lib/usrp/usrp2/fw_common.h @@ -34,7 +34,7 @@ extern "C" { //fpga and firmware compatibility numbers #define USRP2_FPGA_COMPAT_NUM 2 -#define USRP2_FW_COMPAT_NUM 6 +#define USRP2_FW_COMPAT_NUM 7 //used to differentiate control packets over data port #define USRP2_INVALID_VRT_HEADER 0 diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index b7585afe9..6d5eb488c 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -32,6 +32,9 @@ using namespace uhd::usrp; using namespace uhd::transport; namespace asio = boost::asio; +/*********************************************************************** + * constants + **********************************************************************/ static const int underflow_flags = 0 | async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET @@ -39,6 +42,67 @@ static const int underflow_flags = 0 static const size_t vrt_send_header_offset_words32 = 1; +/*********************************************************************** + * flow control monitor for a single tx channel + * - the pirate thread calls update + * - the get send buffer calls check + **********************************************************************/ +class flow_control_monitor{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new flow control monitor. + * \param max_seqs_out num seqs before throttling + */ + flow_control_monitor(size_t max_seqs_out){ + _last_seq_out = 0; + _last_seq_ack = 0; + _max_seqs_out = max_seqs_out; + } + + /*! + * Check the flow control condition. + * \param seq the sequence to go out + * \param timeout the timeout in seconds + * \return false on timeout + */ + UHD_INLINE bool check_fc_condition(boost::uint16_t seq, double timeout){ + boost::unique_lock lock(_fc_mutex); + _last_seq_out = seq; + return _fc_cond.timed_wait( + lock, + boost::posix_time::microseconds(long(timeout*1e6)), + boost::bind(&flow_control_monitor::ready, this) + ); + } + + /*! + * Update the flow control condition. + * \param seq the last sequence number to be ACK'd + */ + UHD_INLINE void update_fc_condition(boost::uint16_t seq){ + boost::unique_lock lock(_fc_mutex); + _last_seq_ack = seq; + lock.unlock(); + _fc_cond.notify_one(); + } + +private: + bool ready(void){ + //return true; + //std::cout << "_last_seq_out " << _last_seq_out << std::endl; + //std::cout << "_last_seq_ack " << _last_seq_ack << std::endl; + //std::cout << "boost::uint16_t(_last_seq_out -_last_seq_ack) " << boost::uint16_t(_last_seq_out -_last_seq_ack) << std::endl; + return boost::uint16_t(_last_seq_out -_last_seq_ack) < boost::uint16_t(_max_seqs_out); + } + + boost::mutex _fc_mutex; + boost::condition _fc_cond; + boost::uint16_t _last_seq_out, _last_seq_ack; + size_t _max_seqs_out; +}; + /*********************************************************************** * io impl details (internal to this file) * - pirate crew @@ -49,12 +113,14 @@ static const size_t vrt_send_header_offset_words32 = 1; struct usrp2_impl::io_impl{ typedef alignment_buffer alignment_buffer_type; - io_impl(size_t num_frames, size_t width): + io_impl(size_t num_recv_frames, size_t send_frame_size, size_t width): packet_handler_recv_state(width), - recv_pirate_booty(alignment_buffer_type::make(num_frames, width)), + recv_pirate_booty(alignment_buffer_type::make(num_recv_frames, width)), async_msg_fifo(bounded_buffer::make(100/*messages deep*/)) { - /* NOP */ + for (size_t i = 0; i < width; i++) fc_mons.push_back( + flow_control_monitor::sptr(new flow_control_monitor(usrp2_impl::sram_bytes/send_frame_size)) + ); } ~io_impl(void){ @@ -76,19 +142,22 @@ struct usrp2_impl::io_impl{ UHD_ASSERT_THROW(trans.size() == buffs.size()); //calculate the 16-bit sequence number for the special header - const boost::uint32_t next_seq = uhd::htonx(boost::uint32_t( - packet_handler_send_state.next_packet_seq & 0xffff - )); + const boost::uint16_t seq_num = boost::uint16_t(packet_handler_send_state.next_packet_seq & 0xffff); + const boost::uint32_t fc_word32 = uhd::htonx(boost::uint32_t(seq_num)); //grab a managed buffer for each index for (size_t i = 0; i < buffs.size(); i++){ + if (not fc_mons[i]->check_fc_condition(seq_num, timeout)) return false; buffs[i] = trans[i]->get_send_buff(timeout); if (not buffs[i].get()) return false; - buffs[i]->cast()[0] = next_seq; + buffs[i]->cast()[0] = fc_word32; } return true; } + //flow control monitors + std::vector fc_mons; + //state management for the vrt packet handler code vrt_packet_handler::recv_state packet_handler_recv_state; vrt_packet_handler::send_state packet_handler_send_state; @@ -138,6 +207,13 @@ void usrp2_impl::io_impl::recv_pirate_loop( ); metadata.event_code = vrt_packet_handler::get_context_code(vrt_hdr, if_packet_info); + //catch the flow control packets and react + if (metadata.event_code == 0){ + boost::uint32_t fc_word32 = uhd::ntohx((vrt_hdr + if_packet_info.num_header_words32)[1]); + this->fc_mons[index]->update_fc_condition(fc_word32 & 0xffff); + continue; + } + //print the famous U, and push the metadata into the message queue if (metadata.event_code & underflow_flags) std::cerr << "U" << std::flush; async_msg_fifo->push_with_pop_on_full(metadata); @@ -172,21 +248,22 @@ void usrp2_impl::io_init(void){ //send a small data packet so the usrp2 knows the udp source port BOOST_FOREACH(zero_copy_if::sptr data_transport, _data_transports){ managed_send_buffer::sptr send_buff = data_transport->get_send_buff(); - static const boost::uint32_t data = uhd::htonx( - boost::uint32_t(USRP2_INVALID_VRT_HEADER) - ); + static const boost::uint32_t data[2] = { + uhd::htonx(boost::uint32_t(0 /* don't care seq num */)), + uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER)) + }; std::memcpy(send_buff->cast(), &data, sizeof(data)); send_buff->commit(sizeof(data)); //drain the recv buffers (may have junk) while (data_transport->get_recv_buff().get()){}; } - //the number of recv frames is the number for the first transport //the assumption is that all data transports should be identical - size_t num_frames = _data_transports.front()->get_num_recv_frames(); + const size_t num_recv_frames = _data_transports.front()->get_num_recv_frames(); + const size_t send_frame_size = _data_transports.front()->get_send_frame_size(); //create new io impl - _io_impl = UHD_PIMPL_MAKE(io_impl, (num_frames, _data_transports.size())); + _io_impl = UHD_PIMPL_MAKE(io_impl, (num_recv_frames, send_frame_size, _data_transports.size())); //create a new pirate thread for each zc if (yarr!!) for (size_t i = 0; i < _data_transports.size(); i++){ diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index a0e6adfad..37e69b39d 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -38,10 +38,11 @@ using namespace uhd::usrp; usrp2_mboard_impl::usrp2_mboard_impl( size_t index, transport::udp_simple::sptr ctrl_transport, - size_t recv_frame_size + size_t recv_samps_per_packet, + size_t send_bytes_per_packet ): _index(index), - _recv_frame_size(recv_frame_size) + _recv_samps_per_packet(recv_samps_per_packet) { //make a new interface for usrp2 stuff _iface = usrp2_iface::make(ctrl_transport); @@ -75,7 +76,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); //init the rx control registers - _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _recv_frame_size); + _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _recv_samps_per_packet); _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1); _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); //reset _iface->poke32(U2_REG_RX_CTRL_VRT_HEADER, 0 @@ -93,6 +94,11 @@ usrp2_mboard_impl::usrp2_mboard_impl( _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1); //sid 1 (different from rx) _iface->poke32(U2_REG_TX_CTRL_POLICY, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); + const size_t cycles_per_ack = size_t(_clock_ctrl->get_master_clock_rate()/100); //100 aps + //_iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_ACK, U2_FLAG_TX_CTRL_ACK_ENB | cycles_per_ack); //FIXME total pause frames + static const double sram_frac = 1.0/8.0; //fraction of sram to fill before ack + const size_t packets_per_ack = size_t(usrp2_impl::sram_bytes*sram_frac/send_bytes_per_packet); + _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_ACK, U2_FLAG_TX_CTRL_ACK_ENB | packets_per_ack); //init the ddc init_ddc_config(); @@ -178,7 +184,7 @@ void usrp2_mboard_impl::set_time_spec(const time_spec_t &time_spec, bool now){ void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){ _iface->poke32(U2_REG_RX_CTRL_STREAM_CMD, dsp_type1::calc_stream_cmd_word( - stream_cmd, _recv_frame_size + stream_cmd, _recv_samps_per_packet )); _iface->poke32(U2_REG_RX_CTRL_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); _iface->poke32(U2_REG_RX_CTRL_TIME_TICKS, stream_cmd.time_spec.get_tick_count(get_master_clock_freq())); diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index 8429a2593..79bf2b260 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -173,7 +173,9 @@ usrp2_impl::usrp2_impl( //create a new mboard handler for each control transport for(size_t i = 0; i < ctrl_transports.size(); i++){ _mboards.push_back(usrp2_mboard_impl::sptr(new usrp2_mboard_impl( - i, ctrl_transports[i], this->get_max_recv_samps_per_packet() + i, ctrl_transports[i], + this->get_max_recv_samps_per_packet(), + _data_transports[i]->get_send_frame_size() ))); //use an empty name when there is only one mboard std::string name = (ctrl_transports.size() > 1)? boost::lexical_cast(i) : ""; diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index 6d35e925d..2077b0a50 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -84,7 +84,8 @@ public: usrp2_mboard_impl( size_t index, uhd::transport::udp_simple::sptr, - size_t recv_frame_size + size_t recv_samps_per_packet, + size_t send_bytes_per_packet ); ~usrp2_mboard_impl(void); @@ -95,7 +96,7 @@ public: private: size_t _index; int _rev_hi, _rev_lo; - const size_t _recv_frame_size; + const size_t _recv_samps_per_packet; //properties for this mboard void get(const wax::obj &, wax::obj &); @@ -171,6 +172,8 @@ private: */ class usrp2_impl : public uhd::device{ public: + static const size_t sram_bytes = size_t(1 << 20); + /*! * Create a new usrp2 impl base. * \param ctrl_transports the udp transports for control -- cgit v1.2.3 From e650ed086c68c9e3458c91817fd0b01da261cd57 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 16:39:31 -0700 Subject: switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate --- usrp2/vrt/gen_context_pkt.v | 18 ++++++++++-------- usrp2/vrt/vita_tx_chain.v | 2 +- usrp2/vrt/vita_tx_deframer.v | 10 +++++----- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 31c2a53e1..0eb035f3e 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -7,8 +7,8 @@ module gen_context_pkt input [31:0] streamid, input [63:0] vita_time, input [31:0] message, - input [15:0] seqnum0, - input [15:0] seqnum1, + input [31:0] seqnum0, + input [31:0] seqnum1, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); localparam CTXT_IDLE = 0; @@ -19,8 +19,9 @@ module gen_context_pkt localparam CTXT_TICS = 5; localparam CTXT_TICS2 = 6; localparam CTXT_MESSAGE = 7; - localparam CTXT_FLOWCTRL = 8; - localparam CTXT_DONE = 9; + localparam CTXT_FLOWCTRL0 = 8; + localparam CTXT_FLOWCTRL1 = 9; + localparam CTXT_DONE = 10; reg [33:0] data_int; wire src_rdy_int, dst_rdy_int; @@ -35,7 +36,7 @@ module gen_context_pkt else if(trigger) stored_message <= message; - else if(ctxt_state == CTXT_FLOWCTRL) + else if(ctxt_state == CTXT_FLOWCTRL1) stored_message <= 0; always @(posedge clk) @@ -70,14 +71,15 @@ module gen_context_pkt always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd32 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd8 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; CTXT_MESSAGE : data_int <= { 2'b00, message }; - CTXT_FLOWCTRL : data_int <= { 2'b10, {seqnum1,seqnum0} }; + CTXT_FLOWCTRL0 : data_int <= { 2'b00, seqnum0 }; + CTXT_FLOWCTRL1 : data_int <= { 2'b10, seqnum1 }; default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 09da377f8..eee19bebf 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -29,7 +29,7 @@ module vita_tx_chain wire error, packet_consumed; wire [31:0] error_code; wire clear_seqnum; - wire [15:0] current_seqnum; + wire [31:0] current_seqnum; assign underrun = error; assign message = error_code; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index d8575b745..40867cc55 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -15,7 +15,7 @@ module vita_tx_deframer output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, - output [15:0] current_seqnum, + output [31:0] current_seqnum, // FIFO Levels output [15:0] fifo_occupied, @@ -48,9 +48,9 @@ module vita_tx_deframer reg [1:0] vector_phase; wire line_done; - wire [15:0] seqnum = data_i[15:0]; - reg [15:0] seqnum_reg; - wire [15:0] next_seqnum = seqnum_reg + 16'd1; + wire [31:0] seqnum = data_i; + reg [31:0] seqnum_reg; + wire [31:0] next_seqnum = seqnum_reg + 32'd1; wire [3:0] vita_seqnum = data_i[19:16]; reg [3:0] vita_seqnum_reg; wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; @@ -80,7 +80,7 @@ module vita_tx_deframer always @(posedge clk) if(reset | clear_seqnum) begin - seqnum_reg <= 16'hFFFF; + seqnum_reg <= 32'hFFFF_FFFF; vita_seqnum_reg <= 4'hF; end else -- cgit v1.2.3 From 41489884015ceb3dd2d4731ece813445d20629d3 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 16:40:25 -0700 Subject: increase compatibility number for flow control --- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 809218a75..d2bc01d6d 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -427,7 +427,7 @@ module u2_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd2; + localparam compat_num = 32'd3; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), -- cgit v1.2.3 From 0edf80fc80303c475b0dfd29d3ce5967fe646bfc Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 16:41:41 -0700 Subject: cleanup for 32 bit seqnum --- usrp2/vrt/vita_tx_chain.v | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index eee19bebf..6cfbdf763 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -71,7 +71,7 @@ module vita_tx_chain (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(32'd0), - .seqnum0(current_seqnum), .seqnum1(16'd0), + .seqnum0(current_seqnum), .seqnum1(32'd0), .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy)); trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt (.clk(clk), .reset(reset), .clear(clear_vita), @@ -82,11 +82,10 @@ module vita_tx_chain (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(error & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), - .seqnum0(current_seqnum), .seqnum1(16'd0), + .seqnum0(current_seqnum), .seqnum1(32'd0), .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); - //assign debug = debug_vtc | debug_vtd; - assign debug = { debug_vtd[15:0], current_seqnum }; + assign debug = debug_vtc | debug_vtd; fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages (.clk(clk), .reset(reset), .clear(clear_vita), -- cgit v1.2.3 From 1314feb429b8c2713d9fd0e9da077825d0a9c3bc Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 11 Oct 2010 18:09:56 -0700 Subject: usrp2: use 32-bit flow control sequence numbers --- host/include/uhd/types/metadata.hpp | 4 ++-- host/lib/usrp/usrp2/fw_common.h | 2 +- host/lib/usrp/usrp2/io_impl.cpp | 29 ++++++++++++----------------- 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/host/include/uhd/types/metadata.hpp b/host/include/uhd/types/metadata.hpp index 65952941c..96c4ad0d3 100644 --- a/host/include/uhd/types/metadata.hpp +++ b/host/include/uhd/types/metadata.hpp @@ -130,7 +130,7 @@ namespace uhd{ /*! * Event codes: - * - success: a packet was successfully transmitted + * - eob ack: an eob packet was successfully transmitted * - underflow: an internal send buffer has emptied * - sequence error: packet loss between host and device * - time error: packet had time that was late (or too early) @@ -138,7 +138,7 @@ namespace uhd{ * - sequence error in burst: packet loss within a burst */ enum event_code_t { - EVENT_CODE_SUCCESS = 0x1, + EVENT_CODE_EOB_ACK = 0x1, EVENT_CODE_UNDERFLOW = 0x2, EVENT_CODE_SEQ_ERROR = 0x4, EVENT_CODE_TIME_ERROR = 0x8, diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h index 783e5c772..2cd3ee595 100644 --- a/host/lib/usrp/usrp2/fw_common.h +++ b/host/lib/usrp/usrp2/fw_common.h @@ -33,7 +33,7 @@ extern "C" { #endif //fpga and firmware compatibility numbers -#define USRP2_FPGA_COMPAT_NUM 2 +#define USRP2_FPGA_COMPAT_NUM 3 #define USRP2_FW_COMPAT_NUM 7 //used to differentiate control packets over data port diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 6d5eb488c..2d1ebe57b 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -49,13 +49,14 @@ static const size_t vrt_send_header_offset_words32 = 1; **********************************************************************/ class flow_control_monitor{ public: + typedef boost::uint32_t seq_type; typedef boost::shared_ptr sptr; /*! * Make a new flow control monitor. * \param max_seqs_out num seqs before throttling */ - flow_control_monitor(size_t max_seqs_out){ + flow_control_monitor(seq_type max_seqs_out){ _last_seq_out = 0; _last_seq_ack = 0; _max_seqs_out = max_seqs_out; @@ -67,7 +68,7 @@ public: * \param timeout the timeout in seconds * \return false on timeout */ - UHD_INLINE bool check_fc_condition(boost::uint16_t seq, double timeout){ + UHD_INLINE bool check_fc_condition(seq_type seq, double timeout){ boost::unique_lock lock(_fc_mutex); _last_seq_out = seq; return _fc_cond.timed_wait( @@ -81,7 +82,7 @@ public: * Update the flow control condition. * \param seq the last sequence number to be ACK'd */ - UHD_INLINE void update_fc_condition(boost::uint16_t seq){ + UHD_INLINE void update_fc_condition(seq_type seq){ boost::unique_lock lock(_fc_mutex); _last_seq_ack = seq; lock.unlock(); @@ -90,17 +91,12 @@ public: private: bool ready(void){ - //return true; - //std::cout << "_last_seq_out " << _last_seq_out << std::endl; - //std::cout << "_last_seq_ack " << _last_seq_ack << std::endl; - //std::cout << "boost::uint16_t(_last_seq_out -_last_seq_ack) " << boost::uint16_t(_last_seq_out -_last_seq_ack) << std::endl; - return boost::uint16_t(_last_seq_out -_last_seq_ack) < boost::uint16_t(_max_seqs_out); + return seq_type(_last_seq_out -_last_seq_ack) < _max_seqs_out; } boost::mutex _fc_mutex; boost::condition _fc_cond; - boost::uint16_t _last_seq_out, _last_seq_ack; - size_t _max_seqs_out; + seq_type _last_seq_out, _last_seq_ack, _max_seqs_out; }; /*********************************************************************** @@ -141,16 +137,15 @@ struct usrp2_impl::io_impl{ ){ UHD_ASSERT_THROW(trans.size() == buffs.size()); - //calculate the 16-bit sequence number for the special header - const boost::uint16_t seq_num = boost::uint16_t(packet_handler_send_state.next_packet_seq & 0xffff); - const boost::uint32_t fc_word32 = uhd::htonx(boost::uint32_t(seq_num)); + //calculate the flow control word + const boost::uint32_t fc_word32 = packet_handler_send_state.next_packet_seq; //grab a managed buffer for each index for (size_t i = 0; i < buffs.size(); i++){ - if (not fc_mons[i]->check_fc_condition(seq_num, timeout)) return false; + if (not fc_mons[i]->check_fc_condition(fc_word32, timeout)) return false; buffs[i] = trans[i]->get_send_buff(timeout); if (not buffs[i].get()) return false; - buffs[i]->cast()[0] = fc_word32; + buffs[i]->cast()[0] = uhd::htonx(fc_word32); } return true; } @@ -209,8 +204,8 @@ void usrp2_impl::io_impl::recv_pirate_loop( //catch the flow control packets and react if (metadata.event_code == 0){ - boost::uint32_t fc_word32 = uhd::ntohx((vrt_hdr + if_packet_info.num_header_words32)[1]); - this->fc_mons[index]->update_fc_condition(fc_word32 & 0xffff); + boost::uint32_t fc_word32 = (vrt_hdr + if_packet_info.num_header_words32)[1]; + this->fc_mons[index]->update_fc_condition(uhd::ntohx(fc_word32)); continue; } -- cgit v1.2.3 From d54fd2abffd8849bf41a5f8084a828e6472ba342 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 11 Oct 2010 18:21:16 -0700 Subject: usrp2: use select rather than manually polling the simple udp socket --- host/include/uhd/transport/udp_simple.hpp | 4 +-- host/lib/transport/udp_simple.cpp | 44 +++++++++++++++---------------- host/lib/usrp/usrp2/usrp2_iface.cpp | 4 +-- host/lib/usrp/usrp2/usrp2_impl.cpp | 5 +--- 4 files changed, 26 insertions(+), 31 deletions(-) diff --git a/host/include/uhd/transport/udp_simple.hpp b/host/include/uhd/transport/udp_simple.hpp index c84393ecf..83f895ba9 100644 --- a/host/include/uhd/transport/udp_simple.hpp +++ b/host/include/uhd/transport/udp_simple.hpp @@ -73,10 +73,10 @@ public: * Receive into the provided buffer. * Blocks until data is received or a timeout occurs. * \param buff a mutable buffer to receive into - * \param timeout_ms the timeout in milliseconds + * \param timeout the timeout in seconds * \return the number of bytes received or zero on timeout */ - virtual size_t recv(const boost::asio::mutable_buffer &buff, size_t timeout_ms) = 0; + virtual size_t recv(const boost::asio::mutable_buffer &buff, double timeout = 0.1) = 0; }; }} //namespace diff --git a/host/lib/transport/udp_simple.cpp b/host/lib/transport/udp_simple.cpp index 89750f99d..5829b462b 100644 --- a/host/lib/transport/udp_simple.cpp +++ b/host/lib/transport/udp_simple.cpp @@ -27,23 +27,25 @@ using namespace uhd::transport; * Helper Functions **********************************************************************/ /*! - * A receive timeout for a socket: - * - * It seems that asio cannot have timeouts with synchronous io. - * However, we can implement a polling loop that will timeout. - * This is okay bacause this is the slow-path implementation. - * + * Wait for available data or timeout. * \param socket the asio socket - * \param timeout_ms the timeout in milliseconds + * \param timeout the timeout in seconds + * \return false for timeout, true for data */ -static void reasonable_recv_timeout( - boost::asio::ip::udp::socket &socket, size_t timeout_ms +static bool wait_available( + boost::asio::ip::udp::socket &socket, double timeout ){ - boost::asio::deadline_timer timer(socket.get_io_service()); - timer.expires_from_now(boost::posix_time::milliseconds(timeout_ms)); - while (not (socket.available() or timer.expires_from_now().is_negative())){ - boost::this_thread::sleep(boost::posix_time::milliseconds(1)); - } + //setup timeval for timeout + timeval tv; + tv.tv_sec = 0; + tv.tv_usec = long(timeout*1e6); + + //setup rset for timeout + fd_set rset; + FD_ZERO(&rset); + FD_SET(socket.native(), &rset); + + return ::select(socket.native()+1, &rset, NULL, NULL, &tv) > 0; } /*********************************************************************** @@ -57,7 +59,7 @@ public: //send/recv size_t send(const boost::asio::const_buffer &); - size_t recv(const boost::asio::mutable_buffer &, size_t); + size_t recv(const boost::asio::mutable_buffer &, double); private: boost::asio::ip::udp::socket *_socket; @@ -86,9 +88,8 @@ size_t udp_connected_impl::send(const boost::asio::const_buffer &buff){ return _socket->send(boost::asio::buffer(buff)); } -size_t udp_connected_impl::recv(const boost::asio::mutable_buffer &buff, size_t timeout_ms){ - reasonable_recv_timeout(*_socket, timeout_ms); - if (not _socket->available()) return 0; +size_t udp_connected_impl::recv(const boost::asio::mutable_buffer &buff, double timeout){ + if (not wait_available(*_socket, timeout)) return 0; return _socket->receive(boost::asio::buffer(buff)); } @@ -103,7 +104,7 @@ public: //send/recv size_t send(const boost::asio::const_buffer &); - size_t recv(const boost::asio::mutable_buffer &, size_t); + size_t recv(const boost::asio::mutable_buffer &, double); private: boost::asio::ip::udp::socket *_socket; @@ -137,9 +138,8 @@ size_t udp_broadcast_impl::send(const boost::asio::const_buffer &buff){ return _socket->send_to(boost::asio::buffer(buff), _receiver_endpoint); } -size_t udp_broadcast_impl::recv(const boost::asio::mutable_buffer &buff, size_t timeout_ms){ - reasonable_recv_timeout(*_socket, timeout_ms); - if (not _socket->available()) return 0; +size_t udp_broadcast_impl::recv(const boost::asio::mutable_buffer &buff, double timeout){ + if (not wait_available(*_socket, timeout)) return 0; boost::asio::ip::udp::endpoint sender_endpoint; return _socket->receive_from(boost::asio::buffer(buff), sender_endpoint); } diff --git a/host/lib/usrp/usrp2/usrp2_iface.cpp b/host/lib/usrp/usrp2/usrp2_iface.cpp index 6fdde7b2e..55c42567e 100644 --- a/host/lib/usrp/usrp2/usrp2_iface.cpp +++ b/host/lib/usrp/usrp2/usrp2_iface.cpp @@ -30,8 +30,6 @@ using namespace uhd; using namespace uhd::transport; -static const size_t CONTROL_TIMEOUT_MS = 200; - class usrp2_iface_impl : public usrp2_iface{ public: /*********************************************************************** @@ -177,7 +175,7 @@ public: boost::uint8_t usrp2_ctrl_data_in_mem[udp_simple::mtu]; //allocate max bytes for recv const usrp2_ctrl_data_t *ctrl_data_in = reinterpret_cast(usrp2_ctrl_data_in_mem); while(true){ - size_t len = _ctrl_transport->recv(boost::asio::buffer(usrp2_ctrl_data_in_mem), CONTROL_TIMEOUT_MS); + size_t len = _ctrl_transport->recv(boost::asio::buffer(usrp2_ctrl_data_in_mem)); if(len >= sizeof(boost::uint32_t) and ntohl(ctrl_data_in->proto_ver) != USRP2_FW_COMPAT_NUM){ throw std::runtime_error(str(boost::format( "Expected protocol compatibility number %d, but got %d:\n" diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index 79bf2b260..1d9f25019 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -35,9 +35,6 @@ using namespace uhd::usrp; using namespace uhd::transport; namespace asio = boost::asio; -//! wait this long for a control response when discovering devices -static const size_t DISCOVERY_TIMEOUT_MS = 100; - /*********************************************************************** * Helper Functions **********************************************************************/ @@ -99,7 +96,7 @@ static uhd::device_addrs_t usrp2_find(const device_addr_t &hint){ boost::uint8_t usrp2_ctrl_data_in_mem[udp_simple::mtu]; //allocate max bytes for recv const usrp2_ctrl_data_t *ctrl_data_in = reinterpret_cast(usrp2_ctrl_data_in_mem); while(true){ - size_t len = udp_transport->recv(asio::buffer(usrp2_ctrl_data_in_mem), DISCOVERY_TIMEOUT_MS); + size_t len = udp_transport->recv(asio::buffer(usrp2_ctrl_data_in_mem)); //std::cout << len << "\n"; if (len > offsetof(usrp2_ctrl_data_t, data)){ //handle the received data -- cgit v1.2.3 From b49e2955b0f68d59e7903f89a26c39dc9b3614fd Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 11 Oct 2010 18:38:06 -0700 Subject: usrp2: enable the cycles per ack, and drain recv without the timeout (fixes previous conflict) --- host/lib/usrp/usrp2/io_impl.cpp | 2 +- host/lib/usrp/usrp2/mboard_impl.cpp | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 2d1ebe57b..c9271cc8c 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -250,7 +250,7 @@ void usrp2_impl::io_init(void){ std::memcpy(send_buff->cast(), &data, sizeof(data)); send_buff->commit(sizeof(data)); //drain the recv buffers (may have junk) - while (data_transport->get_recv_buff().get()){}; + while (data_transport->get_recv_buff(0).get()){}; } //the assumption is that all data transports should be identical diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 37e69b39d..ddf147c8d 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -95,7 +95,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1); //sid 1 (different from rx) _iface->poke32(U2_REG_TX_CTRL_POLICY, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); const size_t cycles_per_ack = size_t(_clock_ctrl->get_master_clock_rate()/100); //100 aps - //_iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_ACK, U2_FLAG_TX_CTRL_ACK_ENB | cycles_per_ack); //FIXME total pause frames + _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_ACK, U2_FLAG_TX_CTRL_ACK_ENB | cycles_per_ack); static const double sram_frac = 1.0/8.0; //fraction of sram to fill before ack const size_t packets_per_ack = size_t(usrp2_impl::sram_bytes*sram_frac/send_bytes_per_packet); _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_ACK, U2_FLAG_TX_CTRL_ACK_ENB | packets_per_ack); @@ -121,7 +121,8 @@ usrp2_mboard_impl::usrp2_mboard_impl( } usrp2_mboard_impl::~usrp2_mboard_impl(void){ - /* NOP */ + _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_ACK, 0); + _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_ACK, 0); } /*********************************************************************** -- cgit v1.2.3 From f9755b0ab33eb20abb5689893061f3b4039505fd Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 12 Oct 2010 10:55:07 -0700 Subject: uhd: test eob ack message, usrp2: remove rx drain on init with the promise of a reset register --- host/examples/test_async_messages.cpp | 32 ++++++++++++++++++++------------ host/lib/usrp/usrp2/io_impl.cpp | 2 -- host/lib/usrp/usrp2/mboard_impl.cpp | 5 ----- 3 files changed, 20 insertions(+), 19 deletions(-) diff --git a/host/examples/test_async_messages.cpp b/host/examples/test_async_messages.cpp index e4a996ef5..fa39bcde6 100644 --- a/host/examples/test_async_messages.cpp +++ b/host/examples/test_async_messages.cpp @@ -27,13 +27,13 @@ namespace po = boost::program_options; /*! - * Test that no messages are received: + * Test the eob ack message: * Send a burst of many samples that will fragment internally. - * We expect to not get any async messages. + * We expect to get an eob ack async message. */ -void test_no_async_message(uhd::usrp::single_usrp::sptr sdev){ +void test_ack_async_message(uhd::usrp::single_usrp::sptr sdev){ uhd::device::sptr dev = sdev->get_device(); - std::cout << "Test no async message... " << std::flush; + std::cout << "Test eob ack message... " << std::flush; uhd::tx_metadata_t md; md.start_of_burst = true; @@ -50,19 +50,27 @@ void test_no_async_message(uhd::usrp::single_usrp::sptr sdev){ ); uhd::async_metadata_t async_md; - if (dev->recv_async_msg(async_md)){ + if (not dev->recv_async_msg(async_md)){ std::cout << boost::format( "failed:\n" - " Got unexpected event code 0x%x.\n" - ) % async_md.event_code << std::endl; - //clear the async messages - while (dev->recv_async_msg(async_md, 0)){}; + " Async message recv timed out.\n" + ) << std::endl; + return; } - else{ + + switch(async_md.event_code){ + case uhd::async_metadata_t::EVENT_CODE_EOB_ACK: std::cout << boost::format( "success:\n" - " Did not get an async message.\n" + " Got event code eob ack message.\n" ) << std::endl; + break; + + default: + std::cout << boost::format( + "failed:\n" + " Got unexpected event code 0x%x.\n" + ) % async_md.event_code << std::endl; } } @@ -195,7 +203,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //------------------------------------------------------------------ // begin asyc messages test //------------------------------------------------------------------ - test_no_async_message(sdev); + test_ack_async_message(sdev); test_underflow_message(sdev); test_time_error_message(sdev); diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index c9271cc8c..48ff7d509 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -249,8 +249,6 @@ void usrp2_impl::io_init(void){ }; std::memcpy(send_buff->cast(), &data, sizeof(data)); send_buff->commit(sizeof(data)); - //drain the recv buffers (may have junk) - while (data_transport->get_recv_buff(0).get()){}; } //the assumption is that all data transports should be identical diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index ddf147c8d..65066f125 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -70,11 +70,6 @@ usrp2_mboard_impl::usrp2_mboard_impl( _allowed_decim_and_interp_rates.push_back(i); } - //Issue a stop streaming command (in case it was left running). - //Since this command is issued before the networking is setup, - //most if not all junk packets will never make it to the socket. - this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); - //init the rx control registers _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _recv_samps_per_packet); _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1); -- cgit v1.2.3 From b77f9abf8597765b53c28b9ac99faaa3d535803b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 12 Oct 2010 13:16:35 -0700 Subject: proper triggering for interrupts generated on the dsp_clk --- usrp2/top/u2_rev3/u2_core_udp.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index d2bc01d6d..b47e7e311 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -541,10 +541,17 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Interrupt Controller, Slave #8 + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + assign irq= {{8'b0}, {8'b0}, {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), -- cgit v1.2.3 From 2c08c9a7e62b2ad7f75047cc54b0256173f1b674 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 12 Oct 2010 15:24:37 -0700 Subject: usrp2: register overflow, underflow, and pps level for pic also fix minor build issue w/ LDADD --- firmware/microblaze/lib/pic.c | 2 +- firmware/microblaze/usrp2/Makefile.am | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/firmware/microblaze/lib/pic.c b/firmware/microblaze/lib/pic.c index e89d2b755..226da5f85 100644 --- a/firmware/microblaze/lib/pic.c +++ b/firmware/microblaze/lib/pic.c @@ -44,7 +44,7 @@ pic_init(void) // uP is level triggered pic_regs->mask = ~0; // mask all interrupts - pic_regs->edge_enable = PIC_ONETIME_INT; + pic_regs->edge_enable = PIC_ONETIME_INT | PIC_UNDERRUN_INT | PIC_OVERRUN_INT | PIC_PPS_INT; pic_regs->polarity = ~0 & ~PIC_PHY_INT; // rising edge pic_regs->pending = ~0; // clear all pending ints } diff --git a/firmware/microblaze/usrp2/Makefile.am b/firmware/microblaze/usrp2/Makefile.am index 8da013980..ba426b75c 100644 --- a/firmware/microblaze/usrp2/Makefile.am +++ b/firmware/microblaze/usrp2/Makefile.am @@ -22,10 +22,11 @@ AM_CFLAGS = \ AM_LDFLAGS = \ $(COMMON_LFLAGS) \ - libusrp2.a \ -Wl,-defsym -Wl,_TEXT_START_ADDR=0x0050 \ -Wl,-defsym -Wl,_STACK_SIZE=3072 +LDADD = libusrp2.a + ######################################################################## # USRP2 specific library and programs ######################################################################## -- cgit v1.2.3 From c82dffc89991272f103866d64fb29d435f67412a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 12 Oct 2010 23:02:30 -0700 Subject: don't flag an error on eob ack --- usrp2/vrt/vita_tx_chain.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 6cfbdf763..00da4c6e1 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -31,7 +31,7 @@ module vita_tx_chain wire clear_seqnum; wire [31:0] current_seqnum; - assign underrun = error; + assign underrun = error & ~(error_code == 1); assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid -- cgit v1.2.3 From ecea1b5b4a0c7eb6683d15ca15e176f57a5a372a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 12 Oct 2010 23:05:47 -0700 Subject: don't clear out following packets on an eob ack --- usrp2/vrt/vita_tx_control.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index ed470418b..936762212 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -109,7 +109,7 @@ module vita_tx_control else if(eop) if(eob) begin - ibs_state <= IBS_ERROR; // Not really an error + ibs_state <= IBS_ERROR_DONE; // Not really an error error_code <= CODE_EOB_ACK; send_error <= 1; end -- cgit v1.2.3 From ee03f1d4acf5c7d3359c86baba5085660d63ebae Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 12 Oct 2010 23:21:39 -0700 Subject: now handles frames larger than the vita packet (i.e. with padding) --- usrp2/vrt/vita_tx_deframer.v | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 40867cc55..7fb8e3893 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -70,11 +70,13 @@ module vita_tx_deframer localparam VITA_PAYLOAD = 8; localparam VITA_STORE = 9; localparam VITA_TRAILER = 10; + localparam VITA_DUMP = 11; wire [15:0] hdr_len = 2 + has_streamid_reg + has_classid_reg + has_classid_reg + has_secs_reg + has_tics_reg + has_tics_reg + has_trailer_reg; - wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets? + wire vita_eof = (pkt_len==hdr_len); + wire eop = eof | vita_eof; // FIXME would ignoring eof allow larger VITA packets? wire fifo_space; always @(posedge clk) @@ -101,12 +103,14 @@ module vita_tx_deframer end else if((vita_state == VITA_STORE) & fifo_space) - if(eop) - if(has_trailer_reg) + if(vita_eof) + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; + else if(has_trailer_reg) vita_state <= VITA_TRAILER; else - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; - else + vita_state <= VITA_DUMP; + else begin vita_state <= VITA_PAYLOAD; pkt_len <= pkt_len - 1; @@ -172,7 +176,13 @@ module vita_tx_deframer else vector_phase <= vector_phase + 1; VITA_TRAILER : - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; + else + vita_state <= VITA_DUMP; + VITA_DUMP : + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; VITA_STORE : ; default : -- cgit v1.2.3 From 35eda148fc3979c022c58166fa628d5b7dbfd80b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 13 Oct 2010 11:59:15 -0700 Subject: usrp2: increment tx sequence after commit --- host/lib/transport/vrt_packet_handler.hpp | 3 ++- host/lib/usrp/usrp2/io_impl.cpp | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/host/lib/transport/vrt_packet_handler.hpp b/host/lib/transport/vrt_packet_handler.hpp index 939517411..d5f03de0e 100644 --- a/host/lib/transport/vrt_packet_handler.hpp +++ b/host/lib/transport/vrt_packet_handler.hpp @@ -318,7 +318,7 @@ template UHD_INLINE T get_context_code( ){ //load the rest of the if_packet_info in here if_packet_info.num_payload_words32 = (num_samps*chans_per_otw_buff*otw_type.get_sample_size())/sizeof(boost::uint32_t); - if_packet_info.packet_count = state.next_packet_seq++; + if_packet_info.packet_count = state.next_packet_seq; //get send buffers for each channel managed_send_buffs_t send_buffs(buffs.size()/chans_per_otw_buff); @@ -345,6 +345,7 @@ template UHD_INLINE T get_context_code( size_t num_bytes_total = (vrt_header_offset_words32+if_packet_info.num_packet_words32)*sizeof(boost::uint32_t); send_buffs[i]->commit(num_bytes_total); } + state.next_packet_seq++; //increment sequence after commits return num_samps; } diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 48ff7d509..d6f7e8476 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -211,6 +211,7 @@ void usrp2_impl::io_impl::recv_pirate_loop( //print the famous U, and push the metadata into the message queue if (metadata.event_code & underflow_flags) std::cerr << "U" << std::flush; + //else std::cout << "metadata.event_code " << metadata.event_code << std::endl; async_msg_fifo->push_with_pop_on_full(metadata); continue; } -- cgit v1.2.3 From 4dfb7b8cabef3097f822ac52f346cd6021cb35da Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 13 Oct 2010 11:59:35 -0700 Subject: usrp: test async messages app randomly runs tests --- host/examples/test_async_messages.cpp | 84 ++++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 17 deletions(-) diff --git a/host/examples/test_async_messages.cpp b/host/examples/test_async_messages.cpp index fa39bcde6..bdee7a504 100644 --- a/host/examples/test_async_messages.cpp +++ b/host/examples/test_async_messages.cpp @@ -19,8 +19,12 @@ #include #include #include +#include #include +#include +#include #include +#include #include #include @@ -31,7 +35,7 @@ namespace po = boost::program_options; * Send a burst of many samples that will fragment internally. * We expect to get an eob ack async message. */ -void test_ack_async_message(uhd::usrp::single_usrp::sptr sdev){ +bool test_eob_ack_message(uhd::usrp::single_usrp::sptr sdev){ uhd::device::sptr dev = sdev->get_device(); std::cout << "Test eob ack message... " << std::flush; @@ -55,7 +59,7 @@ void test_ack_async_message(uhd::usrp::single_usrp::sptr sdev){ "failed:\n" " Async message recv timed out.\n" ) << std::endl; - return; + return false; } switch(async_md.event_code){ @@ -64,13 +68,14 @@ void test_ack_async_message(uhd::usrp::single_usrp::sptr sdev){ "success:\n" " Got event code eob ack message.\n" ) << std::endl; - break; + return true; default: std::cout << boost::format( "failed:\n" " Got unexpected event code 0x%x.\n" ) % async_md.event_code << std::endl; + return false; } } @@ -79,7 +84,7 @@ void test_ack_async_message(uhd::usrp::single_usrp::sptr sdev){ * Send a start of burst packet with no following end of burst. * We expect to get an underflow(within a burst) async message. */ -void test_underflow_message(uhd::usrp::single_usrp::sptr sdev){ +bool test_underflow_message(uhd::usrp::single_usrp::sptr sdev){ uhd::device::sptr dev = sdev->get_device(); std::cout << "Test underflow message... " << std::flush; @@ -88,18 +93,21 @@ void test_underflow_message(uhd::usrp::single_usrp::sptr sdev){ md.end_of_burst = false; md.has_time_spec = false; - dev->send(NULL, 0, md, + std::vector > buff(1); //minimum 1 sample + + dev->send( + &buff.front(), buff.size(), md, uhd::io_type_t::COMPLEX_FLOAT32, uhd::device::SEND_MODE_FULL_BUFF ); uhd::async_metadata_t async_md; - if (not dev->recv_async_msg(async_md)){ + if (not dev->recv_async_msg(async_md, 1)){ std::cout << boost::format( "failed:\n" " Async message recv timed out.\n" ) << std::endl; - return; + return false; } switch(async_md.event_code){ @@ -108,13 +116,14 @@ void test_underflow_message(uhd::usrp::single_usrp::sptr sdev){ "success:\n" " Got event code underflow message.\n" ) << std::endl; - break; + return true; default: std::cout << boost::format( "failed:\n" " Got unexpected event code 0x%x.\n" ) % async_md.event_code << std::endl; + return false; } } @@ -123,7 +132,7 @@ void test_underflow_message(uhd::usrp::single_usrp::sptr sdev){ * Send a burst packet that occurs at a time in the past. * We expect to get a time error async message. */ -void test_time_error_message(uhd::usrp::single_usrp::sptr sdev){ +bool test_time_error_message(uhd::usrp::single_usrp::sptr sdev){ uhd::device::sptr dev = sdev->get_device(); std::cout << "Test time error message... " << std::flush; @@ -135,7 +144,10 @@ void test_time_error_message(uhd::usrp::single_usrp::sptr sdev){ sdev->set_time_now(uhd::time_spec_t(200.0)); //time at 200s - dev->send(NULL, 0, md, + std::vector > buff(1); //minimum 1 sample + + dev->send( + &buff.front(), buff.size(), md, uhd::io_type_t::COMPLEX_FLOAT32, uhd::device::SEND_MODE_FULL_BUFF ); @@ -146,7 +158,7 @@ void test_time_error_message(uhd::usrp::single_usrp::sptr sdev){ "failed:\n" " Async message recv timed out.\n" ) << std::endl; - return; + return false; } switch(async_md.event_code){ @@ -155,29 +167,38 @@ void test_time_error_message(uhd::usrp::single_usrp::sptr sdev){ "success:\n" " Got event code time error message.\n" ) << std::endl; - break; + return true; default: std::cout << boost::format( "failed:\n" " Got unexpected event code 0x%x.\n" ) % async_md.event_code << std::endl; + return false; } } +void flush_async_md(uhd::usrp::single_usrp::sptr sdev){ + uhd::device::sptr dev = sdev->get_device(); + uhd::async_metadata_t async_md; + while (dev->recv_async_msg(async_md, 1.0)){} +} + int UHD_SAFE_MAIN(int argc, char *argv[]){ uhd::set_thread_priority_safe(); //variables to be set by po std::string args; double rate; + size_t ntests; //setup the program options po::options_description desc("Allowed options"); desc.add_options() ("help", "help message") - ("args", po::value(&args)->default_value(""), "single uhd device address args") - ("rate", po::value(&rate)->default_value(1.5e6), "rate of outgoing samples") + ("args", po::value(&args)->default_value(""), "single uhd device address args") + ("rate", po::value(&rate)->default_value(1.5e6), "rate of outgoing samples") + ("ntests", po::value(&ntests)->default_value(10), "number of tests to run") ; po::variables_map vm; po::store(po::parse_command_line(argc, argv, desc), vm); @@ -203,9 +224,38 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //------------------------------------------------------------------ // begin asyc messages test //------------------------------------------------------------------ - test_ack_async_message(sdev); - test_underflow_message(sdev); - test_time_error_message(sdev); + static const uhd::dict > + tests = boost::assign::map_list_of + ("Test EOB ACK ", &test_eob_ack_message) + ("Test Underflow ", &test_underflow_message) + ("Test Time Error", &test_time_error_message) + ; + + //init result counts + uhd::dict failures, successes; + BOOST_FOREACH(const std::string &key, tests.keys()){ + failures[key] = 0; + successes[key] = 0; + } + + //run the tests, pick at random + for (size_t n = 0; n < ntests; n++){ + std::string key = tests.keys()[std::rand() % tests.size()]; + bool pass = tests[key](sdev); + flush_async_md(sdev); + + //store result + if (pass) successes[key]++; + else failures[key]++; + } + + //print the result summary + std::cout << std::endl << "Summary:" << std::endl << std::endl; + BOOST_FOREACH(const std::string &key, tests.keys()){ + std::cout << boost::format( + "%s -> %3d successes, %3d failures" + ) % key % successes[key] % failures[key] << std::endl; + } //finished std::cout << std::endl << "Done!" << std::endl << std::endl; -- cgit v1.2.3 From c6042a0b317a6f74d2b74b259f14431f5c8246d4 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 13 Oct 2010 14:28:52 -0700 Subject: usrp2: added docs on flow control ricer args and using usrp2 with a switch implemented flow control param hints in the mboard impl --- host/docs/transport.rst | 11 +++++++++++ host/docs/usrp2.rst | 15 +++++++-------- host/lib/usrp/usrp2/mboard_impl.cpp | 22 ++++++++++++++-------- host/lib/usrp/usrp2/usrp2_impl.cpp | 8 +++++--- host/lib/usrp/usrp2/usrp2_impl.hpp | 7 +++++-- host/lib/usrp/usrp2/usrp2_regs.hpp | 8 ++++---- 6 files changed, 46 insertions(+), 25 deletions(-) diff --git a/host/docs/transport.rst b/host/docs/transport.rst index 432db4bb5..2f730f8e4 100644 --- a/host/docs/transport.rst +++ b/host/docs/transport.rst @@ -39,6 +39,17 @@ The following parameters can be used to alter the transport's default behavior: **Note:** num_send_frames and concurrency_hint will not have an effect as the asynchronous send implementation is currently disabled. +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Flow control parameters +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The host-based flow control expects periodic update packets from the device. +These update packets inform the host of the last packet consumed by the device, +which allows the host to determine throttling conditions for the transmission of packets. +The following mechanisms affect the transmission of periodic update packets: + +* **ups_per_fifo:** The number of update packets for each FIFO's worth of bytes sent into the device +* **ups_per_sec:** The number of update packets per second + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Resize socket buffers ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/host/docs/usrp2.rst b/host/docs/usrp2.rst index 1ebab388a..8fa666a49 100644 --- a/host/docs/usrp2.rst +++ b/host/docs/usrp2.rst @@ -39,12 +39,10 @@ Use the card burner tool (windows) ------------------------------------------------------------------------ Setup networking ------------------------------------------------------------------------ -The USRP2 only supports gigabit ethernet, and -will not work with a 10/100 Mbps interface. -Because the USRP2 uses gigabit ethernet pause frames for flow control, -you cannot use multiple USRP2s with a switch or a hub. -It is recommended that each USRP2 be plugged directly into its own -dedicated gigabit ethernet interface on the host computer. +The USRP2 only supports gigabit ethernet, +and will not work with a 10/100 Mbps interface. +However, a 10/100 Mbps interface can be connected indirectly +to a USRP2 through a gigabit ethernet switch. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Setup the host interface @@ -63,8 +61,9 @@ It is recommended that you change or disable your firewall settings. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Multiple device configuration ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -As described above, you will need one ethernet interface per USRP2. -Each ethernet interface should have its own subnet, +For maximum throughput, one ethernet interface per USRP2 is recommended, +although multiple devices may be connected via a gigabit ethernet switch. +In any case, each ethernet interface should have its own subnet, and the corresponding USRP2 device should be assigned an address in that subnet. Example: diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 65066f125..5210eee94 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -39,7 +39,8 @@ usrp2_mboard_impl::usrp2_mboard_impl( size_t index, transport::udp_simple::sptr ctrl_transport, size_t recv_samps_per_packet, - size_t send_bytes_per_packet + size_t send_bytes_per_packet, + const device_addr_t &flow_control_hints ): _index(index), _recv_samps_per_packet(recv_samps_per_packet) @@ -89,11 +90,16 @@ usrp2_mboard_impl::usrp2_mboard_impl( _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1); //sid 1 (different from rx) _iface->poke32(U2_REG_TX_CTRL_POLICY, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); - const size_t cycles_per_ack = size_t(_clock_ctrl->get_master_clock_rate()/100); //100 aps - _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_ACK, U2_FLAG_TX_CTRL_ACK_ENB | cycles_per_ack); - static const double sram_frac = 1.0/8.0; //fraction of sram to fill before ack - const size_t packets_per_ack = size_t(usrp2_impl::sram_bytes*sram_frac/send_bytes_per_packet); - _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_ACK, U2_FLAG_TX_CTRL_ACK_ENB | packets_per_ack); + + //setting the cycles per update + const double ups_per_sec = flow_control_hints.cast("ups_per_sec", 100); + const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec); + _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up); + + //setting the packets per update + const double ups_per_fifo = flow_control_hints.cast("ups_per_fifo", 8); + const size_t packets_per_up = size_t(usrp2_impl::sram_bytes/ups_per_fifo/send_bytes_per_packet); + _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | packets_per_up); //init the ddc init_ddc_config(); @@ -116,8 +122,8 @@ usrp2_mboard_impl::usrp2_mboard_impl( } usrp2_mboard_impl::~usrp2_mboard_impl(void){ - _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_ACK, 0); - _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_ACK, 0); + _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, 0); + _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_UP, 0); } /*********************************************************************** diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index 1d9f25019..e271f839c 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -138,7 +138,7 @@ static device::sptr usrp2_make(const device_addr_t &device_addr){ //create the usrp2 implementation guts return device::sptr( - new usrp2_impl(ctrl_transports, data_transports) + new usrp2_impl(ctrl_transports, data_transports, device_addr) ); } @@ -151,7 +151,8 @@ UHD_STATIC_BLOCK(register_usrp2_device){ **********************************************************************/ usrp2_impl::usrp2_impl( std::vector ctrl_transports, - std::vector data_transports + std::vector data_transports, + const device_addr_t &flow_control_hints ): _data_transports(data_transports) { @@ -172,7 +173,8 @@ usrp2_impl::usrp2_impl( _mboards.push_back(usrp2_mboard_impl::sptr(new usrp2_mboard_impl( i, ctrl_transports[i], this->get_max_recv_samps_per_packet(), - _data_transports[i]->get_send_frame_size() + _data_transports[i]->get_send_frame_size(), + flow_control_hints ))); //use an empty name when there is only one mboard std::string name = (ctrl_transports.size() > 1)? boost::lexical_cast(i) : ""; diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index 2077b0a50..3aa6e9cd5 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -85,7 +85,8 @@ public: size_t index, uhd::transport::udp_simple::sptr, size_t recv_samps_per_packet, - size_t send_bytes_per_packet + size_t send_bytes_per_packet, + const uhd::device_addr_t &flow_control_hints ); ~usrp2_mboard_impl(void); @@ -178,10 +179,12 @@ public: * Create a new usrp2 impl base. * \param ctrl_transports the udp transports for control * \param data_transports the udp transports for data + * \param flow_control_hints optional flow control params */ usrp2_impl( std::vector ctrl_transports, - std::vector data_transports + std::vector data_transports, + const uhd::device_addr_t &flow_control_hints ); ~usrp2_impl(void); diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index bdd5194f9..c3a4d22de 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -193,14 +193,14 @@ #define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) #define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) #define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3) -#define U2_REG_TX_CTRL_CYCLES_PER_ACK _SR_ADDR(SR_TX_CTRL + 4) -#define U2_REG_TX_CTRL_PACKETS_PER_ACK _SR_ADDR(SR_TX_CTRL + 5) +#define U2_REG_TX_CTRL_CYCLES_PER_UP _SR_ADDR(SR_TX_CTRL + 4) +#define U2_REG_TX_CTRL_PACKETS_PER_UP _SR_ADDR(SR_TX_CTRL + 5) #define U2_FLAG_TX_CTRL_POLICY_WAIT (0x1 << 0) #define U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET (0x1 << 1) #define U2_FLAG_TX_CTRL_POLICY_NEXT_BURST (0x1 << 2) -//enable flag for registers: cycles and packets per ack -#define U2_FLAG_TX_CTRL_ACK_ENB (1ul << 31) +//enable flag for registers: cycles and packets per update packet +#define U2_FLAG_TX_CTRL_UP_ENB (1ul << 31) #endif /* INCLUDED_USRP2_REGS_HPP */ -- cgit v1.2.3 From c25fd486f82d646cf8a08582c6e7105fd3c58c45 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 13 Oct 2010 15:01:45 -0700 Subject: udp: fix to use concurrency hint, default hint is zero when no async enabled --- host/lib/transport/udp_zero_copy_asio.cpp | 31 ++++++++++++++++++++----------- host/lib/usrp/usrp2/io_impl.cpp | 1 + 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/host/lib/transport/udp_zero_copy_asio.cpp b/host/lib/transport/udp_zero_copy_asio.cpp index d84aeefdd..938ae4473 100644 --- a/host/lib/transport/udp_zero_copy_asio.cpp +++ b/host/lib/transport/udp_zero_copy_asio.cpp @@ -59,16 +59,23 @@ static const size_t DEFAULT_NUM_RECV_FRAMES = 32; #else static const size_t DEFAULT_NUM_RECV_FRAMES = MIN_RECV_SOCK_BUFF_SIZE/udp_simple::mtu; #endif + //The non-async send only ever requires a single frame //because the buffer will be committed before a new get. #ifdef USE_ASIO_ASYNC_SEND static const size_t DEFAULT_NUM_SEND_FRAMES = 32; #else -static const size_t DEFAULT_NUM_SEND_FRAMES = MIN_SEND_SOCK_BUFF_SIZE/udp_simple::mtu;; +static const size_t DEFAULT_NUM_SEND_FRAMES = MIN_SEND_SOCK_BUFF_SIZE/udp_simple::mtu; #endif -//a single concurrent thread for io_service seems to be the fastest +//The number of service threads to spawn for async ASIO: +//A single concurrent thread for io_service seems to be the fastest. +//Threads are disabled when no async implementations are enabled. +#if defined(USE_ASIO_ASYNC_RECV) || defined(USE_ASIO_ASYNC_SEND) static const size_t CONCURRENCY_HINT = 1; +#else +static const size_t CONCURRENCY_HINT = 0; +#endif /*********************************************************************** * Zero Copy UDP implementation with ASIO: @@ -86,11 +93,12 @@ public: const std::string &port, const device_addr_t &hints ): - _io_service(hints.cast("concurrency_hint", CONCURRENCY_HINT)), _recv_frame_size(size_t(hints.cast("recv_frame_size", udp_simple::mtu))), _num_recv_frames(size_t(hints.cast("num_recv_frames", DEFAULT_NUM_RECV_FRAMES))), _send_frame_size(size_t(hints.cast("send_frame_size", udp_simple::mtu))), - _num_send_frames(size_t(hints.cast("num_send_frames", DEFAULT_NUM_SEND_FRAMES))) + _num_send_frames(size_t(hints.cast("num_send_frames", DEFAULT_NUM_SEND_FRAMES))), + _concurrency_hint(hints.cast("concurrency_hint", CONCURRENCY_HINT)), + _io_service(_concurrency_hint) { //std::cout << boost::format("Creating udp transport for %s %s") % addr % port << std::endl; @@ -129,7 +137,7 @@ public: //spawn the service threads that will run the io service _work = new asio::io_service::work(_io_service); //new work to delete later - for (size_t i = 0; i < CONCURRENCY_HINT; i++) _thread_group.create_thread( + for (size_t i = 0; i < _concurrency_hint; i++) _thread_group.create_thread( boost::bind(&udp_zero_copy_asio_impl::service, this) ); } @@ -292,12 +300,6 @@ public: size_t get_send_frame_size(void) const {return _send_frame_size;} private: - //asio guts -> socket and service - asio::ip::udp::socket *_socket; - asio::io_service _io_service; - asio::io_service::work *_work; - int _sock_fd; - //memory management -> buffers and fifos boost::thread_group _thread_group; boost::shared_array _send_buffer, _recv_buffer; @@ -305,6 +307,13 @@ private: pending_buffs_type::sptr _pending_recv_buffs, _pending_send_buffs; const size_t _recv_frame_size, _num_recv_frames; const size_t _send_frame_size, _num_send_frames; + + //asio guts -> socket and service + size_t _concurrency_hint; + asio::io_service _io_service; + asio::ip::udp::socket *_socket; + asio::io_service::work *_work; + int _sock_fd; }; /*********************************************************************** diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index d6f7e8476..25fd1c484 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -69,6 +69,7 @@ public: * \return false on timeout */ UHD_INLINE bool check_fc_condition(seq_type seq, double timeout){ + boost::this_thread::disable_interruption di; //disable because the wait can throw boost::unique_lock lock(_fc_mutex); _last_seq_out = seq; return _fc_cond.timed_wait( -- cgit v1.2.3 From 376e22ca3bf25c8d6bb53cd987b245e5b79860f9 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 13 Oct 2010 18:38:54 -0700 Subject: usrp2: handle destination port unreachable icmp in fw (kills streaming and update packets) --- firmware/microblaze/lib/net_common.c | 11 ++++++++++- firmware/microblaze/usrp2/memory_map.h | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/firmware/microblaze/lib/net_common.c b/firmware/microblaze/lib/net_common.c index 6c9509c92..0efb26639 100644 --- a/firmware/microblaze/lib/net_common.c +++ b/firmware/microblaze/lib/net_common.c @@ -291,8 +291,17 @@ handle_icmp_packet(struct ip_addr src, struct ip_addr dst, { switch (icmp->type){ case ICMP_DUR: // Destinatino Unreachable - //stop_streaming(); //FIXME if (icmp->code == ICMP_DUR_PORT){ // port unreachable + //handle destination port unreachable (the host ctrl+c'd the app): + + //end async update packets per second + sr_tx_ctrl->cyc_per_up = 0; + + //the end continuous streaming command + sr_rx_ctrl->cmd = (1 << 31) | 1; //one sample, asap + sr_rx_ctrl->time_secs = 0; + sr_rx_ctrl->time_ticks = 0; //latch the command + //struct udp_hdr *udp = (struct udp_hdr *)((char *)icmp + 28); //printf("icmp port unr %d\n", udp->dest); putchar('i'); diff --git a/firmware/microblaze/usrp2/memory_map.h b/firmware/microblaze/usrp2/memory_map.h index 41a2820bc..e7f41bc8d 100644 --- a/firmware/microblaze/usrp2/memory_map.h +++ b/firmware/microblaze/usrp2/memory_map.h @@ -463,6 +463,9 @@ typedef struct { typedef struct { volatile uint32_t num_chan; volatile uint32_t clear_state; // clears out state machine, fifos, + volatile uint32_t report_sid; + volatile uint32_t policy; + volatile uint32_t cyc_per_up; } sr_tx_ctrl_t; #define sr_tx_ctrl ((sr_tx_ctrl_t *) _SR_ADDR(SR_TX_CTRL)) -- cgit v1.2.3 From 4582a2deb385c0a4849f5d20c44a5469779bcbb2 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 14 Oct 2010 11:51:48 -0700 Subject: usrp2: move udp port initialization into mboard impl so its done before async registers are setup --- host/lib/usrp/usrp2/io_impl.cpp | 10 ---------- host/lib/usrp/usrp2/mboard_impl.cpp | 16 ++++++++++++++-- host/lib/usrp/usrp2/usrp2_impl.cpp | 3 +-- host/lib/usrp/usrp2/usrp2_impl.hpp | 2 +- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 25fd1c484..8314cf9ae 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -242,16 +242,6 @@ void usrp2_impl::io_impl::recv_pirate_loop( * Helper Functions **********************************************************************/ void usrp2_impl::io_init(void){ - //send a small data packet so the usrp2 knows the udp source port - BOOST_FOREACH(zero_copy_if::sptr data_transport, _data_transports){ - managed_send_buffer::sptr send_buff = data_transport->get_send_buff(); - static const boost::uint32_t data[2] = { - uhd::htonx(boost::uint32_t(0 /* don't care seq num */)), - uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER)) - }; - std::memcpy(send_buff->cast(), &data, sizeof(data)); - send_buff->commit(sizeof(data)); - } //the assumption is that all data transports should be identical const size_t num_recv_frames = _data_transports.front()->get_num_recv_frames(); diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 5210eee94..8f3ae5c1b 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -38,13 +39,24 @@ using namespace uhd::usrp; usrp2_mboard_impl::usrp2_mboard_impl( size_t index, transport::udp_simple::sptr ctrl_transport, + transport::zero_copy_if::sptr data_transport, size_t recv_samps_per_packet, - size_t send_bytes_per_packet, const device_addr_t &flow_control_hints ): _index(index), _recv_samps_per_packet(recv_samps_per_packet) { + //Send a small data packet so the usrp2 knows the udp source port. + //This setup must happen before further initialization occurs + //or the async update packets will cause ICMP destination unreachable. + transport::managed_send_buffer::sptr send_buff = data_transport->get_send_buff(); + static const boost::uint32_t data[2] = { + uhd::htonx(boost::uint32_t(0 /* don't care seq num */)), + uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER)) + }; + std::memcpy(send_buff->cast(), &data, sizeof(data)); + send_buff->commit(sizeof(data)); + //make a new interface for usrp2 stuff _iface = usrp2_iface::make(ctrl_transport); @@ -98,7 +110,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( //setting the packets per update const double ups_per_fifo = flow_control_hints.cast("ups_per_fifo", 8); - const size_t packets_per_up = size_t(usrp2_impl::sram_bytes/ups_per_fifo/send_bytes_per_packet); + const size_t packets_per_up = size_t(usrp2_impl::sram_bytes/ups_per_fifo/data_transport->get_send_frame_size()); _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | packets_per_up); //init the ddc diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index e271f839c..afc69f703 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -171,9 +171,8 @@ usrp2_impl::usrp2_impl( //create a new mboard handler for each control transport for(size_t i = 0; i < ctrl_transports.size(); i++){ _mboards.push_back(usrp2_mboard_impl::sptr(new usrp2_mboard_impl( - i, ctrl_transports[i], + i, ctrl_transports[i], data_transports[i], this->get_max_recv_samps_per_packet(), - _data_transports[i]->get_send_frame_size(), flow_control_hints ))); //use an empty name when there is only one mboard diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index 3aa6e9cd5..2531bd6cb 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -84,8 +84,8 @@ public: usrp2_mboard_impl( size_t index, uhd::transport::udp_simple::sptr, + uhd::transport::zero_copy_if::sptr, size_t recv_samps_per_packet, - size_t send_bytes_per_packet, const uhd::device_addr_t &flow_control_hints ); ~usrp2_mboard_impl(void); -- cgit v1.2.3 From 71e1763332141603e9edba097fd19b00e9a76ab8 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 14 Oct 2010 16:51:47 -0700 Subject: uhd: removed 1 sample buffers in test async messages made a hack in the vrt handler to bump 0 sample requests up to 1 sample (until the hardware supports it) --- host/examples/test_async_messages.cpp | 8 ++------ host/lib/transport/vrt_packet_handler.hpp | 13 +++++++++++-- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/host/examples/test_async_messages.cpp b/host/examples/test_async_messages.cpp index bdee7a504..61db7ec04 100644 --- a/host/examples/test_async_messages.cpp +++ b/host/examples/test_async_messages.cpp @@ -93,10 +93,8 @@ bool test_underflow_message(uhd::usrp::single_usrp::sptr sdev){ md.end_of_burst = false; md.has_time_spec = false; - std::vector > buff(1); //minimum 1 sample - dev->send( - &buff.front(), buff.size(), md, + NULL, 0, md, uhd::io_type_t::COMPLEX_FLOAT32, uhd::device::SEND_MODE_FULL_BUFF ); @@ -144,10 +142,8 @@ bool test_time_error_message(uhd::usrp::single_usrp::sptr sdev){ sdev->set_time_now(uhd::time_spec_t(200.0)); //time at 200s - std::vector > buff(1); //minimum 1 sample - dev->send( - &buff.front(), buff.size(), md, + NULL, 0, md, uhd::io_type_t::COMPLEX_FLOAT32, uhd::device::SEND_MODE_FULL_BUFF ); diff --git a/host/lib/transport/vrt_packet_handler.hpp b/host/lib/transport/vrt_packet_handler.hpp index d5f03de0e..278bcfeaa 100644 --- a/host/lib/transport/vrt_packet_handler.hpp +++ b/host/lib/transport/vrt_packet_handler.hpp @@ -388,10 +388,19 @@ template UHD_INLINE T get_context_code( if_packet_info.sob = metadata.start_of_burst; if_packet_info.eob = metadata.end_of_burst; + //TODO remove this code when sample counts of zero are supported by hardware + std::vector buffs_(buffs); + size_t total_num_samps_(total_num_samps); + if (total_num_samps == 0){ + static const boost::uint64_t zeros = 0; //max size of a host sample + buffs_ = std::vector(buffs.size(), &zeros); + total_num_samps_ = 1; + } + return _send1( state, - buffs, 0, - std::min(total_num_samps, max_samples_per_packet), + buffs_, 0, + std::min(total_num_samps_, max_samples_per_packet), if_packet_info, io_type, otw_type, vrt_packer, -- cgit v1.2.3 From 972fae172ae30323ed57795ca5a4aad790bac7f9 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 15 Oct 2010 14:37:26 -0700 Subject: usrp2: temp fix to send dummy packets and flush so FPGA vita machine are in known state --- host/lib/usrp/usrp2/io_impl.cpp | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 8314cf9ae..00061ae47 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -241,6 +241,8 @@ void usrp2_impl::io_impl::recv_pirate_loop( /*********************************************************************** * Helper Functions **********************************************************************/ +#include //TODO remove when hack below is fixed + void usrp2_impl::io_init(void){ //the assumption is that all data transports should be identical @@ -250,6 +252,30 @@ void usrp2_impl::io_init(void){ //create new io impl _io_impl = UHD_PIMPL_MAKE(io_impl, (num_recv_frames, send_frame_size, _data_transports.size())); + //TODO temporary fix for weird power up state, remove when FPGA fixed + { + //send an initial packet to all transports + tx_metadata_t md; md.end_of_burst = true; + this->send( + std::vector(_data_transports.size(), NULL), 0, md, + io_type_t::COMPLEX_FLOAT32, device::SEND_MODE_ONE_PACKET, 0 + ); + + //issue a stream command to each motherboard + BOOST_FOREACH(usrp2_mboard_impl::sptr mboard, _mboards){ + (*mboard)[MBOARD_PROP_STREAM_CMD] = stream_cmd_t(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + (*mboard)[MBOARD_PROP_STREAM_CMD] = stream_cmd_t(stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); + } + + //wait + boost::this_thread::sleep(boost::posix_time::milliseconds(100)); + + //flush all transport receive queues (no timeout) + BOOST_FOREACH(zero_copy_if::sptr xport, _data_transports){ + while(xport->get_recv_buff(0).get() != NULL){}; + } + } + //create a new pirate thread for each zc if (yarr!!) for (size_t i = 0; i < _data_transports.size(); i++){ _io_impl->recv_pirate_crew.create_thread(boost::bind( -- cgit v1.2.3 From a2abd6bc615cb63e585e7fafa9ea8491bb25f5b5 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 15 Oct 2010 17:05:45 -0700 Subject: usrp2: dont need to start streaming for this hack --- host/lib/usrp/usrp2/io_impl.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 00061ae47..95a627266 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -263,7 +263,6 @@ void usrp2_impl::io_init(void){ //issue a stream command to each motherboard BOOST_FOREACH(usrp2_mboard_impl::sptr mboard, _mboards){ - (*mboard)[MBOARD_PROP_STREAM_CMD] = stream_cmd_t(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); (*mboard)[MBOARD_PROP_STREAM_CMD] = stream_cmd_t(stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); } -- cgit v1.2.3 From c32f4fbc8973633280249399d5d5a937ef0f1f3e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 21 Oct 2010 13:08:23 -0700 Subject: should combine the randomizer with flow_control --- usrp2/extramfifo/Makefile.srcs | 1 + usrp2/extramfifo/ext_fifo.v | 125 ++++++++++++++++++++++++----------- usrp2/extramfifo/ext_fifo_tb.sav | 30 +++++++++ usrp2/extramfifo/ext_fifo_tb.v | 103 ++++++++++++++++++++--------- usrp2/extramfifo/refill_randomizer.v | 66 ++++++++++++++++++ 5 files changed, 254 insertions(+), 71 deletions(-) create mode 100644 usrp2/extramfifo/ext_fifo_tb.sav create mode 100644 usrp2/extramfifo/refill_randomizer.v diff --git a/usrp2/extramfifo/Makefile.srcs b/usrp2/extramfifo/Makefile.srcs index 7cd49f4f6..b255ef916 100644 --- a/usrp2/extramfifo/Makefile.srcs +++ b/usrp2/extramfifo/Makefile.srcs @@ -13,4 +13,5 @@ icon.v \ icon.xco \ ila.v \ ila.xco \ +refill_randomizer.v \ )) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 2af59a75d..6888617a7 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -18,7 +18,7 @@ //`define NO_EXT_FIFO module ext_fifo - #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) + #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) ( input int_clk, input ext_clk, @@ -44,34 +44,29 @@ module ext_fifo wire [EXT_WIDTH-1:0] write_data; wire [EXT_WIDTH-1:0] read_data; - wire full1, empty1; - wire almost_full2, full2, empty2; + wire full1, empty1; + wire almost_full2, full2, empty2; wire [INT_WIDTH-1:0] data_to_fifo; wire [INT_WIDTH-1:0] data_from_fifo; wire [FIFO_DEPTH-1:0] capacity; - + wire space_avail; + wire data_avail; + + // These next 2 lines here purely because ICARUS is crap at handling generate statements. + // Empirically this has been determined to make simulations work. + wire read_input_fifo = space_avail & ~empty1; + wire write_output_fifo = data_avail; - // FIFO buffers data from UDP engine into external FIFO clock domain. - fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( - .rst(rst), - .wr_clk(int_clk), - .rd_clk(ext_clk), - .din(datain), // Bus [35 : 0] - .wr_en(src_rdy_i), - .rd_en(space_avail&~empty1), - .dout(write_data), // Bus [17 : 0] - .full(full1), - .empty(empty1)); - - assign dst_rdy_o = ~full1; + assign src_rdy_o = ~empty2; + assign dst_rdy_o = ~full1; `ifdef NO_EXT_FIFO - assign space_avail = ~full2; - assign data_avail = ~empty1; - assign read_data = write_data; + assign space_avail = ~full2; + assign data_avail = ~empty1; + assign read_data = write_data; `else - // External FIFO running at ext clock rate and 18 bit width. + // External FIFO running at ext clock rate and 18 or 36 bit width. nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH)) nobl_fifo_i1 ( @@ -90,27 +85,80 @@ module ext_fifo .write_strobe(~empty1 ), .space_avail(space_avail), .read_data(read_data), - .read_strobe(~almost_full2), + .read_strobe(~almost_full2_spread), .data_avail(data_avail), .capacity(capacity) ); `endif // !`ifdef NO_EXT_FIFO + + + generate + if (EXT_WIDTH == 18 && INT_WIDTH == 36) begin: fifo_g1 + // FIFO buffers data from UDP engine into external FIFO clock domain. + fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( + .rst(rst), + .wr_clk(int_clk), + .rd_clk(ext_clk), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(read_input_fifo), + .dout(write_data), // Bus [17 : 0] + .full(full1), + .empty(empty1)); + + + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. + fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [17 : 0] + .wr_en(write_output_fifo), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .prog_full(almost_full2), + .empty(empty2)); + end // block: fifo_g1 + else if (EXT_WIDTH == 36 && INT_WIDTH == 36) begin: fifo_g1 + // FIFO buffers data from UDP engine into external FIFO clock domain. + fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i1 ( + .rst(rst), + .wr_clk(int_clk), + .rd_clk(ext_clk), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(read_input_fifo), + .dout(write_data), // Bus [35 : 0] + .full(full1), + .empty(empty1)); + + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. + fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [35 : 0] + .wr_en(write_output_fifo), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .empty(empty2), + .prog_full(almost_full2)); + + end + endgenerate - - // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. - fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( - .rst(rst), - .wr_clk(ext_clk), - .rd_clk(int_clk), - .din(read_data), // Bus [17 : 0] - .wr_en(data_avail), - .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] - .full(full2), - .prog_full(almost_full2), - .empty(empty2)); - assign src_rdy_o = ~empty2; + refill_randomizer #(.BITS(7)) + refill_randomizer_i1 ( + .clk(ext_clk), + .rst(rst), + .full_in(almost_full2), + .full_out(almost_full2_spread) + ); + + always @ (posedge int_clk) debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; @@ -118,6 +166,7 @@ module ext_fifo debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; always@ (posedge ext_clk) -// debug2[31:0] <= {write_data[15:0],read_data[15:0]}; - debug2[31:0] <= 0; + // debug2[31:0] <= {write_data[15:0],read_data[15:0]}; + debug2[31:0] <= 0; + endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.sav b/usrp2/extramfifo/ext_fifo_tb.sav new file mode 100644 index 000000000..a54b40fc5 --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.sav @@ -0,0 +1,30 @@ +[timestart] 0 +[size] 1523 832 +[pos] -1 -1 +*-15.000000 66300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] ext_fifo_tb. +[treeopen] ext_fifo_tb.ext_fifo_i1. +[treeopen] ext_fifo_tb.ext_fifo_i1.nobl_fifo_i1. +@28 +ext_fifo_tb.ext_fifo_i1.src_rdy_i +ext_fifo_tb.ext_fifo_i1.dst_rdy_o +@22 +ext_fifo_tb.ext_fifo_i1.datain[35:0] +@28 +ext_fifo_tb.ext_fifo_i1.src_rdy_o +ext_fifo_tb.ext_fifo_i1.dst_rdy_i +@22 +ext_fifo_tb.ext_fifo_i1.dataout[35:0] +ext_fifo_tb.ext_fifo_i1.RAM_A[17:0] +@28 +ext_fifo_tb.ext_fifo_i1.RAM_WEn +ext_fifo_tb.ext_fifo_i1.RAM_CE1n +@22 +ext_fifo_tb.ext_fifo_i1.RAM_D_pi[35:0] +ext_fifo_tb.ext_fifo_i1.RAM_D_po[35:0] +ext_fifo_tb.ext_fifo_i1.write_data[35:0] +@28 +ext_fifo_tb.ext_fifo_i1.full1 +ext_fifo_tb.ext_fifo_i1.empty1 +@29 +ext_fifo_tb.ext_fifo_i1.space_avail diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index 0eda89769..395ad2884 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -1,18 +1,31 @@ `timescale 1ns / 1ps -`define INT_WIDTH 36 -`define EXT_WIDTH 18 -`define RAM_DEPTH 19 -`define FIFO_DEPTH 8 -`define DUMP_VCD_FULL - -module ext_fifo_tb(); +`define USRP2 +//`define USRP2PLUS +`ifdef USRP2 + `define INT_WIDTH 36 + `define EXT_WIDTH 18 + `define RAM_DEPTH 19 + `define FIFO_DEPTH 8 + `define DUMP_VCD_FULL + `define INT_CLK_PERIOD 5 + `define EXT_CLK_PERIOD 4 +`elsif USRP2PLUS + `define INT_WIDTH 36 + `define EXT_WIDTH 36 + `define RAM_DEPTH 18 + `define FIFO_DEPTH 8 + `define DUMP_VCD_FULL + `define INT_CLK_PERIOD 5 + `define EXT_CLK_PERIOD 5 +`endif // `ifdef USRP2 + +module ext_fifo_tb(); + reg int_clk; reg ext_clk; reg rst; - - wire [`EXT_WIDTH-1:0] RAM_D_pi; wire [`EXT_WIDTH-1:0] RAM_D_po; @@ -33,7 +46,6 @@ module ext_fifo_tb(); reg dst_rdy_i; integer ether_frame; - // Clocks // Int clock is 100MHz // Ext clock is 125MHz @@ -47,10 +59,10 @@ module ext_fifo_tb(); end always - #5 int_clk <= ~int_clk; + #(`INT_CLK_PERIOD/2) int_clk <= ~int_clk; always - #4 ext_clk <= ~ext_clk; + #(`EXT_CLK_PERIOD/2) ext_clk <= ~ext_clk; initial begin @@ -270,7 +282,7 @@ module ext_fifo_tb(); // generate - for (i=0;i<18;i=i+1) + for (i=0;i<`EXT_WIDTH;i=i+1) begin : gen_RAM_D_IO IOBUF #( @@ -309,28 +321,53 @@ module ext_fifo_tb(); assign #2 RAM_A_ext = RAM_A; - - idt71v65603s150 idt71v65603s150_i1 - ( - .A(RAM_A_ext[17:0]), - .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) - .bw1_(1'b0), - .bw2_(1'b0), - .bw3_(1'b1), - .bw4_(1'b1), // byte write enables (low) - .ce1_(RAM_CE1n_ext), - .ce2(1'b1), - .ce2_(1'b0), // chip enables - .cen_(RAM_CENn_ext), // clock enable (low) - .clk(ext_clk), // clock - .IO({RAM_D[16:9],RAM_D[7:0]}), - .IOP({RAM_D[17],RAM_D[8]}), // data bus - .lbo_(1'b0), // linear burst order (low) - .oe_(RAM_OEn_ext), // output enable (low) - .r_w_(RAM_WEn_ext) - ); // read (high) / write (low) + generate + if (`EXT_WIDTH==18) begin: ram_tb_g1 + idt71v65603s150 idt71v65603s150_i1 + ( + .A(RAM_A_ext[17:0]), + .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) + .bw1_(1'b0), + .bw2_(1'b0), + .bw3_(1'b1), + .bw4_(1'b1), // byte write enables (low) + .ce1_(RAM_CE1n_ext), + .ce2(1'b1), + .ce2_(1'b0), // chip enables + .cen_(RAM_CENn_ext), // clock enable (low) + .clk(ext_clk), // clock + .IO({RAM_D[16:9],RAM_D[7:0]}), + .IOP({RAM_D[17],RAM_D[8]}), // data bus + .lbo_(1'b0), // linear burst order (low) + .oe_(RAM_OEn_ext), // output enable (low) + .r_w_(RAM_WEn_ext) + ); // read (high) / write (low) + end // block: ram_tb_g1 + else if (`EXT_WIDTH==36) begin: ram_tb_g1 + idt71v65603s150 idt71v65603s150_i1 + ( + .A(RAM_A_ext[17:0]), + .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) + .bw1_(1'b0), + .bw2_(1'b0), + .bw3_(1'b0), + .bw4_(1'b0), // byte write enables (low) + .ce1_(RAM_CE1n_ext), + .ce2(1'b1), + .ce2_(1'b0), // chip enables + .cen_(RAM_CENn_ext), // clock enable (low) + .clk(ext_clk), // clock + .IO(RAM_D[31:0]), + .IOP(RAM_D[35:32]), // data bus + .lbo_(1'b0), // linear burst order (low) + .oe_(RAM_OEn_ext), // output enable (low) + .r_w_(RAM_WEn_ext) + ); // read (high) / write (low) + end // block: ram_tb_g1 + endgenerate + /* -----\/----- EXCLUDED -----\/----- diff --git a/usrp2/extramfifo/refill_randomizer.v b/usrp2/extramfifo/refill_randomizer.v new file mode 100644 index 000000000..0b30f4049 --- /dev/null +++ b/usrp2/extramfifo/refill_randomizer.v @@ -0,0 +1,66 @@ +// +// EMI mitigation. +// Process FULL flag from FIFO so that de-assertion +// (FIFO now not FULL) is delayed by a pseudo random +// value, but assertion is passed straight through. +// + + +module refill_randomizer + #(parameter BITS=7) + ( + input clk, + input rst, + input full_in, + output full_out + ); + + wire feedback; + reg full_last; + wire full_deasserts; + reg [6:0] shift_reg; + reg [6:0] count; + reg delayed_fall; + + + always @(posedge clk) + full_last <= full_in; + + assign full_deasserts = full_last & ~full_in; + + // 7 bit LFSR + always @(posedge clk) + if (rst) + shift_reg <= 7'b1; + else + if (full_deasserts) + shift_reg <= {shift_reg[5:0],feedback}; + + assign feedback = ^(shift_reg & 7'h41); + + always @(posedge clk) + if (rst) + begin + count <= 1; + delayed_fall <= 1; + end + else if (full_deasserts) + begin + count <= shift_reg; + delayed_fall <= 1; + end + else if (count == 1) + begin + count <= 1; + delayed_fall <= 0; + end + else + begin + count <= count - 1; + delayed_fall <= 1; + end + + // Full_out goes instantly high if full_in does. However its fall is delayed. + assign full_out = (full_in == 1) || (full_last == 1) || delayed_fall; + +endmodule \ No newline at end of file -- cgit v1.2.3 From cd0f9cf58a87866d27ece0a47f85896a9f3ff705 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 21 Oct 2010 13:10:28 -0700 Subject: slow slew rate and lower drive to 8ma on RAM_XX signals to reduce emi --- usrp2/top/u2_rev3/u2_rev3.ucf | 86 +++++++++++++++++++++---------------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 6e0caedd5..deaeecb53 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -74,49 +74,49 @@ NET "MDC" LOC = "V18" ; NET "PHY_INTn" LOC = "AB13" ; NET "PHY_RESETn" LOC = "AA19" ; NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; NET "ser_enable" LOC = "W11" ; NET "ser_prbsen" LOC = "AA3" ; NET "ser_loopen" LOC = "Y4" ; -- cgit v1.2.3 From 9a687bdb82eeb5f5133146bb3af6800d8435c75d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 21 Oct 2010 15:14:37 -0700 Subject: address gray coding --- usrp2/extramfifo/nobl_if.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index 391a841e8..a8303deca 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -39,6 +39,12 @@ module nobl_if assign RAM_LDn = 0; // ZBT/NoBL RAM actually manages its own output enables very well. assign RAM_OEn = 0; + + // gray code the address to reduce EMI + wire [WIDTH-1:0] address_gray; + + bin2gray #(.WIDTH(WIDTH)) bin2gray (.bin(address),.gray(address_gray)); + // // Pipeline stage 1 @@ -59,7 +65,7 @@ module nobl_if if (enable) begin - address_pipe1 <= address; + address_pipe1 <= address_gray; write_pipe1 <= write; RAM_WEn <= ~write; // Creates IOB flob -- cgit v1.2.3 From f14e7eb89b09e6fc4b1619c9ec255ebad3fa2aed Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 21 Oct 2010 21:10:08 -0700 Subject: the width of the address bus is called DEPTH, not WIDTH... --- usrp2/extramfifo/nobl_if.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index a8303deca..adf9f165b 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -41,9 +41,9 @@ module nobl_if assign RAM_OEn = 0; // gray code the address to reduce EMI - wire [WIDTH-1:0] address_gray; + wire [DEPTH-1:0] address_gray; - bin2gray #(.WIDTH(WIDTH)) bin2gray (.bin(address),.gray(address_gray)); + bin2gray #(.WIDTH(DEPTH)) bin2gray (.bin(address),.gray(address_gray)); // -- cgit v1.2.3 From 960078083c602685a8680e68bbd82bbf8956828c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Oct 2010 16:50:23 -0700 Subject: images: remove exe bit left by some build processes --- images/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/images/Makefile b/images/Makefile index 57277e787..a2e3d945b 100644 --- a/images/Makefile +++ b/images/Makefile @@ -119,6 +119,7 @@ $(BUILT_IMAGES_DIR): mkdir $@ images: $(BUILT_IMAGES_DIR) $(IMAGES_LIST) + chmod -x $(BUILT_IMAGES_DIR)/* clean: $(RM) -rf $(BUILT_IMAGES_DIR) -- cgit v1.2.3 From 2d71c7a6e973b5715ca8e14cac99fb81fca9822c Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Fri, 22 Oct 2010 12:47:02 -0700 Subject: BasicRX: GPIOs now output 0 to decrease noise pickup. --- host/lib/usrp/dboard/db_basic_and_lf.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/host/lib/usrp/dboard/db_basic_and_lf.cpp b/host/lib/usrp/dboard/db_basic_and_lf.cpp index 41f6f8002..c58d0e326 100644 --- a/host/lib/usrp/dboard/db_basic_and_lf.cpp +++ b/host/lib/usrp/dboard/db_basic_and_lf.cpp @@ -95,6 +95,11 @@ UHD_STATIC_BLOCK(reg_basic_and_lf_dboards){ **********************************************************************/ basic_rx::basic_rx(ctor_args_t args, double max_freq) : rx_dboard_base(args){ _max_freq = max_freq; + + //set GPIOs to output 0x0000 to decrease noise pickup + this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, 0x0000); + this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, 0xFFFF); + this->get_iface()->write_gpio(dboard_iface::UNIT_RX, 0x0000); } basic_rx::~basic_rx(void){ -- cgit v1.2.3 From 971f6de77c6b67515b5d37d748e823da155b310c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 24 Oct 2010 16:01:47 -0700 Subject: dbsrx: allow for setup time after changing the vco selection --- host/lib/usrp/dboard/db_dbsrx.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/host/lib/usrp/dboard/db_dbsrx.cpp b/host/lib/usrp/dboard/db_dbsrx.cpp index aecd7249d..8ec87a4f7 100644 --- a/host/lib/usrp/dboard/db_dbsrx.cpp +++ b/host/lib/usrp/dboard/db_dbsrx.cpp @@ -374,6 +374,9 @@ void dbsrx::set_lo_freq(double target_freq){ //update vco selection and check vtune send_reg(0x2, 0x2); read_reg(0x0, 0x0); + + //allow for setup time before checking condition again + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); } if(dbsrx_debug) std::cerr << boost::format( -- cgit v1.2.3 From 81c9f77306dc82f250bfb2871b8bd7db67a40085 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 8 Nov 2010 17:22:37 -0800 Subject: usrp2: implemented clear state for RX and TX control, and zero sample command support --- firmware/microblaze/lib/net_common.c | 2 +- host/include/uhd/usrp/dsp_utils.hpp | 5 +---- host/lib/usrp/dsp_utils.cpp | 6 ++---- host/lib/usrp/usrp2/io_impl.cpp | 25 ------------------------- host/lib/usrp/usrp2/mboard_impl.cpp | 13 +++++-------- host/lib/usrp/usrp2/usrp2_impl.hpp | 1 - host/lib/usrp/usrp2/usrp2_regs.hpp | 2 +- 7 files changed, 10 insertions(+), 44 deletions(-) diff --git a/firmware/microblaze/lib/net_common.c b/firmware/microblaze/lib/net_common.c index 0a085db3a..6305408d6 100644 --- a/firmware/microblaze/lib/net_common.c +++ b/firmware/microblaze/lib/net_common.c @@ -298,7 +298,7 @@ handle_icmp_packet(struct ip_addr src, struct ip_addr dst, sr_tx_ctrl->cyc_per_up = 0; //the end continuous streaming command - sr_rx_ctrl->cmd = (1 << 31) | 1; //one sample, asap + sr_rx_ctrl->cmd = 1 << 31; //no samples now sr_rx_ctrl->time_secs = 0; sr_rx_ctrl->time_ticks = 0; //latch the command diff --git a/host/include/uhd/usrp/dsp_utils.hpp b/host/include/uhd/usrp/dsp_utils.hpp index 8ec04dd2f..5b81ce322 100644 --- a/host/include/uhd/usrp/dsp_utils.hpp +++ b/host/include/uhd/usrp/dsp_utils.hpp @@ -85,12 +85,9 @@ namespace dsp_type1{ /*! * Calculate the stream command word from the stream command struct. * \param stream_cmd the requested stream command with mode, flags, timestamp - * \param num_samps_continuous number of samples to request in continuous mode * \return the 32-bit stream command word */ - UHD_API boost::uint32_t calc_stream_cmd_word( - const stream_cmd_t &stream_cmd, size_t num_samps_continuous - ); + UHD_API boost::uint32_t calc_stream_cmd_word(const stream_cmd_t &stream_cmd); } //namespace dsp_type1 diff --git a/host/lib/usrp/dsp_utils.cpp b/host/lib/usrp/dsp_utils.cpp index 10ae9a086..2553e4a25 100644 --- a/host/lib/usrp/dsp_utils.cpp +++ b/host/lib/usrp/dsp_utils.cpp @@ -109,9 +109,7 @@ boost::uint32_t dsp_type1::calc_iq_scale_word(unsigned rate){ return calc_iq_scale_word(scale, scale); } -boost::uint32_t dsp_type1::calc_stream_cmd_word( - const stream_cmd_t &stream_cmd, size_t num_samps_continuous -){ +boost::uint32_t dsp_type1::calc_stream_cmd_word(const stream_cmd_t &stream_cmd){ UHD_ASSERT_THROW(stream_cmd.num_samps <= 0x3fffffff); //setup the mode to instruction flags @@ -133,6 +131,6 @@ boost::uint32_t dsp_type1::calc_stream_cmd_word( word |= boost::uint32_t((stream_cmd.stream_now)? 1 : 0) << 31; word |= boost::uint32_t((inst_chain)? 1 : 0) << 30; word |= boost::uint32_t((inst_reload)? 1 : 0) << 29; - word |= (inst_samps)? stream_cmd.num_samps : ((inst_chain)? num_samps_continuous : 1); + word |= (inst_samps)? stream_cmd.num_samps : ((inst_chain)? 1 : 0); return word; } diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 39e6c167f..844df603c 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -241,8 +241,6 @@ void usrp2_impl::io_impl::recv_pirate_loop( /*********************************************************************** * Helper Functions **********************************************************************/ -#include //TODO remove when hack below is fixed - void usrp2_impl::io_init(void){ //the assumption is that all data transports should be identical @@ -252,29 +250,6 @@ void usrp2_impl::io_init(void){ //create new io impl _io_impl = UHD_PIMPL_MAKE(io_impl, (num_recv_frames, send_frame_size, _data_transports.size())); - //TODO temporary fix for weird power up state, remove when FPGA fixed - { - //send an initial packet to all transports - tx_metadata_t md; md.end_of_burst = true; - this->send( - std::vector(_data_transports.size(), NULL), 0, md, - io_type_t::COMPLEX_FLOAT32, device::SEND_MODE_ONE_PACKET, 0 - ); - - //issue a stream command to each motherboard - BOOST_FOREACH(usrp2_mboard_impl::sptr mboard, _mboards){ - (*mboard)[MBOARD_PROP_STREAM_CMD] = stream_cmd_t(stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); - } - - //wait - boost::this_thread::sleep(boost::posix_time::milliseconds(100)); - - //flush all transport receive queues (no timeout) - BOOST_FOREACH(zero_copy_if::sptr xport, _data_transports){ - while(xport->get_recv_buff(0).get() != NULL){}; - } - } - //create a new pirate thread for each zc if (yarr!!) for (size_t i = 0; i < _data_transports.size(); i++){ _io_impl->recv_pirate_crew.create_thread(boost::bind( diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index bb9b6d1a9..d4dc8a4bd 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -40,7 +40,6 @@ usrp2_mboard_impl::usrp2_mboard_impl( const device_addr_t &flow_control_hints ): _index(index), - _recv_samps_per_packet(recv_samps_per_packet), _iface(usrp2_iface::make(ctrl_transport)) { //Send a small data packet so the usrp2 knows the udp source port. @@ -74,9 +73,9 @@ usrp2_mboard_impl::usrp2_mboard_impl( } //init the rx control registers - _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _recv_samps_per_packet); + _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset + _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, recv_samps_per_packet); _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1); - _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); //reset _iface->poke32(U2_REG_RX_CTRL_VRT_HEADER, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer @@ -88,8 +87,8 @@ usrp2_mboard_impl::usrp2_mboard_impl( _iface->poke32(U2_REG_TIME64_TPS, size_t(get_master_clock_freq())); //init the tx control registers - _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0); //1 channel _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset + _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0); //1 channel _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1); //sid 1 (different from rx) _iface->poke32(U2_REG_TX_CTRL_POLICY, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); @@ -97,6 +96,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( const double ups_per_sec = flow_control_hints.cast("ups_per_sec", 100); const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec); _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up); + _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, 0); //cycles per update is disabled //setting the packets per update const double ups_per_fifo = flow_control_hints.cast("ups_per_fifo", 8); @@ -187,7 +187,6 @@ void usrp2_mboard_impl::set_time_spec(const time_spec_t &time_spec, bool now){ } void usrp2_mboard_impl::handle_overflow(void){ - _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); if (_continuous_streaming){ //re-issue the stream command if already continuous this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); } @@ -195,9 +194,7 @@ void usrp2_mboard_impl::handle_overflow(void){ void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){ _continuous_streaming = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS; - _iface->poke32(U2_REG_RX_CTRL_STREAM_CMD, dsp_type1::calc_stream_cmd_word( - stream_cmd, _recv_samps_per_packet - )); + _iface->poke32(U2_REG_RX_CTRL_STREAM_CMD, dsp_type1::calc_stream_cmd_word(stream_cmd)); _iface->poke32(U2_REG_RX_CTRL_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); _iface->poke32(U2_REG_RX_CTRL_TIME_TICKS, stream_cmd.time_spec.get_tick_count(get_master_clock_freq())); } diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index e4980a539..e41cefc10 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -98,7 +98,6 @@ public: private: size_t _index; - const size_t _recv_samps_per_packet; bool _continuous_streaming; //interfaces diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index c3a4d22de..cef7cf2e6 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -179,7 +179,7 @@ #define U2_REG_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1) #define U2_REG_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2) -#define U2_REG_RX_CTRL_CLEAR_OVERRUN _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun +#define U2_REG_RX_CTRL_CLEAR_STATE _SR_ADDR(SR_RX_CTRL + 3) #define U2_REG_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter #define U2_REG_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet. #define U2_REG_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6) -- cgit v1.2.3 From 4b637f3ea251d39e518e4316521255d4cc648cc1 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 18 Nov 2010 09:49:12 -0800 Subject: Updated fw rev number in N2XX burner. --- host/utils/usrp_n2xx_net_burner.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/host/utils/usrp_n2xx_net_burner.py b/host/utils/usrp_n2xx_net_burner.py index 456f273df..21327e0af 100755 --- a/host/utils/usrp_n2xx_net_burner.py +++ b/host/utils/usrp_n2xx_net_burner.py @@ -16,7 +16,6 @@ # along with this program. If not, see . # -# TODO: make it work # TODO: make it autodetect UHD devices # TODO: you should probably watch sequence numbers @@ -36,7 +35,7 @@ UDP_MAX_XFER_BYTES = 1024 UDP_TIMEOUT = 3 UDP_POLL_INTERVAL = 0.10 #in seconds -USRP2_FW_PROTO_VERSION = 6 +USRP2_FW_PROTO_VERSION = 7 #from bootloader_utils.h -- cgit v1.2.3 From 768af46dc01d036999cb60ff16df4215d014c906 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 18 Nov 2010 09:55:48 -0800 Subject: Firmware mem map changes for flow ctrl somehow didn't get propagated. Also removed firmware update fw rev checking -- it occurs to me that checking fw rev in order to update fw is counterproductive. --- firmware/microblaze/usrp2/memory_map.h | 1 + firmware/microblaze/usrp2p/memory_map.h | 4 ++++ firmware/microblaze/usrp2p/udp_fw_update.c | 4 ++-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/firmware/microblaze/usrp2/memory_map.h b/firmware/microblaze/usrp2/memory_map.h index e7f41bc8d..eac0c217f 100644 --- a/firmware/microblaze/usrp2/memory_map.h +++ b/firmware/microblaze/usrp2/memory_map.h @@ -466,6 +466,7 @@ typedef struct { volatile uint32_t report_sid; volatile uint32_t policy; volatile uint32_t cyc_per_up; + volatile uint32_t packets_per_up; } sr_tx_ctrl_t; #define sr_tx_ctrl ((sr_tx_ctrl_t *) _SR_ADDR(SR_TX_CTRL)) diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h index 8d0d0c365..3b2dc0057 100644 --- a/firmware/microblaze/usrp2p/memory_map.h +++ b/firmware/microblaze/usrp2p/memory_map.h @@ -490,6 +490,10 @@ typedef struct { typedef struct { volatile uint32_t num_chan; volatile uint32_t clear_state; // clears out state machine, fifos, + volatile uint32_t report_sid; + volatile uint32_t policy; + volatile uint32_t cyc_per_up; + volatile uint32_t packets_per_up; } sr_tx_ctrl_t; #define sr_tx_ctrl ((sr_tx_ctrl_t *) _SR_ADDR(SR_TX_CTRL)) diff --git a/firmware/microblaze/usrp2p/udp_fw_update.c b/firmware/microblaze/usrp2p/udp_fw_update.c index 55c206b1b..ead08ad2c 100644 --- a/firmware/microblaze/usrp2p/udp_fw_update.c +++ b/firmware/microblaze/usrp2p/udp_fw_update.c @@ -38,13 +38,13 @@ void handle_udp_fw_update_packet(struct socket_address src, struct socket_addres usrp2_fw_update_id_t update_data_in_id = update_data_in->id; //ensure that the protocol versions match - if (payload_len >= sizeof(uint32_t) && update_data_in->proto_ver != USRP2_FW_COMPAT_NUM){ +/* if (payload_len >= sizeof(uint32_t) && update_data_in->proto_ver != USRP2_FW_COMPAT_NUM){ printf("!Error in update packet handler: Expected compatibility number %d, but got %d\n", USRP2_FW_COMPAT_NUM, update_data_in->proto_ver ); update_data_in_id = USRP2_FW_UPDATE_ID_OHAI_LOL; //so we can respond } - +*/ //ensure that this is not a short packet if (payload_len < sizeof(usrp2_fw_update_data_t)){ printf("!Error in update packet handler: Expected payload length %d, but got %d\n", -- cgit v1.2.3