From c8a2e4881f06212be7e10227220ebac33987143b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 6 Apr 2012 12:07:15 -0700 Subject: usrp: fix set_clock_config typo for external and mimo clock ref This is a typo in the set_clock_config implementation. However, the enum values are the same, so this would not cause a bug. Fixed although set_clock_config is a deprecated interface. --- host/lib/usrp/multi_usrp.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/multi_usrp.cpp b/host/lib/usrp/multi_usrp.cpp index 42c654e6b..93c0eada6 100644 --- a/host/lib/usrp/multi_usrp.cpp +++ b/host/lib/usrp/multi_usrp.cpp @@ -379,8 +379,8 @@ public: std::string clock_source; switch(clock_config.ref_source){ case clock_config_t::REF_INT: clock_source = "internal"; break; - case clock_config_t::PPS_SMA: clock_source = "external"; break; - case clock_config_t::PPS_MIMO: clock_source = "mimo"; break; + case clock_config_t::REF_SMA: clock_source = "external"; break; + case clock_config_t::REF_MIMO: clock_source = "mimo"; break; default: clock_source = "unknown"; } this->set_clock_source(clock_source, mboard); -- cgit v1.2.3 From 00c241844a62c22cac538316d507c524acc1c393 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 9 Apr 2012 14:28:25 -0700 Subject: dsp: clear register now overlaps with numchan register. This fixes the bug of unwanted clearing when setting format. --- host/lib/usrp/cores/rx_dsp_core_200.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/host/lib/usrp/cores/rx_dsp_core_200.cpp b/host/lib/usrp/cores/rx_dsp_core_200.cpp index 4b60f111c..cf8db1927 100644 --- a/host/lib/usrp/cores/rx_dsp_core_200.cpp +++ b/host/lib/usrp/cores/rx_dsp_core_200.cpp @@ -38,13 +38,12 @@ #define REG_RX_CTRL_STREAM_CMD _ctrl_base + 0 #define REG_RX_CTRL_TIME_HI _ctrl_base + 4 #define REG_RX_CTRL_TIME_LO _ctrl_base + 8 -#define REG_RX_CTRL_CLEAR _ctrl_base + 12 +#define REG_RX_CTRL_FORMAT _ctrl_base + 12 #define REG_RX_CTRL_VRT_HDR _ctrl_base + 16 #define REG_RX_CTRL_VRT_SID _ctrl_base + 20 #define REG_RX_CTRL_VRT_TLR _ctrl_base + 24 #define REG_RX_CTRL_NSAMPS_PP _ctrl_base + 28 #define REG_RX_CTRL_NCHANNELS _ctrl_base + 32 -#define REG_RX_CTRL_FORMAT REG_RX_CTRL_CLEAR //re-use clear address template T ceil_log2(T num){ return std::ceil(std::log(num)/std::log(T(2))); @@ -78,8 +77,7 @@ public: } void clear(void){ - _iface->poke32(REG_RX_CTRL_CLEAR, 1); //reset - _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); + _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); //also reset _iface->poke32(REG_RX_CTRL_VRT_HDR, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer -- cgit v1.2.3 From f136b06211dc0fe572d77219b6ce579963d435fe Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 9 Apr 2012 16:35:31 -0700 Subject: vita: moved clear register to overlap with nchan register This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2. --- usrp2/top/B100/u1plus_core.v | 2 +- usrp2/top/E1x0/u1e_core.v | 2 +- usrp2/top/N2x0/u2plus_core.v | 4 ++-- usrp2/top/USRP2/u2_core.v | 2 +- usrp2/vrt/vita_rx_chain.v | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 09b7e11f1..c1d6767d1 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -413,7 +413,7 @@ module u1plus_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd2}; //major, minor + localparam compat_num = {16'd9, 16'd3}; //major, minor wire [31:0] reg_test32; diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index ee27af939..a98e1de34 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -454,7 +454,7 @@ module u1e_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd0}; //major, minor + localparam compat_num = {16'd9, 16'd1}; //major, minor wire [31:0] reg_test32; diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index 369f01183..abc32406e 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -436,8 +436,8 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd0}; //major, minor - wire [31:0] churn = status; //tweak churn until timing meets! + localparam compat_num = {16'd9, 16'd1}; //major, minor + wire [31:0] churn = 0; //tweak churn until timing meets! wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 6bf60fe58..93064254f 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -442,7 +442,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd0}; //major, minor + localparam compat_num = {16'd9, 16'd1}; //major, minor wire [31:0] churn = 0; //tweak churn until timing meets! wb_readback_mux buff_pool_status diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index ca2f847bc..2788dc9d5 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -41,7 +41,7 @@ module vita_rx_chain wire clear; assign clear_o = clear; wire clear_int; - setting_reg #(.my_addr(BASE+3)) sr + setting_reg #(.my_addr(BASE+8)) sr (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_int)); -- cgit v1.2.3