From c07bc03b4f0fe6210f3bfc6ecdc079487d882f7d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 1 Oct 2010 15:18:26 -0700 Subject: fix timing problem on DAC output bus --- usrp2/top/u2_rev3/u2_rev3.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 4daa66212..bab5a7706 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -330,8 +330,8 @@ module u2_rev3 wire [15:0] dac_a_int, dac_b_int; // DAC A and B are swapped in schematic to facilitate clean layout // DAC A is also inverted in schematic to facilitate clean layout - always @(negedge dsp_clk) dac_a <= ~dac_b_int; - always @(negedge dsp_clk) dac_b <= dac_a_int; + always @(posedge dsp_clk) dac_a <= ~dac_b_int; + always @(posedge dsp_clk) dac_b <= dac_a_int; /* OFDDRRSE OFDDRRSE_serdes_inst -- cgit v1.2.3