From be183dae7a5d2e5f546d699c233d17430dd315ee Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 15 Oct 2019 16:30:01 -0700 Subject: Update branch for upcoming 3.15 release - Update submodule pointer - Update CHANGELOG to incorporate latest changes --- CHANGELOG | 6 ++++-- fpga-src | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index a74798479..8d49be808 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -57,7 +57,8 @@ Change Log for Releases mux data streams over liberio transports (e.g. to require fewer DMA channels on E310), wait for DPDK links to come up before proceeding, relax failure handling when updating components (fixes spurious errors - when updating FPGA images over SFP) + when updating FPGA images over SFP), fix issue where RPC + initialization would hang on failure * FPGA: Use new device-tree overlay syntax, upgraded to Vivado 2018.3, broke various paths with critical timing, allow SystemVerilog source files, improve viv_modify_bd and viv_modify_tcl_bd, fix resets on 2clk @@ -78,7 +79,8 @@ Change Log for Releases from the CMake commandline, add replay example, fix missing 'project', replace ENABLE_PYTHON3 with a simpler Python detection, clean up superfluous modules, improve log statements, bump dependency min - versions, add MPM unit testing, fix missing BIGOBJ for MSVC + versions, add MPM unit testing, fix missing BIGOBJ for MSVC, add our + own UHDBoost.cmake to better find Boost across versions and systems * Formatting: Apply clang-format to all files, break after template<> diff --git a/fpga-src b/fpga-src index 9e3d00c4b..ff03b00f3 160000 --- a/fpga-src +++ b/fpga-src @@ -1 +1 @@ -Subproject commit 9e3d00c4b9ead2840e40564e0d0dc3c89e2f877e +Subproject commit ff03b00f3d502cfb5f7c14d4fc4e1fc4d0df1412 -- cgit v1.2.3