From b9e715983eaa625f65f1ac4d18c7fbc9e5ace4cd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 26 Mar 2010 17:12:07 -0700 Subject: connect up the 16 bit spi core --- usrp2/top/u1e/Makefile | 3 +-- usrp2/top/u1e/u1e_core.v | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 3412e227d..2b78b21bd 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -137,8 +137,7 @@ opencores/simple_pic/rtl/simple_pic.v \ opencores/spi/rtl/verilog/spi_clgen.v \ opencores/spi/rtl/verilog/spi_defines.v \ opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ +opencores/spi/rtl/verilog/spi_top16.v \ sdr_lib/acc.v \ sdr_lib/add2.v \ sdr_lib/add2_and_round.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4f0227dfd..f2415d7e1 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -203,9 +203,9 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); -- cgit v1.2.3