From b87c8b834abc6e0db80d06411b1c0983cd740c1d Mon Sep 17 00:00:00 2001 From: Ashish Chaudhari Date: Fri, 24 Jul 2015 13:40:59 -0700 Subject: x300: Updated FPGA->ADC Clock delays for all boards - Delays changed after ADC config change and FPGA fixes --- host/lib/usrp/x300/x300_clock_ctrl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index 0812bcc8e..d5687f5cc 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -49,10 +49,10 @@ struct x300_clk_delays { // If the FPGA_CLK is delayed, we also need to delay the reference clocks going to the DAC // because the data interface clock is generated from FPGA_CLK. static const x300_clk_delays X300_REV0_6_CLK_DELAYS = x300_clk_delays( - /*fpga=*/0.000, /*adc=*/1.600, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); + /*fpga=*/0.000, /*adc=*/2.200, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); static const x300_clk_delays X300_REV7_CLK_DELAYS = x300_clk_delays( - /*fpga=*/0.000, /*adc=*/4.400, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); + /*fpga=*/0.000, /*adc=*/0.000, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); using namespace uhd; -- cgit v1.2.3