From b774533c615ef34732d93c30a6df6fa4d702d90e Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Tue, 23 Feb 2010 08:27:29 -0800 Subject: Manually assign clk_fpga to BUFG to improve timing Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs --- usrp2/top/u2_rev3/u2_rev3.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 23a825007..3c35743a3 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -171,7 +171,11 @@ module u2_rev3 wd <= wd + 1; assign WDI = wd[15]; - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + wire clk_fpga_unbuf; + + IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n)); + BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; wire exp_pps_in; -- cgit v1.2.3