From b63507efb3cf1a8fa20794c452d57028e18da182 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Tue, 22 Jul 2014 15:49:02 -0700 Subject: fpga: Updating FPGA code for UHD-3.7.2-rc1 --- fpga/usrp3/lib/dsp/ddc_chain.v | 26 +- fpga/usrp3/lib/timing/Makefile.srcs | 1 + fpga/usrp3/lib/timing/pps.v | 22 + fpga/usrp3/lib/timing/timekeeper.v | 24 +- fpga/usrp3/top/b200/b200_core.v | 25 +- fpga/usrp3/top/b200/coregen/chipscope_icon.gise | 2 +- fpga/usrp3/top/b200/coregen/chipscope_icon.xise | 4 +- fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise | 2 +- fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise | 4 +- fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise | 2 +- fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise | 4 +- fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise | 2 +- fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise | 4 +- fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise | 2 +- fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise | 4 +- fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise | 2 +- fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise | 4 +- fpga/usrp3/top/x300/Makefile | 4 +- .../top/x300/coregen/axi_intercon_2x64_128.gise | 2 +- .../top/x300/coregen/axi_intercon_2x64_128.ncf | 4 + .../top/x300/coregen/axi_intercon_2x64_128.xise | 4 +- fpga/usrp3/top/x300/coregen/bootram.coe | 6020 ++++++++++---------- fpga/usrp3/top/x300/coregen/chipscope_icon.gise | 2 +- fpga/usrp3/top/x300/coregen/chipscope_icon.xise | 4 +- .../top/x300/coregen/chipscope_icon_2port.gise | 2 +- .../top/x300/coregen/chipscope_icon_2port.xise | 4 +- fpga/usrp3/top/x300/coregen/chipscope_ila.gise | 2 +- fpga/usrp3/top/x300/coregen/chipscope_ila.xise | 4 +- fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise | 2 +- fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise | 4 +- fpga/usrp3/top/x300/coregen/coregen.cgp | 2 +- fpga/usrp3/top/x300/coregen/ddr3_32bit.gise | 2 +- fpga/usrp3/top/x300/coregen/ddr3_32bit.xise | 4 +- fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise | 2 +- fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise | 4 +- .../top/x300/coregen/fifo_xlnx_16x40_2clk.gise | 2 +- .../top/x300/coregen/fifo_xlnx_16x40_2clk.xise | 4 +- fpga/usrp3/top/x300/coregen_dsp/coregen.cgp | 2 +- fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise | 2 +- fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf | 0 fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise | 4 +- fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise | 2 +- fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf | 0 fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise | 4 +- fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise | 2 +- fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf | 0 fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise | 4 +- fpga/usrp3/top/x300/coregen_dsp/hbint1.gise | 2 +- fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf | 0 fpga/usrp3/top/x300/coregen_dsp/hbint1.xise | 4 +- fpga/usrp3/top/x300/coregen_dsp/hbint2.gise | 2 +- fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf | 0 fpga/usrp3/top/x300/coregen_dsp/hbint2.xise | 4 +- fpga/usrp3/top/x300/coregen_dsp/hbint3.gise | 2 +- fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf | 0 fpga/usrp3/top/x300/coregen_dsp/hbint3.xise | 4 +- fpga/usrp3/top/x300/floorplan_X300.ucf | 26 - fpga/usrp3/top/x300/gen_ddrlvds.v | 5 +- 58 files changed, 3153 insertions(+), 3128 deletions(-) create mode 100644 fpga/usrp3/lib/timing/pps.v create mode 100644 fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf create mode 100644 fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf create mode 100644 fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf create mode 100644 fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf create mode 100644 fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf create mode 100644 fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf create mode 100644 fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf diff --git a/fpga/usrp3/lib/dsp/ddc_chain.v b/fpga/usrp3/lib/dsp/ddc_chain.v index 365175bf1..ccddc24e0 100644 --- a/fpga/usrp3/lib/dsp/ddc_chain.v +++ b/fpga/usrp3/lib/dsp/ddc_chain.v @@ -1,5 +1,5 @@ // -// Copyright 2011-2013 Ettus Research LLC +// Copyright 2011-2014 Ettus Research LLC // @@ -37,7 +37,7 @@ module ddc_chain wire [WIDTH-1:0] i_cic, q_cic; wire [WIDTH-1:0] i_hb1, q_hb1; wire [WIDTH-1:0] i_hb2, q_hb2; - + wire strobe_cic, strobe_hb1, strobe_hb2; wire enable_hb1, enable_hb2; wire [7:0] cic_decim_rate; @@ -45,7 +45,9 @@ module ddc_chain reg [WIDTH-1:0] rx_fe_i_mux, rx_fe_q_mux; wire realmode; wire swap_iq; - + wire invert_i; + wire invert_q; + setting_reg #(.my_addr(BASE+0)) sr_0 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_inc),.changed()); @@ -58,22 +60,22 @@ module ddc_chain (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed()); - setting_reg #(.my_addr(BASE+3), .width(2)) sr_3 + setting_reg #(.my_addr(BASE+3), .width(4)) sr_3 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({realmode,swap_iq}),.changed()); + .in(set_data),.out({invert_i,inver_q,realmode,swap_iq}),.changed()); // MUX so we can do realmode signals on either input - + always @(posedge clk) if(swap_iq) begin - rx_fe_i_mux <= rx_fe_q; - rx_fe_q_mux <= realmode ? 0 : rx_fe_i; + rx_fe_i_mux <= invert_i ? ~rx_fe_q + 1 : rx_fe_q; + rx_fe_q_mux <= realmode ? 0 : invert_q ? ~rx_fe_i + 1 : rx_fe_i; end else begin - rx_fe_i_mux <= rx_fe_i; - rx_fe_q_mux <= realmode ? 0 : rx_fe_q; + rx_fe_i_mux <= invert_i ? ~rx_fe_i + 1 : rx_fe_i; + rx_fe_q_mux <= realmode ? 0 : invert_i ? ~rx_fe_q + 1 : rx_fe_q; end // NCO @@ -109,7 +111,7 @@ module ddc_chain decim_i (.clock(clk),.reset(rst),.enable(run), .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), .signal_in(i_cordic_clip),.signal_out(i_cic)); - + cic_decim #(.bw(WIDTH)) decim_q (.clock(clk),.reset(rst),.enable(run), .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), @@ -119,7 +121,7 @@ module ddc_chain small_hb_dec #(.WIDTH(WIDTH)) small_hb_i (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), .stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1)); - + small_hb_dec #(.WIDTH(WIDTH)) small_hb_q (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), .stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1)); diff --git a/fpga/usrp3/lib/timing/Makefile.srcs b/fpga/usrp3/lib/timing/Makefile.srcs index ff4ca17d2..09f0596c5 100644 --- a/fpga/usrp3/lib/timing/Makefile.srcs +++ b/fpga/usrp3/lib/timing/Makefile.srcs @@ -8,4 +8,5 @@ TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/timing/, \ time_compare.v \ timekeeper.v \ +pps.v\ )) diff --git a/fpga/usrp3/lib/timing/pps.v b/fpga/usrp3/lib/timing/pps.v new file mode 100644 index 000000000..49d3641b7 --- /dev/null +++ b/fpga/usrp3/lib/timing/pps.v @@ -0,0 +1,22 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module pps_generator + #(parameter CLK_FREQ=0, DUTY=25) + (input clk, input reset, output pps); + + reg[31:0] count; + + always @(posedge clk) begin + if (reset) begin + count <= 32'b1; + end else if (count >= CLK_FREQ) begin + count <= 32'b1; + end else begin + count <= count + 1'b1; + end + end + + assign pps = (count < CLK_FREQ * DUTY / 100); +endmodule //pps_generator diff --git a/fpga/usrp3/lib/timing/timekeeper.v b/fpga/usrp3/lib/timing/timekeeper.v index 627472094..761bda5bc 100644 --- a/fpga/usrp3/lib/timing/timekeeper.v +++ b/fpga/usrp3/lib/timing/timekeeper.v @@ -1,5 +1,5 @@ // -// Copyright 2013 Ettus Research LLC +// Copyright 2013-2014 Ettus Research LLC // @@ -19,11 +19,11 @@ module timekeeper setting_reg #(.my_addr(BASE), .width()) sr_time_hi (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(time_at_next_event[63:32]), .changed()); - + setting_reg #(.my_addr(BASE+1), .width()) sr_time_lo (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(time_at_next_event[31:0]), .changed()); - + setting_reg #(.my_addr(BASE+2), .width(2)) sr_ctrl (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .out({set_time_pps, set_time_now}), .changed(cmd_trigger)); @@ -37,12 +37,6 @@ module timekeeper wire pps_edge = !pps_del2 & pps_del; - ////////////////////////////////////////////////////////////////////////// - // track the time at last pps so host can detect the pps - ////////////////////////////////////////////////////////////////////////// - always @(posedge clk) - if(pps_edge) vita_time_lastpps <= vita_time; - ////////////////////////////////////////////////////////////////////////// // arm the trigger to latch a new time when the ctrl register is written ////////////////////////////////////////////////////////////////////////// @@ -65,4 +59,16 @@ module timekeeper else vita_time <= vita_time + 64'h1; + ////////////////////////////////////////////////////////////////////////// + // track the time at last pps so host can detect the pps + ////////////////////////////////////////////////////////////////////////// + always @(posedge clk) + if(reset) + vita_time_lastpps <= 64'h0; + else if(pps_edge) + if(time_event) + vita_time_lastpps <= time_at_next_event; + else + vita_time_lastpps <= vita_time + 64'h1; + endmodule // timekeeper diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v index 016037688..dc8baba4f 100644 --- a/fpga/usrp3/top/b200/b200_core.v +++ b/fpga/usrp3/top/b200/b200_core.v @@ -1,5 +1,5 @@ // -// Copyright 2013 Ettus Research LLC +// Copyright 2013-14 Ettus Research LLC // @@ -78,11 +78,24 @@ module b200_core /******************************************************************* * PPS Timing stuff ******************************************************************/ - reg [1:0] int_pps_del, ext_pps_del; + + // Generate an internal PPS signal + wire int_pps; + pps_generator #(.CLK_FREQ(100000000)) pps_gen + (.clk(bus_clk), .pps(int_pps)); + + // Flop PPS signals into radio clock domain + reg [1:0] gpsdo_pps_del, ext_pps_del, int_pps_del; always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext}; - always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], pps_int}; - wire pps_select; - wire pps = pps_select? ext_pps_del[1] : int_pps_del[1]; + always @(posedge radio_clk) gpsdo_pps_del[1:0] <= {gpsdo_pps_del[0], pps_int}; + always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps}; + + // PPS mux + wire [1:0] pps_select; + wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] : + (pps_select == 2'b01)? ext_pps_del[1] : + (pps_select == 2'b10)? int_pps_del[1] : + 1'b0; /******************************************************************* * Response mux Routing logic @@ -189,7 +202,7 @@ module b200_core (.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(gpsdo_st), .changed()); - setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(1)) sr_pps_sel + setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(2)) sr_pps_sel (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(pps_select), .changed()); diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise index a4f878755..29d14a154 100644 --- a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise index 669cbf101..5cb07142c 100644 --- a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise index 3af396d70..8f50adfb5 100644 --- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise index 3bc65beca..d89d10530 100644 --- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise index 6305e6288..85cc00a94 100644 --- a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise index f8c51bac1..a9e75da04 100644 --- a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise index 4bc01d034..e5487e74a 100644 --- a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise index 9a9fb9459..8d210d750 100644 --- a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise index c631a4815..ae7343223 100644 --- a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise index 2d8132c10..951b199cf 100644 --- a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise index ea47d0f4b..ddb581fc1 100644 --- a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise index 1ca7d35ee..1f72b185a 100644 --- a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile index a5a0b22c8..dbe3bdd55 100644 --- a/fpga/usrp3/top/x300/Makefile +++ b/fpga/usrp3/top/x300/Makefile @@ -83,10 +83,10 @@ X310_HGS: $(call post_build,X310,HGS) X300_HGS: - make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)" + make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T FLOORPLAN=1 $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)" $(call post_build,X300,HGS) -# 1Gig on both ports, SRAM Tx FIFO's +# 10Gig on both ports, SRAM Tx FIFO's X310_XGS: make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)" $(call post_build,X310,XGS) diff --git a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.gise b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.gise index a0a0f007e..0712f3aec 100644 --- a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.gise +++ b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf new file mode 100644 index 000000000..3f2148f6a --- /dev/null +++ b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf @@ -0,0 +1,4 @@ +NET "*_resync*" TNM = FFS "axi_intercon_2x64_128_reset_resync"; +NET "*INTERCONNECT_ARESETN" TNM = FFS "axi_intercon_2x64_128_reset_resync"; +TIMESPEC "TS_axi_intercon_2x64_128_reset_resync" = TO "axi_intercon_2x64_128_reset_resync" TIG; + diff --git a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise index fb1579c69..822e58aee 100644 --- a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise +++ b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen/bootram.coe b/fpga/usrp3/top/x300/coregen/bootram.coe index b14aa4f1e..c124e2bee 100755 --- a/fpga/usrp3/top/x300/coregen/bootram.coe +++ b/fpga/usrp3/top/x300/coregen/bootram.coe @@ -2,15 +2,15 @@ memory_initialization_radix=16; memory_initialization_vector= 0b0b0b0b, 82700b0b, -8196c80c, +8196cc0c, 3a0b0b80, -fec90400, +fecc0400, 00000000, 00000000, 00000000, 80088408, 88080b0b, -80ff942d, +80ff972d, 880c840c, 800c0400, 00000000, @@ -162,7 +162,7 @@ c4040000, 00000000, 71fc0608, 0b0b8196, -b4738306, +b8738306, 10100508, 060b0b0b, 88aa0400, @@ -171,7 +171,7 @@ b4738306, 80088408, 88087575, 0b0b80f5, -ee2d5050, +f12d5050, 80085688, 0c840c80, 0c510400, @@ -179,7 +179,7 @@ ee2d5050, 80088408, 88087575, 0b0b80f7, -a02d5050, +a32d5050, 80085688, 0c840c80, 0c510400, @@ -209,7 +209,7 @@ a02d5050, 00000000, 00000000, 810b0b0b, -8196c40c, +8196c80c, 51040000, 00000000, 00000000, @@ -257,7 +257,7 @@ a02d5050, 00000000, 00000000, 82813f80, -f8b53f04, +f8b83f04, 10101010, 10101010, 10101010, @@ -280,56 +280,56 @@ fc060c51, 0a100a53, 72ed3851, 51535104, -8196c408, -802ea438, 8196c808, +802ea438, +8196cc08, 822ebd38, 8380800b, 0b0b819e, -bc0c82a0, +c00c82a0, 800b819e, -c00c8290, +c40c8290, 800b819e, -c40c04f8, +c80c04f8, 808080a4, 0b0b0b81, -9ebc0cf8, +9ec00cf8, 80808280, -0b819ec0, +0b819ec4, 0cf88080, 84800b81, -9ec40c04, +9ec80c04, 80c0a880, 8c0b0b0b, -819ebc0c, +819ec00c, 80c0a880, 940b819e, -c00c0b0b, -8180e80b, -819ec40c, +c40c0b0b, +8180ec0b, +819ec80c, 04ff3d0d, -819ec833, +819ecc33, 5170a738, -8196d008, +8196d408, 70085252, 70802e94, 38841281, -96d00c70, -2d8196d0, +96d40c70, +2d8196d4, 08700852, 5270ee38, 810b819e, -c834833d, +cc34833d, 0d040480, 3d0d0b0b, -819eb808, +819ebc08, 802e8e38, 0b0b0b0b, 800b802e, 09810685, 38823d0d, 040b0b81, -9eb8510b, +9ebc510b, 0b0bf5d4, 3f823d0d, 0404f93d, @@ -357,57 +357,57 @@ b1387218, 04e23d0d, 8ba65283, fa805198, -813f8ba6, +843f8ba6, 5283f280, -5197f73f, +5197fa3f, 8b885280, -51a2a63f, +51a2a93f, 81a65281, -80f051a2, -a73f80cf, +80f451a2, +aa3f80cf, bcc3ab52, 83fc8051, -989d3f80, +98a03f80, cfbcc3ab, 5283fe80, -5198903f, +5198933f, 80cfbcc3, ab5283f8, -80519883, +80519886, 3f810b82, c0840c82, c0900855, 8a567481, 2e833881, 56755281, -819c51a1, -e33f82c0, +81a051a1, +e63f82c0, 9408558a, 5674812e, 83388156, 75528181, -b451a1cc, +b851a1cf, 3fbffc53, 82808052, -819ecc51, -a2e33f81, -9ecc0852, -8181cc51, -a1b23f81, -9ecc51a7, -ad3f80e6, -be3f8d3d, +819ed051, +a2e63f81, +9ed00852, +8181d051, +a1b53f81, +9ed051a7, +b03f80e6, +c13f8d3d, 5b80cc53, -8196d452, +8196d852, 7a5180ee, -9d3f8254, -8180ec53, +a03f8254, +8180f053, 80d05283, fe805198, -d43f80cc, +d73f80cc, 547a5380, d05283fe, -805197ac, +805197af, 3f82c090, 08558257, 74833874, @@ -415,36 +415,36 @@ d05283fe, 0855835c, 74833881, 5c865381, -96dc52a0, +96e052a0, 3dffbc05, 51fdab3f, 80085686, -538196e4, +538196e8, 52a03dc4, 0551fd9a, 3f800858, 84537682, -2b819780, +2b819784, 1153701c, ac115358, 55fd833f, 80085a84, -538196f0, +538196f4, 15529c17, 51fcf33f, 80085984, 537b822b, -81978011, +81978411, 53701cac, 11535855, fcdc3f80, 085b8453, -8196f015, +8196f415, 529c1751, fccc3f80, 0879557a, 54765357, -8051a686, +8051a689, 3f841633, 85173371, 882b0783, @@ -464,7 +464,7 @@ d00c9e80, 0b82c1d4, 0c76547a, 53775281, -51a5b73f, +51a5ba3f, 84183385, 19337188, 2b07831a, @@ -484,44 +484,44 @@ c2840c60, 82c2940c, 800b82c0, 840c80e4, -5180c984, +5180c987, 3f82c090, 08557481, 2e098106, 86388051, -b69f3f82, +b6a23f82, c0940855, 74812e09, 81068638, -7451b68d, +7451b690, 3f805580, e9397451, -a2e23f80, +a2e53f80, 085180d6, -a43f8008, +a73f8008, 53745281, -81e0519e, -833f7451, -a2b53f80, +81e4519e, +863f7451, +a2b83f80, 085180d6, -b23f8008, +b53f8008, 53745281, -81f4519d, -eb3f7451, -a4c43f80, +81f8519d, +ee3f7451, +a4c73f80, 085180d6, -9a3f8008, +9d3f8008, 53745281, -8288519d, -d33f7451, -a4c13f80, +828c519d, +d63f7451, +a4c43f80, 085180d6, -823f8008, +853f8008, 53745281, -829c519d, -bb3f8115, +82a0519d, +be3f8115, 7081ff06, -5155b3b0, +5155b3b3, 3f800875, 24ff8f38, a03d0d04, @@ -529,16 +529,16 @@ f53d0d7e, 60028805, b7053371, 545b5b54, -a1f63f80, +a1f93f80, 0858a855, 78802e83, 38b85573, 902a7081, ff067055, 75548182, -b0535157, -9cf23f78, -51a1b93f, +b4535157, +9cf53f78, +51a1bc3f, 74822b82, c0801180, 08338008, @@ -558,7 +558,7 @@ c0801180, 8818615a, 55535a41, 52525d57, -55a0d43f, +55a0d73f, 80080876, 0c82c08c, 15028405, @@ -602,7 +602,7 @@ f23d0d65, 81b2388c, 3d5b9053, 79527a51, -80e7f33f, +80e7f63f, 668f2688, 387b8207, 5c80f439, @@ -618,7 +618,7 @@ ac38881a, 53903dfc, 055277bf, ffff0651, -80c5fc3f, +80c5ff3f, 84397708, 5f790882, 2a708106, @@ -633,7 +633,7 @@ ffff0651, 80537852, 77bfffff, 065180c4, -dd3f8439, +e03f8439, 78780c79, 08810657, 76802e9c, @@ -643,7 +643,7 @@ dd3f8439, 80d20522, 53615202, 80c30533, -51a7cb3f, +51a7ce3f, 903d0d04, 8c08028c, 0cf03d0d, @@ -669,7 +669,7 @@ ec050808, 0c8c08d4, 0508802e, 913880c8, -b03f8008, +b33f8008, 81068c08, dc050c85, c5398c08, @@ -679,7 +679,7 @@ d8050883, 050c8c08, d4050880, 2e883880, -cabd3f85, +cac03f85, b8398c08, d8050886, 2a708106, @@ -687,7 +687,7 @@ d8050886, 050c8c08, d4050880, 2e883880, -ccba3f85, +ccbd3f85, 98398c08, d8050887, 2a708106, @@ -695,7 +695,7 @@ d8050887, 050c8c08, d4050880, 2e9c3880, -ccaf3f80, +ccb23f80, 0881ff06, 8c08d405, 0c8c08d4, @@ -704,7 +704,7 @@ ccaf3f80, d8398c08, ec050884, 05085180, -ca823f80, +ca853f80, 0881068c, 08dc050c, 8c08dc05, @@ -720,7 +720,7 @@ ca823f80, 98388c08, dc050880, 2e8f3880, -c9e23f80, +c9e53f80, 0881ff06, 8c08dc05, 0c8c08ec, @@ -761,7 +761,7 @@ ec050888, 05088c08, e0050805, 105180c3, -ab3f8008, +ae3f8008, 8c08dc05, 08068c08, dc050c8c, @@ -804,7 +804,7 @@ f4050c02, 05088805, 0810528c, 08f0050c, -80c1ae3f, +80c1b13f, 80088c08, dc050806, 8c08dc05, @@ -867,7 +867,7 @@ d4050880, 22538c08, 8c050852, 8c088b05, -3351a0ca, +3351a0cd, 3f8c08f8, 05080d92, 3d0d8c0c, @@ -876,8 +876,8 @@ d4050880, 2eb73877, 08810657, 768c3881, -82d85192, -a33f7884, +82dc5192, +a63f7884, 07597882, 0759615a, 84180856, @@ -886,7 +886,7 @@ a33f7884, 225402be, 0522537c, 5202af05, -33519ffe, +3351a081, 3f8b3d0d, 04f63d0d, 7c7e5957, @@ -894,7 +894,7 @@ a33f7884, 74547652, 77538c3d, f8055180, -d7b43f7a, +d7b73f7a, 81061681, 165656bf, 7527e538, @@ -903,75 +903,75 @@ d7b43f7a, 3d0deef5, 3f92d452, 83808051, -9cbf3f92, +9cc23f92, aa528380, -81519cb5, +81519cb8, 3f949452, 83808551, -9cab3f9b, +9cae3f9b, 9d528380, -86519ca1, +86519ca4, 3f805682, c0800870, 77315153, 8a968a73, 2784f938, 805b8197, -a0089d3d, +a4089d3d, ffbc0552, -5380cbe7, +5380cbea, 3f8008ac, 140c8197, -a0087bb0, +a4087bb0, 120c5381, -9ed808ff, -05819ed8, -0c819ed8, +9edc08ff, +05819edc, +0c819edc, 08ff2e09, 810680e0, 388fd00b, -819ed80c, -80c9a63f, +819edc0c, +80c9a93f, 805680c6, 397551ba, -ef3f8008, +f23f8008, 81ff0653, 72802e92, 387581ff, 06705253, -80cbd83f, +80cbdb3f, 725180d2, -f63f8116, +f93f8116, 70810670, 547781ff, 06705455, 555580d5, -853f7251, -80ced03f, +883f7251, +80ced33f, 73527251, -80d4f73f, -7456a5fc, +80d4fa3f, +7456a5ff, 3f800876, 26ffb238, -8197a008, +8197a408, 98110854, 54728738, 7294150c, a039819e, -dc08732e, +e008732e, 8e38810b, 94150c80, -0b819ee0, +0b819ee4, 0c8b3981, -9ee00881, -05819ee0, +9ee40881, +05819ee4, 0c981408, -819edc0c, +819ee00c, 8fd00b81, -9ee00827, +9ee40827, 8638800b, 94150c80, -0b819ee4, +0b819ee8, 0b8e3d5a, 5b597881, ff065580, @@ -990,7 +990,7 @@ a0165657, 57758025, f1387481, 268a3874, -5196d53f, +5196d83f, 80081757, 77088419, 08709f2a, @@ -1009,15 +1009,15 @@ f1387481, 88195959, 877927fe, f538819f, -84088105, -819f840c, +88088105, +819f880c, 7b7d5551, 7352fc8d, 3f80087e, 60565274, 5355fc81, 3f807583, -2b819f84, +2b819f88, 08bf0656, 56587375, 27833881, @@ -1025,12 +1025,12 @@ f538819f, 08832b54, 57737327, 83388157, -8051b880, +8051b883, 3f800881, ff065581, -51b7f53f, +51b7f83f, 800881ff, -068197a0, +068197a4, 08941108, 56545673, 802e8338, @@ -1052,224 +1052,191 @@ ff065581, 85387282, 07537282, c0800c81, -9f880881, -11819f88, +9f8c0881, +11819f8c, 0c5383d4, df7327b9, 38800b81, -9f880c80, +9f8c0c80, 54a63973, -51b6f93f, +51b6fc3f, 800881ff, 06537280, 2e933873, 81ff0670, -525390eb, +525390ee, 3f800852, -7251968c, +7251968f, 3f811454, -a2a63f80, +a2a93f80, 087426d3, 388051b2, -8d3f8151, -b2883f82, +903f8151, +b28b3f82, c0800856, -9ceb3f80, -c2be3f81, -97a00881, -9f8c0ba0, +9cee3f80, +c2c13f81, +97a40881, +9f900ba0, 120c81a1, -8c0ba412, +900ba412, 0c5380c0, 0ba8140c, 83fa8051, -81ce3f80, -08548008, -ff2e80c4, -3881a38c, -08810570, -81ff0670, -81a38c0c, -71832b98, -06525653, -72863872, -81a3900c, -73732b81, -a3900807, -7081a390, -0c7581fc, -06819f8c, -0555740c, -8197a008, -7588120c, -53ffad39, -8197a008, -5381a394, -088c1408, -2ebf3881, -a3940870, +81d13f80, +08538008, +ff2e80c7, +3881a390, +08810581, +a3900c81, +a3900870, 832b9806, -71fc0681, -a18c0570, -08722a55, -52555383, -fa8051ba, -3f81a394, -08810570, -81ff0670, -81a3940c, -8197a008, -56515372, -8c15082e, -098106c3, -388197a0, -08538c80, -80730cf9, -aa39803d, -0d727471, -0c51823d, -0d04fe3d, -0d748411, -53537108, -5170802e, -f9388c13, -76710c51, -843d0d04, -fe3d0d74, -88117008, -515253ff, -5270802e, -87389013, -70085351, -71800c84, -3d0d04fc, -3d0d7653, -80fa8980, -52775180, -d1ba3f80, -08ff0570, -83ffff06, -7081ff06, -750c7088, -2a84160c, -51548180, -0b88140c, -863d0d04, +55557386, +387381a3, +940c7281, +ff067075, +2b81a394, +08077081, +a3940c76, +81fc0681, +9f900556, +750c5381, +97a40875, +88120c53, +ffaa3981, +97a40853, +81a39808, +8c14082e, +bf3881a3, +98087083, +2b980671, +fc0681a1, +90057008, +722a5552, +555383fa, +8051ba3f, +81a39808, +81057081, +ff067081, +a3980c81, +97a40856, +5153728c, +15082e09, +8106c338, +8197a408, +538c8080, +730cf9a7, +39803d0d, +7274710c, +51823d0d, +04fe3d0d, +74841153, +53710851, +70802ef9, +388c1376, +710c5184, +3d0d04fe, +3d0d7488, +11700851, +5253ff52, +70802e87, +38901370, +08535171, +800c843d, +0d04fc3d, +0d765380, +fa898052, +775180d1, +ba3f8008, +ff057083, +ffff0670, +81ff0675, +0c70882a, +84160c51, +5481800b, +88140c86, +3d0d04fd, +3d0d7578, +7a555552, +81517280, +2e818238, +90120870, +862a7081, +06515151, +70f23802, +9b053370, +1081078c, +140c5181, +900b9013, +0c901208, +70812a70, +81065151, +5170f238, +90120870, +872a7081, +06708132, +51515151, +70802eb7, +3872802e, +ae3880e8, +5172812e, +8338a051, +7090130c, +90120870, +812a7081, +06515151, +70f2388c, +12085170, +74708105, +5634ff13, +53cf3981, +51873980, +c00b9013, +0c70800c, +853d0d04, fd3d0d75, 787a5555, -52815172, -802e8182, -38901208, +52901208, 70862a70, 81065151, 5170f238, 029b0533, -70108107, -8c140c51, -81900b90, -130c9012, -0870812a, -70810651, -515170f2, -38901208, -70872a70, -81067081, -32515151, -5170802e, -b7387280, -2eae3880, -e8517281, -2e8338a0, +70108c14, +0c5181d0, +5172802e, +84388190, 51709013, 0c901208, 70812a70, 81065151, 5170f238, -8c120851, -70747081, -055634ff, -1353cf39, -81518739, -80c00b90, -130c7080, -0c853d0d, -04fd3d0d, -75787a55, -55529012, -0870862a, -70810651, -515170f2, -38029b05, -3370108c, -140c5181, -d0517280, -2e843881, -90517090, -130c9012, -0870812a, -70810651, -515170f2, -38901208, -70872a70, -81067081, -32515151, -5170802e, -80cb3872, -802e80c1, -3873338c, -130c80d0, -5172812e, -83389051, -7090130c, 90120870, -812a7081, -06515151, -70f23890, -12087087, +872a7081, +06708132, +51515151, +70802e80, +cb387280, +2e80c138, +73338c13, +0c80d051, +72812e83, +38905170, +90130c90, +12087081, 2a708106, -70813251, 51515170, -802e8e38, -8114ff14, -5454ffbb, -39815189, -3980c00b, -90130c80, -5170800c, -853d0d04, -f63d0d7c, -7e60625a, -5d5b5680, -59815585, -39747a29, -55745275, -5180ceb4, -3f80087a, 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+ffad3881, +97ac0853, +bc1308a5, +387951ff, +833f7408, 53722dff, 14fc17fc, 1779812c, 5a575754, -738025d6, -38770858, -77ffad38, -8197a808, -53bc1308, -a5387951, -ff833f74, -0853722d, -ff14fc17, -fc177981, -2c5a5757, -54738025, -ffa838d1, -398057ff, -93397251, -bc130853, -722d7951, -fed73fff, -3d0d819e, -ac0bfc05, +738025ff, +a838d139, +8057ff93, +397251bc, +13085372, +2d7951fe, +d73fff3d, +0d819eb0, +0bfc0570, +08525270, +ff2e9138, +702dfc12, 70085252, -70ff2e91, -38702dfc, -12700852, -5270ff2e, -098106f1, -38833d0d, -0404ff88, -e83f0400, +70ff2e09, +8106f138, +833d0d04, +04ff88e5, +3f040000, 00000040, 00000000, 58333030, @@ -4714,75 +4715,75 @@ e83f0400, 46502b20, 74797065, 2e0a0000, -00002467, -0000246e, -00002461, -00002461, -00002461, -00002461, -0000246e, -0000246e, -0000246e, -0000246e, -0000246e, -0000245b, -0000246e, -0000246e, -00002455, -0000244f, -000025aa, -000025a4, -0000259e, -00002598, -00002592, -0000258c, -00002586, -00002580, -000026b1, -000028c6, -000028c6, -000028c6, -000026aa, -000026a3, -0000269c, -00002695, -0000268e, -00002687, -00002680, -00002679, -00002672, -0000266b, -00002664, -0000265d, -000027fc, -000027ee, -000027e0, -000027d2, -000027c3, -000027b3, -000027a3, -00002793, -00002783, -00002773, -0000276c, -00002765, -00002755, -00002745, -0000280b, -0000272e, -0000286a, -00002864, -0000285e, -00002858, -000028bd, -000028bd, -000028bd, -000028bd, -000028bd, -000028bd, -000028bd, -00002852, -0000284c, +0000246a, +00002471, +00002464, +00002464, +00002464, +00002464, +00002471, +00002471, +00002471, +00002471, +00002471, +0000245e, +00002471, +00002471, +00002458, +00002452, +000025ad, +000025a7, +000025a1, +0000259b, +00002595, +0000258f, +00002589, +00002583, +000026b4, +000028c9, +000028c9, +000028c9, +000026ad, +000026a6, +0000269f, +00002698, +00002691, +0000268a, +00002683, +0000267c, +00002675, +0000266e, +00002667, +00002660, +000027ff, +000027f1, +000027e3, +000027d5, +000027c6, +000027b6, +000027a6, +00002796, +00002786, +00002776, +0000276f, +00002768, +00002758, +00002748, +0000280e, +00002731, +0000286d, +00002867, +00002861, +0000285b, +000028c0, +000028c0, +000028c0, +000028c0, +000028c0, +000028c0, +000028c0, +00002855, +0000284f, 00000000, 00000001, 00000004, @@ -4820,7 +4821,7 @@ ffffff00, 00000000, 00000000, 00000000, -00004f34, +00004f38, 00000000, 00000000, 0050c285, @@ -4841,12 +4842,12 @@ c0a82802, 00000000, 00000000, 00006000, -00004b24, -00004bac, +00004b28, +00004bb0, 00000000, -00004e14, -00004e70, -00004ecc, +00004e18, +00004e74, +00004ed0, 00000000, 00000000, 00000000, @@ -4856,7 +4857,7 @@ c0a82802, 00000000, 00000000, 00000000, -00004b30, +00004b34, 00000000, 00000000, 00000000, @@ -8190,5 +8191,4 @@ ffffffff, 00000000, 00000000, 00000000, -00000000, 00000000; \ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon.gise b/fpga/usrp3/top/x300/coregen/chipscope_icon.gise index a4f878755..29d14a154 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_icon.gise +++ b/fpga/usrp3/top/x300/coregen/chipscope_icon.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon.xise b/fpga/usrp3/top/x300/coregen/chipscope_icon.xise index 45b6ff0c5..82f131ab5 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_icon.xise +++ b/fpga/usrp3/top/x300/coregen/chipscope_icon.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.gise b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.gise index 36f5c446e..e17e6e891 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.gise +++ b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise index 84e1a9201..c1b1aa977 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise +++ b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila.gise b/fpga/usrp3/top/x300/coregen/chipscope_ila.gise index bf58d19ac..ee7bbd2ac 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_ila.gise +++ b/fpga/usrp3/top/x300/coregen/chipscope_ila.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila.xise b/fpga/usrp3/top/x300/coregen/chipscope_ila.xise index 9c38762e8..c77f79bd9 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_ila.xise +++ b/fpga/usrp3/top/x300/coregen/chipscope_ila.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise index 53cc8f886..c0b0e6a23 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise +++ b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise index 3a41b0d74..bc394c976 100644 --- a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise +++ b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen/coregen.cgp b/fpga/usrp3/top/x300/coregen/coregen.cgp index 3e343ea49..287f67be4 100644 --- a/fpga/usrp3/top/x300/coregen/coregen.cgp +++ b/fpga/usrp3/top/x300/coregen/coregen.cgp @@ -1,6 +1,6 @@ SET busformat = BusFormatAngleBracketNotRipped SET designentry = Verilog -SET device = xc7k325t +SET device = xc7k410t SET devicefamily = kintex7 SET flowvendor = Foundation_ISE SET package = ffg900 diff --git a/fpga/usrp3/top/x300/coregen/ddr3_32bit.gise b/fpga/usrp3/top/x300/coregen/ddr3_32bit.gise index ad3ed0e03..53c91b2d8 100644 --- a/fpga/usrp3/top/x300/coregen/ddr3_32bit.gise +++ b/fpga/usrp3/top/x300/coregen/ddr3_32bit.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise b/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise index be231b442..d8694a9ea 100644 --- a/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise +++ b/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise b/fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise index ea47d0f4b..ddb581fc1 100644 --- a/fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise +++ b/fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise b/fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise index 0fa5fd50e..a23da93b5 100644 --- a/fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise +++ b/fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise index a66f268df..64c479aaf 100644 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise +++ b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise index 4c5ef82d1..9d088377d 100644 --- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise +++ b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp b/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp index 75b625f9b..593e2f179 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp +++ b/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp @@ -1,6 +1,6 @@ SET busformat = BusFormatAngleBracketNotRipped SET designentry = Verilog -SET device = xc7k325t +SET device = xc7k410t SET devicefamily = kintex7 SET flowvendor = Other SET package = ffg900 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise index 89731aaf8..5caeab612 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise index 0d52b5d47..61795798c 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise index 3a0d858e5..e87ebf933 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise index ea71dfd55..af99fb5fb 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise index 97abfa58f..d23808b1b 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise index d38b61410..1af65c49d 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint1.gise b/fpga/usrp3/top/x300/coregen_dsp/hbint1.gise index fb4e6f8ff..c6c4013b9 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint1.gise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint1.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise index a18bcca78..ddfc071f2 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise b/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise index f1ee7b4ca..e4b9546a7 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise index 86c139f4e..471c12463 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise b/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise index 2ba7d5965..bad4add7b 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise @@ -15,7 +15,7 @@ - + 11.1 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise index 764b94b96..a608666d2 100644 --- a/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise +++ b/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise @@ -9,10 +9,10 @@ - + - + diff --git a/fpga/usrp3/top/x300/floorplan_X300.ucf b/fpga/usrp3/top/x300/floorplan_X300.ucf index e2b704d7b..5e1b278c1 100644 --- a/fpga/usrp3/top/x300/floorplan_X300.ucf +++ b/fpga/usrp3/top/x300/floorplan_X300.ucf @@ -1,30 +1,4 @@ -INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y39; -INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y40; -INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y41; -INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y42; -INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y43; -INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y44; -INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y45; -INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y46; - -INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y39; -INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y40; -INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y41; -INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y42; -INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y43; -INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y44; -INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y45; -INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y46; - -INST "x300_core/bus_int/sc/axi_stream_to_wb/input_stream_bram/Mram_ram1" LOC = RAMB36_X3Y35; -INST "x300_core/bus_int/sc/axi_stream_to_wb/input_stream_bram/Mram_ram2" LOC = RAMB36_X3Y36; - -INST "x300_core/bus_int/sc/axi_stream_to_wb/output_stream_bram/Mram_ram1" LOC = RAMB36_X3Y37; -INST "x300_core/bus_int/sc/axi_stream_to_wb/output_stream_bram/Mram_ram2" LOC = RAMB36_X3Y38; - -INST "x300_core/bus_int/sc/zpu_top0*" AREA_GROUP = "pblock_0"; -AREA_GROUP "pblock_0" RANGE=SLICE_X80Y179:SLICE_X145Y242; INST "x300_core/radio0/*" AREA_GROUP = "pblock_1"; AREA_GROUP "pblock_1" RANGE=SLICE_X0Y101:SLICE_X79Y248; diff --git a/fpga/usrp3/top/x300/gen_ddrlvds.v b/fpga/usrp3/top/x300/gen_ddrlvds.v index 396d5feda..680b10c84 100644 --- a/fpga/usrp3/top/x300/gen_ddrlvds.v +++ b/fpga/usrp3/top/x300/gen_ddrlvds.v @@ -31,6 +31,8 @@ module gen_ddrlvds reg rising_edge; wire [15:0] i_and_q_2x; reg sync_2x; + reg sync_dacs_reg; + genvar z; @@ -55,6 +57,7 @@ module gen_ddrlvds begin i_reg <= i; q_reg <= q; + sync_dacs_reg <= sync_dacs; end always @(posedge tx_clk_2x) @@ -67,7 +70,7 @@ module gen_ddrlvds // To sync multiple AD9146 DAC's an extended assertion of FRAME is required, // when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME, // also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for. - sync_2x <= (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs) ? 1'b1 /* SET */ : sync_2x /* HOLD */; + sync_2x <= (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs_reg) ? 1'b1 /* SET */ : sync_2x /* HOLD */; rising_edge <= (phase_eq_phase2x && ~sync_2x); phase_2x <= phase; end -- cgit v1.2.3