From 503d95c58373a81ca7404162318f2658cf4c3642 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 1 Oct 2012 17:11:37 -0700 Subject: b100: fix RX ADC I and Q inversion --- usrp2/top/B100/B100.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/usrp2/top/B100/B100.v b/usrp2/top/B100/B100.v index dcda974b4..e333e82aa 100644 --- a/usrp2/top/B100/B100.v +++ b/usrp2/top/B100/B100.v @@ -143,13 +143,13 @@ module B100 always @(posedge clk_fpga) if(rxsync_0) begin - rx_i <= rx_b; - rx_q <= rx_a; + rx_i <= ~rx_b; + rx_q <= ~rx_a; end else begin - rx_i <= rx_a; - rx_q <= rx_b; + rx_i <= ~rx_a; + rx_q <= ~rx_b; end // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From a631a912af5e900c84b366a9c29d1c66f769c98e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 1 Oct 2012 17:19:04 -0700 Subject: e1x0: fix RX ADC I and Q inversion --- usrp2/top/E1x0/u1e.v | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/usrp2/top/E1x0/u1e.v b/usrp2/top/E1x0/u1e.v index 903ef7a6f..cdf2a7f0d 100644 --- a/usrp2/top/E1x0/u1e.v +++ b/usrp2/top/E1x0/u1e.v @@ -121,7 +121,18 @@ module u1e .D1(1'b1), // 1-bit data input (associated with C1) .R(1'b0), // 1-bit reset input .S(1'b0)); // 1-bit set input - + + // ///////////////////////////////////////////////////////////////////////// + // RX ADC -- handles inversion + + reg [11:0] rx_i, rx_q; + always @(posedge clk_fpga) begin + rx_i <= ~DA; + rx_q <= ~DB; + end + + // ///////////////////////////////////////////////////////////////////////// + // ///////////////////////////////////////////////////////////////////////// // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), @@ -138,7 +149,7 @@ module u1e .rx_have_data(overo_gpio146), .io_tx(io_tx), .io_rx(io_rx), .tx_i(tx_i), .tx_q(tx_q), - .rx_i(DA), .rx_q(DB), + .rx_i(rx_i), .rx_q(rx_q), .pps_in(PPS_IN), .proc_int(proc_int) ); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 1db56533253f13dd067234059cf7e471af329dde Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 5 Oct 2012 13:41:02 -0700 Subject: b100/e100: bump compat minor for inversion fix --- usrp2/top/B100/u1plus_core.v | 2 +- usrp2/top/E1x0/u1e_core.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index c1d6767d1..74151ce98 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -413,7 +413,7 @@ module u1plus_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd3}; //major, minor + localparam compat_num = {16'd9, 16'd4}; //major, minor wire [31:0] reg_test32; diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index bd19d6076..408aeb240 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -454,7 +454,7 @@ module u1e_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd3}; //major, minor + localparam compat_num = {16'd9, 16'd4}; //major, minor wire [31:0] reg_test32; -- cgit v1.2.3 From 8cfb73ed7d3b8b687509349ad6452886ce6d028b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 1 Oct 2012 17:19:04 -0700 Subject: e1x0: fix RX ADC I and Q inversion --- usrp2/top/E1x0/E1x0.v | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/usrp2/top/E1x0/E1x0.v b/usrp2/top/E1x0/E1x0.v index e7b0a4e00..8efb056e9 100644 --- a/usrp2/top/E1x0/E1x0.v +++ b/usrp2/top/E1x0/E1x0.v @@ -132,6 +132,15 @@ module E1x0 .R(1'b0), // 1-bit reset input .S(1'b0)); // 1-bit set input + // ///////////////////////////////////////////////////////////////////////// + // RX ADC -- handles inversion + + reg [11:0] rx_i, rx_q; + always @(posedge clk_fpga) begin + rx_i <= ~DA; + rx_q <= ~DB; + end + // ///////////////////////////////////////////////////////////////////////// // Main Core wire [35:0] rx_data, tx_data, ctrl_data, resp_data; @@ -166,7 +175,7 @@ module E1x0 .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso), .io_tx(io_tx), .io_rx(io_rx), .tx_i(tx_i), .tx_q(tx_q), - .rx_i(DA), .rx_q(DB), + .rx_i(rx_i), .rx_q(rx_q), .pps_in(PPS_IN) ); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From f83847318fa60bbc55c7dba2e2bfc01fb7ca2fdc Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 5 Oct 2012 14:11:42 -0700 Subject: b100/e100: bump compat for inversion fix on master --- usrp2/top/B100/u1plus_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index ef0ce51f7..423282153 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -71,7 +71,7 @@ module u1plus_core localparam SR_GPIO = 224; // 5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd11, 16'd0}; //major, minor + localparam compat_num = {16'd11, 16'd1}; //major, minor //assign run signals used for ATR logic wire [NUM_RX_DSPS-1:0] run_rx_n; -- cgit v1.2.3