From 31f4c22df7246ed69899dfd1dcae5888d50a8c98 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 14 Nov 2010 14:35:10 -0800 Subject: packet_router: created nearly empty router with eth in attached to mapped memory --- usrp2/fifo/Makefile.srcs | 1 + usrp2/fifo/packet_router.v | 120 ++++++++++++++++++++++++++++++++++++++++ usrp2/top/u2_rev3/u2_core_udp.v | 33 +++++------ 3 files changed, 135 insertions(+), 19 deletions(-) create mode 100644 usrp2/fifo/packet_router.v diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs index c66979132..acd25d807 100644 --- a/usrp2/fifo/Makefile.srcs +++ b/usrp2/fifo/Makefile.srcs @@ -22,4 +22,5 @@ fifo36_to_fifo19.v \ fifo19_to_fifo36.v \ fifo36_mux.v \ fifo36_demux.v \ +packet_router.v \ )) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v new file mode 100644 index 000000000..53cf1bcce --- /dev/null +++ b/usrp2/fifo/packet_router.v @@ -0,0 +1,120 @@ +module packet_router + #(parameter BUF_SIZE = 9) + ( + //wishbone interface for memory mapped CPU frames + input wb_clk_i, + input wb_rst_i, + input wb_we_i, + input wb_stb_i, + input [15:0] wb_adr_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output reg wb_ack_o, + output wb_err_o, + output wb_rty_o, + + input stream_clk, + input stream_rst, + + //input control register + input [31:0] control, + + //output status register + output [31:0] status, + + output sys_int_o, //want an interrupt? + + // Input Interfaces (in to router) + input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready, + + // Output Interfaces (out of router) + output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready + ); + + //which buffer: 0 = CPU read buffer, 1 = CPU write buffer + wire which_buf = wb_adr_i[BUF_SIZE+2]; + + //////////////////////////////////////////////////////////////////// + // status and controls + //////////////////////////////////////////////////////////////////// + wire eth_to_cpu_flag_ack = control[0]; + + wire eth_to_cpu_flag_rdy; + assign status[0] = eth_to_cpu_flag_rdy; + + //////////////////////////////////////////////////////////////////// + // Ethernet input control + //////////////////////////////////////////////////////////////////// + + localparam ETH_TO_CPU_STATE_WAIT_SOF = 0; + localparam ETH_TO_CPU_STATE_WAIT_EOF = 1; + localparam ETH_TO_CPU_STATE_WAIT_ACK_HI = 2; + localparam ETH_TO_CPU_STATE_WAIT_ACK_LO = 3; + + reg [1:0] eth_to_cpu_state; + reg [BUF_SIZE-1:0] eth_to_cpu_addr; + wire [BUF_SIZE-1:0] eth_to_cpu_addr_next = eth_to_cpu_addr + 1'b1; + + wire eth_to_cpu_reading_input = ( + eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_SOF || + eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_EOF + )? 1'b1 : 1'b0; + + wire eth_to_cpu_we = eth_to_cpu_reading_input; + assign eth_inp_ready = eth_to_cpu_reading_input; + assign eth_to_cpu_flag_rdy = (eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_ACK_HI)? 1'b1 : 1'b0; + + assign wb_err_o = 1'b0; // Unused for now + assign wb_rty_o = 1'b0; // Unused for now + always @(posedge wb_clk_i) + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + RAMB16_S36_S36 eth_to_cpu_buff( + //port A = wishbone memory mapped address space + .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), + .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i), + //port B = input from ethernet packets + .DOB(),.ADDRB(eth_to_cpu_addr),.CLKB(stream_clk),.DIB(eth_inp_data),.DIPB(4'h0), + .ENB(eth_to_cpu_we),.SSRB(0),.WEB(eth_to_cpu_we) + ); + + always @(posedge stream_clk) + if(stream_rst) begin + eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_SOF; + eth_to_cpu_addr <= 0; + end + else begin + case(eth_to_cpu_state) + ETH_TO_CPU_STATE_WAIT_SOF: begin + if (eth_inp_ready & eth_inp_valid & (eth_inp_data[32] == 1'b1)) begin + eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_EOF; + eth_to_cpu_addr <= eth_to_cpu_addr_next; + end + end + + ETH_TO_CPU_STATE_WAIT_EOF: begin + if (eth_inp_ready & eth_inp_valid & (eth_inp_data[33] == 1'b1)) begin + eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_ACK_HI; + end + if (eth_inp_ready & eth_inp_valid) begin + eth_to_cpu_addr <= eth_to_cpu_addr_next; + end + end + + ETH_TO_CPU_STATE_WAIT_ACK_HI: begin + if (eth_to_cpu_flag_ack == 1'b1) begin + eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_ACK_LO; + end + end + + ETH_TO_CPU_STATE_WAIT_ACK_LO: begin + if (eth_to_cpu_flag_ack == 0'b1) begin + eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_SOF; + end + end + + endcase //eth_to_cpu_state + end + + +endmodule // packet_router diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 9e62ee1cc..19b152b70 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -359,29 +359,24 @@ module u2_core wire wr3_ready_i, wr3_ready_o; wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + + wire [31:0] router_control; + + setting_reg #(.my_addr(SR_BUF_POOL)) + sreg(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(router_control),.changed()); + + packet_router #(.BUF_SIZE(9)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - + .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + + .control(router_control), .status(status), .sys_int_o(buffer_int), + + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); wire [31:0] status_enc; -- cgit v1.2.3 From 64e01dbe4c5fa6451e68b5fe7c3ae5d04daa7961 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 15 Nov 2010 10:55:41 -0800 Subject: packet_router: connected and created CPU read from interface (slow path in place) --- usrp2/fifo/packet_router.v | 200 ++++++++++++++++++++++++++++++++++----------- 1 file changed, 153 insertions(+), 47 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 53cf1bcce..6a7826387 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -31,90 +31,196 @@ module packet_router output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready ); + assign wb_err_o = 1'b0; // Unused for now + assign wb_rty_o = 1'b0; // Unused for now + always @(posedge wb_clk_i) + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + //////////////////////////////////////////////////////////////////// + // CPU interface to this packet router + //////////////////////////////////////////////////////////////////// + wire [35:0] cpu_inp_data; + wire cpu_inp_valid; + wire cpu_inp_ready; + wire [35:0] cpu_out_data; + wire cpu_out_valid; + wire cpu_out_ready; + //which buffer: 0 = CPU read buffer, 1 = CPU write buffer wire which_buf = wb_adr_i[BUF_SIZE+2]; //////////////////////////////////////////////////////////////////// - // status and controls + // status and control handshakes //////////////////////////////////////////////////////////////////// - wire eth_to_cpu_flag_ack = control[0]; + wire cpu_inp_hs_ctrl = control[0]; + wire cpu_out_hs_ctrl = control[1]; + wire [BUF_SIZE-1:0] cpu_out_line_count = control[BUF_SIZE-1+16:0+16]; + + wire cpu_inp_hs_stat; + assign status[0] = cpu_inp_hs_stat; + + wire [BUF_SIZE-1:0] cpu_inp_line_count; + assign status[BUF_SIZE-1+16:0+16] = cpu_inp_line_count; - wire eth_to_cpu_flag_rdy; - assign status[0] = eth_to_cpu_flag_rdy; + wire cpu_out_hs_stat; + assign status[1] = cpu_out_hs_stat; //////////////////////////////////////////////////////////////////// // Ethernet input control //////////////////////////////////////////////////////////////////// + //TODO: just connect eth input to cpu input for now + assign cpu_inp_data = eth_inp_data; + assign cpu_inp_valid = eth_inp_valid; + assign eth_inp_ready = cpu_inp_ready; - localparam ETH_TO_CPU_STATE_WAIT_SOF = 0; - localparam ETH_TO_CPU_STATE_WAIT_EOF = 1; - localparam ETH_TO_CPU_STATE_WAIT_ACK_HI = 2; - localparam ETH_TO_CPU_STATE_WAIT_ACK_LO = 3; + //////////////////////////////////////////////////////////////////// + // Ethernet output control + //////////////////////////////////////////////////////////////////// + //TODO: just connect eth output to cpu output for now + assign eth_out_data = cpu_out_data; + assign eth_out_valid = cpu_out_valid; + assign cpu_out_ready = eth_out_ready; - reg [1:0] eth_to_cpu_state; - reg [BUF_SIZE-1:0] eth_to_cpu_addr; - wire [BUF_SIZE-1:0] eth_to_cpu_addr_next = eth_to_cpu_addr + 1'b1; + //////////////////////////////////////////////////////////////////// + // Interface CPU input interface to memory mapped wishbone + //////////////////////////////////////////////////////////////////// + localparam CPU_INP_STATE_WAIT_SOF = 0; + localparam CPU_INP_STATE_WAIT_EOF = 1; + localparam CPU_INP_STATE_WAIT_CTRL_HI = 2; + localparam CPU_INP_STATE_WAIT_CTRL_LO = 3; + + reg [1:0] cpu_inp_state; + reg [BUF_SIZE-1:0] cpu_inp_addr; + assign cpu_inp_line_count = cpu_inp_addr; + wire [BUF_SIZE-1:0] cpu_inp_addr_next = cpu_inp_addr + 1'b1; - wire eth_to_cpu_reading_input = ( - eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_SOF || - eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_EOF + wire cpu_inp_reading = ( + cpu_inp_state == CPU_INP_STATE_WAIT_SOF || + cpu_inp_state == CPU_INP_STATE_WAIT_EOF )? 1'b1 : 1'b0; - wire eth_to_cpu_we = eth_to_cpu_reading_input; - assign eth_inp_ready = eth_to_cpu_reading_input; - assign eth_to_cpu_flag_rdy = (eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_ACK_HI)? 1'b1 : 1'b0; - - assign wb_err_o = 1'b0; // Unused for now - assign wb_rty_o = 1'b0; // Unused for now - always @(posedge wb_clk_i) - wb_ack_o <= wb_stb_i & ~wb_ack_o; + wire cpu_inp_we = cpu_inp_reading; + assign cpu_inp_ready = cpu_inp_reading; + assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; - RAMB16_S36_S36 eth_to_cpu_buff( - //port A = wishbone memory mapped address space - .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), + RAMB16_S36_S36 cpu_inp_buff( + //port A = wishbone memory mapped address space (output only) + .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0), .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i), - //port B = input from ethernet packets - .DOB(),.ADDRB(eth_to_cpu_addr),.CLKB(stream_clk),.DIB(eth_inp_data),.DIPB(4'h0), - .ENB(eth_to_cpu_we),.SSRB(0),.WEB(eth_to_cpu_we) + //port B = packet router interface to CPU (input only) + .DOB(),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(cpu_inp_data),.DIPB(4'h0), + .ENB(cpu_inp_we),.SSRB(0),.WEB(cpu_inp_we) ); always @(posedge stream_clk) if(stream_rst) begin - eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_SOF; - eth_to_cpu_addr <= 0; + cpu_inp_state <= CPU_INP_STATE_WAIT_SOF; + cpu_inp_addr <= 0; end else begin - case(eth_to_cpu_state) - ETH_TO_CPU_STATE_WAIT_SOF: begin - if (eth_inp_ready & eth_inp_valid & (eth_inp_data[32] == 1'b1)) begin - eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_EOF; - eth_to_cpu_addr <= eth_to_cpu_addr_next; + case(cpu_inp_state) + CPU_INP_STATE_WAIT_SOF: begin + if (cpu_inp_ready & cpu_inp_valid & (cpu_inp_data[32] == 1'b1)) begin + cpu_inp_state <= CPU_INP_STATE_WAIT_EOF; + cpu_inp_addr <= cpu_inp_addr_next; end end - ETH_TO_CPU_STATE_WAIT_EOF: begin - if (eth_inp_ready & eth_inp_valid & (eth_inp_data[33] == 1'b1)) begin - eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_ACK_HI; + CPU_INP_STATE_WAIT_EOF: begin + if (cpu_inp_ready & cpu_inp_valid & (cpu_inp_data[33] == 1'b1)) begin + cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; end - if (eth_inp_ready & eth_inp_valid) begin - eth_to_cpu_addr <= eth_to_cpu_addr_next; + if (cpu_inp_ready & cpu_inp_valid) begin + cpu_inp_addr <= cpu_inp_addr_next; end end - ETH_TO_CPU_STATE_WAIT_ACK_HI: begin - if (eth_to_cpu_flag_ack == 1'b1) begin - eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_ACK_LO; + CPU_INP_STATE_WAIT_CTRL_HI: begin + if (cpu_inp_hs_ctrl == 1'b1) begin + cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_LO; end end - ETH_TO_CPU_STATE_WAIT_ACK_LO: begin - if (eth_to_cpu_flag_ack == 0'b1) begin - eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_SOF; + CPU_INP_STATE_WAIT_CTRL_LO: begin + if (cpu_inp_hs_ctrl == 1'b0) begin + cpu_inp_state <= CPU_INP_STATE_WAIT_SOF; end + cpu_inp_addr <= 0; //reset the address counter end - endcase //eth_to_cpu_state + endcase //cpu_inp_state end + //////////////////////////////////////////////////////////////////// + // Interface CPU output interface to memory mapped wishbone + //////////////////////////////////////////////////////////////////// + localparam CPU_OUT_STATE_WAIT_CTRL_HI = 0; + localparam CPU_OUT_STATE_WAIT_CTRL_LO = 1; + localparam CPU_OUT_STATE_UNLOAD = 2; + + reg [1:0] cpu_out_state; + reg [BUF_SIZE-1:0] cpu_out_addr; + wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1; + + reg [BUF_SIZE-1:0] cpu_out_line_count_reg; + + reg cpu_out_flag_sof; + reg cpu_out_flag_eof; + assign cpu_out_data[35:32] = {2'b0, cpu_out_flag_eof, cpu_out_flag_sof}; + + assign cpu_out_valid = (cpu_out_state == CPU_OUT_STATE_UNLOAD)? 1'b1 : 1'b0; + assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; + + RAMB16_S36_S36 cpu_out_buff( + //port A = wishbone memory mapped address space (input only) + .DOA(),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), + .ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i), + //port B = packet router interface from CPU (output only) + .DOB(cpu_out_data[31:0]),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), + .ENB(1'b1),.SSRB(0),.WEB(1'b0) + ); + + always @(posedge stream_clk) + if(stream_rst) begin + cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI; + cpu_out_addr <= 0; + end + else begin + case(cpu_out_state) + CPU_OUT_STATE_WAIT_CTRL_HI: begin + if (cpu_out_hs_ctrl == 1'b1) begin + cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_LO; + end + cpu_out_line_count_reg <= cpu_out_line_count; + cpu_out_addr <= 0; //reset the address counter + end + + CPU_OUT_STATE_WAIT_CTRL_LO: begin + if (cpu_out_hs_ctrl == 1'b0) begin + cpu_out_state <= CPU_OUT_STATE_UNLOAD; + cpu_out_addr <= cpu_out_addr_next; + end + cpu_out_flag_sof <= 1'b1; + cpu_out_flag_eof <= 1'b0; + end + + CPU_OUT_STATE_UNLOAD: begin + if (cpu_out_ready & cpu_out_valid) begin + cpu_out_addr <= cpu_out_addr_next; + cpu_out_flag_sof <= 1'b0; + if (cpu_out_addr == cpu_out_line_count_reg) begin + cpu_out_flag_eof <= 1'b1; + end + else begin + cpu_out_flag_eof <= 1'b0; + end + if (cpu_out_flag_eof) begin + cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI; + end + end + end + + endcase //cpu_out_state + end endmodule // packet_router -- cgit v1.2.3 From 8b49f9a475fea0d110cb6392391a5e6d3cad8658 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 15 Nov 2010 15:36:45 -0800 Subject: packet_router: created inspector and added dsp output (however inspection logic does not enable it yet) --- usrp2/fifo/packet_router.v | 137 ++++++++++++++++++++++++++++++++++++++-- usrp2/top/u2_rev3/u2_core_udp.v | 1 + 2 files changed, 134 insertions(+), 4 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 6a7826387..288ff05e3 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -28,6 +28,7 @@ module packet_router input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready, // Output Interfaces (out of router) + output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready, output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready ); @@ -69,9 +70,9 @@ module packet_router // Ethernet input control //////////////////////////////////////////////////////////////////// //TODO: just connect eth input to cpu input for now - assign cpu_inp_data = eth_inp_data; - assign cpu_inp_valid = eth_inp_valid; - assign eth_inp_ready = cpu_inp_ready; + //assign cpu_inp_data = eth_inp_data; + //assign cpu_inp_valid = eth_inp_valid; + //assign eth_inp_ready = cpu_inp_ready; //////////////////////////////////////////////////////////////////// // Ethernet output control @@ -93,7 +94,7 @@ module packet_router reg [BUF_SIZE-1:0] cpu_inp_addr; assign cpu_inp_line_count = cpu_inp_addr; wire [BUF_SIZE-1:0] cpu_inp_addr_next = cpu_inp_addr + 1'b1; - + wire cpu_inp_reading = ( cpu_inp_state == CPU_INP_STATE_WAIT_SOF || cpu_inp_state == CPU_INP_STATE_WAIT_EOF @@ -223,4 +224,132 @@ module packet_router endcase //cpu_out_state end + //////////////////////////////////////////////////////////////////// + // Ethernet input inspector + // - inspect Ethernet and send it to CPU or DSP + //////////////////////////////////////////////////////////////////// + localparam ETH_INSP_READ_ETH_PRE = 0; + localparam ETH_INSP_READ_ETH = 1; + localparam ETH_INSP_WRITE_DSP_REGS = 2; + localparam ETH_INSP_WRITE_DSP_LIVE = 3; + localparam ETH_INSP_WRITE_CPU_REGS = 4; + localparam ETH_INSP_WRITE_CPU_LIVE = 5; + + localparam ETH_INSP_MAX_NUM_DREGS = 12; //padded_eth + ip + udp + vrt_hdr lines + localparam ETH_INSP_DREGS_DSP_OFFSET = 10; //offset to start dsp at + + reg [2:0] eth_insp_state; + reg [3:0] eth_insp_dreg_count; //data registers to buffer headers + wire [3:0] eth_insp_dreg_count_next = eth_insp_dreg_count + 1'b1; + reg [35:0] eth_insp_dregs [ETH_INSP_MAX_NUM_DREGS-1:0]; + + wire eth_inp_dregs_is_data = 1'b0; //TODO (not data for now) + + ///////////////////////////////////// + //assign output signals to CPU input + ///////////////////////////////////// + assign cpu_inp_data = (eth_insp_state == ETH_INSP_WRITE_CPU_REGS)? + eth_insp_dregs[eth_insp_dreg_count] : eth_inp_data + ; + assign cpu_inp_valid = + (eth_insp_state == ETH_INSP_WRITE_CPU_REGS)? 1'b1 : ( + (eth_insp_state == ETH_INSP_WRITE_CPU_LIVE)? eth_inp_valid : ( + 1'b0)); + + ///////////////////////////////////// + //assign output signals to DSP output + ///////////////////////////////////// + wire [3:0] eth_insp_dsp_flags = (eth_insp_dreg_count == ETH_INSP_DREGS_DSP_OFFSET)? + 4'b0001 : 4'b0000 + ; + assign dsp_out_data = (eth_insp_state == ETH_INSP_WRITE_DSP_REGS)? + {eth_insp_dsp_flags, eth_insp_dregs[eth_insp_dreg_count][31:0]} : eth_inp_data + ; + assign dsp_out_valid = + (eth_insp_state == ETH_INSP_WRITE_DSP_REGS)? 1'b1 : ( + (eth_insp_state == ETH_INSP_WRITE_DSP_LIVE)? eth_inp_valid : ( + 1'b0)); + + ///////////////////////////////////// + //assign output signal to ETH input + ///////////////////////////////////// + assign eth_inp_ready = + (eth_insp_state == ETH_INSP_READ_ETH_PRE) ? 1'b1 : ( + (eth_insp_state == ETH_INSP_READ_ETH) ? 1'b1 : ( + (eth_insp_state == ETH_INSP_WRITE_DSP_LIVE)? dsp_out_ready : ( + (eth_insp_state == ETH_INSP_WRITE_CPU_LIVE)? cpu_inp_ready : ( + 1'b0)))); + + always @(posedge stream_clk) + if(stream_rst) begin + eth_insp_state <= ETH_INSP_READ_ETH_PRE; + eth_insp_dreg_count <= 0; + end + else begin + case(eth_insp_state) + ETH_INSP_READ_ETH_PRE: begin + if (eth_inp_ready & eth_inp_valid & eth_inp_data[32]) begin + eth_insp_state <= ETH_INSP_READ_ETH; + eth_insp_dreg_count <= eth_insp_dreg_count_next; + eth_insp_dregs[eth_insp_dreg_count] <= eth_inp_data; + end + end + + ETH_INSP_READ_ETH: begin + if (eth_inp_ready & eth_inp_valid) begin + eth_insp_dregs[eth_insp_dreg_count] <= eth_inp_data; + if (eth_inp_dregs_is_data & (eth_insp_dreg_count_next == ETH_INSP_MAX_NUM_DREGS)) begin + eth_insp_state <= ETH_INSP_WRITE_DSP_REGS; + eth_insp_dreg_count <= ETH_INSP_DREGS_DSP_OFFSET; + end + else if (eth_inp_data[33] | (eth_insp_dreg_count_next == ETH_INSP_MAX_NUM_DREGS)) begin + eth_insp_state <= ETH_INSP_WRITE_CPU_REGS; + eth_insp_dreg_count <= 0; + end + else begin + eth_insp_dreg_count <= eth_insp_dreg_count_next; + end + end + end + + ETH_INSP_WRITE_DSP_REGS: begin + if (dsp_out_ready & dsp_out_valid) begin + eth_insp_dreg_count <= eth_insp_dreg_count_next; + if (eth_insp_dreg_count_next == ETH_INSP_MAX_NUM_DREGS) begin + eth_insp_state <= ETH_INSP_WRITE_DSP_LIVE; + eth_insp_dreg_count <= 0; + end + end + + end + + ETH_INSP_WRITE_DSP_LIVE: begin + if (dsp_out_ready & dsp_out_valid & eth_inp_data[33]) begin + eth_insp_state <= ETH_INSP_READ_ETH_PRE; + end + end + + ETH_INSP_WRITE_CPU_REGS: begin + if (cpu_inp_ready & cpu_inp_valid) begin + eth_insp_dreg_count <= eth_insp_dreg_count_next; + if (cpu_inp_data[33]) begin + eth_insp_state <= ETH_INSP_READ_ETH_PRE; + eth_insp_dreg_count <= 0; + end + else if (eth_insp_dreg_count_next == ETH_INSP_MAX_NUM_DREGS) begin + eth_insp_state <= ETH_INSP_WRITE_CPU_LIVE; + eth_insp_dreg_count <= 0; + end + end + end + + ETH_INSP_WRITE_CPU_LIVE: begin + if (cpu_inp_ready & cpu_inp_valid & eth_inp_data[33]) begin + eth_insp_state <= ETH_INSP_READ_ETH_PRE; + end + end + + endcase //eth_insp_state + end + endmodule // packet_router diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 19b152b70..d2932d0fc 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -376,6 +376,7 @@ module u2_core .control(router_control), .status(status), .sys_int_o(buffer_int), .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .dsp_out_data({rd0_flags, rd0_dat}), .dsp_out_valid(rd0_ready_o), .dsp_out_ready(rd0_ready_i), .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); -- cgit v1.2.3 From 9066f0f75663199c72d28d9ca650c431ee2d371e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 15 Nov 2010 17:30:34 -0800 Subject: packet_router: created com signals (device IO lines that may be ethernet or serdes) --- usrp2/fifo/packet_router.v | 179 +++++++++++++++++++++++++-------------------- 1 file changed, 100 insertions(+), 79 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 288ff05e3..031fe1c78 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -37,6 +37,9 @@ module packet_router always @(posedge wb_clk_i) wb_ack_o <= wb_stb_i & ~wb_ack_o; + //which buffer: 0 = CPU read buffer, 1 = CPU write buffer + wire which_buf = wb_adr_i[BUF_SIZE+2]; + //////////////////////////////////////////////////////////////////// // CPU interface to this packet router //////////////////////////////////////////////////////////////////// @@ -47,8 +50,15 @@ module packet_router wire cpu_out_valid; wire cpu_out_ready; - //which buffer: 0 = CPU read buffer, 1 = CPU write buffer - wire which_buf = wb_adr_i[BUF_SIZE+2]; + //////////////////////////////////////////////////////////////////// + // Communication interfaces + //////////////////////////////////////////////////////////////////// + wire [35:0] com_inp_data; + wire com_inp_valid; + wire com_inp_ready; + wire [35:0] com_out_data; + wire com_out_valid; + wire com_out_ready; //////////////////////////////////////////////////////////////////// // status and control handshakes @@ -67,20 +77,31 @@ module packet_router assign status[1] = cpu_out_hs_stat; //////////////////////////////////////////////////////////////////// - // Ethernet input control + // Communication input source combiner + // - combine streams from serdes and ethernet + //////////////////////////////////////////////////////////////////// + //TODO: just connect eth input to com input for now + assign com_inp_data = eth_inp_data; + assign com_inp_valid = eth_inp_valid; + assign eth_inp_ready = com_inp_ready; + + //////////////////////////////////////////////////////////////////// + // Communication output sink demuxer + // - demux the stream to serdes or ethernet //////////////////////////////////////////////////////////////////// - //TODO: just connect eth input to cpu input for now - //assign cpu_inp_data = eth_inp_data; - //assign cpu_inp_valid = eth_inp_valid; - //assign eth_inp_ready = cpu_inp_ready; + //TODO: just connect eth output to com output for now + assign eth_out_data = com_out_data; + assign eth_out_valid = com_out_valid; + assign com_out_ready = eth_out_ready; //////////////////////////////////////////////////////////////////// - // Ethernet output control + // Communication output source combiner + // - combine streams from dsp framer, com inspector, and cpu //////////////////////////////////////////////////////////////////// - //TODO: just connect eth output to cpu output for now - assign eth_out_data = cpu_out_data; - assign eth_out_valid = cpu_out_valid; - assign cpu_out_ready = eth_out_ready; + //TODO: just connect com output to cpu output for now + assign com_out_data = cpu_out_data; + assign com_out_valid = cpu_out_valid; + assign cpu_out_ready = com_out_ready; //////////////////////////////////////////////////////////////////// // Interface CPU input interface to memory mapped wishbone @@ -225,131 +246,131 @@ module packet_router end //////////////////////////////////////////////////////////////////// - // Ethernet input inspector - // - inspect Ethernet and send it to CPU or DSP + // Communication input inspector + // - inspect com input and send it to CPU, DSP, or COM //////////////////////////////////////////////////////////////////// - localparam ETH_INSP_READ_ETH_PRE = 0; - localparam ETH_INSP_READ_ETH = 1; - localparam ETH_INSP_WRITE_DSP_REGS = 2; - localparam ETH_INSP_WRITE_DSP_LIVE = 3; - localparam ETH_INSP_WRITE_CPU_REGS = 4; - localparam ETH_INSP_WRITE_CPU_LIVE = 5; + localparam COM_INSP_READ_COM_PRE = 0; + localparam COM_INSP_READ_COM = 1; + localparam COM_INSP_WRITE_DSP_REGS = 2; + localparam COM_INSP_WRITE_DSP_LIVE = 3; + localparam COM_INSP_WRITE_CPU_REGS = 4; + localparam COM_INSP_WRITE_CPU_LIVE = 5; - localparam ETH_INSP_MAX_NUM_DREGS = 12; //padded_eth + ip + udp + vrt_hdr lines - localparam ETH_INSP_DREGS_DSP_OFFSET = 10; //offset to start dsp at + localparam COM_INSP_MAX_NUM_DREGS = 12; //padded_eth + ip + udp + vrt_hdr lines + localparam COM_INSP_DREGS_DSP_OFFSET = 10; //offset to start dsp at - reg [2:0] eth_insp_state; - reg [3:0] eth_insp_dreg_count; //data registers to buffer headers - wire [3:0] eth_insp_dreg_count_next = eth_insp_dreg_count + 1'b1; - reg [35:0] eth_insp_dregs [ETH_INSP_MAX_NUM_DREGS-1:0]; + reg [2:0] com_insp_state; + reg [3:0] com_insp_dreg_count; //data registers to buffer headers + wire [3:0] com_insp_dreg_count_next = com_insp_dreg_count + 1'b1; + reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0]; - wire eth_inp_dregs_is_data = 1'b0; //TODO (not data for now) + wire com_inp_dregs_is_data = 1'b0; //TODO (not data for now) ///////////////////////////////////// //assign output signals to CPU input ///////////////////////////////////// - assign cpu_inp_data = (eth_insp_state == ETH_INSP_WRITE_CPU_REGS)? - eth_insp_dregs[eth_insp_dreg_count] : eth_inp_data + assign cpu_inp_data = (com_insp_state == COM_INSP_WRITE_CPU_REGS)? + com_insp_dregs[com_insp_dreg_count] : com_inp_data ; assign cpu_inp_valid = - (eth_insp_state == ETH_INSP_WRITE_CPU_REGS)? 1'b1 : ( - (eth_insp_state == ETH_INSP_WRITE_CPU_LIVE)? eth_inp_valid : ( + (com_insp_state == COM_INSP_WRITE_CPU_REGS)? 1'b1 : ( + (com_insp_state == COM_INSP_WRITE_CPU_LIVE)? com_inp_valid : ( 1'b0)); ///////////////////////////////////// //assign output signals to DSP output ///////////////////////////////////// - wire [3:0] eth_insp_dsp_flags = (eth_insp_dreg_count == ETH_INSP_DREGS_DSP_OFFSET)? + wire [3:0] com_insp_dsp_flags = (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET)? 4'b0001 : 4'b0000 ; - assign dsp_out_data = (eth_insp_state == ETH_INSP_WRITE_DSP_REGS)? - {eth_insp_dsp_flags, eth_insp_dregs[eth_insp_dreg_count][31:0]} : eth_inp_data + assign dsp_out_data = (com_insp_state == COM_INSP_WRITE_DSP_REGS)? + {com_insp_dsp_flags, com_insp_dregs[com_insp_dreg_count][31:0]} : com_inp_data ; assign dsp_out_valid = - (eth_insp_state == ETH_INSP_WRITE_DSP_REGS)? 1'b1 : ( - (eth_insp_state == ETH_INSP_WRITE_DSP_LIVE)? eth_inp_valid : ( + (com_insp_state == COM_INSP_WRITE_DSP_REGS)? 1'b1 : ( + (com_insp_state == COM_INSP_WRITE_DSP_LIVE)? com_inp_valid : ( 1'b0)); ///////////////////////////////////// - //assign output signal to ETH input + //assign output signal to COM input ///////////////////////////////////// - assign eth_inp_ready = - (eth_insp_state == ETH_INSP_READ_ETH_PRE) ? 1'b1 : ( - (eth_insp_state == ETH_INSP_READ_ETH) ? 1'b1 : ( - (eth_insp_state == ETH_INSP_WRITE_DSP_LIVE)? dsp_out_ready : ( - (eth_insp_state == ETH_INSP_WRITE_CPU_LIVE)? cpu_inp_ready : ( + assign com_inp_ready = + (com_insp_state == COM_INSP_READ_COM_PRE) ? 1'b1 : ( + (com_insp_state == COM_INSP_READ_COM) ? 1'b1 : ( + (com_insp_state == COM_INSP_WRITE_DSP_LIVE)? dsp_out_ready : ( + (com_insp_state == COM_INSP_WRITE_CPU_LIVE)? cpu_inp_ready : ( 1'b0)))); always @(posedge stream_clk) if(stream_rst) begin - eth_insp_state <= ETH_INSP_READ_ETH_PRE; - eth_insp_dreg_count <= 0; + com_insp_state <= COM_INSP_READ_COM_PRE; + com_insp_dreg_count <= 0; end else begin - case(eth_insp_state) - ETH_INSP_READ_ETH_PRE: begin - if (eth_inp_ready & eth_inp_valid & eth_inp_data[32]) begin - eth_insp_state <= ETH_INSP_READ_ETH; - eth_insp_dreg_count <= eth_insp_dreg_count_next; - eth_insp_dregs[eth_insp_dreg_count] <= eth_inp_data; + case(com_insp_state) + COM_INSP_READ_COM_PRE: begin + if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin + com_insp_state <= COM_INSP_READ_COM; + com_insp_dreg_count <= com_insp_dreg_count_next; + com_insp_dregs[com_insp_dreg_count] <= com_inp_data; end end - ETH_INSP_READ_ETH: begin - if (eth_inp_ready & eth_inp_valid) begin - eth_insp_dregs[eth_insp_dreg_count] <= eth_inp_data; - if (eth_inp_dregs_is_data & (eth_insp_dreg_count_next == ETH_INSP_MAX_NUM_DREGS)) begin - eth_insp_state <= ETH_INSP_WRITE_DSP_REGS; - eth_insp_dreg_count <= ETH_INSP_DREGS_DSP_OFFSET; + COM_INSP_READ_COM: begin + if (com_inp_ready & com_inp_valid) begin + com_insp_dregs[com_insp_dreg_count] <= com_inp_data; + if (com_inp_dregs_is_data & (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)) begin + com_insp_state <= COM_INSP_WRITE_DSP_REGS; + com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; end - else if (eth_inp_data[33] | (eth_insp_dreg_count_next == ETH_INSP_MAX_NUM_DREGS)) begin - eth_insp_state <= ETH_INSP_WRITE_CPU_REGS; - eth_insp_dreg_count <= 0; + else if (com_inp_data[33] | (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)) begin + com_insp_state <= COM_INSP_WRITE_CPU_REGS; + com_insp_dreg_count <= 0; end else begin - eth_insp_dreg_count <= eth_insp_dreg_count_next; + com_insp_dreg_count <= com_insp_dreg_count_next; end end end - ETH_INSP_WRITE_DSP_REGS: begin + COM_INSP_WRITE_DSP_REGS: begin if (dsp_out_ready & dsp_out_valid) begin - eth_insp_dreg_count <= eth_insp_dreg_count_next; - if (eth_insp_dreg_count_next == ETH_INSP_MAX_NUM_DREGS) begin - eth_insp_state <= ETH_INSP_WRITE_DSP_LIVE; - eth_insp_dreg_count <= 0; + com_insp_dreg_count <= com_insp_dreg_count_next; + if (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS) begin + com_insp_state <= COM_INSP_WRITE_DSP_LIVE; + com_insp_dreg_count <= 0; end end end - ETH_INSP_WRITE_DSP_LIVE: begin - if (dsp_out_ready & dsp_out_valid & eth_inp_data[33]) begin - eth_insp_state <= ETH_INSP_READ_ETH_PRE; + COM_INSP_WRITE_DSP_LIVE: begin + if (dsp_out_ready & dsp_out_valid & com_inp_data[33]) begin + com_insp_state <= COM_INSP_READ_COM_PRE; end end - ETH_INSP_WRITE_CPU_REGS: begin + COM_INSP_WRITE_CPU_REGS: begin if (cpu_inp_ready & cpu_inp_valid) begin - eth_insp_dreg_count <= eth_insp_dreg_count_next; + com_insp_dreg_count <= com_insp_dreg_count_next; if (cpu_inp_data[33]) begin - eth_insp_state <= ETH_INSP_READ_ETH_PRE; - eth_insp_dreg_count <= 0; + com_insp_state <= COM_INSP_READ_COM_PRE; + com_insp_dreg_count <= 0; end - else if (eth_insp_dreg_count_next == ETH_INSP_MAX_NUM_DREGS) begin - eth_insp_state <= ETH_INSP_WRITE_CPU_LIVE; - eth_insp_dreg_count <= 0; + else if (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS) begin + com_insp_state <= COM_INSP_WRITE_CPU_LIVE; + com_insp_dreg_count <= 0; end end end - ETH_INSP_WRITE_CPU_LIVE: begin - if (cpu_inp_ready & cpu_inp_valid & eth_inp_data[33]) begin - eth_insp_state <= ETH_INSP_READ_ETH_PRE; + COM_INSP_WRITE_CPU_LIVE: begin + if (cpu_inp_ready & cpu_inp_valid & com_inp_data[33]) begin + com_insp_state <= COM_INSP_READ_COM_PRE; end end - endcase //eth_insp_state + endcase //com_insp_state end endmodule // packet_router -- cgit v1.2.3 From 4603d79f5d4a4a02a45ca8e4cef08ae76d6b874d Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 15 Nov 2010 17:53:57 -0800 Subject: packet_router: added all input/output signals to module, created the comm muxes (in and out) --- usrp2/fifo/packet_router.v | 25 +++++++++++++++++++------ usrp2/top/u2_rev3/u2_core_udp.v | 3 +++ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 031fe1c78..1590269f8 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -25,9 +25,12 @@ module packet_router output sys_int_o, //want an interrupt? // Input Interfaces (in to router) + input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready, + input [35:0] dsp_inp_data, input dsp_inp_valid, output dsp_inp_ready, input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready, // Output Interfaces (out of router) + output [35:0] ser_out_data, output ser_out_valid, input ser_out_ready, output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready, output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready ); @@ -80,19 +83,29 @@ module packet_router // Communication input source combiner // - combine streams from serdes and ethernet //////////////////////////////////////////////////////////////////// - //TODO: just connect eth input to com input for now - assign com_inp_data = eth_inp_data; - assign com_inp_valid = eth_inp_valid; - assign eth_inp_ready = com_inp_ready; + fifo36_mux com_input_source( + .clk(stream_clk), .rst(stream_rst), .clear(1'b0), + .data0_i(eth_inp_data), .src0_rdy_i(eth_inp_valid), .dst0_rdy_o(eth_inp_ready), + .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready), + .data_o(com_inp_data), .src_rdy_o(com_inp_valid), .dst_rdy_i(com_inp_ready) + ); //////////////////////////////////////////////////////////////////// // Communication output sink demuxer // - demux the stream to serdes or ethernet //////////////////////////////////////////////////////////////////// - //TODO: just connect eth output to com output for now + wire eth_link_is_up = 1'b1; //TODO should come from input or register + + //connect the ethernet output signals assign eth_out_data = com_out_data; assign eth_out_valid = com_out_valid; - assign com_out_ready = eth_out_ready; + + //connect the serdes output signals + assign ser_out_data = com_out_data; + assign ser_out_valid = com_out_valid; + + //mux the com signal from the ethernet link + assign com_out_ready = (eth_link_is_up)? eth_out_ready : ser_out_ready; //////////////////////////////////////////////////////////////////// // Communication output source combiner diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index d2932d0fc..d8c56e234 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -375,8 +375,11 @@ module u2_core .control(router_control), .status(status), .sys_int_o(buffer_int), + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), .dsp_out_data({rd0_flags, rd0_dat}), .dsp_out_valid(rd0_ready_o), .dsp_out_ready(rd0_ready_i), + .ser_out_data({rd1_flags, rd1_dat}), .ser_out_valid(rd1_ready_o), .ser_out_ready(rd1_ready_i), .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); -- cgit v1.2.3 From 8b0e11fe0d0794d05c9e111b53a14b55499bbc54 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 15 Nov 2010 19:09:20 -0800 Subject: packet_router: some tweaks, dsp output routing seems to work but has wrong offset --- usrp2/fifo/packet_router.v | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 1590269f8..6f0de3164 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -84,7 +84,7 @@ module packet_router // - combine streams from serdes and ethernet //////////////////////////////////////////////////////////////////// fifo36_mux com_input_source( - .clk(stream_clk), .rst(stream_rst), .clear(1'b0), + .clk(stream_clk), .reset(stream_rst), .clear(1'b0), .data0_i(eth_inp_data), .src0_rdy_i(eth_inp_valid), .dst0_rdy_o(eth_inp_ready), .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready), .data_o(com_inp_data), .src_rdy_o(com_inp_valid), .dst_rdy_i(com_inp_ready) @@ -268,16 +268,22 @@ module packet_router localparam COM_INSP_WRITE_DSP_LIVE = 3; localparam COM_INSP_WRITE_CPU_REGS = 4; localparam COM_INSP_WRITE_CPU_LIVE = 5; + //FIXME collapse the write dsp/cpu states and use another register - localparam COM_INSP_MAX_NUM_DREGS = 12; //padded_eth + ip + udp + vrt_hdr lines - localparam COM_INSP_DREGS_DSP_OFFSET = 10; //offset to start dsp at + localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + vrt_hdr + extra cycle + localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at reg [2:0] com_insp_state; reg [3:0] com_insp_dreg_count; //data registers to buffer headers wire [3:0] com_insp_dreg_count_next = com_insp_dreg_count + 1'b1; reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0]; - wire com_inp_dregs_is_data = 1'b0; //TODO (not data for now) + wire com_inp_dregs_is_data = 1'b1 //FIXME bit inspection is wrong (representation) + & (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 + & (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP + & (com_insp_dregs[9][15:0] == 16'd49153) //UDP data port + & (com_insp_dregs[11][31:0] != 32'h0) //VRT hdr non-zero + ; ///////////////////////////////////// //assign output signals to CPU input -- cgit v1.2.3 From ef7368a1f3595a3be6795ef743a4cbb062a7dcaa Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 16 Nov 2010 09:13:40 -0800 Subject: packet_router: collapsed inspector states, fixed terminology for cpu inp vs out --- usrp2/fifo/packet_router.v | 324 ++++++++++++++++++++++----------------------- 1 file changed, 161 insertions(+), 163 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 6f0de3164..6f1df6540 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -66,18 +66,18 @@ module packet_router //////////////////////////////////////////////////////////////////// // status and control handshakes //////////////////////////////////////////////////////////////////// - wire cpu_inp_hs_ctrl = control[0]; - wire cpu_out_hs_ctrl = control[1]; - wire [BUF_SIZE-1:0] cpu_out_line_count = control[BUF_SIZE-1+16:0+16]; + wire cpu_out_hs_ctrl = control[0]; + wire cpu_inp_hs_ctrl = control[1]; + wire [BUF_SIZE-1:0] cpu_inp_line_count = control[BUF_SIZE-1+16:0+16]; - wire cpu_inp_hs_stat; - assign status[0] = cpu_inp_hs_stat; + wire cpu_out_hs_stat; + assign status[0] = cpu_out_hs_stat; - wire [BUF_SIZE-1:0] cpu_inp_line_count; - assign status[BUF_SIZE-1+16:0+16] = cpu_inp_line_count; + wire [BUF_SIZE-1:0] cpu_out_line_count; + assign status[BUF_SIZE-1+16:0+16] = cpu_out_line_count; - wire cpu_out_hs_stat; - assign status[1] = cpu_out_hs_stat; + wire cpu_inp_hs_stat; + assign status[1] = cpu_inp_hs_stat; //////////////////////////////////////////////////////////////////// // Communication input source combiner @@ -112,238 +112,251 @@ module packet_router // - combine streams from dsp framer, com inspector, and cpu //////////////////////////////////////////////////////////////////// //TODO: just connect com output to cpu output for now - assign com_out_data = cpu_out_data; - assign com_out_valid = cpu_out_valid; - assign cpu_out_ready = com_out_ready; + assign com_out_data = cpu_inp_data; + assign com_out_valid = cpu_inp_valid; + assign cpu_inp_ready = com_out_ready; //////////////////////////////////////////////////////////////////// - // Interface CPU input interface to memory mapped wishbone + // Interface CPU output to memory mapped wishbone //////////////////////////////////////////////////////////////////// - localparam CPU_INP_STATE_WAIT_SOF = 0; - localparam CPU_INP_STATE_WAIT_EOF = 1; - localparam CPU_INP_STATE_WAIT_CTRL_HI = 2; - localparam CPU_INP_STATE_WAIT_CTRL_LO = 3; + localparam CPU_OUT_STATE_WAIT_SOF = 0; + localparam CPU_OUT_STATE_WAIT_EOF = 1; + localparam CPU_OUT_STATE_WAIT_CTRL_HI = 2; + localparam CPU_OUT_STATE_WAIT_CTRL_LO = 3; - reg [1:0] cpu_inp_state; - reg [BUF_SIZE-1:0] cpu_inp_addr; - assign cpu_inp_line_count = cpu_inp_addr; - wire [BUF_SIZE-1:0] cpu_inp_addr_next = cpu_inp_addr + 1'b1; + reg [1:0] cpu_out_state; + reg [BUF_SIZE-1:0] cpu_out_addr; + assign cpu_out_line_count = cpu_out_addr; + wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1; - wire cpu_inp_reading = ( - cpu_inp_state == CPU_INP_STATE_WAIT_SOF || - cpu_inp_state == CPU_INP_STATE_WAIT_EOF + wire cpu_out_reading = ( + cpu_out_state == CPU_OUT_STATE_WAIT_SOF || + cpu_out_state == CPU_OUT_STATE_WAIT_EOF )? 1'b1 : 1'b0; - wire cpu_inp_we = cpu_inp_reading; - assign cpu_inp_ready = cpu_inp_reading; - assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; + wire cpu_out_we = cpu_out_reading; + assign cpu_out_ready = cpu_out_reading; + assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; - RAMB16_S36_S36 cpu_inp_buff( + RAMB16_S36_S36 cpu_out_buff( //port A = wishbone memory mapped address space (output only) .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0), .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i), //port B = packet router interface to CPU (input only) - .DOB(),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(cpu_inp_data),.DIPB(4'h0), - .ENB(cpu_inp_we),.SSRB(0),.WEB(cpu_inp_we) + .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data),.DIPB(4'h0), + .ENB(cpu_out_we),.SSRB(0),.WEB(cpu_out_we) ); always @(posedge stream_clk) if(stream_rst) begin - cpu_inp_state <= CPU_INP_STATE_WAIT_SOF; - cpu_inp_addr <= 0; + cpu_out_state <= CPU_OUT_STATE_WAIT_SOF; + cpu_out_addr <= 0; end else begin - case(cpu_inp_state) - CPU_INP_STATE_WAIT_SOF: begin - if (cpu_inp_ready & cpu_inp_valid & (cpu_inp_data[32] == 1'b1)) begin - cpu_inp_state <= CPU_INP_STATE_WAIT_EOF; - cpu_inp_addr <= cpu_inp_addr_next; + case(cpu_out_state) + CPU_OUT_STATE_WAIT_SOF: begin + if (cpu_out_ready & cpu_out_valid & (cpu_out_data[32] == 1'b1)) begin + cpu_out_state <= CPU_OUT_STATE_WAIT_EOF; + cpu_out_addr <= cpu_out_addr_next; end end - CPU_INP_STATE_WAIT_EOF: begin - if (cpu_inp_ready & cpu_inp_valid & (cpu_inp_data[33] == 1'b1)) begin - cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; + CPU_OUT_STATE_WAIT_EOF: begin + if (cpu_out_ready & cpu_out_valid & (cpu_out_data[33] == 1'b1)) begin + cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI; end - if (cpu_inp_ready & cpu_inp_valid) begin - cpu_inp_addr <= cpu_inp_addr_next; + if (cpu_out_ready & cpu_out_valid) begin + cpu_out_addr <= cpu_out_addr_next; end end - CPU_INP_STATE_WAIT_CTRL_HI: begin - if (cpu_inp_hs_ctrl == 1'b1) begin - cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_LO; + CPU_OUT_STATE_WAIT_CTRL_HI: begin + if (cpu_out_hs_ctrl == 1'b1) begin + cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_LO; end end - CPU_INP_STATE_WAIT_CTRL_LO: begin - if (cpu_inp_hs_ctrl == 1'b0) begin - cpu_inp_state <= CPU_INP_STATE_WAIT_SOF; + CPU_OUT_STATE_WAIT_CTRL_LO: begin + if (cpu_out_hs_ctrl == 1'b0) begin + cpu_out_state <= CPU_OUT_STATE_WAIT_SOF; end - cpu_inp_addr <= 0; //reset the address counter + cpu_out_addr <= 0; //reset the address counter end - endcase //cpu_inp_state + endcase //cpu_out_state end //////////////////////////////////////////////////////////////////// - // Interface CPU output interface to memory mapped wishbone + // Interface CPU input to memory mapped wishbone //////////////////////////////////////////////////////////////////// - localparam CPU_OUT_STATE_WAIT_CTRL_HI = 0; - localparam CPU_OUT_STATE_WAIT_CTRL_LO = 1; - localparam CPU_OUT_STATE_UNLOAD = 2; + localparam CPU_INP_STATE_WAIT_CTRL_HI = 0; + localparam CPU_INP_STATE_WAIT_CTRL_LO = 1; + localparam CPU_INP_STATE_UNLOAD = 2; - reg [1:0] cpu_out_state; - reg [BUF_SIZE-1:0] cpu_out_addr; - wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1; + reg [1:0] cpu_inp_state; + reg [BUF_SIZE-1:0] cpu_inp_addr; + wire [BUF_SIZE-1:0] cpu_inp_addr_next = cpu_inp_addr + 1'b1; - reg [BUF_SIZE-1:0] cpu_out_line_count_reg; + reg [BUF_SIZE-1:0] cpu_inp_line_count_reg; - reg cpu_out_flag_sof; - reg cpu_out_flag_eof; - assign cpu_out_data[35:32] = {2'b0, cpu_out_flag_eof, cpu_out_flag_sof}; + reg cpu_inp_flag_sof; + reg cpu_inp_flag_eof; + assign cpu_inp_data[35:32] = {2'b0, cpu_inp_flag_eof, cpu_inp_flag_sof}; - assign cpu_out_valid = (cpu_out_state == CPU_OUT_STATE_UNLOAD)? 1'b1 : 1'b0; - assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; + assign cpu_inp_valid = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? 1'b1 : 1'b0; + assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; - RAMB16_S36_S36 cpu_out_buff( + RAMB16_S36_S36 cpu_inp_buff( //port A = wishbone memory mapped address space (input only) .DOA(),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), .ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i), //port B = packet router interface from CPU (output only) - .DOB(cpu_out_data[31:0]),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), + .DOB(cpu_inp_data[31:0]),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), .ENB(1'b1),.SSRB(0),.WEB(1'b0) ); always @(posedge stream_clk) if(stream_rst) begin - cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI; - cpu_out_addr <= 0; + cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; + cpu_inp_addr <= 0; end else begin - case(cpu_out_state) - CPU_OUT_STATE_WAIT_CTRL_HI: begin - if (cpu_out_hs_ctrl == 1'b1) begin - cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_LO; + case(cpu_inp_state) + CPU_INP_STATE_WAIT_CTRL_HI: begin + if (cpu_inp_hs_ctrl == 1'b1) begin + cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_LO; end - cpu_out_line_count_reg <= cpu_out_line_count; - cpu_out_addr <= 0; //reset the address counter + cpu_inp_line_count_reg <= cpu_inp_line_count; + cpu_inp_addr <= 0; //reset the address counter end - CPU_OUT_STATE_WAIT_CTRL_LO: begin - if (cpu_out_hs_ctrl == 1'b0) begin - cpu_out_state <= CPU_OUT_STATE_UNLOAD; - cpu_out_addr <= cpu_out_addr_next; + CPU_INP_STATE_WAIT_CTRL_LO: begin + if (cpu_inp_hs_ctrl == 1'b0) begin + cpu_inp_state <= CPU_INP_STATE_UNLOAD; + cpu_inp_addr <= cpu_inp_addr_next; end - cpu_out_flag_sof <= 1'b1; - cpu_out_flag_eof <= 1'b0; + cpu_inp_flag_sof <= 1'b1; + cpu_inp_flag_eof <= 1'b0; end - CPU_OUT_STATE_UNLOAD: begin - if (cpu_out_ready & cpu_out_valid) begin - cpu_out_addr <= cpu_out_addr_next; - cpu_out_flag_sof <= 1'b0; - if (cpu_out_addr == cpu_out_line_count_reg) begin - cpu_out_flag_eof <= 1'b1; + CPU_INP_STATE_UNLOAD: begin + if (cpu_inp_ready & cpu_inp_valid) begin + cpu_inp_addr <= cpu_inp_addr_next; + cpu_inp_flag_sof <= 1'b0; + if (cpu_inp_addr == cpu_inp_line_count_reg) begin + cpu_inp_flag_eof <= 1'b1; end else begin - cpu_out_flag_eof <= 1'b0; + cpu_inp_flag_eof <= 1'b0; end - if (cpu_out_flag_eof) begin - cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI; + if (cpu_inp_flag_eof) begin + cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; end end end - endcase //cpu_out_state + endcase //cpu_inp_state end //////////////////////////////////////////////////////////////////// // Communication input inspector // - inspect com input and send it to CPU, DSP, or COM //////////////////////////////////////////////////////////////////// - localparam COM_INSP_READ_COM_PRE = 0; - localparam COM_INSP_READ_COM = 1; - localparam COM_INSP_WRITE_DSP_REGS = 2; - localparam COM_INSP_WRITE_DSP_LIVE = 3; - localparam COM_INSP_WRITE_CPU_REGS = 4; - localparam COM_INSP_WRITE_CPU_LIVE = 5; - //FIXME collapse the write dsp/cpu states and use another register - - localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + vrt_hdr + extra cycle + localparam COM_INSP_STATE_READ_COM_PRE = 0; + localparam COM_INSP_STATE_READ_COM = 1; + localparam COM_INSP_STATE_WRITE_REGS = 2; + localparam COM_INSP_STATE_WRITE_LIVE = 3; + + localparam COM_INSP_DEST_DSP = 0; + localparam COM_INSP_DEST_COM = 1; + localparam COM_INSP_DEST_CPU = 2; + + localparam COM_INSP_MAX_NUM_DREGS = 12; //padded_eth + ip + udp + vrt_hdr localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at - reg [2:0] com_insp_state; + reg [1:0] com_insp_state; + reg [1:0] com_insp_dest; reg [3:0] com_insp_dreg_count; //data registers to buffer headers wire [3:0] com_insp_dreg_count_next = com_insp_dreg_count + 1'b1; + wire com_insp_dreg_counter_done = (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)? 1'b1 : 1'b0; reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0]; - wire com_inp_dregs_is_data = 1'b1 //FIXME bit inspection is wrong (representation) + //Inspection logic: + wire com_inp_dregs_is_data = 1'b1 & (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 & (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP & (com_insp_dregs[9][15:0] == 16'd49153) //UDP data port - & (com_insp_dregs[11][31:0] != 32'h0) //VRT hdr non-zero + & (com_inp_data[31:0] != 32'h0) //VRT hdr non-zero ; - ///////////////////////////////////// - //assign output signals to CPU input - ///////////////////////////////////// - assign cpu_inp_data = (com_insp_state == COM_INSP_WRITE_CPU_REGS)? - com_insp_dregs[com_insp_dreg_count] : com_inp_data + //Inspector output flags special case: + //Inject SOF into flags at first DSP line. + wire [3:0] com_insp_out_flags = ((com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) & (com_insp_dest == COM_INSP_DEST_DSP))? + 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32] ; - assign cpu_inp_valid = - (com_insp_state == COM_INSP_WRITE_CPU_REGS)? 1'b1 : ( - (com_insp_state == COM_INSP_WRITE_CPU_LIVE)? com_inp_valid : ( - 1'b0)); - ///////////////////////////////////// - //assign output signals to DSP output - ///////////////////////////////////// - wire [3:0] com_insp_dsp_flags = (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET)? - 4'b0001 : 4'b0000 - ; - assign dsp_out_data = (com_insp_state == COM_INSP_WRITE_DSP_REGS)? - {com_insp_dsp_flags, com_insp_dregs[com_insp_dreg_count][31:0]} : com_inp_data + //The communication inspector ouput data and valid signals: + //Mux between com input and data registers based on the state. + wire [35:0] com_insp_out_data = (com_insp_state == COM_INSP_STATE_WRITE_REGS)? + {com_insp_out_flags, com_insp_dregs[com_insp_dreg_count][31:0]} : com_inp_data ; - assign dsp_out_valid = - (com_insp_state == COM_INSP_WRITE_DSP_REGS)? 1'b1 : ( - (com_insp_state == COM_INSP_WRITE_DSP_LIVE)? com_inp_valid : ( + wire com_insp_out_valid = + (com_insp_state == COM_INSP_STATE_WRITE_REGS)? 1'b1 : ( + (com_insp_state == COM_INSP_STATE_WRITE_LIVE)? com_inp_valid : ( 1'b0)); - ///////////////////////////////////// - //assign output signal to COM input - ///////////////////////////////////// + //The communication inspector ouput ready signal: + //Mux between the various destination ready signals. + wire com_insp_out_ready = + (com_insp_dest == COM_INSP_DEST_CPU)? cpu_out_ready : ( + (com_insp_dest == COM_INSP_DEST_DSP)? dsp_out_ready : ( + 1'b0)); + + //Always connected output data lines. + assign cpu_out_data = com_insp_out_data; + assign dsp_out_data = com_insp_out_data; + + //Destination output valid signals: + //Comes from inspector valid when destination is selected, and otherwise low. + assign cpu_out_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0; + assign dsp_out_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0; + + //The communication inspector ouput ready signal: + //Always ready when storing to data registers, + //comes from inspector ready output when live, + //and otherwise low. assign com_inp_ready = - (com_insp_state == COM_INSP_READ_COM_PRE) ? 1'b1 : ( - (com_insp_state == COM_INSP_READ_COM) ? 1'b1 : ( - (com_insp_state == COM_INSP_WRITE_DSP_LIVE)? dsp_out_ready : ( - (com_insp_state == COM_INSP_WRITE_CPU_LIVE)? cpu_inp_ready : ( - 1'b0)))); + (com_insp_state == COM_INSP_STATE_READ_COM_PRE) ? 1'b1 : ( + (com_insp_state == COM_INSP_STATE_READ_COM) ? 1'b1 : ( + (com_insp_state == COM_INSP_STATE_WRITE_LIVE) ? com_insp_out_ready : ( + 1'b0))); always @(posedge stream_clk) if(stream_rst) begin - com_insp_state <= COM_INSP_READ_COM_PRE; + com_insp_state <= COM_INSP_STATE_READ_COM_PRE; com_insp_dreg_count <= 0; end else begin case(com_insp_state) - COM_INSP_READ_COM_PRE: begin + COM_INSP_STATE_READ_COM_PRE: begin if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin - com_insp_state <= COM_INSP_READ_COM; + com_insp_state <= COM_INSP_STATE_READ_COM; com_insp_dreg_count <= com_insp_dreg_count_next; com_insp_dregs[com_insp_dreg_count] <= com_inp_data; end end - COM_INSP_READ_COM: begin + COM_INSP_STATE_READ_COM: begin if (com_inp_ready & com_inp_valid) begin com_insp_dregs[com_insp_dreg_count] <= com_inp_data; - if (com_inp_dregs_is_data & (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)) begin - com_insp_state <= COM_INSP_WRITE_DSP_REGS; + if (com_inp_dregs_is_data & com_insp_dreg_counter_done) begin + com_insp_dest <= COM_INSP_DEST_DSP; + com_insp_state <= COM_INSP_STATE_WRITE_REGS; com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; end - else if (com_inp_data[33] | (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)) begin - com_insp_state <= COM_INSP_WRITE_CPU_REGS; + else if (com_inp_data[33] | com_insp_dreg_counter_done) begin + com_insp_dest <= COM_INSP_DEST_CPU; + com_insp_state <= COM_INSP_STATE_WRITE_REGS; com_insp_dreg_count <= 0; end else begin @@ -352,40 +365,25 @@ module packet_router end end - COM_INSP_WRITE_DSP_REGS: begin - if (dsp_out_ready & dsp_out_valid) begin - com_insp_dreg_count <= com_insp_dreg_count_next; - if (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS) begin - com_insp_state <= COM_INSP_WRITE_DSP_LIVE; + COM_INSP_STATE_WRITE_REGS: begin + if (com_insp_out_ready & com_insp_out_valid) begin + if (com_insp_out_data[33]) begin + com_insp_state <= COM_INSP_STATE_READ_COM_PRE; com_insp_dreg_count <= 0; end - end - - end - - COM_INSP_WRITE_DSP_LIVE: begin - if (dsp_out_ready & dsp_out_valid & com_inp_data[33]) begin - com_insp_state <= COM_INSP_READ_COM_PRE; - end - end - - COM_INSP_WRITE_CPU_REGS: begin - if (cpu_inp_ready & cpu_inp_valid) begin - com_insp_dreg_count <= com_insp_dreg_count_next; - if (cpu_inp_data[33]) begin - com_insp_state <= COM_INSP_READ_COM_PRE; + else if (com_insp_dreg_counter_done) begin + com_insp_state <= COM_INSP_STATE_WRITE_LIVE; com_insp_dreg_count <= 0; end - else if (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS) begin - com_insp_state <= COM_INSP_WRITE_CPU_LIVE; - com_insp_dreg_count <= 0; + else begin + com_insp_dreg_count <= com_insp_dreg_count_next; end end end - COM_INSP_WRITE_CPU_LIVE: begin - if (cpu_inp_ready & cpu_inp_valid & com_inp_data[33]) begin - com_insp_state <= COM_INSP_READ_COM_PRE; + COM_INSP_STATE_WRITE_LIVE: begin + if (com_insp_out_ready & com_insp_out_valid & com_insp_out_data[33]) begin + com_insp_state <= COM_INSP_STATE_READ_COM_PRE; end end -- cgit v1.2.3 From bba4d1172d0d2111f5e24e5b4b54d2b05e0c318e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 16 Nov 2010 11:00:44 -0800 Subject: packet_router: fixed swapped connection typo, dsp tx routing works --- usrp2/top/u2_rev3/u2_core_udp.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index d8c56e234..ba4e86f60 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -378,8 +378,9 @@ module u2_core .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .dsp_out_data({rd0_flags, rd0_dat}), .dsp_out_valid(rd0_ready_o), .dsp_out_ready(rd0_ready_i), - .ser_out_data({rd1_flags, rd1_dat}), .ser_out_valid(rd1_ready_o), .ser_out_ready(rd1_ready_i), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); -- cgit v1.2.3 From 5fac09e582e6aa02669dc63a6f79e8be5df3dc49 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 16 Nov 2010 16:22:36 -0800 Subject: packet_router: added lines for com crossbar and com output mux --- usrp2/fifo/packet_router.v | 48 +++++++++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 6f1df6540..095dcd55d 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -91,30 +91,50 @@ module packet_router ); //////////////////////////////////////////////////////////////////// - // Communication output sink demuxer - // - demux the stream to serdes or ethernet + // Communication output sink crossbar + // - when the link is up (master): com -> eth and insp -> serdes + // - when the link is down (slave): com -> serdes (insp disconnected) //////////////////////////////////////////////////////////////////// wire eth_link_is_up = 1'b1; //TODO should come from input or register - //connect the ethernet output signals + //streaming signals from the inspector to the crossbar + wire [35:0] ser_crs_data; + wire ser_crs_valid; + wire ser_crs_ready; + + //connect the ethernet source output signals assign eth_out_data = com_out_data; - assign eth_out_valid = com_out_valid; + assign eth_out_valid = (eth_link_is_up)? com_out_valid : 1'b0; - //connect the serdes output signals - assign ser_out_data = com_out_data; - assign ser_out_valid = com_out_valid; + //connect the serdes source output signals + assign ser_out_data = (eth_link_is_up)? ser_crs_data : com_out_data; + assign ser_out_valid = (eth_link_is_up)? ser_crs_valid : com_out_valid; - //mux the com signal from the ethernet link + //connect the crossbar sink output signals assign com_out_ready = (eth_link_is_up)? eth_out_ready : ser_out_ready; + assign ser_crs_ready = (eth_link_is_up)? ser_out_ready : 1'b1/*null sink*/; //////////////////////////////////////////////////////////////////// // Communication output source combiner // - combine streams from dsp framer, com inspector, and cpu //////////////////////////////////////////////////////////////////// - //TODO: just connect com output to cpu output for now - assign com_out_data = cpu_inp_data; - assign com_out_valid = cpu_inp_valid; - assign cpu_inp_ready = com_out_ready; + + //streaming signals from the dsp framer to the com mux + wire [35:0] dsp_frm_data; + wire dsp_frm_valid; + wire dsp_frm_ready; + + //TODO: tmp connect to dsp inp until we make the framer + assign dsp_frm_data = dsp_inp_data; + assign dsp_frm_valid = dsp_inp_valid; + assign dsp_inp_ready = dsp_frm_ready; + + fifo36_mux com_output_source( + .clk(stream_clk), .reset(stream_rst), .clear(1'b0), + .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready), + .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), + .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) + ); //////////////////////////////////////////////////////////////////// // Interface CPU output to memory mapped wishbone @@ -268,7 +288,7 @@ module packet_router localparam COM_INSP_STATE_WRITE_LIVE = 3; localparam COM_INSP_DEST_DSP = 0; - localparam COM_INSP_DEST_COM = 1; + localparam COM_INSP_DEST_SER = 1; localparam COM_INSP_DEST_CPU = 2; localparam COM_INSP_MAX_NUM_DREGS = 12; //padded_eth + ip + udp + vrt_hdr @@ -315,11 +335,13 @@ module packet_router //Always connected output data lines. assign cpu_out_data = com_insp_out_data; assign dsp_out_data = com_insp_out_data; + assign ser_crs_data = com_insp_out_data; //Destination output valid signals: //Comes from inspector valid when destination is selected, and otherwise low. assign cpu_out_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0; assign dsp_out_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0; + assign ser_crs_valid = (com_insp_dest == COM_INSP_DEST_SER)? com_insp_out_valid : 1'b0; //The communication inspector ouput ready signal: //Always ready when storing to data registers, -- cgit v1.2.3 From 588ea68755cfc48b78532420016d8d080c09380a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 17 Nov 2010 11:38:01 -0800 Subject: packet_router: created dsp framer for rx path --- usrp2/fifo/packet_router.v | 106 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 100 insertions(+), 6 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 095dcd55d..0c79c200d 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -124,11 +124,6 @@ module packet_router wire dsp_frm_valid; wire dsp_frm_ready; - //TODO: tmp connect to dsp inp until we make the framer - assign dsp_frm_data = dsp_inp_data; - assign dsp_frm_valid = dsp_inp_valid; - assign dsp_inp_ready = dsp_frm_ready; - fifo36_mux com_output_source( .clk(stream_clk), .reset(stream_rst), .clear(1'b0), .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready), @@ -253,7 +248,7 @@ module packet_router CPU_INP_STATE_WAIT_CTRL_LO: begin if (cpu_inp_hs_ctrl == 1'b0) begin cpu_inp_state <= CPU_INP_STATE_UNLOAD; - cpu_inp_addr <= cpu_inp_addr_next; + cpu_inp_addr <= cpu_inp_addr_next; //BRAM has a setup delay and this is a bug end cpu_inp_flag_sof <= 1'b1; cpu_inp_flag_eof <= 1'b0; @@ -412,4 +407,103 @@ module packet_router endcase //com_insp_state end + //////////////////////////////////////////////////////////////////// + // DSP input framer + // - add a 1-line frame header to each DSP input packet + // - each header is composed of a byte count and flags + //////////////////////////////////////////////////////////////////// + + localparam DSP_FRM_STATE_WAIT_SOF = 0; + localparam DSP_FRM_STATE_WAIT_EOF = 1; + localparam DSP_FRM_STATE_WRITE_HDR = 2; + localparam DSP_FRM_STATE_WRITE = 3; + + reg [1:0] dsp_frm_state; + reg [BUF_SIZE-1:0] dsp_frm_addr; + reg [BUF_SIZE-1:0] dsp_frm_count; + wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1; + reg dsp_frm_valid_reg; //registered valid to deal with read delay + + //DSP input stream ready in the following states + assign dsp_inp_ready = + (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : ( + (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : ( + 1'b0)); + + //DSP framer output data mux (header or BRAM): + //The header is generated here from the count. + wire [31:0] dsp_frm_data_bram; + wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; + assign dsp_frm_data = + (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( + (dsp_frm_addr_next == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( + {4'b0000, dsp_frm_data_bram})); + assign dsp_frm_valid = dsp_frm_valid_reg; + + RAMB16_S36_S36 dsp_frm_buff( + //port A = DSP input interface (writes to BRAM) + .DOA(),.ADDRA(dsp_frm_addr),.CLKA(stream_clk),.DIA(dsp_inp_data[31:0]),.DIPA(4'h0), + .ENA(dsp_inp_ready),.SSRA(0),.WEA(dsp_inp_ready), + //port B = DSP framer interface (reads from BRAM) + .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), + .ENB(1'b1),.SSRB(0),.WEB(1'b0) + ); + + always @(posedge stream_clk) + if(stream_rst) begin + dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; + dsp_frm_addr <= 0; + dsp_frm_valid_reg <= 1'b0; + end + else begin + case(dsp_frm_state) + DSP_FRM_STATE_WAIT_SOF: begin + if (dsp_inp_ready & dsp_inp_valid & dsp_inp_data[32]) begin + dsp_frm_addr <= dsp_frm_addr_next; + dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF; + end + end + + DSP_FRM_STATE_WAIT_EOF: begin + if (dsp_inp_ready & dsp_inp_valid) begin + if (dsp_inp_data[33]) begin + dsp_frm_count <= dsp_frm_addr_next; + dsp_frm_addr <= 0; + dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR; + end + else begin + dsp_frm_addr <= dsp_frm_addr_next; + end + end + end + + DSP_FRM_STATE_WRITE_HDR: begin + if (dsp_frm_ready & dsp_frm_valid) begin + dsp_frm_addr <= 0; + dsp_frm_state <= DSP_FRM_STATE_WRITE; + dsp_frm_valid_reg <= 1'b0; + end + else begin + dsp_frm_valid_reg <= 1'b1; + end + end + + DSP_FRM_STATE_WRITE: begin + if (dsp_frm_ready & dsp_frm_valid) begin + if (dsp_frm_data[33]) begin + dsp_frm_addr <= 0; + dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; + end + else begin + dsp_frm_addr <= dsp_frm_addr_next; + end + dsp_frm_valid_reg <= 1'b0; + end + else begin + dsp_frm_valid_reg <= 1'b1; + end + end + endcase //dsp_frm_state + end + endmodule // packet_router -- cgit v1.2.3 From b47cfc1feac92730b4cfe16cf4ee2c6d6f8d27c0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 17 Nov 2010 12:22:28 -0800 Subject: packet_router: used registered valid signal for BRAM read cycle delay --- usrp2/fifo/packet_router.v | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 0c79c200d..e8673b065 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -214,11 +214,13 @@ module packet_router reg [BUF_SIZE-1:0] cpu_inp_line_count_reg; - reg cpu_inp_flag_sof; - reg cpu_inp_flag_eof; - assign cpu_inp_data[35:32] = {2'b0, cpu_inp_flag_eof, cpu_inp_flag_sof}; + assign cpu_inp_data[35:32] = + (cpu_inp_addr == 0 )? 4'b0001 : ( + (cpu_inp_addr_next == cpu_inp_line_count_reg)? 4'b0010 : ( + 4'b0000)); - assign cpu_inp_valid = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? 1'b1 : 1'b0; + reg cpu_inp_valid_reg; + assign cpu_inp_valid = cpu_inp_valid_reg; assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; RAMB16_S36_S36 cpu_inp_buff( @@ -234,6 +236,7 @@ module packet_router if(stream_rst) begin cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; cpu_inp_addr <= 0; + cpu_inp_valid_reg <= 1'b0; end else begin case(cpu_inp_state) @@ -242,31 +245,27 @@ module packet_router cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_LO; end cpu_inp_line_count_reg <= cpu_inp_line_count; - cpu_inp_addr <= 0; //reset the address counter end CPU_INP_STATE_WAIT_CTRL_LO: begin if (cpu_inp_hs_ctrl == 1'b0) begin cpu_inp_state <= CPU_INP_STATE_UNLOAD; - cpu_inp_addr <= cpu_inp_addr_next; //BRAM has a setup delay and this is a bug end - cpu_inp_flag_sof <= 1'b1; - cpu_inp_flag_eof <= 1'b0; end CPU_INP_STATE_UNLOAD: begin if (cpu_inp_ready & cpu_inp_valid) begin - cpu_inp_addr <= cpu_inp_addr_next; - cpu_inp_flag_sof <= 1'b0; - if (cpu_inp_addr == cpu_inp_line_count_reg) begin - cpu_inp_flag_eof <= 1'b1; + if (cpu_inp_data[33]) begin + cpu_inp_addr <= 0; + cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; end else begin - cpu_inp_flag_eof <= 1'b0; - end - if (cpu_inp_flag_eof) begin - cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; + cpu_inp_addr <= cpu_inp_addr_next; end + cpu_inp_valid_reg <= 1'b0; + end + else begin + cpu_inp_valid_reg <= 1'b1; end end -- cgit v1.2.3 From eb1dcd167d98fbcb3c3058ffa526e1364d34ac3e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 17 Nov 2010 15:04:33 -0800 Subject: packet_router: swapped comm mux for a crossbar, serdes crossbar out now muxed into the comm output --- usrp2/fifo/packet_router.v | 89 ++++++++++++++++++++++++++++++++-------------- 1 file changed, 62 insertions(+), 27 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index e8673b065..e8c6dd959 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -43,6 +43,8 @@ module packet_router //which buffer: 0 = CPU read buffer, 1 = CPU write buffer wire which_buf = wb_adr_i[BUF_SIZE+2]; + wire master_mode_flag = 1'b1; //TODO should come from input or register + //////////////////////////////////////////////////////////////////// // CPU interface to this packet router //////////////////////////////////////////////////////////////////// @@ -80,54 +82,87 @@ module packet_router assign status[1] = cpu_inp_hs_stat; //////////////////////////////////////////////////////////////////// - // Communication input source combiner - // - combine streams from serdes and ethernet + // Communication input source crossbar + // When in master mode: + // - serdes input -> comm output combiner + // - ethernet input -> comm input inspector + // When in slave mode: + // - serdes input -> comm input inspector + // - ethernet input -> null sink //////////////////////////////////////////////////////////////////// - fifo36_mux com_input_source( - .clk(stream_clk), .reset(stream_rst), .clear(1'b0), - .data0_i(eth_inp_data), .src0_rdy_i(eth_inp_valid), .dst0_rdy_o(eth_inp_ready), - .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready), - .data_o(com_inp_data), .src_rdy_o(com_inp_valid), .dst_rdy_i(com_inp_ready) - ); + + //streaming signals from the crossbar to the combiner + wire [35:0] crs_inp_data; + wire crs_inp_valid; + wire crs_inp_ready; + + //connect the com input signals + assign com_inp_data = (master_mode_flag)? eth_inp_data : ser_inp_data; + assign com_inp_valid = (master_mode_flag)? eth_inp_valid : ser_inp_valid; + + //connect the crossbar input signals + assign crs_inp_data = ser_inp_data; + assign crs_inp_valid = (master_mode_flag)? ser_inp_valid : 1'b0; + + //connect the crossbar ready signals + assign eth_inp_ready = (master_mode_flag)? com_inp_ready : 1'b1/*null sink*/; + assign ser_inp_ready = (master_mode_flag)? crs_inp_ready : eth_inp_ready; //////////////////////////////////////////////////////////////////// // Communication output sink crossbar - // - when the link is up (master): com -> eth and insp -> serdes - // - when the link is down (slave): com -> serdes (insp disconnected) + // When in master mode: + // - comm output -> ethernet output + // - insp output -> serdes output + // When in slave mode: + // - com output -> serdes output + // - insp output -> null sink //////////////////////////////////////////////////////////////////// - wire eth_link_is_up = 1'b1; //TODO should come from input or register //streaming signals from the inspector to the crossbar - wire [35:0] ser_crs_data; - wire ser_crs_valid; - wire ser_crs_ready; + wire [35:0] crs_out_data; + wire crs_out_valid; + wire crs_out_ready; - //connect the ethernet source output signals + //connect the ethernet output signals assign eth_out_data = com_out_data; - assign eth_out_valid = (eth_link_is_up)? com_out_valid : 1'b0; + assign eth_out_valid = (master_mode_flag)? com_out_valid : 1'b0; - //connect the serdes source output signals - assign ser_out_data = (eth_link_is_up)? ser_crs_data : com_out_data; - assign ser_out_valid = (eth_link_is_up)? ser_crs_valid : com_out_valid; + //connect the serdes output signals + assign ser_out_data = (master_mode_flag)? crs_out_data : com_out_data; + assign ser_out_valid = (master_mode_flag)? crs_out_valid : com_out_valid; - //connect the crossbar sink output signals - assign com_out_ready = (eth_link_is_up)? eth_out_ready : ser_out_ready; - assign ser_crs_ready = (eth_link_is_up)? ser_out_ready : 1'b1/*null sink*/; + //connect the crossbar ready signals + assign com_out_ready = (master_mode_flag)? eth_out_ready : ser_out_ready; + assign crs_out_ready = (master_mode_flag)? ser_out_ready : 1'b1/*null sink*/; //////////////////////////////////////////////////////////////////// // Communication output source combiner - // - combine streams from dsp framer, com inspector, and cpu + // - DSP framer + // - CPU input + // - Crossbar input //////////////////////////////////////////////////////////////////// - //streaming signals from the dsp framer to the com mux + //streaming signals from the dsp framer to the combiner wire [35:0] dsp_frm_data; wire dsp_frm_valid; wire dsp_frm_ready; - fifo36_mux com_output_source( + //dummy signals to join the the muxes below + wire [35:0] _combiner_data; + wire _combiner_valid; + wire _combiner_ready; + + fifo36_mux _com_output_source( .clk(stream_clk), .reset(stream_rst), .clear(1'b0), .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready), .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), + .data_o(_combiner_data), .src_rdy_o(_combiner_valid), .dst_rdy_i(_combiner_ready) + ); + + fifo36_mux com_output_source( + .clk(stream_clk), .reset(stream_rst), .clear(1'b0), + .data0_i(_combiner_data), .src0_rdy_i(_combiner_valid), .dst0_rdy_o(_combiner_ready), + .data1_i(crs_inp_data), .src1_rdy_i(crs_inp_valid), .dst1_rdy_o(crs_inp_ready), .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) ); @@ -329,13 +364,13 @@ module packet_router //Always connected output data lines. assign cpu_out_data = com_insp_out_data; assign dsp_out_data = com_insp_out_data; - assign ser_crs_data = com_insp_out_data; + assign crs_out_data = com_insp_out_data; //Destination output valid signals: //Comes from inspector valid when destination is selected, and otherwise low. assign cpu_out_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0; assign dsp_out_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0; - assign ser_crs_valid = (com_insp_dest == COM_INSP_DEST_SER)? com_insp_out_valid : 1'b0; + assign crs_out_valid = (com_insp_dest == COM_INSP_DEST_SER)? com_insp_out_valid : 1'b0; //The communication inspector ouput ready signal: //Always ready when storing to data registers, -- cgit v1.2.3 From ac40436a45c9568094dd6518a858793d0c76bd7e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 17 Nov 2010 16:43:53 -0800 Subject: packet_router: removed unused status words from readback mux --- usrp2/top/u2_rev3/u2_core_udp.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index ba4e86f60..1807f7e9a 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -163,7 +163,7 @@ module u2_core wire ram_loader_rst, wb_rst, dsp_rst; assign dsp_rst = wb_rst; - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire [31:0] status; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; @@ -433,8 +433,8 @@ module u2_core (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) ); -- cgit v1.2.3 From cab6fce99c429cf30946c4a2ace4083a0cd89267 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 17 Nov 2010 17:12:09 -0800 Subject: packet_router: use control register bit for master mode flag --- usrp2/fifo/packet_router.v | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index e8c6dd959..595ec2015 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -43,8 +43,6 @@ module packet_router //which buffer: 0 = CPU read buffer, 1 = CPU write buffer wire which_buf = wb_adr_i[BUF_SIZE+2]; - wire master_mode_flag = 1'b1; //TODO should come from input or register - //////////////////////////////////////////////////////////////////// // CPU interface to this packet router //////////////////////////////////////////////////////////////////// @@ -70,6 +68,7 @@ module packet_router //////////////////////////////////////////////////////////////////// wire cpu_out_hs_ctrl = control[0]; wire cpu_inp_hs_ctrl = control[1]; + wire master_mode_flag = control[2]; wire [BUF_SIZE-1:0] cpu_inp_line_count = control[BUF_SIZE-1+16:0+16]; wire cpu_out_hs_stat; -- cgit v1.2.3 From 4e5a340bb824b78d5101ed190eb688a300556df2 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 18 Nov 2010 12:54:40 -0800 Subject: packet_router: use BRAM enables to perform pipelined reads --- usrp2/fifo/packet_router.v | 47 +++++++++++++++++++++------------------------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 595ec2015..d78e48523 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -249,12 +249,11 @@ module packet_router reg [BUF_SIZE-1:0] cpu_inp_line_count_reg; assign cpu_inp_data[35:32] = - (cpu_inp_addr == 0 )? 4'b0001 : ( - (cpu_inp_addr_next == cpu_inp_line_count_reg)? 4'b0010 : ( + (cpu_inp_addr == 0 )? 4'b0001 : ( + (cpu_inp_addr == cpu_inp_line_count_reg)? 4'b0010 : ( 4'b0000)); - reg cpu_inp_valid_reg; - assign cpu_inp_valid = cpu_inp_valid_reg; + assign cpu_inp_valid = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? 1'b1 : 1'b0; assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; RAMB16_S36_S36 cpu_inp_buff( @@ -263,14 +262,13 @@ module packet_router .ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i), //port B = packet router interface from CPU (output only) .DOB(cpu_inp_data[31:0]),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), - .ENB(1'b1),.SSRB(0),.WEB(1'b0) + .ENB(cpu_inp_ready & cpu_inp_valid),.SSRB(0),.WEB(1'b0) ); always @(posedge stream_clk) if(stream_rst) begin cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; cpu_inp_addr <= 0; - cpu_inp_valid_reg <= 1'b0; end else begin case(cpu_inp_state) @@ -284,6 +282,7 @@ module packet_router CPU_INP_STATE_WAIT_CTRL_LO: begin if (cpu_inp_hs_ctrl == 1'b0) begin cpu_inp_state <= CPU_INP_STATE_UNLOAD; + cpu_inp_addr <= cpu_inp_addr_next; end end @@ -296,10 +295,6 @@ module packet_router else begin cpu_inp_addr <= cpu_inp_addr_next; end - cpu_inp_valid_reg <= 1'b0; - end - else begin - cpu_inp_valid_reg <= 1'b1; end end @@ -330,13 +325,15 @@ module packet_router reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0]; //Inspection logic: - wire com_inp_dregs_is_data = 1'b1 + wire com_inp_dregs_is_dsp = 1'b1 & (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 & (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP & (com_insp_dregs[9][15:0] == 16'd49153) //UDP data port & (com_inp_data[31:0] != 32'h0) //VRT hdr non-zero ; + wire com_inp_dregs_is_ser = 1'b0; + //Inspector output flags special case: //Inject SOF into flags at first DSP line. wire [3:0] com_insp_out_flags = ((com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) & (com_insp_dest == COM_INSP_DEST_DSP))? @@ -399,11 +396,16 @@ module packet_router COM_INSP_STATE_READ_COM: begin if (com_inp_ready & com_inp_valid) begin com_insp_dregs[com_insp_dreg_count] <= com_inp_data; - if (com_inp_dregs_is_data & com_insp_dreg_counter_done) begin + if (com_inp_dregs_is_dsp & com_insp_dreg_counter_done) begin com_insp_dest <= COM_INSP_DEST_DSP; com_insp_state <= COM_INSP_STATE_WRITE_REGS; com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; end + else if (com_inp_dregs_is_ser & com_insp_dreg_counter_done) begin + com_insp_dest <= COM_INSP_DEST_SER; + com_insp_state <= COM_INSP_STATE_WRITE_REGS; + com_insp_dreg_count <= 0; + end else if (com_inp_data[33] | com_insp_dreg_counter_done) begin com_insp_dest <= COM_INSP_DEST_CPU; com_insp_state <= COM_INSP_STATE_WRITE_REGS; @@ -455,7 +457,6 @@ module packet_router reg [BUF_SIZE-1:0] dsp_frm_addr; reg [BUF_SIZE-1:0] dsp_frm_count; wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1; - reg dsp_frm_valid_reg; //registered valid to deal with read delay //DSP input stream ready in the following states assign dsp_inp_ready = @@ -469,9 +470,12 @@ module packet_router wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; assign dsp_frm_data = (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( - (dsp_frm_addr_next == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( + (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( {4'b0000, dsp_frm_data_bram})); - assign dsp_frm_valid = dsp_frm_valid_reg; + assign dsp_frm_valid = ( + (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) | + (dsp_frm_state == DSP_FRM_STATE_WRITE) + )? 1'b1 : 1'b0; RAMB16_S36_S36 dsp_frm_buff( //port A = DSP input interface (writes to BRAM) @@ -479,14 +483,13 @@ module packet_router .ENA(dsp_inp_ready),.SSRA(0),.WEA(dsp_inp_ready), //port B = DSP framer interface (reads from BRAM) .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), - .ENB(1'b1),.SSRB(0),.WEB(1'b0) + .ENB(dsp_frm_ready & dsp_frm_valid),.SSRB(0),.WEB(1'b0) ); always @(posedge stream_clk) if(stream_rst) begin dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; dsp_frm_addr <= 0; - dsp_frm_valid_reg <= 1'b0; end else begin case(dsp_frm_state) @@ -512,12 +515,8 @@ module packet_router DSP_FRM_STATE_WRITE_HDR: begin if (dsp_frm_ready & dsp_frm_valid) begin - dsp_frm_addr <= 0; + dsp_frm_addr <= dsp_frm_addr_next; dsp_frm_state <= DSP_FRM_STATE_WRITE; - dsp_frm_valid_reg <= 1'b0; - end - else begin - dsp_frm_valid_reg <= 1'b1; end end @@ -530,10 +529,6 @@ module packet_router else begin dsp_frm_addr <= dsp_frm_addr_next; end - dsp_frm_valid_reg <= 1'b0; - end - else begin - dsp_frm_valid_reg <= 1'b1; end end endcase //dsp_frm_state -- cgit v1.2.3 From bc0a9958ea5b23d0b69d2493feeb662dc34ba9b9 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 18 Nov 2010 16:00:10 -0800 Subject: packet_router: renamed inspector output signals and connected (for now) to cpu, dsp, crs --- usrp2/fifo/Makefile.srcs | 1 + usrp2/fifo/packet_router.v | 73 ++++++++++++++++++++++++++++++++-------------- 2 files changed, 52 insertions(+), 22 deletions(-) diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs index acd25d807..61eb2c0c8 100644 --- a/usrp2/fifo/Makefile.srcs +++ b/usrp2/fifo/Makefile.srcs @@ -22,5 +22,6 @@ fifo36_to_fifo19.v \ fifo19_to_fifo36.v \ fifo36_mux.v \ fifo36_demux.v \ +fifo36_splitter.v \ packet_router.v \ )) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index d78e48523..96b7e9e07 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -310,13 +310,39 @@ module packet_router localparam COM_INSP_STATE_WRITE_REGS = 2; localparam COM_INSP_STATE_WRITE_LIVE = 3; - localparam COM_INSP_DEST_DSP = 0; - localparam COM_INSP_DEST_SER = 1; - localparam COM_INSP_DEST_CPU = 2; + localparam COM_INSP_DEST_FP_THIS = 0; + localparam COM_INSP_DEST_FP_OTHER = 1; + localparam COM_INSP_DEST_SP_BOTH = 2; localparam COM_INSP_MAX_NUM_DREGS = 12; //padded_eth + ip + udp + vrt_hdr localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at + //output inspector interfaces + wire [35:0] com_insp_out_fp_this_data; + wire com_insp_out_fp_this_valid; + wire com_insp_out_fp_this_ready; + + wire [35:0] com_insp_out_fp_other_data; + wire com_insp_out_fp_other_valid; + wire com_insp_out_fp_other_ready; + + wire [35:0] com_insp_out_sp_both_data; + wire com_insp_out_sp_both_valid; + wire com_insp_out_sp_both_ready; + + //connect the other interfaces into here for now + assign dsp_out_data = com_insp_out_fp_this_data; + assign dsp_out_valid = com_insp_out_fp_this_valid; + assign com_insp_out_fp_this_ready = dsp_out_ready; + + assign crs_out_data = com_insp_out_fp_other_data; + assign crs_out_valid = com_insp_out_fp_other_valid; + assign com_insp_out_fp_other_ready = crs_out_ready; + + assign cpu_out_data = com_insp_out_sp_both_data; + assign cpu_out_valid = com_insp_out_sp_both_valid; + assign com_insp_out_sp_both_ready = cpu_out_ready; + reg [1:0] com_insp_state; reg [1:0] com_insp_dest; reg [3:0] com_insp_dreg_count; //data registers to buffer headers @@ -325,20 +351,22 @@ module packet_router reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0]; //Inspection logic: - wire com_inp_dregs_is_dsp = 1'b1 + wire com_inp_dregs_is_data = 1'b1 & (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 & (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP & (com_insp_dregs[9][15:0] == 16'd49153) //UDP data port & (com_inp_data[31:0] != 32'h0) //VRT hdr non-zero ; - wire com_inp_dregs_is_ser = 1'b0; + wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & 1'b1; //TODO check for ip match + wire com_inp_dregs_is_data_there = com_inp_dregs_is_data & 1'b0; //TODO check for ip mismatch //Inspector output flags special case: //Inject SOF into flags at first DSP line. - wire [3:0] com_insp_out_flags = ((com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) & (com_insp_dest == COM_INSP_DEST_DSP))? - 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32] - ; + wire [3:0] com_insp_out_flags = ( + (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) & + (com_insp_dest == COM_INSP_DEST_FP_THIS) + )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32]; //The communication inspector ouput data and valid signals: //Mux between com input and data registers based on the state. @@ -353,20 +381,21 @@ module packet_router //The communication inspector ouput ready signal: //Mux between the various destination ready signals. wire com_insp_out_ready = - (com_insp_dest == COM_INSP_DEST_CPU)? cpu_out_ready : ( - (com_insp_dest == COM_INSP_DEST_DSP)? dsp_out_ready : ( - 1'b0)); + (com_insp_dest == COM_INSP_DEST_FP_THIS) ? com_insp_out_fp_this_ready : ( + (com_insp_dest == COM_INSP_DEST_FP_OTHER)? com_insp_out_fp_other_ready : ( + (com_insp_dest == COM_INSP_DEST_SP_BOTH) ? com_insp_out_sp_both_ready : ( + 1'b0))); //Always connected output data lines. - assign cpu_out_data = com_insp_out_data; - assign dsp_out_data = com_insp_out_data; - assign crs_out_data = com_insp_out_data; + assign com_insp_out_fp_this_data = com_insp_out_data; + assign com_insp_out_fp_other_data = com_insp_out_data; + assign com_insp_out_sp_both_data = com_insp_out_data; //Destination output valid signals: //Comes from inspector valid when destination is selected, and otherwise low. - assign cpu_out_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0; - assign dsp_out_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0; - assign crs_out_valid = (com_insp_dest == COM_INSP_DEST_SER)? com_insp_out_valid : 1'b0; + assign com_insp_out_fp_this_valid = (com_insp_dest == COM_INSP_DEST_FP_THIS) ? com_insp_out_valid : 1'b0; + assign com_insp_out_fp_other_valid = (com_insp_dest == COM_INSP_DEST_FP_OTHER)? com_insp_out_valid : 1'b0; + assign com_insp_out_sp_both_valid = (com_insp_dest == COM_INSP_DEST_SP_BOTH) ? com_insp_out_valid : 1'b0; //The communication inspector ouput ready signal: //Always ready when storing to data registers, @@ -396,18 +425,18 @@ module packet_router COM_INSP_STATE_READ_COM: begin if (com_inp_ready & com_inp_valid) begin com_insp_dregs[com_insp_dreg_count] <= com_inp_data; - if (com_inp_dregs_is_dsp & com_insp_dreg_counter_done) begin - com_insp_dest <= COM_INSP_DEST_DSP; + if (com_inp_dregs_is_data_here & com_insp_dreg_counter_done) begin + com_insp_dest <= COM_INSP_DEST_FP_THIS; com_insp_state <= COM_INSP_STATE_WRITE_REGS; com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; end - else if (com_inp_dregs_is_ser & com_insp_dreg_counter_done) begin - com_insp_dest <= COM_INSP_DEST_SER; + else if (com_inp_dregs_is_data_there & com_insp_dreg_counter_done) begin + com_insp_dest <= COM_INSP_DEST_FP_OTHER; com_insp_state <= COM_INSP_STATE_WRITE_REGS; com_insp_dreg_count <= 0; end else if (com_inp_data[33] | com_insp_dreg_counter_done) begin - com_insp_dest <= COM_INSP_DEST_CPU; + com_insp_dest <= COM_INSP_DEST_SP_BOTH; com_insp_state <= COM_INSP_STATE_WRITE_REGS; com_insp_dreg_count <= 0; end -- cgit v1.2.3 From 3e0458a6bbe42678b2c2c8a51f48c77eb1c587c7 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 18 Nov 2010 19:31:19 -0800 Subject: packet_router: added splitter and mux for slow path stuff (also fixed typo in crossbar input) --- usrp2/fifo/fifo36_splitter.v | 68 ++++++++++++++++++++++++++++++++++++++++++++ usrp2/fifo/packet_router.v | 37 +++++++++++++++++------- 2 files changed, 95 insertions(+), 10 deletions(-) create mode 100644 usrp2/fifo/fifo36_splitter.v diff --git a/usrp2/fifo/fifo36_splitter.v b/usrp2/fifo/fifo36_splitter.v new file mode 100644 index 000000000..cf1978c34 --- /dev/null +++ b/usrp2/fifo/fifo36_splitter.v @@ -0,0 +1,68 @@ + +// Split packets from a fifo based interface so it goes out identically on two interfaces + +module fifo36_splitter + ( + input clk, input rst, + input [35:0] inp_data, input inp_valid, output inp_ready, + output [35:0] out0_data, output out0_valid, input out0_ready, + output [35:0] out1_data, output out1_valid, input out1_ready + ); + + localparam STATE_COPY_BOTH = 0; + localparam STATE_COPY_ZERO = 1; + localparam STATE_COPY_ONE = 2; + + reg [1:0] state; + reg [35:0] data_reg; + + assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; + assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; + + assign out0_valid = + (state == STATE_COPY_BOTH)? inp_valid : ( + (state == STATE_COPY_ZERO)? 1'b1 : ( + 1'b0)); + + assign out1_valid = + (state == STATE_COPY_BOTH)? inp_valid : ( + (state == STATE_COPY_ONE)? 1'b1 : ( + 1'b0)); + + assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0; + + always @(posedge clk) + if (rst) begin + state <= STATE_COPY_BOTH; + end + else begin + case (state) + + STATE_COPY_BOTH: begin + if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin + state <= STATE_COPY_ONE; + end + else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin + state <= STATE_COPY_ZERO; + end + data_reg <= inp_data; + end + + STATE_COPY_ZERO: begin + if (out0_valid & out0_ready) begin + state <= STATE_COPY_BOTH; + end + end + + STATE_COPY_ONE: begin + if (out1_valid & out1_ready) begin + state <= STATE_COPY_BOTH; + end + end + + endcase //state + end + + + +endmodule //fifo36_splitter diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 96b7e9e07..1ddfc1bc0 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -105,7 +105,7 @@ module packet_router //connect the crossbar ready signals assign eth_inp_ready = (master_mode_flag)? com_inp_ready : 1'b1/*null sink*/; - assign ser_inp_ready = (master_mode_flag)? crs_inp_ready : eth_inp_ready; + assign ser_inp_ready = (master_mode_flag)? crs_inp_ready : com_inp_ready; //////////////////////////////////////////////////////////////////// // Communication output sink crossbar @@ -330,19 +330,11 @@ module packet_router wire com_insp_out_sp_both_valid; wire com_insp_out_sp_both_ready; - //connect the other interfaces into here for now + //connect this fast-path signals directly to the DSP out assign dsp_out_data = com_insp_out_fp_this_data; assign dsp_out_valid = com_insp_out_fp_this_valid; assign com_insp_out_fp_this_ready = dsp_out_ready; - assign crs_out_data = com_insp_out_fp_other_data; - assign crs_out_valid = com_insp_out_fp_other_valid; - assign com_insp_out_fp_other_ready = crs_out_ready; - - assign cpu_out_data = com_insp_out_sp_both_data; - assign cpu_out_valid = com_insp_out_sp_both_valid; - assign com_insp_out_sp_both_ready = cpu_out_ready; - reg [1:0] com_insp_state; reg [1:0] com_insp_dest; reg [3:0] com_insp_dreg_count; //data registers to buffer headers @@ -471,6 +463,31 @@ module packet_router endcase //com_insp_state end + //////////////////////////////////////////////////////////////////// + // Serdes crossbar output source + // - combine slow-path data with fast-path other data + // - slow-path data is duplicated to this and CPU out + //////////////////////////////////////////////////////////////////// + + //dummy signals to join the the splitter and mux below + wire [35:0] _sp_split_to_mux_data; + wire _sp_split_to_mux_valid; + wire _sp_split_to_mux_ready; + + fifo36_splitter crs_out_src0( + .clk(stream_clk), .rst(stream_rst), + .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready), + .out0_data(_sp_split_to_mux_data), .out0_valid(_sp_split_to_mux_valid), .out0_ready(_sp_split_to_mux_ready), + .out1_data(cpu_out_data), .out1_valid(cpu_out_valid), .out1_ready(cpu_out_ready) + ); + + fifo36_mux crs_out_src1( + .clk(stream_clk), .reset(stream_rst), .clear(1'b0), + .data0_i(com_insp_out_fp_other_data), .src0_rdy_i(com_insp_out_fp_other_valid), .dst0_rdy_o(com_insp_out_fp_other_ready), + .data1_i(_sp_split_to_mux_data), .src1_rdy_i(_sp_split_to_mux_valid), .dst1_rdy_o(_sp_split_to_mux_ready), + .data_o(crs_out_data), .src_rdy_o(crs_out_valid), .dst_rdy_i(crs_out_ready) + ); + //////////////////////////////////////////////////////////////////// // DSP input framer // - add a 1-line frame header to each DSP input packet -- cgit v1.2.3 From ff3430ad0623766c752ba91e9462c44975fce602 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 19 Nov 2010 15:24:10 -0800 Subject: packet_router: registered control flags, added clear to all state machines --- usrp2/fifo/packet_router.v | 34 ++++++++++++++++++++++------------ usrp2/top/u2_rev3/u2_core_udp.v | 6 ++++-- 2 files changed, 26 insertions(+), 14 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 1ddfc1bc0..69bae393f 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -18,6 +18,7 @@ module packet_router //input control register input [31:0] control, + input control_changed, //output status register output [31:0] status, @@ -66,10 +67,19 @@ module packet_router //////////////////////////////////////////////////////////////////// // status and control handshakes //////////////////////////////////////////////////////////////////// - wire cpu_out_hs_ctrl = control[0]; - wire cpu_inp_hs_ctrl = control[1]; - wire master_mode_flag = control[2]; - wire [BUF_SIZE-1:0] cpu_inp_line_count = control[BUF_SIZE-1+16:0+16]; + reg cpu_out_hs_ctrl; + reg cpu_inp_hs_ctrl; + reg master_mode_flag; + reg router_clr; + reg [BUF_SIZE-1:0] cpu_inp_line_count; + + always @(posedge control_changed) begin + cpu_out_hs_ctrl <= control[0]; + cpu_inp_hs_ctrl <= control[1]; + master_mode_flag <= control[2]; + router_clr <= control[8]; + cpu_inp_line_count <= control[BUF_SIZE-1+16:0+16]; + end wire cpu_out_hs_stat; assign status[0] = cpu_out_hs_stat; @@ -152,14 +162,14 @@ module packet_router wire _combiner_ready; fifo36_mux _com_output_source( - .clk(stream_clk), .reset(stream_rst), .clear(1'b0), + .clk(stream_clk), .reset(stream_rst), .clear(router_clr), .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready), .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), .data_o(_combiner_data), .src_rdy_o(_combiner_valid), .dst_rdy_i(_combiner_ready) ); fifo36_mux com_output_source( - .clk(stream_clk), .reset(stream_rst), .clear(1'b0), + .clk(stream_clk), .reset(stream_rst), .clear(router_clr), .data0_i(_combiner_data), .src0_rdy_i(_combiner_valid), .dst0_rdy_o(_combiner_ready), .data1_i(crs_inp_data), .src1_rdy_i(crs_inp_valid), .dst1_rdy_o(crs_inp_ready), .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) @@ -197,7 +207,7 @@ module packet_router ); always @(posedge stream_clk) - if(stream_rst) begin + if(stream_rst | router_clr) begin cpu_out_state <= CPU_OUT_STATE_WAIT_SOF; cpu_out_addr <= 0; end @@ -266,7 +276,7 @@ module packet_router ); always @(posedge stream_clk) - if(stream_rst) begin + if(stream_rst | router_clr) begin cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; cpu_inp_addr <= 0; end @@ -400,7 +410,7 @@ module packet_router 1'b0))); always @(posedge stream_clk) - if(stream_rst) begin + if(stream_rst | router_clr) begin com_insp_state <= COM_INSP_STATE_READ_COM_PRE; com_insp_dreg_count <= 0; end @@ -475,14 +485,14 @@ module packet_router wire _sp_split_to_mux_ready; fifo36_splitter crs_out_src0( - .clk(stream_clk), .rst(stream_rst), + .clk(stream_clk), .rst(stream_rst | router_clr), .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready), .out0_data(_sp_split_to_mux_data), .out0_valid(_sp_split_to_mux_valid), .out0_ready(_sp_split_to_mux_ready), .out1_data(cpu_out_data), .out1_valid(cpu_out_valid), .out1_ready(cpu_out_ready) ); fifo36_mux crs_out_src1( - .clk(stream_clk), .reset(stream_rst), .clear(1'b0), + .clk(stream_clk), .reset(stream_rst), .clear(router_clr), .data0_i(com_insp_out_fp_other_data), .src0_rdy_i(com_insp_out_fp_other_valid), .dst0_rdy_o(com_insp_out_fp_other_ready), .data1_i(_sp_split_to_mux_data), .src1_rdy_i(_sp_split_to_mux_valid), .dst1_rdy_o(_sp_split_to_mux_ready), .data_o(crs_out_data), .src_rdy_o(crs_out_valid), .dst_rdy_i(crs_out_ready) @@ -533,7 +543,7 @@ module packet_router ); always @(posedge stream_clk) - if(stream_rst) begin + if(stream_rst | router_clr) begin dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; dsp_frm_addr <= 0; end diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 1807f7e9a..e9c058527 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -361,10 +361,11 @@ module u2_core wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; wire [31:0] router_control; + wire router_control_changed; setting_reg #(.my_addr(SR_BUF_POOL)) sreg(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(router_control),.changed()); + .out(router_control),.changed(router_control_changed)); packet_router #(.BUF_SIZE(9)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), @@ -373,7 +374,8 @@ module u2_core .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .control(router_control), .status(status), .sys_int_o(buffer_int), + .control(router_control), .control_changed(router_control_changed), + .status(status), .sys_int_o(buffer_int), .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), -- cgit v1.2.3 From 15180da94ec11958ad97aaf0e79c29e2081b8b51 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 21 Nov 2010 12:19:04 -0800 Subject: packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debug --- usrp2/fifo/packet_router.v | 50 +++++++++++++++++++++++++++++++++-------- usrp2/top/u2_rev3/u2_core_udp.v | 4 +++- 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 69bae393f..dda1519b8 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -25,6 +25,8 @@ module packet_router output sys_int_o, //want an interrupt? + output [31:0] debug, + // Input Interfaces (in to router) input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready, input [35:0] dsp_inp_data, input dsp_inp_valid, output dsp_inp_ready, @@ -214,14 +216,14 @@ module packet_router else begin case(cpu_out_state) CPU_OUT_STATE_WAIT_SOF: begin - if (cpu_out_ready & cpu_out_valid & (cpu_out_data[32] == 1'b1)) begin + if (cpu_out_ready & cpu_out_valid & cpu_out_data[32]) begin cpu_out_state <= CPU_OUT_STATE_WAIT_EOF; cpu_out_addr <= cpu_out_addr_next; end end CPU_OUT_STATE_WAIT_EOF: begin - if (cpu_out_ready & cpu_out_valid & (cpu_out_data[33] == 1'b1)) begin + if (cpu_out_ready & cpu_out_valid & cpu_out_data[33]) begin cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI; end if (cpu_out_ready & cpu_out_valid) begin @@ -259,7 +261,7 @@ module packet_router reg [BUF_SIZE-1:0] cpu_inp_line_count_reg; assign cpu_inp_data[35:32] = - (cpu_inp_addr == 0 )? 4'b0001 : ( + (cpu_inp_addr == 1 )? 4'b0001 : ( (cpu_inp_addr == cpu_inp_line_count_reg)? 4'b0010 : ( 4'b0000)); @@ -354,10 +356,10 @@ module packet_router //Inspection logic: wire com_inp_dregs_is_data = 1'b1 - & (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 - & (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP - & (com_insp_dregs[9][15:0] == 16'd49153) //UDP data port - & (com_inp_data[31:0] != 32'h0) //VRT hdr non-zero + && (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 + && (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP + && (com_insp_dregs[9][15:0] == 16'd49153) //UDP data port + && (com_inp_data[31:0] != 32'h0) //VRT hdr non-zero ; wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & 1'b1; //TODO check for ip match @@ -366,7 +368,7 @@ module packet_router //Inspector output flags special case: //Inject SOF into flags at first DSP line. wire [3:0] com_insp_out_flags = ( - (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) & + (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) && (com_insp_dest == COM_INSP_DEST_FP_THIS) )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32]; @@ -529,7 +531,7 @@ module packet_router (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( {4'b0000, dsp_frm_data_bram})); assign dsp_frm_valid = ( - (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) | + (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) || (dsp_frm_state == DSP_FRM_STATE_WRITE) )? 1'b1 : 1'b0; @@ -590,4 +592,34 @@ module packet_router endcase //dsp_frm_state end + //////////////////////////////////////////////////////////////////// + // Assign debugs + //////////////////////////////////////////////////////////////////// + + assign debug = { + //inputs to the router (8) + dsp_inp_ready, dsp_inp_valid, + ser_inp_ready, ser_inp_valid, + eth_inp_ready, eth_inp_valid, + cpu_inp_ready, cpu_inp_valid, + + //outputs from the router (8) + dsp_out_ready, dsp_out_valid, + ser_out_ready, ser_out_valid, + eth_out_ready, eth_out_valid, + cpu_out_ready, cpu_out_valid, + + //inspector interfaces (8) + com_inp_ready, com_inp_valid, + com_insp_out_fp_this_ready, com_insp_out_fp_this_valid, + com_insp_out_fp_other_ready, com_insp_out_fp_other_valid, + com_insp_out_sp_both_ready, com_insp_out_sp_both_valid, + + //other interfaces (8) + crs_inp_ready, crs_inp_valid, + com_out_ready, com_out_valid, + crs_out_ready, crs_out_valid, + _sp_split_to_mux_ready, _sp_split_to_mux_valid + }; + endmodule // packet_router diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index e9c058527..78cf641f7 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -363,6 +363,8 @@ module u2_core wire [31:0] router_control; wire router_control_changed; + wire [31:0] router_debug; + setting_reg #(.my_addr(SR_BUF_POOL)) sreg(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), .out(router_control),.changed(router_control_changed)); @@ -375,7 +377,7 @@ module u2_core .stream_clk(dsp_clk), .stream_rst(dsp_rst), .control(router_control), .control_changed(router_control_changed), - .status(status), .sys_int_o(buffer_int), + .status(status), .sys_int_o(buffer_int), .debug(router_debug), .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), -- cgit v1.2.3 From 257ba8bb1caebca29e1dddd9e73bfd32abe8d1d1 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 21 Nov 2010 13:24:48 -0800 Subject: packet_router: added a way to program in the ip and mac addrs, and added inspector check --- usrp2/fifo/packet_router.v | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index dda1519b8..7bc5255be 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -74,6 +74,8 @@ module packet_router reg master_mode_flag; reg router_clr; reg [BUF_SIZE-1:0] cpu_inp_line_count; + reg [31:0] my_ip_addr; + reg [47:0] my_mac_addr; always @(posedge control_changed) begin cpu_out_hs_ctrl <= control[0]; @@ -81,6 +83,18 @@ module packet_router master_mode_flag <= control[2]; router_clr <= control[8]; cpu_inp_line_count <= control[BUF_SIZE-1+16:0+16]; + case (control[6:4]) + 3'b001: + my_ip_addr[15:0] <= control[31:16]; + 3'b010: + my_ip_addr[31:16] <= control[31:16]; + 3'b011: + my_mac_addr[15:0] <= control[31:16]; + 3'b100: + my_mac_addr[31:16] <= control[31:16]; + 3'b101: + my_mac_addr[47:32] <= control[31:16]; + endcase end wire cpu_out_hs_stat; @@ -362,8 +376,9 @@ module packet_router && (com_inp_data[31:0] != 32'h0) //VRT hdr non-zero ; - wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & 1'b1; //TODO check for ip match - wire com_inp_dregs_is_data_there = com_inp_dregs_is_data & 1'b0; //TODO check for ip mismatch + wire com_inp_dregs_my_ip_match = (my_ip_addr == com_insp_dregs[8][31:0])? 1'b1 : 1'b0; + wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & com_inp_dregs_my_ip_match; + wire com_inp_dregs_is_data_there = com_inp_dregs_is_data & ~com_inp_dregs_my_ip_match; //Inspector output flags special case: //Inject SOF into flags at first DSP line. -- cgit v1.2.3 From 8e2f005097fa83776f04ec38a1b2fa7378200cba Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 21 Nov 2010 19:35:30 -0800 Subject: packet_router: transplanted the async error interface, its now sent into the packet router to be muxed to com out --- usrp2/fifo/packet_router.v | 23 ++++++++++++++++------- usrp2/top/u2_rev3/u2_core_udp.v | 15 +++++---------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 7bc5255be..12b12e41c 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -31,6 +31,7 @@ module packet_router input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready, input [35:0] dsp_inp_data, input dsp_inp_valid, output dsp_inp_ready, input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready, + input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready, // Output Interfaces (out of router) output [35:0] ser_out_data, output ser_out_valid, input ser_out_ready, @@ -164,6 +165,7 @@ module packet_router // Communication output source combiner // - DSP framer // - CPU input + // - Error input // - Crossbar input //////////////////////////////////////////////////////////////////// @@ -173,21 +175,28 @@ module packet_router wire dsp_frm_ready; //dummy signals to join the the muxes below - wire [35:0] _combiner_data; - wire _combiner_valid; - wire _combiner_ready; + wire [35:0] _combiner0_data, _combiner1_data; + wire _combiner0_valid, _combiner1_valid; + wire _combiner0_ready, _combiner1_ready; - fifo36_mux _com_output_source( + fifo36_mux _com_output_combiner0( .clk(stream_clk), .reset(stream_rst), .clear(router_clr), .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready), + .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready), + .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready) + ); + + fifo36_mux _com_output_combiner1( + .clk(stream_clk), .reset(stream_rst), .clear(router_clr), + .data0_i(crs_inp_data), .src0_rdy_i(crs_inp_valid), .dst0_rdy_o(crs_inp_ready), .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), - .data_o(_combiner_data), .src_rdy_o(_combiner_valid), .dst_rdy_i(_combiner_ready) + .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) ); fifo36_mux com_output_source( .clk(stream_clk), .reset(stream_rst), .clear(router_clr), - .data0_i(_combiner_data), .src0_rdy_i(_combiner_valid), .dst0_rdy_o(_combiner_ready), - .data1_i(crs_inp_data), .src1_rdy_i(crs_inp_valid), .dst1_rdy_o(crs_inp_ready), + .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready), + .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready), .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) ); diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 78cf641f7..451de9297 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -360,6 +360,9 @@ module u2_core wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + wire [31:0] router_control; wire router_control_changed; @@ -382,6 +385,7 @@ module u2_core .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_src_rdy), .err_inp_valid(tx_err_dst_rdy), .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), @@ -475,20 +479,11 @@ module u2_core .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), .debug(debug_udp) ); - wire [35:0] tx_err_data, udp1_tx_data; - wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); - fifo36_mux #(.prio(0)) mux_err_stream - (.clk(dsp_clk), .reset(dsp_reset), .clear(0), - .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), -- cgit v1.2.3 From 1231a15c889d41fe24e95df69e20653282d9180c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Nov 2010 11:33:21 -0800 Subject: abstract out the crossbar functionality --- usrp2/fifo/crossbar36.v | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 usrp2/fifo/crossbar36.v diff --git a/usrp2/fifo/crossbar36.v b/usrp2/fifo/crossbar36.v new file mode 100644 index 000000000..d90f5659c --- /dev/null +++ b/usrp2/fifo/crossbar36.v @@ -0,0 +1,40 @@ + + +module crossbar36 + (input clk, input reset, input clear, + input cross, + input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o, + input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o, + output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i, + output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i); + + reg cross_int, active0, active1; + + assign data0_o = cross_int ? data1_i : data0_i; + assign data1_o = cross_int ? data0_i : data1_i; + + assign src0_rdy_o = cross_int ? src1_rdy_i : src0_rdy_i; + assign src1_rdy_o = cross_int ? src0_rdy_i : src1_rdy_i; + + assign dst0_rdy_o = cross_int ? dst1_rdy_i : dst0_rdy_i; + assign dst1_rdy_o = cross_int ? dst0_rdy_i : dst1_rdy_i; + + always @(posedge clk) + if(reset | clear) + active0 <= 0; + else if(src0_rdy_i & dst0_rdy_o) + active0 <= ~data0_i[33]; + + always @(posedge clk) + if(reset | clear) + active1 <= 0; + else if(src1_rdy_i & dst1_rdy_o) + active1 <= ~data1_i[33]; + + always @(posedge clk) + if(reset | clear) + cross_int <= 0; + else if(~active0 & ~active1) + cross_int <= cross; + +endmodule // crossbar36 -- cgit v1.2.3 From 9a8704ed46ff66276a207d30b04b8c40b9b87e52 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Nov 2010 11:39:47 -0800 Subject: packet valve. will drop incoming data if shut off. --- usrp2/fifo/valve36.v | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 usrp2/fifo/valve36.v diff --git a/usrp2/fifo/valve36.v b/usrp2/fifo/valve36.v new file mode 100644 index 000000000..b4b23e5a6 --- /dev/null +++ b/usrp2/fifo/valve36.v @@ -0,0 +1,28 @@ + + +module valve36 + (input clk, input reset, input clear, + input shutoff, + input [35:0] data_i, input src_rdy_i, output dst_rdy_o, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + reg shutoff_int, active; + + assign data_o = data_i; + + assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i; + assign src_rdy_o = shutoff_int ? 1'b0 : src_rdy_i; + + always @(posedge clk) + if(reset | clear) + active <= 0; + else if(src_rdy_i & dst_rdy_o) + active <= ~data_i[33]; + + always @(posedge clk) + if(reset | clear) + shutoff_int <= 0; + else if(~active) + shutoff_int <= shutoff; + +endmodule // valve36 -- cgit v1.2.3 From b155031c90fb1caaa4aa0e21e0cf2929019a19b6 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 22 Nov 2010 13:56:40 -0800 Subject: packet_router: implemented crossbar and valve module, moved sreg into router module --- usrp2/fifo/Makefile.srcs | 2 + usrp2/fifo/packet_router.v | 108 +++++++++++++++++++++++----------------- usrp2/top/u2_rev3/u2_core_udp.v | 23 +++------ 3 files changed, 72 insertions(+), 61 deletions(-) diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs index 61eb2c0c8..0508c6b77 100644 --- a/usrp2/fifo/Makefile.srcs +++ b/usrp2/fifo/Makefile.srcs @@ -8,6 +8,7 @@ FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \ buffer_int.v \ buffer_pool.v \ +crossbar36.v \ fifo_2clock.v \ fifo_2clock_cascade.v \ ll8_shortfifo.v \ @@ -24,4 +25,5 @@ fifo36_mux.v \ fifo36_demux.v \ fifo36_splitter.v \ packet_router.v \ +valve36.v \ )) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 12b12e41c..1023df2e5 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -1,5 +1,9 @@ module packet_router - #(parameter BUF_SIZE = 9) + #( + parameter BUF_SIZE = 9, + parameter UDP_BASE = 0, + parameter STATUS_BASE = 0 + ) ( //wishbone interface for memory mapped CPU frames input wb_clk_i, @@ -13,12 +17,12 @@ module packet_router output wb_err_o, output wb_rty_o, + //setting register interface + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input stream_clk, input stream_rst, - - //input control register - input [31:0] control, - input control_changed, + input stream_clr, //output status register output [31:0] status, @@ -73,28 +77,28 @@ module packet_router reg cpu_out_hs_ctrl; reg cpu_inp_hs_ctrl; reg master_mode_flag; - reg router_clr; reg [BUF_SIZE-1:0] cpu_inp_line_count; reg [31:0] my_ip_addr; - reg [47:0] my_mac_addr; + wire [31:0] control; + wire control_changed; + setting_reg #(.my_addr(STATUS_BASE)) sreg( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out(control),.changed(control_changed) + ); + + //grab the pertinent control settings always @(posedge control_changed) begin cpu_out_hs_ctrl <= control[0]; cpu_inp_hs_ctrl <= control[1]; master_mode_flag <= control[2]; - router_clr <= control[8]; cpu_inp_line_count <= control[BUF_SIZE-1+16:0+16]; - case (control[6:4]) - 3'b001: + case (control[5:4]) + 2'b01: my_ip_addr[15:0] <= control[31:16]; - 3'b010: + 2'b10: my_ip_addr[31:16] <= control[31:16]; - 3'b011: - my_mac_addr[15:0] <= control[31:16]; - 3'b100: - my_mac_addr[31:16] <= control[31:16]; - 3'b101: - my_mac_addr[47:32] <= control[31:16]; endcase end @@ -122,17 +126,24 @@ module packet_router wire crs_inp_valid; wire crs_inp_ready; - //connect the com input signals - assign com_inp_data = (master_mode_flag)? eth_inp_data : ser_inp_data; - assign com_inp_valid = (master_mode_flag)? eth_inp_valid : ser_inp_valid; + //dummy signals for valve/xbar below + wire [35:0] _eth_inp_data; + wire _eth_inp_valid; + wire _eth_inp_ready; - //connect the crossbar input signals - assign crs_inp_data = ser_inp_data; - assign crs_inp_valid = (master_mode_flag)? ser_inp_valid : 1'b0; + valve36 eth_inp_valve ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag), + .data_i(eth_inp_data), .src_rdy_i(eth_inp_valid), .dst_rdy_o(eth_inp_ready), + .data_o(_eth_inp_data), .src_rdy_o(_eth_inp_valid), .dst_rdy_i(_eth_inp_ready) + ); - //connect the crossbar ready signals - assign eth_inp_ready = (master_mode_flag)? com_inp_ready : 1'b1/*null sink*/; - assign ser_inp_ready = (master_mode_flag)? crs_inp_ready : com_inp_ready; + crossbar36 com_inp_xbar ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag), + .data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready), + .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready), + .data0_o(com_inp_data), .src0_rdy_o(com_inp_valid), .dst0_rdy_i(com_inp_ready), + .data1_o(crs_inp_data), .src1_rdy_o(crs_inp_valid), .dst1_rdy_i(crs_inp_ready) + ); //////////////////////////////////////////////////////////////////// // Communication output sink crossbar @@ -149,17 +160,24 @@ module packet_router wire crs_out_valid; wire crs_out_ready; - //connect the ethernet output signals - assign eth_out_data = com_out_data; - assign eth_out_valid = (master_mode_flag)? com_out_valid : 1'b0; - - //connect the serdes output signals - assign ser_out_data = (master_mode_flag)? crs_out_data : com_out_data; - assign ser_out_valid = (master_mode_flag)? crs_out_valid : com_out_valid; + //dummy signals for valve/xbar below + wire [35:0] _eth_out_data; + wire _eth_out_valid; + wire _eth_out_ready; + + crossbar36 com_out_xbar ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag), + .data0_i(com_out_data), .src0_rdy_i(com_out_valid), .dst0_rdy_o(com_out_ready), + .data1_i(crs_out_data), .src1_rdy_i(crs_out_valid), .dst1_rdy_o(crs_out_ready), + .data0_o(_eth_out_data), .src0_rdy_o(_eth_out_valid), .dst0_rdy_i(_eth_out_ready), + .data1_o(ser_out_data), .src1_rdy_o(ser_out_valid), .dst1_rdy_i(ser_out_ready) + ); - //connect the crossbar ready signals - assign com_out_ready = (master_mode_flag)? eth_out_ready : ser_out_ready; - assign crs_out_ready = (master_mode_flag)? ser_out_ready : 1'b1/*null sink*/; + valve36 eth_out_valve ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag), + .data_i(_eth_out_data), .src_rdy_i(_eth_out_valid), .dst_rdy_o(_eth_out_ready), + .data_o(eth_out_data), .src_rdy_o(eth_out_valid), .dst_rdy_i(eth_out_ready) + ); //////////////////////////////////////////////////////////////////// // Communication output source combiner @@ -180,21 +198,21 @@ module packet_router wire _combiner0_ready, _combiner1_ready; fifo36_mux _com_output_combiner0( - .clk(stream_clk), .reset(stream_rst), .clear(router_clr), + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready), .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready), .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready) ); fifo36_mux _com_output_combiner1( - .clk(stream_clk), .reset(stream_rst), .clear(router_clr), + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .data0_i(crs_inp_data), .src0_rdy_i(crs_inp_valid), .dst0_rdy_o(crs_inp_ready), .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) ); fifo36_mux com_output_source( - .clk(stream_clk), .reset(stream_rst), .clear(router_clr), + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready), .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready), .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) @@ -232,7 +250,7 @@ module packet_router ); always @(posedge stream_clk) - if(stream_rst | router_clr) begin + if(stream_rst | stream_clr) begin cpu_out_state <= CPU_OUT_STATE_WAIT_SOF; cpu_out_addr <= 0; end @@ -301,7 +319,7 @@ module packet_router ); always @(posedge stream_clk) - if(stream_rst | router_clr) begin + if(stream_rst | stream_clr) begin cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI; cpu_inp_addr <= 0; end @@ -436,7 +454,7 @@ module packet_router 1'b0))); always @(posedge stream_clk) - if(stream_rst | router_clr) begin + if(stream_rst | stream_clr) begin com_insp_state <= COM_INSP_STATE_READ_COM_PRE; com_insp_dreg_count <= 0; end @@ -511,14 +529,14 @@ module packet_router wire _sp_split_to_mux_ready; fifo36_splitter crs_out_src0( - .clk(stream_clk), .rst(stream_rst | router_clr), + .clk(stream_clk), .rst(stream_rst | stream_clr), .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready), .out0_data(_sp_split_to_mux_data), .out0_valid(_sp_split_to_mux_valid), .out0_ready(_sp_split_to_mux_ready), .out1_data(cpu_out_data), .out1_valid(cpu_out_valid), .out1_ready(cpu_out_ready) ); fifo36_mux crs_out_src1( - .clk(stream_clk), .reset(stream_rst), .clear(router_clr), + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .data0_i(com_insp_out_fp_other_data), .src0_rdy_i(com_insp_out_fp_other_valid), .dst0_rdy_o(com_insp_out_fp_other_ready), .data1_i(_sp_split_to_mux_data), .src1_rdy_i(_sp_split_to_mux_valid), .dst1_rdy_o(_sp_split_to_mux_ready), .data_o(crs_out_data), .src_rdy_o(crs_out_valid), .dst_rdy_i(crs_out_ready) @@ -569,7 +587,7 @@ module packet_router ); always @(posedge stream_clk) - if(stream_rst | router_clr) begin + if(stream_rst | stream_clr) begin dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; dsp_frm_addr <= 0; end diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 451de9297..83d218a7c 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -363,37 +363,28 @@ module u2_core wire [35:0] tx_err_data; wire tx_err_src_rdy, tx_err_dst_rdy; - wire [31:0] router_control; - wire router_control_changed; - wire [31:0] router_debug; - setting_reg #(.my_addr(SR_BUF_POOL)) - sreg(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(router_control),.changed(router_control_changed)); - - packet_router #(.BUF_SIZE(9)) packet_router + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .STATUS_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), - .control(router_control), .control_changed(router_control_changed), .status(status), .sys_int_o(buffer_int), .debug(router_debug), .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .err_inp_data(tx_err_data), .err_inp_ready(tx_err_src_rdy), .err_inp_valid(tx_err_dst_rdy), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); - - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); // ///////////////////////////////////////////////////////////////////////// // SPI -- Slave #2 @@ -444,7 +435,7 @@ module u2_core .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 9633a82509463d3bffcb9e8cae4db66dd4d79812 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 22 Nov 2010 14:41:14 -0800 Subject: packet_router: moved dsp framer into a module, added clr to splitter and renamed --- usrp2/fifo/Makefile.srcs | 3 +- usrp2/fifo/dsp_framer36.v | 98 ++++++++++++++++++++++++++++++++++++++++++++ usrp2/fifo/fifo36_splitter.v | 68 ------------------------------ usrp2/fifo/packet_router.v | 94 +++--------------------------------------- usrp2/fifo/splitter36.v | 68 ++++++++++++++++++++++++++++++ 5 files changed, 174 insertions(+), 157 deletions(-) create mode 100644 usrp2/fifo/dsp_framer36.v delete mode 100644 usrp2/fifo/fifo36_splitter.v create mode 100644 usrp2/fifo/splitter36.v diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs index 0508c6b77..5552fbd51 100644 --- a/usrp2/fifo/Makefile.srcs +++ b/usrp2/fifo/Makefile.srcs @@ -9,6 +9,7 @@ FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \ buffer_int.v \ buffer_pool.v \ crossbar36.v \ +dsp_framer36.v \ fifo_2clock.v \ fifo_2clock_cascade.v \ ll8_shortfifo.v \ @@ -23,7 +24,7 @@ fifo36_to_fifo19.v \ fifo19_to_fifo36.v \ fifo36_mux.v \ fifo36_demux.v \ -fifo36_splitter.v \ packet_router.v \ +splitter36.v \ valve36.v \ )) diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v new file mode 100644 index 000000000..fbdc9fbd7 --- /dev/null +++ b/usrp2/fifo/dsp_framer36.v @@ -0,0 +1,98 @@ + +// Frame DSP packets with a header line to be handled by the protocol machine + +module dsp_framer36 + #(parameter BUF_SIZE = 9) + ( + input clk, input rst, input clr, + input [35:0] inp_data, input inp_valid, output inp_ready, + output [35:0] out_data, output out_valid, input out_ready + ); + + localparam DSP_FRM_STATE_WAIT_SOF = 0; + localparam DSP_FRM_STATE_WAIT_EOF = 1; + localparam DSP_FRM_STATE_WRITE_HDR = 2; + localparam DSP_FRM_STATE_WRITE = 3; + + reg [1:0] dsp_frm_state; + reg [BUF_SIZE-1:0] dsp_frm_addr; + reg [BUF_SIZE-1:0] dsp_frm_count; + wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1; + + //DSP input stream ready in the following states + assign inp_ready = + (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : ( + (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : ( + 1'b0)); + + //DSP framer output data mux (header or BRAM): + //The header is generated here from the count. + wire [31:0] dsp_frm_data_bram; + wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; + assign out_data = + (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( + (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( + {4'b0000, dsp_frm_data_bram})); + assign out_valid = ( + (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) || + (dsp_frm_state == DSP_FRM_STATE_WRITE) + )? 1'b1 : 1'b0; + + RAMB16_S36_S36 dsp_frm_buff( + //port A = DSP input interface (writes to BRAM) + .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0), + .ENA(inp_ready),.SSRA(0),.WEA(inp_ready), + //port B = DSP framer interface (reads from BRAM) + .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), + .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) + ); + + always @(posedge clk) + if(rst | clr) begin + dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; + dsp_frm_addr <= 0; + end + else begin + case(dsp_frm_state) + DSP_FRM_STATE_WAIT_SOF: begin + if (inp_ready & inp_valid & inp_data[32]) begin + dsp_frm_addr <= dsp_frm_addr_next; + dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF; + end + end + + DSP_FRM_STATE_WAIT_EOF: begin + if (inp_ready & inp_valid) begin + if (inp_data[33]) begin + dsp_frm_count <= dsp_frm_addr_next; + dsp_frm_addr <= 0; + dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR; + end + else begin + dsp_frm_addr <= dsp_frm_addr_next; + end + end + end + + DSP_FRM_STATE_WRITE_HDR: begin + if (out_ready & out_valid) begin + dsp_frm_addr <= dsp_frm_addr_next; + dsp_frm_state <= DSP_FRM_STATE_WRITE; + end + end + + DSP_FRM_STATE_WRITE: begin + if (out_ready & out_valid) begin + if (out_data[33]) begin + dsp_frm_addr <= 0; + dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; + end + else begin + dsp_frm_addr <= dsp_frm_addr_next; + end + end + end + endcase //dsp_frm_state + end + +endmodule //dsp_framer36 diff --git a/usrp2/fifo/fifo36_splitter.v b/usrp2/fifo/fifo36_splitter.v deleted file mode 100644 index cf1978c34..000000000 --- a/usrp2/fifo/fifo36_splitter.v +++ /dev/null @@ -1,68 +0,0 @@ - -// Split packets from a fifo based interface so it goes out identically on two interfaces - -module fifo36_splitter - ( - input clk, input rst, - input [35:0] inp_data, input inp_valid, output inp_ready, - output [35:0] out0_data, output out0_valid, input out0_ready, - output [35:0] out1_data, output out1_valid, input out1_ready - ); - - localparam STATE_COPY_BOTH = 0; - localparam STATE_COPY_ZERO = 1; - localparam STATE_COPY_ONE = 2; - - reg [1:0] state; - reg [35:0] data_reg; - - assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; - assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; - - assign out0_valid = - (state == STATE_COPY_BOTH)? inp_valid : ( - (state == STATE_COPY_ZERO)? 1'b1 : ( - 1'b0)); - - assign out1_valid = - (state == STATE_COPY_BOTH)? inp_valid : ( - (state == STATE_COPY_ONE)? 1'b1 : ( - 1'b0)); - - assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0; - - always @(posedge clk) - if (rst) begin - state <= STATE_COPY_BOTH; - end - else begin - case (state) - - STATE_COPY_BOTH: begin - if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin - state <= STATE_COPY_ONE; - end - else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin - state <= STATE_COPY_ZERO; - end - data_reg <= inp_data; - end - - STATE_COPY_ZERO: begin - if (out0_valid & out0_ready) begin - state <= STATE_COPY_BOTH; - end - end - - STATE_COPY_ONE: begin - if (out1_valid & out1_ready) begin - state <= STATE_COPY_BOTH; - end - end - - endcase //state - end - - - -endmodule //fifo36_splitter diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 1023df2e5..8bd687c5a 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -528,8 +528,8 @@ module packet_router wire _sp_split_to_mux_valid; wire _sp_split_to_mux_ready; - fifo36_splitter crs_out_src0( - .clk(stream_clk), .rst(stream_rst | stream_clr), + splitter36 crs_out_src0( + .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready), .out0_data(_sp_split_to_mux_data), .out0_valid(_sp_split_to_mux_valid), .out0_ready(_sp_split_to_mux_ready), .out1_data(cpu_out_data), .out1_valid(cpu_out_valid), .out1_ready(cpu_out_ready) @@ -544,96 +544,14 @@ module packet_router //////////////////////////////////////////////////////////////////// // DSP input framer - // - add a 1-line frame header to each DSP input packet - // - each header is composed of a byte count and flags //////////////////////////////////////////////////////////////////// - localparam DSP_FRM_STATE_WAIT_SOF = 0; - localparam DSP_FRM_STATE_WAIT_EOF = 1; - localparam DSP_FRM_STATE_WRITE_HDR = 2; - localparam DSP_FRM_STATE_WRITE = 3; - - reg [1:0] dsp_frm_state; - reg [BUF_SIZE-1:0] dsp_frm_addr; - reg [BUF_SIZE-1:0] dsp_frm_count; - wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1; - - //DSP input stream ready in the following states - assign dsp_inp_ready = - (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : ( - (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : ( - 1'b0)); - - //DSP framer output data mux (header or BRAM): - //The header is generated here from the count. - wire [31:0] dsp_frm_data_bram; - wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; - assign dsp_frm_data = - (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( - (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( - {4'b0000, dsp_frm_data_bram})); - assign dsp_frm_valid = ( - (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) || - (dsp_frm_state == DSP_FRM_STATE_WRITE) - )? 1'b1 : 1'b0; - - RAMB16_S36_S36 dsp_frm_buff( - //port A = DSP input interface (writes to BRAM) - .DOA(),.ADDRA(dsp_frm_addr),.CLKA(stream_clk),.DIA(dsp_inp_data[31:0]),.DIPA(4'h0), - .ENA(dsp_inp_ready),.SSRA(0),.WEA(dsp_inp_ready), - //port B = DSP framer interface (reads from BRAM) - .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), - .ENB(dsp_frm_ready & dsp_frm_valid),.SSRB(0),.WEB(1'b0) + dsp_framer36 #(.BUF_SIZE(BUF_SIZE)) dsp0_framer36( + .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), + .inp_data(dsp_inp_data), .inp_valid(dsp_inp_valid), .inp_ready(dsp_inp_ready), + .out_data(dsp_frm_data), .out_valid(dsp_frm_valid), .out_ready(dsp_frm_ready) ); - always @(posedge stream_clk) - if(stream_rst | stream_clr) begin - dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; - dsp_frm_addr <= 0; - end - else begin - case(dsp_frm_state) - DSP_FRM_STATE_WAIT_SOF: begin - if (dsp_inp_ready & dsp_inp_valid & dsp_inp_data[32]) begin - dsp_frm_addr <= dsp_frm_addr_next; - dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF; - end - end - - DSP_FRM_STATE_WAIT_EOF: begin - if (dsp_inp_ready & dsp_inp_valid) begin - if (dsp_inp_data[33]) begin - dsp_frm_count <= dsp_frm_addr_next; - dsp_frm_addr <= 0; - dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR; - end - else begin - dsp_frm_addr <= dsp_frm_addr_next; - end - end - end - - DSP_FRM_STATE_WRITE_HDR: begin - if (dsp_frm_ready & dsp_frm_valid) begin - dsp_frm_addr <= dsp_frm_addr_next; - dsp_frm_state <= DSP_FRM_STATE_WRITE; - end - end - - DSP_FRM_STATE_WRITE: begin - if (dsp_frm_ready & dsp_frm_valid) begin - if (dsp_frm_data[33]) begin - dsp_frm_addr <= 0; - dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF; - end - else begin - dsp_frm_addr <= dsp_frm_addr_next; - end - end - end - endcase //dsp_frm_state - end - //////////////////////////////////////////////////////////////////// // Assign debugs //////////////////////////////////////////////////////////////////// diff --git a/usrp2/fifo/splitter36.v b/usrp2/fifo/splitter36.v new file mode 100644 index 000000000..ed998b4f5 --- /dev/null +++ b/usrp2/fifo/splitter36.v @@ -0,0 +1,68 @@ + +// Split packets from a fifo based interface so it goes out identically on two interfaces + +module splitter36 + ( + input clk, input rst, input clr, + input [35:0] inp_data, input inp_valid, output inp_ready, + output [35:0] out0_data, output out0_valid, input out0_ready, + output [35:0] out1_data, output out1_valid, input out1_ready + ); + + localparam STATE_COPY_BOTH = 0; + localparam STATE_COPY_ZERO = 1; + localparam STATE_COPY_ONE = 2; + + reg [1:0] state; + reg [35:0] data_reg; + + assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; + assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg; + + assign out0_valid = + (state == STATE_COPY_BOTH)? inp_valid : ( + (state == STATE_COPY_ZERO)? 1'b1 : ( + 1'b0)); + + assign out1_valid = + (state == STATE_COPY_BOTH)? inp_valid : ( + (state == STATE_COPY_ONE)? 1'b1 : ( + 1'b0)); + + assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0; + + always @(posedge clk) + if (rst | clr) begin + state <= STATE_COPY_BOTH; + end + else begin + case (state) + + STATE_COPY_BOTH: begin + if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin + state <= STATE_COPY_ONE; + end + else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin + state <= STATE_COPY_ZERO; + end + data_reg <= inp_data; + end + + STATE_COPY_ZERO: begin + if (out0_valid & out0_ready) begin + state <= STATE_COPY_BOTH; + end + end + + STATE_COPY_ONE: begin + if (out1_valid & out1_ready) begin + state <= STATE_COPY_BOTH; + end + end + + endcase //state + end + + + +endmodule //splitter36 -- cgit v1.2.3 From 05f7a0d5c5070203172683020ecde79c0f15fe28 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 22 Nov 2010 17:12:41 -0800 Subject: packet_router: moved udp tx proto machine into packet router, replaced udp_wrapper in top level with some fifo conversion stuff --- usrp2/fifo/packet_router.v | 44 +++++++++++++++++++++++++++++++++++++++-- usrp2/top/u2_rev3/u2_core_udp.v | 43 +++++++++++++++++++++++++--------------- 2 files changed, 69 insertions(+), 18 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 8bd687c5a..0ccf665f9 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -70,6 +70,9 @@ module packet_router wire [35:0] com_out_data; wire com_out_valid; wire com_out_ready; + wire [35:0] udp_out_data; + wire udp_out_valid; + wire udp_out_ready; //////////////////////////////////////////////////////////////////// // status and control handshakes @@ -180,7 +183,7 @@ module packet_router ); //////////////////////////////////////////////////////////////////// - // Communication output source combiner + // Communication output source combiner (feeds UDP proto machine) // - DSP framer // - CPU input // - Error input @@ -215,7 +218,7 @@ module packet_router .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready), .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready), - .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) + .data_o(udp_out_data), .src_rdy_o(udp_out_valid), .dst_rdy_i(udp_out_ready) ); //////////////////////////////////////////////////////////////////// @@ -552,6 +555,43 @@ module packet_router .out_data(dsp_frm_data), .out_valid(dsp_frm_valid), .out_ready(dsp_frm_ready) ); + //////////////////////////////////////////////////////////////////// + // UDP TX Protocol machine + //////////////////////////////////////////////////////////////////// + + //dummy signals to connect the components below + wire [18:0] _udp_r2s_data, _udp_s2p_data, _udp_p2s_data, _udp_s2r_data; + wire _udp_r2s_valid, _udp_s2p_valid, _udp_p2s_valid, _udp_s2r_valid; + wire _udp_r2s_ready, _udp_s2p_ready, _udp_p2s_ready, _udp_s2r_ready; + + fifo36_to_fifo19 udp_fifo36_to_fifo19 + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), + .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) ); + + fifo_short #(.WIDTH(19)) udp_shortfifo19_inp + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .datain(_udp_r2s_data), .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready), + .dataout(_udp_s2p_data), .src_rdy_o(_udp_s2p_valid), .dst_rdy_i(_udp_s2p_ready), + .space(), .occupied() ); + + prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .datain(_udp_s2p_data), .src_rdy_i(_udp_s2p_valid), .dst_rdy_o(_udp_s2p_ready), + .dataout(_udp_p2s_data), .src_rdy_o(_udp_p2s_valid), .dst_rdy_i(_udp_p2s_ready) ); + + fifo_short #(.WIDTH(19)) udp_shortfifo19_out + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .datain(_udp_p2s_data), .src_rdy_i(_udp_p2s_valid), .dst_rdy_o(_udp_p2s_ready), + .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready), + .space(), .occupied() ); + + fifo19_to_fifo36 udp_fifo19_to_fifo36 + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), + .f36_dataout(com_out_data), .f36_src_rdy_o(com_out_valid), .f36_dst_rdy_i(com_out_ready) ); + //////////////////////////////////////////////////////////////////// // Assign debugs //////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 83d218a7c..033963ed7 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -442,7 +442,7 @@ module u2_core // Ethernet MAC Slave #6 wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), @@ -458,28 +458,39 @@ module u2_core .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] udp_tx_data, udp_rx_data; - wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; - - udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), - .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), - .debug(debug_udp) ); + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); - + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus -- cgit v1.2.3 From a9390f66b72453adefa642919e5a56056bc28655 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Nov 2010 22:04:36 -0800 Subject: allow any unicast packet through. --- usrp2/simple_gemac/Makefile.srcs | 1 + usrp2/simple_gemac/address_filter_promisc.v | 32 +++++++++++++++++++++++++++++ usrp2/simple_gemac/simple_gemac_rx.v | 10 +++++---- usrp2/simple_gemac/simple_gemac_wb.v | 2 +- 4 files changed, 40 insertions(+), 5 deletions(-) create mode 100644 usrp2/simple_gemac/address_filter_promisc.v diff --git a/usrp2/simple_gemac/Makefile.srcs b/usrp2/simple_gemac/Makefile.srcs index 6480cd5a4..b82e64208 100644 --- a/usrp2/simple_gemac/Makefile.srcs +++ b/usrp2/simple_gemac/Makefile.srcs @@ -17,6 +17,7 @@ delay_line.v \ flow_ctrl_tx.v \ flow_ctrl_rx.v \ address_filter.v \ +address_filter_promisc.v \ ll8_to_txmac.v \ rxmac_to_ll8.v \ miim/eth_miim.v \ diff --git a/usrp2/simple_gemac/address_filter_promisc.v b/usrp2/simple_gemac/address_filter_promisc.v new file mode 100644 index 000000000..6047e7c93 --- /dev/null +++ b/usrp2/simple_gemac/address_filter_promisc.v @@ -0,0 +1,32 @@ + + +module address_filter_promisc + (input clk, + input reset, + input go, + input [7:0] data, + output match, + output done); + + reg [2:0] af_state; + + always @(posedge clk) + if(reset) + af_state <= 0; + else + if(go) + af_state <= (data[0] == 1'b0) ? 1 : 7; + else + case(af_state) + 1 : af_state <= 2; + 2 : af_state <= 3; + 3 : af_state <= 4; + 4 : af_state <= 5; + 5 : af_state <= 6; + 6, 7 : af_state <= 0; + endcase // case (af_state) + + assign match = (af_state==6); + assign done = (af_state==6)|(af_state==7); + +endmodule // address_filter_promisc diff --git a/usrp2/simple_gemac/simple_gemac_rx.v b/usrp2/simple_gemac/simple_gemac_rx.v index b02bb0758..32f517bb3 100644 --- a/usrp2/simple_gemac/simple_gemac_rx.v +++ b/usrp2/simple_gemac/simple_gemac_rx.v @@ -56,10 +56,10 @@ module simple_gemac_rx else rx_ack <= (rx_state == RX_GOODFRAME); - wire is_ucast, is_bcast, is_mcast, is_pause; - wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | - (pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all; - + wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast; + wire keep_packet = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | + (pass_bcast & is_bcast) | (pass_pause & is_pause); + assign rx_data = rxd_del; assign rx_error = (rx_state == RX_ERROR); @@ -79,6 +79,8 @@ module simple_gemac_rx .address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done()); address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), .address(48'h0180_c200_0001), .match(is_pause), .done()); + address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), + .match(is_any_ucast), .done()); always @(posedge rx_clk) go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5); diff --git a/usrp2/simple_gemac/simple_gemac_wb.v b/usrp2/simple_gemac/simple_gemac_wb.v index 6df277e3e..f4ecd7f08 100644 --- a/usrp2/simple_gemac/simple_gemac_wb.v +++ b/usrp2/simple_gemac/simple_gemac_wb.v @@ -41,7 +41,7 @@ module simple_gemac_wb wire [6:0] misc_settings; assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings; - wb_reg #(.ADDR(0),.DEFAULT(7'b0111001)) + wb_reg #(.ADDR(0),.DEFAULT(7'b0111011)) wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(misc_settings) ); wb_reg #(.ADDR(1),.DEFAULT(0)) -- cgit v1.2.3 From ffdb0ba08887e9bf9df600138d1e209e37d043db Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 23 Nov 2010 09:17:47 -0800 Subject: packet_router: mux the crossbar input after the protocol framer --- usrp2/fifo/packet_router.v | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 0ccf665f9..810d0aada 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -209,7 +209,7 @@ module packet_router fifo36_mux _com_output_combiner1( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(crs_inp_data), .src0_rdy_i(crs_inp_valid), .dst0_rdy_o(crs_inp_ready), + .data0_i(32'b0), .src0_rdy_i(1'b0), .dst0_rdy_o(), //mux out from dsp1 can go here .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) ); @@ -564,6 +564,9 @@ module packet_router wire _udp_r2s_valid, _udp_s2p_valid, _udp_p2s_valid, _udp_s2r_valid; wire _udp_r2s_ready, _udp_s2p_ready, _udp_p2s_ready, _udp_s2r_ready; + wire [35:0] _com_out_data; + wire _com_out_valid, _com_out_ready; + fifo36_to_fifo19 udp_fifo36_to_fifo19 (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), @@ -590,7 +593,14 @@ module packet_router fifo19_to_fifo36 udp_fifo19_to_fifo36 (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), - .f36_dataout(com_out_data), .f36_src_rdy_o(com_out_valid), .f36_dst_rdy_i(com_out_ready) ); + .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) ); + + fifo36_mux com_out_mux( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(crs_inp_data), .src0_rdy_i(crs_inp_valid), .dst0_rdy_o(crs_inp_ready), + .data1_i(_com_out_data), .src1_rdy_i(_com_out_valid), .dst1_rdy_o(_com_out_ready), + .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) + ); //////////////////////////////////////////////////////////////////// // Assign debugs -- cgit v1.2.3 From 2a2e33575743b4a162935569321d47030f4bd5d0 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 23 Nov 2010 15:30:11 -0800 Subject: reduce warnings, modernize testbench --- usrp2/simple_gemac/eth_tasks_f36.v | 6 +++--- usrp2/simple_gemac/simple_gemac_wb.v | 27 +++++++++++++------------ usrp2/simple_gemac/simple_gemac_wrapper.build | 2 +- usrp2/simple_gemac/simple_gemac_wrapper19.build | 2 +- usrp2/simple_gemac/simple_gemac_wrapper19_tb.v | 10 ++++----- usrp2/simple_gemac/simple_gemac_wrapper_tb.v | 6 +----- 6 files changed, 25 insertions(+), 28 deletions(-) diff --git a/usrp2/simple_gemac/eth_tasks_f36.v b/usrp2/simple_gemac/eth_tasks_f36.v index efd72778b..dc64971d4 100644 --- a/usrp2/simple_gemac/eth_tasks_f36.v +++ b/usrp2/simple_gemac/eth_tasks_f36.v @@ -4,11 +4,11 @@ task SendFlowCtrl; input [15:0] fc_len; begin $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time); - pause_time <= fc_len; + //pause_time <= fc_len; @(posedge eth_clk); - pause_req <= 1; + //pause_req <= 1; @(posedge eth_clk); - pause_req <= 0; + //pause_req <= 0; $display("Sent Flow Control"); end endtask // SendFlowCtrl diff --git a/usrp2/simple_gemac/simple_gemac_wb.v b/usrp2/simple_gemac/simple_gemac_wb.v index f4ecd7f08..1ef38be11 100644 --- a/usrp2/simple_gemac/simple_gemac_wb.v +++ b/usrp2/simple_gemac/simple_gemac_wb.v @@ -1,16 +1,17 @@ module wb_reg #(parameter ADDR=0, - parameter DEFAULT=0) + parameter DEFAULT=0, + parameter WIDTH=32) (input clk, input rst, input [5:0] adr, input wr_acc, - input [31:0] dat_i, output reg [31:0] dat_o); + input [31:0] dat_i, output reg [WIDTH-1:0] dat_o); always @(posedge clk) if(rst) dat_o <= DEFAULT; else if(wr_acc & (adr == ADDR)) - dat_o <= dat_i; + dat_o <= dat_i[WIDTH-1:0]; endmodule // wb_reg @@ -41,19 +42,19 @@ module simple_gemac_wb wire [6:0] misc_settings; assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings; - wb_reg #(.ADDR(0),.DEFAULT(7'b0111011)) + wb_reg #(.ADDR(0),.DEFAULT(7'b0111011),.WIDTH(7)) wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(misc_settings) ); - wb_reg #(.ADDR(1),.DEFAULT(0)) + wb_reg #(.ADDR(1),.DEFAULT(0),.WIDTH(16)) wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) ); - wb_reg #(.ADDR(2),.DEFAULT(0)) + wb_reg #(.ADDR(2),.DEFAULT(0),.WIDTH(32)) wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) ); - wb_reg #(.ADDR(3),.DEFAULT(0)) + wb_reg #(.ADDR(3),.DEFAULT(0),.WIDTH(16)) wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) ); - wb_reg #(.ADDR(4),.DEFAULT(0)) + wb_reg #(.ADDR(4),.DEFAULT(0),.WIDTH(32)) wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) ); @@ -80,15 +81,15 @@ module simple_gemac_wb reg [15:0] MIIRX_DATA; wire [2:0] MIISTATUS; - wb_reg #(.ADDR(5),.DEFAULT(0)) + wb_reg #(.ADDR(5),.DEFAULT(0),.WIDTH(9)) wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) ); - wb_reg #(.ADDR(6),.DEFAULT(0)) + wb_reg #(.ADDR(6),.DEFAULT(0),.WIDTH(13)) wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(MIIADDRESS) ); - wb_reg #(.ADDR(7),.DEFAULT(0)) + wb_reg #(.ADDR(7),.DEFAULT(0),.WIDTH(16)) wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(CtrlData) ); @@ -133,11 +134,11 @@ module simple_gemac_wb .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) ); - wb_reg #(.ADDR(11),.DEFAULT(0)) + wb_reg #(.ADDR(11),.DEFAULT(0),.WIDTH(16)) wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(pause_time) ); - wb_reg #(.ADDR(12),.DEFAULT(0)) + wb_reg #(.ADDR(12),.DEFAULT(0),.WIDTH(16)) wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(pause_thresh) ); diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.build b/usrp2/simple_gemac/simple_gemac_wrapper.build index 30f65ab17..9293deca6 100755 --- a/usrp2/simple_gemac/simple_gemac_wrapper.build +++ b/usrp2/simple_gemac/simple_gemac_wrapper.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v +iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.build b/usrp2/simple_gemac/simple_gemac_wrapper19.build index 4be0aac1f..b9475baa2 100755 --- a/usrp2/simple_gemac/simple_gemac_wrapper19.build +++ b/usrp2/simple_gemac/simple_gemac_wrapper19.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v +iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v index 7d57542dc..b61d60d30 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v @@ -44,12 +44,12 @@ module simple_gemac_wrapper19_tb; reg wb_stb=0, wb_cyc=0, wb_we=0; wire wb_ack; - reg [18:0] tx_f19_data=0; + reg [19:0] tx_f19_data=0; reg tx_f19_src_rdy = 0; wire tx_f19_dst_rdy; - wire [35:0] rx_f36_data; - wire rx_f36_src_rdy; - wire rx_f36_dst_rdy = 1; + wire [35:0] rx_f19_data; + wire rx_f19_src_rdy; + wire rx_f19_dst_rdy = 1; simple_gemac_wrapper19 simple_gemac_wrapper19 (.clk125(eth_clk), .reset(reset), @@ -59,7 +59,7 @@ module simple_gemac_wrapper19_tb; .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), //.pause_req(pause_req), .pause_time(pause_time), - .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy), + .sys_clk(sys_clk), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we), diff --git a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v index 26a471a49..0aadc7e93 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v @@ -24,9 +24,6 @@ module simple_gemac_wrapper_tb; wire [7:0] rx_data, tx_data; - reg [15:0] pause_time; - reg pause_req = 0; - wire GMII_RX_CLK = GMII_GTX_CLK; reg [7:0] FORCE_DAT_ERR = 0; @@ -47,7 +44,7 @@ module simple_gemac_wrapper_tb; reg [35:0] tx_f36_data=0; reg tx_f36_src_rdy = 0; wire tx_f36_dst_rdy; - wire rx_f36_data; + wire [35:0] rx_f36_data; wire rx_f36_src_rdy; wire rx_f36_dst_rdy = 1; @@ -57,7 +54,6 @@ module simple_gemac_wrapper_tb; .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy), .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy), -- cgit v1.2.3 From 0be843e19db7e96984942a3f025ae453fecd401c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 23 Nov 2010 18:13:36 -0800 Subject: packet_router: program the dsp udp port and ip addr through setting registers --- usrp2/fifo/packet_router.v | 64 +++++++++++++++++++++-------------------- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- 2 files changed, 34 insertions(+), 32 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 810d0aada..ba5a2378c 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -2,7 +2,7 @@ module packet_router #( parameter BUF_SIZE = 9, parameter UDP_BASE = 0, - parameter STATUS_BASE = 0 + parameter CTRL_BASE = 0 ) ( //wishbone interface for memory mapped CPU frames @@ -54,38 +54,31 @@ module packet_router //////////////////////////////////////////////////////////////////// // CPU interface to this packet router //////////////////////////////////////////////////////////////////// - wire [35:0] cpu_inp_data; - wire cpu_inp_valid; - wire cpu_inp_ready; - wire [35:0] cpu_out_data; - wire cpu_out_valid; - wire cpu_out_ready; + wire [35:0] cpu_inp_data, cpu_out_data; + wire cpu_inp_valid, cpu_out_valid; + wire cpu_inp_ready, cpu_out_ready; //////////////////////////////////////////////////////////////////// // Communication interfaces //////////////////////////////////////////////////////////////////// - wire [35:0] com_inp_data; - wire com_inp_valid; - wire com_inp_ready; - wire [35:0] com_out_data; - wire com_out_valid; - wire com_out_ready; - wire [35:0] udp_out_data; - wire udp_out_valid; - wire udp_out_ready; + wire [35:0] com_inp_data, com_out_data, udp_out_data; + wire com_inp_valid, com_out_valid, udp_out_valid; + wire com_inp_ready, com_out_ready, udp_out_ready; //////////////////////////////////////////////////////////////////// - // status and control handshakes + // Control signals (setting registers and status signals) + // - handshake lines for the CPU communication + // - setting registers to program the inspector //////////////////////////////////////////////////////////////////// reg cpu_out_hs_ctrl; reg cpu_inp_hs_ctrl; reg master_mode_flag; reg [BUF_SIZE-1:0] cpu_inp_line_count; - reg [31:0] my_ip_addr; + //setting register to misc control + handshakes wire [31:0] control; wire control_changed; - setting_reg #(.my_addr(STATUS_BASE)) sreg( + setting_reg #(.my_addr(CTRL_BASE)) sreg_ctrl( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), .out(control),.changed(control_changed) @@ -97,20 +90,29 @@ module packet_router cpu_inp_hs_ctrl <= control[1]; master_mode_flag <= control[2]; cpu_inp_line_count <= control[BUF_SIZE-1+16:0+16]; - case (control[5:4]) - 2'b01: - my_ip_addr[15:0] <= control[31:16]; - 2'b10: - my_ip_addr[31:16] <= control[31:16]; - endcase end + //setting register to program the IP address + wire [31:0] my_ip_addr; + setting_reg #(.my_addr(CTRL_BASE+1)) sreg_ip_addr( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out(my_ip_addr),.changed() + ); + + //setting register to program the UDP data ports + wire [15:0] dsp0_udp_port, dsp1_udp_port; + setting_reg #(.my_addr(CTRL_BASE+2)) sreg_udp_ports( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out({dsp1_udp_port, dsp0_udp_port}),.changed() + ); + + //assign status output signals wire cpu_out_hs_stat; assign status[0] = cpu_out_hs_stat; - wire [BUF_SIZE-1:0] cpu_out_line_count; assign status[BUF_SIZE-1+16:0+16] = cpu_out_line_count; - wire cpu_inp_hs_stat; assign status[1] = cpu_inp_hs_stat; @@ -400,10 +402,10 @@ module packet_router //Inspection logic: wire com_inp_dregs_is_data = 1'b1 - && (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 - && (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP - && (com_insp_dregs[9][15:0] == 16'd49153) //UDP data port - && (com_inp_data[31:0] != 32'h0) //VRT hdr non-zero + && (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 + && (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP + && (com_insp_dregs[9][15:0] == dsp0_udp_port) //UDP data port + && (com_inp_data[15:0] != 16'h0) //VRT packet size ; wire com_inp_dregs_my_ip_match = (my_ip_addr == com_insp_dregs[8][31:0])? 1'b1 : 1'b0; diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 033963ed7..01a7b324d 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -365,7 +365,7 @@ module u2_core wire [31:0] router_debug; - packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .STATUS_BASE(SR_BUF_POOL)) packet_router + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), -- cgit v1.2.3 From 1fbd220503a81c6e9e5055457539628a48822f54 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 23 Nov 2010 18:37:48 -0800 Subject: packet_router: it makes more sense to connect the control flags this way now --- usrp2/fifo/packet_router.v | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index ba5a2378c..ee20aceee 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -70,27 +70,20 @@ module packet_router // - handshake lines for the CPU communication // - setting registers to program the inspector //////////////////////////////////////////////////////////////////// - reg cpu_out_hs_ctrl; - reg cpu_inp_hs_ctrl; - reg master_mode_flag; - reg [BUF_SIZE-1:0] cpu_inp_line_count; //setting register to misc control + handshakes wire [31:0] control; - wire control_changed; setting_reg #(.my_addr(CTRL_BASE)) sreg_ctrl( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), - .out(control),.changed(control_changed) + .out(control),.changed() ); - //grab the pertinent control settings - always @(posedge control_changed) begin - cpu_out_hs_ctrl <= control[0]; - cpu_inp_hs_ctrl <= control[1]; - master_mode_flag <= control[2]; - cpu_inp_line_count <= control[BUF_SIZE-1+16:0+16]; - end + //connect the pertinent control settings + wire cpu_out_hs_ctrl = control[0]; + wire cpu_inp_hs_ctrl = control[1]; + wire master_mode_flag = control[2]; + wire [BUF_SIZE-1:0] cpu_inp_line_count = control[BUF_SIZE-1+16:0+16]; //setting register to program the IP address wire [31:0] my_ip_addr; -- cgit v1.2.3 From 31110771abf455e9611fc2f650fc0427cedf050e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 23 Nov 2010 20:17:11 -0800 Subject: packet_router: modification for sequence number and vrt header offset --- usrp2/fifo/packet_router.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index ee20aceee..321991c0f 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -365,7 +365,7 @@ module packet_router localparam COM_INSP_DEST_FP_OTHER = 1; localparam COM_INSP_DEST_SP_BOTH = 2; - localparam COM_INSP_MAX_NUM_DREGS = 12; //padded_eth + ip + udp + vrt_hdr + localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at //output inspector interfaces -- cgit v1.2.3 From 3329e1cef4a54de7752c2bef1524d832c888010c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 24 Nov 2010 20:27:08 -0800 Subject: packet_router: split the control register into misc, cpu hs out, cpu hs inp --- usrp2/fifo/packet_router.v | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 321991c0f..09ded1c03 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -71,20 +71,15 @@ module packet_router // - setting registers to program the inspector //////////////////////////////////////////////////////////////////// - //setting register to misc control + handshakes - wire [31:0] control; - setting_reg #(.my_addr(CTRL_BASE)) sreg_ctrl( + //setting register to misc control + wire [31:0] _sreg_misc_ctrl; + wire master_mode_flag = _sreg_misc_ctrl[0]; + setting_reg #(.my_addr(CTRL_BASE+0)) sreg_misc_ctrl( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), - .out(control),.changed() + .out(_sreg_misc_ctrl),.changed() ); - //connect the pertinent control settings - wire cpu_out_hs_ctrl = control[0]; - wire cpu_inp_hs_ctrl = control[1]; - wire master_mode_flag = control[2]; - wire [BUF_SIZE-1:0] cpu_inp_line_count = control[BUF_SIZE-1+16:0+16]; - //setting register to program the IP address wire [31:0] my_ip_addr; setting_reg #(.my_addr(CTRL_BASE+1)) sreg_ip_addr( @@ -101,6 +96,25 @@ module packet_router .out({dsp1_udp_port, dsp0_udp_port}),.changed() ); + //setting register for CPU output handshake + wire [31:0] _sreg_cpu_out_ctrl; + wire cpu_out_hs_ctrl = _sreg_cpu_out_ctrl[0]; + setting_reg #(.my_addr(CTRL_BASE+3)) sreg_cpu_out_ctrl( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out(_sreg_cpu_out_ctrl),.changed() + ); + + //setting register for CPU input handshake + wire [31:0] _sreg_cpu_inp_ctrl; + wire cpu_inp_hs_ctrl = _sreg_cpu_inp_ctrl[0]; + wire [BUF_SIZE-1:0] cpu_inp_line_count = _sreg_cpu_inp_ctrl[BUF_SIZE-1+16:0+16]; + setting_reg #(.my_addr(CTRL_BASE+4)) sreg_cpu_inp_ctrl( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out(_sreg_cpu_inp_ctrl),.changed() + ); + //assign status output signals wire cpu_out_hs_stat; assign status[0] = cpu_out_hs_stat; -- cgit v1.2.3 From 53a57560a35f57d043704f0a92055456faf10b3e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 24 Nov 2010 20:31:32 -0800 Subject: packet_router: added status readback for mode, incremented compat number --- usrp2/fifo/packet_router.v | 1 + usrp2/top/u2_rev3/u2_core_udp.v | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 09ded1c03..6cf022b11 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -122,6 +122,7 @@ module packet_router assign status[BUF_SIZE-1+16:0+16] = cpu_out_line_count; wire cpu_inp_hs_stat; assign status[1] = cpu_inp_hs_stat; + assign status[8] = master_mode_flag; //for the host to readback //////////////////////////////////////////////////////////////////// // Communication input source crossbar diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 01a7b324d..c85e81140 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -426,7 +426,7 @@ module u2_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd3; + localparam compat_num = 32'd4; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), -- cgit v1.2.3 From fa42f88bf3007909a56c3582fe58097edaf2e074 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 6 Dec 2010 17:28:12 -0800 Subject: zpu: added a zpu + wishbone opencore and integrated into top level --- usrp2/opencores/Makefile.srcs | 8 + usrp2/opencores/zpu/core/zpu_config.vhd | 20 + usrp2/opencores/zpu/core/zpu_core.vhd | 948 +++++++++++++++++++++++++ usrp2/opencores/zpu/core/zpupkg.vhd | 168 +++++ usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd | 86 +++ usrp2/opencores/zpu/wishbone/zpu_system.vhd | 105 +++ usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd | 83 +++ usrp2/opencores/zpu/zpu_top_pkg.vhd | 46 ++ usrp2/opencores/zpu/zpu_wb_top.vhd | 72 ++ usrp2/top/u2_rev3/u2_core_udp.v | 28 +- 10 files changed, 1554 insertions(+), 10 deletions(-) create mode 100644 usrp2/opencores/zpu/core/zpu_config.vhd create mode 100644 usrp2/opencores/zpu/core/zpu_core.vhd create mode 100644 usrp2/opencores/zpu/core/zpupkg.vhd create mode 100644 usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd create mode 100644 usrp2/opencores/zpu/wishbone/zpu_system.vhd create mode 100644 usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd create mode 100644 usrp2/opencores/zpu/zpu_top_pkg.vhd create mode 100644 usrp2/opencores/zpu/zpu_wb_top.vhd diff --git a/usrp2/opencores/Makefile.srcs b/usrp2/opencores/Makefile.srcs index 284578b39..838b1b813 100644 --- a/usrp2/opencores/Makefile.srcs +++ b/usrp2/opencores/Makefile.srcs @@ -25,4 +25,12 @@ spi/rtl/verilog/spi_defines.v \ spi/rtl/verilog/spi_shift.v \ spi/rtl/verilog/spi_top.v \ spi/rtl/verilog/spi_top16.v \ +zpu/zpu_top_pkg.vhd \ +zpu/zpu_wb_top.vhd \ +zpu/wishbone/wishbone_pkg.vhd \ +zpu/wishbone/zpu_system.vhd \ +zpu/wishbone/zpu_wb_bridge.vhd \ +zpu/core/zpu_config.vhd \ +zpu/core/zpu_core.vhd \ +zpu/core/zpupkg.vhd \ )) diff --git a/usrp2/opencores/zpu/core/zpu_config.vhd b/usrp2/opencores/zpu/core/zpu_config.vhd new file mode 100644 index 000000000..61949c592 --- /dev/null +++ b/usrp2/opencores/zpu/core/zpu_config.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; + +end zpu_config; diff --git a/usrp2/opencores/zpu/core/zpu_core.vhd b/usrp2/opencores/zpu/core/zpu_core.vhd new file mode 100644 index 000000000..2450f14d3 --- /dev/null +++ b/usrp2/opencores/zpu/core/zpu_core.vhd @@ -0,0 +1,948 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_Interrupt, +State_InsnFetch +); + +type StateType is +( +State_Idle, -- using first state first on the list out of paranoia +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult6, +State_Mult4, +State_BinaryOpResult +); + + +signal pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal stackA : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); +signal multResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult3 : std_logic_vector(wordSize-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); +signal multA : std_logic_vector(wordSize-1 downto 0); +signal multB : std_logic_vector(wordSize-1 downto 0); +signal stackB : std_logic_vector(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; +signal mem_busy : std_logic; +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +signal out_mem_req : std_logic; + +signal inInterrupt : std_logic; + +-- state machine. + +begin + + zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; + zpu_status(31) <= '1'; + zpu_status(39 downto 32) <= trace_opcode; + zpu_status(40) <= '1' when (state = State_Idle) else '0'; + zpu_status(62) <= '1'; + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + mem_req <= out_mem_req; + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable tSpOffset : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= spStart(maxAddrBitIncIO downto minAddrBit); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_we <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + out_mem_req <= '0'; + mem_addr <= (others => DontCareValue); + mem_write <= (others => DontCareValue); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); + trace_pc <= pc; + trace_sp <= sp; + trace_topOfStack <= stackA; + trace_topOfStackB <= stackB; + begin_inst <= '0'; + + -- we terminate the requeset as soon as we get acknowledge + if mem_ack = '1' then + out_mem_req <= '0'; + mem_we <= '0'; + end if; + + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if mem_busy='0' then + mem_addr <= sp; + out_mem_req <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if mem_busy='0' then + stackA <= mem_read; + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if mem_busy='0' then + stackB <= mem_read; + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=tOpcode(3 downto 0); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + else + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + end if; + else + insn <= insn; + end if; + when State_StoreSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= sp+spOffset; + mem_write <= stackA; + stackA <= stackB; + sp <= incSp; + else + insn <= insn; + end if; + + + when State_LoadSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_Emulate => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Callpcrel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Call => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_AddSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + out_mem_req <= '1'; + mem_addr <= sp+spOffset; + else + insn <= insn; + end if; + when State_PushSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_PopPC => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopPCRel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_Add => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Sub => + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + when State_Pop => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + else + insn <= insn; + end if; + when State_PopDown => + if mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Or => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_And => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Eq => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Ulessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Lessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Load => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when State_Dup => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_DupStackB => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_Store => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= stackB; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= incIncSp; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + else + insn <= insn; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + when State_Storeb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when others => +-- sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if mem_busy='0' then + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if mem_busy='0' then + state <= State_LoadSP3; + out_mem_req <= '1'; + mem_addr <= sp+spOffset+1; + end if; + when State_LoadSP3 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= mem_read; + end if; + when State_AddSP2 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + mem_read; + end if; + when State_Load2 => + if mem_busy='0' then + stackA <= mem_read; + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if mem_busy='0' then + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= mem_read; + mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; + out_mem_req <= '1'; + mem_we <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if mem_busy='0' then + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt + inInterrupt <= '1'; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + + report "ZPU jumped to interrupt!" severity note; + else + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + stackA <= multResult3; + state <= State_Mult6; + when State_Mult6 => + if mem_busy='0' then + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + if mem_busy='0' then + -- NB!!!! we know that the memory isn't busy at this point!!!! + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + stackA <= binaryOpResult; + state <= State_Popped; + end if; + when State_Popped => + if mem_busy='0' then + pc <= pc + 1; + stackB <= mem_read; + state <= State_Execute; + end if; + when others => +-- sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/usrp2/opencores/zpu/core/zpupkg.vhd b/usrp2/opencores/zpu/core/zpupkg.vhd new file mode 100644 index 000000000..1a01563b8 --- /dev/null +++ b/usrp2/opencores/zpu/core/zpupkg.vhd @@ -0,0 +1,168 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; + +library work; +use work.zpu_config.all; + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + component dram is + port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component; + + component zpu_core is + port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); + end component; + + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + sample : in std_logic; + reset : in std_logic; + counter : out std_logic_vector(63 downto 0)); + end component; + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); + constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); + constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); + constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); + + + + constant OpCode_Size : integer := 8; + + + +end zpupkg; diff --git a/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd b/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd new file mode 100644 index 000000000..97240def6 --- /dev/null +++ b/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd @@ -0,0 +1,86 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package wishbone_pkg is + + type wishbone_bus_in is record + adr : std_logic_vector(31 downto 0); + sel : std_logic_vector(3 downto 0); + we : std_logic; + dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we' + cyc : std_logic; + stb : std_logic; + end record; + + type wishbone_bus_out is record + dat : std_logic_vector(31 downto 0); + ack : std_logic; + end record; + + type wishbone_bus is record + insig : wishbone_bus_in; + outsig : wishbone_bus_out; + end record; + + component atomic32_access is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from CPU interface + wb_16_i : in wishbone_bus_in; + wb_16_o : out wishbone_bus_out; + -- Wishbone to FPGA registers and ethernet core + wb_32_i : in wishbone_bus_out; + wb_32_o : out wishbone_bus_in); + end component; + + component eth_access_corr is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from Wishbone MUX + eth_raw_o : out wishbone_bus_out; + eth_raw_i : in wishbone_bus_in; + + -- Wishbone ethernet core + eth_slave_i : in wishbone_bus_out; + eth_slave_o : out wishbone_bus_in); + end component; + + +end wishbone_pkg; diff --git a/usrp2/opencores/zpu/wishbone/zpu_system.vhd b/usrp2/opencores/zpu/wishbone/zpu_system.vhd new file mode 100644 index 000000000..294651fe2 --- /dev/null +++ b/usrp2/opencores/zpu/wishbone/zpu_system.vhd @@ -0,0 +1,105 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +library work; +use work.zpu_top_pkg.all; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; + +entity zpu_system is + generic( + simulate : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + + -- ZPU Control signals + enable : in std_logic; + interrupt : in std_logic; + + zpu_status : out std_logic_vector(63 downto 0); + + -- wishbone interfaces + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); +end zpu_system; + +architecture behave of zpu_system is + +signal mem_req : std_logic; +signal mem_we : std_logic; +signal mem_ack : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + +begin + + my_zpu_core: + zpu_core port map ( + clk => cpu_clk, + areset => areset, + enable => enable, + mem_req => mem_req, + mem_we => mem_we, + mem_ack => mem_ack, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => out_mem_addr, + mem_writeMask => mem_writeMask, + interrupt => interrupt, + zpu_status => zpu_status, + break => open); + + my_zpu_wb_bridge: + zpu_wb_bridge port map ( + clk => cpu_clk, + areset => areset, + mem_req => mem_req, + mem_we => mem_we, + mem_ack => mem_ack, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => out_mem_addr, + mem_writeMask => mem_writeMask, + zpu_wb_i => zpu_wb_i, + zpu_wb_o => zpu_wb_o); + +end behave; diff --git a/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd b/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd new file mode 100644 index 000000000..57736b6e6 --- /dev/null +++ b/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd @@ -0,0 +1,83 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_top_pkg.all; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; + +entity zpu_wb_bridge is + port ( -- Native ZPU interface + clk : in std_logic; + areset : in std_logic; + + mem_req : in std_logic; + mem_we : in std_logic; + mem_ack : out std_logic; + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0); + + -- Wishbone from ZPU + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); + +end zpu_wb_bridge; + +architecture behave of zpu_wb_bridge is + +begin + + mem_read <= zpu_wb_i.dat; + mem_ack <= zpu_wb_i.ack; + + zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0); + zpu_wb_o.dat <= mem_write; + zpu_wb_o.sel <= mem_writeMask; + zpu_wb_o.stb <= mem_req; + zpu_wb_o.cyc <= mem_req; + zpu_wb_o.we <= mem_we; + +end behave; + + + + + diff --git a/usrp2/opencores/zpu/zpu_top_pkg.vhd b/usrp2/opencores/zpu/zpu_top_pkg.vhd new file mode 100644 index 000000000..23ff48c39 --- /dev/null +++ b/usrp2/opencores/zpu/zpu_top_pkg.vhd @@ -0,0 +1,46 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpupkg.all; +use work.zpu_config.all; +use work.wishbone_pkg.all; + +package zpu_top_pkg is + component zpu_wb_bridge is + port ( -- Native ZPU interface + clk : in std_logic; + areset : in std_logic; + + mem_req : in std_logic; + mem_we : in std_logic; + mem_ack : out std_logic; + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0); + + -- Wishbone from ZPU + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); + end component; + + component zpu_system is + generic( + simulate : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + + -- ZPU Control signals + enable : in std_logic; + interrupt : in std_logic; + + zpu_status : out std_logic_vector(63 downto 0); + + -- wishbone interfaces + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); + end component; + +end zpu_top_pkg; diff --git a/usrp2/opencores/zpu/zpu_wb_top.vhd b/usrp2/opencores/zpu/zpu_wb_top.vhd new file mode 100644 index 000000000..d3cf96c9c --- /dev/null +++ b/usrp2/opencores/zpu/zpu_wb_top.vhd @@ -0,0 +1,72 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_top_pkg.all; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; + +------------------------------------------------------------------------ +-- Top level ZPU + wishbone componenent to use in a verilog design: +-- zpu_wb_top wraps around the zpu_system component. +-- All IO lines are exposed as std_logic for verilog. +------------------------------------------------------------------------ +entity zpu_wb_top is + generic ( + dat_w: integer := 32; + adr_w: integer := 16; + sel_w: integer := 4 + ); + port ( + clk: in std_logic; + rst: in std_logic; + enb: in std_logic; + + -- wishbone interface + dat_i: in std_logic_vector(dat_w-1 downto 0); + ack_i: in std_logic; + adr_o: out std_logic_vector(adr_w-1 downto 0); + sel_o: out std_logic_vector(sel_w-1 downto 0); + we_o: out std_logic; + dat_o: out std_logic_vector(dat_w-1 downto 0); + cyc_o: out std_logic; + stb_o: out std_logic; + + -- misc zpu signals + interrupt: in std_logic + ); + +end zpu_wb_top; + +architecture syn of zpu_wb_top is + +--wishbone interface (records) +signal zpu_wb_i: wishbone_bus_out; +signal zpu_wb_o: wishbone_bus_in; + +begin + +--assign wishbone signals to records +zpu_wb_i.dat <= dat_i; +zpu_wb_i.ack <= ack_i; + +adr_o <= zpu_wb_o.adr(adr_w-1 downto 0); +sel_o <= zpu_wb_o.sel; +we_o <= zpu_wb_o.we; +dat_o <= zpu_wb_o.dat; +cyc_o <= zpu_wb_o.cyc; +stb_o <= zpu_wb_o.stb; + +--instantiate the zpu system +zpu_system0: zpu_system port map( + cpu_clk => clk, + areset => rst, + enable => enb, + interrupt => interrupt, + zpu_wb_i => zpu_wb_i, + zpu_wb_o => zpu_wb_o +); + +end architecture syn; diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index c85e81140..f90f3b193 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -308,18 +308,26 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .if_adr(if_adr), - .if_dat(if_dat), +// aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) +// aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), +// // Instruction Wishbone bus to I-RAM +// .if_adr(if_adr), +// .if_dat(if_dat), +// // Data Wishbone bus to system bus fabric +// .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), +// .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), +// // Interrupts and exceptions +// .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + //assign bus_error = m0_err | m0_rty; + + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(1'b1), // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; + .interrupt(proc_int)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone -- cgit v1.2.3 From d6a07130299b1727a2210809fa9efe515ce37c24 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 6 Dec 2010 18:55:20 -0800 Subject: zpu: shrank the ram size and address bus to 16k --- usrp2/top/u2_rev3/u2_core_udp.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index f90f3b193..787aa4c2f 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -3,7 +3,7 @@ // //////////////////////////////////////////////////////////////////////////////// module u2_core - #(parameter RAM_SIZE=32768) + #(parameter RAM_SIZE=16384, parameter RAM_AW=14) (// Clocks input dsp_clk, input wb_clk, @@ -292,7 +292,7 @@ module u2_core wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we; wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), @@ -334,10 +334,10 @@ module u2_core // I-port connects directly to processor and ram loader wire flush_icache; - ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), @@ -345,7 +345,7 @@ module u2_core .if_adr(if_adr), .if_data(if_dat), - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), .flush_icache(flush_icache)); -- cgit v1.2.3 From b3c3bc9da17e4536cb54143118aca8d7c0450c57 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 6 Dec 2010 19:29:26 -0800 Subject: zpu: brought status signal out to top level --- usrp2/opencores/zpu/zpu_wb_top.vhd | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/usrp2/opencores/zpu/zpu_wb_top.vhd b/usrp2/opencores/zpu/zpu_wb_top.vhd index d3cf96c9c..9f4b75843 100644 --- a/usrp2/opencores/zpu/zpu_wb_top.vhd +++ b/usrp2/opencores/zpu/zpu_wb_top.vhd @@ -35,7 +35,8 @@ entity zpu_wb_top is stb_o: out std_logic; -- misc zpu signals - interrupt: in std_logic + interrupt: in std_logic; + zpu_status: out std_logic_vector(63 downto 0) ); end zpu_wb_top; @@ -65,6 +66,7 @@ zpu_system0: zpu_system port map( areset => rst, enable => enb, interrupt => interrupt, + zpu_status => zpu_status, zpu_wb_i => zpu_wb_i, zpu_wb_o => zpu_wb_o ); -- cgit v1.2.3 From f2a453f7a04bf397e317ce9aa885a00d629fad7f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 6 Dec 2010 23:19:26 -0800 Subject: zpu: moved stack pointer and made connection for status --- usrp2/opencores/zpu/core/zpu_config.vhd | 2 +- usrp2/top/u2_rev3/u2_core_udp.v | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/opencores/zpu/core/zpu_config.vhd b/usrp2/opencores/zpu/core/zpu_config.vhd index 61949c592..796c5b75d 100644 --- a/usrp2/opencores/zpu/core/zpu_config.vhd +++ b/usrp2/opencores/zpu/core/zpu_config.vhd @@ -15,6 +15,6 @@ package zpu_config is -- start byte address of stack. -- point to top of RAM - 2*words - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"0003ff8"; end zpu_config; diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 787aa4c2f..26e2cc4ab 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -321,13 +321,14 @@ module u2_core //assign bus_error = m0_err | m0_rty; + wire [63:0] zpu_status; zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(1'b1), // Data Wishbone bus to system bus fabric .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .interrupt(proc_int)); + .zpu_status(zpu_status), .interrupt(proc_int)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone -- cgit v1.2.3 From 7aad7adc5a819ae29389cf61d552cf2157986880 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 8 Dec 2010 14:24:04 -0800 Subject: zpu: set all the address widths to 16, grumble --- usrp2/opencores/zpu/core/zpu_config.vhd | 4 ++-- usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd | 2 +- usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd | 2 +- usrp2/opencores/zpu/zpu_wb_top.vhd | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/usrp2/opencores/zpu/core/zpu_config.vhd b/usrp2/opencores/zpu/core/zpu_config.vhd index 796c5b75d..f7743d602 100644 --- a/usrp2/opencores/zpu/core/zpu_config.vhd +++ b/usrp2/opencores/zpu/core/zpu_config.vhd @@ -11,10 +11,10 @@ package zpu_config is -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) - constant maxAddrBitIncIO : integer := 27; + constant maxAddrBitIncIO : integer := 15; -- start byte address of stack. -- point to top of RAM - 2*words - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"0003ff8"; + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"3ff8"; end zpu_config; diff --git a/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd b/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd index 97240def6..375c9ac7e 100644 --- a/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd +++ b/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd @@ -39,7 +39,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; package wishbone_pkg is type wishbone_bus_in is record - adr : std_logic_vector(31 downto 0); + adr : std_logic_vector(15 downto 0); sel : std_logic_vector(3 downto 0); we : std_logic; dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we' diff --git a/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd b/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd index 57736b6e6..104ee10b8 100644 --- a/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd +++ b/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd @@ -68,7 +68,7 @@ begin mem_read <= zpu_wb_i.dat; mem_ack <= zpu_wb_i.ack; - zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0); + zpu_wb_o.adr <= out_mem_addr; zpu_wb_o.dat <= mem_write; zpu_wb_o.sel <= mem_writeMask; zpu_wb_o.stb <= mem_req; diff --git a/usrp2/opencores/zpu/zpu_wb_top.vhd b/usrp2/opencores/zpu/zpu_wb_top.vhd index 9f4b75843..48e5ee31d 100644 --- a/usrp2/opencores/zpu/zpu_wb_top.vhd +++ b/usrp2/opencores/zpu/zpu_wb_top.vhd @@ -53,7 +53,7 @@ begin zpu_wb_i.dat <= dat_i; zpu_wb_i.ack <= ack_i; -adr_o <= zpu_wb_o.adr(adr_w-1 downto 0); +adr_o <= zpu_wb_o.adr; sel_o <= zpu_wb_o.sel; we_o <= zpu_wb_o.we; dat_o <= zpu_wb_o.dat; -- cgit v1.2.3 From 8c7d238c4fde0c3388aba2f91894076af6c5068a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 10 Dec 2010 11:25:27 -0800 Subject: packet_router: renamed top level files in an attempt to merge cleanly --- usrp2/top/u2_rev3/Makefile | 6 +- usrp2/top/u2_rev3/Makefile.udp | 99 ------ usrp2/top/u2_rev3/u2_core.v | 459 +++++++++++-------------- usrp2/top/u2_rev3/u2_core_udp.v | 736 ---------------------------------------- 4 files changed, 209 insertions(+), 1091 deletions(-) delete mode 100644 usrp2/top/u2_rev3/Makefile.udp delete mode 100644 usrp2/top/u2_rev3/u2_core_udp.v diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 68c296b9b..99effb038 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -6,7 +6,7 @@ # Project Setup ################################################## TOP_MODULE = u2_rev3 -BUILD_DIR = $(abspath build$(ISE)) +BUILD_DIR = $(abspath build-udp$(ISE)) ################################################## # Include other makefiles @@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + ################################################## # Project Properties @@ -44,7 +46,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -u2_core.v \ +u2_core_udp.v \ u2_rev3.v \ u2_rev3.ucf diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp deleted file mode 100644 index 99effb038..000000000 --- a/usrp2/top/u2_rev3/Makefile.udp +++ /dev/null @@ -1,99 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2_rev3 -BUILD_DIR = $(abspath build-udp$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -PROJECT_PROPERTIES = \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2_core_udp.v \ -u2_rev3.v \ -u2_rev3.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index a5963f6b1..c85e81140 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -119,11 +119,12 @@ module u2_core inout [15:0] io_rx, // External RAM - inout [17:0] RAM_D, + input [17:0] RAM_D_pi, + output [17:0] RAM_D_po, + output RAM_D_poe, output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -142,7 +143,7 @@ module u2_core localparam SR_RX_CTRL = 176; // 16 localparam SR_TIME64 = 192; // 3 localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 128; // 16 + localparam SR_TX_DSP = 208; // 16 localparam SR_TX_CTRL = 224; // 16 // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 @@ -160,15 +161,17 @@ module u2_core wire ram_loader_done; wire ram_loader_rst, wb_rst, dsp_rst; + assign dsp_rst = wb_rst; - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; wire [31:0] debug_gpio_0, debug_gpio_1; wire [31:0] atr_lines; - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -177,6 +180,12 @@ module u2_core wire serdes_link_up; wire epoch; wire [31:0] irq; + wire [63:0] vita_time; + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; // /////////////////////////////////////////////////////////////////////////////////////////////// // Wishbone Single Master INTERCON @@ -350,33 +359,32 @@ module u2_core wire wr3_ready_i, wr3_ready_o; wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) - ); - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); // ///////////////////////////////////////////////////////////////////////// // SPI -- Slave #2 @@ -405,7 +413,7 @@ module u2_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .gpio({io_tx,io_rx}) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -416,34 +424,73 @@ module u2_core cycle_count <= 0; else cycle_count <= cycle_count + 1; - + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd4; + wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), .sys_clk(dsp_clk), - .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - + + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); + + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus @@ -482,22 +529,30 @@ module u2_core // In Rev3 there are only 6 leds, and the highest one is on the ETH connector wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; + wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); + + setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); // ///////////////////////////////////////////////////////////////////////// // Interrupt Controller, Slave #8 + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + assign irq= {{8'b0}, {8'b0}, - {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; + {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), @@ -506,13 +561,17 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Master Timer, Slave #9 - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - + // No longer used, replaced with simple_timer below + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + // ///////////////////////////////////////////////////////////////////////// // UART, Slave #10 @@ -526,11 +585,6 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // ATR Controller, Slave #11 - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - atr_controller atr_controller (.clk_i(wb_clk),.rst_i(wb_rst), .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), @@ -540,22 +594,9 @@ module u2_core // ////////////////////////////////////////////////////////////////////////// // Time Sync, Slave #12 - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps_in; - always @(posedge dsp_clk) pps_posedge <= pps_in; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), - .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + // ///////////////////////////////////////////////////////////////////////// // SD Card Reader / Writer, Slave #13 @@ -569,44 +610,99 @@ module u2_core assign sd_dat_i[31:8] = 0; // ///////////////////////////////////////////////////////////////////////// - // DSP + // DSP RX wire [31:0] sample_rx, sample_tx; wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; - dsp_core_rx_old dsp_core_rx_old + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), .debug(debug_rx_dsp) ); - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); + wire [31:0] vrc_debug; + wire clear_rx; - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx)); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); - assign dsp_rst = wb_rst; + wire [3:0] vita_state; + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), + .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(clk_to_mac), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(dac_a),.dac_b(dac_b), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + // /////////////////////////////////////////////////////////////////////////////////// // SERDES @@ -620,166 +716,21 @@ module u2_core .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface -/* - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), - .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); + assign RAM_CLK = clk_to_mac; + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing -*/ - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = 0; // wb_clk; - assign debug_clk[1] = clk_to_mac; -/* - - wire mdio_cpy = MDIO; - assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, - { s6_adr[15:8] }, - { s6_adr[7:0] }, - { 6'd0, mdio_cpy, MDC } }; -*/ -/* - assign debug = { { GMII_TXD }, - { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, - { wr2_flags, rd2_flags }, - { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - */ - assign debug = { { GMII_RXD }, - { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, - { wr2_flags, rd2_flags }, - { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - - assign debug_gpio_0 = 0; - //debug_mac; //eth_mac_debug; - assign debug_gpio_1 = 0; + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v deleted file mode 100644 index c85e81140..000000000 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ /dev/null @@ -1,736 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=32768) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - input [17:0] RAM_D_pi, - output [17:0] RAM_D_po, - output RAM_D_poe, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - localparam SR_BUF_POOL = 64; // Uses 1 reg - localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP = 160; // 16 - localparam SR_RX_CTRL = 176; // 16 - localparam SR_TIME64 = 192; // 3 - localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 208; // 16 - localparam SR_TX_CTRL = 224; // 16 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - localparam DSP_TX_FIFOSIZE = 10; - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 10; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - assign dsp_rst = wb_rst; - - wire [31:0] status; - wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - wire [63:0] vita_time; - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; - - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, if_dat; - wire [15:0] ram_loader_adr; - wire [14:0] if_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), - .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), - .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), - .wb_we(ram_loader_we), - .ram_loader_done(ram_loader_done), - // CPLD Interface - .cpld_clk(cpld_clk), - .cpld_din(cpld_din), - .cpld_start(cpld_start_int), - .cpld_mode(cpld_mode_int), - .cpld_done(cpld_done_int), - .cpld_detached(cpld_detached)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .if_adr(if_adr), - .if_dat(if_dat), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), - .ram_loader_done_i(ram_loader_done), - - .if_adr(if_adr), - .if_data(if_dat), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - wire [35:0] tx_err_data; - wire tx_err_src_rdy, tx_err_dst_rdy; - - wire [31:0] router_debug; - - packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), - - .status(status), .sys_int_o(buffer_int), .debug(router_debug), - - .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), - .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), - - .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) - ); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio({io_tx,io_rx}) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd4; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), - .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; - - simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - wire [35:0] rx_f36_data, tx_f36_data; - wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; - - wire [18:0] _rx_f19_data; - wire _rx_f19_src_rdy, _rx_f19_dst_rdy; - - //mac rx to eth input... - fifo19_rxrealign fifo19_rxrealign - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), - .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - - fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), - .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), - .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); - - //eth output to mac tx... - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); - - fifo36_to_fifo19 eth_out_fifo36_to_fifo19 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), - .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - settings_bus_crossclock settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; - - setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - - setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) - sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic - wire underrun_wb, overrun_wb, pps_wb; - - oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); - oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); - oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); - - assign irq= {{8'b0}, - {8'b0}, - {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - // No longer used, replaced with simple_timer below - assign s9_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Simple Timer interrupts - - simple_timer #(.BASE(SR_SIMTIMER)) simple_timer - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .onetime_int(onetime_int), .periodic_int(periodic_int)); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - // No longer used, see time_64bit. Still need to handle mimo time, though - assign sc_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), - .wb_ack_o(sd_ack) ); - - assign sd_dat_i[31:8] = 0; - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx_data; - wire [35:0] rx1_data; - - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - wire [31:0] vrc_debug; - wire clear_rx; - - setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx)); - - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), - .debug_rx(vrc_debug)); - - wire [3:0] vita_state; - - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), - .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty(), - .debug_rx(vita_state) ); - - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), - .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), - .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [35:0] tx_data; - wire tx_src_rdy, tx_dst_rdy; - wire [31:0] debug_vt; - wire clear_tx; - - setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_tx)); - - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) - ext_fifo_i1 - (.int_clk(dsp_clk), - .ext_clk(clk_to_mac), - .rst(dsp_rst | clear_tx), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), - .src_rdy_i(rd1_ready_o), - .dst_rdy_o(rd1_ready_i), - .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), - .src_rdy_o(tx_src_rdy), - .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo), - .debug2(debug_extfifo2) ); - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) - vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(dac_a),.dac_b(dac_b), - .underrun(underrun), .run(run_tx), - .debug(debug_vt)); - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - assign RAM_CLK = clk_to_mac; - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; // debug_extfifo; - assign debug_gpio_0 = 32'd0; - assign debug_gpio_1 = 32'd0; - -endmodule // u2_core -- cgit v1.2.3 From e052378deebaec3a1e06438af95095bbed6d046c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 10 Dec 2010 18:56:18 -0800 Subject: packet_router: gave the inspector a 4th output which is CPU only --- usrp2/fifo/packet_router.v | 206 +++++++++++++++++++++++++++------------------ 1 file changed, 123 insertions(+), 83 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 6cf022b11..9d18c3c42 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -88,9 +88,17 @@ module packet_router .out(my_ip_addr),.changed() ); + //setting register to program the UDP ctrl ports + wire [15:0] ctrl_udp_port, other_udp_port; + setting_reg #(.my_addr(CTRL_BASE+2)) sreg_ctrl_ports( + .clk(stream_clk),.rst(stream_rst), + .strobe(set_stb),.addr(set_addr),.in(set_data), + .out({other_udp_port, ctrl_udp_port}),.changed() + ); + //setting register to program the UDP data ports wire [15:0] dsp0_udp_port, dsp1_udp_port; - setting_reg #(.my_addr(CTRL_BASE+2)) sreg_udp_ports( + setting_reg #(.my_addr(CTRL_BASE+3)) sreg_data_ports( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), .out({dsp1_udp_port, dsp0_udp_port}),.changed() @@ -99,7 +107,7 @@ module packet_router //setting register for CPU output handshake wire [31:0] _sreg_cpu_out_ctrl; wire cpu_out_hs_ctrl = _sreg_cpu_out_ctrl[0]; - setting_reg #(.my_addr(CTRL_BASE+3)) sreg_cpu_out_ctrl( + setting_reg #(.my_addr(CTRL_BASE+4)) sreg_cpu_out_ctrl( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), .out(_sreg_cpu_out_ctrl),.changed() @@ -109,7 +117,7 @@ module packet_router wire [31:0] _sreg_cpu_inp_ctrl; wire cpu_inp_hs_ctrl = _sreg_cpu_inp_ctrl[0]; wire [BUF_SIZE-1:0] cpu_inp_line_count = _sreg_cpu_inp_ctrl[BUF_SIZE-1+16:0+16]; - setting_reg #(.my_addr(CTRL_BASE+4)) sreg_cpu_inp_ctrl( + setting_reg #(.my_addr(CTRL_BASE+5)) sreg_cpu_inp_ctrl( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), .out(_sreg_cpu_inp_ctrl),.changed() @@ -135,9 +143,9 @@ module packet_router //////////////////////////////////////////////////////////////////// //streaming signals from the crossbar to the combiner - wire [35:0] crs_inp_data; - wire crs_inp_valid; - wire crs_inp_ready; + wire [35:0] ext_inp_data; + wire ext_inp_valid; + wire ext_inp_ready; //dummy signals for valve/xbar below wire [35:0] _eth_inp_data; @@ -155,7 +163,7 @@ module packet_router .data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready), .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready), .data0_o(com_inp_data), .src0_rdy_o(com_inp_valid), .dst0_rdy_i(com_inp_ready), - .data1_o(crs_inp_data), .src1_rdy_o(crs_inp_valid), .dst1_rdy_i(crs_inp_ready) + .data1_o(ext_inp_data), .src1_rdy_o(ext_inp_valid), .dst1_rdy_i(ext_inp_ready) ); //////////////////////////////////////////////////////////////////// @@ -169,9 +177,9 @@ module packet_router //////////////////////////////////////////////////////////////////// //streaming signals from the inspector to the crossbar - wire [35:0] crs_out_data; - wire crs_out_valid; - wire crs_out_ready; + wire [35:0] ext_out_data; + wire ext_out_valid; + wire ext_out_ready; //dummy signals for valve/xbar below wire [35:0] _eth_out_data; @@ -181,7 +189,7 @@ module packet_router crossbar36 com_out_xbar ( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag), .data0_i(com_out_data), .src0_rdy_i(com_out_valid), .dst0_rdy_o(com_out_ready), - .data1_i(crs_out_data), .src1_rdy_i(crs_out_valid), .dst1_rdy_o(crs_out_ready), + .data1_i(ext_out_data), .src1_rdy_i(ext_out_valid), .dst1_rdy_o(ext_out_ready), .data0_o(_eth_out_data), .src0_rdy_o(_eth_out_valid), .dst0_rdy_i(_eth_out_ready), .data1_o(ser_out_data), .src1_rdy_o(ser_out_valid), .dst1_rdy_i(ser_out_ready) ); @@ -196,8 +204,7 @@ module packet_router // Communication output source combiner (feeds UDP proto machine) // - DSP framer // - CPU input - // - Error input - // - Crossbar input + // - ERR input //////////////////////////////////////////////////////////////////// //streaming signals from the dsp framer to the combiner @@ -369,37 +376,42 @@ module packet_router //////////////////////////////////////////////////////////////////// // Communication input inspector - // - inspect com input and send it to CPU, DSP, or COM + // - inspect com input and send it to DSP, EXT, CPU, or BOTH //////////////////////////////////////////////////////////////////// localparam COM_INSP_STATE_READ_COM_PRE = 0; localparam COM_INSP_STATE_READ_COM = 1; localparam COM_INSP_STATE_WRITE_REGS = 2; localparam COM_INSP_STATE_WRITE_LIVE = 3; - localparam COM_INSP_DEST_FP_THIS = 0; - localparam COM_INSP_DEST_FP_OTHER = 1; - localparam COM_INSP_DEST_SP_BOTH = 2; + localparam COM_INSP_DEST_DSP = 0; + localparam COM_INSP_DEST_EXT = 1; + localparam COM_INSP_DEST_CPU = 2; + localparam COM_INSP_DEST_BOF = 3; localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at //output inspector interfaces - wire [35:0] com_insp_out_fp_this_data; - wire com_insp_out_fp_this_valid; - wire com_insp_out_fp_this_ready; + wire [35:0] com_insp_out_dsp_data; + wire com_insp_out_dsp_valid; + wire com_insp_out_dsp_ready; + + wire [35:0] com_insp_out_ext_data; + wire com_insp_out_ext_valid; + wire com_insp_out_ext_ready; - wire [35:0] com_insp_out_fp_other_data; - wire com_insp_out_fp_other_valid; - wire com_insp_out_fp_other_ready; + wire [35:0] com_insp_out_cpu_data; + wire com_insp_out_cpu_valid; + wire com_insp_out_cpu_ready; - wire [35:0] com_insp_out_sp_both_data; - wire com_insp_out_sp_both_valid; - wire com_insp_out_sp_both_ready; + wire [35:0] com_insp_out_bof_data; + wire com_insp_out_bof_valid; + wire com_insp_out_bof_ready; //connect this fast-path signals directly to the DSP out - assign dsp_out_data = com_insp_out_fp_this_data; - assign dsp_out_valid = com_insp_out_fp_this_valid; - assign com_insp_out_fp_this_ready = dsp_out_ready; + assign dsp_out_data = com_insp_out_dsp_data; + assign dsp_out_valid = com_insp_out_dsp_valid; + assign com_insp_out_dsp_ready = dsp_out_ready; reg [1:0] com_insp_state; reg [1:0] com_insp_dest; @@ -409,22 +421,24 @@ module packet_router reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0]; //Inspection logic: - wire com_inp_dregs_is_data = 1'b1 + wire com_insp_is_ip_udp = 1'b1 && (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 && (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP - && (com_insp_dregs[9][15:0] == dsp0_udp_port) //UDP data port - && (com_inp_data[15:0] != 16'h0) //VRT packet size ; - - wire com_inp_dregs_my_ip_match = (my_ip_addr == com_insp_dregs[8][31:0])? 1'b1 : 1'b0; - wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & com_inp_dregs_my_ip_match; - wire com_inp_dregs_is_data_there = com_inp_dregs_is_data & ~com_inp_dregs_my_ip_match; + wire com_insp_is_bcast = 1'b1 + && (com_insp_dregs[0][15:0] == 16'hffff) //ethernet dst mac + && (com_insp_dregs[1][31:0] == 32'hffffffff) //ethernet dst mac + ; + wire com_insp_is_ip_match = (my_ip_addr == com_insp_dregs[8][31:0])? 1'b1 : 1'b0; + wire com_insp_is_dsp0_port = (com_insp_dregs[9][15:0] == dsp0_udp_port)? 1'b1 : 1'b0; + wire com_insp_is_ctrl_port = (com_insp_dregs[9][15:0] == ctrl_udp_port)? 1'b1 : 1'b0; + wire com_insp_is_vrt_pkt = (com_inp_data[15:0] != 16'h0)? 1'b1 : 1'b0; //Inspector output flags special case: //Inject SOF into flags at first DSP line. wire [3:0] com_insp_out_flags = ( (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) && - (com_insp_dest == COM_INSP_DEST_FP_THIS) + (com_insp_dest == COM_INSP_DEST_DSP) )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32]; //The communication inspector ouput data and valid signals: @@ -440,21 +454,24 @@ module packet_router //The communication inspector ouput ready signal: //Mux between the various destination ready signals. wire com_insp_out_ready = - (com_insp_dest == COM_INSP_DEST_FP_THIS) ? com_insp_out_fp_this_ready : ( - (com_insp_dest == COM_INSP_DEST_FP_OTHER)? com_insp_out_fp_other_ready : ( - (com_insp_dest == COM_INSP_DEST_SP_BOTH) ? com_insp_out_sp_both_ready : ( - 1'b0))); + (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_dsp_ready : ( + (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_ext_ready : ( + (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_cpu_ready : ( + (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_bof_ready : ( + 1'b0)))); //Always connected output data lines. - assign com_insp_out_fp_this_data = com_insp_out_data; - assign com_insp_out_fp_other_data = com_insp_out_data; - assign com_insp_out_sp_both_data = com_insp_out_data; + assign com_insp_out_dsp_data = com_insp_out_data; + assign com_insp_out_ext_data = com_insp_out_data; + assign com_insp_out_cpu_data = com_insp_out_data; + assign com_insp_out_bof_data = com_insp_out_data; //Destination output valid signals: //Comes from inspector valid when destination is selected, and otherwise low. - assign com_insp_out_fp_this_valid = (com_insp_dest == COM_INSP_DEST_FP_THIS) ? com_insp_out_valid : 1'b0; - assign com_insp_out_fp_other_valid = (com_insp_dest == COM_INSP_DEST_FP_OTHER)? com_insp_out_valid : 1'b0; - assign com_insp_out_sp_both_valid = (com_insp_dest == COM_INSP_DEST_SP_BOTH) ? com_insp_out_valid : 1'b0; + assign com_insp_out_dsp_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0; + assign com_insp_out_ext_valid = (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_valid : 1'b0; + assign com_insp_out_cpu_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0; + assign com_insp_out_bof_valid = (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_valid : 1'b0; //The communication inspector ouput ready signal: //Always ready when storing to data registers, @@ -484,20 +501,36 @@ module packet_router COM_INSP_STATE_READ_COM: begin if (com_inp_ready & com_inp_valid) begin com_insp_dregs[com_insp_dreg_count] <= com_inp_data; - if (com_inp_dregs_is_data_here & com_insp_dreg_counter_done) begin - com_insp_dest <= COM_INSP_DEST_FP_THIS; - com_insp_state <= COM_INSP_STATE_WRITE_REGS; - com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; - end - else if (com_inp_dregs_is_data_there & com_insp_dreg_counter_done) begin - com_insp_dest <= COM_INSP_DEST_FP_OTHER; + if (com_insp_dreg_counter_done | com_inp_data[33]) begin com_insp_state <= COM_INSP_STATE_WRITE_REGS; - com_insp_dreg_count <= 0; - end - else if (com_inp_data[33] | com_insp_dreg_counter_done) begin - com_insp_dest <= COM_INSP_DEST_SP_BOTH; - com_insp_state <= COM_INSP_STATE_WRITE_REGS; - com_insp_dreg_count <= 0; + + //---------- begin inspection decision -----------// + if (com_insp_is_bcast | com_inp_data[33]) begin + com_insp_dest <= COM_INSP_DEST_BOF; + com_insp_dreg_count <= 0; + end + + else if (~com_insp_is_ip_udp) begin + com_insp_dest <= COM_INSP_DEST_CPU; + com_insp_dreg_count <= 0; + end + + else if (~com_insp_is_ip_match) begin + com_insp_dest <= COM_INSP_DEST_EXT; + com_insp_dreg_count <= 0; + end + + else if (com_insp_is_dsp0_port & com_insp_is_vrt_pkt) begin + com_insp_dest <= COM_INSP_DEST_DSP; + com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; + end + + else begin + com_insp_dest <= COM_INSP_DEST_CPU; + com_insp_dreg_count <= 0; + end + //---------- end inspection decision -------------// + end else begin com_insp_dreg_count <= com_insp_dreg_count_next; @@ -531,28 +564,35 @@ module packet_router end //////////////////////////////////////////////////////////////////// - // Serdes crossbar output source - // - combine slow-path data with fast-path other data - // - slow-path data is duplicated to this and CPU out + // Splitter and output muxes for the bof packets + // - split the bof packets into two streams + // - mux split packets into cpu out and ext out //////////////////////////////////////////////////////////////////// - //dummy signals to join the the splitter and mux below - wire [35:0] _sp_split_to_mux_data; - wire _sp_split_to_mux_valid; - wire _sp_split_to_mux_ready; + //dummy signals to join the the splitter and muxes below + wire [35:0] _split_to_ext_data, _split_to_cpu_data; + wire _split_to_ext_valid, _split_to_cpu_valid; + wire _split_to_ext_ready, _split_to_cpu_ready; - splitter36 crs_out_src0( + splitter36 bof_out_splitter( .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), - .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready), - .out0_data(_sp_split_to_mux_data), .out0_valid(_sp_split_to_mux_valid), .out0_ready(_sp_split_to_mux_ready), - .out1_data(cpu_out_data), .out1_valid(cpu_out_valid), .out1_ready(cpu_out_ready) + .inp_data(com_insp_out_bof_data), .inp_valid(com_insp_out_bof_valid), .inp_ready(com_insp_out_bof_ready), + .out0_data(_split_to_ext_data), .out0_valid(_split_to_ext_valid), .out0_ready(_split_to_ext_ready), + .out1_data(_split_to_cpu_data), .out1_valid(_split_to_cpu_valid), .out1_ready(_split_to_cpu_ready) + ); + + fifo36_mux ext_out_mux( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(com_insp_out_ext_data), .src0_rdy_i(com_insp_out_ext_valid), .dst0_rdy_o(com_insp_out_ext_ready), + .data1_i(_split_to_ext_data), .src1_rdy_i(_split_to_ext_valid), .dst1_rdy_o(_split_to_ext_ready), + .data_o(ext_out_data), .src_rdy_o(ext_out_valid), .dst_rdy_i(ext_out_ready) ); - fifo36_mux crs_out_src1( + fifo36_mux cpu_out_mux( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(com_insp_out_fp_other_data), .src0_rdy_i(com_insp_out_fp_other_valid), .dst0_rdy_o(com_insp_out_fp_other_ready), - .data1_i(_sp_split_to_mux_data), .src1_rdy_i(_sp_split_to_mux_valid), .dst1_rdy_o(_sp_split_to_mux_ready), - .data_o(crs_out_data), .src_rdy_o(crs_out_valid), .dst_rdy_i(crs_out_ready) + .data0_i(com_insp_out_cpu_data), .src0_rdy_i(com_insp_out_cpu_valid), .dst0_rdy_o(com_insp_out_cpu_ready), + .data1_i(_split_to_cpu_data), .src1_rdy_i(_split_to_cpu_valid), .dst1_rdy_o(_split_to_cpu_ready), + .data_o(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready) ); //////////////////////////////////////////////////////////////////// @@ -607,7 +647,7 @@ module packet_router fifo36_mux com_out_mux( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(crs_inp_data), .src0_rdy_i(crs_inp_valid), .dst0_rdy_o(crs_inp_ready), + .data0_i(ext_inp_data), .src0_rdy_i(ext_inp_valid), .dst0_rdy_o(ext_inp_ready), .data1_i(_com_out_data), .src1_rdy_i(_com_out_valid), .dst1_rdy_o(_com_out_ready), .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) ); @@ -630,16 +670,16 @@ module packet_router cpu_out_ready, cpu_out_valid, //inspector interfaces (8) - com_inp_ready, com_inp_valid, - com_insp_out_fp_this_ready, com_insp_out_fp_this_valid, - com_insp_out_fp_other_ready, com_insp_out_fp_other_valid, - com_insp_out_sp_both_ready, com_insp_out_sp_both_valid, + com_insp_out_dsp_ready, com_insp_out_dsp_valid, + com_insp_out_ext_ready, com_insp_out_ext_valid, + com_insp_out_cpu_ready, com_insp_out_cpu_valid, + com_insp_out_bof_ready, com_insp_out_bof_valid, //other interfaces (8) - crs_inp_ready, crs_inp_valid, + ext_inp_ready, ext_inp_valid, com_out_ready, com_out_valid, - crs_out_ready, crs_out_valid, - _sp_split_to_mux_ready, _sp_split_to_mux_valid + ext_out_ready, ext_out_valid, + com_inp_ready, com_inp_valid }; endmodule // packet_router -- cgit v1.2.3 From 6ab84f8f1a51ecd7eb9562f9e2fb52f893721c43 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 10 Dec 2010 20:29:00 -0800 Subject: packet_router: added fifo before cpu_out, tweaked inspection logic --- usrp2/fifo/packet_router.v | 54 +++++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 9d18c3c42..df1ba7351 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -89,12 +89,14 @@ module packet_router ); //setting register to program the UDP ctrl ports + /* wire [15:0] ctrl_udp_port, other_udp_port; setting_reg #(.my_addr(CTRL_BASE+2)) sreg_ctrl_ports( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), .out({other_udp_port, ctrl_udp_port}),.changed() ); + */ //setting register to program the UDP data ports wire [15:0] dsp0_udp_port, dsp1_udp_port; @@ -420,19 +422,13 @@ module packet_router wire com_insp_dreg_counter_done = (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)? 1'b1 : 1'b0; reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0]; - //Inspection logic: - wire com_insp_is_ip_udp = 1'b1 - && (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4 - && (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP - ; - wire com_insp_is_bcast = 1'b1 - && (com_insp_dregs[0][15:0] == 16'hffff) //ethernet dst mac - && (com_insp_dregs[1][31:0] == 32'hffffffff) //ethernet dst mac - ; - wire com_insp_is_ip_match = (my_ip_addr == com_insp_dregs[8][31:0])? 1'b1 : 1'b0; - wire com_insp_is_dsp0_port = (com_insp_dregs[9][15:0] == dsp0_udp_port)? 1'b1 : 1'b0; - wire com_insp_is_ctrl_port = (com_insp_dregs[9][15:0] == ctrl_udp_port)? 1'b1 : 1'b0; - wire com_insp_is_vrt_pkt = (com_inp_data[15:0] != 16'h0)? 1'b1 : 1'b0; + //extract various packet components: + wire [47:0] com_insp_dregs_eth_dst_mac = {com_insp_dregs[0][15:0], com_insp_dregs[1][31:0]}; + wire [15:0] com_insp_dregs_eth_type = com_insp_dregs[3][15:0]; + wire [7:0] com_insp_dregs_ipv4_proto = com_insp_dregs[6][23:16]; + wire [31:0] com_insp_dregs_ipv4_dst_addr = com_insp_dregs[8][31:0]; + wire [15:0] com_insp_dregs_udp_dst_port = com_insp_dregs[9][15:0]; + wire [15:0] com_insp_dregs_vrt_size = com_inp_data[15:0]; //Inspector output flags special case: //Inject SOF into flags at first DSP line. @@ -503,31 +499,33 @@ module packet_router com_insp_dregs[com_insp_dreg_count] <= com_inp_data; if (com_insp_dreg_counter_done | com_inp_data[33]) begin com_insp_state <= COM_INSP_STATE_WRITE_REGS; + com_insp_dreg_count <= 0; //---------- begin inspection decision -----------// - if (com_insp_is_bcast | com_inp_data[33]) begin + //bcast or EOF: + if ((com_insp_dregs_eth_dst_mac == 48'hffffffffffff) || com_inp_data[33]) begin com_insp_dest <= COM_INSP_DEST_BOF; - com_insp_dreg_count <= 0; end - else if (~com_insp_is_ip_udp) begin + //not IPv4/UDP: + else if ((com_insp_dregs_eth_type != 16'h800) || (com_insp_dregs_ipv4_proto != 8'h11)) begin com_insp_dest <= COM_INSP_DEST_CPU; - com_insp_dreg_count <= 0; end - else if (~com_insp_is_ip_match) begin + //not my IP address: + else if (com_insp_dregs_ipv4_dst_addr != my_ip_addr) begin com_insp_dest <= COM_INSP_DEST_EXT; - com_insp_dreg_count <= 0; end - else if (com_insp_is_dsp0_port & com_insp_is_vrt_pkt) begin + //UDP data port and VRT: + else if ((com_insp_dregs_udp_dst_port == dsp0_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin com_insp_dest <= COM_INSP_DEST_DSP; com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; end + //other: else begin com_insp_dest <= COM_INSP_DEST_CPU; - com_insp_dreg_count <= 0; end //---------- end inspection decision -------------// @@ -570,9 +568,9 @@ module packet_router //////////////////////////////////////////////////////////////////// //dummy signals to join the the splitter and muxes below - wire [35:0] _split_to_ext_data, _split_to_cpu_data; - wire _split_to_ext_valid, _split_to_cpu_valid; - wire _split_to_ext_ready, _split_to_cpu_ready; + wire [35:0] _split_to_ext_data, _split_to_cpu_data, _cpu_out_data; + wire _split_to_ext_valid, _split_to_cpu_valid, _cpu_out_valid; + wire _split_to_ext_ready, _split_to_cpu_ready, _cpu_out_ready; splitter36 bof_out_splitter( .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), @@ -592,7 +590,13 @@ module packet_router .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .data0_i(com_insp_out_cpu_data), .src0_rdy_i(com_insp_out_cpu_valid), .dst0_rdy_o(com_insp_out_cpu_ready), .data1_i(_split_to_cpu_data), .src1_rdy_i(_split_to_cpu_valid), .dst1_rdy_o(_split_to_cpu_ready), - .data_o(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready) + .data_o(_cpu_out_data), .src_rdy_o(_cpu_out_valid), .dst_rdy_i(_cpu_out_ready) + ); + + fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) cpu_out_fifo ( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .datain(_cpu_out_data), .src_rdy_i(_cpu_out_valid), .dst_rdy_o(_cpu_out_ready), + .dataout(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready) ); //////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 179c651716798bd7b3aaa74c6a546f041e2e3688 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 11 Dec 2010 17:44:27 -0800 Subject: packet_router: raise enable for bram reads the cycle before as well --- usrp2/fifo/dsp_framer36.v | 3 ++- usrp2/fifo/packet_router.v | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index fbdc9fbd7..e44f91305 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -29,6 +29,7 @@ module dsp_framer36 //The header is generated here from the count. wire [31:0] dsp_frm_data_bram; wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; + wire dsp_frm_enb = (dsp_frm_state == DSP_FRM_STATE_WRITE)? (out_ready & out_valid) : 1'b1; assign out_data = (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( @@ -44,7 +45,7 @@ module dsp_framer36 .ENA(inp_ready),.SSRA(0),.WEA(inp_ready), //port B = DSP framer interface (reads from BRAM) .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), - .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) + .ENB(dsp_frm_enb),.SSRB(0),.WEB(1'b0) ); always @(posedge clk) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index df1ba7351..5118c69b3 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -328,6 +328,7 @@ module packet_router (cpu_inp_addr == cpu_inp_line_count_reg)? 4'b0010 : ( 4'b0000)); + wire cpu_inp_enb = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? (cpu_inp_ready & cpu_inp_valid) : 1'b1; assign cpu_inp_valid = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? 1'b1 : 1'b0; assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; @@ -337,7 +338,7 @@ module packet_router .ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i), //port B = packet router interface from CPU (output only) .DOB(cpu_inp_data[31:0]),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), - .ENB(cpu_inp_ready & cpu_inp_valid),.SSRB(0),.WEB(1'b0) + .ENB(cpu_inp_enb),.SSRB(0),.WEB(1'b0) ); always @(posedge stream_clk) -- cgit v1.2.3 From 04f391a2948c07ff1fed9f02497c85cf0f098fee Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Dec 2010 01:09:29 -0800 Subject: packet_router: reverted enable change to dsp framer, it was already correct --- usrp2/fifo/dsp_framer36.v | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index e44f91305..fbdc9fbd7 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -29,7 +29,6 @@ module dsp_framer36 //The header is generated here from the count. wire [31:0] dsp_frm_data_bram; wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; - wire dsp_frm_enb = (dsp_frm_state == DSP_FRM_STATE_WRITE)? (out_ready & out_valid) : 1'b1; assign out_data = (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( @@ -45,7 +44,7 @@ module dsp_framer36 .ENA(inp_ready),.SSRA(0),.WEA(inp_ready), //port B = DSP framer interface (reads from BRAM) .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), - .ENB(dsp_frm_enb),.SSRB(0),.WEB(1'b0) + .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) ); always @(posedge clk) -- cgit v1.2.3 From 6c1d4ebdbd2229654976dd672a5433c300dc0d17 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Dec 2010 17:48:58 -0800 Subject: packet_router: harmless logic tweaks --- usrp2/fifo/dsp_framer36.v | 10 +++++----- usrp2/fifo/packet_router.v | 9 +++------ 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index fbdc9fbd7..34a05d91e 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -20,10 +20,10 @@ module dsp_framer36 wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1; //DSP input stream ready in the following states - assign inp_ready = - (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : ( - (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : ( - 1'b0)); + assign inp_ready = ( + dsp_frm_state == DSP_FRM_STATE_WAIT_SOF || + dsp_frm_state == DSP_FRM_STATE_WAIT_EOF + )? 1'b1 : 1'b0; //DSP framer output data mux (header or BRAM): //The header is generated here from the count. @@ -41,7 +41,7 @@ module dsp_framer36 RAMB16_S36_S36 dsp_frm_buff( //port A = DSP input interface (writes to BRAM) .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0), - .ENA(inp_ready),.SSRA(0),.WEA(inp_ready), + .ENA(inp_ready & inp_valid),.SSRA(0),.WEA(inp_ready & inp_valid), //port B = DSP framer interface (reads from BRAM) .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 5118c69b3..9491d4346 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -253,13 +253,10 @@ module packet_router assign cpu_out_line_count = cpu_out_addr; wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1; - wire cpu_out_reading = ( + assign cpu_out_ready = ( cpu_out_state == CPU_OUT_STATE_WAIT_SOF || cpu_out_state == CPU_OUT_STATE_WAIT_EOF )? 1'b1 : 1'b0; - - wire cpu_out_we = cpu_out_reading; - assign cpu_out_ready = cpu_out_reading; assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; RAMB16_S36_S36 cpu_out_buff( @@ -267,8 +264,8 @@ module packet_router .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0), .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i), //port B = packet router interface to CPU (input only) - .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data),.DIPB(4'h0), - .ENB(cpu_out_we),.SSRB(0),.WEB(cpu_out_we) + .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data[31:0]),.DIPB(4'h0), + .ENB(cpu_out_ready & cpu_out_valid),.SSRB(0),.WEB(cpu_out_ready & cpu_out_valid) ); always @(posedge stream_clk) -- cgit v1.2.3 From b6b5b7b65dca848322941c2df73d1b9f5b6ac907 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Dec 2010 17:51:53 -0800 Subject: zpu: moved top level file in hopes for easy merge --- usrp2/top/u2_rev3/u2_core.v | 498 ++++++++++++--------------- usrp2/top/u2_rev3/u2_core_udp.v | 745 ---------------------------------------- 2 files changed, 229 insertions(+), 1014 deletions(-) delete mode 100644 usrp2/top/u2_rev3/u2_core_udp.v diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index a5963f6b1..26e2cc4ab 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -3,7 +3,7 @@ // //////////////////////////////////////////////////////////////////////////////// module u2_core - #(parameter RAM_SIZE=32768) + #(parameter RAM_SIZE=16384, parameter RAM_AW=14) (// Clocks input dsp_clk, input wb_clk, @@ -119,11 +119,12 @@ module u2_core inout [15:0] io_rx, // External RAM - inout [17:0] RAM_D, + input [17:0] RAM_D_pi, + output [17:0] RAM_D_po, + output RAM_D_poe, output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -142,7 +143,7 @@ module u2_core localparam SR_RX_CTRL = 176; // 16 localparam SR_TIME64 = 192; // 3 localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 128; // 16 + localparam SR_TX_DSP = 208; // 16 localparam SR_TX_CTRL = 224; // 16 // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 @@ -160,15 +161,17 @@ module u2_core wire ram_loader_done; wire ram_loader_rst, wb_rst, dsp_rst; + assign dsp_rst = wb_rst; - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; wire [31:0] debug_gpio_0, debug_gpio_1; wire [31:0] atr_lines; - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -177,6 +180,12 @@ module u2_core wire serdes_link_up; wire epoch; wire [31:0] irq; + wire [63:0] vita_time; + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; // /////////////////////////////////////////////////////////////////////////////////////////////// // Wishbone Single Master INTERCON @@ -283,7 +292,7 @@ module u2_core wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we; wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), @@ -299,28 +308,37 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .if_adr(if_adr), - .if_dat(if_dat), +// aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) +// aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), +// // Instruction Wishbone bus to I-RAM +// .if_adr(if_adr), +// .if_dat(if_dat), +// // Data Wishbone bus to system bus fabric +// .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), +// .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), +// // Interrupts and exceptions +// .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + //assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(1'b1), // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; + .zpu_status(zpu_status), .interrupt(proc_int)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone // I-port connects directly to processor and ram loader wire flush_icache; - ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), @@ -328,7 +346,7 @@ module u2_core .if_adr(if_adr), .if_data(if_dat), - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), .flush_icache(flush_icache)); @@ -350,33 +368,32 @@ module u2_core wire wr3_ready_i, wr3_ready_o; wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) - ); - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); // ///////////////////////////////////////////////////////////////////////// // SPI -- Slave #2 @@ -405,7 +422,7 @@ module u2_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .gpio({io_tx,io_rx}) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -416,34 +433,73 @@ module u2_core cycle_count <= 0; else cycle_count <= cycle_count + 1; - + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd4; + wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), .sys_clk(dsp_clk), - .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - + + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); + + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus @@ -482,22 +538,30 @@ module u2_core // In Rev3 there are only 6 leds, and the highest one is on the ETH connector wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; + wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); + + setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); // ///////////////////////////////////////////////////////////////////////// // Interrupt Controller, Slave #8 + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + assign irq= {{8'b0}, {8'b0}, - {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; + {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), @@ -506,13 +570,17 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Master Timer, Slave #9 - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - + // No longer used, replaced with simple_timer below + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + // ///////////////////////////////////////////////////////////////////////// // UART, Slave #10 @@ -526,11 +594,6 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // ATR Controller, Slave #11 - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - atr_controller atr_controller (.clk_i(wb_clk),.rst_i(wb_rst), .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), @@ -540,22 +603,9 @@ module u2_core // ////////////////////////////////////////////////////////////////////////// // Time Sync, Slave #12 - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps_in; - always @(posedge dsp_clk) pps_posedge <= pps_in; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), - .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + // ///////////////////////////////////////////////////////////////////////// // SD Card Reader / Writer, Slave #13 @@ -569,44 +619,99 @@ module u2_core assign sd_dat_i[31:8] = 0; // ///////////////////////////////////////////////////////////////////////// - // DSP + // DSP RX wire [31:0] sample_rx, sample_tx; wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; - dsp_core_rx_old dsp_core_rx_old + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), .debug(debug_rx_dsp) ); - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); + wire [31:0] vrc_debug; + wire clear_rx; - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx)); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); - assign dsp_rst = wb_rst; + wire [3:0] vita_state; + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), + .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(clk_to_mac), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(dac_a),.dac_b(dac_b), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + // /////////////////////////////////////////////////////////////////////////////////// // SERDES @@ -620,166 +725,21 @@ module u2_core .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface -/* - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), - .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); + assign RAM_CLK = clk_to_mac; + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing -*/ - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = 0; // wb_clk; - assign debug_clk[1] = clk_to_mac; -/* - - wire mdio_cpy = MDIO; - assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, - { s6_adr[15:8] }, - { s6_adr[7:0] }, - { 6'd0, mdio_cpy, MDC } }; -*/ -/* - assign debug = { { GMII_TXD }, - { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, - { wr2_flags, rd2_flags }, - { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - */ - assign debug = { { GMII_RXD }, - { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, - { wr2_flags, rd2_flags }, - { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - - assign debug_gpio_0 = 0; - //debug_mac; //eth_mac_debug; - assign debug_gpio_1 = 0; + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v deleted file mode 100644 index 26e2cc4ab..000000000 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ /dev/null @@ -1,745 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=16384, parameter RAM_AW=14) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - input [17:0] RAM_D_pi, - output [17:0] RAM_D_po, - output RAM_D_poe, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - localparam SR_BUF_POOL = 64; // Uses 1 reg - localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP = 160; // 16 - localparam SR_RX_CTRL = 176; // 16 - localparam SR_TIME64 = 192; // 3 - localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 208; // 16 - localparam SR_TX_CTRL = 224; // 16 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - localparam DSP_TX_FIFOSIZE = 10; - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 10; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - assign dsp_rst = wb_rst; - - wire [31:0] status; - wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - wire [63:0] vita_time; - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; - - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, if_dat; - wire [15:0] ram_loader_adr; - wire [14:0] if_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) - ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), - .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), - .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), - .wb_we(ram_loader_we), - .ram_loader_done(ram_loader_done), - // CPLD Interface - .cpld_clk(cpld_clk), - .cpld_din(cpld_din), - .cpld_start(cpld_start_int), - .cpld_mode(cpld_mode_int), - .cpld_done(cpld_done_int), - .cpld_detached(cpld_detached)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor -// aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) -// aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), -// // Instruction Wishbone bus to I-RAM -// .if_adr(if_adr), -// .if_dat(if_dat), -// // Data Wishbone bus to system bus fabric -// .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), -// .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), -// // Interrupts and exceptions -// .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - //assign bus_error = m0_err | m0_rty; - - wire [63:0] zpu_status; - zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(1'b1), - // Data Wishbone bus to system bus fabric - .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), - .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), - // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int)); - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), - .ram_loader_done_i(ram_loader_done), - - .if_adr(if_adr), - .if_data(if_dat), - - .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - wire [35:0] tx_err_data; - wire tx_err_src_rdy, tx_err_dst_rdy; - - wire [31:0] router_debug; - - packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), - - .status(status), .sys_int_o(buffer_int), .debug(router_debug), - - .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), - .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), - - .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) - ); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio({io_tx,io_rx}) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd4; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), - .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; - - simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - wire [35:0] rx_f36_data, tx_f36_data; - wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; - - wire [18:0] _rx_f19_data; - wire _rx_f19_src_rdy, _rx_f19_dst_rdy; - - //mac rx to eth input... - fifo19_rxrealign fifo19_rxrealign - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), - .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - - fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), - .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), - .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); - - //eth output to mac tx... - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); - - fifo36_to_fifo19 eth_out_fifo36_to_fifo19 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), - .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - settings_bus_crossclock settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; - - setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - - setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) - sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic - wire underrun_wb, overrun_wb, pps_wb; - - oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); - oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); - oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); - - assign irq= {{8'b0}, - {8'b0}, - {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - // No longer used, replaced with simple_timer below - assign s9_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Simple Timer interrupts - - simple_timer #(.BASE(SR_SIMTIMER)) simple_timer - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .onetime_int(onetime_int), .periodic_int(periodic_int)); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - // No longer used, see time_64bit. Still need to handle mimo time, though - assign sc_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), - .wb_ack_o(sd_ack) ); - - assign sd_dat_i[31:8] = 0; - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx_data; - wire [35:0] rx1_data; - - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - wire [31:0] vrc_debug; - wire clear_rx; - - setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx)); - - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), - .debug_rx(vrc_debug)); - - wire [3:0] vita_state; - - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), - .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty(), - .debug_rx(vita_state) ); - - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), - .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), - .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [35:0] tx_data; - wire tx_src_rdy, tx_dst_rdy; - wire [31:0] debug_vt; - wire clear_tx; - - setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_tx)); - - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) - ext_fifo_i1 - (.int_clk(dsp_clk), - .ext_clk(clk_to_mac), - .rst(dsp_rst | clear_tx), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), - .src_rdy_i(rd1_ready_o), - .dst_rdy_o(rd1_ready_i), - .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), - .src_rdy_o(tx_src_rdy), - .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo), - .debug2(debug_extfifo2) ); - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) - vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(dac_a),.dac_b(dac_b), - .underrun(underrun), .run(run_tx), - .debug(debug_vt)); - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - assign RAM_CLK = clk_to_mac; - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; // debug_extfifo; - assign debug_gpio_0 = 32'd0; - assign debug_gpio_1 = 32'd0; - -endmodule // u2_core -- cgit v1.2.3 From e932dc72689bb7a20dda6cb28c8567eaf528554b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 13 Dec 2010 15:53:46 -0800 Subject: packet_router: all non ip/udp should also go to both --- usrp2/fifo/packet_router.v | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 9491d4346..cf4047c5f 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -500,16 +500,14 @@ module packet_router com_insp_dreg_count <= 0; //---------- begin inspection decision -----------// - //bcast or EOF: - if ((com_insp_dregs_eth_dst_mac == 48'hffffffffffff) || com_inp_data[33]) begin + //EOF or bcast or not IPv4 or not UDP: + if ( + com_inp_data[33] || (com_insp_dregs_eth_dst_mac == 48'hffffffffffff) || + (com_insp_dregs_eth_type != 16'h800) || (com_insp_dregs_ipv4_proto != 8'h11) + ) begin com_insp_dest <= COM_INSP_DEST_BOF; end - //not IPv4/UDP: - else if ((com_insp_dregs_eth_type != 16'h800) || (com_insp_dregs_ipv4_proto != 8'h11)) begin - com_insp_dest <= COM_INSP_DEST_CPU; - end - //not my IP address: else if (com_insp_dregs_ipv4_dst_addr != my_ip_addr) begin com_insp_dest <= COM_INSP_DEST_EXT; -- cgit v1.2.3 From e4dc2a1c5688ab5c14285628a32212333b84f46f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Dec 2010 13:11:09 -0800 Subject: zpu: working, modified top level sizes, disable interrupt --- usrp2/top/u2_rev3/u2_core.v | 11 ++++------- usrp2/top/u2_rev3/u2_rev3.v | 2 +- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index fff7ab914..97de38a82 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -286,12 +286,10 @@ module u2_core // /////////////////////////////////////////////////////////////////// // RAM Loader - wire [31:0] ram_loader_dat, if_dat; + wire [31:0] ram_loader_dat; wire [15:0] ram_loader_adr; - wire [14:0] if_adr; wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we; - wire iwb_ack, iwb_stb; ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), @@ -323,12 +321,12 @@ module u2_core wire [63:0] zpu_status; zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(1'b1), + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), // Data Wishbone bus to system bus fabric .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int)); + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone @@ -343,8 +341,7 @@ module u2_core .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), - .if_adr(if_adr), - .if_data(if_dat), + .if_adr(16'b0), .if_data(), .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index f2bba6c50..759f7b7b8 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -471,7 +471,7 @@ module u2_rev3 // - u2_core #(.RAM_SIZE(32768)) + u2_core #(.RAM_SIZE(16384), .RAM_AW(14)) u2_core(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), -- cgit v1.2.3 From a96f39ef767ffcecac4a1cb7d20584fb7bd1e11a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Dec 2010 16:32:08 -0800 Subject: usrp-n210: integrate zpu and packet router, builds but untested --- usrp2/top/u2plus/u2plus_core.v | 149 +++++++++++++++++++++-------------------- 1 file changed, 77 insertions(+), 72 deletions(-) diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 4e0b190ef..72dee909b 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -155,7 +155,7 @@ module u2plus_core wire wb_rst, dsp_rst; - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire [31:0] status; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; wire proc_int, overrun, underrun; wire [3:0] uart_tx_int, uart_rx_int; @@ -254,32 +254,39 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // Processor - wire [31:0] if_dat; - wire [15:0] if_adr; - - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .if_adr(if_adr), - .if_dat(if_dat), +// wire [31:0] if_dat; +// wire [15:0] if_adr; + +// aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) +// aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), +// // Instruction Wishbone bus to I-RAM +// .if_adr(if_adr), +// .if_dat(if_dat), +// // Data Wishbone bus to system bus fabric +// .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), +// .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), +// // Interrupts and exceptions +// .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + +// assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone // I-port connects directly to processor - wire [31:0] if_dat_boot, if_dat_main; - assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot; - bootram bootram(.clk(wb_clk), .reset(wb_rst), - .if_adr(if_adr[12:0]), .if_data(if_dat_boot), + .if_adr(13'b0), .if_data(), .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); @@ -289,10 +296,10 @@ module u2plus_core `include "bootloader.rmi" - ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) + ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .if_adr(if_adr[14:0]), .if_data(if_dat_main), - .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); // ///////////////////////////////////////////////////////////////////////// @@ -310,34 +317,30 @@ module u2plus_core wire wr3_ready_i, wr3_ready_o; wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - // ///////////////////////////////////////////////////////////////////////// // SPI -- Slave #2 spi_top shared_spi @@ -384,17 +387,17 @@ module u2plus_core (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), @@ -410,36 +413,38 @@ module u2plus_core .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] udp_tx_data, udp_rx_data; - wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; - - udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), - .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), - .debug(debug_udp) ); + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - wire [35:0] tx_err_data, udp1_tx_data; - wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - fifo36_mux #(.prio(0)) mux_err_stream - (.clk(dsp_clk), .reset(dsp_reset), .clear(0), - .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 -- cgit v1.2.3 From 21c3765da33652ec186e230d2aabc52625e32d7f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 15 Dec 2010 17:17:11 -0800 Subject: now supports up to 4 different udp ports --- usrp2/udp/prot_eng_tx.v | 39 ++++++++++++++++++++++++++------------- usrp2/udp/prot_eng_tx_tb.v | 27 +++++++++++++++++---------- 2 files changed, 43 insertions(+), 23 deletions(-) diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index a18eb73ae..06ae166ba 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -7,6 +7,7 @@ // Odd means the last word is half full // Flags[1:0] is {eop, sop} // Protocol word format is: +// 20 UDP Port Here // 19 Last Header Line // 18 IP Header Checksum XOR // 17 IP Length Here @@ -34,13 +35,18 @@ module prot_eng_tx assign dst_rdy_o = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30)); assign src_rdy_o = src_rdy_i & ~((state==0) | (state==1) | (state==30)); - localparam HDR_WIDTH = 16 + 4; // 16 bits plus flags + localparam HDR_WIDTH = 16 + 5; // 16 bits plus flags localparam HDR_LEN = 32; // Up to 64 bytes of protocol // Store header values in a small dual-port (distributed) ram reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1]; wire [HDR_WIDTH-1:0] header_word; - reg [15:0] chk_precompute; + + reg [1:0] port_sel; + reg [15:0] per_port_data[0:3]; + reg [15:0] udp_port, chk_precompute; + + always @(posedge clk) udp_port <= per_port_data[port_sel]; always @(posedge clk) if(set_stb & ((set_addr & 8'hE0) == BASE)) @@ -49,13 +55,18 @@ module prot_eng_tx if(set_data[18]) chk_precompute <= set_data[15:0]; end - - assign header_word = header_ram[state]; + always @(posedge clk) + if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) + per_port_data[set_addr[1:0]] <= set_data; + + wire do_udp_port = header_word[20]; wire last_hdr_line = header_word[19]; - wire ip_chk = header_word[18]; - wire ip_len = header_word[17]; - wire udp_len = header_word[16]; + wire do_ip_chk = header_word[18]; + wire do_ip_len = header_word[17]; + wire do_udp_len = header_word[16]; + + assign header_word = header_ram[state]; // Protocol State Machine reg [15:0] length; @@ -75,6 +86,7 @@ module prot_eng_tx 0 : begin fast_path <= datain[0]; + port_sel <= datain[2:1]; state <= 1; end 1 : @@ -113,15 +125,16 @@ module prot_eng_tx checksum_reg <= checksum; always @* - if(ip_chk) - //dataout_int <= header_word[15:0] ^ ip_length; + if(do_payload) + dataout_int <= datain[15:0]; + else if(do_ip_chk) dataout_int <= 16'hFFFF ^ checksum_reg; - else if(ip_len) + else if(do_ip_len) dataout_int <= ip_length; - else if(udp_len) + else if(do_udp_len) dataout_int <= udp_length; - else if(do_payload) - dataout_int <= datain[15:0]; + else if(do_udp_port) + dataout_int <= udp_port; else dataout_int <= header_word[15:0]; diff --git a/usrp2/udp/prot_eng_tx_tb.v b/usrp2/udp/prot_eng_tx_tb.v index e7ffeb5e1..c8fffe605 100644 --- a/usrp2/udp/prot_eng_tx_tb.v +++ b/usrp2/udp/prot_eng_tx_tb.v @@ -80,7 +80,7 @@ module prot_eng_tx_tb(); begin count <= 4; src_rdy_f36i <= 1; - f36_data <= 32'h0001_000c; + f36_data <= 32'h0003_000c; f36_sof <= 1; f36_eof <= 0; f36_occ <= 0; @@ -140,16 +140,23 @@ module prot_eng_tx_tb(); @(negedge rst); @(posedge clk); WriteSREG(BASE, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234}); - WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678}); - WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+1, {11'b0, 5'h00, 16'h0000}); + WriteSREG(BASE+2, {11'b0, 5'h00, 16'hABCD}); + WriteSREG(BASE+3, {11'b0, 5'h00, 16'h1234}); + WriteSREG(BASE+4, {11'b0, 5'h00, 16'h5678}); + WriteSREG(BASE+5, {11'b0, 5'h00, 16'hF00D}); + WriteSREG(BASE+6, {11'b0, 5'h00, 16'hBEEF}); + WriteSREG(BASE+7, {11'b0, 5'h10, 16'hDCBA}); + WriteSREG(BASE+8, {11'b0, 5'h00, 16'h4321}); + WriteSREG(BASE+9, {11'b0, 5'h04, 16'hABCD}); + WriteSREG(BASE+10, {11'b0, 5'h08, 16'hABCD}); @(posedge clk); + + WriteSREG(BASE+24, 16'h6666); + WriteSREG(BASE+25, 16'h7777); + WriteSREG(BASE+26, 16'h8888); + WriteSREG(BASE+27, 16'h9999); + PutPacketInFIFO36(32'hA0B0C0D0,16); @(posedge clk); @(posedge clk); -- cgit v1.2.3 From 54588404b0e168d42ca963a282c61fa137612a63 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 15 Dec 2010 17:37:58 -0800 Subject: generate port number headers in the dsp error units --- usrp2/top/u2_rev3/u2_core.v | 3 ++- usrp2/top/u2plus/u2plus_core.v | 3 ++- usrp2/vrt/gen_context_pkt.v | 7 ++++--- usrp2/vrt/vita_tx_chain.v | 7 ++++--- 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 30b47b818..41e308723 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -691,7 +691,8 @@ module u2_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 4e0b190ef..33db2c2d3 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -652,7 +652,8 @@ module u2plus_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 44bb7b548..cc34cceed 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -1,7 +1,8 @@ module gen_context_pkt - #(parameter PROT_ENG_FLAGS=1) + #(parameter PROT_ENG_FLAGS=1, + parameter DSP_NUMBER=0) (input clk, input reset, input clear, input trigger, output sent, input [31:0] streamid, @@ -67,10 +68,10 @@ module gen_context_pkt endcase // case (ctxt_state) assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); - + always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd28 }; // UDP port 1 or 3 CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 2ec78189b..6f567668d 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -5,7 +5,8 @@ module vita_tx_chain parameter REPORT_ERROR=0, parameter DO_FLOW_CONTROL=0, parameter PROT_ENG_FLAGS=0, - parameter USE_TRANS_HEADER=0) + parameter USE_TRANS_HEADER=0, + parameter DSP_NUMBER=0) (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, @@ -71,7 +72,7 @@ module vita_tx_chain wire [35:0] flow_data, err_data_int; wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int; - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(32'd0), @@ -82,7 +83,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .packet_consumed(packet_consumed), .trigger(trigger)); - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), -- cgit v1.2.3 From abe10a16e3654eeac3195b344f703ce6f2fa542e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 17 Dec 2010 13:44:40 -0800 Subject: udp_ports: set the source port and destination port from table --- usrp2/udp/prot_eng_tx.v | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index 06ae166ba..b86a9950c 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -35,7 +35,7 @@ module prot_eng_tx assign dst_rdy_o = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30)); assign src_rdy_o = src_rdy_i & ~((state==0) | (state==1) | (state==30)); - localparam HDR_WIDTH = 16 + 5; // 16 bits plus flags + localparam HDR_WIDTH = 16 + 6; // 16 bits plus flags localparam HDR_LEN = 32; // Up to 64 bytes of protocol // Store header values in a small dual-port (distributed) ram @@ -43,11 +43,12 @@ module prot_eng_tx wire [HDR_WIDTH-1:0] header_word; reg [1:0] port_sel; - reg [15:0] per_port_data[0:3]; - reg [15:0] udp_port, chk_precompute; + reg [32:0] per_port_data[0:3]; + reg [15:0] udp_src_port, udp_dst_port, chk_precompute; + + always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16]; + always @(posedge clk) udp_dst_port <= per_port_data[port_sel][15:0]; - always @(posedge clk) udp_port <= per_port_data[port_sel]; - always @(posedge clk) if(set_stb & ((set_addr & 8'hE0) == BASE)) begin @@ -60,11 +61,12 @@ module prot_eng_tx if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) per_port_data[set_addr[1:0]] <= set_data; - wire do_udp_port = header_word[20]; - wire last_hdr_line = header_word[19]; - wire do_ip_chk = header_word[18]; - wire do_ip_len = header_word[17]; - wire do_udp_len = header_word[16]; + wire do_udp_src_port = header_word[21]; + wire do_udp_dst_port = header_word[20]; + wire last_hdr_line = header_word[19]; + wire do_ip_chk = header_word[18]; + wire do_ip_len = header_word[17]; + wire do_udp_len = header_word[16]; assign header_word = header_ram[state]; @@ -133,8 +135,10 @@ module prot_eng_tx dataout_int <= ip_length; else if(do_udp_len) dataout_int <= udp_length; - else if(do_udp_port) - dataout_int <= udp_port; + else if(do_udp_src_port) + dataout_int <= udp_src_port; + else if(do_udp_dst_port) + dataout_int <= udp_dst_port; else dataout_int <= header_word[15:0]; -- cgit v1.2.3 From 110070fe371e521c0f20cbbb1b1da66312cb4d74 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 17 Dec 2010 19:02:14 -0800 Subject: usrp-n210: almost working w/ packet router + zpu added stack start signal to zpu removed wb perifs in n210 out of 0-16k added reset controller for main app rewire cpu addr line after booted use 0-16k --- usrp2/opencores/zpu/core/zpu_config.vhd | 5 - usrp2/opencores/zpu/core/zpu_core.vhd | 3 +- usrp2/opencores/zpu/core/zpupkg.vhd | 1 + usrp2/opencores/zpu/wishbone/zpu_system.vhd | 3 +- usrp2/opencores/zpu/zpu_top_pkg.vhd | 2 +- usrp2/opencores/zpu/zpu_wb_top.vhd | 2 + usrp2/top/u2_rev3/u2_core.v | 16 +- usrp2/top/u2plus/bootloader.rmi | 472 ++++++++++++++-------------- usrp2/top/u2plus/u2plus_core.v | 110 ++++--- 9 files changed, 313 insertions(+), 301 deletions(-) diff --git a/usrp2/opencores/zpu/core/zpu_config.vhd b/usrp2/opencores/zpu/core/zpu_config.vhd index f7743d602..b7e894232 100644 --- a/usrp2/opencores/zpu/core/zpu_config.vhd +++ b/usrp2/opencores/zpu/core/zpu_config.vhd @@ -12,9 +12,4 @@ package zpu_config is constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 15; - - -- start byte address of stack. - -- point to top of RAM - 2*words - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"3ff8"; - end zpu_config; diff --git a/usrp2/opencores/zpu/core/zpu_core.vhd b/usrp2/opencores/zpu/core/zpu_core.vhd index 2450f14d3..24586b2f6 100644 --- a/usrp2/opencores/zpu/core/zpu_core.vhd +++ b/usrp2/opencores/zpu/core/zpu_core.vhd @@ -26,6 +26,7 @@ entity zpu_core is mem_write : out std_logic_vector(wordSize-1 downto 0); out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); interrupt : in std_logic; break : out std_logic; zpu_status : out std_logic_vector(63 downto 0)); @@ -202,7 +203,7 @@ begin if areset = '1' then state <= State_Idle; break <= '0'; - sp <= spStart(maxAddrBitIncIO downto minAddrBit); + sp <= stack_start(maxAddrBitIncIO downto minAddrBit); pc <= (others => '0'); idim_flag <= '0'; diff --git a/usrp2/opencores/zpu/core/zpupkg.vhd b/usrp2/opencores/zpu/core/zpupkg.vhd index 1a01563b8..eee967a09 100644 --- a/usrp2/opencores/zpu/core/zpupkg.vhd +++ b/usrp2/opencores/zpu/core/zpupkg.vhd @@ -73,6 +73,7 @@ package zpupkg is mem_write : out std_logic_vector(wordSize-1 downto 0); out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); interrupt : in std_logic; break : out std_logic; zpu_status : out std_logic_vector(63 downto 0)); diff --git a/usrp2/opencores/zpu/wishbone/zpu_system.vhd b/usrp2/opencores/zpu/wishbone/zpu_system.vhd index 294651fe2..8af678b6a 100644 --- a/usrp2/opencores/zpu/wishbone/zpu_system.vhd +++ b/usrp2/opencores/zpu/wishbone/zpu_system.vhd @@ -51,7 +51,7 @@ entity zpu_system is -- ZPU Control signals enable : in std_logic; interrupt : in std_logic; - + stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); zpu_status : out std_logic_vector(63 downto 0); -- wishbone interfaces @@ -84,6 +84,7 @@ begin mem_write => mem_write, out_mem_addr => out_mem_addr, mem_writeMask => mem_writeMask, + stack_start => stack_start, interrupt => interrupt, zpu_status => zpu_status, break => open); diff --git a/usrp2/opencores/zpu/zpu_top_pkg.vhd b/usrp2/opencores/zpu/zpu_top_pkg.vhd index 23ff48c39..a158ab9c0 100644 --- a/usrp2/opencores/zpu/zpu_top_pkg.vhd +++ b/usrp2/opencores/zpu/zpu_top_pkg.vhd @@ -35,7 +35,7 @@ package zpu_top_pkg is -- ZPU Control signals enable : in std_logic; interrupt : in std_logic; - + stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); zpu_status : out std_logic_vector(63 downto 0); -- wishbone interfaces diff --git a/usrp2/opencores/zpu/zpu_wb_top.vhd b/usrp2/opencores/zpu/zpu_wb_top.vhd index 48e5ee31d..9735c4b54 100644 --- a/usrp2/opencores/zpu/zpu_wb_top.vhd +++ b/usrp2/opencores/zpu/zpu_wb_top.vhd @@ -36,6 +36,7 @@ entity zpu_wb_top is -- misc zpu signals interrupt: in std_logic; + stack_start: in std_logic_vector(adr_w-1 downto 0); zpu_status: out std_logic_vector(63 downto 0) ); @@ -66,6 +67,7 @@ zpu_system0: zpu_system port map( areset => rst, enable => enb, interrupt => interrupt, + stack_start => stack_start, zpu_status => zpu_status, zpu_wb_i => zpu_wb_i, zpu_wb_o => zpu_wb_o diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 97de38a82..66c951638 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -306,18 +306,8 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Processor -// aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) -// aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), -// // Instruction Wishbone bus to I-RAM -// .if_adr(if_adr), -// .if_dat(if_dat), -// // Data Wishbone bus to system bus fabric -// .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), -// .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), -// // Interrupts and exceptions -// .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - //assign bus_error = m0_err | m0_rty; + + assign bus_error = m0_err | m0_rty; wire [63:0] zpu_status; zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) @@ -326,7 +316,7 @@ module u2_core .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone diff --git a/usrp2/top/u2plus/bootloader.rmi b/usrp2/top/u2plus/bootloader.rmi index 7c15699db..0916adaf7 100644 --- a/usrp2/top/u2plus/bootloader.rmi +++ b/usrp2/top/u2plus/bootloader.rmi @@ -1,245 +1,231 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b808175c_00000000_b8080050; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081764; -defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401e70_31a01e98_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40668_80000000_b9f400cc; -defparam bootram.RAM0.INIT_04=256'he8830000_e8601e78_80000000_99fc2000_f8601e78_b8000044_bc030014_f9e10000; -defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01e8c_bc030010_30600000_b0000000_30630004_be24ffec; -defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; -defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01e8c_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01e90_bc030014_30800000_b0000000_e8601e90; -defparam bootram.RAM0.INIT_09=256'h06463800_20e01e98_20c01e98_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; -defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; -defparam bootram.RAM0.INIT_0B=256'hb9f415f8_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; -defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401c8_20e00000_20c00000_80000000_b9f41778_80000000; -defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f415c4_80000000_b9f41780; -defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; -defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; -defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; -defparam bootram.RAM0.INIT_11=256'hb9f4062c_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; -defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01984_10b30000_b9f40da4_10d60000_10b30000; -defparam bootram.RAM0.INIT_13=256'h30a01984_bc120040_aa430001_30a0194c_e061001c_10a30000_be520034_16439003; -defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406c0_b800ffb4_80000000_b9f406cc; -defparam bootram.RAM0.INIT_15=256'h80000000_b9f40694_b800ff88_80000000_b9f406a0_30a0194c_80000000_b9f4155c; -defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f40678_30a01950_80000000_b9f411e8_30a08000_b0000000; -defparam bootram.RAM0.INIT_17=256'hbe030020_30a00050_31000001_30e1001c_30c000f7_f9e10000_a46500ff_3021ffe0; -defparam bootram.RAM0.INIT_18=256'hb810ffe8_30210020_b60f0008_e9e10000_80000000_b9f40330_f081001c_3080005e; -defparam bootram.RAM0.INIT_19=256'h31000001_b9f40280_f9e10000_30e1001c_30c000f7_30a00050_3021ffe0_308000dc; -defparam bootram.RAM0.INIT_1A=256'h3021ffdc_30210020_b60f0008_6463001f_3063ffff_a863005e_e9e10000_e061001c; -defparam bootram.RAM0.INIT_1B=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c_f9e10000; -defparam bootram.RAM0.INIT_1C=256'hb9f40ea8_80000000_b9f4082c_f800200c_80000000_b9f4fe74_f860200c_306000ff; -defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ff6c_80000000_b9f4059c_30a01988_80000000_b9f409ec_80000000; -defparam bootram.RAM0.INIT_1E=256'h30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000_be23017c; -defparam bootram.RAM0.INIT_1F=256'hb0000000_80000000_b9f40558_30a01b04_12c30000_be030068_80000000_b9f41180; -defparam bootram.RAM0.INIT_20=256'hb9f41094_30a08000_b0000000_30c07c00_b9f40e70_30a00000_b0000030_30e08000; -defparam bootram.RAM0.INIT_21=256'he9e10000_30600001_10a00000_b9f41244_80000000_b9f40524_30a01b30_80000000; -defparam bootram.RAM0.INIT_22=256'hb000003f_80000000_b9f404f8_30a01b6c_30210024_b60f0008_eac10020_ea61001c; -defparam bootram.RAM0.INIT_23=256'h80000000_b9f404d4_30a019f8_12630000_be230024_80000000_b9f410fc_30a00000; -defparam bootram.RAM0.INIT_24=256'h30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000_b9f4fd9c; -defparam bootram.RAM0.INIT_25=256'hb9f40490_30a019bc_80000000_b9f41000_30a08000_b0000000_30c07c00_b9f40ddc; -defparam bootram.RAM0.INIT_26=256'h80000000_b9f40474_30a01a50_30600001_b810ff70_10b60000_b9f411b0_80000000; -defparam bootram.RAM0.INIT_27=256'h80000000_b9f40454_30a01ab4_bc230098_80000000_b9f41000_30a00000_b0000018; -defparam bootram.RAM0.INIT_28=256'h80000000_b9f41048_30a00000_b000003f_80000000_b9f40444_30a0199c_b800fed8; -defparam bootram.RAM0.INIT_29=256'hb9f4fda4_b800fe9c_80000000_b9f4fcec_80000000_b9f40424_30a019f8_bc230028; -defparam bootram.RAM0.INIT_2A=256'h30c07c00_b9f40d24_30a00000_b000003f_30e08000_b0000000_b800fe84_10a00000; -defparam bootram.RAM0.INIT_2B=256'hb9f410f8_80000000_b9f403d8_30a019bc_80000000_b9f40f48_30a08000_b0000000; -defparam bootram.RAM0.INIT_2C=256'hb9f4fc60_30a00001_b9f4fd4c_80000000_b9f403c0_30a01a7c_b800fe50_10b30000; -defparam bootram.RAM0.INIT_2D=256'hfa610020_3021ffd4_b800ff40_80000000_b9f410c8_30a00000_b0000018_30a07530; -defparam bootram.RAM0.INIT_2E=256'hfac10024_30e00001_30c1001c_12e70000_f0c1001c_fae10028_10b30000_a66500ff; -defparam bootram.RAM0.INIT_2F=256'h10b30000_10f60000_10d70000_10830000_be030030_12c80000_b9f40898_f9e10000; -defparam bootram.RAM0.INIT_30=256'h10640000_a8830001_6463001f_3063ffff_80000000_b9f407d0_30800001_be76001c; -defparam bootram.RAM0.INIT_31=256'hfac10024_3021ffcc_3021002c_b60f0008_eae10028_eac10024_ea610020_e9e10000; -defparam bootram.RAM0.INIT_32=256'hf9e10000_12c80000_12e70000_13250000_13060000_fb210030_fb01002c_fae10028; -defparam bootram.RAM0.INIT_33=256'h32d6ffff_e0770000_f301001c_30e00002_be76005c_30c1001c_10b90000_fa610020; -defparam bootram.RAM0.INIT_34=256'hbe33ffcc_32f70001_b9f4089c_30a0000a_12630000_33180001_b9f407f8_f061001d; -defparam bootram.RAM0.INIT_35=256'heb210030_eb01002c_eae10028_eac10024_ea610020_e9e10000_10730000_10b90000; -defparam bootram.RAM0.INIT_36=256'h80000000_b9f4f998_f9e10000_3021ffe4_30600001_b810ffe0_30210034_b60f0008; -defparam bootram.RAM0.INIT_37=256'h12660000_fb21002c_fb010028_fae10024_fa61001c_3021ffd0_80000000_b60f0008; -defparam bootram.RAM0.INIT_38=256'haa43ffff_12c00000_b810001c_f9e10000_fac10020_13260000_12e70000_13050000; -defparam bootram.RAM0.INIT_39=256'h10960000_90630060_10b80000_b9f405ec_32730001_bcb2002c_16572001_bc120030; -defparam bootram.RAM0.INIT_3A=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffd4_aa43000a_f0730000; -defparam bootram.RAM0.INIT_3B=256'h3021ffd0_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; -defparam bootram.RAM0.INIT_3C=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; -defparam bootram.RAM0.INIT_3D=256'hb9f4051c_32730001_bcb2002c_16572001_12c00000_b8100014_f9e10000_fac10020; -defparam bootram.RAM0.INIT_3E=256'h14999800_32d60001_be32ffdc_aa43000a_f0730000_10960000_90630060_10b80000; -defparam bootram.RAM0.INIT_3F=256'heb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000_10640000_f0130000; -defparam bootram.RAM1.INIT_00=256'h12e60000_12c50000_fae10024_fac10020_fa61001c_3021ffd8_30210030_b60f0008; -defparam bootram.RAM1.INIT_01=256'hbe32ffec_aa43000a_f0730000_90630060_10b60000_b9f404b0_12660000_f9e10000; -defparam bootram.RAM1.INIT_02=256'heae10024_eac10020_ea61001c_e9e10000_10770000_f0130000_3273ffff_32730001; -defparam bootram.RAM1.INIT_03=256'he9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4_10c50000_30210028_b60f0008; -defparam bootram.RAM1.INIT_04=256'hb60f0008_e9e10000_80000000_b9f40448_f9e10000_3021ffe4_3021001c_b60f0008; -defparam bootram.RAM1.INIT_05=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc_f9e10000_3021ffe4_3021001c; -defparam bootram.RAM1.INIT_06=256'hbe060024_90c30060_12660000_e0660000_f9e10000_fac10020_fa61001c_3021ffdc; -defparam bootram.RAM1.INIT_07=256'h10b60000_be26fff0_90c30060_e0730000_32730001_b9f40324_10b60000_12c50000; -defparam bootram.RAM1.INIT_08=256'hfac1001c_3021ffe0_30210024_b60f0008_10600000_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_09=256'heac1001c_e9e10000_30c0000a_b9f402dc_10b60000_12c50000_b9f4ff9c_f9e10000; -defparam bootram.RAM1.INIT_0A=256'h10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000_30210020_b60f0008_10600000; -defparam bootram.RAM1.INIT_0B=256'h10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000_3021001c_b60f0008_e9e10000; -defparam bootram.RAM1.INIT_0C=256'he9e10000_30c0000a_b9f40278_f9e10000_3021ffe4_3021001c_b60f0008_e9e10000; -defparam bootram.RAM1.INIT_0D=256'hb9f40250_f9e10000_10a00000_12c50000_fac1001c_3021ffe0_3021001c_b60f0008; -defparam bootram.RAM1.INIT_0E=256'hfac1001c_3021ffe0_30210020_b60f0008_eac1001c_e9e10000_10760000_10d60000; -defparam bootram.RAM1.INIT_0F=256'h30210020_b60f0008_eac1001c_e9e10000_10760000_12c60000_b9f40228_f9e10000; -defparam bootram.RAM1.INIT_10=256'h94e08001_3021001c_b60f0008_e9e10000_80000000_b9f401b8_f9e10000_3021ffe4; -defparam bootram.RAM1.INIT_11=256'h80633000_84632000_84c62800_a866ffff_e880f81c_b0000000_9404c001_ac870002; -defparam bootram.RAM1.INIT_12=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f81c_b0000000_f860200c; -defparam bootram.RAM1.INIT_13=256'h88a52000_e880f81c_b0000000_9406c001_acc30002_94608001_80000000_b60f0008; -defparam bootram.RAM1.INIT_14=256'h9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c_b0000000_f8a0200c; -defparam bootram.RAM1.INIT_15=256'ha866ffff_e880f820_b0000000_9404c001_ac870002_94e08001_80000000_b60f0008; -defparam bootram.RAM1.INIT_16=256'h94808001_a4e70002_f860f820_b0000000_f8602020_80633000_84632000_84c62800; -defparam bootram.RAM1.INIT_17=256'hfae10024_fa61001c_3021ffd4_80000000_b60f0008_9404c001_80843800_ac840002; -defparam bootram.RAM1.INIT_18=256'hbe060040_90c30060_13050000_12e60000_e0660000_fac10020_f9e10000_fb010028; -defparam bootram.RAM1.INIT_19=256'h10730000_be120028_16569800_32c70001_b8100014_32600001_be670038_12660000; -defparam bootram.RAM1.INIT_1A=256'h10730000_3273ffff_32730001_be26ffe4_90c30060_c0779800_10b80000_b9f400cc; -defparam bootram.RAM1.INIT_1B=256'h3021ffe4_3021002c_b60f0008_eb010028_eae10024_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_1C=256'hf0c51e7c_3021001c_b60f0008_e9e10000_30c0000a_b9f40084_f9e10000_10a00000; -defparam bootram.RAM1.INIT_1D=256'h80000000_b60f0008_f8653700_64a50405_e4661bac_10c63000_80000000_b60f0008; -defparam bootram.RAM1.INIT_1E=256'h90c60060_b9f4ffc4_10b30000_e0d31e7c_12600000_f9e10000_fa61001c_3021ffe0; -defparam bootram.RAM1.INIT_1F=256'he9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc_32730001_10b30000_e0d31ba8; -defparam bootram.RAM1.INIT_20=256'h12c60000_f9e10000_fac10020_fa61001c_3021ffdc_30210020_b60f0008_ea61001c; -defparam bootram.RAM1.INIT_21=256'hfac5000c_bc03fffc_e8650004_30a33700_64730405_12650000_be120030_aa46000a; -defparam bootram.RAM1.INIT_22=256'hbc32ffd0_aa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_23=256'hf9e10000_fac10020_fa61001c_3021ffdc_64730405_b810ffc8_30c0000d_b9f4ffac; -defparam bootram.RAM1.INIT_24=256'hbc040008_e8830004_30633700_64730405_12650000_be120030_aa46000a_12c60000; -defparam bootram.RAM1.INIT_25=256'haa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000_fac3000c; -defparam bootram.RAM1.INIT_26=256'h30a53700_64a50405_64730405_b810ffc4_80000000_b9f4ff44_30c0000d_be32ffd0; -defparam bootram.RAM1.INIT_27=256'he8650008_30a53700_64a50405_80000000_b60f0008_e8650010_bc03fffc_e8650008; -defparam bootram.RAM1.INIT_28=256'h64a50405_80000000_b60f0008_90630060_be24fff8_e8850008_e8650010_bc030014; -defparam bootram.RAM1.INIT_29=256'h32600001_be230040_e8760008_32c53700_fa61001c_f9e10000_fac10020_3021ffdc; -defparam bootram.RAM1.INIT_2A=256'hbe03ffe8_e8760008_30a00001_b9f401e0_3060ffff_be120034_aa53012d_b8000010; -defparam bootram.RAM1.INIT_2B=256'he9e10000_e8760010_3060ffff_be52000c_16539001_3240012b_3273ffff_32730001; -defparam bootram.RAM1.INIT_2C=256'h32400004_a463000f_e8603324_f8003108_30210024_b60f0008_eac10020_ea61001c; -defparam bootram.RAM1.INIT_2D=256'ha46300ff_64a30008_e4641bb8_10831800_30600004_10831800_beb20010_16439001; -defparam bootram.RAM1.INIT_2E=256'ha4a500ff_be070088_80000000_b60f0008_f8603108_30600080_f8a03104_f8603100; -defparam bootram.RAM1.INIT_2F=256'hf8803110_30800090_f860310c_a0630001_10652800_be23fff8_a4630040_e8603110; -defparam bootram.RAM1.INIT_30=256'haa470001_10800000_be230058_a4630080_e8603110_bc23fff8_a4630002_e8603110; -defparam bootram.RAM1.INIT_31=256'h30e7ffff_e860310c_bc23fff8_a4630002_e8603110_f8603110_30600020_be120038; -defparam bootram.RAM1.INIT_32=256'h30600068_b810ffd0_30600020_be32ffd8_aa470001_30c60001_be07001c_f0660000; -defparam bootram.RAM1.INIT_33=256'ha4a500ff_10640000_b60f0008_f8603110_30600040_10640000_b60f0008_30800001; -defparam bootram.RAM1.INIT_34=256'h306000d0_30600090_be27000c_f860310c_10652800_be23fff8_a4630040_e8603110; -defparam bootram.RAM1.INIT_35=256'h10800000_be23005c_a4630080_e8603110_bc23fff8_a4630002_e8603110_f8603110; -defparam bootram.RAM1.INIT_36=256'hf8803110_bc120030_aa470001_f860310c_30800010_e0660000_30800001_be070068; -defparam bootram.RAM1.INIT_37=256'hbe070028_30e7ffff_be23001c_a4630080_e8603110_bc23fff8_a4630002_e8603110; -defparam bootram.RAM1.INIT_38=256'hb60f0008_f8603110_30600040_10800000_30800050_b810ffd4_b800ffc4_30c60001; -defparam bootram.RAM1.INIT_39=256'hbc260054_a4c30000_b0008000_e8603324_10640000_b60f0008_30800001_10640000; -defparam bootram.RAM1.INIT_3A=256'h80000000_10800000_bc660030_e8c01e80_10660000_be650048_bc430054_e8601e80; -defparam bootram.RAM1.INIT_3B=256'h16443000_30840001_80000000_80000000_80000000_80000000_80000000_80000000; -defparam bootram.RAM1.INIT_3C=256'ha4630007_e8603324_80000000_b60f0008_bc32ffc8_16432800_30630001_bc32ffdc; -defparam bootram.RAM1.INIT_3D=256'h16459001_3240005a_3065ffa9_90a50060_b800ff9c_f8801e80_e4831bc4_10631800; -defparam bootram.RAM1.INIT_3E=256'h3085ffd0_be52000c_16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024; -defparam bootram.RAM1.INIT_3F=256'hf9e10000_fb610034_13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff; -defparam bootram.RAM2.INIT_00=256'haa43003a_13660000_e0790000_fb410030_fb010028_fae10024_fac10020_fa61001c; -defparam bootram.RAM2.INIT_01=256'heb010028_eae10024_eac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034; -defparam bootram.RAM2.INIT_02=256'hc085c800_30a00001_e8c01e84_30210038_b60f0008_eb610034_eb410030_eb21002c; -defparam bootram.RAM2.INIT_03=256'hb810ffac_bc23ffe4_a4630044_c0662000_a4a300ff_be04001c_90840060_30650001; -defparam bootram.RAM2.INIT_04=256'h12761800_66c30404_b9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe; -defparam bootram.RAM2.INIT_05=256'he0b90005_30a0fffd_be38ff74_93040060_e083000b_10791800_fa7b0004_10739800; -defparam bootram.RAM2.INIT_06=256'h66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0; -defparam bootram.RAM2.INIT_07=256'he0b90007_fafb0008_12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006; -defparam bootram.RAM2.INIT_08=256'hbe130060_f07b0000_1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0; -defparam bootram.RAM2.INIT_09=256'hb9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000; -defparam bootram.RAM2.INIT_0A=256'he8fb0004_ea7b000c_d0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000; -defparam bootram.RAM2.INIT_0B=256'headb0008_a74300ff_be52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001; -defparam bootram.RAM2.INIT_0C=256'h107a1800_12c7b000_10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000; -defparam bootram.RAM2.INIT_0D=256'ha6d600ff_1063c000_16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10; -defparam bootram.RAM2.INIT_0E=256'ha4630100_e8603b10_10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff; -defparam bootram.RAM2.INIT_0F=256'ha4a500ff_80884800_a1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8; -defparam bootram.RAM2.INIT_10=256'ha0840100_f8603b18_a46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10; -defparam bootram.RAM2.INIT_11=256'hb60f0008_e8603b00_bc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10; -defparam bootram.RAM2.INIT_12=256'h31200400_31000008_10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000; -defparam bootram.RAM2.INIT_13=256'h3021ffc4_3021001c_b60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001; -defparam bootram.RAM2.INIT_14=256'hb9f4ff3c_fae10034_13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030; -defparam bootram.RAM2.INIT_15=256'hfac03b00_f8603b04_3060000b_66d60408_f8603b10_f8003b18_30600400_12670000; -defparam bootram.RAM2.INIT_16=256'h80000000_b9f4ff00_f8603b10_30600528_f8803b10_30800428_f8603b18_30600001; -defparam bootram.RAM2.INIT_17=256'hf8803b10_30800500_f8603b10_30600400_3261001c_12e00000_12d30000_be18009c; -defparam bootram.RAM2.INIT_18=256'he8803b04_f8610020_e8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8; -defparam bootram.RAM2.INIT_19=256'h30a00010_10800000_beb20034_16459003_22400010_f8610028_e8603b00_f8810024; -defparam bootram.RAM2.INIT_1A=256'hbeb20020_1658b803_12f72800_bc32fff0_16442800_30840001_d0762000_c0732000; -defparam bootram.RAM2.INIT_1B=256'hf8003b18_12d62800_be52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800; -defparam bootram.RAM2.INIT_1C=256'hb0009f00_3021003c_b60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000; -defparam bootram.RAM2.INIT_1D=256'h31200400_b9f4fe34_f9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000; -defparam bootram.RAM2.INIT_1E=256'h3021ffe4_e860f828_b0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000; -defparam bootram.RAM2.INIT_1F=256'h64830008_80000000_b9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000; -defparam bootram.RAM2.INIT_20=256'h16439001_32400015_80000000_b9f40330_a46300ff_be120010_aa440020_a48400ff; -defparam bootram.RAM2.INIT_21=256'hb0000000_b800ffb0_f860f828_b0000000_bc52ffe4_16439001_32400018_bcb2fff0; -defparam bootram.RAM2.INIT_22=256'hb9f4ff40_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824; -defparam bootram.RAM2.INIT_23=256'h80000000_b9f402c8_a4a300ff_be120010_aa440020_a48400ff_64830008_80000000; -defparam bootram.RAM2.INIT_24=256'hb0000000_e0651bbe_bc52ffe4_16459001_32400018_bcb2fff0_16459001_32400015; -defparam bootram.RAM2.INIT_25=256'h10c50000_12c00000_fac1001c_3021ffe0_b800ffa4_f860f824_b0000000_f8a0f828; -defparam bootram.RAM2.INIT_26=256'heac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40334_f9e10000_10b60000; -defparam bootram.RAM2.INIT_27=256'hb810001c_30e1001c_b9f4fd88_f9e10000_30c00040_3021ffa4_30210020_b60f0008; -defparam bootram.RAM2.INIT_28=256'he063001c_10612800_10600000_be520044_16459001_3240003e_30a50001_10a00000; -defparam bootram.RAM2.INIT_29=256'haa440099_e083001c_10612800_30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff; -defparam bootram.RAM2.INIT_2A=256'h3021005c_b60f0008_e9e10000_3021005c_b60f0008_e9e10000_30600001_be32ffc8; -defparam bootram.RAM2.INIT_2B=256'h10b60000_30c00006_b9f4fd08_f9e10000_10f60000_32c1001c_fac10028_3021ffd4; -defparam bootram.RAM2.INIT_2C=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8_30c01bd8; -defparam bootram.RAM2.INIT_2D=256'h65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008_6464001f; -defparam bootram.RAM2.INIT_2E=256'ha4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407_65240405; -defparam bootram.RAM2.INIT_2F=256'h81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800_10842000; -defparam bootram.RAM2.INIT_30=256'h64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008_80634800; -defparam bootram.RAM2.INIT_31=256'ha4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407_65050405; -defparam bootram.RAM2.INIT_32=256'h81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000_10a52800; -defparam bootram.RAM2.INIT_33=256'hb00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff_81294000; -defparam bootram.RAM2.INIT_34=256'h30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000_a6c5ffff; -defparam bootram.RAM2.INIT_35=256'h30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99_b9f4ff6c; -defparam bootram.RAM2.INIT_36=256'h30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008_b9f4ff4c; -defparam bootram.RAM2.INIT_37=256'h30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b_b9f4ff2c; -defparam bootram.RAM2.INIT_38=256'h10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000_b9f4ff0c; -defparam bootram.RAM2.INIT_39=256'h30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020_b9f4feec; -defparam bootram.RAM2.INIT_3A=256'hb6110000_30a0ffff_b9f4e91c_80000000_b9f4f220_f9e10000_3021ffe4_30a01be0; -defparam bootram.RAM2.INIT_3B=256'h22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000_80000000; -defparam bootram.RAM2.INIT_3C=256'h16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c_16479003; -defparam bootram.RAM2.INIT_3D=256'h30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc_bc320040; -defparam bootram.RAM2.INIT_3E=256'h30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028_aa47ffff; -defparam bootram.RAM2.INIT_3F=256'h2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff_30e7ffff; -defparam bootram.RAM3.INIT_00=256'hbc070024_11050000_be030034_a4630003_80662800_10850000_beb20018_16479003; -defparam bootram.RAM3.INIT_01=256'h30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000_11040000; -defparam bootram.RAM3.INIT_02=256'he8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000_b60f0008; -defparam bootram.RAM3.INIT_03=256'h31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c_f8880008; -defparam bootram.RAM3.INIT_04=256'h22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003_22400003; -defparam bootram.RAM3.INIT_05=256'he860193c_10880000_b810ff68_11044000_10c43000_30840004_be52ffec_16479003; -defparam bootram.RAM3.INIT_06=256'h3273fffc_99fc1800_bc120018_aa43ffff_3260193c_f9e10000_fa61001c_3021ffe0; -defparam bootram.RAM3.INIT_07=256'h3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff_e8730000; -defparam bootram.RAM3.INIT_08=256'h30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e7d4_d9e00800; -defparam bootram.RAM3.INIT_09=256'hffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e74c_d9e00800_3021fff8; -defparam bootram.RAM3.INIT_0A=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff_00000000; -defparam bootram.RAM3.INIT_0B=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265; -defparam bootram.RAM3.INIT_0C=256'h53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00; -defparam bootram.RAM3.INIT_0D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; -defparam bootram.RAM3.INIT_0E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072; -defparam bootram.RAM3.INIT_0F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368; -defparam bootram.RAM3.INIT_10=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361; -defparam bootram.RAM3.INIT_11=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061; -defparam bootram.RAM3.INIT_12=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845; -defparam bootram.RAM3.INIT_13=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070; -defparam bootram.RAM3.INIT_14=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072; -defparam bootram.RAM3.INIT_15=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d; -defparam bootram.RAM3.INIT_16=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374; -defparam bootram.RAM3.INIT_17=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67; -defparam bootram.RAM3.INIT_18=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00; -defparam bootram.RAM3.INIT_19=256'h6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61_756e642e; -defparam bootram.RAM3.INIT_1A=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; -defparam bootram.RAM3.INIT_1B=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068; -defparam bootram.RAM3.INIT_1C=256'h6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d; -defparam bootram.RAM3.INIT_1D=256'h0018000f_ffff0031_01b200d9_05160364_14580a2c_05050400_2e2e2e00_77617265; -defparam bootram.RAM3.INIT_1E=256'hb8080000_b0000000_10101200_06820594_09c407d0_13880d05_00002710_000b0000; -defparam bootram.RAM3.INIT_1F=256'h20202020_28282820_20202828_20202020_00202020_00000000_6f72740a_0a0a6162; -defparam bootram.RAM3.INIT_20=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020; -defparam bootram.RAM3.INIT_21=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404; -defparam bootram.RAM3.INIT_22=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101; -defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a7fc0400_3a0b0b0b_0bb1fc0c_80700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba8b92d_88080b0b_80088408; +defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; +defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; +defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; +defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; +defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; +defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; +defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c3040000_0b0b0b88; +defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a6_0981050b_72729f06; +defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; +defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; +defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; +defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; +defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; +defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_e8738306_0b0b0bb1_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_f32d5050_0b0b0ba1_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_a52d5050_0b0b0ba3_88087575_80088408; +defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; +defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; +defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bb1f80c_810b0b0b; +defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; +defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; +defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d93f0410_81f33fa1; +defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; +defparam bootram.RAM0.INIT_22=256'h535104b1_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; +defparam bootram.RAM0.INIT_23=256'hcc0c8290_a0800bb9_b9c80c82_0b0b0b0b_38838080_08822eb9_a138b1fc_f808802e; +defparam bootram.RAM0.INIT_24=256'h80808480_b9cc0cf8_8082800b_c80cf880_0b0b0bb9_8080a40b_0c04f880_800bb9d0; +defparam bootram.RAM0.INIT_25=256'h0baa880b_cc0c0b0b_80940bb9_0c80c0a8_0b0bb9c8_808c0b0b_0480c0a8_0bb9d00c; +defparam bootram.RAM0.INIT_26=256'hb2840c70_92388412_5270802e_08700852_a338b284_d4335170_ff3d0db9_b9d00c04; +defparam bootram.RAM0.INIT_27=256'hc408802e_0b0b0bb9_04803d0d_833d0d04_0bb9d434_70f03881_70085252_2db28408; +defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb9c4_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; +defparam bootram.RAM0.INIT_29=256'h518bdc3f_d0055273_3fb23dfe_525486b3_59923d70_3dfee005_d03d0db2_3d0d0404; +defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_8e3faa8c_5273519c_38765378_ff74278f_775481ff_8008b238; +defparam bootram.RAM0.INIT_2B=256'hb039803d_85b13fff_39aac451_aa905184_3f91f53f_8c5185bf_068f38aa_812e0981; +defparam bootram.RAM0.INIT_2C=256'h0ca78851_0b81a08c_3d0d81ff_3d0d04fc_51f63982_380bff11_70ff2e87_0dff1351; +defparam bootram.RAM0.INIT_2D=256'h81ff0655_ee3f8008_84f53f83_3faac851_f43f86e9_85f43f8e_81a08c0c_dd3f800b; +defparam bootram.RAM0.INIT_2E=256'h81fc8080_5184d03f_c338aaf4_51547380_70810651_08708d2a_3f81c6b4_805182ed; +defparam bootram.RAM0.INIT_2F=256'h8ebe3f90_fc808051_ffff5281_80805380_82c33f82_a6388151_8008802e_5190d43f; +defparam bootram.RAM0.INIT_30=256'ha851848b_74b238ac_3ffe8d3f_d0518497_3f8a39ab_735191b0_5184a43f_e33fab94; +defparam bootram.RAM0.INIT_31=256'hfec03fb0_3f82ac51_815181f9_5183f83f_9938acd4_8008802e_518fbf3f_3fb0800a; +defparam bootram.RAM0.INIT_32=256'h83cd3f82_38addc51_08802eaa_8fe53f80_98800a51_5183e03f_f73fad8c_800a5190; +defparam bootram.RAM0.INIT_33=256'h3faeac51_853f8fe8_82ac51fe_5183b83f_cf3fae88_800a518d_ffff5298_80805380; +defparam bootram.RAM0.INIT_34=256'h5380ffff_38828080_08802eb5_80085480_518fa83f_81fc8080_5183a43f_ba39aee8; +defparam bootram.RAM0.INIT_35=256'hee3f82ac_ab945182_3f8fad3f_ac51fdca_82fd3f82_3fae8851_80518d94_5281fc80; +defparam bootram.RAM0.INIT_36=256'h04f83d0d_0c863d0d_cf3f7380_82d93ffc_39abd051_3f81548a_80518ff4_51fdbb3f; +defparam bootram.RAM0.INIT_37=256'h70810558_8a3d3476_17575473_b7387581_54807425_74ff1656_5a575758_7a7c7f7f; +defparam bootram.RAM0.INIT_38=256'h8a518790_81ff0654_e23f8008_ff065185_05527781_538a3dfc_a1053482_33028405; +defparam bootram.RAM0.INIT_39=256'h748338dc_5580de56_02a30533_04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e; +defparam bootram.RAM0.INIT_3A=256'h7c5702ab_04f93d0d_3f883d0d_d051ff89_81f75280_3dfc0553_34815488_5675883d; +defparam bootram.RAM0.INIT_3B=256'h56547380_81ff0670_823f8008_70525685_02a70533_3dfc0552_34815389_0533893d; +defparam bootram.RAM0.INIT_3C=256'h83388155_5473802e_ff067056_3f800881_755183c5_76537b52_77259738_2e9e3880; +defparam bootram.RAM0.INIT_3D=256'h883d3356_a03f800b_80d051ff_5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89; +defparam bootram.RAM0.INIT_3E=256'h81e33f72_53538051_3d0d7470_3d0d04fe_75800c88_83388156_2e098106_567480de; +defparam bootram.RAM0.INIT_3F=256'h7481ff06_90388115_5472802e_81ff0654_56743370_0d777956_0d04fb3d_800c843d; +defparam bootram.RAM1.INIT_00=256'h8a527251_5253cb3f_74765370_04fe3d0d_0c873d0d_39800b80_81bb3fe5_53765255; +defparam bootram.RAM1.INIT_01=256'h78705555_fc3d0d76_833d0d04_8051de3f_3d0d7352_3d0d04ff_0b800c84_819f3f80; +defparam bootram.RAM1.INIT_02=256'h38807334_098106e7_52718a2e_0881ff06_08733480_81b23f80_13537451_55843981; +defparam bootram.RAM1.INIT_03=256'h33b28812_51028f05_803d0d72_833d0d04_8051c93f_3d0d7352_3d0d04ff_73800c86; +defparam bootram.RAM1.INIT_04=256'h0d04fe3d_5351833d_7022720c_10afa405_ce800575_73a02981_04ff3d0d_34823d0d; +defparam bootram.RAM1.INIT_05=256'h38843d0d_827325e7_3f811353_527251d1_b28c1333_7251c93f_88133352_0d8053b2; +defparam bootram.RAM1.INIT_06=256'h388d5273_09810687_5372812e_b2881433_81069438_748a2e09_76785654_04fc3d0d; +defparam bootram.RAM1.INIT_07=256'hff3d0d73_863d0d04_748c150c_802ef838_14085372_80055484_a02981ce_51df3f73; +defparam bootram.RAM1.INIT_08=256'h800b81c2_04ff3d0d_0c833d0d_90120880_802ef838_12085170_80055288_a02981ce; +defparam bootram.RAM1.INIT_09=256'h0681c280_227081ff_b2900570_84517010_71258338_06515184_a408708f_880c81c6; +defparam bootram.RAM1.INIT_0A=256'h05970533_76780288_04fd3d0d_0c833d0d_0b81c288_51518180_81c2840c_0c70882a; +defparam bootram.RAM1.INIT_0B=256'h10810781_70f13872_06515151_862a7081_c2900870_81863881_5171802e_55535481; +defparam bootram.RAM1.INIT_0C=256'h90087087_f13881c2_51515170_2a708106_90087081_900c81c2_900b81c2_c28c0c81; +defparam bootram.RAM1.INIT_0D=256'h38a05170_71812e83_3880e851_71802eb1_802eba38_51515170_70813251_2a708106; +defparam bootram.RAM1.INIT_0E=256'h81055634_51707470_81c28c08_5170f138_81065151_70812a70_81c29008_81c2900c; +defparam bootram.RAM1.INIT_0F=256'h02880597_3d0d7678_3d0d04fd_70800c85_81c2900c_3980c00b_39815188_ff1252cc; +defparam bootram.RAM1.INIT_10=256'hd0517180_c28c0c81_38721081_515170f1_70810651_0870862a_5481c290_05335553; +defparam bootram.RAM1.INIT_11=256'hc2900870_70f13881_06515151_812a7081_c2900870_c2900c81_90517081_2e843881; +defparam bootram.RAM1.INIT_12=256'h8c0c80d0_733381c2_2e80c538_cf387180_70802e80_51515151_06708132_872a7081; +defparam bootram.RAM1.INIT_13=256'h3881c290_515170f1_70810651_0870812a_0c81c290_7081c290_83389051_5171812e; +defparam bootram.RAM1.INIT_14=256'h81518a39_54ffb739_14ff1353_2e8e3881_51517080_81325151_70810670_0870872a; +defparam bootram.RAM1.INIT_15=256'h24a638b2_52528071_81c6a408_ff3d0d73_853d0d04_5170800c_c2900c80_80c00b81; +defparam bootram.RAM1.INIT_16=256'h7151ff11_72258938_0c515180_1122b29c_8e06b2a0_a4087010_923881c6_9c088025; +defparam bootram.RAM1.INIT_17=256'h269638c9_527180da_ff065152_a9117081_8f0533ff_ff3d0d02_833d0d04_5170fb38; +defparam bootram.RAM1.INIT_18=256'h3d0d797b_3d0d04f9_70800c83_ff065151_d0127081_b9268938_06515171_127081ff; +defparam bootram.RAM1.INIT_19=256'haa387281_5371782e_81173353_ef38810b_09810682_5371ba2e_335358ff_58568076; +defparam bootram.RAM1.INIT_1A=256'hbd387216_71802e82_53515452_06515151_337080c4_33afd511_06721970_147081ff; +defparam bootram.RAM1.INIT_1B=256'h3f800881_5252feec_06821733_842b9ff0_fb3f8008_163351fe_71d83881_70335152; +defparam bootram.RAM1.INIT_1C=256'hcb3f8008_163351fe_828a3883_54fd5374_11335753_7010178b_7084190c_ff067205; +defparam bootram.RAM1.INIT_1D=256'h53fea93f_85173352_80067305_882b83fe_bb3f8008_335253fe_80068417_8c2bbfe0; +defparam bootram.RAM1.INIT_1E=256'h163351fe_88180c87_ff067305_3f800881_5253fe98_05861733_9ff00673_8008842b; +defparam bootram.RAM1.INIT_1F=256'hd2387410_74742780_52717734_3f800812_5252fdf8_06881733_842b9ff0_873f8008; +defparam bootram.RAM1.INIT_20=256'h842b9ff0_cf3f8008_565152fd_52335552_70708105_08177119_ff068c19_89057081; +defparam bootram.RAM1.INIT_21=256'h197081ff_81ff0681_33701a70_17081570_7274348c_80081353_53fdc13f_06723352; +defparam bootram.RAM1.INIT_22=256'h05547305_0571882a_08783372_17088818_ffb03884_17087526_51515284_065a525b; +defparam bootram.RAM1.INIT_23=256'h068a1533_842b9ff0_f33f8008_515354fc_3356545b_101a8911_81ff0673_19703070; +defparam bootram.RAM1.INIT_24=256'h83398053_8539fe53_81068938_77722e09_5152fb53_7081ff06_3f800812_5252fce4; +defparam bootram.RAM1.INIT_25=256'h0d04fe3d_f138823d_51515170_2a708106_90087088_3d0d81d6_3d0d0480_72800c89; +defparam bootram.RAM1.INIT_26=256'h81065151_70882a70_81d69008_80075353_060780c0_067a8c80_337880ff_0d029305; +defparam bootram.RAM1.INIT_27=256'h900c7251_800781d6_980c7182_ff0681d6_900c7581_0c7181d6_7681d680_5170f138; +defparam bootram.RAM1.INIT_28=256'h0c843d0d_08517080_3881d680_515170f1_70810651_0870882a_3881d690_72802e96; +defparam bootram.RAM1.INIT_29=256'hf33d0d60_863d0d04_51ff873f_53805280_55885480_940c8880_810b81d6_04fc3d0d; +defparam bootram.RAM1.INIT_2A=256'h800c810b_882b81d6_d6840c7f_0c8b0b81_0b81d690_980c8880_800b81d6_59fee43f; +defparam bootram.RAM1.INIT_2B=256'h80de3888_58777927_3f615780_900cfeb3_a80b81d6_d6900c8a_88a80b81_81d6980c; +defparam bootram.RAM1.INIT_2C=256'h84085d81_085c81d6_5b81d688_81d68c08_0cfe983f_0b81d690_900c8a80_800b81d6; +defparam bootram.RAM1.INIT_2D=256'h1a547333_279c3874_80557476_83387356_56737627_31555a90_8b3d7979_d680085e; +defparam bootram.RAM1.INIT_2E=256'h800b81d6_58ff9e39_e1397518_3f811555_b05183e3_741852af_59347653_77708105; +defparam bootram.RAM1.INIT_2F=256'h57557417_84059d05_c73f8002_526851fe_545780c0_0d883d70_0d04ea3d_980c8f3d; +defparam bootram.RAM1.INIT_30=256'h2e098106_54738199_16703351_06943874_aa2e0981_9d387381_7381ff2e_70335154; +defparam bootram.RAM1.INIT_31=256'h70545486_3d0d863d_3d0d04f9_73800c98_d1388054_55be7527_8b398115_85388154; +defparam bootram.RAM1.INIT_32=256'h5574800c_06833881_752e0981_9e3f8008_52735189_8653afb8_f73f8055_527951fd; +defparam bootram.RAM1.INIT_33=256'h832a8406_872a0771_2a820671_05337085_3d0d0297_940c04fd_810b81a0_893d0d04; +defparam bootram.RAM1.INIT_34=256'h2b80c006_ff067685_07077081_a0067173_0674832b_07731090_06717307_72812a88; +defparam bootram.RAM1.INIT_35=256'hfe3d0d74_853d0d04_52555552_52535155_d4800c51_81ff0681_872b0770_70720778; +defparam bootram.RAM1.INIT_36=256'h51ff8c3f_923f8199_81aa51ff_51ff983f_9e3f81ff_81ff51ff_d00a0753_d00a0681; +defparam bootram.RAM1.INIT_37=256'hfeed3fb2_81ff0651_fef53f72_ff065252_882a7081_ff813f72_3f80e151_b251ff87; +defparam bootram.RAM1.INIT_38=256'h3fb051fe_5253fecf_7081ff06_3f72902a_2a51fedb_e23f7298_818151fe_51fee83f; +defparam bootram.RAM1.INIT_39=256'ha051feab_51feb03f_feb53f80_ba3fa051_3f8e51fe_8051febf_51fec43f_ca3f81a1; +defparam bootram.RAM1.INIT_3A=256'h9f2a515b_33703070_9005bb05_7e616302_f63d0d7c_0d04ff39_a63f843d_3f8051fe; +defparam bootram.RAM1.INIT_3B=256'h38795578_77772694_2d763057_52ad5178_2e8a3879_8f387580_57768025_5f5d5b59; +defparam bootram.RAM1.INIT_3C=256'h3351782d_08afc005_82b83f80_77527651_51ffbd3f_a03f8008_52765182_54805377; +defparam bootram.RAM1.INIT_3D=256'h52089fa4_70708405_3d0d8c3d_3d0d04f7_f0a53f82_8b053351_803d0d02_8c3d0d04; +defparam bootram.RAM1.INIT_3E=256'h80db3881_2e098106_065675a5_387681ff_802e81d1_06575775_337081ff_5c5a5878; +defparam bootram.RAM1.INIT_3F=256'h8a387580_7580e324_e32eb938_a0387580_7580f024_2e80fb38_597580f0_19703357; +defparam bootram.RAM2.INIT_00=256'h387580f3_80f5248b_2eac3875_397580f5_c638818b_80e42e80_81953975_2e819e38; +defparam bootram.RAM2.INIT_01=256'h51792d80_56805275_12335259_77841983_3880ec39_80f82eba_80f53975_2e80db38; +defparam bootram.RAM2.INIT_02=256'h559fa454_52595680_84197108_53903977_9fa45480_59568055_19710852_da397784; +defparam bootram.RAM2.INIT_03=256'h9e397784_51fdd13f_53905275_9fa45480_59568055_19710852_92397784_81538a52; +defparam bootram.RAM2.INIT_04=256'h1959fea3_2dec3981_58335179_76708105_8e388052_5675802e_59567633_19710859; +defparam bootram.RAM2.INIT_05=256'h05085182_528c0888_088c0508_0d80538c_8c0cfd3d_048c0802_0c8b3d0d_39800b80; +defparam bootram.RAM2.INIT_06=256'h08528c08_8c088c05_3d0d8153_028c0cfd_0c048c08_853d0d8c_70800c54_de3f8008; +defparam bootram.RAM2.INIT_07=256'h0b8c08fc_f93d0d80_08028c0c_8c0c048c_54853d0d_0870800c_82b93f80_88050851; +defparam bootram.RAM2.INIT_08=256'h0c8c08fc_8c08f405_050c800b_308c0888_08880508_25ab388c_88050880_050c8c08; +defparam bootram.RAM2.INIT_09=256'hab388c08_05088025_0c8c088c_8c08fc05_08f40508_f4050c8c_810b8c08_05088838; +defparam bootram.RAM2.INIT_0A=256'h050c8c08_0b8c08f0_08883881_8c08fc05_08f0050c_0c800b8c_8c088c05_8c050830; +defparam bootram.RAM2.INIT_0B=256'h8c08f805_3f800870_085181a7_8c088805_8c050852_80538c08_08fc050c_f005088c; +defparam bootram.RAM2.INIT_0C=256'h800c5489_f8050870_050c8c08_308c08f8_08f80508_2e8c388c_fc050880_0c548c08; +defparam bootram.RAM2.INIT_0D=256'h388c0888_08802593_8c088805_08fc050c_0d800b8c_8c0cfb3d_048c0802_3d0d8c0c; +defparam bootram.RAM2.INIT_0E=256'h08308c08_8c088c05_80258c38_088c0508_fc050c8c_810b8c08_0888050c_0508308c; +defparam bootram.RAM2.INIT_0F=256'h8c08fc05_f8050c54_08708c08_51ad3f80_08880508_0508528c_538c088c_8c050c81; +defparam bootram.RAM2.INIT_10=256'h8c0c048c_54873d0d_0870800c_8c08f805_08f8050c_0508308c_388c08f8_08802e8c; +defparam bootram.RAM2.INIT_11=256'h88050827_05088c08_0c8c088c_8c08f805_050c800b_0b8c08fc_fd3d0d81_08028c0c; +defparam bootram.RAM2.INIT_12=256'h088c050c_0508108c_388c088c_05082499_0b8c088c_2ea33880_fc050880_ac388c08; +defparam bootram.RAM2.INIT_13=256'h8c088805_088c0508_80c9388c_0508802e_398c08fc_fc050cc9_08108c08_8c08fc05; +defparam bootram.RAM2.INIT_14=256'h0508078c_088c08fc_8c08f805_0888050c_0508318c_088c088c_8c088805_0826a138; +defparam bootram.RAM2.INIT_15=256'hffaf398c_088c050c_08812a8c_8c088c05_08fc050c_08812a8c_8c08fc05_08f8050c; +defparam bootram.RAM2.INIT_16=256'h8c08f405_f8050870_8d398c08_f4050c51_08708c08_8c088805_802e8f38_08900508; +defparam bootram.RAM2.INIT_17=256'h38747407_8372278c_79565652_3d0d7877_8c0c04fc_0c853d0d_f4050880_0c518c08; +defparam bootram.RAM2.INIT_18=256'hbd388115_2e098106_52537271_74337433_ff2ea038_ff125271_802eb038_83065170; +defparam bootram.RAM2.INIT_19=256'h0873082e_74545170_3d0d0474_0b800c86_06e23880_ff2e0981_54555571_8115ff14; +defparam bootram.RAM2.INIT_1A=256'h31800c86_af397271_735555ff_26e93870_54517183_14fc1454_38841184_0981068f; +defparam bootram.RAM2.INIT_1B=256'ha738ff12_5170802e_75078306_278c3872_55558f72_797b5555_3d0d7670_3d0d04fc; +defparam bootram.RAM2.INIT_1C=256'h3874800c_098106ea_5271ff2e_5634ff12_74708105_81055433_98387270_5271ff2e; +defparam bootram.RAM2.INIT_1D=256'h530c7270_71708405_84055408_530c7270_71708405_84055408_74517270_863d0d04; +defparam bootram.RAM2.INIT_1E=256'hc9388372_52718f26_530cf012_71708405_84055408_530c7270_71708405_84055408; +defparam bootram.RAM2.INIT_1F=256'hfd3d0d80_54ff8339_26ed3870_12527183_05530cfc_08717084_70840554_27953872; +defparam bootram.RAM2.INIT_20=256'h3f800851_8151e2f7_3fb2b052_ce3fdfec_b9d80ce0_2e983873_54547281_0bb1fc08; +defparam bootram.RAM2.INIT_21=256'hf73d0d7b_3f00ff39_80085184_51e2e03f_b2b05281_3fdfd53f_d80ce0b7_9b3f72b9; +defparam bootram.RAM2.INIT_22=256'h55598074_81712b59_1908ff05_81881884_2e80d938_545a7780_c811085a_b2b40882; +defparam bootram.RAM2.INIT_23=256'hb5387816_5372802e_19087706_56568180_78118805_3873822b_807424b5_2480e938; +defparam bootram.RAM2.INIT_24=256'h38770858_738025d6_5a575754_1779812c_14fc17fc_53722dff_79517408_70085353; +defparam bootram.RAM2.INIT_25=256'h1779812c_14fc17fc_53722dff_993f7408_387951f5_bc1308a5_b2b40853_77ffad38; +defparam bootram.RAM2.INIT_26=256'hed3fff3d_2d7951f4_13085372_397251bc_8057ff94_a938d239_738025ff_5a575754; +defparam bootram.RAM2.INIT_27=256'h06f13883_ff2e0981_08525270_2dfc1270_2e913870_525270ff_fc057008_0db9b80b; +defparam bootram.RAM2.INIT_28=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040_dfbe3f04_3d0d0404; +defparam bootram.RAM2.INIT_29=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265; +defparam bootram.RAM2.INIT_2A=256'h70657220_72207375_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00; +defparam bootram.RAM2.INIT_2B=256'h20555352_74696e67_53746172_6e0a0000_6974696f_55206564_61205a50_756c7472; +defparam bootram.RAM2.INIT_2C=256'h65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20; +defparam bootram.RAM2.INIT_2D=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; +defparam bootram.RAM2.INIT_2E=256'h66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068_206e6576; +defparam bootram.RAM2.INIT_2F=256'h6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520_69726d77; +defparam bootram.RAM2.INIT_30=256'h5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963; +defparam bootram.RAM2.INIT_31=256'h726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000_2052414d; +defparam bootram.RAM2.INIT_32=256'h6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f; +defparam bootram.RAM2.INIT_33=256'h7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e; +defparam bootram.RAM2.INIT_34=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f; +defparam bootram.RAM2.INIT_35=256'h20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741; +defparam bootram.RAM2.INIT_36=256'h56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164; +defparam bootram.RAM2.INIT_37=256'h204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563_64207072; +defparam bootram.RAM2.INIT_38=256'h61727469_2e205374_64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67; +defparam bootram.RAM2.INIT_39=256'h6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000_6d616765_6e672069; +defparam bootram.RAM2.INIT_3A=256'h65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20; +defparam bootram.RAM2.INIT_3B=256'h6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065; +defparam bootram.RAM2.INIT_3C=256'h77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265; +defparam bootram.RAM2.INIT_3D=256'h80700000_0b0b0b0b_25640a00_25643a20_01b200d9_05160364_14580a2c_2e2e2e00; +defparam bootram.RAM2.INIT_3E=256'h20202828_20202020_00202020_00000000_43444546_38394142_34353637_30313233; +defparam bootram.RAM2.INIT_3F=256'h10101010_10101010_20881010_20202020_20202020_20202020_20202020_28282820; +defparam bootram.RAM3.INIT_00=256'h01010101_41414141_10104141_10101010_04040410_04040404_10040404_10101010; +defparam bootram.RAM3.INIT_01=256'h02020202_42424242_10104242_10101010_01010101_01010101_01010101_01010101; +defparam bootram.RAM3.INIT_02=256'h00000000_00000000_20000000_10101010_02020202_02020202_02020202_02020202; +defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_06=256'h792e6578_64756d6d_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_07=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000; +defparam bootram.RAM3.INIT_08=256'hffffffff_000b0000_0018000f_ffff0031_05050400_01010100_00001cc0_00000000; +defparam bootram.RAM3.INIT_09=256'h00001ba0_00000000_00001938_000018d8_06820594_09c407d0_13880d05_00002710; +defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001c58_00001bfc; +defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_000018e4_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001; +defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_25=256'hffffffff_00000000_ffffffff_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2B=256'h28282020_20282828_20202020_20202020_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2C=256'h10101010_10101010_10101010_88101010_20202020_20202020_20202020_20202020; -defparam bootram.RAM3.INIT_2D=256'h01010101_01010101_41414101_10414141_10101010_04041010_04040404_04040404; -defparam bootram.RAM3.INIT_2E=256'h02020202_02020202_42424202_10424242_10101010_01010110_01010101_01010101; -defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_10101020_02020210_02020202_02020202; -defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_33=256'h01010100_00001948_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001d70_ffffffff; diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 72dee909b..1969883d7 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -131,7 +131,7 @@ module u2plus_core output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi ); - localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_BUF_POOL = 64; // router localparam SR_UDP_SM = 96; // 64 regs localparam SR_RX_DSP = 160; // 16 localparam SR_RX_CTRL = 176; // 16 @@ -197,21 +197,21 @@ module u2plus_core wb_1master #(.decode_w(8), .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM - .s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool - .s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI - .s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C - .s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO - .s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback - .s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC - .s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K) - .s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC - .s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused - .sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART - .sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR - .sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused - .sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP - .se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash - .sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // 16K-20K, Buffer Pool + .s2_addr(8'b0110_0000),.s2_mask(8'b1111_1111), // SPI + .s3_addr(8'b0110_0001),.s3_mask(8'b1111_1111), // I2C + .s4_addr(8'b0110_0010),.s4_mask(8'b1111_1111), // GPIO + .s5_addr(8'b0110_0011),.s5_mask(8'b1111_1111), // Readback + .s6_addr(8'b0110_0100),.s6_mask(8'b1111_1111), // Ethernet MAC + .s7_addr(8'b0101_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b0110_0101),.s8_mask(8'b1111_1111), // PIC + .s9_addr(8'b0110_0110),.s9_mask(8'b1111_1111), // Unused + .sa_addr(8'b0110_0111),.sa_mask(8'b1111_1111), // UART + .sb_addr(8'b0110_1000),.sb_mask(8'b1111_1111), // ATR + .sc_addr(8'b0110_1001),.sc_mask(8'b1111_1111), // Unused + .sd_addr(8'b0110_1010),.sd_mask(8'b1111_1111), // ICAP + .se_addr(8'b0110_1011),.se_mask(8'b1111_1111), // SPI Flash + .sf_addr(8'b1000_0000),.sf_mask(8'b1100_0000), // 32-48K, Main RAM .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), @@ -251,33 +251,58 @@ module u2plus_core ////////////////////////////////////////////////////////////////////////////////////////// // Reset Controller - + + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + reg cpu_rst; + wire cpu_enb = ~cpu_rst; + wire [aw-1:0] cpu_adr; + wire [aw-1:0] cpu_sp_init = (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)? + 16'h3ff8 /*16K main ram*/: 16'h1ff8 /*8K boot ram*/; + + //When the main program runs, it will try to access system ram at 0. + //This logic sets the upper bit high to force select the system ram. + assign m0_adr = ((cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE) && + (cpu_adr[15:14] == 2'b00))? {2'b10, cpu_adr[13:0]} : cpu_adr; + + always @(posedge wb_clk) + if(wb_rst) begin + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; + cpu_rst <= 1'b0; + end + else begin + case(cpu_bldr_ctrl_state) + + CPU_BLDR_CTRL_WAIT: begin + if (bldr_done == 1'b1) begin //set by the bootloader + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; + cpu_rst <= 1'b1; + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + cpu_rst <= 1'b0; + end + + endcase //cpu_bldr_ctrl_state + end + // ///////////////////////////////////////////////////////////////////////// // Processor -// wire [31:0] if_dat; -// wire [15:0] if_adr; - -// aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) -// aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), -// // Instruction Wishbone bus to I-RAM -// .if_adr(if_adr), -// .if_dat(if_dat), -// // Data Wishbone bus to system bus fabric -// .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), -// .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), -// // Interrupts and exceptions -// .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - -// assign bus_error = m0_err | m0_rty; + + assign bus_error = m0_err | m0_rty; wire [63:0] zpu_status; zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), + zpu_top0 (.clk(wb_clk), .rst(wb_rst | cpu_rst), .enb(cpu_enb), // Data Wishbone bus to system bus fabric - .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + .stack_start(cpu_sp_init), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// @@ -476,6 +501,8 @@ module u2plus_core .in(set_data),.out(adc_outs),.changed()); setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phy_reset),.changed()); + setting_reg #(.my_addr(5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(bldr_done),.changed()); // ///////////////////////////////////////////////////////////////////////// // LEDS @@ -694,8 +721,17 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; // debug_extfifo; + //assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + //assign debug = 32'd0; // debug_extfifo; + assign debug_clk = {wb_rst, wb_clk}; + assign debug = { + cpu_adr, //16 bits + cpu_bldr_ctrl_state, //1 bits + bldr_done, //1 bit + cpu_rst, cpu_enb, // 2 bits + m0_we, m0_stb, m0_ack, m0_cyc, //4 + button, 7'b0 + }; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; -- cgit v1.2.3 From 97eebac5c5d1b43ad7620f3038ab022ab131431d Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 18 Dec 2010 00:09:41 -0800 Subject: usrp-n210: delay reset for boot loader stack pointer to init, copied bl.rmi without debug --- usrp2/top/u2plus/bootloader.rmi | 357 +++++++++++++++++++--------------------- usrp2/top/u2plus/u2plus_core.v | 3 +- 2 files changed, 173 insertions(+), 187 deletions(-) diff --git a/usrp2/top/u2plus/bootloader.rmi b/usrp2/top/u2plus/bootloader.rmi index 0916adaf7..4c7d918c0 100644 --- a/usrp2/top/u2plus/bootloader.rmi +++ b/usrp2/top/u2plus/bootloader.rmi @@ -1,5 +1,5 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a7fc0400_3a0b0b0b_0bb1fc0c_80700b0b_0b0b0b0b; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba8b92d_88080b0b_80088408; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4b70400_3a0b0b0b_0bae9c0c_80700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4f42d_88080b0b_80088408; defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; @@ -18,214 +18,199 @@ defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_ defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; -defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_e8738306_0b0b0bb1_71fc0608; -defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_f32d5050_0b0b0ba1_88087575_80088408; -defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_a52d5050_0b0b0ba3_88087575_80088408; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_88738306_0b0b0bae_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ae2d5050_0b0b0b9e_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_e02d5050_0b0b0b9f_88087575_80088408; defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; -defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bb1f80c_810b0b0b; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae980c_810b0b0b; defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; -defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d93f0410_81f33fa1; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_943f0410_81f33f9e; defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; -defparam bootram.RAM0.INIT_22=256'h535104b1_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; -defparam bootram.RAM0.INIT_23=256'hcc0c8290_a0800bb9_b9c80c82_0b0b0b0b_38838080_08822eb9_a138b1fc_f808802e; -defparam bootram.RAM0.INIT_24=256'h80808480_b9cc0cf8_8082800b_c80cf880_0b0b0bb9_8080a40b_0c04f880_800bb9d0; -defparam bootram.RAM0.INIT_25=256'h0baa880b_cc0c0b0b_80940bb9_0c80c0a8_0b0bb9c8_808c0b0b_0480c0a8_0bb9d00c; -defparam bootram.RAM0.INIT_26=256'hb2840c70_92388412_5270802e_08700852_a338b284_d4335170_ff3d0db9_b9d00c04; -defparam bootram.RAM0.INIT_27=256'hc408802e_0b0b0bb9_04803d0d_833d0d04_0bb9d434_70f03881_70085252_2db28408; -defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb9c4_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; -defparam bootram.RAM0.INIT_29=256'h518bdc3f_d0055273_3fb23dfe_525486b3_59923d70_3dfee005_d03d0db2_3d0d0404; -defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_8e3faa8c_5273519c_38765378_ff74278f_775481ff_8008b238; -defparam bootram.RAM0.INIT_2B=256'hb039803d_85b13fff_39aac451_aa905184_3f91f53f_8c5185bf_068f38aa_812e0981; +defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; +defparam bootram.RAM0.INIT_23=256'hec0c8290_a0800bb5_b5e80c82_0b0b0b0b_38838080_08822eb9_a138ae9c_9808802e; +defparam bootram.RAM0.INIT_24=256'h80808480_b5ec0cf8_8082800b_e80cf880_0b0b0bb5_8080a40b_0c04f880_800bb5f0; +defparam bootram.RAM0.INIT_25=256'h0ba6c40b_ec0c0b0b_80940bb5_0c80c0a8_0b0bb5e8_808c0b0b_0480c0a8_0bb5f00c; +defparam bootram.RAM0.INIT_26=256'haea40c70_92388412_5270802e_08700852_a338aea4_f4335170_ff3d0db5_b5f00c04; +defparam bootram.RAM0.INIT_27=256'he408802e_0b0b0bb5_04803d0d_833d0d04_0bb5f434_70f03881_70085252_2daea408; +defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5e4_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; +defparam bootram.RAM0.INIT_29=256'h518bc93f_d0055273_3fb23dfe_525486a0_59923d70_3dfee005_d03d0db2_3d0d0404; +defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_c93fa6c8_52735198_38765378_ff74278f_775481ff_8008b238; +defparam bootram.RAM0.INIT_2B=256'hb039803d_859e3fff_39a78051_a6cc5184_3f91d73f_c85185ac_068f38a6_812e0981; defparam bootram.RAM0.INIT_2C=256'h0ca78851_0b81a08c_3d0d81ff_3d0d04fc_51f63982_380bff11_70ff2e87_0dff1351; -defparam bootram.RAM0.INIT_2D=256'h81ff0655_ee3f8008_84f53f83_3faac851_f43f86e9_85f43f8e_81a08c0c_dd3f800b; -defparam bootram.RAM0.INIT_2E=256'h81fc8080_5184d03f_c338aaf4_51547380_70810651_08708d2a_3f81c6b4_805182ed; -defparam bootram.RAM0.INIT_2F=256'h8ebe3f90_fc808051_ffff5281_80805380_82c33f82_a6388151_8008802e_5190d43f; -defparam bootram.RAM0.INIT_30=256'ha851848b_74b238ac_3ffe8d3f_d0518497_3f8a39ab_735191b0_5184a43f_e33fab94; -defparam bootram.RAM0.INIT_31=256'hfec03fb0_3f82ac51_815181f9_5183f83f_9938acd4_8008802e_518fbf3f_3fb0800a; -defparam bootram.RAM0.INIT_32=256'h83cd3f82_38addc51_08802eaa_8fe53f80_98800a51_5183e03f_f73fad8c_800a5190; -defparam bootram.RAM0.INIT_33=256'h3faeac51_853f8fe8_82ac51fe_5183b83f_cf3fae88_800a518d_ffff5298_80805380; -defparam bootram.RAM0.INIT_34=256'h5380ffff_38828080_08802eb5_80085480_518fa83f_81fc8080_5183a43f_ba39aee8; -defparam bootram.RAM0.INIT_35=256'hee3f82ac_ab945182_3f8fad3f_ac51fdca_82fd3f82_3fae8851_80518d94_5281fc80; -defparam bootram.RAM0.INIT_36=256'h04f83d0d_0c863d0d_cf3f7380_82d93ffc_39abd051_3f81548a_80518ff4_51fdbb3f; +defparam bootram.RAM0.INIT_2D=256'h81ff0655_ee3f8008_84e23f83_3fa78451_e13f86d6_85e13f8e_81a08c0c_dd3f800b; +defparam bootram.RAM0.INIT_2E=256'h81fc8080_5184bd3f_c338a7b0_51547380_70810651_08708d2a_3f81c6b4_805182ed; +defparam bootram.RAM0.INIT_2F=256'h8eab3f90_fc808051_ffff5281_80805380_82c33f82_a6388151_8008802e_5190b63f; +defparam bootram.RAM0.INIT_30=256'he45183f8_74b238a8_3ffe8d3f_8c518484_3f8a39a8_73519192_5184913f_c53fa7d0; +defparam bootram.RAM0.INIT_31=256'hfec03fb0_3f82ac51_815181f9_5183e53f_9938a990_8008802e_518fa13f_3fb0800a; +defparam bootram.RAM0.INIT_32=256'h83ba3f82_38aa9851_08802eaa_8fc73f80_98800a51_5183cd3f_d93fa9c8_800a5190; +defparam bootram.RAM0.INIT_33=256'h3faae851_853f8fca_82ac51fe_5183a53f_bc3faac4_800a518d_ffff5298_80805380; +defparam bootram.RAM0.INIT_34=256'h5380ffff_38828080_08802eb5_80085480_518f8a3f_81fc8080_5183913f_ba39aba4; +defparam bootram.RAM0.INIT_35=256'hdb3f82ac_a7d05182_3f8f8f3f_ac51fdca_82ea3f82_3faac451_80518d81_5281fc80; +defparam bootram.RAM0.INIT_36=256'h04f83d0d_0c863d0d_cf3f7380_82c63ffc_39a88c51_3f81548a_80518fd6_51fdbb3f; defparam bootram.RAM0.INIT_37=256'h70810558_8a3d3476_17575473_b7387581_54807425_74ff1656_5a575758_7a7c7f7f; -defparam bootram.RAM0.INIT_38=256'h8a518790_81ff0654_e23f8008_ff065185_05527781_538a3dfc_a1053482_33028405; +defparam bootram.RAM0.INIT_38=256'h8a5186fd_81ff0654_cf3f8008_ff065185_05527781_538a3dfc_a1053482_33028405; defparam bootram.RAM0.INIT_39=256'h748338dc_5580de56_02a30533_04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e; defparam bootram.RAM0.INIT_3A=256'h7c5702ab_04f93d0d_3f883d0d_d051ff89_81f75280_3dfc0553_34815488_5675883d; -defparam bootram.RAM0.INIT_3B=256'h56547380_81ff0670_823f8008_70525685_02a70533_3dfc0552_34815389_0533893d; -defparam bootram.RAM0.INIT_3C=256'h83388155_5473802e_ff067056_3f800881_755183c5_76537b52_77259738_2e9e3880; +defparam bootram.RAM0.INIT_3B=256'h56547380_81ff0670_ef3f8008_70525684_02a70533_3dfc0552_34815389_0533893d; +defparam bootram.RAM0.INIT_3C=256'h83388155_5473802e_ff067056_3f800881_755183b2_76537b52_77259738_2e9e3880; defparam bootram.RAM0.INIT_3D=256'h883d3356_a03f800b_80d051ff_5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89; -defparam bootram.RAM0.INIT_3E=256'h81e33f72_53538051_3d0d7470_3d0d04fe_75800c88_83388156_2e098106_567480de; -defparam bootram.RAM0.INIT_3F=256'h7481ff06_90388115_5472802e_81ff0654_56743370_0d777956_0d04fb3d_800c843d; -defparam bootram.RAM1.INIT_00=256'h8a527251_5253cb3f_74765370_04fe3d0d_0c873d0d_39800b80_81bb3fe5_53765255; -defparam bootram.RAM1.INIT_01=256'h78705555_fc3d0d76_833d0d04_8051de3f_3d0d7352_3d0d04ff_0b800c84_819f3f80; -defparam bootram.RAM1.INIT_02=256'h38807334_098106e7_52718a2e_0881ff06_08733480_81b23f80_13537451_55843981; -defparam bootram.RAM1.INIT_03=256'h33b28812_51028f05_803d0d72_833d0d04_8051c93f_3d0d7352_3d0d04ff_73800c86; -defparam bootram.RAM1.INIT_04=256'h0d04fe3d_5351833d_7022720c_10afa405_ce800575_73a02981_04ff3d0d_34823d0d; -defparam bootram.RAM1.INIT_05=256'h38843d0d_827325e7_3f811353_527251d1_b28c1333_7251c93f_88133352_0d8053b2; -defparam bootram.RAM1.INIT_06=256'h388d5273_09810687_5372812e_b2881433_81069438_748a2e09_76785654_04fc3d0d; -defparam bootram.RAM1.INIT_07=256'hff3d0d73_863d0d04_748c150c_802ef838_14085372_80055484_a02981ce_51df3f73; -defparam bootram.RAM1.INIT_08=256'h800b81c2_04ff3d0d_0c833d0d_90120880_802ef838_12085170_80055288_a02981ce; -defparam bootram.RAM1.INIT_09=256'h0681c280_227081ff_b2900570_84517010_71258338_06515184_a408708f_880c81c6; -defparam bootram.RAM1.INIT_0A=256'h05970533_76780288_04fd3d0d_0c833d0d_0b81c288_51518180_81c2840c_0c70882a; -defparam bootram.RAM1.INIT_0B=256'h10810781_70f13872_06515151_862a7081_c2900870_81863881_5171802e_55535481; -defparam bootram.RAM1.INIT_0C=256'h90087087_f13881c2_51515170_2a708106_90087081_900c81c2_900b81c2_c28c0c81; -defparam bootram.RAM1.INIT_0D=256'h38a05170_71812e83_3880e851_71802eb1_802eba38_51515170_70813251_2a708106; -defparam bootram.RAM1.INIT_0E=256'h81055634_51707470_81c28c08_5170f138_81065151_70812a70_81c29008_81c2900c; -defparam bootram.RAM1.INIT_0F=256'h02880597_3d0d7678_3d0d04fd_70800c85_81c2900c_3980c00b_39815188_ff1252cc; -defparam bootram.RAM1.INIT_10=256'hd0517180_c28c0c81_38721081_515170f1_70810651_0870862a_5481c290_05335553; -defparam bootram.RAM1.INIT_11=256'hc2900870_70f13881_06515151_812a7081_c2900870_c2900c81_90517081_2e843881; -defparam bootram.RAM1.INIT_12=256'h8c0c80d0_733381c2_2e80c538_cf387180_70802e80_51515151_06708132_872a7081; -defparam bootram.RAM1.INIT_13=256'h3881c290_515170f1_70810651_0870812a_0c81c290_7081c290_83389051_5171812e; -defparam bootram.RAM1.INIT_14=256'h81518a39_54ffb739_14ff1353_2e8e3881_51517080_81325151_70810670_0870872a; -defparam bootram.RAM1.INIT_15=256'h24a638b2_52528071_81c6a408_ff3d0d73_853d0d04_5170800c_c2900c80_80c00b81; -defparam bootram.RAM1.INIT_16=256'h7151ff11_72258938_0c515180_1122b29c_8e06b2a0_a4087010_923881c6_9c088025; -defparam bootram.RAM1.INIT_17=256'h269638c9_527180da_ff065152_a9117081_8f0533ff_ff3d0d02_833d0d04_5170fb38; -defparam bootram.RAM1.INIT_18=256'h3d0d797b_3d0d04f9_70800c83_ff065151_d0127081_b9268938_06515171_127081ff; -defparam bootram.RAM1.INIT_19=256'haa387281_5371782e_81173353_ef38810b_09810682_5371ba2e_335358ff_58568076; -defparam bootram.RAM1.INIT_1A=256'hbd387216_71802e82_53515452_06515151_337080c4_33afd511_06721970_147081ff; -defparam bootram.RAM1.INIT_1B=256'h3f800881_5252feec_06821733_842b9ff0_fb3f8008_163351fe_71d83881_70335152; -defparam bootram.RAM1.INIT_1C=256'hcb3f8008_163351fe_828a3883_54fd5374_11335753_7010178b_7084190c_ff067205; -defparam bootram.RAM1.INIT_1D=256'h53fea93f_85173352_80067305_882b83fe_bb3f8008_335253fe_80068417_8c2bbfe0; -defparam bootram.RAM1.INIT_1E=256'h163351fe_88180c87_ff067305_3f800881_5253fe98_05861733_9ff00673_8008842b; -defparam bootram.RAM1.INIT_1F=256'hd2387410_74742780_52717734_3f800812_5252fdf8_06881733_842b9ff0_873f8008; -defparam bootram.RAM1.INIT_20=256'h842b9ff0_cf3f8008_565152fd_52335552_70708105_08177119_ff068c19_89057081; -defparam bootram.RAM1.INIT_21=256'h197081ff_81ff0681_33701a70_17081570_7274348c_80081353_53fdc13f_06723352; -defparam bootram.RAM1.INIT_22=256'h05547305_0571882a_08783372_17088818_ffb03884_17087526_51515284_065a525b; -defparam bootram.RAM1.INIT_23=256'h068a1533_842b9ff0_f33f8008_515354fc_3356545b_101a8911_81ff0673_19703070; -defparam bootram.RAM1.INIT_24=256'h83398053_8539fe53_81068938_77722e09_5152fb53_7081ff06_3f800812_5252fce4; -defparam bootram.RAM1.INIT_25=256'h0d04fe3d_f138823d_51515170_2a708106_90087088_3d0d81d6_3d0d0480_72800c89; -defparam bootram.RAM1.INIT_26=256'h81065151_70882a70_81d69008_80075353_060780c0_067a8c80_337880ff_0d029305; -defparam bootram.RAM1.INIT_27=256'h900c7251_800781d6_980c7182_ff0681d6_900c7581_0c7181d6_7681d680_5170f138; -defparam bootram.RAM1.INIT_28=256'h0c843d0d_08517080_3881d680_515170f1_70810651_0870882a_3881d690_72802e96; -defparam bootram.RAM1.INIT_29=256'hf33d0d60_863d0d04_51ff873f_53805280_55885480_940c8880_810b81d6_04fc3d0d; -defparam bootram.RAM1.INIT_2A=256'h800c810b_882b81d6_d6840c7f_0c8b0b81_0b81d690_980c8880_800b81d6_59fee43f; -defparam bootram.RAM1.INIT_2B=256'h80de3888_58777927_3f615780_900cfeb3_a80b81d6_d6900c8a_88a80b81_81d6980c; -defparam bootram.RAM1.INIT_2C=256'h84085d81_085c81d6_5b81d688_81d68c08_0cfe983f_0b81d690_900c8a80_800b81d6; -defparam bootram.RAM1.INIT_2D=256'h1a547333_279c3874_80557476_83387356_56737627_31555a90_8b3d7979_d680085e; -defparam bootram.RAM1.INIT_2E=256'h800b81d6_58ff9e39_e1397518_3f811555_b05183e3_741852af_59347653_77708105; -defparam bootram.RAM1.INIT_2F=256'h57557417_84059d05_c73f8002_526851fe_545780c0_0d883d70_0d04ea3d_980c8f3d; -defparam bootram.RAM1.INIT_30=256'h2e098106_54738199_16703351_06943874_aa2e0981_9d387381_7381ff2e_70335154; -defparam bootram.RAM1.INIT_31=256'h70545486_3d0d863d_3d0d04f9_73800c98_d1388054_55be7527_8b398115_85388154; -defparam bootram.RAM1.INIT_32=256'h5574800c_06833881_752e0981_9e3f8008_52735189_8653afb8_f73f8055_527951fd; -defparam bootram.RAM1.INIT_33=256'h832a8406_872a0771_2a820671_05337085_3d0d0297_940c04fd_810b81a0_893d0d04; -defparam bootram.RAM1.INIT_34=256'h2b80c006_ff067685_07077081_a0067173_0674832b_07731090_06717307_72812a88; -defparam bootram.RAM1.INIT_35=256'hfe3d0d74_853d0d04_52555552_52535155_d4800c51_81ff0681_872b0770_70720778; -defparam bootram.RAM1.INIT_36=256'h51ff8c3f_923f8199_81aa51ff_51ff983f_9e3f81ff_81ff51ff_d00a0753_d00a0681; -defparam bootram.RAM1.INIT_37=256'hfeed3fb2_81ff0651_fef53f72_ff065252_882a7081_ff813f72_3f80e151_b251ff87; -defparam bootram.RAM1.INIT_38=256'h3fb051fe_5253fecf_7081ff06_3f72902a_2a51fedb_e23f7298_818151fe_51fee83f; -defparam bootram.RAM1.INIT_39=256'ha051feab_51feb03f_feb53f80_ba3fa051_3f8e51fe_8051febf_51fec43f_ca3f81a1; -defparam bootram.RAM1.INIT_3A=256'h9f2a515b_33703070_9005bb05_7e616302_f63d0d7c_0d04ff39_a63f843d_3f8051fe; -defparam bootram.RAM1.INIT_3B=256'h38795578_77772694_2d763057_52ad5178_2e8a3879_8f387580_57768025_5f5d5b59; -defparam bootram.RAM1.INIT_3C=256'h3351782d_08afc005_82b83f80_77527651_51ffbd3f_a03f8008_52765182_54805377; -defparam bootram.RAM1.INIT_3D=256'h52089fa4_70708405_3d0d8c3d_3d0d04f7_f0a53f82_8b053351_803d0d02_8c3d0d04; -defparam bootram.RAM1.INIT_3E=256'h80db3881_2e098106_065675a5_387681ff_802e81d1_06575775_337081ff_5c5a5878; -defparam bootram.RAM1.INIT_3F=256'h8a387580_7580e324_e32eb938_a0387580_7580f024_2e80fb38_597580f0_19703357; -defparam bootram.RAM2.INIT_00=256'h387580f3_80f5248b_2eac3875_397580f5_c638818b_80e42e80_81953975_2e819e38; -defparam bootram.RAM2.INIT_01=256'h51792d80_56805275_12335259_77841983_3880ec39_80f82eba_80f53975_2e80db38; -defparam bootram.RAM2.INIT_02=256'h559fa454_52595680_84197108_53903977_9fa45480_59568055_19710852_da397784; -defparam bootram.RAM2.INIT_03=256'h9e397784_51fdd13f_53905275_9fa45480_59568055_19710852_92397784_81538a52; -defparam bootram.RAM2.INIT_04=256'h1959fea3_2dec3981_58335179_76708105_8e388052_5675802e_59567633_19710859; -defparam bootram.RAM2.INIT_05=256'h05085182_528c0888_088c0508_0d80538c_8c0cfd3d_048c0802_0c8b3d0d_39800b80; -defparam bootram.RAM2.INIT_06=256'h08528c08_8c088c05_3d0d8153_028c0cfd_0c048c08_853d0d8c_70800c54_de3f8008; -defparam bootram.RAM2.INIT_07=256'h0b8c08fc_f93d0d80_08028c0c_8c0c048c_54853d0d_0870800c_82b93f80_88050851; -defparam bootram.RAM2.INIT_08=256'h0c8c08fc_8c08f405_050c800b_308c0888_08880508_25ab388c_88050880_050c8c08; -defparam bootram.RAM2.INIT_09=256'hab388c08_05088025_0c8c088c_8c08fc05_08f40508_f4050c8c_810b8c08_05088838; -defparam bootram.RAM2.INIT_0A=256'h050c8c08_0b8c08f0_08883881_8c08fc05_08f0050c_0c800b8c_8c088c05_8c050830; -defparam bootram.RAM2.INIT_0B=256'h8c08f805_3f800870_085181a7_8c088805_8c050852_80538c08_08fc050c_f005088c; -defparam bootram.RAM2.INIT_0C=256'h800c5489_f8050870_050c8c08_308c08f8_08f80508_2e8c388c_fc050880_0c548c08; -defparam bootram.RAM2.INIT_0D=256'h388c0888_08802593_8c088805_08fc050c_0d800b8c_8c0cfb3d_048c0802_3d0d8c0c; -defparam bootram.RAM2.INIT_0E=256'h08308c08_8c088c05_80258c38_088c0508_fc050c8c_810b8c08_0888050c_0508308c; -defparam bootram.RAM2.INIT_0F=256'h8c08fc05_f8050c54_08708c08_51ad3f80_08880508_0508528c_538c088c_8c050c81; -defparam bootram.RAM2.INIT_10=256'h8c0c048c_54873d0d_0870800c_8c08f805_08f8050c_0508308c_388c08f8_08802e8c; -defparam bootram.RAM2.INIT_11=256'h88050827_05088c08_0c8c088c_8c08f805_050c800b_0b8c08fc_fd3d0d81_08028c0c; -defparam bootram.RAM2.INIT_12=256'h088c050c_0508108c_388c088c_05082499_0b8c088c_2ea33880_fc050880_ac388c08; -defparam bootram.RAM2.INIT_13=256'h8c088805_088c0508_80c9388c_0508802e_398c08fc_fc050cc9_08108c08_8c08fc05; -defparam bootram.RAM2.INIT_14=256'h0508078c_088c08fc_8c08f805_0888050c_0508318c_088c088c_8c088805_0826a138; -defparam bootram.RAM2.INIT_15=256'hffaf398c_088c050c_08812a8c_8c088c05_08fc050c_08812a8c_8c08fc05_08f8050c; -defparam bootram.RAM2.INIT_16=256'h8c08f405_f8050870_8d398c08_f4050c51_08708c08_8c088805_802e8f38_08900508; -defparam bootram.RAM2.INIT_17=256'h38747407_8372278c_79565652_3d0d7877_8c0c04fc_0c853d0d_f4050880_0c518c08; -defparam bootram.RAM2.INIT_18=256'hbd388115_2e098106_52537271_74337433_ff2ea038_ff125271_802eb038_83065170; -defparam bootram.RAM2.INIT_19=256'h0873082e_74545170_3d0d0474_0b800c86_06e23880_ff2e0981_54555571_8115ff14; -defparam bootram.RAM2.INIT_1A=256'h31800c86_af397271_735555ff_26e93870_54517183_14fc1454_38841184_0981068f; -defparam bootram.RAM2.INIT_1B=256'ha738ff12_5170802e_75078306_278c3872_55558f72_797b5555_3d0d7670_3d0d04fc; -defparam bootram.RAM2.INIT_1C=256'h3874800c_098106ea_5271ff2e_5634ff12_74708105_81055433_98387270_5271ff2e; -defparam bootram.RAM2.INIT_1D=256'h530c7270_71708405_84055408_530c7270_71708405_84055408_74517270_863d0d04; -defparam bootram.RAM2.INIT_1E=256'hc9388372_52718f26_530cf012_71708405_84055408_530c7270_71708405_84055408; -defparam bootram.RAM2.INIT_1F=256'hfd3d0d80_54ff8339_26ed3870_12527183_05530cfc_08717084_70840554_27953872; -defparam bootram.RAM2.INIT_20=256'h3f800851_8151e2f7_3fb2b052_ce3fdfec_b9d80ce0_2e983873_54547281_0bb1fc08; -defparam bootram.RAM2.INIT_21=256'hf73d0d7b_3f00ff39_80085184_51e2e03f_b2b05281_3fdfd53f_d80ce0b7_9b3f72b9; -defparam bootram.RAM2.INIT_22=256'h55598074_81712b59_1908ff05_81881884_2e80d938_545a7780_c811085a_b2b40882; -defparam bootram.RAM2.INIT_23=256'hb5387816_5372802e_19087706_56568180_78118805_3873822b_807424b5_2480e938; -defparam bootram.RAM2.INIT_24=256'h38770858_738025d6_5a575754_1779812c_14fc17fc_53722dff_79517408_70085353; -defparam bootram.RAM2.INIT_25=256'h1779812c_14fc17fc_53722dff_993f7408_387951f5_bc1308a5_b2b40853_77ffad38; -defparam bootram.RAM2.INIT_26=256'hed3fff3d_2d7951f4_13085372_397251bc_8057ff94_a938d239_738025ff_5a575754; -defparam bootram.RAM2.INIT_27=256'h06f13883_ff2e0981_08525270_2dfc1270_2e913870_525270ff_fc057008_0db9b80b; -defparam bootram.RAM2.INIT_28=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040_dfbe3f04_3d0d0404; -defparam bootram.RAM2.INIT_29=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265; -defparam bootram.RAM2.INIT_2A=256'h70657220_72207375_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00; -defparam bootram.RAM2.INIT_2B=256'h20555352_74696e67_53746172_6e0a0000_6974696f_55206564_61205a50_756c7472; -defparam bootram.RAM2.INIT_2C=256'h65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20; -defparam bootram.RAM2.INIT_2D=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; -defparam bootram.RAM2.INIT_2E=256'h66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068_206e6576; -defparam bootram.RAM2.INIT_2F=256'h6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520_69726d77; -defparam bootram.RAM2.INIT_30=256'h5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963; -defparam bootram.RAM2.INIT_31=256'h726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000_2052414d; -defparam bootram.RAM2.INIT_32=256'h6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f; -defparam bootram.RAM2.INIT_33=256'h7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e; -defparam bootram.RAM2.INIT_34=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f; -defparam bootram.RAM2.INIT_35=256'h20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741; -defparam bootram.RAM2.INIT_36=256'h56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164; -defparam bootram.RAM2.INIT_37=256'h204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563_64207072; -defparam bootram.RAM2.INIT_38=256'h61727469_2e205374_64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67; -defparam bootram.RAM2.INIT_39=256'h6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000_6d616765_6e672069; -defparam bootram.RAM2.INIT_3A=256'h65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20; -defparam bootram.RAM2.INIT_3B=256'h6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065; -defparam bootram.RAM2.INIT_3C=256'h77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265; -defparam bootram.RAM2.INIT_3D=256'h80700000_0b0b0b0b_25640a00_25643a20_01b200d9_05160364_14580a2c_2e2e2e00; -defparam bootram.RAM2.INIT_3E=256'h20202828_20202020_00202020_00000000_43444546_38394142_34353637_30313233; -defparam bootram.RAM2.INIT_3F=256'h10101010_10101010_20881010_20202020_20202020_20202020_20202020_28282820; -defparam bootram.RAM3.INIT_00=256'h01010101_41414141_10104141_10101010_04040410_04040404_10040404_10101010; -defparam bootram.RAM3.INIT_01=256'h02020202_42424242_10104242_10101010_01010101_01010101_01010101_01010101; -defparam bootram.RAM3.INIT_02=256'h00000000_00000000_20000000_10101010_02020202_02020202_02020202_02020202; +defparam bootram.RAM0.INIT_3E=256'h7081ff06_56567433_3d0d7779_3d0d04fb_75800c88_83388156_2e098106_567480de; +defparam bootram.RAM0.INIT_3F=256'h0d04fe3d_800c873d_e539800b_5581bb3f_06537652_157481ff_2e903881_54547280; +defparam bootram.RAM1.INIT_00=256'h528051de_ff3d0d73_843d0d04_800b800c_51819f3f_3f8a5272_705253cb_0d747653; +defparam bootram.RAM1.INIT_01=256'h800881ff_80087334_5181b23f_81135374_55558439_76787055_04fc3d0d_3f833d0d; +defparam bootram.RAM1.INIT_02=256'h3f833d0d_528051c9_ff3d0d73_863d0d04_3473800c_e7388073_2e098106_0652718a; +defparam bootram.RAM1.INIT_03=256'h7510abe0_81ce8005_0d73a029_0d04ff3d_1234823d_0533aea8_7251028f_04803d0d; +defparam bootram.RAM1.INIT_04=256'h33527251_3faeac13_527251c9_aea81333_3d0d8053_3d0d04fe_0c535183_05702272; +defparam bootram.RAM1.INIT_05=256'h38aea814_09810694_54748a2e_0d767856_0d04fc3d_e738843d_53827325_d13f8113; +defparam bootram.RAM1.INIT_06=256'h72802ef8_84140853_ce800554_73a02981_7351df3f_87388d52_2e098106_33537281; +defparam bootram.RAM1.INIT_07=256'h38901208_70802ef8_88120851_ce800552_73a02981_04ff3d0d_0c863d0d_38748c15; +defparam bootram.RAM1.INIT_08=256'h38845170_84712583_8f065151_c6a40870_c2880c81_0d800b81_0d04ff3d_800c833d; +defparam bootram.RAM1.INIT_09=256'h880c833d_800b81c2_0c515181_2a81c284_800c7088_ff0681c2_70227081_10aeb005; +defparam bootram.RAM1.INIT_0A=256'h70862a70_81c29008_2e818638_81517180_33555354_88059705_0d767802_0d04fd3d; +defparam bootram.RAM1.INIT_0B=256'h812a7081_c2900870_c2900c81_81900b81_81c28c0c_72108107_5170f138_81065151; +defparam bootram.RAM1.INIT_0C=256'h3871802e_70802eba_51515151_06708132_872a7081_c2900870_70f13881_06515151; +defparam bootram.RAM1.INIT_0D=256'h515170f1_70810651_0870812a_0c81c290_7081c290_8338a051_5171812e_b13880e8; +defparam bootram.RAM1.INIT_0E=256'h0c70800c_0b81c290_883980c0_cc398151_34ff1252_70810556_08517074_3881c28c; +defparam bootram.RAM1.INIT_0F=256'h51515170_2a708106_90087086_535481c2_97053355_78028805_fd3d0d76_853d0d04; +defparam bootram.RAM1.INIT_10=256'h70812a70_81c29008_81c2900c_81905170_802e8438_81d05171_81c28c0c_f1387210; +defparam bootram.RAM1.INIT_11=256'h80cf3871_5170802e_32515151_81067081_70872a70_81c29008_5170f138_81065151; +defparam bootram.RAM1.INIT_12=256'h90087081_900c81c2_517081c2_2e833890_d0517181_c28c0c80_38733381_802e80c5; +defparam bootram.RAM1.INIT_13=256'h802e8e38_51515170_70813251_2a708106_90087087_f13881c2_51515170_2a708106; +defparam bootram.RAM1.INIT_14=256'h04ff3d0d_0c853d0d_80517080_81c2900c_3980c00b_3981518a_5354ffb7_8114ff13; +defparam bootram.RAM1.INIT_15=256'hc01122ae_108e06ae_c6a40870_25923881_aebc0880_7124a638_08525280_7381c6a4; +defparam bootram.RAM1.INIT_16=256'hffa91170_028f0533_04ff3d0d_38833d0d_115170fb_387151ff_80722589_bc0c5151; +defparam bootram.RAM1.INIT_17=256'h81ff0651_38d01270_71b92689_ff065151_c9127081_da269638_52527180_81ff0651; +defparam bootram.RAM1.INIT_18=256'h82ef3881_2e098106_ff5371ba_76335358_7b585680_f93d0d79_833d0d04_5170800c; +defparam bootram.RAM1.INIT_19=256'hc4065151_11337080_7033abf5_ff067219_81147081_2eaa3872_53537178_0b811733; +defparam bootram.RAM1.INIT_1A=256'h08842b9f_fefb3f80_81163351_5271d838_16703351_82bd3872_5271802e_51535154; +defparam bootram.RAM1.INIT_1B=256'h5354fd53_8b113357_0c701017_05708419_81ff0672_ec3f8008_335252fe_f0068217; +defparam bootram.RAM1.INIT_1C=256'h08882b83_febb3f80_17335253_e0800684_088c2bbf_fecb3f80_83163351_74828a38; +defparam bootram.RAM1.INIT_1D=256'h983f8008_335253fe_73058617_2b9ff006_3f800884_5253fea9_05851733_fe800673; +defparam bootram.RAM1.INIT_1E=256'hf83f8008_335252fd_f0068817_08842b9f_fe873f80_87163351_0588180c_81ff0673; +defparam bootram.RAM1.INIT_1F=256'h05523355_19707081_19081771_81ff068c_10890570_80d23874_34747427_12527177; +defparam bootram.RAM1.INIT_20=256'h8c170815_53727434_3f800813_5253fdc1_f0067233_08842b9f_fdcf3f80_52565152; +defparam bootram.RAM1.INIT_21=256'h84170888_26ffb038_84170875_5b515152_ff065a52_81197081_7081ff06_7033701a; +defparam bootram.RAM1.INIT_22=256'h5b515354_11335654_73101a89_7081ff06_05197030_2a055473_72057188_18087833; +defparam bootram.RAM1.INIT_23=256'h5377722e_065152fb_127081ff_e43f8008_335252fc_f0068a15_08842b9f_fcf33f80; +defparam bootram.RAM1.INIT_24=256'h882a7081_d6900870_803d0d81_893d0d04_5372800c_53833980_388539fe_09810689; +defparam bootram.RAM1.INIT_25=256'hc0800753_80060780_ff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151; +defparam bootram.RAM1.INIT_26=256'h81ff0681_d6900c75_800c7181_387681d6_515170f1_70810651_0870882a_5381d690; +defparam bootram.RAM1.INIT_27=256'h51515170_2a708106_90087088_963881d6_5172802e_d6900c72_82800781_d6980c71; +defparam bootram.RAM1.INIT_28=256'h80538052_80558854_d6940c88_0d810b81_0d04fc3d_800c843d_80085170_f13881d6; +defparam bootram.RAM1.INIT_29=256'h900c8b0b_800b81d6_d6980c88_3f800b81_7d56fee4_04f63d0d_3f863d0d_8051ff87; +defparam bootram.RAM1.INIT_2A=256'hd6900cfe_8aa80b81_81d6900c_0c88a80b_0b81d698_d6800c81_7c882b81_81d6840c; +defparam bootram.RAM1.INIT_2B=256'h3f81d68c_900cfe98_800b81d6_d6900c8a_88800b81_2780d338_80547376_b33f7e55; +defparam bootram.RAM1.INIT_2C=256'h27833870_90537073_75315257_5b883d76_81d68008_d684085a_88085981_085881d6; +defparam bootram.RAM1.INIT_2D=256'ha939800b_721454ff_1252ec39_05573481_33757081_71175170_73279138_53805271; +defparam bootram.RAM1.INIT_2E=256'h9d055755_80028405_51fed23f_80c05268_3d705457_ea3d0d88_8c3d0d04_81d6980c; +defparam bootram.RAM1.INIT_2F=256'h81992e09_33515473_38741670_09810694_7381aa2e_ff2e9d38_51547381_74177033; +defparam bootram.RAM1.INIT_30=256'h863d7054_04f93d0d_0c983d0d_80547380_7527d138_811555be_81548b39_81068538; +defparam bootram.RAM1.INIT_31=256'h38815574_09810683_8008752e_5185f73f_abec5273_80558653_51fe823f_54865279; +defparam bootram.RAM1.INIT_32=256'h0771832a_0671872a_70852a82_02970533_04fd3d0d_81a0940c_0d04810b_800c893d; +defparam bootram.RAM1.INIT_33=256'h76852b80_7081ff06_71730707_832ba006_10900674_73070773_2a880671_84067281; +defparam bootram.RAM1.INIT_34=256'h0d04fe3d_5552853d_51555255_0c515253_0681d480_077081ff_0778872b_c0067072; +defparam bootram.RAM1.INIT_35=256'h819951ff_51ff923f_983f81aa_81ff51ff_51ff9e3f_075381ff_0681d00a_0d74d00a; +defparam bootram.RAM1.INIT_36=256'h0651feed_3f7281ff_5252fef5_7081ff06_3f72882a_e151ff81_ff873f80_8c3fb251; +defparam bootram.RAM1.INIT_37=256'hfecf3fb0_ff065253_902a7081_fedb3f72_72982a51_51fee23f_e83f8181_3fb251fe; +defparam bootram.RAM1.INIT_38=256'hb03fa051_3f8051fe_a051feb5_51feba3f_febf3f8e_c43f8051_81a151fe_51feca3f; +defparam bootram.RAM1.INIT_39=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_ff398c08_843d0d04_51fea63f_feab3f80; +defparam bootram.RAM1.INIT_3A=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025; +defparam bootram.RAM1.INIT_3B=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4; +defparam bootram.RAM1.INIT_3C=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c; +defparam bootram.RAM1.INIT_3D=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80; +defparam bootram.RAM1.INIT_3E=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e; +defparam bootram.RAM1.INIT_3F=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c; +defparam bootram.RAM2.INIT_00=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81; +defparam bootram.RAM2.INIT_01=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05; +defparam bootram.RAM2.INIT_02=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; +defparam bootram.RAM2.INIT_03=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b; +defparam bootram.RAM2.INIT_04=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e; +defparam bootram.RAM2.INIT_05=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc; +defparam bootram.RAM2.INIT_06=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508; +defparam bootram.RAM2.INIT_07=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508; +defparam bootram.RAM2.INIT_08=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c; +defparam bootram.RAM2.INIT_09=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c; +defparam bootram.RAM2.INIT_0A=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff; +defparam bootram.RAM2.INIT_0B=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff; +defparam bootram.RAM2.INIT_0C=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414; +defparam bootram.RAM2.INIT_0D=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079; +defparam bootram.RAM2.INIT_0E=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081; +defparam bootram.RAM2.INIT_0F=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084; +defparam bootram.RAM2.INIT_10=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553; +defparam bootram.RAM2.INIT_11=256'hae9c0854_3d0d800b_ff8339fd_ed387054_52718326_530cfc12_71708405_84055408; +defparam bootram.RAM2.INIT_12=256'h3f72b5f8_8008519b_51e6bc3f_aed05281_3fe3b13f_f80ce493_983873b5_5472812e; +defparam bootram.RAM2.INIT_13=256'hd40882c8_3d0d7bae_00ff39f7_0851843f_e6a53f80_d0528151_e39a3fae_0ce3fc3f; +defparam bootram.RAM2.INIT_14=256'h80e93880_59807424_712b5955_08ff0581_88188419_80d93881_5a77802e_11085a54; +defparam bootram.RAM2.INIT_15=256'h08535379_38781670_72802eb5_08770653_56818019_11880556_73822b78_7424b538; +defparam bootram.RAM2.INIT_16=256'hffad38ae_77085877_8025d638_57575473_79812c5a_fc17fc17_722dff14_51740853; +defparam bootram.RAM2.INIT_17=256'h57575473_79812c5a_fc17fc17_722dff14_3f740853_7951f8c0_1308a538_d40853bc; +defparam bootram.RAM2.INIT_18=256'hb5d80bfc_3fff3d0d_7951f894_0853722d_7251bc13_57ff9439_38d23980_8025ffa9; +defparam bootram.RAM2.INIT_19=256'h0d0404e3_f138833d_2e098106_525270ff_fc127008_9138702d_5270ff2e_05700852; +defparam bootram.RAM2.INIT_1A=256'h65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040_833f0400; +defparam bootram.RAM2.INIT_1B=256'h64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e; +defparam bootram.RAM2.INIT_1C=256'h756c7472_70657220_72207375_6f616465_6f6f746c_322b2062_55535250_4e4f4b00; +defparam bootram.RAM2.INIT_1D=256'h50322b20_20555352_74696e67_53746172_6e0a0000_6974696f_55206564_61205a50; +defparam bootram.RAM2.INIT_1E=256'h6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073; +defparam bootram.RAM2.INIT_1F=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; +defparam bootram.RAM2.INIT_20=256'h69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068; +defparam bootram.RAM2.INIT_21=256'h62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520; +defparam bootram.RAM2.INIT_22=256'h2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046; +defparam bootram.RAM2.INIT_23=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000; +defparam bootram.RAM2.INIT_24=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; +defparam bootram.RAM2.INIT_25=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; +defparam bootram.RAM2.INIT_26=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; +defparam bootram.RAM2.INIT_27=256'h6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61; +defparam bootram.RAM2.INIT_28=256'h64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f; +defparam bootram.RAM2.INIT_29=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563; +defparam bootram.RAM2.INIT_2A=256'h6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69_2e2e2e00; +defparam bootram.RAM2.INIT_2B=256'h61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000_6d616765; +defparam bootram.RAM2.INIT_2C=256'h61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67; +defparam bootram.RAM2.INIT_2D=256'h77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000; +defparam bootram.RAM2.INIT_2E=256'h2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75; +defparam bootram.RAM2.INIT_2F=256'h20202828_20202020_00202020_80700000_0b0b0b0b_01b200d9_05160364_14580a2c; +defparam bootram.RAM2.INIT_30=256'h10101010_10101010_20881010_20202020_20202020_20202020_20202020_28282820; +defparam bootram.RAM2.INIT_31=256'h01010101_41414141_10104141_10101010_04040410_04040404_10040404_10101010; +defparam bootram.RAM2.INIT_32=256'h02020202_42424242_10104242_10101010_01010101_01010101_01010101_01010101; +defparam bootram.RAM2.INIT_33=256'h00000000_00000000_20000000_10101010_02020202_02020202_02020202_02020202; +defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_37=256'h792e6578_64756d6d_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_38=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000; +defparam bootram.RAM2.INIT_39=256'hffffffff_000b0000_0018000f_ffff0031_05050400_01010100_00001ae0_00000000; +defparam bootram.RAM2.INIT_3A=256'h000019c0_00000000_00001758_000016f8_06820594_09c407d0_13880d05_00002710; +defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001a78_00001a1c; +defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00001704_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001; +defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_06=256'h792e6578_64756d6d_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_07=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000; -defparam bootram.RAM3.INIT_08=256'hffffffff_000b0000_0018000f_ffff0031_05050400_01010100_00001cc0_00000000; -defparam bootram.RAM3.INIT_09=256'h00001ba0_00000000_00001938_000018d8_06820594_09c407d0_13880d05_00002710; -defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001c58_00001bfc; -defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_000018e4_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001; +defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_16=256'hffffffff_00000000_ffffffff_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_25=256'hffffffff_00000000_ffffffff_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 1969883d7..0193eb2d3 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -271,12 +271,13 @@ module u2plus_core always @(posedge wb_clk) if(wb_rst) begin cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; - cpu_rst <= 1'b0; + cpu_rst <= 1'b1; end else begin case(cpu_bldr_ctrl_state) CPU_BLDR_CTRL_WAIT: begin + cpu_rst <= 1'b0; if (bldr_done == 1'b1) begin //set by the bootloader cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; cpu_rst <= 1'b1; -- cgit v1.2.3 From 6dbdffd226139b3a780f3894a46b844869956571 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 21 Dec 2010 13:27:12 -0800 Subject: don't overwrite checksum values --- usrp2/udp/prot_eng_tx.v | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index b86a9950c..76250029c 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -7,7 +7,8 @@ // Odd means the last word is half full // Flags[1:0] is {eop, sop} // Protocol word format is: -// 20 UDP Port Here +// 21 UDP Source Port Here +// 20 UDP Dest Port Here // 19 Last Header Line // 18 IP Header Checksum XOR // 17 IP Length Here @@ -43,7 +44,7 @@ module prot_eng_tx wire [HDR_WIDTH-1:0] header_word; reg [1:0] port_sel; - reg [32:0] per_port_data[0:3]; + reg [31:0] per_port_data[0:3]; reg [15:0] udp_src_port, udp_dst_port, chk_precompute; always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16]; @@ -51,11 +52,11 @@ module prot_eng_tx always @(posedge clk) if(set_stb & ((set_addr & 8'hE0) == BASE)) - begin - header_ram[set_addr[4:0]] <= set_data; - if(set_data[18]) - chk_precompute <= set_data[15:0]; - end + header_ram[set_addr[4:0]] <= set_data; + + always @(posedge clk) + if(set_stb & ((set_addr[4:0] & 8'hE0) == (BASE + 14))) + chk_precompute <= set_data[15:0]; always @(posedge clk) if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) -- cgit v1.2.3 From 64293ea66b52ad00cfc6862d39d0b16f0a1a63b0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 21 Dec 2010 17:27:46 -0800 Subject: udp_ports: fixed address comparison B+14 is comparison --- usrp2/udp/prot_eng_tx.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index 76250029c..c642842f6 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -55,7 +55,7 @@ module prot_eng_tx header_ram[set_addr[4:0]] <= set_data; always @(posedge clk) - if(set_stb & ((set_addr[4:0] & 8'hE0) == (BASE + 14))) + if(set_stb & (set_addr == (BASE + 14))) chk_precompute <= set_data[15:0]; always @(posedge clk) -- cgit v1.2.3 From 73f7b2cde070ef3b6c5db513407ba0b90296ac7d Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 22 Dec 2010 12:02:45 -0800 Subject: usrp-n210: add missing wires, incr compat, use boot ram as stack space --- usrp2/top/u2plus/u2plus_core.v | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 0193eb2d3..83bfce05d 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -261,12 +261,16 @@ module u2plus_core wire cpu_enb = ~cpu_rst; wire [aw-1:0] cpu_adr; wire [aw-1:0] cpu_sp_init = (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)? - 16'h3ff8 /*16K main ram*/: 16'h1ff8 /*8K boot ram*/; + 16'hfff8 : //top of 8K boot ram re-purposed at 56K + 16'h1ff8 ; //top of 8K boot ram //When the main program runs, it will try to access system ram at 0. - //This logic sets the upper bit high to force select the system ram. - assign m0_adr = ((cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE) && - (cpu_adr[15:14] == 2'b00))? {2'b10, cpu_adr[13:0]} : cpu_adr; + //This logic re-maps the cpu address to force select the system ram. + assign m0_adr = + (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_WAIT)? cpu_adr : ( //in bootloader + (cpu_adr[15:14] == 2'b00)? {2'b10, cpu_adr[13:0]} : ( //map 0-16 to 32-48 (main ram) + (cpu_adr[15:13] == 3'b111)? {3'b000, cpu_adr[12:0]} : ( //map 56-64 to 0-8 (boot ram) + cpu_adr))); //otherwise always @(posedge wb_clk) if(wb_rst) begin @@ -344,6 +348,9 @@ module u2plus_core wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + wire [31:0] router_debug; packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router @@ -407,7 +414,7 @@ module u2plus_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd3; + localparam compat_num = 32'd4; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -722,17 +729,8 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - //assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - //assign debug = 32'd0; // debug_extfifo; - assign debug_clk = {wb_rst, wb_clk}; - assign debug = { - cpu_adr, //16 bits - cpu_bldr_ctrl_state, //1 bits - bldr_done, //1 bit - cpu_rst, cpu_enb, // 2 bits - m0_we, m0_stb, m0_ack, m0_cyc, //4 - button, 7'b0 - }; + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; -- cgit v1.2.3