From a9f3336efeec5936ddfaf7f37344700cf79b3243 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 25 Oct 2010 17:00:18 -0700
Subject: add padding into gpif response path
---
usrp2/control_lib/fifo_to_wb_tb.v | 8 +++++++-
usrp2/fifo/Makefile.srcs | 1 +
usrp2/gpif/gpif.v | 11 ++++++++---
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/usrp2/control_lib/fifo_to_wb_tb.v b/usrp2/control_lib/fifo_to_wb_tb.v
index f1538e8d9..96ef4647c 100644
--- a/usrp2/control_lib/fifo_to_wb_tb.v
+++ b/usrp2/control_lib/fifo_to_wb_tb.v
@@ -107,7 +107,13 @@ module fifo_to_wb_tb();
@(posedge clk);
@(posedge clk);
InsertRW(16'hF00D, 6'd0, 8'hB5, 16'd7, 16'h1234);
+ #20000;
+ InsertRW(16'h9876, 6'd0, 8'h43, 16'd8, 16'hBEEF);
+ #20000;
+ InsertRW(16'h1000, 6'd0, 8'h96, 16'd4, 16'hF00D);
+ #20000;
+ InsertRW(16'h3000, 6'd0, 8'h12, 16'd10,16'hDEAD);
+ #20000 $finish;
end
- initial #20000 $finish;
endmodule // fifo_to_wb_tb
diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index 31b1f505a..7e6a231ae 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -34,4 +34,5 @@ packet_generator32.v \
packet_generator.v \
packet_verifier32.v \
packet_verifier.v \
+fifo19_pad.v \
))
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index e88ffce20..1edcbf6ad 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -75,8 +75,8 @@ module gpif
wire rx36_src_rdy, rx36_dst_rdy;
wire [17:0] rx18_data;
wire rx18_src_rdy, rx18_dst_rdy;
- wire [17:0] resp_data;
- wire resp_src_rdy, resp_dst_rdy;
+ wire [17:0] resp_data, resp_int;
+ wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int;
fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
@@ -104,12 +104,17 @@ module gpif
fifo_to_wb fifo_to_wb
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
.data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy),
- .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy),
+ .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int),
.wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o),
.wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i),
.triggers(triggers),
.debug0(), .debug1());
+ fifo19_pad #(.LENGTH(16)) fifo19_pad
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear),
+ .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int),
+ .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy));
+
// ////////////////////////////////////////////
// DEBUG
--
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