From 9e97e773b9952ec3212e6c818bb40d785016afa4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 11 Aug 2010 16:26:58 -0700 Subject: connect the setting reg to the real clock and reset --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 516a5cf96..4561df173 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -70,7 +70,7 @@ module u1e_core wire clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear; setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear)); assign clear_tx = clear_tx_int & do_clear; assign clear_rx = clear_rx_int & do_clear; -- cgit v1.2.3