From 9451cb630962216492496f2f13d43ab2d08bde5d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 23 May 2011 18:21:09 -0700 Subject: u2p: FPGA internal termination on the clock line from ADC --- usrp2/top/u2plus/capture_ddrlvds.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v index 2bf114988..d263e0cfa 100644 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ b/usrp2/top/u2plus/capture_ddrlvds.v @@ -14,7 +14,7 @@ module capture_ddrlvds wire [(2*WIDTH)-1:0] out_pre1; reg [(2*WIDTH)-1:0] out_pre2; - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("FALSE")) + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); genvar i; @@ -29,7 +29,7 @@ module capture_ddrlvds end endgenerate - always @(negedge clk) + always @(posedge clk) out_pre2 <= out_pre1; always @(posedge clk) -- cgit v1.2.3