From 0f705316752a911ed031a479355e44f922222970 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 20 May 2011 10:49:52 -0700 Subject: usrp2: turn on ups_per_sec to avoid timeout issues on low sample rates --- host/docs/transport.rst | 2 +- host/examples/tx_timed_samples.cpp | 3 --- host/lib/usrp/usrp2/mboard_impl.cpp | 2 +- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/host/docs/transport.rst b/host/docs/transport.rst index 2371d2497..e7c2f1885 100644 --- a/host/docs/transport.rst +++ b/host/docs/transport.rst @@ -47,7 +47,7 @@ which allows the host to determine throttling conditions for the transmission of The following mechanisms affect the transmission of periodic update packets: * **ups_per_fifo:** The number of update packets for each FIFO's worth of bytes sent into the device -* **ups_per_sec:** The number of update packets per second (disabled by default) +* **ups_per_sec:** The number of update packets per second (defaults to 20 updates per second) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Resize socket buffers diff --git a/host/examples/tx_timed_samples.cpp b/host/examples/tx_timed_samples.cpp index 03f87122d..d33dc13c3 100644 --- a/host/examples/tx_timed_samples.cpp +++ b/host/examples/tx_timed_samples.cpp @@ -100,9 +100,6 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ uhd::device::SEND_MODE_ONE_PACKET, timeout ); - //use a small timeout for subsequent packets - timeout = 0.1; - //do not use time spec for subsequent packets md.has_time_spec = false; diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 2885e57e4..027cb5f78 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -116,7 +116,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( dsp_init(); //setting the cycles per update (disabled by default) - const double ups_per_sec = device_addr.cast("ups_per_sec", 0.0); + const double ups_per_sec = device_addr.cast("ups_per_sec", 20); if (ups_per_sec > 0.0){ const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec); _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up); -- cgit v1.2.3 From 7dbd83533974713a4d170f01cd2421378cf96ec7 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 20 May 2011 11:01:58 -0700 Subject: uhd: picked some minor changes from super packet handler --- host/include/uhd/types/metadata.hpp | 2 ++ host/lib/transport/gen_vrt_if_packet.py | 1 + 2 files changed, 3 insertions(+) diff --git a/host/include/uhd/types/metadata.hpp b/host/include/uhd/types/metadata.hpp index f4e084430..269c77c7c 100644 --- a/host/include/uhd/types/metadata.hpp +++ b/host/include/uhd/types/metadata.hpp @@ -81,6 +81,8 @@ namespace uhd{ ERROR_CODE_BROKEN_CHAIN = 0x4, //! An internal receive buffer has filled. ERROR_CODE_OVERFLOW = 0x8, + //! Multi-channel alignment failed. + ERROR_CODE_ALIGNMENT = 0xc, //! The packet could not be parsed. ERROR_CODE_BAD_PACKET = 0xf } error_code; diff --git a/host/lib/transport/gen_vrt_if_packet.py b/host/lib/transport/gen_vrt_if_packet.py index 7df2092d8..7440def6a 100755 --- a/host/lib/transport/gen_vrt_if_packet.py +++ b/host/lib/transport/gen_vrt_if_packet.py @@ -140,6 +140,7 @@ void vrt::if_hdr_pack_$(suffix)( //fill in complete header word packet_buff[0] = $(XE_MACRO)(boost::uint32_t(0 + | (if_packet_info.packet_type << 29) | vrt_hdr_flags | ((if_packet_info.packet_count & 0xf) << 16) | (if_packet_info.num_packet_words32 & 0xffff) -- cgit v1.2.3 From f58abdcba9ab23a399d7da2687e772c6ae24f41d Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Fri, 20 May 2011 13:25:05 -0700 Subject: N210: how the heck did the PPS fix get dropped again --- usrp2/top/u2plus/u2plus.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index c0140e989..7c2270df6 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -348,12 +348,15 @@ module u2plus // DAC A is also inverted in schematic to facilitate clean layout always @(negedge dsp_clk) DACA <= ~dac_b_int; always @(negedge dsp_clk) DACB <= dac_a_int; + + wire pps; + assign pps = PPS_IN ^ PPS2_IN; u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), .clk_to_mac (CLK_TO_MAC_int2), - .pps_in (PPS_IN), + .pps_in (pps), .leds (leds_int), .debug (debug[31:0]), .debug_clk (debug_clk[1:0]), -- cgit v1.2.3 From 4d947971f4a8ec52bb39e80f1b0651daacf4f078 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 20 May 2011 13:25:17 -0700 Subject: usrp-e100: set_ignore_sync_fpga_plus_codec --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 49ce0c742..f1b29840a 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -180,7 +180,6 @@ public: _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC; - _ad9522_regs.divider0_ignore_sync = 1; // master FPGA clock ignores sync (always on, cannot be disabled by sync pulse) this->use_internal_ref(); @@ -438,6 +437,8 @@ private: } void calibrate_now(void){ + set_ignore_sync_fpga_plus_codec(false); //want vco cal to sync + //vco calibration routine: _ad9522_regs.vco_calibration_now = 0; this->send_reg(0x18); @@ -466,9 +467,20 @@ private: _ad9522_regs.get_read_reg(addr), 24 ); _ad9522_regs.set_reg(addr, reg); - if (_ad9522_regs.digital_lock_detect) return; + if (_ad9522_regs.digital_lock_detect) goto finalize; } UHD_MSG(error) << "USRP-E100 clock control: lock detection timeout" << std::endl; + finalize: + + set_ignore_sync_fpga_plus_codec(true); //never loose sync between these two + } + + void set_ignore_sync_fpga_plus_codec(bool enb){ + _ad9522_regs.divider0_ignore_sync = (enb)?1:0; // master FPGA clock ignores sync (always on, cannot be disabled by sync pulse) + _ad9522_regs.divider1_ignore_sync = (enb)?1:0; // codec clock ignores sync (always on, cannot be disabled by sync pulse) + this->send_reg(0x191); + this->send_reg(0x194); + this->latch_regs(); } void soft_sync(void){ -- cgit v1.2.3 From 9b4fa86af2d0ed59d0881a3d153b309c94c7e4e5 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 16 May 2011 11:55:42 -0700 Subject: u1e: incremented compat # to 4 for vita length change --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 8e6d74edf..d10a3ab30 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -36,7 +36,7 @@ module u1e_core localparam SR_GLOBAL_RESET = 50; // 1 reg localparam SR_REG_TEST32 = 52; // 1 reg - wire [7:0] COMPAT_NUM = 8'd3; + wire [7:0] COMPAT_NUM = 8'd4; wire wb_clk = clk_fpga; wire wb_rst, global_reset; -- cgit v1.2.3 From f9fae3373e67c1bc19ab594d4b5604d69ecb0d68 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 23 May 2011 13:17:42 -0700 Subject: tvrx2: fix docs formatting typo --- host/docs/dboards.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/host/docs/dboards.rst b/host/docs/dboards.rst index 959a1b300..593dd3a42 100644 --- a/host/docs/dboards.rst +++ b/host/docs/dboards.rst @@ -265,6 +265,7 @@ The TVRX2 board has 2 real-mode subdevices. It is operated at a low IF. Receive Subdevices: + * **Subdevice RX1:** real signal on antenna J100 * **Subdevice RX2:** real signal on antenna J140 -- cgit v1.2.3