From 8ca9a0cd06251cd2f44708b8a89f97bdb3efce1a Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Fri, 22 Feb 2019 11:31:39 -0800 Subject: mpm: rhodium: Fix clock value log formatting Before, the log messages would occasionally print 6 digits worth of precision for sample clock values that only require 2. --- mpm/python/usrp_mpm/dboard_manager/lmk_rh.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_rh.py b/mpm/python/usrp_mpm/dboard_manager/lmk_rh.py index c2c2ca560..062f50ddd 100644 --- a/mpm/python/usrp_mpm/dboard_manager/lmk_rh.py +++ b/mpm/python/usrp_mpm/dboard_manager/lmk_rh.py @@ -21,8 +21,9 @@ class LMK04828Rh(LMK04828): parent_log.getChild("LMK04828-{}".format(slot_idx)) if parent_log is not None \ else get_logger("LMK04828-{}".format(slot_idx)) LMK04828.__init__(self, regs_iface, parent_log) - self.log.debug("Using reference clock frequency {} MHz".format(ref_clock_freq/1e6)) - self.log.debug("Using sampling clock frequency: {} MHz".format(sampling_clock_freq/1e6)) + self.log.debug("Using reference clock frequency {:.2f} MHz".format(ref_clock_freq/1e6)) + self.log.debug("Using sampling clock frequency: {:.2f} MHz" + .format(sampling_clock_freq/1e6)) self.ref_clock_freq = ref_clock_freq self.sampling_clock_freq = sampling_clock_freq # VCXO on Rh runs at 122.88 MHz -- cgit v1.2.3