From 2faaa1e36257c9909415f142e165e5ad74495a4e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Feb 2010 18:26:47 -0800 Subject: skeletons that don't work yet --- usrp2/top/safe_u1e/Makefile | 245 ++++++++++++++++++++++++++++ usrp2/top/safe_u1e/safe_u1e.v | 362 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 607 insertions(+) create mode 100644 usrp2/top/safe_u1e/Makefile create mode 100644 usrp2/top/safe_u1e/safe_u1e.v diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile new file mode 100644 index 000000000..8fe77d554 --- /dev/null +++ b/usrp2/top/safe_u1e/Makefile @@ -0,0 +1,245 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := safe_u1e +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/safe_u1e/u1e.ucf \ +top/safe_u1e/safe_u1e.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v new file mode 100644 index 000000000..c880a9e55 --- /dev/null +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -0,0 +1,362 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module safe_u1e + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + //input ADC_clkout_p, //input ADC_clkout_n, + //input ADCA_12_p, //input ADCA_12_n, + //input ADCA_10_p, //input ADCA_10_n, + //input ADCA_8_p, //input ADCA_8_n, + //input ADCA_6_p, //input ADCA_6_n, + //input ADCA_4_p, //input ADCA_4_n, + //input ADCA_2_p, //input ADCA_2_n, + //input ADCA_0_p, //input ADCA_0_n, + //input ADCB_12_p, //input ADCB_12_n, + //input ADCB_10_p, //input ADCB_10_n, + //input ADCB_8_p, //input ADCB_8_n, + //input ADCB_6_p, //input ADCB_6_n, + //input ADCB_4_p, //input ADCB_4_n, + //input ADCB_2_p, //input ADCB_2_n, + //input ADCB_0_p, //input ADCB_0_n, + + // DAC + //output [15:0] DACA, + //output [15:0] DACB, + //input DAC_LOCK, // unused for now + + // DB IO Pins + //inout [15:0] io_tx, + //inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + //input FPGA_RESET, + //output [1:0] debug_clk, + //output [31:0] debug, + //output [3:1] TXD, //input [3:1] RXD, // UARTs + ////input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + //output [1:0] clk_en, + //output [1:0] clk_sel, + //input CLK_FUNC, // FIXME is an //input to control the 9510 + //input CLK_STATUS, + + //inout SCL, //inout SDA, // I2C + + // PPS + //input PPS_IN, //input PPS2_IN, + + // SPI + //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, + //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, + //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, + //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, + //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, + //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, + //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, + //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, + //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, + + // GigE PHY + //input CLK_TO_MAC, + + //output reg [7:0] GMII_TXD, + //output reg GMII_TX_EN, + //output reg GMII_TX_ER, + //output GMII_GTX_CLK, + //input GMII_TX_CLK, // 100mbps clk + + //input GMII_RX_CLK, + //input [7:0] GMII_RXD, + //input GMII_RX_DV, + //input GMII_RX_ER, + //input GMII_COL, + //input GMII_CRS, + + //input PHY_INTn, // open drain + //inout MDIO, + //output MDC, + //output PHY_RESETn, + output ETH_LED + + //input POR, + + // Expansion + //input exp_time_in_p, //input exp_time_in_n, // Diff + //output exp_time_out_p, //output exp_time_out_n, // Diff + //input exp_user_in_p, //input exp_user_in_n, // Diff + //output exp_user_out_p, //output exp_user_out_n, // Diff + + // SERDES + //output ser_enable, + //output ser_prbsen, + //output ser_loopen, + //output ser_rx_en, + + //output ser_tx_clk, + //output reg [15:0] ser_t, + //output reg ser_tklsb, + //output reg ser_tkmsb, + + //input ser_rx_clk, + //input [15:0] ser_r, + //input ser_rklsb, + //input ser_rkmsb, + + // SRAM + //inout [35:0] RAM_D, + //output [20:0] RAM_A, + //output [3:0] RAM_BWn, + //output RAM_ZZ, + //output RAM_LDn, + //output RAM_OEn, + //output RAM_WEn, + //output RAM_CENn, + //output RAM_CLK, + + // SPI Flash + //output flash_cs, + //output flash_clk, + //output flash_mosi, + //input flash_miso + ); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + reg [31:0] ctr; + + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign {leds,ETH_LED} = ~ctr[29:24]; + + +/* + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire dcm_rst = 0; + + wire [13:0] adc_a, adc_b; + + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a,adc_b})); + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = ~leds_int; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + u2_core u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_time_in), + .exp_pps_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (DACA[15:0]), + .dac_b (DACB[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); +*/ +endmodule // safe_u2plus -- cgit v1.2.3 From 3f2e589f639c6ec16e62b337568ebca96e241ae2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Feb 2010 18:41:22 -0800 Subject: first cut at blinking leds --- usrp2/top/safe_u1e/.gitignore | 2 + usrp2/top/safe_u1e/Makefile | 2 +- usrp2/top/safe_u1e/safe_u1e.ucf | 228 ++++++++++++++++++++++++++ usrp2/top/safe_u1e/safe_u1e.v | 350 +--------------------------------------- 4 files changed, 237 insertions(+), 345 deletions(-) create mode 100644 usrp2/top/safe_u1e/.gitignore create mode 100644 usrp2/top/safe_u1e/safe_u1e.ucf diff --git a/usrp2/top/safe_u1e/.gitignore b/usrp2/top/safe_u1e/.gitignore new file mode 100644 index 000000000..bdc5af040 --- /dev/null +++ b/usrp2/top/safe_u1e/.gitignore @@ -0,0 +1,2 @@ +*~ +build diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile index 8fe77d554..664835187 100644 --- a/usrp2/top/safe_u1e/Makefile +++ b/usrp2/top/safe_u1e/Makefile @@ -175,7 +175,7 @@ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ top/u2_core/u2_core.v \ -top/safe_u1e/u1e.ucf \ +top/safe_u1e/safe_u1e.ucf \ top/safe_u1e/safe_u1e.v ################################################## diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf new file mode 100644 index 000000000..83dbeca54 --- /dev/null +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -0,0 +1,228 @@ +#NET "EM_CLK" LOC = "F11" ; +#NET "overo_gpio23" LOC = "B3" ; +#NET "overo_gpio22" LOC = "A3" ; +#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio14" LOC = "C4" ; +#NET "overo_gpio176" LOC = "B4" ; +#NET "overo_gpio64" LOC = "A4" ; +#NET "overo_gpio65" LOC = "F8" ; +#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio145" LOC = "C7" ; +#NET "overo_gpio163" LOC = "D7" ; +#NET "overo_gpio146" LOC = "A6" ; +#NET "overo_gpio144" LOC = "A5" ; +#NET "overo_gpio147" LOC = "B6" ; +#NET "overo_gpio128" LOC = "G8" ; +#NET "overo_gpio0" LOC = "F9" ; +#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; +#NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NWP" LOC = "F13" ; +#NET "EM_NBE1" LOC = "D14" ; +#NET "EM_NBE0" LOC = "A13" ; +#NET "EM_NWE" LOC = "B13" ; +#NET "EM_NOE" LOC = "A14" ; +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_D15" LOC = "D13" ; +#NET "EM_D14" LOC = "D15" ; +#NET "EM_D13" LOC = "C16" ; +#NET "EM_D12" LOC = "B20" ; +#NET "EM_D11" LOC = "A19" ; +#NET "EM_D10" LOC = "A17" ; +#NET "EM_D9" LOC = "E15" ; +#NET "EM_D8" LOC = "F15" ; +#NET "EM_D7" LOC = "E16" ; +#NET "EM_D6" LOC = "F16" ; +#NET "EM_D5" LOC = "B17" ; +#NET "EM_D4" LOC = "C17" ; +#NET "EM_D3" LOC = "B19" ; +#NET "EM_D2" LOC = "D19" ; +#NET "EM_D1" LOC = "C19" ; +#NET "EM_D0" LOC = "A20" ; +#NET "SYSEN" LOC = "C11" ; +#NET "EM_NCS6" LOC = "E17" ; +#NET "EM_NCS5" LOC = "E10" ; +#NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; +#NET "EM_A10" LOC = "C14" ; +#NET "EM_A9" LOC = "C10" ; +#NET "EM_A8" LOC = "C5" ; +#NET "EM_A7" LOC = "A18" ; +#NET "EM_A6" LOC = "A15" ; +#NET "EM_A5" LOC = "A12" ; +#NET "EM_A4" LOC = "A10" ; +#NET "EM_A3" LOC = "E7" ; +#NET "EM_A2" LOC = "A7" ; +#NET "EM_A1" LOC = "C15" ; +#NET "db_scl" LOC = "U4" ; +#NET "db_sda" LOC = "U5" ; +#NET "db_sclk_rx" LOC = "W3" ; +#NET "db_miso_rx" LOC = "W2" ; +#NET "db_mosi_rx" LOC = "V4" ; +#NET "db_sen_rx" LOC = "V3" ; +#NET "db_sclk_tx" LOC = "Y1" ; +#NET "db_miso_tx" LOC = "W1" ; +#NET "db_mosi_tx" LOC = "R3" ; +#NET "db_sen_tx" LOC = "T4" ; +#NET "cgen_miso" LOC = "U2" ; +#NET "cgen_mosi" LOC = "V1" ; +#NET "cgen_sclk" LOC = "R5" ; +#NET "cgen_sen_b" LOC = "T1" ; +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; +#NET "debug_00" LOC = "P6" ; +#NET "debug_01" LOC = "R6" ; +#NET "debug_02" LOC = "P1" ; +#NET "debug_03" LOC = "P2" ; +#NET "debug_04" LOC = "N6" ; +#NET "debug_05" LOC = "N5" ; +#NET "debug_06" LOC = "N1" ; +#NET "debug_07" LOC = "K2" ; +#NET "debug_08" LOC = "K3" ; +#NET "debug_09" LOC = "K6" ; +#NET "debug_10" LOC = "L5" ; +#NET "debug_11" LOC = "H2" ; +#NET "debug_12" LOC = "K4" ; +#NET "debug_13" LOC = "K5" ; +#NET "debug_14" LOC = "G1" ; +#NET "debug_15" LOC = "H1" ; +#NET "debug_16" LOC = "H5" ; +#NET "debug_17" LOC = "H6" ; +#NET "debug_18" LOC = "E3" ; +#NET "debug_19" LOC = "E4" ; +#NET "debug_20" LOC = "G5" ; +#NET "debug_21" LOC = "G6" ; +#NET "debug_22" LOC = "F2" ; +#NET "debug_23" LOC = "F1" ; +#NET "debug_24" LOC = "H3" ; +#NET "debug_25" LOC = "H4" ; +#NET "debug_26" LOC = "F4" ; +#NET "debug_27" LOC = "F5" ; +#NET "debug_28" LOC = "C2" ; +#NET "debug_29" LOC = "C1" ; +#NET "debug_30" LOC = "F3" ; +#NET "debug_31" LOC = "G3" ; +#NET "debug_pb2" LOC = "Y2" ; +#NET "debug_pb1" LOC = "AA1" ; +#NET "debug_pb0" LOC = "N3" ; +#NET "dip_sw_7" LOC = "T3" ; +#NET "dip_sw_6" LOC = "U3" ; +#NET "dip_sw_5" LOC = "M3" ; +#NET "dip_sw_4" LOC = "N4" ; +#NET "dip_sw_3" LOC = "J3" ; +#NET "dip_sw_2" LOC = "J4" ; +#NET "dip_sw_1" LOC = "J6" ; +#NET "dip_sw_0" LOC = "J7" ; +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; +#NET "debug_clk0" LOC = "L6" ; +#NET "debug_clk1" LOC = "M5" ; +#NET "unnamed_net37" LOC = "B1" ; +#NET "unnamed_net36" LOC = "B22" ; +#NET "unnamed_net35" LOC = "D2" ; +#NET "unnamed_net34" LOC = "A21" ; +#NET "GND" LOC = "V19" ; +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "unnamed_net45" LOC = "F7" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; +#NET "unnamed_net44" LOC = "V6" ; +#NET "unnamed_net43" LOC = "AA3" ; +#NET "unnamed_net42" LOC = "AB3" ; +#NET "aux_sdi_codec" LOC = "F19" ; +#NET "aux_sdo_codec" LOC = "F18" ; +#NET "aux_sclk_codec" LOC = "D21" ; +#NET "reset_codec" LOC = "D22" ; +#NET "sen_codec" LOC = "D20" ; +#NET "mosi_codec" LOC = "E19" ; +#NET "miso_codec" LOC = "F21" ; +#NET "sclk_codec" LOC = "E20" ; +#NET "RXSYNC" LOC = "F22" ; +#NET "DB11" LOC = "E22" ; +#NET "DB10" LOC = "J19" ; +#NET "DB09" LOC = "H20" ; +#NET "DB08" LOC = "G19" ; +#NET "DB07" LOC = "F20" ; +#NET "DB06" LOC = "K16" ; +#NET "DB05" LOC = "J17" ; +#NET "DB04" LOC = "H22" ; +#NET "DB03" LOC = "G22" ; +#NET "DB02" LOC = "H17" ; +#NET "DB01" LOC = "H18" ; +#NET "DB00" LOC = "K20" ; +#NET "DA11" LOC = "J20" ; +#NET "DA10" LOC = "K19" ; +#NET "DA09" LOC = "K18" ; +#NET "DA08" LOC = "L22" ; +#NET "DA07" LOC = "K22" ; +#NET "DA06" LOC = "N22" ; +#NET "DA05" LOC = "M22" ; +#NET "DA04" LOC = "N20" ; +#NET "DA03" LOC = "N19" ; +#NET "DA02" LOC = "R22" ; +#NET "DA01" LOC = "P22" ; +#NET "DA00" LOC = "N17" ; +#NET "TX13" LOC = "P19" ; +#NET "TX12" LOC = "R18" ; +#NET "TX11" LOC = "U20" ; +#NET "TX10" LOC = "T20" ; +#NET "TX09" LOC = "R19" ; +#NET "TX08" LOC = "R20" ; +#NET "TX07" LOC = "W22" ; +#NET "TX06" LOC = "Y22" ; +#NET "TX05" LOC = "T18" ; +#NET "TX04" LOC = "T17" ; +#NET "TX03" LOC = "W19" ; +#NET "TX02" LOC = "V20" ; +#NET "TX01" LOC = "Y21" ; +#NET "TX00" LOC = "AA22" ; +#NET "TXSYNC" LOC = "U18" ; +#NET "TXBLANK" LOC = "U19" ; +#NET "PPS_IN" LOC = "M17" ; +#NET "io_tx_00" LOC = "AB20" ; +#NET "io_tx_01" LOC = "Y17" ; +#NET "io_tx_02" LOC = "Y16" ; +#NET "io_tx_03" LOC = "U16" ; +#NET "io_tx_04" LOC = "V16" ; +#NET "io_tx_05" LOC = "AB19" ; +#NET "io_tx_06" LOC = "AA19" ; +#NET "io_tx_07" LOC = "U14" ; +#NET "io_tx_08" LOC = "U15" ; +#NET "io_tx_09" LOC = "AB17" ; +#NET "io_tx_10" LOC = "AB18" ; +#NET "io_tx_11" LOC = "Y13" ; +#NET "io_tx_12" LOC = "W14" ; +#NET "io_tx_13" LOC = "U13" ; +#NET "io_tx_14" LOC = "AA15" ; +#NET "io_tx_15" LOC = "AB14" ; +#NET "io_rx_00" LOC = "Y8" ; +#NET "io_rx_01" LOC = "Y9" ; +#NET "io_rx_02" LOC = "V7" ; +#NET "io_rx_03" LOC = "U8" ; +#NET "io_rx_04" LOC = "V10" ; +#NET "io_rx_05" LOC = "U9" ; +#NET "io_rx_06" LOC = "AB7" ; +#NET "io_rx_07" LOC = "AA8" ; +#NET "io_rx_08" LOC = "W8" ; +#NET "io_rx_09" LOC = "V8" ; +#NET "io_rx_10" LOC = "AB5" ; +#NET "io_rx_11" LOC = "AB6" ; +#NET "io_rx_12" LOC = "AB4" ; +#NET "io_rx_13" LOC = "AA4" ; +#NET "io_rx_14" LOC = "W5" ; +#NET "io_rx_15" LOC = "Y4" ; +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; +NET "debug_led<2>" LOC = "T5" ; +NET "debug_led<1>" LOC = "R2" ; +NET "debug_led<0>" LOC = "R1" ; diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index c880a9e55..79aaac6cd 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -4,131 +4,14 @@ module safe_u1e ( input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - //input ADC_clkout_p, //input ADC_clkout_n, - //input ADCA_12_p, //input ADCA_12_n, - //input ADCA_10_p, //input ADCA_10_n, - //input ADCA_8_p, //input ADCA_8_n, - //input ADCA_6_p, //input ADCA_6_n, - //input ADCA_4_p, //input ADCA_4_n, - //input ADCA_2_p, //input ADCA_2_n, - //input ADCA_0_p, //input ADCA_0_n, - //input ADCB_12_p, //input ADCB_12_n, - //input ADCB_10_p, //input ADCB_10_n, - //input ADCB_8_p, //input ADCB_8_n, - //input ADCB_6_p, //input ADCB_6_n, - //input ADCB_4_p, //input ADCB_4_n, - //input ADCB_2_p, //input ADCB_2_n, - //input ADCB_0_p, //input ADCB_0_n, - - // DAC - //output [15:0] DACA, - //output [15:0] DACB, - //input DAC_LOCK, // unused for now - - // DB IO Pins - //inout [15:0] io_tx, - //inout [15:0] io_rx, - - // Misc, debug - output [5:1] leds, // LED4 is shared w/INIT_B - //input FPGA_RESET, - //output [1:0] debug_clk, - //output [31:0] debug, - //output [3:1] TXD, //input [3:1] RXD, // UARTs - ////input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - //output [1:0] clk_en, - //output [1:0] clk_sel, - //input CLK_FUNC, // FIXME is an //input to control the 9510 - //input CLK_STATUS, - - //inout SCL, //inout SDA, // I2C - - // PPS - //input PPS_IN, //input PPS2_IN, - - // SPI - //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, - //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, - //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, - //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, - //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, - //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, - //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, - //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, - //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, - - // GigE PHY - //input CLK_TO_MAC, - - //output reg [7:0] GMII_TXD, - //output reg GMII_TX_EN, - //output reg GMII_TX_ER, - //output GMII_GTX_CLK, - //input GMII_TX_CLK, // 100mbps clk - - //input GMII_RX_CLK, - //input [7:0] GMII_RXD, - //input GMII_RX_DV, - //input GMII_RX_ER, - //input GMII_COL, - //input GMII_CRS, - - //input PHY_INTn, // open drain - //inout MDIO, - //output MDC, - //output PHY_RESETn, - output ETH_LED - - //input POR, - - // Expansion - //input exp_time_in_p, //input exp_time_in_n, // Diff - //output exp_time_out_p, //output exp_time_out_n, // Diff - //input exp_user_in_p, //input exp_user_in_n, // Diff - //output exp_user_out_p, //output exp_user_out_n, // Diff - - // SERDES - //output ser_enable, - //output ser_prbsen, - //output ser_loopen, - //output ser_rx_en, - - //output ser_tx_clk, - //output reg [15:0] ser_t, - //output reg ser_tklsb, - //output reg ser_tkmsb, - - //input ser_rx_clk, - //input [15:0] ser_r, - //input ser_rklsb, - //input ser_rkmsb, - - // SRAM - //inout [35:0] RAM_D, - //output [20:0] RAM_A, - //output [3:0] RAM_BWn, - //output RAM_ZZ, - //output RAM_LDn, - //output RAM_OEn, - //output RAM_WEn, - //output RAM_CENn, - //output RAM_CLK, - - // SPI Flash - //output flash_cs, - //output flash_clk, - //output flash_mosi, - //input flash_miso + output [2:0] debug_led ); // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + wire clk_fpga; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; reg [31:0] ctr; @@ -136,227 +19,6 @@ module safe_u1e always @(posedge clk_fpga) ctr <= ctr + 1; - assign {leds,ETH_LED} = ~ctr[29:24]; - - -/* - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire dcm_rst = 0; - - wire [13:0] adc_a, adc_b; - - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a,adc_b})); - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; + assign debug_led = ctr[27:25]; - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - u2_core u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_time_in), - .exp_pps_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (DACA[15:0]), - .dac_b (DACB[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); -*/ endmodule // safe_u2plus -- cgit v1.2.3 From 36138857e9d64a129840814aed79c00cc6f505e9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Feb 2010 19:04:26 -0800 Subject: builds a successful led blinker --- usrp2/top/safe_u1e/.gitignore | 2 ++ usrp2/top/safe_u1e/Makefile | 3 ++- usrp2/top/safe_u1e/safe_u1e.v | 1 - 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/usrp2/top/safe_u1e/.gitignore b/usrp2/top/safe_u1e/.gitignore index bdc5af040..f8b57ea21 100644 --- a/usrp2/top/safe_u1e/.gitignore +++ b/usrp2/top/safe_u1e/.gitignore @@ -1,2 +1,4 @@ *~ build +*.log +*.cmd diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile index 664835187..d28cc2b89 100644 --- a/usrp2/top/safe_u1e/Makefile +++ b/usrp2/top/safe_u1e/Makefile @@ -217,7 +217,8 @@ export GEN_PROG_FILE_PROPERTIES := \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" export SIM_MODEL_PROPERTIES := "" diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index 79aaac6cd..1b81bab5a 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -12,7 +12,6 @@ module safe_u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; reg [31:0] ctr; -- cgit v1.2.3 From 44d8aeb6bdbe598d6d453c4530015892959cb765 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Feb 2010 21:09:56 -0800 Subject: organized the pins in the ucf by function --- usrp2/top/safe_u1e/safe_u1e.ucf | 128 ++++++++++++++++++++++------------------ 1 file changed, 72 insertions(+), 56 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf index 83dbeca54..16265c203 100644 --- a/usrp2/top/safe_u1e/safe_u1e.ucf +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -1,3 +1,8 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC #NET "EM_CLK" LOC = "F11" ; #NET "overo_gpio23" LOC = "B3" ; #NET "overo_gpio22" LOC = "A3" ; @@ -56,6 +61,7 @@ #NET "EM_A3" LOC = "E7" ; #NET "EM_A2" LOC = "A7" ; #NET "EM_A1" LOC = "C15" ; + #NET "db_scl" LOC = "U4" ; #NET "db_sda" LOC = "U5" ; #NET "db_sclk_rx" LOC = "W3" ; @@ -72,49 +78,57 @@ #NET "cgen_sen_b" LOC = "T1" ; #NET "FPGA_TXD" LOC = "U1" ; #NET "FPGA_RXD" LOC = "T6" ; -#NET "debug_00" LOC = "P6" ; -#NET "debug_01" LOC = "R6" ; -#NET "debug_02" LOC = "P1" ; -#NET "debug_03" LOC = "P2" ; -#NET "debug_04" LOC = "N6" ; -#NET "debug_05" LOC = "N5" ; -#NET "debug_06" LOC = "N1" ; -#NET "debug_07" LOC = "K2" ; -#NET "debug_08" LOC = "K3" ; -#NET "debug_09" LOC = "K6" ; -#NET "debug_10" LOC = "L5" ; -#NET "debug_11" LOC = "H2" ; -#NET "debug_12" LOC = "K4" ; -#NET "debug_13" LOC = "K5" ; -#NET "debug_14" LOC = "G1" ; -#NET "debug_15" LOC = "H1" ; -#NET "debug_16" LOC = "H5" ; -#NET "debug_17" LOC = "H6" ; -#NET "debug_18" LOC = "E3" ; -#NET "debug_19" LOC = "E4" ; -#NET "debug_20" LOC = "G5" ; -#NET "debug_21" LOC = "G6" ; -#NET "debug_22" LOC = "F2" ; -#NET "debug_23" LOC = "F1" ; -#NET "debug_24" LOC = "H3" ; -#NET "debug_25" LOC = "H4" ; -#NET "debug_26" LOC = "F4" ; -#NET "debug_27" LOC = "F5" ; -#NET "debug_28" LOC = "C2" ; -#NET "debug_29" LOC = "C1" ; -#NET "debug_30" LOC = "F3" ; -#NET "debug_31" LOC = "G3" ; -#NET "debug_pb2" LOC = "Y2" ; -#NET "debug_pb1" LOC = "AA1" ; -#NET "debug_pb0" LOC = "N3" ; -#NET "dip_sw_7" LOC = "T3" ; -#NET "dip_sw_6" LOC = "U3" ; -#NET "dip_sw_5" LOC = "M3" ; -#NET "dip_sw_4" LOC = "N4" ; -#NET "dip_sw_3" LOC = "J3" ; -#NET "dip_sw_2" LOC = "J4" ; -#NET "dip_sw_1" LOC = "J6" ; -#NET "dip_sw_0" LOC = "J7" ; + +## Debug pins +NET "debug_led<2>" LOC = "T5" ; +NET "debug_led<1>" LOC = "R2" ; +NET "debug_led<0>" LOC = "R1" ; +#NET "debug<0>" LOC = "P6" ; +#NET "debug<1>" LOC = "R6" ; +#NET "debug<2>" LOC = "P1" ; +#NET "debug<3>" LOC = "P2" ; +#NET "debug<4>" LOC = "N6" ; +#NET "debug<5>" LOC = "N5" ; +#NET "debug<6>" LOC = "N1" ; +#NET "debug<7>" LOC = "K2" ; +#NET "debug<8>" LOC = "K3" ; +#NET "debug<9>" LOC = "K6" ; +#NET "debug<10>" LOC = "L5" ; +#NET "debug<11>" LOC = "H2" ; +#NET "debug<12>" LOC = "K4" ; +#NET "debug<13>" LOC = "K5" ; +#NET "debug<14>" LOC = "G1" ; +#NET "debug<15>" LOC = "H1" ; +#NET "debug<16>" LOC = "H5" ; +#NET "debug<17>" LOC = "H6" ; +#NET "debug<18>" LOC = "E3" ; +#NET "debug<19>" LOC = "E4" ; +#NET "debug<20>" LOC = "G5" ; +#NET "debug<21>" LOC = "G6" ; +#NET "debug<22>" LOC = "F2" ; +#NET "debug<23>" LOC = "F1" ; +#NET "debug<24>" LOC = "H3" ; +#NET "debug<25>" LOC = "H4" ; +#NET "debug<26>" LOC = "F4" ; +#NET "debug<27>" LOC = "F5" ; +#NET "debug<28>" LOC = "C2" ; +#NET "debug<29>" LOC = "C1" ; +#NET "debug<30>" LOC = "F3" ; +#NET "debug<31>" LOC = "G3" ; + +#NET "debug_pb<2>" LOC = "Y2" ; +#NET "debug_pb<1>" LOC = "AA1" ; +#NET "debug_pb<0>" LOC = "N3" ; + +#NET "dip_sw<7>" LOC = "T3" ; +#NET "dip_sw<6>" LOC = "U3" ; +#NET "dip_sw<5>" LOC = "M3" ; +#NET "dip_sw<4>" LOC = "N4" ; +#NET "dip_sw<3>" LOC = "J3" ; +#NET "dip_sw<2>" LOC = "J4" ; +#NET "dip_sw<1>" LOC = "J6" ; +#NET "dip_sw<0>" LOC = "J7" ; + #NET "cgen_st_status" LOC = "D4" ; #NET "cgen_st_ld" LOC = "D1" ; #NET "cgen_st_refmon" LOC = "E1" ; @@ -122,20 +136,12 @@ #NET "cgen_ref_sel" LOC = "J1" ; #NET "debug_clk0" LOC = "L6" ; #NET "debug_clk1" LOC = "M5" ; -#NET "unnamed_net37" LOC = "B1" ; -#NET "unnamed_net36" LOC = "B22" ; -#NET "unnamed_net35" LOC = "D2" ; -#NET "unnamed_net34" LOC = "A21" ; #NET "GND" LOC = "V19" ; #NET "fpga_cfg_prog_b" LOC = "A2" ; #NET "fpga_cfg_done" LOC = "AB21" ; -#NET "unnamed_net45" LOC = "F7" ; #NET "fpga_cfg_din" LOC = "W17" ; #NET "fpga_cfg_cclk" LOC = "V17" ; #NET "fpga_cfg_init_b" LOC = "W15" ; -#NET "unnamed_net44" LOC = "V6" ; -#NET "unnamed_net43" LOC = "AA3" ; -#NET "unnamed_net42" LOC = "AB3" ; #NET "aux_sdi_codec" LOC = "F19" ; #NET "aux_sdo_codec" LOC = "F18" ; #NET "aux_sclk_codec" LOC = "D21" ; @@ -144,7 +150,9 @@ #NET "mosi_codec" LOC = "E19" ; #NET "miso_codec" LOC = "F21" ; #NET "sclk_codec" LOC = "E20" ; + #NET "RXSYNC" LOC = "F22" ; + #NET "DB11" LOC = "E22" ; #NET "DB10" LOC = "J19" ; #NET "DB09" LOC = "H20" ; @@ -169,6 +177,7 @@ #NET "DA02" LOC = "R22" ; #NET "DA01" LOC = "P22" ; #NET "DA00" LOC = "N17" ; + #NET "TX13" LOC = "P19" ; #NET "TX12" LOC = "R18" ; #NET "TX11" LOC = "U20" ; @@ -185,7 +194,9 @@ #NET "TX00" LOC = "AA22" ; #NET "TXSYNC" LOC = "U18" ; #NET "TXBLANK" LOC = "U19" ; + #NET "PPS_IN" LOC = "M17" ; + #NET "io_tx_00" LOC = "AB20" ; #NET "io_tx_01" LOC = "Y17" ; #NET "io_tx_02" LOC = "Y16" ; @@ -218,11 +229,16 @@ #NET "io_rx_13" LOC = "AA4" ; #NET "io_rx_14" LOC = "W5" ; #NET "io_rx_15" LOC = "Y4" ; + #NET "CLKOUT2_CODEC" LOC = "U12" ; #NET "CLKOUT1_CODEC" LOC = "V12" ; -NET "CLK_FPGA_P" LOC = "Y11" ; -NET "CLK_FPGA_N" LOC = "Y10" ; -NET "debug_led<2>" LOC = "T5" ; -NET "debug_led<1>" LOC = "R2" ; -NET "debug_led<0>" LOC = "R1" ; +## Unnamed, need to figure out what they do +#NET "unnamed_net37" LOC = "B1" ; +#NET "unnamed_net36" LOC = "B22" ; +#NET "unnamed_net35" LOC = "D2" ; +#NET "unnamed_net34" LOC = "A21" ; +#NET "unnamed_net45" LOC = "F7" ; +#NET "unnamed_net44" LOC = "V6" ; +#NET "unnamed_net43" LOC = "AA3" ; +#NET "unnamed_net42" LOC = "AB3" ; -- cgit v1.2.3 From a6872631b33fca08bb39fd8b1329146470369b19 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 14 Feb 2010 17:07:24 -0800 Subject: connect GPMC pins to debug bus --- usrp2/top/safe_u1e/safe_u1e.ucf | 156 +++++++++++++++++++++------------------- usrp2/top/safe_u1e/safe_u1e.v | 14 +++- 2 files changed, 94 insertions(+), 76 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf index 16265c203..14389f299 100644 --- a/usrp2/top/safe_u1e/safe_u1e.ucf +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -3,7 +3,52 @@ NET "CLK_FPGA_P" LOC = "Y11" ; NET "CLK_FPGA_N" LOC = "Y10" ; ## GPMC -#NET "EM_CLK" LOC = "F11" ; +NET "EM_CLK" LOC = "F11" ; + +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +#NET "EM_NCS6" LOC = "E17" ; +#NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE1" LOC = "D14" ; +#NET "EM_NBE0" LOC = "A13" ; +NET "EM_NWP" LOC = "F13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; + + +## Overo GPIO #NET "overo_gpio23" LOC = "B3" ; #NET "overo_gpio22" LOC = "A3" ; #NET "overo_gpio21" LOC = "D5" ; @@ -20,47 +65,12 @@ NET "CLK_FPGA_N" LOC = "Y10" ; #NET "overo_gpio128" LOC = "G8" ; #NET "overo_gpio0" LOC = "F9" ; #NET "overo_gpio127" LOC = "C8" ; + +## Overo UART #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; -#NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NWP" LOC = "F13" ; -#NET "EM_NBE1" LOC = "D14" ; -#NET "EM_NBE0" LOC = "A13" ; -#NET "EM_NWE" LOC = "B13" ; -#NET "EM_NOE" LOC = "A14" ; -#NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_D15" LOC = "D13" ; -#NET "EM_D14" LOC = "D15" ; -#NET "EM_D13" LOC = "C16" ; -#NET "EM_D12" LOC = "B20" ; -#NET "EM_D11" LOC = "A19" ; -#NET "EM_D10" LOC = "A17" ; -#NET "EM_D9" LOC = "E15" ; -#NET "EM_D8" LOC = "F15" ; -#NET "EM_D7" LOC = "E16" ; -#NET "EM_D6" LOC = "F16" ; -#NET "EM_D5" LOC = "B17" ; -#NET "EM_D4" LOC = "C17" ; -#NET "EM_D3" LOC = "B19" ; -#NET "EM_D2" LOC = "D19" ; -#NET "EM_D1" LOC = "C19" ; -#NET "EM_D0" LOC = "A20" ; + #NET "SYSEN" LOC = "C11" ; -#NET "EM_NCS6" LOC = "E17" ; -#NET "EM_NCS5" LOC = "E10" ; -#NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; -#NET "EM_A10" LOC = "C14" ; -#NET "EM_A9" LOC = "C10" ; -#NET "EM_A8" LOC = "C5" ; -#NET "EM_A7" LOC = "A18" ; -#NET "EM_A6" LOC = "A15" ; -#NET "EM_A5" LOC = "A12" ; -#NET "EM_A4" LOC = "A10" ; -#NET "EM_A3" LOC = "E7" ; -#NET "EM_A2" LOC = "A7" ; -#NET "EM_A1" LOC = "C15" ; #NET "db_scl" LOC = "U4" ; #NET "db_sda" LOC = "U5" ; @@ -83,38 +93,40 @@ NET "CLK_FPGA_N" LOC = "Y10" ; NET "debug_led<2>" LOC = "T5" ; NET "debug_led<1>" LOC = "R2" ; NET "debug_led<0>" LOC = "R1" ; -#NET "debug<0>" LOC = "P6" ; -#NET "debug<1>" LOC = "R6" ; -#NET "debug<2>" LOC = "P1" ; -#NET "debug<3>" LOC = "P2" ; -#NET "debug<4>" LOC = "N6" ; -#NET "debug<5>" LOC = "N5" ; -#NET "debug<6>" LOC = "N1" ; -#NET "debug<7>" LOC = "K2" ; -#NET "debug<8>" LOC = "K3" ; -#NET "debug<9>" LOC = "K6" ; -#NET "debug<10>" LOC = "L5" ; -#NET "debug<11>" LOC = "H2" ; -#NET "debug<12>" LOC = "K4" ; -#NET "debug<13>" LOC = "K5" ; -#NET "debug<14>" LOC = "G1" ; -#NET "debug<15>" LOC = "H1" ; -#NET "debug<16>" LOC = "H5" ; -#NET "debug<17>" LOC = "H6" ; -#NET "debug<18>" LOC = "E3" ; -#NET "debug<19>" LOC = "E4" ; -#NET "debug<20>" LOC = "G5" ; -#NET "debug<21>" LOC = "G6" ; -#NET "debug<22>" LOC = "F2" ; -#NET "debug<23>" LOC = "F1" ; -#NET "debug<24>" LOC = "H3" ; -#NET "debug<25>" LOC = "H4" ; -#NET "debug<26>" LOC = "F4" ; -#NET "debug<27>" LOC = "F5" ; -#NET "debug<28>" LOC = "C2" ; -#NET "debug<29>" LOC = "C1" ; -#NET "debug<30>" LOC = "F3" ; -#NET "debug<31>" LOC = "G3" ; +NET "debug<0>" LOC = "P6" ; +NET "debug<1>" LOC = "R6" ; +NET "debug<2>" LOC = "P1" ; +NET "debug<3>" LOC = "P2" ; +NET "debug<4>" LOC = "N6" ; +NET "debug<5>" LOC = "N5" ; +NET "debug<6>" LOC = "N1" ; +NET "debug<7>" LOC = "K2" ; +NET "debug<8>" LOC = "K3" ; +NET "debug<9>" LOC = "K6" ; +NET "debug<10>" LOC = "L5" ; +NET "debug<11>" LOC = "H2" ; +NET "debug<12>" LOC = "K4" ; +NET "debug<13>" LOC = "K5" ; +NET "debug<14>" LOC = "G1" ; +NET "debug<15>" LOC = "H1" ; +NET "debug<16>" LOC = "H5" ; +NET "debug<17>" LOC = "H6" ; +NET "debug<18>" LOC = "E3" ; +NET "debug<19>" LOC = "E4" ; +NET "debug<20>" LOC = "G5" ; +NET "debug<21>" LOC = "G6" ; +NET "debug<22>" LOC = "F2" ; +NET "debug<23>" LOC = "F1" ; +NET "debug<24>" LOC = "H3" ; +NET "debug<25>" LOC = "H4" ; +NET "debug<26>" LOC = "F4" ; +NET "debug<27>" LOC = "F5" ; +NET "debug<28>" LOC = "C2" ; +NET "debug<29>" LOC = "C1" ; +NET "debug<30>" LOC = "F3" ; +NET "debug<31>" LOC = "G3" ; +NET "debug_clk<0>" LOC = "L6" ; +NET "debug_clk<1>" LOC = "M5" ; #NET "debug_pb<2>" LOC = "Y2" ; #NET "debug_pb<1>" LOC = "AA1" ; @@ -134,8 +146,6 @@ NET "debug_led<0>" LOC = "R1" ; #NET "cgen_st_refmon" LOC = "E1" ; #NET "cgen_sync_b" LOC = "M1" ; #NET "cgen_ref_sel" LOC = "J1" ; -#NET "debug_clk0" LOC = "L6" ; -#NET "debug_clk1" LOC = "M5" ; #NET "GND" LOC = "V19" ; #NET "fpga_cfg_prog_b" LOC = "A2" ; #NET "fpga_cfg_done" LOC = "AB21" ; diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index 1b81bab5a..3f16d941c 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -4,7 +4,11 @@ module safe_u1e ( input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPMC + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, + input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE ); // FPGA-specific pins connections @@ -13,11 +17,15 @@ module safe_u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + // Debug circuitry reg [31:0] ctr; - always @(posedge clk_fpga) ctr <= ctr + 1; + assign debug_led = ctr[27:25]; - + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + endmodule // safe_u2plus -- cgit v1.2.3 From e091b4812ff4f7e6f959aabf48ac65bac5be86b7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 14 Feb 2010 17:23:43 -0800 Subject: reorg pin defs --- usrp2/top/safe_u1e/safe_u1e.ucf | 196 +++++++++++++++++++++------------------- 1 file changed, 102 insertions(+), 94 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf index 14389f299..cb6d6372e 100644 --- a/usrp2/top/safe_u1e/safe_u1e.ucf +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -49,27 +49,30 @@ NET "EM_NADV_ALE" LOC = "B15" ; ## Overo GPIO -#NET "overo_gpio23" LOC = "B3" ; -#NET "overo_gpio22" LOC = "A3" ; -#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio0" LOC = "F9" ; #NET "overo_gpio14" LOC = "C4" ; -#NET "overo_gpio176" LOC = "B4" ; +#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio22" LOC = "A3" ; +#NET "overo_gpio23" LOC = "B3" ; #NET "overo_gpio64" LOC = "A4" ; #NET "overo_gpio65" LOC = "F8" ; -#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_gpio128" LOC = "G8" ; +#NET "overo_gpio144" LOC = "A5" ; #NET "overo_gpio145" LOC = "C7" ; -#NET "overo_gpio163" LOC = "D7" ; #NET "overo_gpio146" LOC = "A6" ; -#NET "overo_gpio144" LOC = "A5" ; #NET "overo_gpio147" LOC = "B6" ; -#NET "overo_gpio128" LOC = "G8" ; -#NET "overo_gpio0" LOC = "F9" ; -#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_gpio163" LOC = "D7" ; +#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio176" LOC = "B4" ; ## Overo UART #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; + #NET "SYSEN" LOC = "C11" ; #NET "db_scl" LOC = "U4" ; @@ -82,12 +85,17 @@ NET "EM_NADV_ALE" LOC = "B15" ; #NET "db_miso_tx" LOC = "W1" ; #NET "db_mosi_tx" LOC = "R3" ; #NET "db_sen_tx" LOC = "T4" ; + +## Clock Gen #NET "cgen_miso" LOC = "U2" ; #NET "cgen_mosi" LOC = "V1" ; #NET "cgen_sclk" LOC = "R5" ; #NET "cgen_sen_b" LOC = "T1" ; -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; ## Debug pins NET "debug_led<2>" LOC = "T5" ; @@ -141,17 +149,7 @@ NET "debug_clk<1>" LOC = "M5" ; #NET "dip_sw<1>" LOC = "J6" ; #NET "dip_sw<0>" LOC = "J7" ; -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; -#NET "GND" LOC = "V19" ; -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "AB21" ; -#NET "fpga_cfg_din" LOC = "W17" ; -#NET "fpga_cfg_cclk" LOC = "V17" ; -#NET "fpga_cfg_init_b" LOC = "W15" ; +## AD9862 Interface #NET "aux_sdi_codec" LOC = "F19" ; #NET "aux_sdo_codec" LOC = "F18" ; #NET "aux_sclk_codec" LOC = "D21" ; @@ -163,86 +161,94 @@ NET "debug_clk<1>" LOC = "M5" ; #NET "RXSYNC" LOC = "F22" ; -#NET "DB11" LOC = "E22" ; -#NET "DB10" LOC = "J19" ; -#NET "DB09" LOC = "H20" ; -#NET "DB08" LOC = "G19" ; -#NET "DB07" LOC = "F20" ; -#NET "DB06" LOC = "K16" ; -#NET "DB05" LOC = "J17" ; -#NET "DB04" LOC = "H22" ; -#NET "DB03" LOC = "G22" ; -#NET "DB02" LOC = "H17" ; -#NET "DB01" LOC = "H18" ; -#NET "DB00" LOC = "K20" ; -#NET "DA11" LOC = "J20" ; -#NET "DA10" LOC = "K19" ; -#NET "DA09" LOC = "K18" ; -#NET "DA08" LOC = "L22" ; -#NET "DA07" LOC = "K22" ; -#NET "DA06" LOC = "N22" ; -#NET "DA05" LOC = "M22" ; -#NET "DA04" LOC = "N20" ; -#NET "DA03" LOC = "N19" ; -#NET "DA02" LOC = "R22" ; -#NET "DA01" LOC = "P22" ; -#NET "DA00" LOC = "N17" ; - -#NET "TX13" LOC = "P19" ; -#NET "TX12" LOC = "R18" ; -#NET "TX11" LOC = "U20" ; -#NET "TX10" LOC = "T20" ; -#NET "TX09" LOC = "R19" ; -#NET "TX08" LOC = "R20" ; -#NET "TX07" LOC = "W22" ; -#NET "TX06" LOC = "Y22" ; -#NET "TX05" LOC = "T18" ; -#NET "TX04" LOC = "T17" ; -#NET "TX03" LOC = "W19" ; -#NET "TX02" LOC = "V20" ; -#NET "TX01" LOC = "Y21" ; -#NET "TX00" LOC = "AA22" ; +#NET "DB<11>" LOC = "E22" ; +#NET "DB<10>" LOC = "J19" ; +#NET "DB<9>" LOC = "H20" ; +#NET "DB<8>" LOC = "G19" ; +#NET "DB<7>" LOC = "F20" ; +#NET "DB<6>" LOC = "K16" ; +#NET "DB<5>" LOC = "J17" ; +#NET "DB<4>" LOC = "H22" ; +#NET "DB<3>" LOC = "G22" ; +#NET "DB<2>" LOC = "H17" ; +#NET "DB<1>" LOC = "H18" ; +#NET "DB<0>" LOC = "K20" ; +#NET "DA<11>" LOC = "J20" ; +#NET "DA<10>" LOC = "K19" ; +#NET "DA<9>" LOC = "K18" ; +#NET "DA<8>" LOC = "L22" ; +#NET "DA<7>" LOC = "K22" ; +#NET "DA<6>" LOC = "N22" ; +#NET "DA<5>" LOC = "M22" ; +#NET "DA<4>" LOC = "N20" ; +#NET "DA<3>" LOC = "N19" ; +#NET "DA<2>" LOC = "R22" ; +#NET "DA<1>" LOC = "P22" ; +#NET "DA<0>" LOC = "N17" ; + +#NET "TX<13>" LOC = "P19" ; +#NET "TX<12>" LOC = "R18" ; +#NET "TX<11>" LOC = "U20" ; +#NET "TX<10>" LOC = "T20" ; +#NET "TX<9>" LOC = "R19" ; +#NET "TX<8>" LOC = "R20" ; +#NET "TX<7>" LOC = "W22" ; +#NET "TX<6>" LOC = "Y22" ; +#NET "TX<5>" LOC = "T18" ; +#NET "TX<4>" LOC = "T17" ; +#NET "TX<3>" LOC = "W19" ; +#NET "TX<2>" LOC = "V20" ; +#NET "TX<1>" LOC = "Y21" ; +#NET "TX<0>" LOC = "AA22" ; #NET "TXSYNC" LOC = "U18" ; #NET "TXBLANK" LOC = "U19" ; #NET "PPS_IN" LOC = "M17" ; -#NET "io_tx_00" LOC = "AB20" ; -#NET "io_tx_01" LOC = "Y17" ; -#NET "io_tx_02" LOC = "Y16" ; -#NET "io_tx_03" LOC = "U16" ; -#NET "io_tx_04" LOC = "V16" ; -#NET "io_tx_05" LOC = "AB19" ; -#NET "io_tx_06" LOC = "AA19" ; -#NET "io_tx_07" LOC = "U14" ; -#NET "io_tx_08" LOC = "U15" ; -#NET "io_tx_09" LOC = "AB17" ; -#NET "io_tx_10" LOC = "AB18" ; -#NET "io_tx_11" LOC = "Y13" ; -#NET "io_tx_12" LOC = "W14" ; -#NET "io_tx_13" LOC = "U13" ; -#NET "io_tx_14" LOC = "AA15" ; -#NET "io_tx_15" LOC = "AB14" ; -#NET "io_rx_00" LOC = "Y8" ; -#NET "io_rx_01" LOC = "Y9" ; -#NET "io_rx_02" LOC = "V7" ; -#NET "io_rx_03" LOC = "U8" ; -#NET "io_rx_04" LOC = "V10" ; -#NET "io_rx_05" LOC = "U9" ; -#NET "io_rx_06" LOC = "AB7" ; -#NET "io_rx_07" LOC = "AA8" ; -#NET "io_rx_08" LOC = "W8" ; -#NET "io_rx_09" LOC = "V8" ; -#NET "io_rx_10" LOC = "AB5" ; -#NET "io_rx_11" LOC = "AB6" ; -#NET "io_rx_12" LOC = "AB4" ; -#NET "io_rx_13" LOC = "AA4" ; -#NET "io_rx_14" LOC = "W5" ; -#NET "io_rx_15" LOC = "Y4" ; +#NET "io_tx<0>" LOC = "AB20" ; +#NET "io_tx<1>" LOC = "Y17" ; +#NET "io_tx<2>" LOC = "Y16" ; +#NET "io_tx<3>" LOC = "U16" ; +#NET "io_tx<4>" LOC = "V16" ; +#NET "io_tx<5>" LOC = "AB19" ; +#NET "io_tx<6>" LOC = "AA19" ; +#NET "io_tx<7>" LOC = "U14" ; +#NET "io_tx<8>" LOC = "U15" ; +#NET "io_tx<9>" LOC = "AB17" ; +#NET "io_tx<10>" LOC = "AB18" ; +#NET "io_tx<11>" LOC = "Y13" ; +#NET "io_tx<12>" LOC = "W14" ; +#NET "io_tx<13>" LOC = "U13" ; +#NET "io_tx<14>" LOC = "AA15" ; +#NET "io_tx<15>" LOC = "AB14" ; + +#NET "io_rx<0>" LOC = "Y8" ; +#NET "io_rx<1>" LOC = "Y9" ; +#NET "io_rx<2>" LOC = "V7" ; +#NET "io_rx<3>" LOC = "U8" ; +#NET "io_rx<4>" LOC = "V10" ; +#NET "io_rx<5>" LOC = "U9" ; +#NET "io_rx<6>" LOC = "AB7" ; +#NET "io_rx<7>" LOC = "AA8" ; +#NET "io_rx<8>" LOC = "W8" ; +#NET "io_rx<9>" LOC = "V8" ; +#NET "io_rx<10>" LOC = "AB5" ; +#NET "io_rx<11>" LOC = "AB6" ; +#NET "io_rx<12>" LOC = "AB4" ; +#NET "io_rx<13>" LOC = "AA4" ; +#NET "io_rx<14>" LOC = "W5" ; +#NET "io_rx<15>" LOC = "Y4" ; #NET "CLKOUT2_CODEC" LOC = "U12" ; #NET "CLKOUT1_CODEC" LOC = "V12" ; +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + ## Unnamed, need to figure out what they do #NET "unnamed_net37" LOC = "B1" ; #NET "unnamed_net36" LOC = "B22" ; @@ -252,3 +258,5 @@ NET "debug_clk<1>" LOC = "M5" ; #NET "unnamed_net44" LOC = "V6" ; #NET "unnamed_net43" LOC = "AA3" ; #NET "unnamed_net42" LOC = "AB3" ; + +#NET "GND" LOC = "V19" ; -- cgit v1.2.3 From 034eeacfe8d35b0e9733dd9183f1a9dbed78f347 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 10:24:18 -0800 Subject: basic read support for the GPMC, responds with 16'hBEEF --- usrp2/top/safe_u1e/safe_u1e.v | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index 3f16d941c..ddd203cf9 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -7,7 +7,7 @@ module safe_u1e output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, // GPMC - input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE ); @@ -27,5 +27,11 @@ module safe_u1e assign debug_clk = { EM_CLK, clk_fpga }; assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; - + + wire EM_output_enable = (~EM_NOE & ~EM_NCS4); + wire [15:0] EM_D_out = 16'hBEEF; + wire [15:0] EM_D_in = EM_D; + + assign EM_D = EM_output_enable ? EM_D_out : 16'bz; + endmodule // safe_u2plus -- cgit v1.2.3 From 8e76952016272c9898776b6beb7a69f476d4707e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 16:21:00 -0800 Subject: block ram interface to GPMC --- usrp2/top/safe_u1e/safe_u1e.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index ddd203cf9..dee9c6067 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -29,9 +29,13 @@ module safe_u1e { EM_D } }; wire EM_output_enable = (~EM_NOE & ~EM_NCS4); - wire [15:0] EM_D_out = 16'hBEEF; - wire [15:0] EM_D_in = EM_D; + wire [15:0] EM_D_out; assign EM_D = EM_output_enable ? EM_D_out : 16'bz; + + ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port + (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), + .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + endmodule // safe_u2plus -- cgit v1.2.3 From c1ddc5c082c053eaa46c8bc87064d3e3e56b0d9e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 16:29:44 -0800 Subject: copied over from safe_u1e --- usrp2/top/u1e/.gitignore | 4 + usrp2/top/u1e/Makefile | 246 ++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/u1e.ucf | 262 +++++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/u1e.v | 41 ++++++++ 4 files changed, 553 insertions(+) create mode 100644 usrp2/top/u1e/.gitignore create mode 100644 usrp2/top/u1e/Makefile create mode 100644 usrp2/top/u1e/u1e.ucf create mode 100644 usrp2/top/u1e/u1e.v diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore new file mode 100644 index 000000000..f8b57ea21 --- /dev/null +++ b/usrp2/top/u1e/.gitignore @@ -0,0 +1,4 @@ +*~ +build +*.log +*.cmd diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile new file mode 100644 index 000000000..e9c101226 --- /dev/null +++ b/usrp2/top/u1e/Makefile @@ -0,0 +1,246 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u1e +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u1e/u1e.ucf \ +top/u1e/u1e.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf new file mode 100644 index 000000000..cb6d6372e --- /dev/null +++ b/usrp2/top/u1e/u1e.ucf @@ -0,0 +1,262 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +NET "EM_CLK" LOC = "F11" ; + +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +#NET "EM_NCS6" LOC = "E17" ; +#NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE1" LOC = "D14" ; +#NET "EM_NBE0" LOC = "A13" ; +NET "EM_NWP" LOC = "F13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; + + +## Overo GPIO +#NET "overo_gpio0" LOC = "F9" ; +#NET "overo_gpio14" LOC = "C4" ; +#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio22" LOC = "A3" ; +#NET "overo_gpio23" LOC = "B3" ; +#NET "overo_gpio64" LOC = "A4" ; +#NET "overo_gpio65" LOC = "F8" ; +#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_gpio128" LOC = "G8" ; +#NET "overo_gpio144" LOC = "A5" ; +#NET "overo_gpio145" LOC = "C7" ; +#NET "overo_gpio146" LOC = "A6" ; +#NET "overo_gpio147" LOC = "B6" ; +#NET "overo_gpio163" LOC = "D7" ; +#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio176" LOC = "B4" ; + +## Overo UART +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; + +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; + +#NET "SYSEN" LOC = "C11" ; + +#NET "db_scl" LOC = "U4" ; +#NET "db_sda" LOC = "U5" ; +#NET "db_sclk_rx" LOC = "W3" ; +#NET "db_miso_rx" LOC = "W2" ; +#NET "db_mosi_rx" LOC = "V4" ; +#NET "db_sen_rx" LOC = "V3" ; +#NET "db_sclk_tx" LOC = "Y1" ; +#NET "db_miso_tx" LOC = "W1" ; +#NET "db_mosi_tx" LOC = "R3" ; +#NET "db_sen_tx" LOC = "T4" ; + +## Clock Gen +#NET "cgen_miso" LOC = "U2" ; +#NET "cgen_mosi" LOC = "V1" ; +#NET "cgen_sclk" LOC = "R5" ; +#NET "cgen_sen_b" LOC = "T1" ; +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; + +## Debug pins +NET "debug_led<2>" LOC = "T5" ; +NET "debug_led<1>" LOC = "R2" ; +NET "debug_led<0>" LOC = "R1" ; +NET "debug<0>" LOC = "P6" ; +NET "debug<1>" LOC = "R6" ; +NET "debug<2>" LOC = "P1" ; +NET "debug<3>" LOC = "P2" ; +NET "debug<4>" LOC = "N6" ; +NET "debug<5>" LOC = "N5" ; +NET "debug<6>" LOC = "N1" ; +NET "debug<7>" LOC = "K2" ; +NET "debug<8>" LOC = "K3" ; +NET "debug<9>" LOC = "K6" ; +NET "debug<10>" LOC = "L5" ; +NET "debug<11>" LOC = "H2" ; +NET "debug<12>" LOC = "K4" ; +NET "debug<13>" LOC = "K5" ; +NET "debug<14>" LOC = "G1" ; +NET "debug<15>" LOC = "H1" ; +NET "debug<16>" LOC = "H5" ; +NET "debug<17>" LOC = "H6" ; +NET "debug<18>" LOC = "E3" ; +NET "debug<19>" LOC = "E4" ; +NET "debug<20>" LOC = "G5" ; +NET "debug<21>" LOC = "G6" ; +NET "debug<22>" LOC = "F2" ; +NET "debug<23>" LOC = "F1" ; +NET "debug<24>" LOC = "H3" ; +NET "debug<25>" LOC = "H4" ; +NET "debug<26>" LOC = "F4" ; +NET "debug<27>" LOC = "F5" ; +NET "debug<28>" LOC = "C2" ; +NET "debug<29>" LOC = "C1" ; +NET "debug<30>" LOC = "F3" ; +NET "debug<31>" LOC = "G3" ; +NET "debug_clk<0>" LOC = "L6" ; +NET "debug_clk<1>" LOC = "M5" ; + +#NET "debug_pb<2>" LOC = "Y2" ; +#NET "debug_pb<1>" LOC = "AA1" ; +#NET "debug_pb<0>" LOC = "N3" ; + +#NET "dip_sw<7>" LOC = "T3" ; +#NET "dip_sw<6>" LOC = "U3" ; +#NET "dip_sw<5>" LOC = "M3" ; +#NET "dip_sw<4>" LOC = "N4" ; +#NET "dip_sw<3>" LOC = "J3" ; +#NET "dip_sw<2>" LOC = "J4" ; +#NET "dip_sw<1>" LOC = "J6" ; +#NET "dip_sw<0>" LOC = "J7" ; + +## AD9862 Interface +#NET "aux_sdi_codec" LOC = "F19" ; +#NET "aux_sdo_codec" LOC = "F18" ; +#NET "aux_sclk_codec" LOC = "D21" ; +#NET "reset_codec" LOC = "D22" ; +#NET "sen_codec" LOC = "D20" ; +#NET "mosi_codec" LOC = "E19" ; +#NET "miso_codec" LOC = "F21" ; +#NET "sclk_codec" LOC = "E20" ; + +#NET "RXSYNC" LOC = "F22" ; + +#NET "DB<11>" LOC = "E22" ; +#NET "DB<10>" LOC = "J19" ; +#NET "DB<9>" LOC = "H20" ; +#NET "DB<8>" LOC = "G19" ; +#NET "DB<7>" LOC = "F20" ; +#NET "DB<6>" LOC = "K16" ; +#NET "DB<5>" LOC = "J17" ; +#NET "DB<4>" LOC = "H22" ; +#NET "DB<3>" LOC = "G22" ; +#NET "DB<2>" LOC = "H17" ; +#NET "DB<1>" LOC = "H18" ; +#NET "DB<0>" LOC = "K20" ; +#NET "DA<11>" LOC = "J20" ; +#NET "DA<10>" LOC = "K19" ; +#NET "DA<9>" LOC = "K18" ; +#NET "DA<8>" LOC = "L22" ; +#NET "DA<7>" LOC = "K22" ; +#NET "DA<6>" LOC = "N22" ; +#NET "DA<5>" LOC = "M22" ; +#NET "DA<4>" LOC = "N20" ; +#NET "DA<3>" LOC = "N19" ; +#NET "DA<2>" LOC = "R22" ; +#NET "DA<1>" LOC = "P22" ; +#NET "DA<0>" LOC = "N17" ; + +#NET "TX<13>" LOC = "P19" ; +#NET "TX<12>" LOC = "R18" ; +#NET "TX<11>" LOC = "U20" ; +#NET "TX<10>" LOC = "T20" ; +#NET "TX<9>" LOC = "R19" ; +#NET "TX<8>" LOC = "R20" ; +#NET "TX<7>" LOC = "W22" ; +#NET "TX<6>" LOC = "Y22" ; +#NET "TX<5>" LOC = "T18" ; +#NET "TX<4>" LOC = "T17" ; +#NET "TX<3>" LOC = "W19" ; +#NET "TX<2>" LOC = "V20" ; +#NET "TX<1>" LOC = "Y21" ; +#NET "TX<0>" LOC = "AA22" ; +#NET "TXSYNC" LOC = "U18" ; +#NET "TXBLANK" LOC = "U19" ; + +#NET "PPS_IN" LOC = "M17" ; + +#NET "io_tx<0>" LOC = "AB20" ; +#NET "io_tx<1>" LOC = "Y17" ; +#NET "io_tx<2>" LOC = "Y16" ; +#NET "io_tx<3>" LOC = "U16" ; +#NET "io_tx<4>" LOC = "V16" ; +#NET "io_tx<5>" LOC = "AB19" ; +#NET "io_tx<6>" LOC = "AA19" ; +#NET "io_tx<7>" LOC = "U14" ; +#NET "io_tx<8>" LOC = "U15" ; +#NET "io_tx<9>" LOC = "AB17" ; +#NET "io_tx<10>" LOC = "AB18" ; +#NET "io_tx<11>" LOC = "Y13" ; +#NET "io_tx<12>" LOC = "W14" ; +#NET "io_tx<13>" LOC = "U13" ; +#NET "io_tx<14>" LOC = "AA15" ; +#NET "io_tx<15>" LOC = "AB14" ; + +#NET "io_rx<0>" LOC = "Y8" ; +#NET "io_rx<1>" LOC = "Y9" ; +#NET "io_rx<2>" LOC = "V7" ; +#NET "io_rx<3>" LOC = "U8" ; +#NET "io_rx<4>" LOC = "V10" ; +#NET "io_rx<5>" LOC = "U9" ; +#NET "io_rx<6>" LOC = "AB7" ; +#NET "io_rx<7>" LOC = "AA8" ; +#NET "io_rx<8>" LOC = "W8" ; +#NET "io_rx<9>" LOC = "V8" ; +#NET "io_rx<10>" LOC = "AB5" ; +#NET "io_rx<11>" LOC = "AB6" ; +#NET "io_rx<12>" LOC = "AB4" ; +#NET "io_rx<13>" LOC = "AA4" ; +#NET "io_rx<14>" LOC = "W5" ; +#NET "io_rx<15>" LOC = "Y4" ; + +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unnamed, need to figure out what they do +#NET "unnamed_net37" LOC = "B1" ; +#NET "unnamed_net36" LOC = "B22" ; +#NET "unnamed_net35" LOC = "D2" ; +#NET "unnamed_net34" LOC = "A21" ; +#NET "unnamed_net45" LOC = "F7" ; +#NET "unnamed_net44" LOC = "V6" ; +#NET "unnamed_net43" LOC = "AA3" ; +#NET "unnamed_net42" LOC = "AB3" ; + +#NET "GND" LOC = "V19" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v new file mode 100644 index 000000000..e28a6a582 --- /dev/null +++ b/usrp2/top/u1e/u1e.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, + input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE + ); + + // FPGA-specific pins connections + wire clk_fpga; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + // Debug circuitry + reg [31:0] ctr; + always @(posedge clk_fpga) + ctr <= ctr + 1; + + + assign debug_led = ctr[27:25]; + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + wire EM_output_enable = (~EM_NOE & ~EM_NCS4); + wire [15:0] EM_D_out; + + assign EM_D = EM_output_enable ? EM_D_out : 16'bz; + + ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port + (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), + .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + + +endmodule // u2plus -- cgit v1.2.3 From b115e4d7661d64c6d20f0421908622b56a91e950 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 18:47:22 -0800 Subject: first cut at gpmc <-> wb bridge, split u1e into core, top, and tb --- .gitignore | 1 + usrp2/gpmc/gpmc.v | 66 ++++++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 3 ++- usrp2/top/u1e/tb_u1e.v | 25 ++++++++++++++++++ usrp2/top/u1e/u1e.ucf | 14 +++++----- usrp2/top/u1e/u1e.v | 33 ++++++------------------ usrp2/top/u1e/u1e_core.v | 52 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 160 insertions(+), 34 deletions(-) create mode 100644 .gitignore create mode 100644 usrp2/gpmc/gpmc.v create mode 100644 usrp2/top/u1e/tb_u1e.v create mode 100644 usrp2/top/u1e/u1e_core.v diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..b25c15b81 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +*~ diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v new file mode 100644 index 000000000..96ee139fd --- /dev/null +++ b/usrp2/gpmc/gpmc.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module gpmc + (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + input wb_clk, input wb_rst, + output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_ram; + reg [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; + + // CS4 is RAM_2PORT for high-speed data + ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port + (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), + .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + + // CS6 is Control, Wishbone bus bridge (wb master) + // Sync version + reg [1:0] cs_del, we_del, oe_del; + + // Synchronize the async control signals + always @(posedge wb_clk) + begin + cs_del <= { cs_del[0], EM_NCS6 }; + we_del <= { we_del[0], EM_NWE }; + oe_del <= { oe_del[0], EM_NOE }; + end + + always @(posedge wb_clk) + if(cs_del == 2'b10) // Falling Edge + wb_adr_o <= { EM_A, 1'b0 }; + + always @(posedge wb_clk) + if(we_del == 2'b10) // Falling Edge + begin + wb_dat_mosi <= EM_D; + wb_sel_o <= ~EM_NBE; + end + + always @(posedge wb_clk) + if(wb_ack_i) + EM_D_wb <= wb_dat_miso; + + // stb, oe_del, we_del + assign wb_cyc_o = wb_stb_o; + + always @(posedge wb_clk) + if( ~cs_del[0] & (we_del == 2'b10) ) + wb_we_o <= 1; + else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... + wb_we_o <= 0; + + always @(posedge wb_clk) + if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) + wb_stb_o <= 1; + else if(wb_ack_i) + wb_stb_o <= 0; + +endmodule // gpmc diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index e9c101226..cdbdf995e 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -174,7 +174,8 @@ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ -top/u2_core/u2_core.v \ +gpmc/gpmc.v \ +top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/u1e.v diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v new file mode 100644 index 000000000..6e0c60e17 --- /dev/null +++ b/usrp2/top/u1e/tb_u1e.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0; + always #100 clk_fpga = ~clk_fpga; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // u1e diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index cb6d6372e..3b524a6ea 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -3,8 +3,6 @@ NET "CLK_FPGA_P" LOC = "Y11" ; NET "CLK_FPGA_N" LOC = "Y10" ; ## GPMC -NET "EM_CLK" LOC = "F11" ; - NET "EM_D<15>" LOC = "D13" ; NET "EM_D<14>" LOC = "D15" ; NET "EM_D<13>" LOC = "C16" ; @@ -33,20 +31,20 @@ NET "EM_A<3>" LOC = "E7" ; NET "EM_A<2>" LOC = "A7" ; NET "EM_A<1>" LOC = "C15" ; -#NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS6" LOC = "E17" ; #NET "EM_NCS5" LOC = "E10" ; NET "EM_NCS4" LOC = "E6" ; #NET "EM_NCS1" LOC = "D18" ; #NET "EM_NCS0" LOC = "D17" ; +NET "EM_CLK" LOC = "F11" ; NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE1" LOC = "D14" ; -#NET "EM_NBE0" LOC = "A13" ; -NET "EM_NWP" LOC = "F13" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; NET "EM_NWE" LOC = "B13" ; NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; - +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; ## Overo GPIO #NET "overo_gpio0" LOC = "F9" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index e28a6a582..8832d6e11 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -2,13 +2,12 @@ ////////////////////////////////////////////////////////////////////////////////// module u1e - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE ); // FPGA-specific pins connections @@ -17,25 +16,9 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - // Debug circuitry - reg [31:0] ctr; - always @(posedge clk_fpga) - ctr <= ctr + 1; - - - assign debug_led = ctr[27:25]; - assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, - { EM_D } }; - - wire EM_output_enable = (~EM_NOE & ~EM_NCS4); - wire [15:0] EM_D_out; - - assign EM_D = EM_output_enable ? EM_D_out : 16'bz; - - ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), - .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - -endmodule // u2plus +endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v new file mode 100644 index 000000000..2481549b2 --- /dev/null +++ b/usrp2/top/u1e/u1e_core.v @@ -0,0 +1,52 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e_core + (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE + ); + + // Debug circuitry + reg [31:0] ctr; + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign debug_led = ctr[27:25]; + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + wire wb_clk, wb_rst; + wire wb_cyc, wb_stb, wb_we, wb_ack; + wire [1:0] wb_sel; + wire [10:0] wb_adr; + wire [15:0] wb_dat_mosi, wb_dat_miso; + + gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), .wb_we_o(wb_we), + .wb_ack_i(wb_ack)); + + assign wb_clk = clk_fpga; + reg [15:0] reg_fast, reg_slow; + + localparam [10:0] WB_ADR_REG_FAST = 36; + localparam [10:0] WB_ADR_REG_SLOW = 38; + + always @(posedge wb_clk) + if(wb_cyc & wb_stb & wb_we & (wb_adr == WB_ADR_REG_FAST)) + reg_fast <= wb_dat_mosi; + + assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx; + + assign wb_ack = wb_stb & wb_cyc; + + +endmodule // u2plus -- cgit v1.2.3 From d4649caee02a1c76802dc4f8d7d76bb31b14ce09 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 22:49:02 -0800 Subject: wishbone bridge now with minimal functionality. Need to check timing and handle wait states. --- usrp2/gpmc/gpmc.v | 4 +-- usrp2/models/gpmc_model.v | 70 +++++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/.gitignore | 2 ++ usrp2/top/u1e/README | 4 +++ usrp2/top/u1e/cmdfile | 19 +++++++++++++ usrp2/top/u1e/make.sim | 7 +++++ usrp2/top/u1e/tb_u1e.v | 17 +++++++++--- usrp2/top/u1e/u1e_core.v | 9 +++--- 8 files changed, 121 insertions(+), 11 deletions(-) create mode 100644 usrp2/models/gpmc_model.v create mode 100644 usrp2/top/u1e/README create mode 100644 usrp2/top/u1e/cmdfile create mode 100644 usrp2/top/u1e/make.sim diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 96ee139fd..1963af6e6 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -18,8 +18,8 @@ module gpmc // CS4 is RAM_2PORT for high-speed data ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), - .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + (.clka(wb_clk), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), + .clkb(wb_clk), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); // CS6 is Control, Wishbone bus bridge (wb master) // Sync version diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v new file mode 100644 index 000000000..ce3acaacf --- /dev/null +++ b/usrp2/models/gpmc_model.v @@ -0,0 +1,70 @@ + + +module gpmc_model + (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + assign EM_CLK = 0; + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input [10:0] addr; + input [15:0] data; + begin + #2; + EM_A <= addr[10:1]; + EM_D_int <= data; + #4; + EM_NCS6 <= 0; + #5; + EM_NWE <= 0; + #41; + EM_NWE <= 1; + EM_NCS6 <= 1; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + end + endtask // GPMC_Write + + task GPMC_Read; + input [10:0] addr; + begin + #2; + EM_A <= addr[10:1]; + #4; + EM_NCS6 <= 0; + #5; + EM_NOE <= 0; + #41; + EM_NOE <= 1; + EM_NCS6 <= 1; + EM_A <= 10'bz; + $display("Data Read from GPMC: %X",EM_D); + end + endtask // GPMC_Read + + initial + begin + #1000; + GPMC_Write(36,16'hBEEF); + #1000; + GPMC_Read(36); + #1000; + $finish; + end + +endmodule // gpmc_model diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore index f8b57ea21..8d872713e 100644 --- a/usrp2/top/u1e/.gitignore +++ b/usrp2/top/u1e/.gitignore @@ -2,3 +2,5 @@ build *.log *.cmd +tb_u1e +*.lxt diff --git a/usrp2/top/u1e/README b/usrp2/top/u1e/README new file mode 100644 index 000000000..14c7a4955 --- /dev/null +++ b/usrp2/top/u1e/README @@ -0,0 +1,4 @@ + +make clean +make sim +./tb_u1e -lxt2 diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..5e4db5c65 --- /dev/null +++ b/usrp2/top/u1e/cmdfile @@ -0,0 +1,19 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models + +# Open Cores +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog + diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim new file mode 100644 index 000000000..1c163884c --- /dev/null +++ b/usrp2/top/u1e/make.sim @@ -0,0 +1,7 @@ +all: sim + +sim: + iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e + +clean: + rm -f tb_u1e *.vcd *.lxt a.out diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 6e0c60e17..85d2b49f0 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -6,8 +6,12 @@ module tb_u1e(); wire [2:0] debug_led; wire [31:0] debug; wire [1:0] debug_clk; - - + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + // GPMC wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; wire [15:0] EM_D; @@ -15,11 +19,16 @@ module tb_u1e(); wire [1:0] EM_NBE; reg clk_fpga = 0; - always #100 clk_fpga = ~clk_fpga; + always #15.625 clk_fpga = ~clk_fpga; u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model gpmc_model + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); -endmodule // u1e +endmodule // tb_u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 2481549b2..b0edbb9b6 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -10,7 +10,7 @@ module u1e_core ); // Debug circuitry - reg [31:0] ctr; + reg [31:0] ctr=0; always @(posedge clk_fpga) ctr <= ctr + 1; @@ -37,7 +37,7 @@ module u1e_core assign wb_clk = clk_fpga; reg [15:0] reg_fast, reg_slow; - localparam [10:0] WB_ADR_REG_FAST = 36; + localparam [10:0] WB_ADR_REG_FAST = 11'd36; localparam [10:0] WB_ADR_REG_SLOW = 38; always @(posedge wb_clk) @@ -47,6 +47,5 @@ module u1e_core assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx; assign wb_ack = wb_stb & wb_cyc; - - -endmodule // u2plus + +endmodule // u1e_core -- cgit v1.2.3 From 1912ff60acd490a24204a7596e373e9aef9276cd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 17 Feb 2010 15:00:41 -0800 Subject: speed up the presentation of registered wb data to the gpmc --- usrp2/gpmc/gpmc.v | 7 +++++-- usrp2/models/gpmc_model.v | 26 +++++++++++++++----------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 1963af6e6..56f879abc 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -12,7 +12,7 @@ module gpmc wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); wire [15:0] EM_D_ram; - reg [15:0] EM_D_wb; + wire [15:0] EM_D_wb; assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; @@ -44,10 +44,13 @@ module gpmc wb_sel_o <= ~EM_NBE; end + reg [15:0] EM_D_wb_reg; always @(posedge wb_clk) if(wb_ack_i) - EM_D_wb <= wb_dat_miso; + EM_D_wb_reg <= wb_dat_miso; + assign EM_D_wb = wb_ack_i ? wb_dat_miso : EM_D_wb_reg; + // stb, oe_del, we_del assign wb_cyc_o = wb_stb_o; diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v index ce3acaacf..38dde1fa5 100644 --- a/usrp2/models/gpmc_model.v +++ b/usrp2/models/gpmc_model.v @@ -25,16 +25,18 @@ module gpmc_model input [10:0] addr; input [15:0] data; begin - #2; + #2.3; EM_A <= addr[10:1]; EM_D_int <= data; - #4; + #2.01; EM_NCS6 <= 0; - #5; + #14; EM_NWE <= 0; - #41; - EM_NWE <= 1; + #77.5; EM_NCS6 <= 1; + //#1.5; + EM_NWE <= 1; + #6; EM_A <= 10'bz; EM_D_int <= 16'bz; end @@ -43,17 +45,19 @@ module gpmc_model task GPMC_Read; input [10:0] addr; begin - #2; + #1.3; EM_A <= addr[10:1]; - #4; + #3; EM_NCS6 <= 0; - #5; + #14; EM_NOE <= 0; - #41; - EM_NOE <= 1; + #77.5; EM_NCS6 <= 1; - EM_A <= 10'bz; + //#1.5; $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254; + EM_A <= 10'bz; end endtask // GPMC_Read -- cgit v1.2.3 From e56b4767451dcdca41512faba634b812e44d2e1d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 18:03:26 -0800 Subject: Fixed paths to help icarus find opencores and xilinx models. Added Xilinx global set and reset module. --- usrp2/top/u1e/cmdfile | 9 +++++---- usrp2/top/u1e/tb_u1e.v | 2 ++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile index 5e4db5c65..291c723b8 100644 --- a/usrp2/top/u1e/cmdfile +++ b/usrp2/top/u1e/cmdfile @@ -10,10 +10,11 @@ # Models -y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims # Open Cores --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 85d2b49f0..319645af6 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -7,6 +7,8 @@ module tb_u1e(); wire [31:0] debug; wire [1:0] debug_clk; + xlnx_glbl glbl (.GSR(),.GTS()); + initial begin $dumpfile("tb_u1e.lxt"); $dumpvars(0,tb_u1e); -- cgit v1.2.3 From 7c31f8d25d563b9f2795914f8ea0f3e49b214c56 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 18:04:24 -0800 Subject: allow default uart clock divider --- usrp2/control_lib/simple_uart.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/usrp2/control_lib/simple_uart.v b/usrp2/control_lib/simple_uart.v index 22f0e70a2..0dd58b5f5 100644 --- a/usrp2/control_lib/simple_uart.v +++ b/usrp2/control_lib/simple_uart.v @@ -1,11 +1,12 @@ module simple_uart #(parameter TXDEPTH = 1, - parameter RXDEPTH = 1) - (input clk_i, input rst_i, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, - output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); + parameter RXDEPTH = 1, + parameter CLKDIV_DEFAULT = 16'd0) + (input clk_i, input rst_i, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, + output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); // Register Map localparam SUART_CLKDIV = 0; @@ -30,7 +31,7 @@ module simple_uart always @(posedge clk_i) if (rst_i) - clkdiv <= 0; + clkdiv <= CLKDIV_DEFAULT; else if (wb_wr) case(adr_i) SUART_CLKDIV : clkdiv <= dat_i[15:0]; -- cgit v1.2.3 From f3c61700fbeba30f420ef939a1cabdc42bd15fb7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 18:05:42 -0800 Subject: Added I2C, UART, debug pins, misc wishbone stuff --- usrp2/top/u1e/u1e.ucf | 38 +++++----- usrp2/top/u1e/u1e.v | 12 ++- usrp2/top/u1e/u1e_core.v | 185 ++++++++++++++++++++++++++++++++++++++++------- 3 files changed, 187 insertions(+), 48 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 3b524a6ea..40d458034 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -56,10 +56,10 @@ NET "EM_NOE" LOC = "A14" ; #NET "overo_gpio65" LOC = "F8" ; #NET "overo_gpio127" LOC = "C8" ; #NET "overo_gpio128" LOC = "G8" ; -#NET "overo_gpio144" LOC = "A5" ; -#NET "overo_gpio145" LOC = "C7" ; -#NET "overo_gpio146" LOC = "A6" ; -#NET "overo_gpio147" LOC = "B6" ; +NET "overo_gpio144" LOC = "A5" ; # tx_have_space +NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio146" LOC = "A6" ; # rx_have_data +NET "overo_gpio147" LOC = "B6" ; # rx_overrun #NET "overo_gpio163" LOC = "D7" ; #NET "overo_gpio170" LOC = "E8" ; #NET "overo_gpio176" LOC = "B4" ; @@ -68,13 +68,13 @@ NET "EM_NOE" LOC = "A14" ; #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; +NET "FPGA_TXD" LOC = "U1" ; +NET "FPGA_RXD" LOC = "T6" ; #NET "SYSEN" LOC = "C11" ; -#NET "db_scl" LOC = "U4" ; -#NET "db_sda" LOC = "U5" ; +NET "db_scl" LOC = "U4" ; +NET "db_sda" LOC = "U5" ; #NET "db_sclk_rx" LOC = "W3" ; #NET "db_miso_rx" LOC = "W2" ; #NET "db_mosi_rx" LOC = "V4" ; @@ -134,18 +134,18 @@ NET "debug<31>" LOC = "G3" ; NET "debug_clk<0>" LOC = "L6" ; NET "debug_clk<1>" LOC = "M5" ; -#NET "debug_pb<2>" LOC = "Y2" ; -#NET "debug_pb<1>" LOC = "AA1" ; -#NET "debug_pb<0>" LOC = "N3" ; +NET "debug_pb<2>" LOC = "Y2" ; +NET "debug_pb<1>" LOC = "AA1" ; +NET "debug_pb<0>" LOC = "N3" ; -#NET "dip_sw<7>" LOC = "T3" ; -#NET "dip_sw<6>" LOC = "U3" ; -#NET "dip_sw<5>" LOC = "M3" ; -#NET "dip_sw<4>" LOC = "N4" ; -#NET "dip_sw<3>" LOC = "J3" ; -#NET "dip_sw<2>" LOC = "J4" ; -#NET "dip_sw<1>" LOC = "J6" ; -#NET "dip_sw<0>" LOC = "J7" ; +NET "dip_sw<7>" LOC = "T3" ; +NET "dip_sw<6>" LOC = "U3" ; +NET "dip_sw<5>" LOC = "M3" ; +NET "dip_sw<4>" LOC = "N4" ; +NET "dip_sw<3>" LOC = "J3" ; +NET "dip_sw<2>" LOC = "J4" ; +NET "dip_sw<1>" LOC = "J6" ; +NET "dip_sw<0>" LOC = "J7" ; ## AD9862 Interface #NET "aux_sdi_codec" LOC = "F19" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 8832d6e11..4ca9b5580 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -4,10 +4,14 @@ module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, // I2C + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147 // Fifo controls ); // FPGA-specific pins connections @@ -17,8 +21,12 @@ module u1e clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .db_sda(db_sda), .db_scl(db_scl), + .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), + .rx_have_data(overo_gpio_146), .rx_overrun(overo_gpio147) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index b0edbb9b6..cad697858 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -3,49 +3,180 @@ module u1e_core (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - + input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd, + // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE - ); - - // Debug circuitry - reg [31:0] ctr=0; - always @(posedge clk_fpga) - ctr <= ctr + 1; + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - assign debug_led = ctr[27:25]; - assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, - { EM_D } }; + inout db_sda, inout db_scl, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun + ); wire wb_clk, wb_rst; - wire wb_cyc, wb_stb, wb_we, wb_ack; - wire [1:0] wb_sel; - wire [10:0] wb_adr; - wire [15:0] wb_dat_mosi, wb_dat_miso; + + assign tx_have_space = 0; + assign tx_underrun = 0; + assign rx_have_data = 0; + assign rx_overrun = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPMC Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), - .wb_sel_o(wb_sel), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), .wb_we_o(wb_we), - .wb_ack_i(wb_ack)); + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack)); assign wb_clk = clk_fpga; - reg [15:0] reg_fast, reg_slow; - localparam [10:0] WB_ADR_REG_FAST = 11'd36; - localparam [10:0] WB_ADR_REG_SLOW = 38; + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s4_ack = 0; assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; + assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, LEDs and Switches + + reg [15:0] reg_fast, reg_slow; + localparam REG_FAST = 7'd4; + localparam REG_SWITCHES = 7'd5; always @(posedge wb_clk) - if(wb_cyc & wb_stb & wb_we & (wb_adr == WB_ADR_REG_FAST)) - reg_fast <= wb_dat_mosi; + if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST)) + reg_fast <= s0_dat_mosi; - assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : + (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + 16'hBEEF; + assign s0_ack = s0_stb & s0_cyc; - assign wb_ack = wb_stb & wb_cyc; - + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[4:2]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + /* + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + */ + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // Debug circuitry + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board + endmodule // u1e_core -- cgit v1.2.3 From bc3c1fb34afba5fb4358f1b7eaaf3832360cc375 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 19:13:10 -0800 Subject: added gpio control to the wishbone --- usrp2/top/u1e/u1e.v | 2 +- usrp2/top/u1e/u1e_core.v | 23 +++++++++++++---------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 4ca9b5580..326476b21 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -27,6 +27,6 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio_146), .rx_overrun(overo_gpio147) ); + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index cad697858..257156d4b 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -12,20 +12,15 @@ module u1e_core inout db_sda, inout db_scl, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun ); - - wire wb_clk, wb_rst; - - assign tx_have_space = 0; - assign tx_underrun = 0; - assign rx_have_data = 0; - assign rx_overrun = 0; + + wire wb_clk, wb_rst; // ///////////////////////////////////////////////////////////////////////////////////// // GPMC Slave to Wishbone Master localparam dw = 16; localparam aw = 11; localparam sw = 2; - + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; wire [aw-1:0] m0_adr; wire [sw-1:0] m0_sel; @@ -114,19 +109,27 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, LEDs and Switches - reg [15:0] reg_fast, reg_slow; + reg [15:0] reg_fast, reg_slow; localparam REG_FAST = 7'd4; - localparam REG_SWITCHES = 7'd5; + localparam REG_SWITCHES = 7'd6; + localparam REG_GPIOS = 7'd8; + + reg [3:0] reg_gpios; always @(posedge wb_clk) if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST)) reg_fast <= s0_dat_mosi; + always @(posedge wb_clk) + if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS)) + reg_gpios <= s0_dat_mosi; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; + assign { rx_overrun, rx_have_data, tx_underrun, tx_have_space } = reg_gpios; // ///////////////////////////////////////////////////////////////////////////////////// // Slave 1, UART -- cgit v1.2.3 From 2e4d962021334109b268c9080e5a5903b99be217 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 12:30:22 -0800 Subject: GPIOs now on the wishbone interface --- usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e.ucf | 64 ++++++++++++++++++++++++------------------------ usrp2/top/u1e/u1e.v | 6 +++-- usrp2/top/u1e/u1e_core.v | 19 ++++++++++++-- 4 files changed, 54 insertions(+), 37 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index cdbdf995e..9381789a7 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -64,7 +64,7 @@ control_lib/gray_send.v \ control_lib/icache.v \ control_lib/mux4.v \ control_lib/mux8.v \ -control_lib/nsgpio.v \ +control_lib/nsgpio16LE.v \ control_lib/ram_2port.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 40d458034..f237eb60c 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -203,39 +203,39 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "PPS_IN" LOC = "M17" ; -#NET "io_tx<0>" LOC = "AB20" ; -#NET "io_tx<1>" LOC = "Y17" ; -#NET "io_tx<2>" LOC = "Y16" ; -#NET "io_tx<3>" LOC = "U16" ; -#NET "io_tx<4>" LOC = "V16" ; -#NET "io_tx<5>" LOC = "AB19" ; -#NET "io_tx<6>" LOC = "AA19" ; -#NET "io_tx<7>" LOC = "U14" ; -#NET "io_tx<8>" LOC = "U15" ; -#NET "io_tx<9>" LOC = "AB17" ; -#NET "io_tx<10>" LOC = "AB18" ; -#NET "io_tx<11>" LOC = "Y13" ; -#NET "io_tx<12>" LOC = "W14" ; -#NET "io_tx<13>" LOC = "U13" ; -#NET "io_tx<14>" LOC = "AA15" ; -#NET "io_tx<15>" LOC = "AB14" ; +NET "io_tx<0>" LOC = "AB20" ; +NET "io_tx<1>" LOC = "Y17" ; +NET "io_tx<2>" LOC = "Y16" ; +NET "io_tx<3>" LOC = "U16" ; +NET "io_tx<4>" LOC = "V16" ; +NET "io_tx<5>" LOC = "AB19" ; +NET "io_tx<6>" LOC = "AA19" ; +NET "io_tx<7>" LOC = "U14" ; +NET "io_tx<8>" LOC = "U15" ; +NET "io_tx<9>" LOC = "AB17" ; +NET "io_tx<10>" LOC = "AB18" ; +NET "io_tx<11>" LOC = "Y13" ; +NET "io_tx<12>" LOC = "W14" ; +NET "io_tx<13>" LOC = "U13" ; +NET "io_tx<14>" LOC = "AA15" ; +NET "io_tx<15>" LOC = "AB14" ; -#NET "io_rx<0>" LOC = "Y8" ; -#NET "io_rx<1>" LOC = "Y9" ; -#NET "io_rx<2>" LOC = "V7" ; -#NET "io_rx<3>" LOC = "U8" ; -#NET "io_rx<4>" LOC = "V10" ; -#NET "io_rx<5>" LOC = "U9" ; -#NET "io_rx<6>" LOC = "AB7" ; -#NET "io_rx<7>" LOC = "AA8" ; -#NET "io_rx<8>" LOC = "W8" ; -#NET "io_rx<9>" LOC = "V8" ; -#NET "io_rx<10>" LOC = "AB5" ; -#NET "io_rx<11>" LOC = "AB6" ; -#NET "io_rx<12>" LOC = "AB4" ; -#NET "io_rx<13>" LOC = "AA4" ; -#NET "io_rx<14>" LOC = "W5" ; -#NET "io_rx<15>" LOC = "Y4" ; +NET "io_rx<0>" LOC = "Y8" ; +NET "io_rx<1>" LOC = "Y9" ; +NET "io_rx<2>" LOC = "V7" ; +NET "io_rx<3>" LOC = "U8" ; +NET "io_rx<4>" LOC = "V10" ; +NET "io_rx<5>" LOC = "U9" ; +NET "io_rx<6>" LOC = "AB7" ; +NET "io_rx<7>" LOC = "AA8" ; +NET "io_rx<8>" LOC = "W8" ; +NET "io_rx<9>" LOC = "V8" ; +NET "io_rx<10>" LOC = "AB5" ; +NET "io_rx<11>" LOC = "AB6" ; +NET "io_rx<12>" LOC = "AB4" ; +NET "io_rx<13>" LOC = "AA4" ; +NET "io_rx<14>" LOC = "W5" ; +NET "io_rx<15>" LOC = "Y4" ; #NET "CLKOUT2_CODEC" LOC = "U12" ; #NET "CLKOUT1_CODEC" LOC = "V12" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 326476b21..667372434 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -11,7 +11,8 @@ module u1e input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C - output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147 // Fifo controls + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + inout [15:0] io_tx, inout [15:0] io_rx ); // FPGA-specific pins connections @@ -27,6 +28,7 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147) ); + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .io_tx(io_tx), .io_rx(io_rx) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 257156d4b..ad3234b56 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -10,7 +10,8 @@ module u1e_core input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, - output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx ); wire wb_clk, wb_rst; @@ -102,7 +103,7 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s4_ack = 0; assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; + assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; @@ -172,6 +173,20 @@ module u1e_core IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////////////////// // Debug Pins -- cgit v1.2.3 From 7043c21bcef95879c58c9101f8bd16f216aa277a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 12:30:55 -0800 Subject: Modified nsgpio.v to support 16 bit little endian bus interface. --- usrp2/control_lib/nsgpio16LE.v | 124 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 usrp2/control_lib/nsgpio16LE.v diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v new file mode 100644 index 000000000..6847bb4a9 --- /dev/null +++ b/usrp2/control_lib/nsgpio16LE.v @@ -0,0 +1,124 @@ +// Modified from code originally by Richard Herveille, his copyright is below + +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple General Purpose IO core //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +module nsgpio16LE + (input clk_i, input rst_i, + input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, + output reg [15:0] dat_o, output reg ack_o, + input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, + inout [31:0] gpio + ); + + reg [63:0] ctrl; + reg [31:0] line; + reg [31:0] lgpio; // LatchedGPIO pins + reg [31:0] ddr; + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + begin + ctrl <= 64'h0; + line <= 0; + end + else if (wb_wr) + case( adr_i[3:1] ) + 3'b000 : + line[15:0] <= dat_i; + 3'b001 : + line[31:16] <= dat_i; + 3'b010 : + ddr[15:0] <= dat_i; + 3'b011 : + ddr[31:16] <= dat_i; + 3'b100 : + ctrl[15:0] <= dat_i; + 3'b101 : + ctrl[31:16] <= dat_i; + 3'b110 : + ctrl[47:32] <= dat_i; + 3'b111 : + ctrl[63:48] <= dat_i; + endcase // case ( adr_i[3:1] ) + + always @(posedge clk_i) + case (adr_i[3:1]) + 3'b000 : + dat_o <= lgpio[15:0]; + 3'b001 : + dat_o <= lgpio[31:16]; + 3'b010 : + dat_o <= ddr[15:0]; + 3'b011 : + dat_o <= ddr[31:16]; + 3'b100 : + dat_o <= ctrl[15:0]; + 3'b101 : + dat_o <= ctrl[31:16]; + 3'b110 : + dat_o <= ctrl[47:32]; + 3'b111 : + dat_o <= ctrl[63:48]; + endcase // case (adr_i[3:1]) + + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + ack_o <= 1'b0; + else + ack_o <= wb_acc & !ack_o; + + // latch GPIO input pins + always @(posedge clk_i) + lgpio <= gpio; + + // assign GPIO outputs + integer n; + reg [31:0] igpio; // temporary internal signal + + always @(ctrl or line or debug_1 or debug_0 or atr) + for(n=0;n<32;n=n+1) + igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : + (ctrl[2*n] ? atr[n] : line[n]) ) + : 1'bz; + + assign gpio = igpio; + +endmodule + -- cgit v1.2.3 From ba97786f44d66c634f289e9a23021e8e13548326 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 12:33:13 -0800 Subject: remove the #1 delay in all the regs. They just slow down sims. --- usrp2/opencores/spi/rtl/verilog/spi_clgen.v | 20 +++--- usrp2/opencores/spi/rtl/verilog/spi_defines.v | 8 +-- usrp2/opencores/spi/rtl/verilog/spi_shift.v | 90 +++++++++++++-------------- usrp2/opencores/spi/rtl/verilog/spi_top.v | 68 ++++++++++---------- 4 files changed, 90 insertions(+), 96 deletions(-) diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v index 7bc4f6e5e..3f29f6d7f 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v @@ -43,8 +43,6 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); - parameter Tp = 1; - input clk_in; // input clock (system clock) input rst; // reset input enable; // clock enable @@ -71,13 +69,13 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, always @(posedge clk_in or posedge rst) begin if(rst) - cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}}; + cnt <= {`SPI_DIVIDER_LEN{1'b1}}; else begin if(!enable || cnt_zero) - cnt <= #Tp divider; + cnt <= divider; else - cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; + cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; end end @@ -85,9 +83,9 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, always @(posedge clk_in or posedge rst) begin if(rst) - clk_out <= #Tp 1'b0; + clk_out <= 1'b0; else - clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; end // Pos and neg edge signals @@ -95,13 +93,13 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, begin if(rst) begin - pos_edge <= #Tp 1'b0; - neg_edge <= #Tp 1'b0; + pos_edge <= 1'b0; + neg_edge <= 1'b0; end else begin - pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); - neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + pos_edge <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); end end endmodule diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v index a6925918e..01de2584d 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -43,8 +43,8 @@ // low frequency of system clock this can be reduced. // Use SPI_DIVIDER_LEN for fine tuning theexact number. // -//`define SPI_DIVIDER_LEN_8 -`define SPI_DIVIDER_LEN_16 +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 //`define SPI_DIVIDER_LEN_24 //`define SPI_DIVIDER_LEN_32 @@ -66,9 +66,9 @@ // Use SPI_MAX_CHAR for fine tuning the exact number, when using // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. // -`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_128 //`define SPI_MAX_CHAR_64 -//`define SPI_MAX_CHAR_32 +`define SPI_MAX_CHAR_32 //`define SPI_MAX_CHAR_24 //`define SPI_MAX_CHAR_16 //`define SPI_MAX_CHAR_8 diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v index b17ac8b1f..c8c73706b 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_shift.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v @@ -46,8 +46,6 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, tip, last, p_in, p_out, s_clk, s_in, s_out); - parameter Tp = 1; - input clk; // system clock input rst; // reset input [3:0] latch; // latch signal for storing the data in shift register @@ -92,13 +90,13 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, always @(posedge clk or posedge rst) begin if(rst) - cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}}; else begin if(tip) - cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; else - cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; end end @@ -106,132 +104,132 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, always @(posedge clk or posedge rst) begin if(rst) - tip <= #Tp 1'b0; + tip <= 1'b0; else if(go && ~tip) - tip <= #Tp 1'b1; + tip <= 1'b1; else if(tip && last && pos_edge) - tip <= #Tp 1'b0; + tip <= 1'b0; end // Sending bits to the line always @(posedge clk or posedge rst) begin if (rst) - s_out <= #Tp 1'b0; + s_out <= 1'b0; else - s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; end // Receiving bits from the line always @(posedge clk or posedge rst) begin if (rst) - data <= #Tp {`SPI_MAX_CHAR{1'b0}}; + data <= {`SPI_MAX_CHAR{1'b0}}; `ifdef SPI_MAX_CHAR_128 else if (latch[0] && !tip) begin if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; + data[31:24] <= p_in[31:24]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; end else if (latch[1] && !tip) begin if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; + data[63:56] <= p_in[31:24]; if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; + data[55:48] <= p_in[23:16]; if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; + data[47:40] <= p_in[15:8]; if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; + data[39:32] <= p_in[7:0]; end else if (latch[2] && !tip) begin if (byte_sel[3]) - data[95:88] <= #Tp p_in[31:24]; + data[95:88] <= p_in[31:24]; if (byte_sel[2]) - data[87:80] <= #Tp p_in[23:16]; + data[87:80] <= p_in[23:16]; if (byte_sel[1]) - data[79:72] <= #Tp p_in[15:8]; + data[79:72] <= p_in[15:8]; if (byte_sel[0]) - data[71:64] <= #Tp p_in[7:0]; + data[71:64] <= p_in[7:0]; end else if (latch[3] && !tip) begin if (byte_sel[3]) - data[127:120] <= #Tp p_in[31:24]; + data[127:120] <= p_in[31:24]; if (byte_sel[2]) - data[119:112] <= #Tp p_in[23:16]; + data[119:112] <= p_in[23:16]; if (byte_sel[1]) - data[111:104] <= #Tp p_in[15:8]; + data[111:104] <= p_in[15:8]; if (byte_sel[0]) - data[103:96] <= #Tp p_in[7:0]; + data[103:96] <= p_in[7:0]; end `else `ifdef SPI_MAX_CHAR_64 else if (latch[0] && !tip) begin if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; + data[31:24] <= p_in[31:24]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; end else if (latch[1] && !tip) begin if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; + data[63:56] <= p_in[31:24]; if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; + data[55:48] <= p_in[23:16]; if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; + data[47:40] <= p_in[15:8]; if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; + data[39:32] <= p_in[7:0]; end `else else if (latch[0] && !tip) begin `ifdef SPI_MAX_CHAR_8 if (byte_sel[0]) - data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0]; + data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0]; `endif `ifdef SPI_MAX_CHAR_16 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8]; + data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8]; `endif `ifdef SPI_MAX_CHAR_24 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[2]) - data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16]; + data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16]; `endif `ifdef SPI_MAX_CHAR_32 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[3]) - data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24]; + data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24]; `endif end `endif `endif else - data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; end endmodule diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v index 09b2e50e1..071aeefca 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_top.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v @@ -52,8 +52,6 @@ module spi_top ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i ); - parameter Tp = 1; - // Wishbone signals input wb_clk_i; // master clock input input wb_rst_i; // synchronous active high reset @@ -142,18 +140,18 @@ module spi_top always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - wb_dat_o <= #Tp 32'b0; + wb_dat_o <= 32'b0; else - wb_dat_o <= #Tp wb_dat; + wb_dat_o <= wb_dat; end // Wb acknowledge always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - wb_ack_o <= #Tp 1'b0; + wb_ack_o <= 1'b0; else - wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; end // Wb error @@ -163,47 +161,47 @@ module spi_top always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - wb_int_o <= #Tp 1'b0; + wb_int_o <= 1'b0; else if (ie && tip && last_bit && pos_edge) - wb_int_o <= #Tp 1'b1; + wb_int_o <= 1'b1; else if (wb_ack_o) - wb_int_o <= #Tp 1'b0; + wb_int_o <= 1'b0; end // Divider register always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}}; + divider <= {`SPI_DIVIDER_LEN{1'b0}}; else if (spi_divider_sel && wb_we_i && !tip) begin `ifdef SPI_DIVIDER_LEN_8 if (wb_sel_i[0]) - divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0]; + divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0]; `endif `ifdef SPI_DIVIDER_LEN_16 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8]; + divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8]; `endif `ifdef SPI_DIVIDER_LEN_24 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; + divider[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16]; + divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16]; `endif `ifdef SPI_DIVIDER_LEN_32 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; + divider[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - divider[23:16] <= #Tp wb_dat_i[23:16]; + divider[23:16] <= wb_dat_i[23:16]; if (wb_sel_i[3]) - divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24]; + divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24]; `endif end end @@ -212,16 +210,16 @@ module spi_top always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}}; + ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; else if(spi_ctrl_sel && wb_we_i && !tip) begin if (wb_sel_i[0]) - ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; + ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; if (wb_sel_i[1]) - ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; end else if(tip && last_bit && pos_edge) - ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; + ctrl[`SPI_CTRL_GO] <= 1'b0; end assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; @@ -236,36 +234,36 @@ module spi_top always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - ss <= #Tp {`SPI_SS_NB{1'b0}}; + ss <= {`SPI_SS_NB{1'b0}}; else if(spi_ss_sel && wb_we_i && !tip) begin `ifdef SPI_SS_NB_8 if (wb_sel_i[0]) - ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + ss <= wb_dat_i[`SPI_SS_NB-1:0]; `endif `ifdef SPI_SS_NB_16 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8]; + ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8]; `endif `ifdef SPI_SS_NB_24 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; + ss[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16]; + ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16]; `endif `ifdef SPI_SS_NB_32 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; + ss[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - ss[23:16] <= #Tp wb_dat_i[23:16]; + ss[23:16] <= wb_dat_i[23:16]; if (wb_sel_i[3]) - ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24]; + ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24]; `endif end end -- cgit v1.2.3 From 035440ab7dce5c13655539db606de531606bad59 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 15:39:53 -0800 Subject: settings bus with 16 bit wishbone interface, put on the main wishbone in u1e --- usrp2/control_lib/settings_bus_16LE.v | 54 +++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e_core.v | 15 ++++++++-- 3 files changed, 68 insertions(+), 3 deletions(-) create mode 100644 usrp2/control_lib/settings_bus_16LE.v diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v new file mode 100644 index 000000000..fbef9b1c9 --- /dev/null +++ b/usrp2/control_lib/settings_bus_16LE.v @@ -0,0 +1,54 @@ + +// Grab settings off the wishbone bus, send them out to settings bus +// 16 bits little endian, but all registers need to be written 32 bits at a time. +// This means that you write the low 16 bits first and then the high 16 bits. +// The setting regs are strobed when the high 16 bits are written + +module settings_bus_16LE + #(parameter AWIDTH=16) + (input wb_clk, + input wb_rst, + input [AWIDTH-1:0] wb_adr_i, + input [15:0] wb_dat_i, + input wb_stb_i, + input wb_we_i, + output reg wb_ack_o, + output strobe, + output reg [7:0] addr, + output reg [31:0] data); + + reg stb_int; + + always @(posedge wb_clk) + if(wb_rst) + begin + stb_int <= 1'b0; + addr <= 8'd0; + data <= 32'd0; + end + else if(wb_we_i & wb_stb_i) + begin + addr <= wb_adr_i[9:2]; + if(wb_adr_i[1]) + begin + stb_int <= 1'b1; // We now have both halves + data[31:16] <= wb_dat_i; + end + else + begin + stb_int <= 1'b0; // Don't strobe, we need other half + data[15:0] <= wb_dat_i; + end + end + else + stb_int <= 1'b0; + + always @(posedge wb_clk) + if(wb_rst) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + assign strobe = stb_int & wb_ack_o; + +endmodule // settings_bus_16LE diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 9381789a7..bcd80df6a 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -69,7 +69,7 @@ control_lib/ram_2port.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ -control_lib/settings_bus.v \ +control_lib/settings_bus_16LE.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ad3234b56..7ac4c8f86 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -103,7 +103,7 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; + assign s6_ack = 0; assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; @@ -182,10 +182,21 @@ module u1e_core nsgpio16LE nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #5 + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + settings_bus_16LE settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), + .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); // ///////////////////////////////////////////////////////////////////////////////////// // Debug Pins -- cgit v1.2.3 From 89fc3946d6fa590dd8047984ed8718a6ffa4ab77 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 23 Feb 2010 16:35:06 -0800 Subject: use our fancy new debug ports --- usrp2/top/u1e/u1e_core.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7ac4c8f86..12c566b6c 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -206,6 +206,9 @@ module u1e_core assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; + assign debug_gpio_0 = { m0_we, m0_stb, m0_ack, s1_stb, s0_stb, m0_adr[10:0], m0_dat_mosi[15:0] }; + assign debug_gpio_1 = { debug_txd, debug_rxd }; + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board endmodule // u1e_core -- cgit v1.2.3 From 702c87c3bae259f038d2c10fe32903f391e95de1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 23 Feb 2010 19:54:54 -0800 Subject: first cut at making a bidirectional 2 port ram for the gpmc data interface ISE chokes on the unequal size ram --- usrp2/control_lib/ram_2port_mixed_width.v | 44 +++++++++++++++++++++++++++++++ usrp2/gpmc/gpmc.v | 24 ++++++++++++----- usrp2/top/u1e/Makefile | 1 + 3 files changed, 63 insertions(+), 6 deletions(-) create mode 100644 usrp2/control_lib/ram_2port_mixed_width.v diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v new file mode 100644 index 000000000..3fa43114f --- /dev/null +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -0,0 +1,44 @@ + + +module ram_2port_mixed_width + #(parameter AWIDTH=9) + (input clk16, + input en16, + input we16, + input [10:0] addr16, + input [15:0] di16, + output reg [15:0] do16, + + input clk32, + input en32, + input we32, + input [9:0] addr32, + input [31:0] di32, + output reg [31:0] do32); + + reg [31:0] ram [(1< Date: Thu, 25 Feb 2010 16:50:09 -0800 Subject: First cut at passing data buffers around on GPMC bus --- usrp2/gpmc/dbsm.v | 88 +++++++++++++++++++++++++++++++++++++++++++++++ usrp2/gpmc/gpmc.v | 45 ++++++++++++++++++------ usrp2/models/gpmc_model.v | 23 ++++++++++--- usrp2/top/u1e/tb_u1e.v | 11 ++++-- usrp2/top/u1e/u1e.v | 3 +- usrp2/top/u1e/u1e_core.v | 20 +++++++---- 6 files changed, 165 insertions(+), 25 deletions(-) create mode 100644 usrp2/gpmc/dbsm.v diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v new file mode 100644 index 000000000..0f27be46a --- /dev/null +++ b/usrp2/gpmc/dbsm.v @@ -0,0 +1,88 @@ + +module bsm + (input clk, input reset, input clear, + input write_done, + input read_done, + output readable, + output writeable); + + reg state; + localparam ST_WRITEABLE = 0; + localparam ST_READABLE = 1; + + always @(posedge clk) + if(reset | clear) + state <= ST_WRITEABLE; + else + case(state) + ST_WRITEABLE : + if(write_done) + state <= ST_READABLE; + ST_READABLE : + if(read_done) + state <= ST_WRITEABLE; + endcase // case (state) + + assign readable = (state == ST_READABLE); + assign writeable = (state == ST_WRITEABLE); + +endmodule // bsm + +module dbsm + (input clk, input reset, input clear, + output reg read_sel, output read_ready, input read_done, + output reg write_sel, output write_ready, input write_done); + + localparam NUM_BUFS = 2; + + wire [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf; + + // Two of these buffer state machines + genvar i; + for(i=0;i Date: Thu, 25 Feb 2010 16:50:29 -0800 Subject: ISE chokes on the pure verilog version so we use the macro --- usrp2/control_lib/ram_2port_mixed_width.v | 53 ++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index 3fa43114f..e10321959 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -1,5 +1,3 @@ - - module ram_2port_mixed_width #(parameter AWIDTH=9) (input clk16, @@ -7,14 +5,58 @@ module ram_2port_mixed_width input we16, input [10:0] addr16, input [15:0] di16, - output reg [15:0] do16, + output [15:0] do16, input clk32, input en32, input we32, input [9:0] addr32, input [31:0] di32, - output reg [31:0] do32); + output [31:0] do32); + + RAMB16BWER #(.DATA_WIDTH_A(18), // Valid values are 0, 1, 2, 4, 9, 18, or 36 + .DATA_WIDTH_B(36), // Valid values are 0, 1, 2, 4, 9, 18, or 36 + .DOA_REG(0), // Specifies to enable=1/disable=0 port A output registers + .DOB_REG(0), // Specifies to enable=1/disable=0 port B output registers + .INIT_A(36'h000000000), // Initial values on A output port + .INIT_B(36'h000000000), // Initial values on B output port + .RSTTYPE("SYNC"), // Specifes reset type to be "SYNC" or "ASYNC" + .SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY", + // "GENERATE_X_ONLY" or "NONE" + .SRVAL_A(36'h000000000), // Set/Reset value for A port output + .SRVAL_B(36'h000000000), // Set/Reset value for B port output + .WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" + .WRITE_MODE_B("WRITE_FIRST")) // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" + RAMB16BWER_inst (.DOA(do16), // 32-bit A port data output + .DOB(do32), // 32-bit B port data output + .DOPA(), // 4-bit A port parity data output + .DOPB(), // 4-bit B port parity data output + .ADDRA(addr16), // 14-bit A port address input + .ADDRB(addr32), // 14-bit B port address input + .CLKA(clk16), // 1-bit A port clock input + .CLKB(clk32), // 1-bit B port clock input + .DIA(di16), // 32-bit A port data input + .DIB(di32), // 32-bit B port data input + .DIPA(0), // 4-bit A port parity data input + .DIPB(0), // 4-bit B port parity data input + .ENA(en16), // 1-bit A port enable input + .ENB(en32), // 1-bit B port enable input + .REGCEA(0), // 1-bit A port output register enable input + .REGCEB(0), // 1-bit B port output register enable input + .RSTA(0), // 1-bit A port reset input + .RSTB(0), // 1-bit B port reset input + .WEA({2{we16}}), // 4-bit A port write enable input + .WEB({4{we32}}) // 4-bit B port write enable input + ); + +endmodule // ram_2port_mixed_width + + + + +// ISE 10.1.03 chokes on the following + +/* reg [31:0] ram [(1< Date: Thu, 25 Feb 2010 18:37:25 -0800 Subject: Switched xilinx primitives because they order the bits funny in the other one --- usrp2/control_lib/ram_2port_mixed_width.v | 127 +++++++++++++++++++----------- 1 file changed, 79 insertions(+), 48 deletions(-) diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index e10321959..e84b0da02 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -1,54 +1,85 @@ + module ram_2port_mixed_width - #(parameter AWIDTH=9) - (input clk16, - input en16, - input we16, - input [10:0] addr16, - input [15:0] di16, - output [15:0] do16, - - input clk32, - input en32, - input we32, - input [9:0] addr32, - input [31:0] di32, - output [31:0] do32); + (input clk16, + input en16, + input we16, + input [10:0] addr16, + input [15:0] di16, + output [15:0] do16, + input clk32, + input en32, + input we32, + input [9:0] addr32, + input [31:0] di32, + output [31:0] do32); + + wire en32a = en32 & ~addr32[9]; + wire en32b = en32 & addr32[9]; + wire en16a = en16 & ~addr16[9]; + wire en16b = en16 & addr16[9]; - RAMB16BWER #(.DATA_WIDTH_A(18), // Valid values are 0, 1, 2, 4, 9, 18, or 36 - .DATA_WIDTH_B(36), // Valid values are 0, 1, 2, 4, 9, 18, or 36 - .DOA_REG(0), // Specifies to enable=1/disable=0 port A output registers - .DOB_REG(0), // Specifies to enable=1/disable=0 port B output registers - .INIT_A(36'h000000000), // Initial values on A output port - .INIT_B(36'h000000000), // Initial values on B output port - .RSTTYPE("SYNC"), // Specifes reset type to be "SYNC" or "ASYNC" - .SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY", - // "GENERATE_X_ONLY" or "NONE" - .SRVAL_A(36'h000000000), // Set/Reset value for A port output - .SRVAL_B(36'h000000000), // Set/Reset value for B port output - .WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" - .WRITE_MODE_B("WRITE_FIRST")) // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" - RAMB16BWER_inst (.DOA(do16), // 32-bit A port data output - .DOB(do32), // 32-bit B port data output - .DOPA(), // 4-bit A port parity data output - .DOPB(), // 4-bit B port parity data output - .ADDRA(addr16), // 14-bit A port address input - .ADDRB(addr32), // 14-bit B port address input - .CLKA(clk16), // 1-bit A port clock input - .CLKB(clk32), // 1-bit B port clock input - .DIA(di16), // 32-bit A port data input - .DIB(di32), // 32-bit B port data input - .DIPA(0), // 4-bit A port parity data input - .DIPB(0), // 4-bit B port parity data input - .ENA(en16), // 1-bit A port enable input - .ENB(en32), // 1-bit B port enable input - .REGCEA(0), // 1-bit A port output register enable input - .REGCEB(0), // 1-bit B port output register enable input - .RSTA(0), // 1-bit A port reset input - .RSTB(0), // 1-bit B port reset input - .WEA({2{we16}}), // 4-bit A port write enable input - .WEB({4{we32}}) // 4-bit B port write enable input - ); + wire [31:0] do32a, do32b; + wire [15:0] do16a, do16b; + + assign do32 = addr32[9] ? do32b : do32a; + assign do16 = addr16[10] ? do16b : do16a; + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output + .DOB(do16a), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32a), // Port A 1-bit RAM Enable Input + .ENB(en16a), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output + .DOB(do16b), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32b), // Port A 1-bit RAM Enable Input + .ENB(en16b), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + endmodule // ram_2port_mixed_width -- cgit v1.2.3 From 2f9b93f32ed8e561a0e92e2e32af03707475011c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 18:38:07 -0800 Subject: edge sync on done signals so we only fill/empty one buffer --- usrp2/gpmc/edge_sync.v | 22 ++++++++++++++++++++++ usrp2/gpmc/gpmc.v | 12 ++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 usrp2/gpmc/edge_sync.v diff --git a/usrp2/gpmc/edge_sync.v b/usrp2/gpmc/edge_sync.v new file mode 100644 index 000000000..5d9417c08 --- /dev/null +++ b/usrp2/gpmc/edge_sync.v @@ -0,0 +1,22 @@ + + +module edge_sync + #(parameter POSEDGE = 1) + (input clk, + input rst, + input sig, + output trig); + + reg [1:0] delay; + + always @(posedge clk) + if(rst) + delay <= 2'b00; + else + delay <= {delay[0],sig}; + + assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10); + +endmodule // edge_sync + + diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 91d02bfec..831df3b4c 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -32,7 +32,11 @@ module gpmc // //////////////////////////////////////////// // Write path wire read_sel_in, write_sel_in, clear_in; - wire write_done_in = ~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF); + wire write_done_in; + + edge_sync #(.POSEDGE(0)) + edge_sync_wdi(.clk(wb_clk), .rst(wb_rst), + .sig(~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF)), .trig(write_done_in)); ram_2port_mixed_width buffer_in (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({write_sel_in,EM_A}), .di16(EM_D), .do16(), @@ -47,7 +51,11 @@ module gpmc // //////////////////////////////////////////// // Read path wire read_sel_out, write_sel_out, clear_out; - wire read_done_out = ~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF); + wire read_done_out; + + edge_sync #(.POSEDGE(0)) + edge_sync_rdo(.clk(wb_clk), .rst(wb_rst), + .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_out)); ram_2port_mixed_width buffer_out (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_out,EM_A}), .di16(0), .do16(EM_D_ram), -- cgit v1.2.3 From d808829fee0c93f22c2ff3b34d0772d7cb91df5c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 18:38:35 -0800 Subject: corrected logic --- usrp2/gpmc/dbsm.v | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v index 0f27be46a..ff61859ec 100644 --- a/usrp2/gpmc/dbsm.v +++ b/usrp2/gpmc/dbsm.v @@ -56,28 +56,18 @@ module dbsm full <= 0; end else - if(write_done) - if(writeable[write_sel]==(NUM_BUFS-1)) - begin - write_sel <= 0; - if(read_sel == 0) - full <= 1; - end + if(write_done & writeable[write_sel]) + if(write_sel ==(NUM_BUFS-1)) + write_sel <= 0; else - begin - write_sel <= write_sel + 1; - if(read_sel == write_sel + 1) - full <= 1; - end // else: !if(writeable[write_sel]==(NUM_BUFS-1)) - else if(read_done) - full <= 0; - + write_sel <= write_sel + 1; + always @(posedge clk) if(reset | clear) read_sel <= 0; else - if(read_done) - if(readable[read_sel]==(NUM_BUFS-1)) + if(read_done & readable[read_sel]) + if(read_sel==(NUM_BUFS-1)) read_sel <= 0; else read_sel <= read_sel + 1; -- cgit v1.2.3 From c8e869b2e685cb8a5c012498b7f47aaadf39698a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 18:38:48 -0800 Subject: loopback and test --- usrp2/models/gpmc_model.v | 11 ++++++----- usrp2/top/u1e/u1e_core.v | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 7 deletions(-) diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v index 1e7dcdde5..3424671bd 100644 --- a/usrp2/models/gpmc_model.v +++ b/usrp2/models/gpmc_model.v @@ -78,11 +78,12 @@ module gpmc_model #1000; GPMC_Read(1,36); #1000; - GPMC_Write(0,36,16'hF00D); - GPMC_Write(0,38,16'hF00D); - GPMC_Write(0,40,16'hF00D); - GPMC_Write(0,11'h7FFE,16'hF00D); - #1000; + GPMC_Write(0,36,16'h1234); + GPMC_Write(0,38,16'h5678); + GPMC_Write(0,40,16'h9abc); + GPMC_Write(0,11'h2F4,16'hF00D); + GPMC_Write(0,11'h7FE,16'hF00D); + #100000; $finish; end diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7feafeda8..e14152f33 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -26,6 +26,13 @@ module u1e_core wire [aw-1:0] m0_adr; wire [sw-1:0] m0_sel; wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + // FIFO buffers + wire [31:0] read_data, write_data; + wire [8:0] read_addr, write_addr; + reg [8:0] addr; + + wire read_done, write_done, read_en, write_en, read_ready, write_ready; gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), @@ -43,9 +50,32 @@ module u1e_core .read_ready(read_ready), .read_done(read_done), .write_en(write_en), .write_addr(write_addr), .write_data(write_data), .write_ready(write_ready), .write_done(write_done) ); + + // Loopback + assign write_data = read_data; + + reg [10:0] counter; + assign write_addr = counter[10:2]; + assign read_addr = counter[10:2]; - assign wb_clk = clk_fpga; - + assign read_done = (counter == 11'h7FF); + assign write_done = (counter == 11'h7FF); + + always @(posedge wb_clk) + if(wb_rst) + counter <= 0; + else + if(counter == 0) + counter <= write_ready & read_ready; + else if(counter == 11'h7FF) + counter <= 0; + else + counter <= counter + 1; + + assign read_en = (counter[1:0] == 1); + assign write_en = (counter[1:0] == 2); + + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, -- cgit v1.2.3 From bcf582bab2544a1d519f84c659322c4c4adc59a1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 18:48:51 -0800 Subject: fix syntax error which icarus allowed (filed a bug with them) --- usrp2/gpmc/dbsm.v | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v index ff61859ec..530af7205 100644 --- a/usrp2/gpmc/dbsm.v +++ b/usrp2/gpmc/dbsm.v @@ -39,13 +39,15 @@ module dbsm // Two of these buffer state machines genvar i; - for(i=0;i Date: Thu, 25 Feb 2010 18:49:20 -0800 Subject: point to the new files --- usrp2/top/u1e/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 306ab5bae..3412e227d 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -176,6 +176,8 @@ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ gpmc/gpmc.v \ +gpmc/edge_sync.v \ +gpmc/dbsm.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/u1e.v -- cgit v1.2.3 From 67dd6732b70c1cd35a7134f4830b09b893255935 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 19:43:01 -0800 Subject: gpmc debug pins --- usrp2/gpmc/gpmc.v | 9 ++++++++- usrp2/top/u1e/u1e_core.v | 9 ++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 831df3b4c..cf1357232 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -16,7 +16,8 @@ module gpmc // RAM Interface signals input ram_clk, input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done, - input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done + input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done, + output [31:0] debug ); wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); @@ -65,6 +66,12 @@ module gpmc .read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out), .write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done)); + + assign debug = { { 2'b00, write_done_in, write_sel_in, read_en, read_sel_in, read_ready, read_done}, + { 2'b00, read_sel_out, write_en, write_sel_out, read_done_out, write_ready, write_done }, + { 8'd0 }, + { 8'd0 } }; + // CS6 is Control, Wishbone bus bridge (wb master) // Sync version reg [1:0] cs_del, we_del, oe_del; diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e14152f33..6706d4aac 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -33,6 +33,8 @@ module u1e_core reg [8:0] addr; wire read_done, write_done, read_en, write_en, read_ready, write_ready; + + wire [31:0] debug_gpmc; gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), @@ -49,7 +51,8 @@ module u1e_core .read_en(read_en), .read_addr(read_addr), .read_data(read_data), .read_ready(read_ready), .read_done(read_done), .write_en(write_en), .write_addr(write_addr), .write_data(write_data), - .write_ready(write_ready), .write_done(write_done) ); + .write_ready(write_ready), .write_done(write_done), + .debug(debug_gpmc)); // Loopback assign write_data = read_data; @@ -241,10 +244,10 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; - assign debug_gpio_0 = { m0_we, m0_stb, m0_ack, s1_stb, s0_stb, m0_adr[10:0], m0_dat_mosi[15:0] }; + assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board -- cgit v1.2.3 From e775ce6c17d1e43865cdd3f9472157d0d2d26b92 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 21:09:34 -0800 Subject: invert the pushbuttons since they are active low --- usrp2/top/u1e/u1e.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 066d02ca4..329d61aa9 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -21,9 +21,9 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(debug_pb[2]), + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), -- cgit v1.2.3 From db60b00d7a1bafe4f3f49e1ec2367897fc8c71ab Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 21:10:26 -0800 Subject: enable was on the wrong address pin, needs to be the highest order one --- usrp2/control_lib/ram_2port_mixed_width.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index e84b0da02..fae7d8de3 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -15,8 +15,8 @@ module ram_2port_mixed_width wire en32a = en32 & ~addr32[9]; wire en32b = en32 & addr32[9]; - wire en16a = en16 & ~addr16[9]; - wire en16b = en16 & addr16[9]; + wire en16a = en16 & ~addr16[10]; + wire en16b = en16 & addr16[10]; wire [31:0] do32a, do32b; wire [15:0] do16a, do16b; -- cgit v1.2.3 From 4288c956b45143f3cab7b798758ff41ffb43aa4a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 21:55:13 -0800 Subject: debug pins --- usrp2/top/u1e/u1e_core.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 6706d4aac..2645225a0 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -216,7 +216,7 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // GPIOs -- Slave #4 - +/* wire [31:0] atr_lines; wire [31:0] debug_gpio_0, debug_gpio_1; @@ -226,7 +226,7 @@ module u1e_core .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); - +*/ // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 @@ -247,6 +247,7 @@ module u1e_core assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; + assign {io_tx,io_rx} = debug_gpmc; assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; -- cgit v1.2.3 From b74388567c0ed3048e45158ac077e31def59fea1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Mar 2010 15:49:23 -0700 Subject: connected spi pins, but the spi core still needs to be redone for 16 bit interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs --- usrp2/top/u1e/u1e.ucf | 72 ++++++++++++++++++++++++++---------------------- usrp2/top/u1e/u1e.v | 16 +++++++++++ usrp2/top/u1e/u1e_core.v | 12 ++++---- 3 files changed, 60 insertions(+), 40 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index f237eb60c..27f507c6b 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -68,27 +68,43 @@ NET "overo_gpio147" LOC = "B6" ; # rx_overrun #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; +## FTDI UART to USB converter NET "FPGA_TXD" LOC = "U1" ; NET "FPGA_RXD" LOC = "T6" ; #NET "SYSEN" LOC = "C11" ; +## I2C NET "db_scl" LOC = "U4" ; NET "db_sda" LOC = "U5" ; -#NET "db_sclk_rx" LOC = "W3" ; -#NET "db_miso_rx" LOC = "W2" ; -#NET "db_mosi_rx" LOC = "V4" ; -#NET "db_sen_rx" LOC = "V3" ; -#NET "db_sclk_tx" LOC = "Y1" ; -#NET "db_miso_tx" LOC = "W1" ; -#NET "db_mosi_tx" LOC = "R3" ; -#NET "db_sen_tx" LOC = "T4" ; -## Clock Gen -#NET "cgen_miso" LOC = "U2" ; -#NET "cgen_mosi" LOC = "V1" ; -#NET "cgen_sclk" LOC = "R5" ; -#NET "cgen_sen_b" LOC = "T1" ; +## SPI +### DBoard SPI +NET "db_sclk_rx" LOC = "W3" ; +NET "db_miso_rx" LOC = "W2" ; +NET "db_mosi_rx" LOC = "V4" ; +NET "db_sen_rx" LOC = "V3" ; +NET "db_sclk_tx" LOC = "Y1" ; +NET "db_miso_tx" LOC = "W1" ; +NET "db_mosi_tx" LOC = "R3" ; +NET "db_sen_tx" LOC = "T4" ; + +### AD9862 SPI and aux SPI Interfaces +#NET "aux_sdi_codec" LOC = "F19" ; +#NET "aux_sdo_codec" LOC = "F18" ; +#NET "aux_sclk_codec" LOC = "D21" ; +NET "sen_codec" LOC = "D20" ; +NET "mosi_codec" LOC = "E19" ; +NET "miso_codec" LOC = "F21" ; +NET "sclk_codec" LOC = "E20" ; + +### Clock Gen SPI +NET "cgen_miso" LOC = "U2" ; +NET "cgen_mosi" LOC = "V1" ; +NET "cgen_sclk" LOC = "R5" ; +NET "cgen_sen_b" LOC = "T1" ; + +## Clock gen control #NET "cgen_st_status" LOC = "D4" ; #NET "cgen_st_ld" LOC = "D1" ; #NET "cgen_st_refmon" LOC = "E1" ; @@ -147,17 +163,8 @@ NET "dip_sw<2>" LOC = "J4" ; NET "dip_sw<1>" LOC = "J6" ; NET "dip_sw<0>" LOC = "J7" ; -## AD9862 Interface -#NET "aux_sdi_codec" LOC = "F19" ; -#NET "aux_sdo_codec" LOC = "F18" ; -#NET "aux_sclk_codec" LOC = "D21" ; -#NET "reset_codec" LOC = "D22" ; -#NET "sen_codec" LOC = "D20" ; -#NET "mosi_codec" LOC = "E19" ; -#NET "miso_codec" LOC = "F21" ; -#NET "sclk_codec" LOC = "E20" ; - #NET "RXSYNC" LOC = "F22" ; +#NET "reset_codec" LOC = "D22" ; #NET "DB<11>" LOC = "E22" ; #NET "DB<10>" LOC = "J19" ; @@ -248,13 +255,12 @@ NET "io_rx<15>" LOC = "Y4" ; #NET "fpga_cfg_init_b" LOC = "W15" ; ## Unnamed, need to figure out what they do -#NET "unnamed_net37" LOC = "B1" ; -#NET "unnamed_net36" LOC = "B22" ; -#NET "unnamed_net35" LOC = "D2" ; -#NET "unnamed_net34" LOC = "A21" ; -#NET "unnamed_net45" LOC = "F7" ; -#NET "unnamed_net44" LOC = "V6" ; -#NET "unnamed_net43" LOC = "AA3" ; -#NET "unnamed_net42" LOC = "AB3" ; - -#NET "GND" LOC = "V19" ; +#NET "unnamed_net37" LOC = "B1" ; # TMS +#NET "unnamed_net36" LOC = "B22" ; # TDO +#NET "unnamed_net35" LOC = "D2" ; # TDI +#NET "unnamed_net34" LOC = "A21" ; # TCK +#NET "unnamed_net45" LOC = "F7" ; # PUDC_B +#NET "unnamed_net44" LOC = "V6" ; # M2 +#NET "unnamed_net43" LOC = "AA3" ; # M1 +#NET "unnamed_net42" LOC = "AB3" ; # M0 +#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 329d61aa9..f1f491a97 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -11,6 +11,12 @@ module u1e input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C + + output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI + output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI + output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI + output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls inout [15:0] io_tx, inout [15:0] io_rx ); @@ -21,6 +27,15 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + // SPI pins + wire mosi, sclk, miso; + assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; + assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; + assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; + assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), @@ -28,6 +43,7 @@ module u1e .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx) ); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 2645225a0..c74d385ee 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -9,6 +9,8 @@ module u1e_core input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, + output sclk, output [7:0] sen, output mosi, input miso, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx ); @@ -187,14 +189,11 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI - /* spi_top shared_spi (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - */ + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); // ///////////////////////////////////////////////////////////////////////// // Slave 3, I2C @@ -216,7 +215,7 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // GPIOs -- Slave #4 -/* + wire [31:0] atr_lines; wire [31:0] debug_gpio_0, debug_gpio_1; @@ -226,7 +225,7 @@ module u1e_core .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); -*/ + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 @@ -247,7 +246,6 @@ module u1e_core assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; - assign {io_tx,io_rx} = debug_gpmc; assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; -- cgit v1.2.3 From 7a3064b67172aea1be00d188bdd79185a7df2ecf Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 26 Mar 2010 11:30:13 -0700 Subject: connect 2 clock gen controls and 3 status pins to the wishbone so they can be read/controlled from SW --- usrp2/top/u1e/u1e.ucf | 10 +++++----- usrp2/top/u1e/u1e.v | 4 ++++ usrp2/top/u1e/u1e_core.v | 20 +++++++++++++++++--- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 27f507c6b..c39759d0b 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -105,11 +105,11 @@ NET "cgen_sclk" LOC = "R5" ; NET "cgen_sen_b" LOC = "T1" ; ## Clock gen control -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; +NET "cgen_st_status" LOC = "D4" ; +NET "cgen_st_ld" LOC = "D1" ; +NET "cgen_st_refmon" LOC = "E1" ; +NET "cgen_sync_b" LOC = "M1" ; +NET "cgen_ref_sel" LOC = "J1" ; ## Debug pins NET "debug_led<2>" LOC = "T5" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index f1f491a97..ab270879c 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -16,6 +16,8 @@ module u1e output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls inout [15:0] io_tx, inout [15:0] io_rx @@ -44,6 +46,8 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx) ); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index c74d385ee..4f0227dfd 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -10,7 +10,8 @@ module u1e_core inout db_sda, inout db_scl, output sclk, output [7:0] sen, output mosi, input miso, - + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx ); @@ -151,13 +152,15 @@ module u1e_core assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 0, LEDs and Switches + // Slave 0, Misc LEDs, Switches, controls reg [15:0] reg_fast, reg_slow; localparam REG_FAST = 7'd4; localparam REG_SWITCHES = 7'd6; localparam REG_GPIOS = 7'd8; - + localparam REG_CGEN_ST = 7'd9; + localparam REG_CGEN_CTRL = 7'd10; + reg [3:0] reg_gpios; always @(posedge wb_clk) @@ -168,8 +171,19 @@ module u1e_core if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS)) reg_gpios <= s0_dat_mosi; + reg [1:0] reg_cgen_ctrls; + + always @(posedge wb_clk) + if(wb_rst) + reg_cgen_ctrls <= 2'b11; + else if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_CGEN_CTRL)) + reg_cgen_ctrls <= s0_dat_mosi; + + assign {cgen_sync_b, cgen_ref_sel} = reg_cgen_ctrls; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 806a2de4cdd9794f6fba915e32534fd2a0f31cb5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 26 Mar 2010 14:04:22 -0700 Subject: remove timescale junk get rid of asynchronous resets fix spelling error corrected comment --- usrp2/opencores/spi/rtl/verilog/spi_clgen.v | 7 +++---- usrp2/opencores/spi/rtl/verilog/spi_defines.v | 2 +- usrp2/opencores/spi/rtl/verilog/spi_shift.v | 9 ++++----- usrp2/opencores/spi/rtl/verilog/spi_top.v | 20 +++++++++++--------- usrp2/opencores/spi/rtl/verilog/timescale.v | 2 -- 5 files changed, 19 insertions(+), 21 deletions(-) delete mode 100644 usrp2/opencores/spi/rtl/verilog/timescale.v diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v index 3f29f6d7f..2d9c34f40 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v @@ -39,7 +39,6 @@ ////////////////////////////////////////////////////////////////////// `include "spi_defines.v" -`include "timescale.v" module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); @@ -66,7 +65,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; // Counter counts half period - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) cnt <= {`SPI_DIVIDER_LEN{1'b1}}; @@ -80,7 +79,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, end // clk_out is asserted every other half period - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) clk_out <= 1'b0; @@ -89,7 +88,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, end // Pos and neg edge signals - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) begin diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v index 01de2584d..963a680a8 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -137,7 +137,7 @@ `define SPI_TX_2 2 `define SPI_TX_3 3 `define SPI_CTRL 4 -`define SPI_DEVIDE 5 +`define SPI_DIVIDE 5 `define SPI_SS 6 // diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v index c8c73706b..ac3bb3f48 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_shift.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v @@ -39,7 +39,6 @@ ////////////////////////////////////////////////////////////////////// `include "spi_defines.v" -`include "timescale.v" module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, pos_edge, neg_edge, rx_negedge, tx_negedge, @@ -87,7 +86,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; // Character bit counter - always @(posedge clk or posedge rst) + always @(posedge clk) begin if(rst) cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}}; @@ -101,7 +100,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, end // Transfer in progress - always @(posedge clk or posedge rst) + always @(posedge clk) begin if(rst) tip <= 1'b0; @@ -112,7 +111,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, end // Sending bits to the line - always @(posedge clk or posedge rst) + always @(posedge clk) begin if (rst) s_out <= 1'b0; @@ -121,7 +120,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, end // Receiving bits from the line - always @(posedge clk or posedge rst) + always @(posedge clk) begin if (rst) data <= {`SPI_MAX_CHAR{1'b0}}; diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v index 071aeefca..8289449a9 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_top.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v @@ -1,3 +1,6 @@ + +// Modified 2010 by Matt Ettus to remove old verilog style + ////////////////////////////////////////////////////////////////////// //// //// //// spi_top.v //// @@ -40,7 +43,6 @@ `include "spi_defines.v" -`include "timescale.v" module spi_top ( @@ -99,7 +101,7 @@ module spi_top wire last_bit; // marks last character bit // Address decoder - assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE); + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE); assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); @@ -130,14 +132,14 @@ module spi_top `endif `endif `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; - `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; + `SPI_DIVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; default: wb_dat = 32'bx; endcase end // Wb data out - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) wb_dat_o <= 32'b0; @@ -146,7 +148,7 @@ module spi_top end // Wb acknowledge - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) wb_ack_o <= 1'b0; @@ -158,7 +160,7 @@ module spi_top assign wb_err_o = 1'b0; // Interrupt - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) wb_int_o <= 1'b0; @@ -169,7 +171,7 @@ module spi_top end // Divider register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) divider <= {`SPI_DIVIDER_LEN{1'b0}}; @@ -207,7 +209,7 @@ module spi_top end // Ctrl register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; @@ -231,7 +233,7 @@ module spi_top assign ass = ctrl[`SPI_CTRL_ASS]; // Slave select register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) ss <= {`SPI_SS_NB{1'b0}}; diff --git a/usrp2/opencores/spi/rtl/verilog/timescale.v b/usrp2/opencores/spi/rtl/verilog/timescale.v deleted file mode 100644 index 60d4ecbd1..000000000 --- a/usrp2/opencores/spi/rtl/verilog/timescale.v +++ /dev/null @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - -- cgit v1.2.3 From b9e715983eaa625f65f1ac4d18c7fbc9e5ace4cd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 26 Mar 2010 17:12:07 -0700 Subject: connect up the 16 bit spi core --- usrp2/top/u1e/Makefile | 3 +-- usrp2/top/u1e/u1e_core.v | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 3412e227d..2b78b21bd 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -137,8 +137,7 @@ opencores/simple_pic/rtl/simple_pic.v \ opencores/spi/rtl/verilog/spi_clgen.v \ opencores/spi/rtl/verilog/spi_defines.v \ opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ +opencores/spi/rtl/verilog/spi_top16.v \ sdr_lib/acc.v \ sdr_lib/add2.v \ sdr_lib/add2_and_round.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4f0227dfd..f2415d7e1 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -203,9 +203,9 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); -- cgit v1.2.3 From cce4104964c1e1930f85dbb0bb8b8f33086bd75e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 27 Mar 2010 09:20:50 -0700 Subject: 16 bit wide spi core --- usrp2/opencores/spi/rtl/verilog/spi_top16.v | 182 ++++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) create mode 100644 usrp2/opencores/spi/rtl/verilog/spi_top16.v diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top16.v b/usrp2/opencores/spi/rtl/verilog/spi_top16.v new file mode 100644 index 000000000..ee808a8ab --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/spi_top16.v @@ -0,0 +1,182 @@ + +// Modified 2010 by Matt Ettus to remove old verilog style and +// allow 16-bit operation + +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" + +module spi_top16 + (input wb_clk_i, input wb_rst_i, + input [4:0] wb_adr_i, + input [15:0] wb_dat_i, + output reg [15:0] wb_dat_o, + input [1:0] wb_sel_i, + input wb_we_i, input wb_stb_i, input wb_cyc_i, + output reg wb_ack_o, output wb_err_o, output reg wb_int_o, + + // SPI signals + output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); + + // Internal signals + reg [15:0] divider; // Divider register + reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [15:0] ss; // Slave select register + reg [31:0] wb_dat; // wb data out + wire [31:0] rx; // Rx register + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len + wire go; // go + wire lsb; // lsb first on line + wire ie; // interrupt enable + wire ass; // automatic slave select + wire spi_divider_sel; // divider register select + wire spi_ctrl_sel; // ctrl register select + wire [3:0] spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + // Address decoder + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE); + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL); + assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0); + assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1); + assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2); + assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS); + + always @(wb_adr_i or rx or ctrl or divider or ss) + case (wb_adr_i[4:2]) + `SPI_RX_0: wb_dat = rx[31:0]; + `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; + `SPI_DIVIDE: wb_dat = {16'b0, divider}; + `SPI_SS: wb_dat = {16'b0, ss}; + default : wb_dat = 32'd0; + endcase // case (wb_adr_i[4:2]) + + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_dat_o <= 32'b0; + else + wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0]; + + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; + + assign wb_err_o = 1'b0; + + // Interrupt + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_int_o <= 1'b0; + else if (ie && tip && last_bit && pos_edge) + wb_int_o <= 1'b1; + else if (wb_ack_o) + wb_int_o <= 1'b0; + + // Divider register + always @(posedge wb_clk_i) + if (wb_rst_i) + divider <= 16'b0; + else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1]) + divider <= wb_dat_i; + + // Ctrl register + always @(posedge wb_clk_i) + if (wb_rst_i) + ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; + else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1]) + begin + if (wb_sel_i[0]) + ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; + if (wb_sel_i[1]) + ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + end + else if(tip && last_bit && pos_edge) + ctrl[`SPI_CTRL_GO] <= 1'b0; + + assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; + assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; + assign go = ctrl[`SPI_CTRL_GO]; + assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; + assign lsb = ctrl[`SPI_CTRL_LSB]; + assign ie = ctrl[`SPI_CTRL_IE]; + assign ass = ctrl[`SPI_CTRL_ASS]; + + // Slave select register + always @(posedge wb_clk_i) + if (wb_rst_i) + ss <= 16'b0; + else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1]) + begin + if (wb_sel_i[0]) + ss[7:0] <= wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[15:8] <= wb_dat_i[15:8]; + end + + assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}})); + + spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), + .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), + .neg_edge(neg_edge)); + + wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), + (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) }; + + + spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), + .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), + .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), + .tip(tip), .last(last_bit), + .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), + .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); + +endmodule // spi_top16 -- cgit v1.2.3 From 52c8d239ac4b2c448a15b7cc2e2cadf6f296c3e0 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Apr 2010 17:05:50 -0700 Subject: added 16-bit wide atr controller settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits --- usrp2/control_lib/atr_controller16.v | 60 ++++++++++++++++++++++++++++ usrp2/control_lib/nsgpio16LE.v | 23 +++++------ usrp2/control_lib/settings_bus_16LE.v | 4 +- usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e_core.v | 75 ++++++++++++++++++++--------------- 5 files changed, 117 insertions(+), 47 deletions(-) create mode 100644 usrp2/control_lib/atr_controller16.v diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v new file mode 100644 index 000000000..3d8b5b1e9 --- /dev/null +++ b/usrp2/control_lib/atr_controller16.v @@ -0,0 +1,60 @@ + +// Automatic transmit/receive switching of control pins to daughterboards +// Store everything in registers for now, but could use a RAM for more +// complex state machines in the future + +module atr_controller16 + (input clk_i, input rst_i, + input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input run_rx, input run_tx, input [31:0] master_time, + output [31:0] ctrl_lines); + + reg [3:0] state; + reg [31:0] atr_ram [0:15]; // DP distributed RAM + + wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]), + (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) }; + + // WB Interface + always @(posedge clk_i) + if(we_i & stb_i & cyc_i) + begin + if(sel_int[3]) + atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8]; + if(sel_int[2]) + atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0]; + if(sel_int[1]) + atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; + if(sel_int[0]) + atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; + end // if (we_i & stb_i & cyc_i) + + always @(posedge clk_i) + dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + + always @(posedge clk_i) + ack_o <= stb_i & cyc_i & ~ack_o; + + // Control side of DP RAM + assign ctrl_lines = atr_ram[state]; + + // Put a more complex state machine with time delays and multiple states here + // if daughterboard requires more complex sequencing + localparam ATR_IDLE = 4'd0; + localparam ATR_TX = 4'd1; + localparam ATR_RX = 4'd2; + localparam ATR_FULL_DUPLEX = 4'd3; + + always @(posedge clk_i) + if(rst_i) + state <= ATR_IDLE; + else + case ({run_rx,run_tx}) + 2'b00 : state <= ATR_IDLE; + 2'b01 : state <= ATR_TX; + 2'b10 : state <= ATR_RX; + 2'b11 : state <= ATR_FULL_DUPLEX; + endcase // case({run_rx,run_tx}) + +endmodule // atr_controller16 diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v index 6847bb4a9..d6d7dcf56 100644 --- a/usrp2/control_lib/nsgpio16LE.v +++ b/usrp2/control_lib/nsgpio16LE.v @@ -43,10 +43,7 @@ module nsgpio16LE inout [31:0] gpio ); - reg [63:0] ctrl; - reg [31:0] line; - reg [31:0] lgpio; // LatchedGPIO pins - reg [31:0] ddr; + reg [31:0] ctrl, line, ddr, dbg, lgpio; wire wb_acc = cyc_i & stb_i; // WISHBONE access wire wb_wr = wb_acc & we_i; // WISHBONE write access @@ -54,8 +51,10 @@ module nsgpio16LE always @(posedge clk_i or posedge rst_i) if (rst_i) begin - ctrl <= 64'h0; - line <= 0; + ctrl <= 32'h0; + line <= 32'h0; + ddr <= 32'h0; + dbg <= 32'h0; end else if (wb_wr) case( adr_i[3:1] ) @@ -72,9 +71,9 @@ module nsgpio16LE 3'b101 : ctrl[31:16] <= dat_i; 3'b110 : - ctrl[47:32] <= dat_i; + dbg[15:0] <= dat_i; 3'b111 : - ctrl[63:48] <= dat_i; + dbg[31:16] <= dat_i; endcase // case ( adr_i[3:1] ) always @(posedge clk_i) @@ -92,9 +91,9 @@ module nsgpio16LE 3'b101 : dat_o <= ctrl[31:16]; 3'b110 : - dat_o <= ctrl[47:32]; + dat_o <= dbg[15:0]; 3'b111 : - dat_o <= ctrl[63:48]; + dat_o <= dbg[31:16]; endcase // case (adr_i[3:1]) @@ -114,8 +113,8 @@ module nsgpio16LE always @(ctrl or line or debug_1 or debug_0 or atr) for(n=0;n<32;n=n+1) - igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : - (ctrl[2*n] ? atr[n] : line[n]) ) + igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : + (ctrl[n] ? atr[n] : line[n]) ) : 1'bz; assign gpio = igpio; diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v index fbef9b1c9..76061e9e0 100644 --- a/usrp2/control_lib/settings_bus_16LE.v +++ b/usrp2/control_lib/settings_bus_16LE.v @@ -5,7 +5,7 @@ // The setting regs are strobed when the high 16 bits are written module settings_bus_16LE - #(parameter AWIDTH=16) + #(parameter AWIDTH=16, RWIDTH=8) (input wb_clk, input wb_rst, input [AWIDTH-1:0] wb_adr_i, @@ -28,7 +28,7 @@ module settings_bus_16LE end else if(wb_we_i & wb_stb_i) begin - addr <= wb_adr_i[9:2]; + addr <= wb_adr_i[RWIDTH+1:2]; // Zero pad high bits if(wb_adr_i[1]) begin stb_int <= 1'b1; // We now have both halves diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 2b78b21bd..a0f921485 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -54,7 +54,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ export SOURCE_ROOT := ../../../ export SOURCES := \ control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ +control_lib/atr_controller16.v \ control_lib/bin2gray.v \ control_lib/dcache.v \ control_lib/decoder_3_8.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index f2415d7e1..e692cbc3d 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -147,48 +147,52 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s6_ack = 0; assign s7_ack = 0; + assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, Misc LEDs, Switches, controls - reg [15:0] reg_fast, reg_slow; - localparam REG_FAST = 7'd4; - localparam REG_SWITCHES = 7'd6; - localparam REG_GPIOS = 7'd8; - localparam REG_CGEN_ST = 7'd9; - localparam REG_CGEN_CTRL = 7'd10; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test; - reg [3:0] reg_gpios; - - always @(posedge wb_clk) - if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST)) - reg_fast <= s0_dat_mosi; - - always @(posedge wb_clk) - if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS)) - reg_gpios <= s0_dat_mosi; - - reg [1:0] reg_cgen_ctrls; + localparam REG_LEDS = 7'd0; // out + localparam REG_SWITCHES = 7'd2; // in + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out always @(posedge wb_clk) if(wb_rst) - reg_cgen_ctrls <= 2'b11; - else if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_CGEN_CTRL)) - reg_cgen_ctrls <= s0_dat_mosi; + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) - assign {cgen_sync_b, cgen_ref_sel} = reg_cgen_ctrls; + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + assign { rx_overrun, tx_undderun } = reg_test; - assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : 16'hBEEF; + assign s0_ack = s0_stb & s0_cyc; - assign { rx_overrun, tx_underrun } = reg_gpios; - // ///////////////////////////////////////////////////////////////////////////////////// // Slave 1, UART // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock @@ -196,7 +200,7 @@ module u1e_core simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart (.clk_i(wb_clk),.rst_i(wb_rst), .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), - .adr_i(s1_adr[4:2]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), .rx_int_o(),.tx_int_o(), .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); @@ -246,16 +250,25 @@ module u1e_core wire [7:0] set_addr; wire [31:0] set_data; wire set_stb; - - settings_bus_16LE settings_bus_16LE + + // only have 32 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); - // ///////////////////////////////////////////////////////////////////////////////////// - // Debug Pins + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(), .run_tx(), .master_time(0), .ctrl_lines(atr_lines)); + // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry + assign debug_clk = { EM_CLK, clk_fpga }; assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; @@ -263,6 +276,4 @@ module u1e_core assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; - assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board - endmodule // u1e_core -- cgit v1.2.3 From 4aca5e04d026977272e35db4e0c1ccaac5da555f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Apr 2010 19:06:04 -0700 Subject: split out gpmc to wishbone interface to make gpmc top level cleaner --- usrp2/gpmc/gpmc_wb.v | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 usrp2/gpmc/gpmc_wb.v diff --git a/usrp2/gpmc/gpmc_wb.v b/usrp2/gpmc/gpmc_wb.v new file mode 100644 index 000000000..64f6a1c00 --- /dev/null +++ b/usrp2/gpmc/gpmc_wb.v @@ -0,0 +1,57 @@ + + +module gpmc_wb + (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, input EM_NOE, + + input wb_clk, input wb_rst, + output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i); + + // //////////////////////////////////////////// + // Control Path, Wishbone bus bridge (wb master) + reg [1:0] cs_del, we_del, oe_del; + + // Synchronize the async control signals + always @(posedge wb_clk) + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + oe_del <= { oe_del[0], EM_NOE }; + end + + always @(posedge wb_clk) + if(cs_del == 2'b10) // Falling Edge + wb_adr_o <= { EM_A, 1'b0 }; + + always @(posedge wb_clk) + if(we_del == 2'b10) // Falling Edge + begin + wb_dat_mosi <= EM_D; + wb_sel_o <= ~EM_NBE; + end + + reg [15:0] EM_D_hold; + + always @(posedge wb_clk) + if(wb_ack_i) + EM_D_hold <= wb_dat_miso; + + assign EM_D = wb_ack_i ? wb_dat_miso : EM_D_hold; + + assign wb_cyc_o = wb_stb_o; + + always @(posedge wb_clk) + if(~cs_del[0] & (we_del == 2'b10) ) + wb_we_o <= 1; + else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... + wb_we_o <= 0; + + // FIXME should this look at cs_del[1]? + always @(posedge wb_clk) + if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) + wb_stb_o <= 1; + else if(wb_ack_i) + wb_stb_o <= 0; + +endmodule // gpmc_wb -- cgit v1.2.3 From 45b9ec4c39a2f4a3087b2f637f70818fd0efb94e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Apr 2010 19:06:49 -0700 Subject: replaced ram interface with a fifo interface. still need to do rx side --- usrp2/gpmc/gpmc.v | 133 ++++++++++++++++++---------------------------- usrp2/gpmc/gpmc_to_fifo.v | 58 ++++++++++++++++++++ usrp2/top/u1e/u1e_core.v | 46 +++------------- 3 files changed, 117 insertions(+), 120 deletions(-) create mode 100644 usrp2/gpmc/gpmc_to_fifo.v diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index cf1357232..2715414b3 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -10,13 +10,14 @@ module gpmc // Wishbone signals input wb_clk, input wb_rst, - output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, - // RAM Interface signals - input ram_clk, - input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done, - input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done, + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + output [31:0] debug ); @@ -26,94 +27,64 @@ module gpmc assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; - // CS4 is RAM_2PORT for high-speed data - // Writes go into one RAM, reads come from the other - + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) // //////////////////////////////////////////// - // Write path - wire read_sel_in, write_sel_in, clear_in; - wire write_done_in; - - edge_sync #(.POSEDGE(0)) - edge_sync_wdi(.clk(wb_clk), .rst(wb_rst), - .sig(~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF)), .trig(write_done_in)); - - ram_2port_mixed_width buffer_in - (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({write_sel_in,EM_A}), .di16(EM_D), .do16(), - .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel_in,read_addr}), .di32(0), .do32(read_data)); + // TX Data Path - dbsm dbsm_in(.clk(wb_clk), .reset(wb_rst), .clear(clear_in), - .read_sel(read_sel_in), .read_ready(read_ready), .read_done(read_done), - .write_sel(write_sel_in), .write_ready(tx_have_space), .write_done(write_done_in)); + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space, tx_frame_len; + assign tx_frame_len = 10; + + gpmc_to_fifo gpmc_to_fifo + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space)); + fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy)); + + fifo19_to_fifo36 f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + // //////////////////////////////////////////// - // Read path - wire read_sel_out, write_sel_out, clear_out; - wire read_done_out; + // RX Data Path + wire read_sel_rx, write_sel_rx, clear_rx; + wire read_done_rx; edge_sync #(.POSEDGE(0)) - edge_sync_rdo(.clk(wb_clk), .rst(wb_rst), - .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_out)); + edge_sync_rx(.clk(wb_clk), .rst(wb_rst), + .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_rx)); - ram_2port_mixed_width buffer_out - (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_out,EM_A}), .di16(0), .do16(EM_D_ram), - .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_out,write_addr}), .di32(write_data), .do32()); - - dbsm dbsm_out(.clk(wb_clk), .reset(wb_rst), .clear(clear_out), - .read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out), - .write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done)); + ram_2port_mixed_width buffer_rx + (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_rx,EM_A}), .di16(0), .do16(EM_D_ram), + .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_rx,write_addr}), .di32(write_data), .do32()); + dbsm dbsm_rx(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .read_sel(read_sel_rx), .read_ready(rx_have_data), .read_done(read_done_rx), + .write_sel(write_sel_rx), .write_ready(write_ready), .write_done(write_done)); - assign debug = { { 2'b00, write_done_in, write_sel_in, read_en, read_sel_in, read_ready, read_done}, - { 2'b00, read_sel_out, write_en, write_sel_out, read_done_out, write_ready, write_done }, - { 8'd0 }, - { 8'd0 } }; + // //////////////////////////////////////////// + // Control path on CS6 - // CS6 is Control, Wishbone bus bridge (wb master) - // Sync version - reg [1:0] cs_del, we_del, oe_del; - - // Synchronize the async control signals - always @(posedge wb_clk) - begin - cs_del <= { cs_del[0], EM_NCS6 }; - we_del <= { we_del[0], EM_NWE }; - oe_del <= { oe_del[0], EM_NOE }; - end - - always @(posedge wb_clk) - if(cs_del == 2'b10) // Falling Edge - wb_adr_o <= { EM_A, 1'b0 }; - - always @(posedge wb_clk) - if(we_del == 2'b10) // Falling Edge - begin - wb_dat_mosi <= EM_D; - wb_sel_o <= ~EM_NBE; - end - - reg [15:0] EM_D_wb_reg; - always @(posedge wb_clk) - if(wb_ack_i) - EM_D_wb_reg <= wb_dat_miso; - - assign EM_D_wb = wb_ack_i ? wb_dat_miso : EM_D_wb_reg; + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); - assign wb_cyc_o = wb_stb_o; - - always @(posedge wb_clk) - if(~cs_del[0] & (we_del == 2'b10) ) - wb_we_o <= 1; - else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... - wb_we_o <= 0; - - always @(posedge wb_clk) - if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) - wb_stb_o <= 1; - else if(wb_ack_i) - wb_stb_o <= 0; + assign debug = 0; endmodule // gpmc diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v new file mode 100644 index 000000000..5d499494f --- /dev/null +++ b/usrp2/gpmc/gpmc_to_fifo.v @@ -0,0 +1,58 @@ + +module gpmc_to_fifo + (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, + + input fifo_clk, input fifo_rst, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); + + // Synchronize the async control signals + reg [1:0] cs_del, we_del; + always @(posedge fifo_clk) + if(fifo_rst) + begin + cs_del <= 2'b11; + we_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + end + + wire do_write = (~cs_del[0] & (we_del == 2'b10)); + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + + always @(posedge fifo_clk) + if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge fifo_clk) + if(fifo_rst) + src_rdy_o <= 0; + else if(do_write) + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken + + reg [10:0] counter; + always @(posedge fifo_clk) + if(fifo_rst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + +endmodule // gpmc_to_fifo diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e692cbc3d..e5e5285bd 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -30,15 +30,8 @@ module u1e_core wire [sw-1:0] m0_sel; wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; - // FIFO buffers - wire [31:0] read_data, write_data; - wire [8:0] read_addr, write_addr; - reg [8:0] addr; - - wire read_done, write_done, read_en, write_en, read_ready, write_ready; - wire [31:0] debug_gpmc; - + gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), @@ -50,37 +43,12 @@ module u1e_core .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), .wb_ack_i(m0_ack), - .ram_clk(wb_clk), - .read_en(read_en), .read_addr(read_addr), .read_data(read_data), - .read_ready(read_ready), .read_done(read_done), - .write_en(write_en), .write_addr(write_addr), .write_data(write_data), - .write_ready(write_ready), .write_done(write_done), + .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .tx_data_o(), .tx_src_rdy_o(), .tx_dst_rdy_i(0), + .rx_data_i(0), .rx_src_rdy_i(0), .rx_dst_rdy_o(), + .debug(debug_gpmc)); - // Loopback - assign write_data = read_data; - - reg [10:0] counter; - assign write_addr = counter[10:2]; - assign read_addr = counter[10:2]; - - assign read_done = (counter == 11'h7FF); - assign write_done = (counter == 11'h7FF); - - always @(posedge wb_clk) - if(wb_rst) - counter <= 0; - else - if(counter == 0) - counter <= write_ready & read_ready; - else if(counter == 11'h7FF) - counter <= 0; - else - counter <= counter + 1; - - assign read_en = (counter[1:0] == 1); - assign write_en = (counter[1:0] == 2); - // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master @@ -182,7 +150,7 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - assign { rx_overrun, tx_undderun } = reg_test; + assign { rx_overrun, tx_underrun } = reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : @@ -210,7 +178,7 @@ module u1e_core spi_top16 shared_spi (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From f95bf4d8d94511d26a5bb1f52823f8ffd5f637fe Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Apr 2010 19:20:22 -0700 Subject: lengthened delay between cycles, added more transactions on the data bus --- usrp2/models/gpmc_model.v | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v index 3424671bd..6066ede6e 100644 --- a/usrp2/models/gpmc_model.v +++ b/usrp2/models/gpmc_model.v @@ -41,7 +41,7 @@ module gpmc_model EM_NCS6 <= 1; //#1.5; EM_NWE <= 1; - #6; + #60; EM_A <= 10'bz; EM_D_int <= 16'bz; end @@ -82,7 +82,12 @@ module gpmc_model GPMC_Write(0,38,16'h5678); GPMC_Write(0,40,16'h9abc); GPMC_Write(0,11'h2F4,16'hF00D); - GPMC_Write(0,11'h7FE,16'hF00D); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); #100000; $finish; end -- cgit v1.2.3 From 19d476df81cdf7a51b871154510be8f7c575ffde Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 13 Apr 2010 17:33:16 -0700 Subject: minor changes to get it to synthesize --- usrp2/gpmc/gpmc_to_fifo.v | 2 +- usrp2/top/u1e/Makefile | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v index 5d499494f..267804469 100644 --- a/usrp2/gpmc/gpmc_to_fifo.v +++ b/usrp2/gpmc/gpmc_to_fifo.v @@ -8,6 +8,7 @@ module gpmc_to_fifo input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); + reg [10:0] counter; // Synchronize the async control signals reg [1:0] cs_del, we_del; always @(posedge fifo_clk) @@ -43,7 +44,6 @@ module gpmc_to_fifo else src_rdy_o <= 0; // Assume it was taken - reg [10:0] counter; always @(posedge fifo_clk) if(fifo_rst) counter <= 0; diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index a0f921485..1cb56d7a9 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -109,6 +109,7 @@ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ @@ -177,6 +178,8 @@ timing/timer.v \ gpmc/gpmc.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ +gpmc/gpmc_to_fifo.v \ +gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/u1e.v -- cgit v1.2.3 From 8cef80c8ebb9b59f1fe65971c9066fd832ab2504 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 18:01:28 -0700 Subject: probably won't be using this, and it hasn't been tested --- usrp2/gpmc/ram_to_fifo.v | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 usrp2/gpmc/ram_to_fifo.v diff --git a/usrp2/gpmc/ram_to_fifo.v b/usrp2/gpmc/ram_to_fifo.v new file mode 100644 index 000000000..8549dcc35 --- /dev/null +++ b/usrp2/gpmc/ram_to_fifo.v @@ -0,0 +1,46 @@ + + +module ram_to_fifo + (input clk, input reset, + input [10:0] read_length, // From the dbsm (?) + output read_en, output reg [8:0] read_addr, input [31:0] read_data, input read_ready, output read_done, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + // read_length/2 = number of 32 bit lines, numbered 0 through read_length/2-1 + wire [8:0] last_line = (read_length[10:1]-1); + + reg read_phase, sop; + + assign read_en = (read_phase == 0) | dst_rdy_i; + assign src_rdy_o = (read_phase == 1); + + always @(posedge clk) + if(reset) + begin + read_addr <= 0; + read_phase <= 0; + sop <= 1; + end + else + if(read_phase == 0) + begin + read_addr <= read_ready; + read_phase <= read_ready; + end + else if(dst_rdy_i) + begin + sop <= 0; + if(read_addr == last_line) + begin + read_addr <= 0; + read_phase <= 0; + end + else + read_addr <= read_addr + 1; + end + + assign read_done = (read_phase == 1) & (read_addr == last_line) & dst_rdy_i; + wire eop = (read_addr == last_line); + assign data_o = { 2'b00, eop, sop, read_data }; + +endmodule // ram_to_fifo -- cgit v1.2.3 From 17fc80cb82309879dd2b1dc03681058dd432327b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 18:02:29 -0700 Subject: added in a loopback fifo --- usrp2/top/u1e/u1e_core.v | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e5e5285bd..7df7b0a48 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -32,6 +32,9 @@ module u1e_core wire [31:0] debug_gpmc; + wire [35:0] tx_data, rx_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; + gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), @@ -44,12 +47,16 @@ module u1e_core .wb_ack_i(m0_ack), .fifo_clk(wb_clk), .fifo_rst(wb_rst), - .tx_data_o(), .tx_src_rdy_o(), .tx_dst_rdy_i(0), - .rx_data_i(0), .rx_src_rdy_i(0), .rx_dst_rdy_o(), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), .debug(debug_gpmc)); - - + + fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, -- cgit v1.2.3 From fc54a55f97171f5714c370d566f31429ce112e89 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 18:07:00 -0700 Subject: make timing diagrams for bus transactions. Still need to do reads --- usrp2/gpmc/.gitignore | 2 ++ usrp2/gpmc/burst_data_write.txt | 16 ++++++++++++++++ usrp2/gpmc/make_timing_diag | 6 ++++++ usrp2/gpmc/single_data_read.txt | 12 ++++++++++++ usrp2/gpmc/single_data_write.txt | 10 ++++++++++ 5 files changed, 46 insertions(+) create mode 100644 usrp2/gpmc/.gitignore create mode 100644 usrp2/gpmc/burst_data_write.txt create mode 100755 usrp2/gpmc/make_timing_diag create mode 100644 usrp2/gpmc/single_data_read.txt create mode 100644 usrp2/gpmc/single_data_write.txt diff --git a/usrp2/gpmc/.gitignore b/usrp2/gpmc/.gitignore new file mode 100644 index 000000000..3e14fa4f7 --- /dev/null +++ b/usrp2/gpmc/.gitignore @@ -0,0 +1,2 @@ +*.gif + diff --git a/usrp2/gpmc/burst_data_write.txt b/usrp2/gpmc/burst_data_write.txt new file mode 100644 index 000000000..3b5dfc785 --- /dev/null +++ b/usrp2/gpmc/burst_data_write.txt @@ -0,0 +1,16 @@ +# OMAP burst writes to FPGA + +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA1. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA2. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA3. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA4. +CLK=1. +CLK=0,nWE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/usrp2/gpmc/make_timing_diag b/usrp2/gpmc/make_timing_diag new file mode 100755 index 000000000..03166ad35 --- /dev/null +++ b/usrp2/gpmc/make_timing_diag @@ -0,0 +1,6 @@ +#!/bin/sh +drawtiming -o single_data_write.gif single_data_write.txt +drawtiming -o single_data_read.gif single_data_read.txt +drawtiming -o burst_data_write.gif burst_data_write.txt +#drawtiming -o burst_data_read.gif burst_data_read.txt + diff --git a/usrp2/gpmc/single_data_read.txt b/usrp2/gpmc/single_data_read.txt new file mode 100644 index 000000000..1dc0e3a78 --- /dev/null +++ b/usrp2/gpmc/single_data_read.txt @@ -0,0 +1,12 @@ +# OMAP writes to FPGA +# initialize the signals +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nOE=0,nCS=0,DATA=RD_DATA. +CLK=1. +CLK=0. +CLK=1. +CLK=0,nOE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/usrp2/gpmc/single_data_write.txt b/usrp2/gpmc/single_data_write.txt new file mode 100644 index 000000000..287e3e2c1 --- /dev/null +++ b/usrp2/gpmc/single_data_write.txt @@ -0,0 +1,10 @@ +# OMAP writes to FPGA +# initialize the signals +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA. +CLK=1. +CLK=0,nWE=1,nCS=1,DATA=Z. +CLK=1. + + -- cgit v1.2.3 From 204c591cd478958b4e2ddea4c61d3908d9520bbe Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 18:13:49 -0700 Subject: renamed to async. Will be building a sync version for GPMC_CLK --- usrp2/gpmc/gpmc_to_fifo.v | 58 ----------------------------------------- usrp2/gpmc/gpmc_to_fifo_async.v | 58 +++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 2 +- 3 files changed, 59 insertions(+), 59 deletions(-) delete mode 100644 usrp2/gpmc/gpmc_to_fifo.v create mode 100644 usrp2/gpmc/gpmc_to_fifo_async.v diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v deleted file mode 100644 index 267804469..000000000 --- a/usrp2/gpmc/gpmc_to_fifo.v +++ /dev/null @@ -1,58 +0,0 @@ - -module gpmc_to_fifo - (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, - input EM_NCS, input EM_NWE, - - input fifo_clk, input fifo_rst, - output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, - - input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); - - reg [10:0] counter; - // Synchronize the async control signals - reg [1:0] cs_del, we_del; - always @(posedge fifo_clk) - if(fifo_rst) - begin - cs_del <= 2'b11; - we_del <= 2'b11; - end - else - begin - cs_del <= { cs_del[0], EM_NCS }; - we_del <= { we_del[0], EM_NWE }; - end - - wire do_write = (~cs_del[0] & (we_del == 2'b10)); - wire first_write = (counter == 0); - wire last_write = ((counter+1) == frame_len); - - always @(posedge fifo_clk) - if(do_write) - begin - data_o[15:0] <= EM_D; - data_o[16] <= first_write; - data_o[17] <= last_write; - // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME - end - - always @(posedge fifo_clk) - if(fifo_rst) - src_rdy_o <= 0; - else if(do_write) - src_rdy_o <= 1; - else - src_rdy_o <= 0; // Assume it was taken - - always @(posedge fifo_clk) - if(fifo_rst) - counter <= 0; - else if(do_write) - if(last_write) - counter <= 0; - else - counter <= counter + 1; - - assign fifo_ready = first_write & (fifo_space > frame_len); - -endmodule // gpmc_to_fifo diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v new file mode 100644 index 000000000..c47d69d7d --- /dev/null +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -0,0 +1,58 @@ + +module gpmc_to_fifo_async + (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, + + input fifo_clk, input fifo_rst, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); + + reg [10:0] counter; + // Synchronize the async control signals + reg [1:0] cs_del, we_del; + always @(posedge fifo_clk) + if(fifo_rst) + begin + cs_del <= 2'b11; + we_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + end + + wire do_write = (~cs_del[0] & (we_del == 2'b10)); + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + + always @(posedge fifo_clk) + if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge fifo_clk) + if(fifo_rst) + src_rdy_o <= 0; + else if(do_write) + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken + + always @(posedge fifo_clk) + if(fifo_rst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + +endmodule // gpmc_to_fifo_async diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 1cb56d7a9..ca4d9ce89 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -178,7 +178,7 @@ timing/timer.v \ gpmc/gpmc.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ -gpmc/gpmc_to_fifo.v \ +gpmc/gpmc_to_fifo_async.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ -- cgit v1.2.3 From 108109e649397147ecf6f5d6b82bdb3d5b852539 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 19:14:46 -0700 Subject: more progress on synchronous interface --- usrp2/gpmc/gpmc.v | 61 ++++++++++++++++++++++++----------------- usrp2/gpmc/gpmc_to_fifo_async.v | 2 +- usrp2/gpmc/gpmc_to_fifo_sync.v | 57 ++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 1 + 4 files changed, 95 insertions(+), 26 deletions(-) create mode 100644 usrp2/gpmc/gpmc_to_fifo_sync.v diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 2715414b3..d6a685bba 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -4,7 +4,8 @@ module gpmc (// GPMC signals input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - + output bus_error, + // GPIOs for FIFO signalling output rx_have_data, output tx_have_space, @@ -17,15 +18,15 @@ module gpmc input fifo_clk, input fifo_rst, output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - + output [31:0] debug ); wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); - wire [15:0] EM_D_ram; + wire [15:0] EM_D_fifo; wire [15:0] EM_D_wb; - assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; // CS4 is RAM_2PORT for DATA PATH (high-speed data) // Writes go into one RAM, reads come from the other @@ -37,19 +38,22 @@ module gpmc wire [17:0] tx18_data, tx18b_data; wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; wire [15:0] tx_fifo_space, tx_frame_len; - + assign tx_frame_len = 10; + wire arst; - gpmc_to_fifo gpmc_to_fifo - (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + gpmc_to_fifo_sync gpmc_to_fifo_sync + (.arst(arst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), - .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space)); + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error) ); - fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), - .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy)); + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.wclk(EM_CLK), .datain(tx18_data), + .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .rclk(fifo_clk), .dataout(tx18b_data), + .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); fifo19_to_fifo36 f19_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), @@ -59,21 +63,28 @@ module gpmc // //////////////////////////////////////////// // RX Data Path - wire read_sel_rx, write_sel_rx, clear_rx; - wire read_done_rx; - - edge_sync #(.POSEDGE(0)) - edge_sync_rx(.clk(wb_clk), .rst(wb_rst), - .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_rx)); + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space, rx_frame_len; - ram_2port_mixed_width buffer_rx - (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_rx,EM_A}), .di16(0), .do16(EM_D_ram), - .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_rx,write_addr}), .di32(write_data), .do32()); + fifo36_to_fifo18 f18_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); - dbsm dbsm_rx(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .read_sel(read_sel_rx), .read_ready(rx_have_data), .read_done(read_done_rx), - .write_sel(write_sel_rx), .write_ready(write_ready), .write_done(write_done)); + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + (.wclk(fifo_clk), .datain(rx18_data), + .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .rclk(EM_CLK), .dataout(rx18b_data), + .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); + fifo_to_gpmc_sync fifo_to_gpmc_sync + (.arst(arst), + .data_i(tx18b_data), .src_rdy_i(tx18b_src_rdy), .dst_rdy_o(tx18b_dst_rdy), + .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .fifo_ready(rx_have_data) ); + // //////////////////////////////////////////// // Control path on CS6 diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index c47d69d7d..a8068022f 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -1,6 +1,6 @@ module gpmc_to_fifo_async - (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, input fifo_clk, input fifo_rst, diff --git a/usrp2/gpmc/gpmc_to_fifo_sync.v b/usrp2/gpmc/gpmc_to_fifo_sync.v new file mode 100644 index 000000000..688de0e17 --- /dev/null +++ b/usrp2/gpmc/gpmc_to_fifo_sync.v @@ -0,0 +1,57 @@ + +// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module gpmc_to_fifo_sync + (input arst, + input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, + output reg bus_error); + + reg [10:0] counter; + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + wire do_write = ~EM_NCS & ~EM_NWE; + + always @(posedge EM_CLK or posedge arst) + if(arst) + data_o <= 0; + else if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge EM_CLK or posedge arst) + if(arst) + src_rdy_o <= 0; + else if(do_write & ~bus_error) // Don't put junk in if there is a bus error + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i + + always @(posedge EM_CLK or posedge arst) + if(arst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + + always @(posedge EM_CLK or posedge arst) + if(arst) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; + // must be reset to make the error go away + +endmodule // gpmc_to_fifo_sync diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index ca4d9ce89..057de64cf 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -179,6 +179,7 @@ gpmc/gpmc.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ gpmc/gpmc_to_fifo_async.v \ +gpmc/gpmc_to_fifo_sync.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ -- cgit v1.2.3 From f89ed91930f5933c827726d17b8c5b0313b6c297 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 19:16:47 -0700 Subject: more sync progress. This is just a skeleton for now, with junk content --- usrp2/gpmc/fifo_to_gpmc_sync.v | 56 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 usrp2/gpmc/fifo_to_gpmc_sync.v diff --git a/usrp2/gpmc/fifo_to_gpmc_sync.v b/usrp2/gpmc/fifo_to_gpmc_sync.v new file mode 100644 index 000000000..647a507b4 --- /dev/null +++ b/usrp2/gpmc/fifo_to_gpmc_sync.v @@ -0,0 +1,56 @@ + +// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module fifo_to_gpmc_sync + (input arst, + input [17:0] data_i, input src_rdy_i, output reg dst_rdy_o, + input EM_CLK, inout [15:0] EM_D, input EM_NCS, input EM_NOE, + output fifo_ready, + output reg bus_error); + + reg [10:0] counter; + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + wire do_write = ~EM_NCS & ~EM_NWE; + + always @(posedge EM_CLK or posedge arst) + if(arst) + data_o <= 0; + else if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge EM_CLK or posedge arst) + if(arst) + src_rdy_o <= 0; + else if(do_write & ~bus_error) // Don't put junk in if there is a bus error + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i + + always @(posedge EM_CLK or posedge arst) + if(arst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + + always @(posedge EM_CLK or posedge arst) + if(arst) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; + // must be reset to make the error go away + +endmodule // fifo_to_gpmc_sync -- cgit v1.2.3 From 7d00d3a7b93d53b2f60107f0e43645d35788cf2f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 12:52:18 -0700 Subject: handle all tri-state in the top level of gpmc --- usrp2/gpmc/gpmc.v | 6 +++--- usrp2/gpmc/gpmc_wb.v | 6 +++--- usrp2/top/u1e/Makefile | 2 ++ 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index d6a685bba..93308a2d2 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -77,11 +77,11 @@ module gpmc (.wclk(fifo_clk), .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), .rclk(EM_CLK), .dataout(rx18b_data), - .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); + .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst)); fifo_to_gpmc_sync fifo_to_gpmc_sync (.arst(arst), - .data_i(tx18b_data), .src_rdy_i(tx18b_src_rdy), .dst_rdy_o(tx18b_dst_rdy), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), .fifo_ready(rx_have_data) ); @@ -89,7 +89,7 @@ module gpmc // Control path on CS6 gpmc_wb gpmc_wb - (.EM_CLK(EM_CLK), .EM_D(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), diff --git a/usrp2/gpmc/gpmc_wb.v b/usrp2/gpmc/gpmc_wb.v index 64f6a1c00..db6fbc6e9 100644 --- a/usrp2/gpmc/gpmc_wb.v +++ b/usrp2/gpmc/gpmc_wb.v @@ -1,7 +1,7 @@ module gpmc_wb - (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, input EM_NOE, input wb_clk, input wb_rst, @@ -27,7 +27,7 @@ module gpmc_wb always @(posedge wb_clk) if(we_del == 2'b10) // Falling Edge begin - wb_dat_mosi <= EM_D; + wb_dat_mosi <= EM_D_in; wb_sel_o <= ~EM_NBE; end @@ -37,7 +37,7 @@ module gpmc_wb if(wb_ack_i) EM_D_hold <= wb_dat_miso; - assign EM_D = wb_ack_i ? wb_dat_miso : EM_D_hold; + assign EM_D_out = wb_ack_i ? wb_dat_miso : EM_D_hold; assign wb_cyc_o = wb_stb_o; diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 057de64cf..160e67894 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -109,6 +109,7 @@ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/fifo36_to_fifo18.v \ control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ @@ -180,6 +181,7 @@ gpmc/edge_sync.v \ gpmc/dbsm.v \ gpmc/gpmc_to_fifo_async.v \ gpmc/gpmc_to_fifo_sync.v \ +gpmc/fifo_to_gpmc_sync.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ -- cgit v1.2.3 From d7342b46abac60bf4e2811ac4798dc4e06b5844f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 14:51:41 -0700 Subject: synchronous and asynchronous gpmc models --- usrp2/models/gpmc_model.v | 95 ---------------------------------------- usrp2/models/gpmc_model_async.v | 95 ++++++++++++++++++++++++++++++++++++++++ usrp2/models/gpmc_model_sync.v | 97 +++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/tb_u1e.v | 2 +- 4 files changed, 193 insertions(+), 96 deletions(-) delete mode 100644 usrp2/models/gpmc_model.v create mode 100644 usrp2/models/gpmc_model_async.v create mode 100644 usrp2/models/gpmc_model_sync.v diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v deleted file mode 100644 index 6066ede6e..000000000 --- a/usrp2/models/gpmc_model.v +++ /dev/null @@ -1,95 +0,0 @@ - - -module gpmc_model - (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, - output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, - output reg EM_NWE, output reg EM_NOE ); - - assign EM_CLK = 0; - reg [15:0] EM_D_int; - assign EM_D = EM_D_int; - - initial - begin - EM_A <= 10'bz; - EM_NBE <= 2'b11; - EM_NWE <= 1; - EM_NOE <= 1; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - EM_D_int <= 16'bz; - EM_WAIT0 <= 0; // FIXME this is actually an input - end - - task GPMC_Write; - input ctrl; - input [10:0] addr; - input [15:0] data; - begin - #2.3; - EM_A <= addr[10:1]; - EM_D_int <= data; - #2.01; - if(ctrl) - EM_NCS6 <= 0; - else - EM_NCS4 <= 0; - #14; - EM_NWE <= 0; - #77.5; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - //#1.5; - EM_NWE <= 1; - #60; - EM_A <= 10'bz; - EM_D_int <= 16'bz; - end - endtask // GPMC_Write - - task GPMC_Read; - input ctrl; - input [10:0] addr; - begin - #1.3; - EM_A <= addr[10:1]; - #3; - if(ctrl) - EM_NCS6 <= 0; - else - EM_NCS4 <= 0; - #14; - EM_NOE <= 0; - #77.5; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - //#1.5; - $display("Data Read from GPMC: %X",EM_D); - EM_NOE <= 1; - #254; - EM_A <= 10'bz; - end - endtask // GPMC_Read - - initial - begin - #1000; - GPMC_Write(1,36,16'hF00D); - #1000; - GPMC_Read(1,36); - #1000; - GPMC_Write(0,36,16'h1234); - GPMC_Write(0,38,16'h5678); - GPMC_Write(0,40,16'h9abc); - GPMC_Write(0,11'h2F4,16'hF00D); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - #100000; - $finish; - end - -endmodule // gpmc_model diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v new file mode 100644 index 000000000..a63a5a8fd --- /dev/null +++ b/usrp2/models/gpmc_model_async.v @@ -0,0 +1,95 @@ + + +module gpmc_model_async + (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + assign EM_CLK = 0; + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input ctrl; + input [10:0] addr; + input [15:0] data; + begin + #2.3; + EM_A <= addr[10:1]; + EM_D_int <= data; + #2.01; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14; + EM_NWE <= 0; + #77.5; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + EM_NWE <= 1; + #60; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + end + endtask // GPMC_Write + + task GPMC_Read; + input ctrl; + input [10:0] addr; + begin + #1.3; + EM_A <= addr[10:1]; + #3; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14; + EM_NOE <= 0; + #77.5; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254; + EM_A <= 10'bz; + end + endtask // GPMC_Read + + initial + begin + #1000; + GPMC_Write(1,36,16'hF00D); + #1000; + GPMC_Read(1,36); + #1000; + GPMC_Write(0,36,16'h1234); + GPMC_Write(0,38,16'h5678); + GPMC_Write(0,40,16'h9abc); + GPMC_Write(0,11'h2F4,16'hF00D); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + #100000; + $finish; + end + +endmodule // gpmc_model_async diff --git a/usrp2/models/gpmc_model_sync.v b/usrp2/models/gpmc_model_sync.v new file mode 100644 index 000000000..641720c15 --- /dev/null +++ b/usrp2/models/gpmc_model_sync.v @@ -0,0 +1,97 @@ + + +module gpmc_model_sync + (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_CLK <= 0; + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input ctrl; + input [10:0] addr; + input [15:0] data; + begin + EM_CLK <= 1; + #10; + EM_CLK <= 0; + EM_NWE <= 0; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + EM_A <= addr[10:1]; + EM_D_int <= data; + #10; + EM_CLK <= 1; + #10; + EM_CLK <= 0; + EM_NWE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + #100; + end + endtask // GPMC_Write + + task GPMC_Read; + input ctrl; + input [10:0] addr; + begin + #1.3; + EM_A <= addr[10:1]; + #3; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14; + EM_NOE <= 0; + #77.5; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254; + EM_A <= 10'bz; + end + endtask // GPMC_Read + + initial + begin + #1000; + GPMC_Write(1,36,16'hF00D); + #1000; + GPMC_Read(1,36); + #1000; + GPMC_Write(0,36,16'h1234); + GPMC_Write(0,38,16'h5678); + GPMC_Write(0,40,16'h9abc); + GPMC_Write(0,11'h2F4,16'hF00D); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + #100000; + $finish; + end + +endmodule // gpmc_model diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 3cae74c8a..31e4fcb69 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -33,7 +33,7 @@ module tb_u1e(); .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - gpmc_model gpmc_model + gpmc_model_async gpmc_model_async (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); -- cgit v1.2.3 From 6dd46af16008e46ee8830748194bbc2a1df9fdf3 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 14:56:19 -0700 Subject: progress on synchronous gpmc, but it may not be possible due to the limited number of clock edges --- usrp2/gpmc/fifo_to_gpmc_sync.v | 44 +++-------------- usrp2/gpmc/fifo_watcher.v | 26 ++++++++++ usrp2/gpmc/gpmc.v | 101 -------------------------------------- usrp2/gpmc/gpmc_sync.v | 107 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 140 insertions(+), 138 deletions(-) create mode 100644 usrp2/gpmc/fifo_watcher.v delete mode 100644 usrp2/gpmc/gpmc.v create mode 100644 usrp2/gpmc/gpmc_sync.v diff --git a/usrp2/gpmc/fifo_to_gpmc_sync.v b/usrp2/gpmc/fifo_to_gpmc_sync.v index 647a507b4..ef59d7137 100644 --- a/usrp2/gpmc/fifo_to_gpmc_sync.v +++ b/usrp2/gpmc/fifo_to_gpmc_sync.v @@ -6,51 +6,21 @@ module fifo_to_gpmc_sync (input arst, - input [17:0] data_i, input src_rdy_i, output reg dst_rdy_o, - input EM_CLK, inout [15:0] EM_D, input EM_NCS, input EM_NOE, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + input EM_CLK, output [15:0] EM_D, input EM_NCS, input EM_NOE, output fifo_ready, output reg bus_error); - - reg [10:0] counter; - wire first_write = (counter == 0); - wire last_write = ((counter+1) == frame_len); - wire do_write = ~EM_NCS & ~EM_NWE; - - always @(posedge EM_CLK or posedge arst) - if(arst) - data_o <= 0; - else if(do_write) - begin - data_o[15:0] <= EM_D; - data_o[16] <= first_write; - data_o[17] <= last_write; - // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME - end - always @(posedge EM_CLK or posedge arst) - if(arst) - src_rdy_o <= 0; - else if(do_write & ~bus_error) // Don't put junk in if there is a bus error - src_rdy_o <= 1; - else - src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i + assign EM_D = data_i[15:0]; + wire read_access = ~EM_NCS & ~EM_NOE; - always @(posedge EM_CLK or posedge arst) - if(arst) - counter <= 0; - else if(do_write) - if(last_write) - counter <= 0; - else - counter <= counter + 1; + assign dst_rdy_o = read_access; - assign fifo_ready = first_write & (fifo_space > frame_len); - always @(posedge EM_CLK or posedge arst) if(arst) bus_error <= 0; - else if(src_rdy_o & ~dst_rdy_i) + else if(dst_rdy_o & ~src_rdy_i) bus_error <= 1; - // must be reset to make the error go away + endmodule // fifo_to_gpmc_sync diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v new file mode 100644 index 000000000..8b8f1abfb --- /dev/null +++ b/usrp2/gpmc/fifo_watcher.v @@ -0,0 +1,26 @@ + + +module fifo_watcher + (input clk, input reset, input clear, + input src_rdy, input dst_rdy, input sof, input eof, + output have_packet, output [15:0] length, input next); + + wire write = src_rdy & dst_rdy & eof; + + fifo_short #(.WIDTH(16)) frame_lengths + (.clk(clk), .reset(reset), .clear(clear), + .datain(counter), .src_rdy_i(write), .dst_rdy_o(), + .dataout(length), .src_rdy_o(have_packet), .dst_rdy_i(next) ); + + reg [15:0] counter; + always @(posedge clk) + if(reset | clear) + counter <= 1; // Start at 1 + else if(src_rdy & dst_rdy) + if(eof) + counter <= 1; + else + counter <= counter + 1; + + +endmodule // fifo_watcher diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v deleted file mode 100644 index 93308a2d2..000000000 --- a/usrp2/gpmc/gpmc.v +++ /dev/null @@ -1,101 +0,0 @@ -////////////////////////////////////////////////////////////////////////////////// - -module gpmc - (// GPMC signals - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - output bus_error, - - // GPIOs for FIFO signalling - output rx_have_data, output tx_have_space, - - // Wishbone signals - input wb_clk, input wb_rst, - output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, - - // FIFO interface - input fifo_clk, input fifo_rst, - output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, - input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - - output [31:0] debug - ); - - wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); - wire [15:0] EM_D_fifo; - wire [15:0] EM_D_wb; - - assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; - - // CS4 is RAM_2PORT for DATA PATH (high-speed data) - // Writes go into one RAM, reads come from the other - // CS6 is for CONTROL PATH (wishbone) - - // //////////////////////////////////////////// - // TX Data Path - - wire [17:0] tx18_data, tx18b_data; - wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; - wire [15:0] tx_fifo_space, tx_frame_len; - - assign tx_frame_len = 10; - wire arst; - - gpmc_to_fifo_sync gpmc_to_fifo_sync - (.arst(arst), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), - .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), - .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), - .bus_error(bus_error) ); - - fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo - (.wclk(EM_CLK), .datain(tx18_data), - .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), - .rclk(fifo_clk), .dataout(tx18b_data), - .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); - - fifo19_to_fifo36 f19_to_f36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), - .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); - - - // //////////////////////////////////////////// - // RX Data Path - - wire [17:0] rx18_data, rx18b_data; - wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; - wire [15:0] rx_fifo_space, rx_frame_len; - - fifo36_to_fifo18 f18_to_f36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), - .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); - - fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo - (.wclk(fifo_clk), .datain(rx18_data), - .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), - .rclk(EM_CLK), .dataout(rx18b_data), - .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst)); - - fifo_to_gpmc_sync fifo_to_gpmc_sync - (.arst(arst), - .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), - .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), - .fifo_ready(rx_have_data) ); - - // //////////////////////////////////////////// - // Control path on CS6 - - gpmc_wb gpmc_wb - (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), - .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), - .wb_ack_i(wb_ack_i) ); - - assign debug = 0; - -endmodule // gpmc diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v new file mode 100644 index 000000000..41dfeb49e --- /dev/null +++ b/usrp2/gpmc/gpmc_sync.v @@ -0,0 +1,107 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpmc + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + wire bus_error_tx, bus_error_rx; + assign bus_error = bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space, tx_frame_len; + + assign tx_frame_len = 10; + + gpmc_to_fifo_sync gpmc_to_fifo_sync + (.arst(arst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) tx_fifo + (.wclk(EM_CLK), .datain(tx18_data), + .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .rclk(fifo_clk), .dataout(tx18b_data), + .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); + + fifo19_to_fifo36 f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space, rx_frame_len; + + fifo36_to_fifo18 f18_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + (.wclk(fifo_clk), .datain(rx18_data), + .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .rclk(EM_CLK), .dataout(rx18b_data), + .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst)); + + fifo_to_gpmc_sync fifo_to_gpmc_sync + (.arst(arst), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .fifo_ready(rx_have_data) ); + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]), + .have_packet(), .length(), .next() ); + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = 0; + +endmodule // gpmc -- cgit v1.2.3 From 8f6ddf93ef81deb73a8b84496e115be299769951 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 16:13:42 -0700 Subject: correct name of module --- usrp2/gpmc/gpmc_sync.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v index 41dfeb49e..825d131d8 100644 --- a/usrp2/gpmc/gpmc_sync.v +++ b/usrp2/gpmc/gpmc_sync.v @@ -1,6 +1,6 @@ ////////////////////////////////////////////////////////////////////////////////// -module gpmc +module gpmc_sync (// GPMC signals input arst, input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -104,4 +104,4 @@ module gpmc assign debug = 0; -endmodule // gpmc +endmodule // gpmc_sync -- cgit v1.2.3 From 883c60cad6756042b5e90785668be3dd98e920bf Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 16:14:24 -0700 Subject: add bus error reporting --- usrp2/gpmc/gpmc_to_fifo_async.v | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index a8068022f..1df93f910 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -1,12 +1,12 @@ module gpmc_to_fifo_async - (input [15:0] EM_D, input [1:0] EM_NBE, - input EM_NCS, input EM_NWE, + (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, input fifo_clk, input fifo_rst, output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, - input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, + output reg bus_error ); reg [10:0] counter; // Synchronize the async control signals @@ -54,5 +54,11 @@ module gpmc_to_fifo_async counter <= counter + 1; assign fifo_ready = first_write & (fifo_space > frame_len); + + always @(posedge fifo_clk) + if(fifo_rst) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; endmodule // gpmc_to_fifo_async -- cgit v1.2.3 From 2e6079841b7509f08a54c67db2ec19e07329e0d9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 16:14:57 -0700 Subject: change time parameters because Xilinx IP has a 1ps timescale --- usrp2/models/gpmc_model_async.v | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v index a63a5a8fd..64b596284 100644 --- a/usrp2/models/gpmc_model_async.v +++ b/usrp2/models/gpmc_model_async.v @@ -1,4 +1,4 @@ - +`timescale 1ps/1ps module gpmc_model_async (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, @@ -26,22 +26,22 @@ module gpmc_model_async input [10:0] addr; input [15:0] data; begin - #2.3; + #23000; EM_A <= addr[10:1]; EM_D_int <= data; - #2.01; + #20100; if(ctrl) EM_NCS6 <= 0; else EM_NCS4 <= 0; - #14; + #14000; EM_NWE <= 0; - #77.5; + #77500; EM_NCS4 <= 1; EM_NCS6 <= 1; //#1.5; EM_NWE <= 1; - #60; + #60000; EM_A <= 10'bz; EM_D_int <= 16'bz; end @@ -51,33 +51,33 @@ module gpmc_model_async input ctrl; input [10:0] addr; begin - #1.3; + #13000; EM_A <= addr[10:1]; - #3; + #3000; if(ctrl) EM_NCS6 <= 0; else EM_NCS4 <= 0; - #14; + #14000; EM_NOE <= 0; - #77.5; + #77500; EM_NCS4 <= 1; EM_NCS6 <= 1; //#1.5; $display("Data Read from GPMC: %X",EM_D); EM_NOE <= 1; - #254; + #254000; EM_A <= 10'bz; end endtask // GPMC_Read initial begin - #1000; + #1000000; GPMC_Write(1,36,16'hF00D); - #1000; + #1000000; GPMC_Read(1,36); - #1000; + #1000000; GPMC_Write(0,36,16'h1234); GPMC_Write(0,38,16'h5678); GPMC_Write(0,40,16'h9abc); @@ -89,6 +89,19 @@ module gpmc_model_async GPMC_Write(0,11'h7FE,16'hDEAD); GPMC_Write(0,11'h7FE,16'hDEAD); #100000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + #100000; + GPMC_Read(0,0); + #100000000; $finish; end -- cgit v1.2.3 From 449a420f4024004abc49f3a17d224910710def92 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 16:16:31 -0700 Subject: async gpmc progress --- usrp2/gpmc/fifo_to_gpmc_async.v | 45 +++++++++++++++++ usrp2/gpmc/gpmc_async.v | 108 ++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/tb_u1e.v | 4 +- usrp2/top/u1e/u1e_core.v | 34 +++++++------ 4 files changed, 173 insertions(+), 18 deletions(-) create mode 100644 usrp2/gpmc/fifo_to_gpmc_async.v create mode 100644 usrp2/gpmc/gpmc_async.v diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v new file mode 100644 index 000000000..4f253e1b5 --- /dev/null +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -0,0 +1,45 @@ + +// Assumes an asynchronous GPMC cycle +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module fifo_to_gpmc_async + (input clk, input reset, input clear, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + output [15:0] EM_D, input EM_NCS, input EM_NOE, + input [15:0] frame_len, output reg bus_error); + + // Synchronize the async control signals + reg [1:0] cs_del, oe_del; + reg [15:0] counter; + + always @(posedge clk) + if(reset) + begin + cs_del <= 2'b11; + oe_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + oe_del <= { oe_del[0], EM_NOE }; + end + + //wire do_read = (~cs_del[0] & (oe_del == 2'b10)); + wire do_read = (~cs_del[1] & (oe_del == 2'b01)); // change output on trailing edge + wire first_read = (counter == 0); + wire last_read = ((counter+1) == frame_len); + + assign EM_D = data_i[15:0]; + + assign dst_rdy_o = do_read; + + always @(posedge clk) + if(reset) + bus_error <= 0; + else if(dst_rdy_o & ~src_rdy_i) + bus_error <= 1; + + +endmodule // fifo_to_gpmc_async diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v new file mode 100644 index 000000000..c4cf0ef89 --- /dev/null +++ b/usrp2/gpmc/gpmc_async.v @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpmc_async + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + wire bus_error_tx, bus_error_rx; + assign bus_error = bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space, tx_frame_len; + + assign tx_frame_len = 10; + + gpmc_to_fifo_async gpmc_to_fifo_async + (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); + + fifo19_to_fifo36 f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space, rx_frame_len; + assign rx_frame_len = tx_frame_len; + + fifo36_to_fifo18 f18_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + + fifo_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); + + fifo_to_gpmc_async fifo_to_gpmc_async + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .frame_len(rx_frame_len), .bus_error(bus_error_rx) ); + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]), + .have_packet(), .length(), .next() ); + + assign rx_have_data = 0; + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = 0; + +endmodule // gpmc_async diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 31e4fcb69..5fc8134fb 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -21,9 +21,9 @@ module tb_u1e(); wire [1:0] EM_NBE; reg clk_fpga = 0, rst_fpga = 1; - always #15.625 clk_fpga = ~clk_fpga; + always #15625 clk_fpga = ~clk_fpga; - initial #200 + initial #200000 @(posedge clk_fpga) rst_fpga <= 0; diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7df7b0a48..40950bf82 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -35,22 +35,24 @@ module u1e_core wire [35:0] tx_data, rx_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; - gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), - .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), - - .fifo_clk(wb_clk), .fifo_rst(wb_rst), - .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), - .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - - .debug(debug_gpmc)); + gpmc_async gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .debug(debug_gpmc)); fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), -- cgit v1.2.3 From beccd823da07b7c8b8d95b4688c6e05732f66165 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 17:55:22 -0700 Subject: async seems to work with packet lengths now. Still need to do wishbone regs for gpmc --- usrp2/gpmc/fifo_to_gpmc_async.v | 9 +------- usrp2/gpmc/fifo_watcher.v | 38 +++++++++++++++++++++++++++------- usrp2/gpmc/gpmc_async.v | 10 ++++----- usrp2/models/gpmc_model_async.v | 46 ++++++++++++++++++++++++++++++----------- usrp2/top/u1e/Makefile | 6 +++--- 5 files changed, 72 insertions(+), 37 deletions(-) diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v index 4f253e1b5..5ac8b19bd 100644 --- a/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -8,7 +8,7 @@ module fifo_to_gpmc_async (input clk, input reset, input clear, input [17:0] data_i, input src_rdy_i, output dst_rdy_o, output [15:0] EM_D, input EM_NCS, input EM_NOE, - input [15:0] frame_len, output reg bus_error); + input [15:0] frame_len); // Synchronize the async control signals reg [1:0] cs_del, oe_del; @@ -35,11 +35,4 @@ module fifo_to_gpmc_async assign dst_rdy_o = do_read; - always @(posedge clk) - if(reset) - bus_error <= 0; - else if(dst_rdy_o & ~src_rdy_i) - bus_error <= 1; - - endmodule // fifo_to_gpmc_async diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index 8b8f1abfb..da2051b04 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -2,25 +2,47 @@ module fifo_watcher (input clk, input reset, input clear, - input src_rdy, input dst_rdy, input sof, input eof, - output have_packet, output [15:0] length, input next); + input src_rdy1, input dst_rdy1, input sof1, input eof1, + input src_rdy2, input dst_rdy2, input sof2, input eof2, + output have_packet, output [15:0] length, output reg bus_error); - wire write = src_rdy & dst_rdy & eof; + wire write = src_rdy1 & dst_rdy1 & eof1; + wire read = src_rdy2 & dst_rdy2 & eof2; + wire have_packet_int; + reg [15:0] counter; fifo_short #(.WIDTH(16)) frame_lengths (.clk(clk), .reset(reset), .clear(clear), .datain(counter), .src_rdy_i(write), .dst_rdy_o(), - .dataout(length), .src_rdy_o(have_packet), .dst_rdy_i(next) ); + .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read) ); - reg [15:0] counter; always @(posedge clk) if(reset | clear) counter <= 1; // Start at 1 - else if(src_rdy & dst_rdy) - if(eof) + else if(src_rdy1 & dst_rdy1) + if(eof1) counter <= 1; else counter <= counter + 1; - + always @(posedge clk) + if(reset | clear) + bus_error <= 0; + else if(dst_rdy2 & ~src_rdy2) + bus_error <= 1; + else if(read & ~have_packet_int) + bus_error <= 1; + + reg in_packet; + assign have_packet = have_packet_int & ~in_packet; + + always @(posedge clk) + if(reset | clear) + in_packet <= 0; + else if(src_rdy2 & dst_rdy2) + if(eof2) + in_packet <= 0; + else + in_packet <= 1; + endmodule // fifo_watcher diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index c4cf0ef89..22e56cc89 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -67,7 +67,6 @@ module gpmc_async wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; wire [15:0] rx_fifo_space, rx_frame_len; - assign rx_frame_len = tx_frame_len; fifo36_to_fifo18 f18_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), @@ -83,15 +82,14 @@ module gpmc_async (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), - .frame_len(rx_frame_len), .bus_error(bus_error_rx) ); + .frame_len(rx_frame_len) ); fifo_watcher fifo_watcher (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]), - .have_packet(), .length(), .next() ); + .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), + .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), + .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) ); - assign rx_have_data = 0; - // //////////////////////////////////////////// // Control path on CS6 diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v index 64b596284..beeaee028 100644 --- a/usrp2/models/gpmc_model_async.v +++ b/usrp2/models/gpmc_model_async.v @@ -78,28 +78,50 @@ module gpmc_model_async #1000000; GPMC_Read(1,36); #1000000; - GPMC_Write(0,36,16'h1234); - GPMC_Write(0,38,16'h5678); - GPMC_Write(0,40,16'h9abc); - GPMC_Write(0,11'h2F4,16'hF00D); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - #100000; + GPMC_Write(0,0,16'h1234); + GPMC_Write(0,0,16'h5678); + GPMC_Write(0,0,16'h9abc); + GPMC_Write(0,0,16'hF00D); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + #1000000; + GPMC_Write(0,0,16'h1234); + GPMC_Write(0,0,16'h5678); + GPMC_Write(0,0,16'h9abc); + GPMC_Write(0,0,16'hF00D); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'h9876); + #1000000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); + #1000000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); - #100000; + GPMC_Read(0,0); + GPMC_Read(0,0); + #1000000; GPMC_Read(0,0); #100000000; $finish; diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 160e67894..e15a49e10 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -176,12 +176,12 @@ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ -gpmc/gpmc.v \ +gpmc/gpmc_async.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ gpmc/gpmc_to_fifo_async.v \ -gpmc/gpmc_to_fifo_sync.v \ -gpmc/fifo_to_gpmc_sync.v \ +gpmc/fifo_to_gpmc_async.v \ +gpmc/fifo_watcher.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ -- cgit v1.2.3 From d94a0fbea165463a132006a15eb8548cde79a4d2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 18:55:20 -0700 Subject: access frame length regs from wishbone --- usrp2/gpmc/gpmc_async.v | 8 ++++---- usrp2/top/u1e/u1e_core.v | 20 ++++++++++++++------ 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 22e56cc89..b1a545907 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -19,6 +19,8 @@ module gpmc_async output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + input [15:0] tx_frame_len, output [15:0] rx_frame_len, + output [31:0] debug ); @@ -40,9 +42,7 @@ module gpmc_async wire [17:0] tx18_data, tx18b_data; wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; - wire [15:0] tx_fifo_space, tx_frame_len; - - assign tx_frame_len = 10; + wire [15:0] tx_fifo_space; gpmc_to_fifo_async gpmc_to_fifo_async (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), @@ -66,7 +66,7 @@ module gpmc_async wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; - wire [15:0] rx_fifo_space, rx_frame_len; + wire [15:0] rx_fifo_space; fifo36_to_fifo18 f18_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 40950bf82..30396de3a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -34,6 +34,8 @@ module u1e_core wire [35:0] tx_data, rx_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; + reg [15:0] tx_frame_len; + wire [15:0] rx_frame_len; gpmc_async gpmc (.arst(wb_rst), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), @@ -51,7 +53,8 @@ module u1e_core .fifo_clk(wb_clk), .fifo_rst(wb_rst), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .debug(debug_gpmc)); fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo @@ -133,11 +136,13 @@ module u1e_core reg [15:0] reg_leds, reg_cgen_ctrl, reg_test; - localparam REG_LEDS = 7'd0; // out - localparam REG_SWITCHES = 7'd2; // in - localparam REG_CGEN_CTRL = 7'd4; // out - localparam REG_CGEN_ST = 7'd6; // in - localparam REG_TEST = 7'd8; // out + localparam REG_LEDS = 7'd0; // out + localparam REG_SWITCHES = 7'd2; // in + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // out + localparam REG_TX_FRAMELEN = 7'd12; // in always @(posedge wb_clk) if(wb_rst) @@ -155,6 +160,8 @@ module u1e_core reg_cgen_ctrl <= s0_dat_mosi; REG_TEST : reg_test <= s0_dat_mosi; + REG_TX_FRAMELEN : + tx_frame_len <= s0_dat_mosi; endcase // case (s0_adr[6:0]) assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board @@ -166,6 +173,7 @@ module u1e_core (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 23316f1ac73c917757a70980c3a9f251852ee426 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 21:27:03 -0700 Subject: added pps and time capability --- usrp2/top/u1e/u1e.ucf | 2 +- usrp2/top/u1e/u1e.v | 6 ++++-- usrp2/top/u1e/u1e_core.v | 18 ++++++++++++++++-- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index c39759d0b..1c8dfc197 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -208,7 +208,7 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "TXSYNC" LOC = "U18" ; #NET "TXBLANK" LOC = "U19" ; -#NET "PPS_IN" LOC = "M17" ; +NET "PPS_IN" LOC = "M17" ; NET "io_tx<0>" LOC = "AB20" ; NET "io_tx<1>" LOC = "Y17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index ab270879c..b8f716d26 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -20,7 +20,8 @@ module u1e input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls - inout [15:0] io_tx, inout [15:0] io_rx + inout [15:0] io_tx, inout [15:0] io_rx, + input PPS_IN ); // FPGA-specific pins connections @@ -50,6 +51,7 @@ module u1e .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), - .io_tx(io_tx), .io_rx(io_rx) ); + .io_tx(io_tx), .io_rx(io_rx), + .pps_in(PPS_IN) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 30396de3a..9e65faeed 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,7 +13,9 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx + inout [15:0] io_tx, inout [15:0] io_rx, + + input pps_in ); wire wb_clk = clk_fpga; @@ -249,7 +251,19 @@ module u1e_core (.clk_i(wb_clk), .rst_i(wb_rst), .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(), .run_tx(), .master_time(0), .ctrl_lines(atr_lines)); + .run_rx(0), .run_tx(0), .ctrl_lines(atr_lines)); + + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + localparam SR_TIME64 = 0; + wire pps_int; + wire [63:0] vita_time; + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From 21ceee337d61ccb2f31edaefd5c7418e8025b4b1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 20 Apr 2010 10:51:23 -0700 Subject: find time_64bit --- usrp2/top/u1e/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index e15a49e10..5f712b046 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -176,6 +176,7 @@ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ +timing/time_64bit.v \ gpmc/gpmc_async.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ -- cgit v1.2.3 From 5de2543e9cee644009d9ec15c19c70986df89594 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 23 Apr 2010 14:43:29 -0700 Subject: Register outputs to omap to prevent runt pulses from falsely triggering interrupts --- usrp2/gpmc/fifo_watcher.v | 8 ++++++-- usrp2/gpmc/gpmc_async.v | 9 +++++++-- usrp2/gpmc/gpmc_to_fifo_async.v | 10 +++++++--- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index da2051b04..7a3f00483 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -4,7 +4,7 @@ module fifo_watcher (input clk, input reset, input clear, input src_rdy1, input dst_rdy1, input sof1, input eof1, input src_rdy2, input dst_rdy2, input sof2, input eof2, - output have_packet, output [15:0] length, output reg bus_error); + output reg have_packet, output [15:0] length, output reg bus_error); wire write = src_rdy1 & dst_rdy1 & eof1; wire read = src_rdy2 & dst_rdy2 & eof2; @@ -34,7 +34,11 @@ module fifo_watcher bus_error <= 1; reg in_packet; - assign have_packet = have_packet_int & ~in_packet; + always @(posedge clk) + if(reset | clear) + have_packet <= 0; + else + have_packet <= have_packet_int & ~in_packet; always @(posedge clk) if(reset | clear) diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index b1a545907..02a00ce57 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -7,7 +7,7 @@ module gpmc_async input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, // GPIOs for FIFO signalling - output rx_have_data, output tx_have_space, output bus_error, input bus_reset, + output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset, // Wishbone signals input wb_clk, input wb_rst, @@ -31,7 +31,12 @@ module gpmc_async assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; wire bus_error_tx, bus_error_rx; - assign bus_error = bus_error_tx | bus_error_rx; + + always @(posedge fifo_clk) + if(fifo_rst) + bus_error <= 0; + else + bus_error <= bus_error_tx | bus_error_rx; // CS4 is RAM_2PORT for DATA PATH (high-speed data) // Writes go into one RAM, reads come from the other diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 1df93f910..38f1165fc 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -5,10 +5,10 @@ module gpmc_to_fifo_async input fifo_clk, input fifo_rst, output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, - input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, + input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready, output reg bus_error ); - reg [10:0] counter; + reg [15:0] counter; // Synchronize the async control signals reg [1:0] cs_del, we_del; always @(posedge fifo_clk) @@ -53,7 +53,11 @@ module gpmc_to_fifo_async else counter <= counter + 1; - assign fifo_ready = first_write & (fifo_space > frame_len); + always @(posedge fifo_clk) + if(fifo_rst) + fifo_ready <= 0; + else + fifo_ready <= first_write & (fifo_space > frame_len); always @(posedge fifo_clk) if(fifo_rst) -- cgit v1.2.3 From aeed16ec6e220f99df41534febe85336e5b384e6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 23 Apr 2010 18:06:28 -0700 Subject: Only allow new packets if we can fit the largest possible packet (2KB) --- usrp2/gpmc/gpmc_to_fifo_async.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 38f1165fc..6232244d4 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -57,7 +57,7 @@ module gpmc_to_fifo_async if(fifo_rst) fifo_ready <= 0; else - fifo_ready <= first_write & (fifo_space > frame_len); + fifo_ready <= first_write & (fifo_space > 16'd1023); always @(posedge fifo_clk) if(fifo_rst) -- cgit v1.2.3 From ae4b885e3533a73f0781e2fdb892f5d505081240 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 24 Apr 2010 22:58:06 -0700 Subject: Pass previously unused GPIOs to debug pins to help debug interrupts --- usrp2/top/u1e/u1e.ucf | 24 ++++++++++++------------ usrp2/top/u1e/u1e.v | 7 +++++++ usrp2/top/u1e/u1e_core.v | 6 ++---- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 1c8dfc197..9c42b00ac 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -47,22 +47,22 @@ NET "EM_NOE" LOC = "A14" ; #NET "EM_NWP" LOC = "F13" ; ## Overo GPIO -#NET "overo_gpio0" LOC = "F9" ; -#NET "overo_gpio14" LOC = "C4" ; -#NET "overo_gpio21" LOC = "D5" ; -#NET "overo_gpio22" LOC = "A3" ; -#NET "overo_gpio23" LOC = "B3" ; -#NET "overo_gpio64" LOC = "A4" ; -#NET "overo_gpio65" LOC = "F8" ; -#NET "overo_gpio127" LOC = "C8" ; -#NET "overo_gpio128" LOC = "G8" ; +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug +NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug NET "overo_gpio144" LOC = "A5" ; # tx_have_space NET "overo_gpio145" LOC = "C7" ; # tx_underrun NET "overo_gpio146" LOC = "A6" ; # rx_have_data NET "overo_gpio147" LOC = "B6" ; # rx_overrun -#NET "overo_gpio163" LOC = "D7" ; -#NET "overo_gpio170" LOC = "E8" ; -#NET "overo_gpio176" LOC = "B4" ; +NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug ## Overo UART #NET "overo_txd1" LOC = "C6" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index b8f716d26..2ed6b71c8 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -20,6 +20,10 @@ module u1e input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO + input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + inout [15:0] io_tx, inout [15:0] io_rx, input PPS_IN ); @@ -52,6 +56,9 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), + .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, + {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, + {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), .pps_in(PPS_IN) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 9e65faeed..e67b1b158 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,9 +13,7 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx, - - input pps_in + inout [15:0] io_tx, inout [15:0] io_rx, input [11:0] misc_gpio, input pps_in ); wire wb_clk = clk_fpga; @@ -273,6 +271,6 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { debug_txd, debug_rxd }; + assign debug_gpio_1 = { misc_gpio }; endmodule // u1e_core -- cgit v1.2.3 From 97af4bd12673fbb8d68dd087690dabb3e9488c4d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 26 Apr 2010 17:15:53 -0700 Subject: send bus error to debug pins --- usrp2/top/u1e/u1e_core.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e67b1b158..f231791da 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -36,6 +36,8 @@ module u1e_core wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; + + wire bus_error; gpmc_async gpmc (.arst(wb_rst), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), @@ -43,7 +45,7 @@ module u1e_core .EM_NOE(EM_NOE), .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - .bus_error(), .bus_reset(0), + .bus_error(bus_error), .bus_reset(0), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), @@ -271,6 +273,6 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { misc_gpio }; + assign debug_gpio_1 = { bus_error, misc_gpio[11:0] }; endmodule // u1e_core -- cgit v1.2.3 From eb5bfb963459dbb3e51df49b5aa22fcbda1627d5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 28 Apr 2010 17:03:14 -0700 Subject: separate timed tx and rx instead of loopback --- usrp2/top/u1e/u1e_core.v | 54 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index f231791da..d5a3ddf68 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -58,12 +58,48 @@ module u1e_core .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .debug(debug_gpmc)); - +/* fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); +*/ + wire tx_strobe, rx_strobe, tx_enable, rx_enable; + wire [7:0] rate; + wire tx_fifo_rdy, rx_fifo_rdy; + + cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable), + .rate(rate), .strobe_fast(1), .strobe_slow(tx_strobe)); + + fifo_cascade #(.WIDTH(36), .SIZE(11)) tx_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .dataout(), .src_rdy_o(tx_fifo_rdy), .dst_rdy_i(tx_strobe)); + + + reg [15:0] ctr; + wire [15:0] rx_pkt_len = 480; + wire rx_eof = (ctr == rx_pkt_len); + wire rx_sof = (ctr == 0); + + cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable), + .rate(rate), .strobe_fast(1), .strobe_slow(rx_strobe)); + + fifo_cascade #(.WIDTH(36), .SIZE(11)) rx_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain({2'b00,rx_eof,rx_sof,16'd0,ctr}), .src_rdy_i(rx_strobe), .dst_rdy_o(rx_fifo_rdy), + .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + always @(posedge wb_clk) + if(wb_rst) + ctr <= 0; + else if(rx_strobe & rx_fifo_rdy) + if(ctr == rx_pkt_len) + ctr <= 0; + else + ctr <= ctr + 1; + + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -136,7 +172,7 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, Misc LEDs, Switches, controls - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; localparam REG_LEDS = 7'd0; // out localparam REG_SWITCHES = 7'd2; // in @@ -145,6 +181,7 @@ module u1e_core localparam REG_TEST = 7'd8; // out localparam REG_RX_FRAMELEN = 7'd10; // out localparam REG_TX_FRAMELEN = 7'd12; // in + localparam REG_XFER_RATE = 7'd14; // in always @(posedge wb_clk) if(wb_rst) @@ -152,6 +189,8 @@ module u1e_core reg_leds <= 0; reg_cgen_ctrl <= 2'b11; reg_test <= 0; + tx_frame_len <= 0; + xfer_rate <= 0; end else if(s0_cyc & s0_stb & s0_we) @@ -164,7 +203,13 @@ module u1e_core reg_test <= s0_dat_mosi; REG_TX_FRAMELEN : tx_frame_len <= s0_dat_mosi; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) + + assign tx_enable = xfer_rate[15]; + assign rx_enable = xfer_rate[14]; + assign rate = xfer_rate[7:0]; assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; @@ -273,6 +318,9 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { bus_error, misc_gpio[11:0] }; + assign debug_gpio_1 = { {rx_enable, rx_strobe, rx_fifo_rdy, rx_strobe & ~rx_fifo_rdy}, + {tx_enable, tx_strobe, tx_fifo_rdy, tx_strobe & ~tx_fifo_rdy}, + {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, + {3'b0, bus_error, misc_gpio[11:0]} }; endmodule // u1e_core -- cgit v1.2.3 From b30cbe85e8537de6a94e481a57033b5e57a73e12 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 3 May 2010 12:34:45 -0700 Subject: have_space and have_packet now stay high even while busy, as long as there really is more data/space. This should allow bursting without having additional interrupts. Also lenghten RX FIFO --- usrp2/gpmc/fifo_watcher.v | 6 ++++-- usrp2/gpmc/gpmc_async.v | 2 +- usrp2/gpmc/gpmc_to_fifo_async.v | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index 7a3f00483..4bba142b0 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -10,11 +10,13 @@ module fifo_watcher wire read = src_rdy2 & dst_rdy2 & eof2; wire have_packet_int; reg [15:0] counter; + wire [4:0] pkt_count; fifo_short #(.WIDTH(16)) frame_lengths (.clk(clk), .reset(reset), .clear(clear), .datain(counter), .src_rdy_i(write), .dst_rdy_o(), - .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read) ); + .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read), + .occupied(pkt_count), .space()); always @(posedge clk) if(reset | clear) @@ -38,7 +40,7 @@ module fifo_watcher if(reset | clear) have_packet <= 0; else - have_packet <= have_packet_int & ~in_packet; + have_packet <= (have_packet_int & ~in_packet) | (pkt_count>1) ; always @(posedge clk) if(reset | clear) diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 02a00ce57..dd06478b3 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -78,7 +78,7 @@ module gpmc_async .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); - fifo_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 6232244d4..3d29745a2 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -57,7 +57,7 @@ module gpmc_to_fifo_async if(fifo_rst) fifo_ready <= 0; else - fifo_ready <= first_write & (fifo_space > 16'd1023); + fifo_ready <= /* first_write & */ (fifo_space > 16'd1023); always @(posedge fifo_clk) if(fifo_rst) -- cgit v1.2.3 From c4698bb0a42b60dea924a83d18b27131a15958a2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 4 May 2010 09:44:28 -0700 Subject: changed comment --- usrp2/top/u1e/u1e.ucf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 9c42b00ac..055a1ef17 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -254,7 +254,7 @@ NET "io_rx<15>" LOC = "Y4" ; #NET "fpga_cfg_cclk" LOC = "V17" ; #NET "fpga_cfg_init_b" LOC = "W15" ; -## Unnamed, need to figure out what they do +## Unused #NET "unnamed_net37" LOC = "B1" ; # TMS #NET "unnamed_net36" LOC = "B22" ; # TDO #NET "unnamed_net35" LOC = "D2" ; # TDI -- cgit v1.2.3 From 031becd1f05f0fbcab6a4f2be353292cd667a88f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 4 May 2010 12:30:56 -0700 Subject: add timing constraints. Just have main clock signal at 64 MHz for now. --- usrp2/top/u1e/Makefile | 1 + usrp2/top/u1e/timing.ucf | 13 +++++++++++++ 2 files changed, 14 insertions(+) create mode 100644 usrp2/top/u1e/timing.ucf diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 5f712b046..2aebb33f9 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -186,6 +186,7 @@ gpmc/fifo_watcher.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ +top/u1e/timing.ucf \ top/u1e/u1e.v ################################################## diff --git a/usrp2/top/u1e/timing.ucf b/usrp2/top/u1e/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/usrp2/top/u1e/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; -- cgit v1.2.3 From 2ddaba2d8bdcdda07b949f007d2555cf57c7c8d7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 4 May 2010 15:06:03 -0700 Subject: added DAC output pins, and a sine wave generator to test them --- usrp2/top/u1e/u1e.ucf | 32 ++++++++++++++++---------------- usrp2/top/u1e/u1e.v | 4 ++++ usrp2/top/u1e/u1e_core.v | 45 +++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 63 insertions(+), 18 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 055a1ef17..a73ebceb8 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -191,22 +191,22 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "DA<1>" LOC = "P22" ; #NET "DA<0>" LOC = "N17" ; -#NET "TX<13>" LOC = "P19" ; -#NET "TX<12>" LOC = "R18" ; -#NET "TX<11>" LOC = "U20" ; -#NET "TX<10>" LOC = "T20" ; -#NET "TX<9>" LOC = "R19" ; -#NET "TX<8>" LOC = "R20" ; -#NET "TX<7>" LOC = "W22" ; -#NET "TX<6>" LOC = "Y22" ; -#NET "TX<5>" LOC = "T18" ; -#NET "TX<4>" LOC = "T17" ; -#NET "TX<3>" LOC = "W19" ; -#NET "TX<2>" LOC = "V20" ; -#NET "TX<1>" LOC = "Y21" ; -#NET "TX<0>" LOC = "AA22" ; -#NET "TXSYNC" LOC = "U18" ; -#NET "TXBLANK" LOC = "U19" ; +NET "TX<13>" LOC = "P19" ; +NET "TX<12>" LOC = "R18" ; +NET "TX<11>" LOC = "U20" ; +NET "TX<10>" LOC = "T20" ; +NET "TX<9>" LOC = "R19" ; +NET "TX<8>" LOC = "R20" ; +NET "TX<7>" LOC = "W22" ; +NET "TX<6>" LOC = "Y22" ; +NET "TX<5>" LOC = "T18" ; +NET "TX<4>" LOC = "T17" ; +NET "TX<3>" LOC = "W19" ; +NET "TX<2>" LOC = "V20" ; +NET "TX<1>" LOC = "Y21" ; +NET "TX<0>" LOC = "AA22" ; +NET "TXSYNC" LOC = "U18" ; +NET "TXBLANK" LOC = "U19" ; NET "PPS_IN" LOC = "M17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 2ed6b71c8..35818e8c8 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -25,6 +25,9 @@ module u1e input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] TX, output TXSYNC, output TXBLANK, + input PPS_IN ); @@ -56,6 +59,7 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), + .tx(TX), .txsync(TXSYNC), .txblank(TXBLANK), .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index d5a3ddf68..74ffc4657 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,7 +13,10 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx, input [11:0] misc_gpio, input pps_in + inout [15:0] io_tx, inout [15:0] io_rx, + output reg [13:0] tx, output reg txsync, output txblank, + + input [11:0] misc_gpio, input pps_in ); wire wb_clk = clk_fpga; @@ -213,7 +216,7 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - assign { rx_overrun, tx_underrun } = reg_test; + assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : @@ -309,6 +312,44 @@ module u1e_core time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + + // ///////////////////////////////////////////////////////////////////////// + // TX + + assign txblank = 0; + + wire [23:0] freq = {reg_test,8'd0}; + + reg [23:0] tx_q_hold; + wire [23:0] tx_i, tx_q; + + reg tx_stb; + always @(posedge wb_clk) + tx_stb <= ~tx_stb; + + always @(posedge wb_clk) + if(tx_stb) + tx <= tx_i[23:10]; + else + tx <= tx_q_hold[23:10]; + + always @(posedge wb_clk) + if(tx_stb) + tx_q_hold <= tx_q; + + always @(posedge wb_clk) + txsync <= ~tx_stb; // TX Sync low indicates first data item + // We invert here if we don't use inv_txsync in the 9862 + + reg [23:0] phase; + always @(posedge wb_clk) + if(tx_stb) + phase <= phase + freq; + + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd15000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From 45d92a0610582672cea4f1d97d116af00eac7bef Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 7 May 2010 10:27:33 -0700 Subject: SPI passthru for programming clock gen chip on brand new boards --- usrp2/top/u1e_passthru/Makefile | 107 +++++++++++++++ usrp2/top/u1e_passthru/passthru.ucf | 266 ++++++++++++++++++++++++++++++++++++ usrp2/top/u1e_passthru/passthru.v | 18 +++ 3 files changed, 391 insertions(+) create mode 100644 usrp2/top/u1e_passthru/Makefile create mode 100644 usrp2/top/u1e_passthru/passthru.ucf create mode 100644 usrp2/top/u1e_passthru/passthru.v diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile new file mode 100644 index 000000000..62923f87f --- /dev/null +++ b/usrp2/top/u1e_passthru/Makefile @@ -0,0 +1,107 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := passthru +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +top/u1e_passthru/passthru.ucf \ +top/u1e_passthru/passthru.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf new file mode 100644 index 000000000..1672132a2 --- /dev/null +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -0,0 +1,266 @@ + +#NET "CLK_FPGA_P" LOC = "Y11" ; +#NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +#NET "EM_D<15>" LOC = "D13" ; +#NET "EM_D<14>" LOC = "D15" ; +#NET "EM_D<13>" LOC = "C16" ; +#NET "EM_D<12>" LOC = "B20" ; +#NET "EM_D<11>" LOC = "A19" ; +#NET "EM_D<10>" LOC = "A17" ; +#NET "EM_D<9>" LOC = "E15" ; +#NET "EM_D<8>" LOC = "F15" ; +#NET "EM_D<7>" LOC = "E16" ; +#NET "EM_D<6>" LOC = "F16" ; +#NET "EM_D<5>" LOC = "B17" ; +#NET "EM_D<4>" LOC = "C17" ; +#NET "EM_D<3>" LOC = "B19" ; +#NET "EM_D<2>" LOC = "D19" ; +#NET "EM_D<1>" LOC = "C19" ; +#NET "EM_D<0>" LOC = "A20" ; + +#NET "EM_A<10>" LOC = "C14" ; +#NET "EM_A<9>" LOC = "C10" ; +#NET "EM_A<8>" LOC = "C5" ; +#NET "EM_A<7>" LOC = "A18" ; +#NET "EM_A<6>" LOC = "A15" ; +#NET "EM_A<5>" LOC = "A12" ; +#NET "EM_A<4>" LOC = "A10" ; +#NET "EM_A<3>" LOC = "E7" ; +#NET "EM_A<2>" LOC = "A7" ; +#NET "EM_A<1>" LOC = "C15" ; + +#NET "EM_NCS6" LOC = "E17" ; +##NET "EM_NCS5" LOC = "E10" ; +#NET "EM_NCS4" LOC = "E6" ; +##NET "EM_NCS1" LOC = "D18" ; +##NET "EM_NCS0" LOC = "D17" ; + +#NET "EM_CLK" LOC = "F11" ; +#NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE<1>" LOC = "D14" ; +#NET "EM_NBE<0>" LOC = "A13" ; +#NET "EM_NWE" LOC = "B13" ; +#NET "EM_NOE" LOC = "A14" ; +##NET "EM_NADV_ALE" LOC = "B15" ; +##NET "EM_NWP" LOC = "F13" ; + +## Overo GPIO +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +#NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +#NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +#NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +#NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +#NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +#NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug +#NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +#NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug +#NET "overo_gpio144" LOC = "A5" ; # tx_have_space +#NET "overo_gpio145" LOC = "C7" ; # tx_underrun +#NET "overo_gpio146" LOC = "A6" ; # rx_have_data +#NET "overo_gpio147" LOC = "B6" ; # rx_overrun +#NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +#NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +#NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug + +## Overo UART +##NET "overo_txd1" LOC = "C6" ; +##NET "overo_rxd1" LOC = "D6" ; + +## FTDI UART to USB converter +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; + +##NET "SYSEN" LOC = "C11" ; + +## I2C +#NET "db_scl" LOC = "U4" ; +#NET "db_sda" LOC = "U5" ; + +## SPI +### DBoard SPI +#NET "db_sclk_rx" LOC = "W3" ; +#NET "db_miso_rx" LOC = "W2" ; +#NET "db_mosi_rx" LOC = "V4" ; +#NET "db_sen_rx" LOC = "V3" ; +#NET "db_sclk_tx" LOC = "Y1" ; +#NET "db_miso_tx" LOC = "W1" ; +#NET "db_mosi_tx" LOC = "R3" ; +#NET "db_sen_tx" LOC = "T4" ; + +### AD9862 SPI and aux SPI Interfaces +##NET "aux_sdi_codec" LOC = "F19" ; +##NET "aux_sdo_codec" LOC = "F18" ; +##NET "aux_sclk_codec" LOC = "D21" ; +#NET "sen_codec" LOC = "D20" ; +#NET "mosi_codec" LOC = "E19" ; +#NET "miso_codec" LOC = "F21" ; +#NET "sclk_codec" LOC = "E20" ; + +### Clock Gen SPI +#NET "cgen_miso" LOC = "U2" ; +NET "cgen_mosi" LOC = "V1" ; +NET "cgen_sclk" LOC = "R5" ; +NET "cgen_sen_b" LOC = "T1" ; + +## Clock gen control +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; + +## Debug pins +#NET "debug_led<2>" LOC = "T5" ; +#NET "debug_led<1>" LOC = "R2" ; +#NET "debug_led<0>" LOC = "R1" ; +#NET "debug<0>" LOC = "P6" ; +#NET "debug<1>" LOC = "R6" ; +#NET "debug<2>" LOC = "P1" ; +#NET "debug<3>" LOC = "P2" ; +#NET "debug<4>" LOC = "N6" ; +#NET "debug<5>" LOC = "N5" ; +#NET "debug<6>" LOC = "N1" ; +#NET "debug<7>" LOC = "K2" ; +#NET "debug<8>" LOC = "K3" ; +#NET "debug<9>" LOC = "K6" ; +#NET "debug<10>" LOC = "L5" ; +#NET "debug<11>" LOC = "H2" ; +#NET "debug<12>" LOC = "K4" ; +#NET "debug<13>" LOC = "K5" ; +#NET "debug<14>" LOC = "G1" ; +#NET "debug<15>" LOC = "H1" ; +#NET "debug<16>" LOC = "H5" ; +#NET "debug<17>" LOC = "H6" ; +#NET "debug<18>" LOC = "E3" ; +#NET "debug<19>" LOC = "E4" ; +#NET "debug<20>" LOC = "G5" ; +#NET "debug<21>" LOC = "G6" ; +#NET "debug<22>" LOC = "F2" ; +#NET "debug<23>" LOC = "F1" ; +#NET "debug<24>" LOC = "H3" ; +#NET "debug<25>" LOC = "H4" ; +#NET "debug<26>" LOC = "F4" ; +#NET "debug<27>" LOC = "F5" ; +#NET "debug<28>" LOC = "C2" ; +#NET "debug<29>" LOC = "C1" ; +#NET "debug<30>" LOC = "F3" ; +#NET "debug<31>" LOC = "G3" ; +#NET "debug_clk<0>" LOC = "L6" ; +#NET "debug_clk<1>" LOC = "M5" ; + +#NET "debug_pb<2>" LOC = "Y2" ; +#NET "debug_pb<1>" LOC = "AA1" ; +#NET "debug_pb<0>" LOC = "N3" ; + +#NET "dip_sw<7>" LOC = "T3" ; +#NET "dip_sw<6>" LOC = "U3" ; +#NET "dip_sw<5>" LOC = "M3" ; +#NET "dip_sw<4>" LOC = "N4" ; +#NET "dip_sw<3>" LOC = "J3" ; +#NET "dip_sw<2>" LOC = "J4" ; +#NET "dip_sw<1>" LOC = "J6" ; +#NET "dip_sw<0>" LOC = "J7" ; + +##NET "RXSYNC" LOC = "F22" ; +##NET "reset_codec" LOC = "D22" ; + +##NET "DB<11>" LOC = "E22" ; +##NET "DB<10>" LOC = "J19" ; +##NET "DB<9>" LOC = "H20" ; +##NET "DB<8>" LOC = "G19" ; +##NET "DB<7>" LOC = "F20" ; +##NET "DB<6>" LOC = "K16" ; +##NET "DB<5>" LOC = "J17" ; +##NET "DB<4>" LOC = "H22" ; +##NET "DB<3>" LOC = "G22" ; +##NET "DB<2>" LOC = "H17" ; +##NET "DB<1>" LOC = "H18" ; +##NET "DB<0>" LOC = "K20" ; +##NET "DA<11>" LOC = "J20" ; +##NET "DA<10>" LOC = "K19" ; +##NET "DA<9>" LOC = "K18" ; +##NET "DA<8>" LOC = "L22" ; +##NET "DA<7>" LOC = "K22" ; +##NET "DA<6>" LOC = "N22" ; +##NET "DA<5>" LOC = "M22" ; +##NET "DA<4>" LOC = "N20" ; +##NET "DA<3>" LOC = "N19" ; +##NET "DA<2>" LOC = "R22" ; +##NET "DA<1>" LOC = "P22" ; +##NET "DA<0>" LOC = "N17" ; + +#NET "TX<13>" LOC = "P19" ; +#NET "TX<12>" LOC = "R18" ; +#NET "TX<11>" LOC = "U20" ; +#NET "TX<10>" LOC = "T20" ; +#NET "TX<9>" LOC = "R19" ; +#NET "TX<8>" LOC = "R20" ; +#NET "TX<7>" LOC = "W22" ; +#NET "TX<6>" LOC = "Y22" ; +#NET "TX<5>" LOC = "T18" ; +#NET "TX<4>" LOC = "T17" ; +#NET "TX<3>" LOC = "W19" ; +#NET "TX<2>" LOC = "V20" ; +#NET "TX<1>" LOC = "Y21" ; +#NET "TX<0>" LOC = "AA22" ; +#NET "TXSYNC" LOC = "U18" ; +#NET "TXBLANK" LOC = "U19" ; + +#NET "PPS_IN" LOC = "M17" ; + +#NET "io_tx<0>" LOC = "AB20" ; +#NET "io_tx<1>" LOC = "Y17" ; +#NET "io_tx<2>" LOC = "Y16" ; +#NET "io_tx<3>" LOC = "U16" ; +#NET "io_tx<4>" LOC = "V16" ; +#NET "io_tx<5>" LOC = "AB19" ; +#NET "io_tx<6>" LOC = "AA19" ; +#NET "io_tx<7>" LOC = "U14" ; +#NET "io_tx<8>" LOC = "U15" ; +#NET "io_tx<9>" LOC = "AB17" ; +#NET "io_tx<10>" LOC = "AB18" ; +#NET "io_tx<11>" LOC = "Y13" ; +#NET "io_tx<12>" LOC = "W14" ; +#NET "io_tx<13>" LOC = "U13" ; +#NET "io_tx<14>" LOC = "AA15" ; +#NET "io_tx<15>" LOC = "AB14" ; + +#NET "io_rx<0>" LOC = "Y8" ; +#NET "io_rx<1>" LOC = "Y9" ; +#NET "io_rx<2>" LOC = "V7" ; +#NET "io_rx<3>" LOC = "U8" ; +#NET "io_rx<4>" LOC = "V10" ; +#NET "io_rx<5>" LOC = "U9" ; +#NET "io_rx<6>" LOC = "AB7" ; +#NET "io_rx<7>" LOC = "AA8" ; +#NET "io_rx<8>" LOC = "W8" ; +#NET "io_rx<9>" LOC = "V8" ; +#NET "io_rx<10>" LOC = "AB5" ; +#NET "io_rx<11>" LOC = "AB6" ; +#NET "io_rx<12>" LOC = "AB4" ; +#NET "io_rx<13>" LOC = "AA4" ; +#NET "io_rx<14>" LOC = "W5" ; +#NET "io_rx<15>" LOC = "Y4" ; + +##NET "CLKOUT2_CODEC" LOC = "U12" ; +##NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +##NET "fpga_cfg_prog_b" LOC = "A2" ; +##NET "fpga_cfg_done" LOC = "AB21" ; +NET "fpga_cfg_din" LOC = "W17" ; +NET "fpga_cfg_cclk" LOC = "V17" ; +##NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unused +##NET "unnamed_net37" LOC = "B1" ; # TMS +##NET "unnamed_net36" LOC = "B22" ; # TDO +##NET "unnamed_net35" LOC = "D2" ; # TDI +##NET "unnamed_net34" LOC = "A21" ; # TCK +##NET "unnamed_net45" LOC = "F7" ; # PUDC_B +##NET "unnamed_net44" LOC = "V6" ; # M2 +##NET "unnamed_net43" LOC = "AA3" ; # M1 +##NET "unnamed_net42" LOC = "AB3" ; # M0 +##NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v new file mode 100644 index 000000000..459c226ee --- /dev/null +++ b/usrp2/top/u1e_passthru/passthru.v @@ -0,0 +1,18 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio0, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio0; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru -- cgit v1.2.3 From 4a573b5dcc78f9a13162efce09f0bc31f298a818 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 10 May 2010 13:23:48 -0700 Subject: proper signal level for 24 bit data --- usrp2/top/u1e/u1e_core.v | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 74ffc4657..a262184a8 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -349,15 +349,20 @@ module u1e_core cordic_z24 #(.bitwidth(24)) tx_cordic (.clock(wb_clk), .reset(wb_rst), .enable(1), - .xi(24'd15000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, +/* + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; +*/ + assign debug = { phase[23:8], txsync, txblank, tx }; + + assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { {rx_enable, rx_strobe, rx_fifo_rdy, rx_strobe & ~rx_fifo_rdy}, {tx_enable, tx_strobe, tx_fifo_rdy, tx_strobe & ~tx_fifo_rdy}, -- cgit v1.2.3 From 57114cf6579a0c6f8fc4626d4c20e8fc09cddb72 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 10 May 2010 14:56:14 -0700 Subject: switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_u1e necessary. --- usrp2/top/safe_u1e/.gitignore | 4 - usrp2/top/safe_u1e/Makefile | 246 --------------------------------- usrp2/top/safe_u1e/safe_u1e.ucf | 262 ------------------------------------ usrp2/top/safe_u1e/safe_u1e.v | 41 ------ usrp2/top/u1e/u1e.ucf | 2 +- usrp2/top/u1e_passthru/.gitignore | 1 + usrp2/top/u1e_passthru/passthru.ucf | 4 +- usrp2/top/u1e_passthru/passthru.v | 10 +- 8 files changed, 9 insertions(+), 561 deletions(-) delete mode 100644 usrp2/top/safe_u1e/.gitignore delete mode 100644 usrp2/top/safe_u1e/Makefile delete mode 100644 usrp2/top/safe_u1e/safe_u1e.ucf delete mode 100644 usrp2/top/safe_u1e/safe_u1e.v create mode 100644 usrp2/top/u1e_passthru/.gitignore diff --git a/usrp2/top/safe_u1e/.gitignore b/usrp2/top/safe_u1e/.gitignore deleted file mode 100644 index f8b57ea21..000000000 --- a/usrp2/top/safe_u1e/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*~ -build -*.log -*.cmd diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile deleted file mode 100644 index d28cc2b89..000000000 --- a/usrp2/top/safe_u1e/Makefile +++ /dev/null @@ -1,246 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u1e -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/safe_u1e/safe_u1e.ucf \ -top/safe_u1e/safe_u1e.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf deleted file mode 100644 index cb6d6372e..000000000 --- a/usrp2/top/safe_u1e/safe_u1e.ucf +++ /dev/null @@ -1,262 +0,0 @@ - -NET "CLK_FPGA_P" LOC = "Y11" ; -NET "CLK_FPGA_N" LOC = "Y10" ; - -## GPMC -NET "EM_CLK" LOC = "F11" ; - -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -#NET "EM_NCS6" LOC = "E17" ; -#NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE1" LOC = "D14" ; -#NET "EM_NBE0" LOC = "A13" ; -NET "EM_NWP" LOC = "F13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; - - -## Overo GPIO -#NET "overo_gpio0" LOC = "F9" ; -#NET "overo_gpio14" LOC = "C4" ; -#NET "overo_gpio21" LOC = "D5" ; -#NET "overo_gpio22" LOC = "A3" ; -#NET "overo_gpio23" LOC = "B3" ; -#NET "overo_gpio64" LOC = "A4" ; -#NET "overo_gpio65" LOC = "F8" ; -#NET "overo_gpio127" LOC = "C8" ; -#NET "overo_gpio128" LOC = "G8" ; -#NET "overo_gpio144" LOC = "A5" ; -#NET "overo_gpio145" LOC = "C7" ; -#NET "overo_gpio146" LOC = "A6" ; -#NET "overo_gpio147" LOC = "B6" ; -#NET "overo_gpio163" LOC = "D7" ; -#NET "overo_gpio170" LOC = "E8" ; -#NET "overo_gpio176" LOC = "B4" ; - -## Overo UART -#NET "overo_txd1" LOC = "C6" ; -#NET "overo_rxd1" LOC = "D6" ; - -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; - -#NET "SYSEN" LOC = "C11" ; - -#NET "db_scl" LOC = "U4" ; -#NET "db_sda" LOC = "U5" ; -#NET "db_sclk_rx" LOC = "W3" ; -#NET "db_miso_rx" LOC = "W2" ; -#NET "db_mosi_rx" LOC = "V4" ; -#NET "db_sen_rx" LOC = "V3" ; -#NET "db_sclk_tx" LOC = "Y1" ; -#NET "db_miso_tx" LOC = "W1" ; -#NET "db_mosi_tx" LOC = "R3" ; -#NET "db_sen_tx" LOC = "T4" ; - -## Clock Gen -#NET "cgen_miso" LOC = "U2" ; -#NET "cgen_mosi" LOC = "V1" ; -#NET "cgen_sclk" LOC = "R5" ; -#NET "cgen_sen_b" LOC = "T1" ; -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; - -## Debug pins -NET "debug_led<2>" LOC = "T5" ; -NET "debug_led<1>" LOC = "R2" ; -NET "debug_led<0>" LOC = "R1" ; -NET "debug<0>" LOC = "P6" ; -NET "debug<1>" LOC = "R6" ; -NET "debug<2>" LOC = "P1" ; -NET "debug<3>" LOC = "P2" ; -NET "debug<4>" LOC = "N6" ; -NET "debug<5>" LOC = "N5" ; -NET "debug<6>" LOC = "N1" ; -NET "debug<7>" LOC = "K2" ; -NET "debug<8>" LOC = "K3" ; -NET "debug<9>" LOC = "K6" ; -NET "debug<10>" LOC = "L5" ; -NET "debug<11>" LOC = "H2" ; -NET "debug<12>" LOC = "K4" ; -NET "debug<13>" LOC = "K5" ; -NET "debug<14>" LOC = "G1" ; -NET "debug<15>" LOC = "H1" ; -NET "debug<16>" LOC = "H5" ; -NET "debug<17>" LOC = "H6" ; -NET "debug<18>" LOC = "E3" ; -NET "debug<19>" LOC = "E4" ; -NET "debug<20>" LOC = "G5" ; -NET "debug<21>" LOC = "G6" ; -NET "debug<22>" LOC = "F2" ; -NET "debug<23>" LOC = "F1" ; -NET "debug<24>" LOC = "H3" ; -NET "debug<25>" LOC = "H4" ; -NET "debug<26>" LOC = "F4" ; -NET "debug<27>" LOC = "F5" ; -NET "debug<28>" LOC = "C2" ; -NET "debug<29>" LOC = "C1" ; -NET "debug<30>" LOC = "F3" ; -NET "debug<31>" LOC = "G3" ; -NET "debug_clk<0>" LOC = "L6" ; -NET "debug_clk<1>" LOC = "M5" ; - -#NET "debug_pb<2>" LOC = "Y2" ; -#NET "debug_pb<1>" LOC = "AA1" ; -#NET "debug_pb<0>" LOC = "N3" ; - -#NET "dip_sw<7>" LOC = "T3" ; -#NET "dip_sw<6>" LOC = "U3" ; -#NET "dip_sw<5>" LOC = "M3" ; -#NET "dip_sw<4>" LOC = "N4" ; -#NET "dip_sw<3>" LOC = "J3" ; -#NET "dip_sw<2>" LOC = "J4" ; -#NET "dip_sw<1>" LOC = "J6" ; -#NET "dip_sw<0>" LOC = "J7" ; - -## AD9862 Interface -#NET "aux_sdi_codec" LOC = "F19" ; -#NET "aux_sdo_codec" LOC = "F18" ; -#NET "aux_sclk_codec" LOC = "D21" ; -#NET "reset_codec" LOC = "D22" ; -#NET "sen_codec" LOC = "D20" ; -#NET "mosi_codec" LOC = "E19" ; -#NET "miso_codec" LOC = "F21" ; -#NET "sclk_codec" LOC = "E20" ; - -#NET "RXSYNC" LOC = "F22" ; - -#NET "DB<11>" LOC = "E22" ; -#NET "DB<10>" LOC = "J19" ; -#NET "DB<9>" LOC = "H20" ; -#NET "DB<8>" LOC = "G19" ; -#NET "DB<7>" LOC = "F20" ; -#NET "DB<6>" LOC = "K16" ; -#NET "DB<5>" LOC = "J17" ; -#NET "DB<4>" LOC = "H22" ; -#NET "DB<3>" LOC = "G22" ; -#NET "DB<2>" LOC = "H17" ; -#NET "DB<1>" LOC = "H18" ; -#NET "DB<0>" LOC = "K20" ; -#NET "DA<11>" LOC = "J20" ; -#NET "DA<10>" LOC = "K19" ; -#NET "DA<9>" LOC = "K18" ; -#NET "DA<8>" LOC = "L22" ; -#NET "DA<7>" LOC = "K22" ; -#NET "DA<6>" LOC = "N22" ; -#NET "DA<5>" LOC = "M22" ; -#NET "DA<4>" LOC = "N20" ; -#NET "DA<3>" LOC = "N19" ; -#NET "DA<2>" LOC = "R22" ; -#NET "DA<1>" LOC = "P22" ; -#NET "DA<0>" LOC = "N17" ; - -#NET "TX<13>" LOC = "P19" ; -#NET "TX<12>" LOC = "R18" ; -#NET "TX<11>" LOC = "U20" ; -#NET "TX<10>" LOC = "T20" ; -#NET "TX<9>" LOC = "R19" ; -#NET "TX<8>" LOC = "R20" ; -#NET "TX<7>" LOC = "W22" ; -#NET "TX<6>" LOC = "Y22" ; -#NET "TX<5>" LOC = "T18" ; -#NET "TX<4>" LOC = "T17" ; -#NET "TX<3>" LOC = "W19" ; -#NET "TX<2>" LOC = "V20" ; -#NET "TX<1>" LOC = "Y21" ; -#NET "TX<0>" LOC = "AA22" ; -#NET "TXSYNC" LOC = "U18" ; -#NET "TXBLANK" LOC = "U19" ; - -#NET "PPS_IN" LOC = "M17" ; - -#NET "io_tx<0>" LOC = "AB20" ; -#NET "io_tx<1>" LOC = "Y17" ; -#NET "io_tx<2>" LOC = "Y16" ; -#NET "io_tx<3>" LOC = "U16" ; -#NET "io_tx<4>" LOC = "V16" ; -#NET "io_tx<5>" LOC = "AB19" ; -#NET "io_tx<6>" LOC = "AA19" ; -#NET "io_tx<7>" LOC = "U14" ; -#NET "io_tx<8>" LOC = "U15" ; -#NET "io_tx<9>" LOC = "AB17" ; -#NET "io_tx<10>" LOC = "AB18" ; -#NET "io_tx<11>" LOC = "Y13" ; -#NET "io_tx<12>" LOC = "W14" ; -#NET "io_tx<13>" LOC = "U13" ; -#NET "io_tx<14>" LOC = "AA15" ; -#NET "io_tx<15>" LOC = "AB14" ; - -#NET "io_rx<0>" LOC = "Y8" ; -#NET "io_rx<1>" LOC = "Y9" ; -#NET "io_rx<2>" LOC = "V7" ; -#NET "io_rx<3>" LOC = "U8" ; -#NET "io_rx<4>" LOC = "V10" ; -#NET "io_rx<5>" LOC = "U9" ; -#NET "io_rx<6>" LOC = "AB7" ; -#NET "io_rx<7>" LOC = "AA8" ; -#NET "io_rx<8>" LOC = "W8" ; -#NET "io_rx<9>" LOC = "V8" ; -#NET "io_rx<10>" LOC = "AB5" ; -#NET "io_rx<11>" LOC = "AB6" ; -#NET "io_rx<12>" LOC = "AB4" ; -#NET "io_rx<13>" LOC = "AA4" ; -#NET "io_rx<14>" LOC = "W5" ; -#NET "io_rx<15>" LOC = "Y4" ; - -#NET "CLKOUT2_CODEC" LOC = "U12" ; -#NET "CLKOUT1_CODEC" LOC = "V12" ; - -## FPGA Config Pins -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "AB21" ; -#NET "fpga_cfg_din" LOC = "W17" ; -#NET "fpga_cfg_cclk" LOC = "V17" ; -#NET "fpga_cfg_init_b" LOC = "W15" ; - -## Unnamed, need to figure out what they do -#NET "unnamed_net37" LOC = "B1" ; -#NET "unnamed_net36" LOC = "B22" ; -#NET "unnamed_net35" LOC = "D2" ; -#NET "unnamed_net34" LOC = "A21" ; -#NET "unnamed_net45" LOC = "F7" ; -#NET "unnamed_net44" LOC = "V6" ; -#NET "unnamed_net43" LOC = "AA3" ; -#NET "unnamed_net42" LOC = "AB3" ; - -#NET "GND" LOC = "V19" ; diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v deleted file mode 100644 index dee9c6067..000000000 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ /dev/null @@ -1,41 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u1e - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - - // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE - ); - - // FPGA-specific pins connections - wire clk_fpga; - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - - // Debug circuitry - reg [31:0] ctr; - always @(posedge clk_fpga) - ctr <= ctr + 1; - - - assign debug_led = ctr[27:25]; - assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, - { EM_D } }; - - wire EM_output_enable = (~EM_NOE & ~EM_NCS4); - wire [15:0] EM_D_out; - - assign EM_D = EM_output_enable ? EM_D_out : 16'bz; - - ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), - .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); - - -endmodule // safe_u2plus diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index a73ebceb8..2caa46639 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -54,7 +54,7 @@ NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug, also used on the passthru image as the cgen_sen_b pin NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug NET "overo_gpio144" LOC = "A5" ; # tx_have_space NET "overo_gpio145" LOC = "C7" ; # tx_underrun diff --git a/usrp2/top/u1e_passthru/.gitignore b/usrp2/top/u1e_passthru/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/u1e_passthru/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf index 1672132a2..3ffe33882 100644 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -47,14 +47,14 @@ ##NET "EM_NWP" LOC = "F13" ; ## Overo GPIO -NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +#NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug #NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug #NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug #NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug #NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug #NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug #NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -#NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +NET "overo_gpio127" LOC = "C8" ; # passed through as cgen_sen_b #NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug #NET "overo_gpio144" LOC = "A5" ; # tx_have_space #NET "overo_gpio145" LOC = "C7" ; # tx_underrun diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v index 459c226ee..d846f2cf6 100644 --- a/usrp2/top/u1e_passthru/passthru.v +++ b/usrp2/top/u1e_passthru/passthru.v @@ -2,16 +2,16 @@ ////////////////////////////////////////////////////////////////////////////////// module passthru - (input overo_gpio0, - output cgen_sclk, - output cgen_sen_b, - output cgen_mosi, + (input overo_gpio127, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, input fpga_cfg_din, input fpga_cfg_cclk ); assign cgen_sclk = fpga_cfg_cclk; - assign cgen_sen_b = overo_gpio0; + assign cgen_sen_b = overo_gpio127; assign cgen_mosi = fpga_cfg_din; -- cgit v1.2.3 From 247e36dcbace9ef06763c2c537b44c8225a9d6a7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 12 May 2010 16:12:00 -0700 Subject: packet generator and verifier, to test gpmc and other data transfer stuff --- usrp2/control_lib/newfifo/.gitignore | 2 + usrp2/control_lib/newfifo/packet_generator.v | 59 ++++++++++++++++++++++++++ usrp2/control_lib/newfifo/packet_tb.v | 29 +++++++++++++ usrp2/control_lib/newfifo/packet_verifier.v | 63 ++++++++++++++++++++++++++++ 4 files changed, 153 insertions(+) create mode 100644 usrp2/control_lib/newfifo/packet_generator.v create mode 100644 usrp2/control_lib/newfifo/packet_tb.v create mode 100644 usrp2/control_lib/newfifo/packet_verifier.v diff --git a/usrp2/control_lib/newfifo/.gitignore b/usrp2/control_lib/newfifo/.gitignore index cba7efc8e..866f1faad 100644 --- a/usrp2/control_lib/newfifo/.gitignore +++ b/usrp2/control_lib/newfifo/.gitignore @@ -1 +1,3 @@ +*.vcd +*.lxt a.out diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v new file mode 100644 index 000000000..e5bfe5b26 --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_generator.v @@ -0,0 +1,59 @@ + + +module packet_generator + (input clk, input reset, input clear, + output reg [7:0] data_o, output sof_o, output eof_o, + output src_rdy_o, input dst_rdy_i); + + localparam len = 32'd100; + + reg [31:0] state; + reg [31:0] seq; + wire [31:0] crc_out; + wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF); + + + always @(posedge clk) + if(reset | clear) + seq <= 0; + else + if(eof_o & src_rdy_o & dst_rdy_i) + seq <= seq + 1; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_o & dst_rdy_i) + if(state == (len - 1)) + state <= 32'hFFFF_FFFC; + else + state <= state + 1; + + always @* + case(state) + 0 : data_o <= len[7:0]; + 1 : data_o <= len[15:8]; + 2 : data_o <= len[23:16]; + 3 : data_o <= len[31:24]; + 4 : data_o <= seq[7:0]; + 5 : data_o <= seq[15:8]; + 6 : data_o <= seq[23:16]; + 7 : data_o <= seq[31:24]; + 32'hFFFF_FFFC : data_o <= crc_out[31:24]; + 32'hFFFF_FFFD : data_o <= crc_out[23:16]; + 32'hFFFF_FFFE : data_o <= crc_out[15:8]; + 32'hFFFF_FFFF : data_o <= crc_out[7:0]; + default : data_o <= state[7:0]; + endcase // case (state) + + assign src_rdy_o = 1; + assign sof_o = (state == 0); + assign eof_o = (state == 32'hFFFF_FFFF); + + wire clear_crc = eof_o & src_rdy_o & dst_rdy_i; + + crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), + .calc(calc_crc), .crc_out(crc_out), .match()); + +endmodule // packet_generator diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/control_lib/newfifo/packet_tb.v new file mode 100644 index 000000000..3c423d2ba --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_tb.v @@ -0,0 +1,29 @@ + + +module packet_tb(); + + wire [7:0] data; + wire sof, eof, src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet_tb.vcd"); + initial $dumpvars(0,packet_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .sof_o(sof), .eof_o(eof), + .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .sof_i(sof), .eof_i(eof), + .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_tb diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v new file mode 100644 index 000000000..22c924198 --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_verifier.v @@ -0,0 +1,63 @@ + + +// Packet format -- +// Line 1 -- Length, 32 bits +// Line 2 -- Sequence number, 32 bits +// Last line -- CRC, 32 bits + +module packet_verifier + (input clk, input reset, input clear, + input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o, + + output reg [31:0] total, + output reg [31:0] crc_err, + output reg [31:0] seq_err, + output reg [31:0] len_err); + + assign dst_rdy_o = ~last_byte_d1; + + reg [31:0] seq_num; + reg [31:0] length; + + wire calc_crc = src_rdy_i & dst_rdy_o; + + crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), + .calc(calc_crc), .crc_out(), .match(match_crc)); + + wire first_byte, last_byte; + reg second_byte, last_byte_d1; + + assign first_byte = src_rdy_i & dst_rdy_o & sof_i; + assign last_byte = src_rdy_i & dst_rdy_o & eof_i; + + // stubs for now + wire match_seq = 1; + wire match_len = 1; + + always @(posedge clk) + if(reset | clear) + last_byte_d1 <= 0; + else + last_byte_d1 <= last_byte; + + always @(posedge clk) + if(reset | clear) + begin + total <= 0; + crc_err <= 0; + seq_err <= 0; + len_err <= 0; + end + else + if(last_byte_d1) + begin + total <= total + 1; + if(~match_crc) + crc_err <= crc_err + 1; + else if(~match_seq) + seq_err <= seq_err + 1; + else if(~match_len) + seq_err <= len_err + 1; + end + +endmodule // packet_verifier -- cgit v1.2.3 From ed48630974fb8cbdc3b863b13d4e7d7e8fe31434 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 12 May 2010 16:16:18 -0700 Subject: add missing signal from sensitivity list --- usrp2/control_lib/nsgpio16LE.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v index d6d7dcf56..514b003ce 100644 --- a/usrp2/control_lib/nsgpio16LE.v +++ b/usrp2/control_lib/nsgpio16LE.v @@ -111,7 +111,7 @@ module nsgpio16LE integer n; reg [31:0] igpio; // temporary internal signal - always @(ctrl or line or debug_1 or debug_0 or atr) + always @(ctrl or line or debug_1 or debug_0 or atr or ddr) for(n=0;n<32;n=n+1) igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : (ctrl[n] ? atr[n] : line[n]) ) -- cgit v1.2.3 From b04a1beaab300000ce2d8a5814bd2e37af48286c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 12 May 2010 18:51:33 -0700 Subject: moved fifos into gpmc_async, reorganized top level a bit, added in crc packet gen and test --- usrp2/control_lib/newfifo/packet_generator32.v | 21 ++++++ usrp2/control_lib/newfifo/packet_verifier.v | 10 ++- usrp2/control_lib/newfifo/packet_verifier32.v | 23 +++++++ usrp2/gpmc/gpmc_async.v | 91 +++++++++++++++----------- usrp2/top/u1e/Makefile | 4 ++ usrp2/top/u1e/u1e_core.v | 61 ++++++++++------- 6 files changed, 144 insertions(+), 66 deletions(-) create mode 100644 usrp2/control_lib/newfifo/packet_generator32.v create mode 100644 usrp2/control_lib/newfifo/packet_verifier32.v diff --git a/usrp2/control_lib/newfifo/packet_generator32.v b/usrp2/control_lib/newfifo/packet_generator32.v new file mode 100644 index 000000000..6f8004964 --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_generator32.v @@ -0,0 +1,21 @@ + + +module packet_generator32 + (input clk, input reset, input clear, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + wire [7:0] ll_data; + wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n; + + packet_generator pkt_gen + (.clk(clk), .reset(reset), .clear(clear), + .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), + .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n)); + + ll8_to_fifo36 ll8_to_f36 + (.clk(clk), .reset(reset), .clear(clear), + .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof), + .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n), + .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i)); + +endmodule // packet_generator32 diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v index 22c924198..b49ad1bbb 100644 --- a/usrp2/control_lib/newfifo/packet_verifier.v +++ b/usrp2/control_lib/newfifo/packet_verifier.v @@ -7,28 +7,26 @@ module packet_verifier (input clk, input reset, input clear, - input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o, + input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o, output reg [31:0] total, output reg [31:0] crc_err, output reg [31:0] seq_err, output reg [31:0] len_err); - assign dst_rdy_o = ~last_byte_d1; - reg [31:0] seq_num; reg [31:0] length; + wire first_byte, last_byte; + reg second_byte, last_byte_d1; wire calc_crc = src_rdy_i & dst_rdy_o; crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), .calc(calc_crc), .crc_out(), .match(match_crc)); - wire first_byte, last_byte; - reg second_byte, last_byte_d1; - assign first_byte = src_rdy_i & dst_rdy_o & sof_i; assign last_byte = src_rdy_i & dst_rdy_o & eof_i; + assign dst_rdy_o = ~last_byte_d1; // stubs for now wire match_seq = 1; diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v new file mode 100644 index 000000000..065607b6c --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_verifier32.v @@ -0,0 +1,23 @@ + + +module packet_verifier32 + (input clk, input reset, input clear, + input [35:0] data_i, input src_rdy_i, output dst_rdy_o, + output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); + + wire [7:0] ll_data; + wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; + + fifo36_to_ll8 f36_to_ll8 + (.clk(clk), .reset(reset), .clear(clear), + .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); + + packet_verifier pkt_ver + (.clk(clk), .reset(reset), .clear(clear), + .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), + .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_verifier32 diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index dd06478b3..380689c62 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -1,37 +1,38 @@ ////////////////////////////////////////////////////////////////////////////////// module gpmc_async - (// GPMC signals - input arst, - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - - // GPIOs for FIFO signalling - output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset, - - // Wishbone signals - input wb_clk, input wb_rst, - output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + input [15:0] tx_frame_len, output [15:0] rx_frame_len, + + output [31:0] debug + ); - // FIFO interface - input fifo_clk, input fifo_rst, - output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, - input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - - input [15:0] tx_frame_len, output [15:0] rx_frame_len, + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; - output [31:0] debug - ); - - wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); - wire [15:0] EM_D_fifo; - wire [15:0] EM_D_wb; - assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; - - wire bus_error_tx, bus_error_rx; - + + wire bus_error_tx, bus_error_rx; + always @(posedge fifo_clk) if(fifo_rst) bus_error <= 0; @@ -45,9 +46,11 @@ module gpmc_async // //////////////////////////////////////////// // TX Data Path - wire [17:0] tx18_data, tx18b_data; - wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; - wire [15:0] tx_fifo_space; + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space; + wire [35:0] tx36_data; + wire tx36_src_rdy, tx36_dst_rdy; gpmc_to_fifo_async gpmc_to_fifo_async (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), @@ -64,18 +67,30 @@ module gpmc_async fifo19_to_fifo36 f19_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), - .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + // //////////////////////////////////////////// // RX Data Path - - wire [17:0] rx18_data, rx18b_data; - wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; - wire [15:0] rx_fifo_space; + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space; + wire [35:0] rx36_data; + wire rx36_src_rdy, rx36_dst_rdy; + + fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + fifo36_to_fifo18 f18_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo @@ -106,6 +121,6 @@ module gpmc_async .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i) ); - assign debug = 0; + assign debug = 0; endmodule // gpmc_async diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 2aebb33f9..8622b8480 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -111,6 +111,10 @@ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ control_lib/newfifo/fifo36_to_fifo18.v \ control_lib/newfifo/fifo19_to_fifo36.v \ +control_lib/newfifo/packet_generator.v \ +control_lib/newfifo/packet_verifier.v \ +control_lib/newfifo/packet_generator32.v \ +control_lib/newfifo/packet_verifier32.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index a262184a8..903121832 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,4 +1,9 @@ + +//`define LOOPBACK 1 +//`define TIMED 1 +`define CRC 1 + module u1e_core (input clk_fpga, input rst_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -61,47 +66,59 @@ module u1e_core .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .debug(debug_gpmc)); -/* + +`ifdef LOOPBACK fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); -*/ - wire tx_strobe, rx_strobe, tx_enable, rx_enable; + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; +`endif // LOOPBACK + +`ifdef TIMED wire [7:0] rate; - wire tx_fifo_rdy, rx_fifo_rdy; - + + // TX side + wire tx_enable; cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable), - .rate(rate), .strobe_fast(1), .strobe_slow(tx_strobe)); - - fifo_cascade #(.WIDTH(36), .SIZE(11)) tx_fifo - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .dataout(), .src_rdy_o(tx_fifo_rdy), .dst_rdy_i(tx_strobe)); + .rate(rate), .strobe_fast(1), .strobe_slow(tx_dst_rdy)); - + // RX side + wire rx_enable; reg [15:0] ctr; wire [15:0] rx_pkt_len = 480; wire rx_eof = (ctr == rx_pkt_len); wire rx_sof = (ctr == 0); cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable), - .rate(rate), .strobe_fast(1), .strobe_slow(rx_strobe)); + .rate(rate), .strobe_fast(1), .strobe_slow(rx_src_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(11)) rx_fifo - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .datain({2'b00,rx_eof,rx_sof,16'd0,ctr}), .src_rdy_i(rx_strobe), .dst_rdy_o(rx_fifo_rdy), - .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - always @(posedge wb_clk) if(wb_rst) ctr <= 0; - else if(rx_strobe & rx_fifo_rdy) + else if(rx_dst_rdy & rx_src_rdy) if(ctr == rx_pkt_len) ctr <= 0; else ctr <= ctr + 1; - + + assign rx_data = {2'b00,rx_eof,rx_sof,~ctr,ctr}; +`endif // TIMED + +`ifdef CRC + packet_generator32 pktgen32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + packet_verifier32 pktver32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; +`endif // CRC // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master @@ -364,8 +381,8 @@ module u1e_core assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { {rx_enable, rx_strobe, rx_fifo_rdy, rx_strobe & ~rx_fifo_rdy}, - {tx_enable, tx_strobe, tx_fifo_rdy, tx_strobe & ~tx_fifo_rdy}, + assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, + {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, {3'b0, bus_error, misc_gpio[11:0]} }; -- cgit v1.2.3 From 47230fadfbbde3b45fbf57e8ff506f4fac812ca2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 17 May 2010 20:59:55 -0700 Subject: better debug pins --- usrp2/top/u1e/u1e_core.v | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 903121832..4637df0cc 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,8 +1,8 @@ -//`define LOOPBACK 1 +`define LOOPBACK 1 //`define TIMED 1 -`define CRC 1 +//`define CRC 1 module u1e_core (input clk_fpga, input rst_fpga, @@ -372,12 +372,10 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; -/* - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; -*/ - assign debug = { phase[23:8], txsync, txblank, tx }; + //assign debug = { phase[23:8], txsync, txblank, tx }; assign debug_gpio_0 = { debug_gpmc }; -- cgit v1.2.3 From c94256034819feb26d739e57e8cf7d3f60539e9c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 00:30:49 -0700 Subject: combined timed and crc cases. fifo pacer produces/consumes at a fixed rate --- usrp2/control_lib/newfifo/fifo_pacer.v | 24 ++++++++++++++ usrp2/top/u1e/Makefile | 1 + usrp2/top/u1e/u1e_core.v | 57 ++++++++++++++-------------------- 3 files changed, 48 insertions(+), 34 deletions(-) create mode 100644 usrp2/control_lib/newfifo/fifo_pacer.v diff --git a/usrp2/control_lib/newfifo/fifo_pacer.v b/usrp2/control_lib/newfifo/fifo_pacer.v new file mode 100644 index 000000000..1bf03ab6e --- /dev/null +++ b/usrp2/control_lib/newfifo/fifo_pacer.v @@ -0,0 +1,24 @@ + + +module fifo_pacer + (input clk, + input reset, + input [7:0] rate, + input enable, + input src1_rdy_i, output dst1_rdy_o, + output src2_rdy_o, input dst2_rdy_i, + output underrun, overrun); + + wire strobe; + + cic_strober strober (.clock(clk), .reset(reset), .enable(enable), + .rate(rate), .strobe_fast(1), .strobe_slow(strobe)); + + wire all_ready = src1_rdy_i & dst2_rdy_i; + assign dst1_rdy_o = all_ready & strobe; + assign src2_rdy_o = dst1_rdy_o; + + assign underrun = strobe & ~src1_rdy_i; + assign overrun = strobe & ~dst2_rdy_i; + +endmodule // fifo_pacer diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 8622b8480..0277ef4f2 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -115,6 +115,7 @@ control_lib/newfifo/packet_generator.v \ control_lib/newfifo/packet_verifier.v \ control_lib/newfifo/packet_generator32.v \ control_lib/newfifo/packet_verifier32.v \ +control_lib/newfifo/fifo_pacer.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 903121832..21ac97dbd 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,8 +1,7 @@ //`define LOOPBACK 1 -//`define TIMED 1 -`define CRC 1 +`define TIMED 1 module u1e_core (input clk_fpga, input rst_fpga, @@ -80,45 +79,35 @@ module u1e_core wire [7:0] rate; // TX side - wire tx_enable; - cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable), - .rate(rate), .strobe_fast(1), .strobe_slow(tx_dst_rdy)); - - // RX side - wire rx_enable; - reg [15:0] ctr; - wire [15:0] rx_pkt_len = 480; - wire rx_eof = (ctr == rx_pkt_len); - wire rx_sof = (ctr == 0); + wire tx_enable, tx_src_rdy_int, tx_dst_rdy_int; - cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable), - .rate(rate), .strobe_fast(1), .strobe_slow(rx_src_rdy)); + fifo_pacer tx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), + .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy), + .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); - always @(posedge wb_clk) - if(wb_rst) - ctr <= 0; - else if(rx_dst_rdy & rx_src_rdy) - if(ctr == rx_pkt_len) - ctr <= 0; - else - ctr <= ctr + 1; - - assign rx_data = {2'b00,rx_eof,rx_sof,~ctr,ctr}; -`endif // TIMED - -`ifdef CRC - packet_generator32 pktgen32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear), - .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - packet_verifier32 pktver32 (.clk(wb_clk), .reset(wb_rst), .clear(clear), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + // RX side + wire rx_enable, rx_src_rdy_int, rx_dst_rdy_int; wire rx_sof = rx_data[32]; wire rx_eof = rx_data[33]; -`endif // CRC + + packet_generator32 pktgen32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear), + .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable), + .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int), + .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + +`endif // `ifdef TIMED // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master @@ -233,7 +222,7 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - assign { rx_overrun, tx_underrun } = 0; // reg_test; + //assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : -- cgit v1.2.3 From 3b96b1f0f443acb9412b40592de5dc13e1f840d6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 00:34:35 -0700 Subject: put over/underrun on debug bus, remove high order address bits --- usrp2/top/u1e/u1e_core.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 71b9b8712..48b5bd010 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -361,7 +361,8 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, + { EM_A[8:1] }, { EM_D } }; //assign debug = { phase[23:8], txsync, txblank, tx }; -- cgit v1.2.3 From c6e8d0658dc66e9a24a87d4574c649b77ec4075d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 13:43:13 -0700 Subject: removes the icache and pipelines the reads --- usrp2/control_lib/ram_harvard.v | 71 +++++++++++++++++++++++++ usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v | 5 +- usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v | 27 ++++++---- usrp2/top/u2_core/u2_core.v | 10 ++-- usrp2/top/u2_rev3/Makefile | 1 + 5 files changed, 98 insertions(+), 16 deletions(-) create mode 100644 usrp2/control_lib/ram_harvard.v diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v new file mode 100644 index 000000000..6711da366 --- /dev/null +++ b/usrp2/control_lib/ram_harvard.v @@ -0,0 +1,71 @@ + + +// Dual ported, Harvard architecture, cached ram + +module ram_harvard + #(parameter AWIDTH=15, + parameter RAM_SIZE=16384, + parameter ICWIDTH=6, + parameter DCWIDTH=6) + + (input wb_clk_i, + input wb_rst_i, + // Firmware download port. + input [AWIDTH-1:0] ram_loader_adr_i, + input [31:0] ram_loader_dat_i, + input ram_loader_stb_i, + input [3:0] ram_loader_sel_i, + input ram_loader_we_i, + output ram_loader_ack_o, + input ram_loader_done_i, + // Instruction fetch port. + input [AWIDTH-1:0] if_adr, + output [31:0] if_data, + // Data access port. + input [AWIDTH-1:0] dwb_adr_i, + input [31:0] dwb_dat_i, + output [31:0] dwb_dat_o, + input dwb_we_i, + output dwb_ack_o, + input dwb_stb_i, + input [3:0] dwb_sel_i, + + input flush_icache ); + + reg ack_d1; + reg stb_d1; + + + dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) + sys_ram + (.clk(wb_clk_i), + .adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i), + .dat1_i(ram_loader_dat_i), + .dat1_o(if_data), + .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i), + .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i), + .sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), + .adr2_i(dwb_adr_i), + .dat2_i(dwb_dat_i), + .dat2_o(dwb_dat_o), + .we2_i(dwb_we_i), + .en2_i(dwb_stb_i), + .sel2_i(dwb_sel_i) + ); + + assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1)); + + always @(posedge wb_clk_i) + if(wb_rst_i) + ack_d1 <= 1'b0; + else + ack_d1 <= dwb_ack_o; + + always @(posedge wb_clk_i) + if(wb_rst_i) + stb_d1 <= 0; + else + stb_d1 <= dwb_stb_i; + + +endmodule // ram_harv_cache diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v index a7c686e7e..81587e25c 100644 --- a/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v @@ -125,7 +125,7 @@ module aeMB_bpcu (/*AUTOARG*/ reg [31:2] rPC, xPC; reg [31:2] rPCLNK, xPCLNK; - assign iwb_adr_o = rIPC[IW-1:2]; + assign iwb_adr_o = gena ? xIPC[IW-1:2] : rIPC[IW-1:2]; //IJB always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin //xPCLNK <= (^rATOM) ? rPC : rPC; @@ -168,7 +168,8 @@ module aeMB_bpcu (/*AUTOARG*/ rATOM <= 2'h0; rBRA <= 1'h0; rDLY <= 1'h0; - rIPC <= 30'h0; +// rIPC <= 30'h0; + rIPC <= 30'h3fffffff; // DWORD aligned address rPC <= 30'h0; rPCLNK <= 30'h0; // End of automatics diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v index 9ffa20ff2..38ca3a023 100644 --- a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v @@ -10,12 +10,10 @@ module aeMB_core_BE parameter MUL=0, parameter BSF=0) (input sys_clk_i, input sys_rst_i, - - output iwb_stb_o, - output [ISIZ-1:0] iwb_adr_o, - input [31:0] iwb_dat_i, - input iwb_ack_i, - + // Instruction port + output [14:0] if_adr, + input [31:0] if_dat, + // Data port output dwb_we_o, output dwb_stb_o, output [DSIZ-1:0] dwb_adr_o, @@ -28,17 +26,28 @@ module aeMB_core_BE input sys_int_i, input sys_exc_i); - assign dwb_cyc_o = dwb_stb_o; + wire [ISIZ-1:0] iwb_adr_o; + wire [31:0] iwb_dat_i; + wire iwb_ack_i; + wire iwb_stb_o; + + assign dwb_cyc_o = dwb_stb_o; + assign iwb_ack_i = 1'b1; + assign if_adr = iwb_adr_o[14:0]; + assign iwb_dat_i = if_dat; + + // Note some "wishbone" instruction fetch signals pruned on external interface + // but not propogated change deep into aeMB. aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF)) aeMB_edk32 (.sys_clk_i(sys_clk_i), .sys_rst_i(sys_rst_i), - + // Instruction Port .iwb_stb_o(iwb_stb_o), .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), .iwb_ack_i(iwb_ack_i), .iwb_dat_i(iwb_dat_i), - + // Data port .dwb_wre_o(dwb_we_o), .dwb_stb_o(dwb_stb_o), .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index df74c7dba..5e0b569cc 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -284,8 +284,8 @@ module u2_core aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + .if_adr(if_adr), + .if_dat(if_dat), // Data Wishbone bus to system bus fabric .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), @@ -299,7 +299,7 @@ module u2_core // I-port connects directly to processor and ram loader wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), @@ -307,8 +307,8 @@ module u2_core .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), .ram_loader_done_i(ram_loader_done), - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + .if_adr(if_adr), + .if_data(if_dat), .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 80d09acb7..bfebcac8b 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -66,6 +66,7 @@ control_lib/mux4.v \ control_lib/mux8.v \ control_lib/nsgpio.v \ control_lib/ram_2port.v \ +control_lib/ram_harvard.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ -- cgit v1.2.3 From 1d38c098122746ff34c0c1f16668b44d7337175d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 16:48:59 -0700 Subject: send bigger packets to reduce cpu load --- usrp2/control_lib/newfifo/packet_generator.v | 2 +- usrp2/top/u1e/u1e_core.v | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v index e5bfe5b26..6e8b45ccd 100644 --- a/usrp2/control_lib/newfifo/packet_generator.v +++ b/usrp2/control_lib/newfifo/packet_generator.v @@ -5,7 +5,7 @@ module packet_generator output reg [7:0] data_o, output sof_o, output eof_o, output src_rdy_o, input dst_rdy_i); - localparam len = 32'd100; + localparam len = 32'd2000; reg [31:0] state; reg [31:0] seq; diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 48b5bd010..ee193ffb9 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -43,6 +43,7 @@ module u1e_core wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; + wire [7:0] rate; wire bus_error; @@ -76,7 +77,6 @@ module u1e_core `endif // LOOPBACK `ifdef TIMED - wire [7:0] rate; // TX side wire tx_enable, tx_src_rdy_int, tx_dst_rdy_int; @@ -362,7 +362,7 @@ module u1e_core assign debug_clk = { EM_CLK, clk_fpga }; assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, - { EM_A[8:1] }, + { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; //assign debug = { phase[23:8], txsync, txblank, tx }; -- cgit v1.2.3 From 268324b62898a916c0ef01e9336c34cd4ae1ff93 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 21 May 2010 15:56:01 -0700 Subject: fix double declaration --- usrp2/control_lib/newfifo/fifo36_to_ll8.v | 1 - 1 file changed, 1 deletion(-) diff --git a/usrp2/control_lib/newfifo/fifo36_to_ll8.v b/usrp2/control_lib/newfifo/fifo36_to_ll8.v index 0dee1dfc6..9604d0e38 100644 --- a/usrp2/control_lib/newfifo/fifo36_to_ll8.v +++ b/usrp2/control_lib/newfifo/fifo36_to_ll8.v @@ -55,6 +55,5 @@ module fifo36_to_ll8 assign advance = ll_src_rdy & ll_dst_rdy; assign f36_dst_rdy_o = advance & ((state==3)|ll_eof); - assign debug = state; endmodule // ll8_to_fifo36 -- cgit v1.2.3 From d3e6f630945076cc9d5fb91e86e1caf0b554ac89 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 21 May 2010 15:56:18 -0700 Subject: fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock (by design) --- usrp2/control_lib/newfifo/packet_verifier32.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v index 065607b6c..06a13d242 100644 --- a/usrp2/control_lib/newfifo/packet_verifier32.v +++ b/usrp2/control_lib/newfifo/packet_verifier32.v @@ -7,10 +7,17 @@ module packet_verifier32 wire [7:0] ll_data; wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_short #(.WIDTH(36)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); fifo36_to_ll8 f36_to_ll8 (.clk(clk), .reset(reset), .clear(clear), - .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); -- cgit v1.2.3 From 6f63773d7425dd952c5ca24da618c22c486ae294 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 24 May 2010 11:34:42 -0700 Subject: test full width packets --- usrp2/control_lib/newfifo/packet32_tb.v | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 usrp2/control_lib/newfifo/packet32_tb.v diff --git a/usrp2/control_lib/newfifo/packet32_tb.v b/usrp2/control_lib/newfifo/packet32_tb.v new file mode 100644 index 000000000..82bb09c29 --- /dev/null +++ b/usrp2/control_lib/newfifo/packet32_tb.v @@ -0,0 +1,27 @@ + + +module packet32_tb(); + + wire [35:0] data; + wire src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet32_tb.vcd"); + initial $dumpvars(0,packet32_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet32_tb -- cgit v1.2.3 From d32cedbf00eb342d999832737f9f1ba2109ef2ad Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 24 May 2010 14:21:03 -0700 Subject: fixes from IJB from 5/24. Basically connect unconnected wires. --- usrp2/control_lib/ram_harvard.v | 2 ++ usrp2/top/u2_core/u2_core.v | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v index 6711da366..3c00f87c7 100644 --- a/usrp2/control_lib/ram_harvard.v +++ b/usrp2/control_lib/ram_harvard.v @@ -36,6 +36,8 @@ module ram_harvard reg stb_d1; + assign ram_loader_ack_o = ram_loader_stb_i; + dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram (.clk(wb_clk_i), diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 5e0b569cc..600bd7f3f 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -259,8 +259,9 @@ module u2_core // /////////////////////////////////////////////////////////////////// // RAM Loader - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; + wire [31:0] ram_loader_dat, if_dat; + wire [15:0] ram_loader_adr; + wire [14:0] if_adr; wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we, ram_loader_ack; wire iwb_ack, iwb_stb; -- cgit v1.2.3 From a1284e5d02fbb9e0b7cf541a9ffe501707d37c8c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 26 May 2010 18:45:01 -0700 Subject: experimental mods to make ram loader fully synchronous. Based on IJB's work --- usrp2/control_lib/ram_harvard.v | 12 +- usrp2/control_lib/ram_loader.v | 460 ++++++++++++++++++++++------------------ usrp2/top/u2_core/u2_core.v | 29 ++- 3 files changed, 266 insertions(+), 235 deletions(-) diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v index 3c00f87c7..948f9b36f 100644 --- a/usrp2/control_lib/ram_harvard.v +++ b/usrp2/control_lib/ram_harvard.v @@ -13,10 +13,9 @@ module ram_harvard // Firmware download port. input [AWIDTH-1:0] ram_loader_adr_i, input [31:0] ram_loader_dat_i, - input ram_loader_stb_i, input [3:0] ram_loader_sel_i, + input ram_loader_stb_i, input ram_loader_we_i, - output ram_loader_ack_o, input ram_loader_done_i, // Instruction fetch port. input [AWIDTH-1:0] if_adr, @@ -35,9 +34,6 @@ module ram_harvard reg ack_d1; reg stb_d1; - - assign ram_loader_ack_o = ram_loader_stb_i; - dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram (.clk(wb_clk_i), @@ -46,7 +42,8 @@ module ram_harvard .dat1_o(if_data), .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i), .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i), - .sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), + //.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), + .sel1_i(ram_loader_sel_i), // Sel is only for writes anyway .adr2_i(dwb_adr_i), .dat2_i(dwb_dat_i), .dat2_o(dwb_dat_o), @@ -68,6 +65,5 @@ module ram_harvard stb_d1 <= 0; else stb_d1 <= dwb_stb_i; - -endmodule // ram_harv_cache +endmodule // ram_harvard diff --git a/usrp2/control_lib/ram_loader.v b/usrp2/control_lib/ram_loader.v index cb67de739..c53ea7aa7 100644 --- a/usrp2/control_lib/ram_loader.v +++ b/usrp2/control_lib/ram_loader.v @@ -1,225 +1,261 @@ +module ram_loader + #(parameter AWIDTH=16, RAM_SIZE=16384) + ( + // Wishbone I/F and clock domain + input wb_clk, + input dsp_clk, + input ram_loader_rst, + output wire [31:0] wb_dat, + output wire [AWIDTH-1:0] wb_adr, + output wb_stb, + output reg [3:0] wb_sel, + output wb_we, + output reg ram_loader_done, + // CPLD signals and clock domain + input cpld_clk, + input cpld_din, + output reg cpld_start, + output reg cpld_mode, + output reg cpld_done, + input cpld_detached + ); -// Adapted from VHDL code in spi_boot by Arnim Legauer -// Added a full wishbone master interface (32-bit) - -module ram_loader #(parameter AWIDTH=16, RAM_SIZE=16384) - (input clk_i, input rst_i, - // CPLD Interface - input cfg_clk_i, input cfg_data_i, - output start_o, output mode_o, output done_o, - input detached_i, - // Wishbone interface - output wire [31:0] wb_dat_o, - output reg [AWIDTH-1:0] wb_adr_o, - output wb_stb_o, - output wb_cyc_o, - output reg [3:0] wb_sel_o, - output reg wb_we_o, - input wb_ack_i, - output ram_loader_done_o); + localparam S0 = 0; + localparam S1 = 1; + localparam S2 = 2; + localparam S3 = 3; + localparam S4 = 4; + localparam S5 = 5; + localparam S6 = 6; + localparam RESET = 7; - // FSM to control start signal, clocked on main clock - localparam FSM1_WAIT_DETACH = 2'b00; - localparam FSM1_CHECK_NO_DONE = 2'b01; - localparam FSM1_WAIT_DONE = 2'b10; - - reg [1:0] start_fsm_q, start_fsm_s; - reg start_q, enable_q, start_s, enable_s; - reg done_q, done_s; + localparam WB_IDLE = 0; + localparam WB_WRITE = 1; + + + reg [AWIDTH+2:0] count; // 3 LSB's count bits in, the MSB's generate the Wishbone address + reg [6:0] shift_reg; + reg [7:0] data_reg; + reg sampled_clk; + reg sampled_clk_meta; + reg sampled_din; + reg inc_count; + reg load_data_reg; + reg shift; + reg wb_state, wb_next_state; + reg [2:0] state, next_state; + + // + // CPLD clock doesn't free run and is approximately 12.5MHz. + // Use 50MHz Wishbone clock to sample it as a signal and avoid having + // an extra clock domain for no reason. + // + + always @(posedge dsp_clk or posedge ram_loader_rst) + if (ram_loader_rst) + begin + sampled_clk_meta <= 1'b0; + sampled_clk <= 1'b0; + sampled_din <= 1'b0; + count <= 'h7FFF8; // Initialize so that address will be 0 when first byte fully received. + data_reg <= 0; + shift_reg <= 0; + end + else + begin + sampled_clk_meta <= cpld_clk; + sampled_clk <= sampled_clk_meta; + sampled_din <= cpld_din; + if (inc_count) + count <= count + 1'b1; + if (load_data_reg) + data_reg <= {shift_reg,sampled_din}; + if (shift) + shift_reg <= {shift_reg[5:0],sampled_din}; + end // else: !if(ram_loader_rst) - always @(posedge clk_i or posedge rst_i) - if(rst_i) - begin - start_fsm_q <= FSM1_WAIT_DETACH; - start_q <= 1'b0; - enable_q <= 1'b0; - end + + always @(posedge dsp_clk or posedge ram_loader_rst) + if (ram_loader_rst) + state <= RESET; else - begin - start_fsm_q <= start_fsm_s; - enable_q <= enable_s; - start_q <= start_s; - end // else: !if(rst_i) - + state <= next_state; + + always @* - case(start_fsm_q) - FSM1_WAIT_DETACH: - if(detached_i == 1'b1) - begin - start_fsm_s <= FSM1_CHECK_NO_DONE; - enable_s <= 1'b1; - start_s <= 1'b1; - end - else - begin - start_fsm_s <= FSM1_WAIT_DETACH; - enable_s <= enable_q; - start_s <= start_q; - end // else: !if(detached_i == 1'b1) - FSM1_CHECK_NO_DONE: - if(~done_q) - begin - start_fsm_s <= FSM1_WAIT_DONE; - enable_s <= enable_q; - start_s <= start_q; - end - else - begin - start_fsm_s <= FSM1_CHECK_NO_DONE; - enable_s <= enable_q; - start_s <= start_q; - end // else: !if(~done_q) - FSM1_WAIT_DONE: - if(done_q) - begin - start_fsm_s <= FSM1_WAIT_DETACH; - enable_s <= 1'b0; - start_s <= 1'b0; - end - else - begin - start_fsm_s <= FSM1_WAIT_DONE; - enable_s <= enable_q; - start_s <= start_q; - end // else: !if(done_q) - default: - begin - start_fsm_s <= FSM1_WAIT_DETACH; - enable_s <= enable_q; - start_s <= start_q; - end // else: !if(done_q) - endcase // case(start_fsm_q) - - // FSM running on data clock - - localparam FSM2_IDLE = 3'b000; - localparam FSM2_WE_ON = 3'b001; - localparam FSM2_WE_OFF = 3'b010; - localparam FSM2_INC_ADDR1 = 3'b011; - localparam FSM2_INC_ADDR2 = 3'b100; - localparam FSM2_FINISHED = 3'b101; - - reg [AWIDTH-1:0] addr_q; - reg [7:0] shift_dat_q, ser_dat_q; - reg [2:0] bit_q, fsm_q, fsm_s; - reg bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s, inc_addr_s; - - always @(posedge cfg_clk_i or posedge rst_i) - if(rst_i) - begin - addr_q <= 0; - shift_dat_q <= 8'd0; - ser_dat_q <= 8'd0; - bit_q <= 3'd0; - bit_ovfl_q <= 1'b0; - fsm_q <= FSM2_IDLE; - ram_we_q <= 1'b0; - done_q <= 1'b0; - mode_q <= 1'b0; - end + begin + // Defaults + next_state = state; + cpld_start = 1'b0; + shift = 1'b0; + inc_count = 0; + load_data_reg = 1'b0; + ram_loader_done = 1'b0; + cpld_mode = 1'b0; + cpld_done = 1'b1; + + + + case (state) //synthesis parallel_case full_case + // After reset wait until CPLD indicates its detached. + RESET: begin + if (cpld_detached) + next_state = S0; + else + next_state = RESET; + end + + // Assert cpld_start to signal the CPLD its to start sending serial clock and data. + // Assume cpld_clk is low as we transition into search for first rising edge + S0: begin + cpld_start = 1'b1; + cpld_done = 1'b0; + if (~cpld_detached) + next_state = S2; + else + next_state = S0; + end + + // + S1: begin + cpld_start = 1'b1; + cpld_done = 1'b0; + if (sampled_clk) + begin + // Found rising edge on cpld_clk. + if (count[2:0] == 3'b111) + // Its the last bit of a byte, send it out to the Wishbone bus. + begin + load_data_reg = 1'b1; + inc_count = 1'b1; + end + else + // Shift databit into LSB of shift register and increment count + begin + shift = 1'b1; + inc_count = 1'b1; + end // else: !if(count[2:0] == 3'b111) + next_state = S2; + end // if (sampled_clk) + else + next_state = S1; + end // case: S1 + + // + S2: begin + cpld_start = 1'b1; + cpld_done = 1'b0; + if (~sampled_clk) + // Found negative edge of clock + if (count[AWIDTH+2:3] == RAM_SIZE-1) // NOTE need to change this constant + // All firmware now downloaded + next_state = S3; + else + next_state = S1; + else + next_state = S2; + end // case: S2 + + // Now that terminal count is reached and all firmware is downloaded signal CPLD that download is done + // and that mode is now SPI mode. + S3: begin + if (sampled_clk) + begin + cpld_mode = 1'b1; + cpld_done = 1'b1; + next_state = S4; + end + else + next_state = S3; + end + + // Search for negedge of cpld_clk whilst keeping done sequence asserted. + // Keep done assserted + S4: begin + cpld_mode = 1'b1; + cpld_done = 1'b1; + if (~sampled_clk) + next_state = S5; + else + next_state = S4; + end + + // Search for posedge of cpld_clk whilst keeping done sequence asserted. + S5: begin + cpld_mode = 1'b1; + cpld_done = 1'b1; + if (sampled_clk) + next_state = S6; + else + next_state = S5; + end + + // Stay in this state until reset/power down + S6: begin + ram_loader_done = 1'b1; + cpld_done = 1'b1; + cpld_mode = 1'b1; + next_state = S6; + end + + endcase // case(state) + end + + always @(posedge dsp_clk or posedge ram_loader_rst) + if (ram_loader_rst) + wb_state <= WB_IDLE; else - begin - if(inc_addr_s) - addr_q <= addr_q + 1; - if(enable_q) - begin - bit_q <= bit_q + 1; - bit_ovfl_q <= (bit_q == 3'd7); - shift_dat_q[0] <= cfg_data_i; - shift_dat_q[7:1] <= shift_dat_q[6:0]; - end - if(bit_ovfl_q) - ser_dat_q <= shift_dat_q; - - fsm_q <= fsm_s; - - ram_we_q <= ram_we_s; - - if(done_s) - done_q <= 1'b1; - mode_q <= mode_s; - end // else: !if(rst_i) + wb_state <= wb_next_state; + reg do_write; + wire empty, full; + always @* begin - inc_addr_s <= 1'b0; - ram_we_s <= 1'b0; - done_s <= 1'b0; - fsm_s <= FSM2_IDLE; - mode_s <= 1'b0; - - case(fsm_q) - FSM2_IDLE : - if(start_q) - if(bit_ovfl_q) - fsm_s <= FSM2_WE_ON; - FSM2_WE_ON: - begin - ram_we_s <= 1'b1; - fsm_s <= FSM2_WE_OFF; - end - FSM2_WE_OFF: - begin - ram_we_s <= 1'b1; - fsm_s <= FSM2_INC_ADDR1; - end - FSM2_INC_ADDR1: - fsm_s <= FSM2_INC_ADDR2; - FSM2_INC_ADDR2: - if(addr_q == (RAM_SIZE-1)) - //if(&addr_q) - begin - fsm_s <= FSM2_FINISHED; - done_s <= 1'b1; - mode_s <= 1'b1; - end - else - begin - inc_addr_s <= 1'b1; - fsm_s <= FSM2_IDLE; - end // else: !if(&addr_q) - FSM2_FINISHED: - begin - fsm_s <= FSM2_FINISHED; - mode_s <= 1'b1; - end - endcase // case(fsm_q) + wb_next_state = wb_state; + do_write = 1'b0; + + case (wb_state) //synthesis full_case parallel_case + // + WB_IDLE: begin + if (load_data_reg) + // Data reg will load ready to write wishbone @ next clock edge + wb_next_state = WB_WRITE; + else + wb_next_state = WB_IDLE; + end + + // Drive address and data onto wishbone. + WB_WRITE: begin + do_write = 1'b1; + if (~full) + wb_next_state = WB_IDLE; + else + wb_next_state = WB_WRITE; + end + + endcase // case(wb_state) end // always @ * - assign start_o = start_q; - assign mode_o = mode_q; - assign done_o = start_q ? done_q : 1'b1; - wire [AWIDTH-1:0] ram_addr = addr_q; - wire [7:0] ram_data = ser_dat_q; - assign ram_loader_done_o = (fsm_q == FSM2_FINISHED); - - // wishbone master, only writes - reg [7:0] dat_holder; - assign wb_dat_o = {4{dat_holder}}; - assign wb_stb_o = wb_we_o; - assign wb_cyc_o = wb_we_o; + wire [1:0] count_out; + wire [7:0] data_out; + + fifo_xlnx_16x40_2clk crossclk + (.rst(ram_loader_rst), + .wr_clk(dsp_clk), .din({count[4:3],count[AWIDTH+2:3],data_reg}), .wr_en(do_write), .full(full), + .rd_clk(wb_clk), .dout({count_out,wb_adr,data_out}), .rd_en(~empty), .empty(empty)); + + assign wb_dat = {4{data_out}}; + + always @* + case(count_out[1:0]) //synthesis parallel_case full_case + 2'b00 : wb_sel = 4'b1000; + 2'b01 : wb_sel = 4'b0100; + 2'b10 : wb_sel = 4'b0010; + 2'b11 : wb_sel = 4'b0001; + endcase + + assign wb_we = ~empty; + assign wb_stb = ~empty; - always @(posedge clk_i or posedge rst_i) - if(rst_i) - begin - dat_holder <= 8'd0; - wb_adr_o <= 0; - wb_sel_o <= 4'b0000; - wb_we_o <= 1'b0; - end - else if(ram_we_q) - begin - dat_holder <= ram_data; - wb_adr_o <= ram_addr; - wb_we_o <= 1'b1; - case(ram_addr[1:0]) // Big Endian - 2'b00 : wb_sel_o <= 4'b1000; - 2'b01 : wb_sel_o <= 4'b0100; - 2'b10 : wb_sel_o <= 4'b0010; - 2'b11 : wb_sel_o <= 4'b0001; - endcase // case(ram_addr[1:0]) - end // if (ram_we_q) - else if(wb_ack_i) - wb_we_o <= 1'b0; - endmodule // ram_loader diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 600bd7f3f..a90e2ced6 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -263,23 +263,22 @@ module u2_core wire [15:0] ram_loader_adr; wire [14:0] if_adr; wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire ram_loader_stb, ram_loader_we; wire iwb_ack, iwb_stb; ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), + .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), + .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), + .wb_we(ram_loader_we), + .ram_loader_done(ram_loader_done), // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - + .cpld_clk(cpld_clk), + .cpld_din(cpld_din), + .cpld_start(cpld_start_int), + .cpld_mode(cpld_mode_int), + .cpld_done(cpld_done_int), + .cpld_detached(cpld_detached)); + // ///////////////////////////////////////////////////////////////////////// // Processor aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) @@ -305,7 +304,7 @@ module u2_core .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), .if_adr(if_adr), -- cgit v1.2.3 From 1c8fc02f8787b8f809335d18a6691c2d7510be9a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 26 May 2010 18:45:46 -0700 Subject: change the debug pins, which makes it more reliable. This is unnerving. --- usrp2/top/u2_core/u2_core.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 600bd7f3f..fc2e10d52 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -683,7 +683,8 @@ module u2_core { wr2_flags, rd2_flags }, { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - assign debug_gpio_0 = debug_mac; //eth_mac_debug; + assign debug_gpio_0 = 0; + //debug_mac; //eth_mac_debug; assign debug_gpio_1 = 0; endmodule // u2_core -- cgit v1.2.3 From 2d45c8537171f8a82baf13674fbe9ccefa2cc0c0 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 10:18:13 -0700 Subject: zero out debug pins. helps timing a little bit. --- usrp2/top/u2_core/u2_core_udp.v | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/usrp2/top/u2_core/u2_core_udp.v b/usrp2/top/u2_core/u2_core_udp.v index 1fe3aafd8..d2e842b1c 100644 --- a/usrp2/top/u2_core/u2_core_udp.v +++ b/usrp2/top/u2_core/u2_core_udp.v @@ -729,7 +729,15 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins + + assign debug_clk[1:0] = 2'b00; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; +endmodule // u2_core + + /* // FIFO Level Debugging reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; @@ -756,15 +764,12 @@ module u2_core assign debug_clk[0] = GMII_RX_CLK; // wb_clk; assign debug_clk[1] = dsp_clk; -/* - wire mdio_cpy = MDIO; assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, { s6_adr[15:8] }, { s6_adr[7:0] }, { 6'd0, mdio_cpy, MDC } }; -*/ -/* + assign debug = { { GMII_TXD }, { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, { wr2_flags, rd2_flags }, @@ -773,9 +778,8 @@ module u2_core { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, { wr2_flags, rd2_flags }, { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - */ -// assign debug = debug_udp; + assign debug = debug_udp; assign debug = vrc_debug; assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, @@ -784,14 +788,12 @@ module u2_core assign debug_gpio_1 = {vita_time[63:32] }; -/* - assign debug_gpio_1 = { { tx_f19_data[15:8] }, + assign debug_gpio_1 = { { tx_f19_data[15:8] }, { tx_f19_data[7:0] }, { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; */ -endmodule // u2_core // wire debug_mux; // setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -- cgit v1.2.3 From e5bc7a493252753ad9ddf6799e986fa19841221a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 15:50:06 -0700 Subject: vita49 tx and rx added in, all sample rates now at main system clock rate. --- usrp2/top/u1e/Makefile | 5 ++ usrp2/top/u1e/u1e.ucf | 50 ++++++------ usrp2/top/u1e/u1e.v | 68 ++++++++++++++-- usrp2/top/u1e/u1e_core.v | 204 ++++++++++++++++++++++++++++++----------------- 4 files changed, 220 insertions(+), 107 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 0277ef4f2..7f5085275 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -189,6 +189,11 @@ gpmc/gpmc_to_fifo_async.v \ gpmc/fifo_to_gpmc_async.v \ gpmc/fifo_watcher.v \ gpmc/gpmc_wb.v \ +vrt/vita_rx_control.v \ +vrt/vita_rx_framer.v \ +vrt/vita_tx_control.v \ +vrt/vita_tx_deframer.v \ +timing/time_compare.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/timing.ucf \ diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 2caa46639..659a9dce5 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -163,33 +163,33 @@ NET "dip_sw<2>" LOC = "J4" ; NET "dip_sw<1>" LOC = "J6" ; NET "dip_sw<0>" LOC = "J7" ; -#NET "RXSYNC" LOC = "F22" ; #NET "reset_codec" LOC = "D22" ; -#NET "DB<11>" LOC = "E22" ; -#NET "DB<10>" LOC = "J19" ; -#NET "DB<9>" LOC = "H20" ; -#NET "DB<8>" LOC = "G19" ; -#NET "DB<7>" LOC = "F20" ; -#NET "DB<6>" LOC = "K16" ; -#NET "DB<5>" LOC = "J17" ; -#NET "DB<4>" LOC = "H22" ; -#NET "DB<3>" LOC = "G22" ; -#NET "DB<2>" LOC = "H17" ; -#NET "DB<1>" LOC = "H18" ; -#NET "DB<0>" LOC = "K20" ; -#NET "DA<11>" LOC = "J20" ; -#NET "DA<10>" LOC = "K19" ; -#NET "DA<9>" LOC = "K18" ; -#NET "DA<8>" LOC = "L22" ; -#NET "DA<7>" LOC = "K22" ; -#NET "DA<6>" LOC = "N22" ; -#NET "DA<5>" LOC = "M22" ; -#NET "DA<4>" LOC = "N20" ; -#NET "DA<3>" LOC = "N19" ; -#NET "DA<2>" LOC = "R22" ; -#NET "DA<1>" LOC = "P22" ; -#NET "DA<0>" LOC = "N17" ; +NET "RXSYNC" LOC = "F22" ; +NET "DB<11>" LOC = "E22" ; +NET "DB<10>" LOC = "J19" ; +NET "DB<9>" LOC = "H20" ; +NET "DB<8>" LOC = "G19" ; +NET "DB<7>" LOC = "F20" ; +NET "DB<6>" LOC = "K16" ; +NET "DB<5>" LOC = "J17" ; +NET "DB<4>" LOC = "H22" ; +NET "DB<3>" LOC = "G22" ; +NET "DB<2>" LOC = "H17" ; +NET "DB<1>" LOC = "H18" ; +NET "DB<0>" LOC = "K20" ; +NET "DA<11>" LOC = "J20" ; +NET "DA<10>" LOC = "K19" ; +NET "DA<9>" LOC = "K18" ; +NET "DA<8>" LOC = "L22" ; +NET "DA<7>" LOC = "K22" ; +NET "DA<6>" LOC = "N22" ; +NET "DA<5>" LOC = "M22" ; +NET "DA<4>" LOC = "N20" ; +NET "DA<3>" LOC = "N19" ; +NET "DA<2>" LOC = "R22" ; +NET "DA<1>" LOC = "P22" ; +NET "DA<0>" LOC = "N17" ; NET "TX<13>" LOC = "P19" ; NET "TX<12>" LOC = "R18" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 35818e8c8..3018ff100 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -26,18 +26,46 @@ module u1e inout [15:0] io_tx, inout [15:0] io_rx, - output [13:0] TX, output TXSYNC, output TXBLANK, - + output reg [13:0] TX, output reg TXSYNC, output TXBLANK, + input [11:0] DA, input [11:0] DB, input RXSYNC, + input PPS_IN ); - // FPGA-specific pins connections - wire clk_fpga; + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in, clk_2x, dcm_rst, dcm_locked; IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + DCM #(.CLK_FEEDBACK ( "1X" ), + .CLKDV_DIVIDE ( 2.0 ), + .CLKFX_DIVIDE ( 1 ), + .CLKFX_MULTIPLY ( 2 ), + .CLKIN_DIVIDE_BY_2 ( "FALSE" ), + .CLKIN_PERIOD ( 15.625 ), + .CLKOUT_PHASE_SHIFT ( "NONE" ), + .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), + .DFS_FREQUENCY_MODE ( "LOW" ), + .DLL_FREQUENCY_MODE ( "LOW" ), + .DUTY_CYCLE_CORRECTION ( "TRUE" ), + .FACTORY_JF ( 16'h8080 ), + .PHASE_SHIFT ( 0 ), + .STARTUP_WAIT ( "FALSE" )) + clk_doubler (.CLKFB(clk_fpga), .CLKIN(clk_fpga_in), .RST(dcm_rst), + .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), + .CLKDV(), .CLKFX(), .CLKFX180(), + .CLK2X(clk_2x), .CLK2X180(), + .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), + .LOCKED(dcm_locked), .STATUS()); + + //BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + //BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + - // SPI pins + // ///////////////////////////////////////////////////////////////////////// + // SPI wire mosi, sclk, miso; assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; @@ -45,7 +73,27 @@ module u1e assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + always @(posedge clk_2x) + if(clk_fpga) + begin + TX <= tx_i; + TXSYNC <= 0; // Low indicates first data item + end + else + begin + TX <= tx_q; + TXSYNC <= 1; + end + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), @@ -59,10 +107,16 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), - .tx(TX), .txsync(TXSYNC), .txblank(TXBLANK), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(DA), .rx_q(DB), .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Local Debug + // assign debug_clk = {clk_fpga, clk_2x }; + // assign debug = { TXSYNC, TXBLANK, TX }; endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ee193ffb9..002b28f7a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,7 +1,8 @@ //`define LOOPBACK 1 -`define TIMED 1 +//`define TIMED 1 +`define DSP 1 module u1e_core (input clk_fpga, input rst_fpga, @@ -18,14 +19,31 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx, - output reg [13:0] tx, output reg txsync, output txblank, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, input [11:0] misc_gpio, input pps_in ); - + + localparam TXFIFOSIZE = 11; + localparam RXFIFOSIZE = 11; + localparam SR_TIME64 = 0; + localparam SR_RX_DSP = 0; + localparam SR_RX_CTRL = 0; + localparam SR_TX_DSP = 0; + localparam SR_TX_CTRL = 0; + wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; + wire pps_int; + wire [63:0] vita_time; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + // ///////////////////////////////////////////////////////////////////////////////////// // GPMC Slave to Wishbone Master localparam dw = 16; @@ -47,33 +65,36 @@ module u1e_core wire bus_error; - gpmc_async gpmc (.arst(wb_rst), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - .bus_error(bus_error), .bus_reset(0), - - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), - .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), - - .fifo_clk(wb_clk), .fifo_rst(wb_rst), - .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), - .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - - .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), - .debug(debug_gpmc)); + gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(bus_error), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .debug(debug_gpmc)); + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; + wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; + `ifdef LOOPBACK fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; `endif // LOOPBACK `ifdef TIMED @@ -93,9 +114,7 @@ module u1e_core .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); // RX side - wire rx_enable, rx_src_rdy_int, rx_dst_rdy_int; - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; + wire rx_enable; packet_generator32 pktgen32 (.clk(wb_clk), .reset(wb_rst), .clear(clear), @@ -108,7 +127,90 @@ module u1e_core .underrun(), .overrun(rx_overrun)); `endif // `ifdef TIMED + +`ifdef DSP + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), + .debug_rx(vrc_debug)); + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), + .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vrf_debug) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [99:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire [15:0] tx_i_int, tx_q_int; + wire [31:0] debug_vtc, debug_vtd, debug_vt; + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .debug(debug_tx_dsp) ); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + +`else // !`ifdef DSP + // Dummy DSP signal generator for test purposes + wire [23:0] tx_i_int, tx_q_int; + wire [23:0] freq = {reg_test,8'd0}; + reg [23:0] phase; + + always @(posedge wb_clk) + phase <= phase + freq; + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); + + assign tx_i = tx_i_int[23:10]; + assign tx_q = tx_q_int[23:10]; +`endif // !`ifdef DSP + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -181,8 +283,6 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, Misc LEDs, Switches, controls - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; - localparam REG_LEDS = 7'd0; // out localparam REG_SWITCHES = 7'd2; // in localparam REG_CGEN_CTRL = 7'd4; // out @@ -288,10 +388,6 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - // only have 32 regs, 32 bits each with current setup... settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), @@ -311,51 +407,9 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // VITA Timing - localparam SR_TIME64 = 0; - wire pps_int; - wire [63:0] vita_time; - time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); - - - // ///////////////////////////////////////////////////////////////////////// - // TX - - assign txblank = 0; - - wire [23:0] freq = {reg_test,8'd0}; - - reg [23:0] tx_q_hold; - wire [23:0] tx_i, tx_q; - - reg tx_stb; - always @(posedge wb_clk) - tx_stb <= ~tx_stb; - - always @(posedge wb_clk) - if(tx_stb) - tx <= tx_i[23:10]; - else - tx <= tx_q_hold[23:10]; - - always @(posedge wb_clk) - if(tx_stb) - tx_q_hold <= tx_q; - - always @(posedge wb_clk) - txsync <= ~tx_stb; // TX Sync low indicates first data item - // We invert here if we don't use inv_txsync in the 9862 - - reg [23:0] phase; - always @(posedge wb_clk) - if(tx_stb) - phase <= phase + freq; - - cordic_z24 #(.bitwidth(24)) tx_cordic - (.clock(wb_clk), .reset(wb_rst), .enable(1), - .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From 552c3477734c6c302c53fe039d6e85134fcf210c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 16:20:24 -0700 Subject: assign addresses for the settings regs --- usrp2/top/u1e/u1e_core.v | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 002b28f7a..ed4176ca5 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -27,11 +27,12 @@ module u1e_core localparam TXFIFOSIZE = 11; localparam RXFIFOSIZE = 11; - localparam SR_TIME64 = 0; - localparam SR_RX_DSP = 0; - localparam SR_RX_CTRL = 0; - localparam SR_TX_DSP = 0; - localparam SR_TX_CTRL = 0; + + localparam SR_RX_DSP = 0; // 7 regs + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_TIME64 = 28; // 4 regs wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; -- cgit v1.2.3 From 7a776f9fce357b298566d0a417a1417c4484723c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 18:23:09 -0700 Subject: use DDR regs instead of a 2nd clock --- usrp2/top/u1e/u1e.v | 54 +++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 8 deletions(-) diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 3018ff100..523aae1b9 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -1,6 +1,8 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// +//`define DCM 1 + module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -26,7 +28,7 @@ module u1e inout [15:0] io_tx, inout [15:0] io_rx, - output reg [13:0] TX, output reg TXSYNC, output TXBLANK, + output [13:0] TX, output TXSYNC, output TXBLANK, input [11:0] DA, input [11:0] DB, input RXSYNC, input PPS_IN @@ -34,11 +36,13 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Clocking - wire clk_fpga, clk_fpga_in, clk_2x, dcm_rst, dcm_locked; + wire clk_fpga, clk_fpga_in; IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); +`ifdef DCM + wire clk_2x, dcm_rst, dcm_locked; DCM #(.CLK_FEEDBACK ( "1X" ), .CLKDV_DIVIDE ( 2.0 ), .CLKFX_DIVIDE ( 1 ), @@ -59,11 +63,10 @@ module u1e .CLK2X(clk_2x), .CLK2X180(), .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); - - //BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - //BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - +`else // !`ifdef DCM + BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); +`endif // !`ifdef DCM + // ///////////////////////////////////////////////////////////////////////// // SPI wire mosi, sclk, miso; @@ -79,6 +82,10 @@ module u1e assign TXBLANK = 0; wire [13:0] tx_i, tx_q; + +`ifdef DCM + reg [13:0] TX; + reg TXSYNC; always @(posedge clk_2x) if(clk_fpga) @@ -91,7 +98,38 @@ module u1e TX <= tx_q; TXSYNC <= 1; end - +`else // !`ifdef DCM + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(tx_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + +`endif // !`ifdef DCM + // ///////////////////////////////////////////////////////////////////////// // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), -- cgit v1.2.3 From b96282d6d9d7aad94d82f2ac6487460f4850a55c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 18:23:35 -0700 Subject: connect the rx run lines so it doesn't get optimized out --- usrp2/top/u1e/u1e_core.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ed4176ca5..7307a0299 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -138,12 +138,14 @@ module u1e_core wire strobe_rx, strobe_tx; wire rx1_dst_rdy, rx1_src_rdy; wire [99:0] rx1_data; + wire run_rx; + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .debug(debug_rx_dsp) ); vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control @@ -169,6 +171,7 @@ module u1e_core wire tx1_src_rdy, tx1_dst_rdy; wire [15:0] tx_i_int, tx_q_int; wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire run_tx; vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer (.clk(wb_clk), .reset(wb_rst), .clear(0), -- cgit v1.2.3 From d2163a256d55692c19b0a717e382850a6546f80f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 18:56:44 -0700 Subject: use same version as usrp2-udp, so regs are same place in memory map --- usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e_core.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 7f5085275..edfc47c53 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -160,7 +160,7 @@ sdr_lib/clip_reg.v \ sdr_lib/cordic.v \ sdr_lib/cordic_z24.v \ sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_rx_udp.v \ sdr_lib/dsp_core_tx.v \ sdr_lib/hb_dec.v \ sdr_lib/hb_interp.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7307a0299..12ce41c23 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -28,7 +28,7 @@ module u1e_core localparam TXFIFOSIZE = 11; localparam RXFIFOSIZE = 11; - localparam SR_RX_DSP = 0; // 7 regs + localparam SR_RX_DSP = 0; // 5 regs localparam SR_RX_CTRL = 8; // 9 regs localparam SR_TX_DSP = 17; // 5 regs localparam SR_TX_CTRL = 24; // 2 regs -- cgit v1.2.3 From 4f1b2441c0250a61f691c038f8bd9cfb229bd103 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 3 Jun 2010 08:44:13 -0700 Subject: Phil wants gpio #145 --- usrp2/top/u1e_passthru/passthru.ucf | 4 ++-- usrp2/top/u1e_passthru/passthru.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf index 3ffe33882..fcfce61b2 100644 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -54,10 +54,10 @@ #NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug #NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug #NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -NET "overo_gpio127" LOC = "C8" ; # passed through as cgen_sen_b +#NET "overo_gpio127" LOC = "C8" ; # passed through as cgen_sen_b #NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug #NET "overo_gpio144" LOC = "A5" ; # tx_have_space -#NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio145" LOC = "C7" ; # tx_underrun #NET "overo_gpio146" LOC = "A6" ; # rx_have_data #NET "overo_gpio147" LOC = "B6" ; # rx_overrun #NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v index d846f2cf6..12e4db017 100644 --- a/usrp2/top/u1e_passthru/passthru.v +++ b/usrp2/top/u1e_passthru/passthru.v @@ -2,7 +2,7 @@ ////////////////////////////////////////////////////////////////////////////////// module passthru - (input overo_gpio127, + (input overo_gpio145, output cgen_sclk, output cgen_sen_b, output cgen_mosi, @@ -11,7 +11,7 @@ module passthru ); assign cgen_sclk = fpga_cfg_cclk; - assign cgen_sen_b = overo_gpio127; + assign cgen_sen_b = overo_gpio145; assign cgen_mosi = fpga_cfg_din; -- cgit v1.2.3 From 761e22013c6715987c411216d012098e60684836 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 02:26:48 -0700 Subject: get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bit --- usrp2/control_lib/newfifo/fifo36_to_fifo18.v | 40 ---------------------------- usrp2/gpmc/gpmc_async.v | 5 ++-- usrp2/gpmc/gpmc_sync.v | 5 ++-- 3 files changed, 6 insertions(+), 44 deletions(-) delete mode 100644 usrp2/control_lib/newfifo/fifo36_to_fifo18.v diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo18.v b/usrp2/control_lib/newfifo/fifo36_to_fifo18.v deleted file mode 100644 index b636ab9ca..000000000 --- a/usrp2/control_lib/newfifo/fifo36_to_fifo18.v +++ /dev/null @@ -1,40 +0,0 @@ - -module fifo36_to_fifo18 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [17:0] f18_dataout, - output f18_src_rdy_o, - input f18_dst_rdy_i ); - - wire f36_sof = f36_datain[32]; - wire f36_eof = f36_datain[33]; - wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - - assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; - assign f18_dataout[16] = phase ? 0 : f36_sof; - assign f18_dataout[17] = phase ? f36_eof : half_line; - - assign f18_src_rdy_o = f36_src_rdy_i; - assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i; - - wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - - always @(posedge clk) - if(reset) - phase <= 0; - else if(f36_xfer) - phase <= 0; - else if(f18_xfer) - phase <= 1; - - -endmodule // fifo36_to_fifo18 - diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 380689c62..f42b835ed 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -82,16 +82,17 @@ module gpmc_async wire [15:0] rx_fifo_space; wire [35:0] rx36_data; wire rx36_src_rdy, rx36_dst_rdy; + wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo18 f18_to_f36 + fifo36_to_fifo19 f36_to_f19 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo (.clk(fifo_clk), .reset(fifo_rst), .clear(0), diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v index 825d131d8..bac489ca0 100644 --- a/usrp2/gpmc/gpmc_sync.v +++ b/usrp2/gpmc/gpmc_sync.v @@ -68,11 +68,12 @@ module gpmc_sync wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; wire [15:0] rx_fifo_space, rx_frame_len; + wire dummy; - fifo36_to_fifo18 f18_to_f36 + fifo36_to_fifo19 f36_to_f19 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), - .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo (.wclk(fifo_clk), .datain(rx18_data), -- cgit v1.2.3 From 3122c8c3d9740a2fd5e68b99df627bc632d764da Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 02:50:18 -0700 Subject: added little endian capability for gpmc to fifo and fifo to gpmc, since ARM is LE. --- usrp2/control_lib/newfifo/fifo19_to_fifo36.v | 40 ++++++++++++++----------- usrp2/control_lib/newfifo/fifo36_to_fifo19.v | 44 +++++++++++++++------------- usrp2/gpmc/gpmc_async.v | 4 +-- usrp2/gpmc/gpmc_sync.v | 4 +-- 4 files changed, 51 insertions(+), 41 deletions(-) diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v index 5f9aeff9b..0e6bcea68 100644 --- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v +++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v @@ -1,26 +1,31 @@ +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. + module fifo19_to_fifo36 - (input clk, input reset, input clear, - input [18:0] f19_datain, - input f19_src_rdy_i, - output f19_dst_rdy_o, + #(parameter LE=0) + (input clk, input reset, input clear, + input [18:0] f19_datain, + input f19_src_rdy_i, + output f19_dst_rdy_o, - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i, - output [31:0] debug - ); + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i, + output [31:0] debug + ); - reg f36_sof, f36_eof, f36_occ; + reg f36_sof, f36_eof, f36_occ; - reg [1:0] state; - reg [15:0] dat0, dat1; + reg [1:0] state; + reg [15:0] dat0, dat1; - wire f19_sof = f19_datain[16]; - wire f19_eof = f19_datain[17]; - wire f19_occ = f19_datain[18]; + wire f19_sof = f19_datain[16]; + wire f19_eof = f19_datain[17]; + wire f19_occ = f19_datain[18]; - wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; + wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; always @(posedge clk) if(f19_src_rdy_i & ((state==0)|xfer_out)) @@ -68,7 +73,8 @@ module fifo19_to_fifo36 dat0 <= f19_datain; assign f19_dst_rdy_o = xfer_out | (state != 2); - assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; + assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} : + {f36_occ,f36_eof,f36_sof,dat0,dat1}; assign f36_src_rdy_o = (state == 2); assign debug = state; diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v index de249aaeb..517a2a476 100644 --- a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v +++ b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v @@ -1,33 +1,38 @@ -module fifo36_to_fifo19 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [18:0] f19_dataout, - output f19_src_rdy_o, - input f19_dst_rdy_i ); +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. +module fifo36_to_fifo19 + #(parameter LE=0) + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [18:0] f19_dataout, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + wire f36_sof = f36_datain[32]; wire f36_eof = f36_datain[33]; wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16]; assign f19_dataout[16] = phase ? 0 : f36_sof; assign f19_dataout[17] = phase ? f36_eof : half_line; assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); assign f19_src_rdy_o = f36_src_rdy_i; assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; - - wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - + + wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + always @(posedge clk) if(reset) phase <= 0; @@ -36,6 +41,5 @@ module fifo36_to_fifo19 else if(f19_xfer) phase <= 1; - + endmodule // fifo36_to_fifo19 - diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index f42b835ed..1050cef7d 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -64,7 +64,7 @@ module gpmc_async .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); - fifo19_to_fifo36 f19_to_f36 + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); @@ -89,7 +89,7 @@ module gpmc_async .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo19 f36_to_f19 + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v index bac489ca0..61c54a793 100644 --- a/usrp2/gpmc/gpmc_sync.v +++ b/usrp2/gpmc/gpmc_sync.v @@ -57,7 +57,7 @@ module gpmc_sync .rclk(fifo_clk), .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); - fifo19_to_fifo36 f19_to_f36 + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); @@ -70,7 +70,7 @@ module gpmc_sync wire [15:0] rx_fifo_space, rx_frame_len; wire dummy; - fifo36_to_fifo19 f36_to_f19 + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); -- cgit v1.2.3 From 2f92808d27efae16368d6dddfbcc74ca181f4d7c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 03:18:39 -0700 Subject: use fifo19 not fifo18 in makefile --- usrp2/top/u1e/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index edfc47c53..cfef1378f 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -109,7 +109,7 @@ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/newfifo/fifo36_to_fifo18.v \ +control_lib/newfifo/fifo36_to_fifo19.v \ control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/newfifo/packet_generator.v \ control_lib/newfifo/packet_verifier.v \ -- cgit v1.2.3 From 552b06b5b281e0953b0268a22357c5f43bd9657c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 09:53:42 -0700 Subject: remove double declaration --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 12ce41c23..6dae653ce 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -101,7 +101,7 @@ module u1e_core `ifdef TIMED // TX side - wire tx_enable, tx_src_rdy_int, tx_dst_rdy_int; + wire tx_enable; fifo_pacer tx_pacer (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), -- cgit v1.2.3 From de1d009c69c6233340bb4b5e58427c87a1a7c5e8 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 22:12:06 -0700 Subject: skeleton files copied over from a dead branch --- usrp2/top/safe_u2plus/.gitignore | 2 + usrp2/top/safe_u2plus/Makefile | 246 +++++++++++++++++ usrp2/top/safe_u2plus/safe_u2plus.v | 362 ++++++++++++++++++++++++ usrp2/top/safe_u2plus/u2plus.ucf | 401 +++++++++++++++++++++++++++ usrp2/top/u2plus/.gitignore | 1 + usrp2/top/u2plus/Makefile | 246 +++++++++++++++++ usrp2/top/u2plus/capture_ddrlvds.v | 39 +++ usrp2/top/u2plus/u2plus.ucf | 531 ++++++++++++++++++++---------------- usrp2/top/u2plus/u2plus.v | 274 ++++++++++--------- 9 files changed, 1728 insertions(+), 374 deletions(-) create mode 100644 usrp2/top/safe_u2plus/.gitignore create mode 100644 usrp2/top/safe_u2plus/Makefile create mode 100644 usrp2/top/safe_u2plus/safe_u2plus.v create mode 100755 usrp2/top/safe_u2plus/u2plus.ucf create mode 100644 usrp2/top/u2plus/.gitignore create mode 100644 usrp2/top/u2plus/Makefile create mode 100644 usrp2/top/u2plus/capture_ddrlvds.v diff --git a/usrp2/top/safe_u2plus/.gitignore b/usrp2/top/safe_u2plus/.gitignore new file mode 100644 index 000000000..a96f0be92 --- /dev/null +++ b/usrp2/top/safe_u2plus/.gitignore @@ -0,0 +1,2 @@ +build* +*impact* diff --git a/usrp2/top/safe_u2plus/Makefile b/usrp2/top/safe_u2plus/Makefile new file mode 100644 index 000000000..62a02ff40 --- /dev/null +++ b/usrp2/top/safe_u2plus/Makefile @@ -0,0 +1,246 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := safe_u2plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2plus/capture_ddrlvds.v \ +top/safe_u2plus/u2plus.ucf \ +top/safe_u2plus/safe_u2plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/safe_u2plus/safe_u2plus.v b/usrp2/top/safe_u2plus/safe_u2plus.v new file mode 100644 index 000000000..38b276000 --- /dev/null +++ b/usrp2/top/safe_u2plus/safe_u2plus.v @@ -0,0 +1,362 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module safe_u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + //input ADC_clkout_p, //input ADC_clkout_n, + //input ADCA_12_p, //input ADCA_12_n, + //input ADCA_10_p, //input ADCA_10_n, + //input ADCA_8_p, //input ADCA_8_n, + //input ADCA_6_p, //input ADCA_6_n, + //input ADCA_4_p, //input ADCA_4_n, + //input ADCA_2_p, //input ADCA_2_n, + //input ADCA_0_p, //input ADCA_0_n, + //input ADCB_12_p, //input ADCB_12_n, + //input ADCB_10_p, //input ADCB_10_n, + //input ADCB_8_p, //input ADCB_8_n, + //input ADCB_6_p, //input ADCB_6_n, + //input ADCB_4_p, //input ADCB_4_n, + //input ADCB_2_p, //input ADCB_2_n, + //input ADCB_0_p, //input ADCB_0_n, + + // DAC + //output [15:0] DACA, + //output [15:0] DACB, + //input DAC_LOCK, // unused for now + + // DB IO Pins + //inout [15:0] io_tx, + //inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + //input FPGA_RESET, + //output [1:0] debug_clk, + //output [31:0] debug, + //output [3:1] TXD, //input [3:1] RXD, // UARTs + ////input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + //output [1:0] clk_en, + //output [1:0] clk_sel, + //input CLK_FUNC, // FIXME is an //input to control the 9510 + //input CLK_STATUS, + + //inout SCL, //inout SDA, // I2C + + // PPS + //input PPS_IN, //input PPS2_IN, + + // SPI + //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, + //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, + //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, + //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, + //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, + //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, + //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, + //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, + //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, + + // GigE PHY + //input CLK_TO_MAC, + + //output reg [7:0] GMII_TXD, + //output reg GMII_TX_EN, + //output reg GMII_TX_ER, + //output GMII_GTX_CLK, + //input GMII_TX_CLK, // 100mbps clk + + //input GMII_RX_CLK, + //input [7:0] GMII_RXD, + //input GMII_RX_DV, + //input GMII_RX_ER, + //input GMII_COL, + //input GMII_CRS, + + //input PHY_INTn, // open drain + //inout MDIO, + //output MDC, + //output PHY_RESETn, + output ETH_LED + + //input POR, + + // Expansion + //input exp_time_in_p, //input exp_time_in_n, // Diff + //output exp_time_out_p, //output exp_time_out_n, // Diff + //input exp_user_in_p, //input exp_user_in_n, // Diff + //output exp_user_out_p, //output exp_user_out_n, // Diff + + // SERDES + //output ser_enable, + //output ser_prbsen, + //output ser_loopen, + //output ser_rx_en, + + //output ser_tx_clk, + //output reg [15:0] ser_t, + //output reg ser_tklsb, + //output reg ser_tkmsb, + + //input ser_rx_clk, + //input [15:0] ser_r, + //input ser_rklsb, + //input ser_rkmsb, + + // SRAM + //inout [35:0] RAM_D, + //output [20:0] RAM_A, + //output [3:0] RAM_BWn, + //output RAM_ZZ, + //output RAM_LDn, + //output RAM_OEn, + //output RAM_WEn, + //output RAM_CENn, + //output RAM_CLK, + + // SPI Flash + //output flash_cs, + //output flash_clk, + //output flash_mosi, + //input flash_miso + ); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + reg [31:0] ctr; + + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign {leds,ETH_LED} = ~ctr[29:24]; + + +/* + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire dcm_rst = 0; + + wire [13:0] adc_a, adc_b; + + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a,adc_b})); + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = ~leds_int; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + u2_core u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_time_in), + .exp_pps_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (DACA[15:0]), + .dac_b (DACB[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); +*/ +endmodule // safe_u2plus diff --git a/usrp2/top/safe_u2plus/u2plus.ucf b/usrp2/top/safe_u2plus/u2plus.ucf new file mode 100755 index 000000000..0a9460d86 --- /dev/null +++ b/usrp2/top/safe_u2plus/u2plus.ucf @@ -0,0 +1,401 @@ +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC +#NET "ADC_clkout_p" LOC = "P1" ; +#NET "ADC_clkout_n" LOC = "P2" ; +#NET "ADCA_12_p" LOC = "Y1" ; +#NET "ADCA_12_n" LOC = "Y2" ; +#NET "ADCA_10_p" LOC = "W3" ; +#NET "ADCA_10_n" LOC = "W4" ; +#NET "ADCA_8_p" LOC = "T7" ; +#NET "ADCA_8_n" LOC = "U6" ; +#NET "ADCA_6_p" LOC = "U5" ; +#NET "ADCA_6_n" LOC = "V5" ; +#NET "ADCA_4_p" LOC = "T10" ; +#NET "ADCA_4_n" LOC = "T9" ; +#NET "ADCA_2_p" LOC = "V1" ; +#NET "ADCA_2_n" LOC = "V2" ; +#NET "ADCA_0_p" LOC = "R8" ; +#NET "ADCA_0_n" LOC = "R7" ; +#NET "ADCB_2_p" LOC = "U7" ; +#NET "ADCB_2_n" LOC = "U8" ; +#NET "ADCB_0_p" LOC = "AA2" ; +#NET "ADCB_0_n" LOC = "AA3" ; +#NET "ADCB_4_p" LOC = "AE1" ; +#NET "ADCB_4_n" LOC = "AE2" ; +#NET "ADCB_6_p" LOC = "W1" ; +#NET "ADCB_6_n" LOC = "W2" ; +#NET "ADCB_8_p" LOC = "U3" ; +#NET "ADCB_8_n" LOC = "V4" ; +#NET "ADCB_10_p" LOC = "J1" ; +#NET "ADCB_10_n" LOC = "K1" ; +#NET "ADCB_12_p" LOC = "J3" ; +#NET "ADCB_12_n" LOC = "J2" ; + +## DAC +#NET "DAC_LOCK" LOC = "P4" ; +#NET "DACA<0>" LOC = "P8" ; +#NET "DACA<1>" LOC = "P9" ; +#NET "DACA<2>" LOC = "R5" ; +#NET "DACA<3>" LOC = "R6" ; +#NET "DACA<4>" LOC = "P7" ; +#NET "DACA<5>" LOC = "P6" ; +#NET "DACA<6>" LOC = "T3" ; +#NET "DACA<7>" LOC = "T4" ; +#NET "DACA<8>" LOC = "R3" ; +#NET "DACA<9>" LOC = "R4" ; +#NET "DACA<10>" LOC = "R2" ; +#NET "DACA<11>" LOC = "N1" ; +#NET "DACA<12>" LOC = "N2" ; +#NET "DACA<13>" LOC = "N5" ; +#NET "DACA<14>" LOC = "N4" ; +#NET "DACA<15>" LOC = "M2" ; +#NET "DACB<0>" LOC = "M5" ; +#NET "DACB<1>" LOC = "M6" ; +#NET "DACB<2>" LOC = "M4" ; +#NET "DACB<3>" LOC = "M3" ; +#NET "DACB<4>" LOC = "M8" ; +#NET "DACB<5>" LOC = "M7" ; +#NET "DACB<6>" LOC = "L4" ; +#NET "DACB<7>" LOC = "L3" ; +#NET "DACB<8>" LOC = "K3" ; +#NET "DACB<9>" LOC = "K2" ; +#NET "DACB<10>" LOC = "K5" ; +#NET "DACB<11>" LOC = "K4" ; +#NET "DACB<12>" LOC = "M10" ; +#NET "DACB<13>" LOC = "M9" ; +#NET "DACB<14>" LOC = "J5" ; +#NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO +#NET "io_tx<15>" LOC = "K6" ; +#NET "io_tx<14>" LOC = "L7" ; +#NET "io_tx<13>" LOC = "H2" ; +#NET "io_tx<12>" LOC = "H1" ; +#NET "io_tx<11>" LOC = "L10" ; +#NET "io_tx<10>" LOC = "L9" ; +#NET "io_tx<9>" LOC = "G3" ; +#NET "io_tx<8>" LOC = "F3" ; +#NET "io_tx<7>" LOC = "K7" ; +#NET "io_tx<6>" LOC = "J6" ; +#NET "io_tx<5>" LOC = "E1" ; +#NET "io_tx<4>" LOC = "F2" ; +#NET "io_tx<3>" LOC = "J7" ; +#NET "io_tx<2>" LOC = "H6" ; +#NET "io_tx<1>" LOC = "F5" ; +#NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +#NET "io_rx<15>" LOC = "AD1" ; +#NET "io_rx<14>" LOC = "AD2" ; +#NET "io_rx<13>" LOC = "AC2" ; +#NET "io_rx<12>" LOC = "AC3" ; +#NET "io_rx<11>" LOC = "W7" ; +#NET "io_rx<10>" LOC = "W6" ; +#NET "io_rx<9>" LOC = "U9" ; +#NET "io_rx<8>" LOC = "V8" ; +#NET "io_rx<7>" LOC = "AB1" ; +#NET "io_rx<6>" LOC = "AC1" ; +#NET "io_rx<5>" LOC = "V7" ; +#NET "io_rx<4>" LOC = "V6" ; +#NET "io_rx<3>" LOC = "Y5" ; +#NET "io_rx<2>" LOC = "R10" ; +#NET "io_rx<1>" LOC = "R1" ; +#NET "io_rx<0>" LOC = "M1" ; + +## MISC +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +#NET "FPGA_RESET" LOC = "K24" ; + +## Debug +#NET "debug_clk<0>" LOC = "AA10" ; +#NET "debug_clk<1>" LOC = "AD11" ; +#NET "debug<0>" LOC = "AC19" ; +#NET "debug<1>" LOC = "AF20" ; +#NET "debug<2>" LOC = "AE20" ; +#NET "debug<3>" LOC = "AC16" ; +#NET "debug<4>" LOC = "AB16" ; +#NET "debug<5>" LOC = "AF19" ; +#NET "debug<6>" LOC = "AE19" ; +#NET "debug<7>" LOC = "V15" ; +#NET "debug<8>" LOC = "U15" ; +#NET "debug<9>" LOC = "AE17" ; +#NET "debug<10>" LOC = "AD17" ; +#NET "debug<11>" LOC = "V14" ; +#NET "debug<12>" LOC = "W15" ; +#NET "debug<13>" LOC = "AC15" ; +#NET "debug<14>" LOC = "AD14" ; +#NET "debug<15>" LOC = "AC14" ; +#NET "debug<16>" LOC = "AC11" ; +#NET "debug<17>" LOC = "AB12" ; +#NET "debug<18>" LOC = "AC12" ; +#NET "debug<19>" LOC = "V13" ; +#NET "debug<20>" LOC = "W13" ; +#NET "debug<21>" LOC = "AE8" ; +#NET "debug<22>" LOC = "AF8" ; +#NET "debug<23>" LOC = "V12" ; +#NET "debug<24>" LOC = "W12" ; +#NET "debug<25>" LOC = "AB9" ; +#NET "debug<26>" LOC = "AC9" ; +#NET "debug<27>" LOC = "AC8" ; +#NET "debug<28>" LOC = "AB7" ; +#NET "debug<29>" LOC = "V11" ; +#NET "debug<30>" LOC = "U11" ; +#NET "debug<31>" LOC = "Y10" ; + +## UARTS +#NET "TXD<3>" LOC = "AD20" ; +#NET "TXD<2>" LOC = "AC20" ; +#NET "TXD<1>" LOC = "AD19" ; +#NET "RXD<3>" LOC = "AF17" ; +#NET "RXD<2>" LOC = "AF15" ; +#NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +#NET "CLK_STATUS" LOC = "AD22" ; +#NET "CLK_FUNC" LOC = "AC21" ; +#NET "clk_sel<0>" LOC = "AE21" ; +#NET "clk_sel<1>" LOC = "AD21" ; +#NET "clk_en<1>" LOC = "AA17" ; +#NET "clk_en<0>" LOC = "Y17" ; + +## I2C +#NET "SDA" LOC = "V16" ; +#NET "SCL" LOC = "U16" ; + +## Timing +#NET "PPS_IN" LOC = "AB6" ; +#NET "PPS2_IN" LOC = "AA20" ; + +## SPI +#NET "SEN_CLK" LOC = "AA18" ; +#NET "MOSI_CLK" LOC = "W17" ; +#NET "SCLK_CLK" LOC = "V17" ; +#NET "MISO_CLK" LOC = "AC10" ; + +#NET "SEN_DAC" LOC = "AE7" ; +#NET "SCLK_DAC" LOC = "AF5" ; +#NET "MOSI_DAC" LOC = "AE6" ; +#NET "MISO_DAC" LOC = "Y3" ; + +#NET "SCLK_ADC" LOC = "B1" ; +#NET "MOSI_ADC" LOC = "J8" ; +#NET "SEN_ADC" LOC = "J9" ; + +#NET "MOSI_TX_ADC" LOC = "V10" ; +#NET "SEN_TX_ADC" LOC = "W10" ; +#NET "SCLK_TX_ADC" LOC = "AC6" ; +#NET "MISO_TX_ADC" LOC = "G1" ; + +#NET "MOSI_TX_DAC" LOC = "AD6" ; +#NET "SEN_TX_DAC" LOC = "AE4" ; +#NET "SCLK_TX_DAC" LOC = "AF4" ; + +#NET "SCLK_TX_DB" LOC = "AE3" ; +#NET "MOSI_TX_DB" LOC = "AF3" ; +#NET "SEN_TX_DB" LOC = "W9" ; +#NET "MISO_TX_DB" LOC = "AA5" ; + +#NET "MOSI_RX_ADC" LOC = "E3" ; +#NET "SCLK_RX_ADC" LOC = "F4" ; +#NET "SEN_RX_ADC" LOC = "D3" ; +#NET "MISO_RX_ADC" LOC = "C1" ; + +#NET "SCLK_RX_DAC" LOC = "E4" ; +#NET "SEN_RX_DAC" LOC = "K9" ; +#NET "MOSI_RX_DAC" LOC = "K8" ; + +#NET "SCLK_RX_DB" LOC = "G6" ; +#NET "MOSI_RX_DB" LOC = "H7" ; +#NET "SEN_RX_DB" LOC = "B2" ; +#NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY +#NET "CLK_TO_MAC" LOC = "P26" ; + +#NET "GMII_TXD<7>" LOC = "G21" ; +#NET "GMII_TXD<6>" LOC = "C26" ; +#NET "GMII_TXD<5>" LOC = "C25" ; +#NET "GMII_TXD<4>" LOC = "J21" ; +#NET "GMII_TXD<3>" LOC = "H21" ; +#NET "GMII_TXD<2>" LOC = "D25" ; +#NET "GMII_TXD<1>" LOC = "D24" ; +#NET "GMII_TXD<0>" LOC = "E26" ; +#NET "GMII_TX_EN" LOC = "D26" ; +#NET "GMII_TX_ER" LOC = "J19" ; +#NET "GMII_GTX_CLK" LOC = "J20" ; +#NET "GMII_TX_CLK" LOC = "P25" ; + +#NET "GMII_RX_CLK" LOC = "P21" ; +#NET "GMII_RXD<7>" LOC = "G22" ; +#NET "GMII_RXD<6>" LOC = "K19" ; +#NET "GMII_RXD<5>" LOC = "K18" ; +#NET "GMII_RXD<4>" LOC = "E24" ; +#NET "GMII_RXD<3>" LOC = "F23" ; +#NET "GMII_RXD<2>" LOC = "L18" ; +#NET "GMII_RXD<1>" LOC = "L17" ; +#NET "GMII_RXD<0>" LOC = "F25" ; +#NET "GMII_RX_DV" LOC = "F24" ; +#NET "GMII_RX_ER" LOC = "L20" ; +#NET "GMII_CRS" LOC = "K20" ; +#NET "GMII_COL" LOC = "G23" ; + +#NET "PHY_INTn" LOC = "L22" ; +#NET "MDIO" LOC = "K21" ; +#NET "MDC" LOC = "J23" ; +#NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" ; + +## MIMO Interface +#NET "exp_time_out_p" LOC = "Y14" ; +#NET "exp_time_out_n" LOC = "AA14" ; +#NET "exp_time_in_p" LOC = "N18" ; +#NET "exp_time_in_n" LOC = "N17" ; +#NET "exp_user_out_p" LOC = "AF14" ; +#NET "exp_user_out_n" LOC = "AE14" ; +#NET "exp_user_in_p" LOC = "L24" ; +#NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +#NET "ser_enable" LOC = "R20" ; +#NET "ser_prbsen" LOC = "U23" ; +#NET "ser_loopen" LOC = "R19" ; +#NET "ser_rx_en" LOC = "Y21" ; +#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +#NET "ser_t<15>" LOC = "V23" ; +#NET "ser_t<14>" LOC = "U22" ; +#NET "ser_t<13>" LOC = "V24" ; +#NET "ser_t<12>" LOC = "V25" ; +#NET "ser_t<11>" LOC = "W23" ; +#NET "ser_t<10>" LOC = "V22" ; +#NET "ser_t<9>" LOC = "T18" ; +#NET "ser_t<8>" LOC = "T17" ; +#NET "ser_t<7>" LOC = "Y24" ; +#NET "ser_t<6>" LOC = "Y25" ; +#NET "ser_t<5>" LOC = "U21" ; +#NET "ser_t<4>" LOC = "T20" ; +#NET "ser_t<3>" LOC = "Y22" ; +#NET "ser_t<2>" LOC = "Y23" ; +#NET "ser_t<1>" LOC = "U19" ; +#NET "ser_t<0>" LOC = "U18" ; +#NET "ser_tkmsb" LOC = "AA24" ; +#NET "ser_tklsb" LOC = "AA25" ; +#NET "ser_rx_clk" LOC = "P18" ; +#NET "ser_r<15>" LOC = "V21" ; +#NET "ser_r<14>" LOC = "U20" ; +#NET "ser_r<13>" LOC = "AA22" ; +#NET "ser_r<12>" LOC = "AA23" ; +#NET "ser_r<11>" LOC = "V18" ; +#NET "ser_r<10>" LOC = "V19" ; +#NET "ser_r<9>" LOC = "AB23" ; +#NET "ser_r<8>" LOC = "AC26" ; +#NET "ser_r<7>" LOC = "AB26" ; +#NET "ser_r<6>" LOC = "AD26" ; +#NET "ser_r<5>" LOC = "AC25" ; +#NET "ser_r<4>" LOC = "W20" ; +#NET "ser_r<3>" LOC = "W21" ; +#NET "ser_r<2>" LOC = "AC23" ; +#NET "ser_r<1>" LOC = "AC24" ; +#NET "ser_r<0>" LOC = "AE26" ; +#NET "ser_rkmsb" LOC = "AD25" ; +#NET "ser_rklsb" LOC = "Y20" ; + +## SRAM +#NET "RAM_D<35>" LOC = "K16" ; +#NET "RAM_D<34>" LOC = "D20" ; +#NET "RAM_D<33>" LOC = "C20" ; +#NET "RAM_D<32>" LOC = "E21" ; +#NET "RAM_D<31>" LOC = "D21" ; +#NET "RAM_D<30>" LOC = "C21" ; +#NET "RAM_D<29>" LOC = "B21" ; +#NET "RAM_D<28>" LOC = "H17" ; +#NET "RAM_D<27>" LOC = "G17" ; +#NET "RAM_D<26>" LOC = "B23" ; +#NET "RAM_D<25>" LOC = "A22" ; +#NET "RAM_D<24>" LOC = "D23" ; +#NET "RAM_D<23>" LOC = "C23" ; +#NET "RAM_D<22>" LOC = "D22" ; +#NET "RAM_D<21>" LOC = "C22" ; +#NET "RAM_D<20>" LOC = "F19" ; +#NET "RAM_D<19>" LOC = "G20" ; +#NET "RAM_D<18>" LOC = "F20" ; +#NET "RAM_D<17>" LOC = "F7" ; +#NET "RAM_D<16>" LOC = "E7" ; +#NET "RAM_D<15>" LOC = "G9" ; +#NET "RAM_D<14>" LOC = "H9" ; +#NET "RAM_D<13>" LOC = "G10" ; +#NET "RAM_D<12>" LOC = "H10" ; +#NET "RAM_D<11>" LOC = "A4" ; +#NET "RAM_D<10>" LOC = "B4" ; +#NET "RAM_D<9>" LOC = "C5" ; +#NET "RAM_D<8>" LOC = "D6" ; +#NET "RAM_D<7>" LOC = "J11" ; +#NET "RAM_D<6>" LOC = "K11" ; +#NET "RAM_D<5>" LOC = "B7" ; +#NET "RAM_D<4>" LOC = "C7" ; +#NET "RAM_D<3>" LOC = "B6" ; +#NET "RAM_D<2>" LOC = "C6" ; +#NET "RAM_D<1>" LOC = "C8" ; +#NET "RAM_D<0>" LOC = "D8" ; +#NET "RAM_A<0>" LOC = "C11" ; +#NET "RAM_A<1>" LOC = "E12" ; +#NET "RAM_A<2>" LOC = "F12" ; +#NET "RAM_A<3>" LOC = "D13" ; +#NET "RAM_A<4>" LOC = "C12" ; +#NET "RAM_A<5>" LOC = "A12" ; +#NET "RAM_A<6>" LOC = "B12" ; +#NET "RAM_A<7>" LOC = "E14" ; +#NET "RAM_A<8>" LOC = "F14" ; +#NET "RAM_A<9>" LOC = "B15" ; +#NET "RAM_A<10>" LOC = "A15" ; +#NET "RAM_A<11>" LOC = "D16" ; +#NET "RAM_A<12>" LOC = "C15" ; +#NET "RAM_A<13>" LOC = "D17" ; +#NET "RAM_A<14>" LOC = "C16" ; +#NET "RAM_A<15>" LOC = "F15" ; +#NET "RAM_A<16>" LOC = "C17" ; +#NET "RAM_A<17>" LOC = "B17" ; +#NET "RAM_A<18>" LOC = "B18" ; +#NET "RAM_A<19>" LOC = "A18" ; +#NET "RAM_A<20>" LOC = "D18" ; +#NET "RAM_BWn<3>" LOC = "D9" ; +#NET "RAM_BWn<2>" LOC = "A9" ; +#NET "RAM_BWn<1>" LOC = "B9" ; +#NET "RAM_BWn<0>" LOC = "G12" ; +#NET "RAM_ZZ" LOC = "J12" ; +#NET "RAM_LDn" LOC = "H12" ; +#NET "RAM_OEn" LOC = "C10" ; +#NET "RAM_WEn" LOC = "D10" ; +#NET "RAM_CENn" LOC = "B10" ; +#NET "RAM_CLK" LOC = "A10" ; + +## SPI Flash +#NET "flash_miso" LOC = "AF24" ; +#NET "flash_clk" LOC = "AE24" ; +#NET "flash_mosi" LOC = "AB15" ; +#NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +##NET "PROG_B" LOC = "A2" ; +##NET "PUDC_B" LOC = "G8" ; +##NET "DONE" LOC = "AB21" ; +##NET "INIT_B" LOC = "AA15" ; + + +##NET "unnamed_net19" LOC = "AE9" ; # VS1 +##NET "unnamed_net18" LOC = "AF9" ; # VS0 +##NET "unnamed_net17" LOC = "AA12" ; # VS2 +##NET "unnamed_net16" LOC = "Y7" ; # M2 +##NET "unnamed_net15" LOC = "AC4" ; # M1 +##NET "unnamed_net14" LOC = "AD4" ; # M0 +##NET "unnamed_net13" LOC = "D4" ; # TMS +##NET "unnamed_net12" LOC = "E23" ; # TDO +##NET "unnamed_net11" LOC = "G7" ; # TDI +##NET "unnamed_net10" LOC = "A25" ; # TCK +##NET "unnamed_net20" LOC = "V20" ; # SUSPEND diff --git a/usrp2/top/u2plus/.gitignore b/usrp2/top/u2plus/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/u2plus/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile new file mode 100644 index 000000000..305b5b9e3 --- /dev/null +++ b/usrp2/top/u2plus/Makefile @@ -0,0 +1,246 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2plus/capture_ddrlvds.v \ +top/u2plus/u2plus.ucf \ +top/u2plus/u2plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v new file mode 100644 index 000000000..b9f53ff8c --- /dev/null +++ b/usrp2/top/u2plus/capture_ddrlvds.v @@ -0,0 +1,39 @@ + + +module capture_ddrlvds + #(parameter WIDTH=7) + (input clk, + input ssclk_p, + input ssclk_n, + input [WIDTH-1:0] in_p, + input [WIDTH-1:0] in_n, + output reg [(2*WIDTH)-1:0] out); + + wire [WIDTH-1:0] ddr_dat; + wire ssclk_regional; + wire ssclk_io; + wire ssclk; + wire [(2*WIDTH)-1:0] out_pre1; + reg [(2*WIDTH)-1:0] out_pre2; + + IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + + genvar i; + generate + for(i = 0; i < WIDTH; i = i + 1) + begin : gen_lvds_pins + IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds + (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); + IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 + (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), + .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); + end + endgenerate + + always @(negedge clk) + out_pre2 <= out_pre1; + + always @(posedge clk) + out <= out_pre2; + +endmodule // capture_ddrlvds diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index 091eb2005..31404dda9 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -1,157 +1,137 @@ -NET "DAC_LOCK" LOC = "P4" ; +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC NET "ADC_clkout_p" LOC = "P1" ; NET "ADC_clkout_n" LOC = "P2" ; -NET "io_rx<15>" LOC = "AD1" ; -NET "io_rx<14>" LOC = "AD2" ; -NET "io_rx<13>" LOC = "AC2" ; -NET "io_rx<12>" LOC = "AC3" ; -NET "io_rx<11>" LOC = "W7" ; -NET "io_rx<10>" LOC = "W6" ; -NET "io_rx<09>" LOC = "U9" ; -NET "io_rx<08>" LOC = "V8" ; -NET "io_rx<07>" LOC = "AB1" ; -NET "io_rx<06>" LOC = "AC1" ; -NET "io_rx<05>" LOC = "V7" ; -NET "io_rx<04>" LOC = "V6" ; -NET "io_rx<03>" LOC = "Y5" ; -NET "ADCB_2_3_p" LOC = "U7" ; -NET "ADCB_2_3_n" LOC = "U8" ; -NET "ADCB_0_1_p" LOC = "AA2" ; -NET "ADCB_0_1_n" LOC = "AA3" ; -NET "ADCA_12_13_p" LOC = "Y1" ; -NET "ADCA_12_13_n" LOC = "Y2" ; -NET "ADCA_10_11_p" LOC = "W3" ; -NET "ADCA_10_11_n" LOC = "W4" ; -NET "ADCA_8_9_p" LOC = "T7" ; -NET "ADCA_8_9_n" LOC = "U6" ; -NET "ADCA_6_7_p" LOC = "U5" ; -NET "ADCA_6_7_n" LOC = "V5" ; -NET "ADCA_4_5_p" LOC = "T10" ; -NET "ADCA_4_5_n" LOC = "T9" ; -NET "ADCA_2_3_p" LOC = "V1" ; -NET "ADCA_2_3_n" LOC = "V2" ; -NET "ADCA_0_1_p" LOC = "R8" ; -NET "ADCA_0_1_n" LOC = "R7" ; -NET "TX00_A" LOC = "P8" ; -NET "TX01_A" LOC = "P9" ; -NET "TX02_A" LOC = "R5" ; -NET "TX03_A" LOC = "R6" ; -NET "TX04_A" LOC = "P7" ; -NET "TX05_A" LOC = "P6" ; -NET "TX06_A" LOC = "T3" ; -NET "TX07_A" LOC = "T4" ; -NET "TX08_A" LOC = "R3" ; -NET "TX09_A" LOC = "R4" ; -NET "TX10_A" LOC = "R2" ; -NET "TX11_A" LOC = "N1" ; -NET "TX12_A" LOC = "N2" ; -NET "TX13_A" LOC = "N5" ; -NET "TX14_A" LOC = "N4" ; -NET "TX15_A" LOC = "M2" ; -NET "TX00_B" LOC = "M5" ; -NET "TX01_B" LOC = "M6" ; -NET "TX02_B" LOC = "M4" ; -NET "TX03_B" LOC = "M3" ; -NET "TX04_B" LOC = "M8" ; -NET "TX05_B" LOC = "M7" ; -NET "TX06_B" LOC = "L4" ; -NET "TX07_B" LOC = "L3" ; -NET "TX08_B" LOC = "K3" ; -NET "TX09_B" LOC = "K2" ; -NET "TX10_B" LOC = "K5" ; -NET "TX11_B" LOC = "K4" ; -NET "TX12_B" LOC = "M10" ; -NET "TX13_B" LOC = "M9" ; -NET "TX14_B" LOC = "J5" ; -NET "TX15_B" LOC = "J4" ; +NET "ADCA_12_p" LOC = "Y1" ; +NET "ADCA_12_n" LOC = "Y2" ; +NET "ADCA_10_p" LOC = "W3" ; +NET "ADCA_10_n" LOC = "W4" ; +NET "ADCA_8_p" LOC = "T7" ; +NET "ADCA_8_n" LOC = "U6" ; +NET "ADCA_6_p" LOC = "U5" ; +NET "ADCA_6_n" LOC = "V5" ; +NET "ADCA_4_p" LOC = "T10" ; +NET "ADCA_4_n" LOC = "T9" ; +NET "ADCA_2_p" LOC = "V1" ; +NET "ADCA_2_n" LOC = "V2" ; +NET "ADCA_0_p" LOC = "R8" ; +NET "ADCA_0_n" LOC = "R7" ; +NET "ADCB_2_p" LOC = "U7" ; +NET "ADCB_2_n" LOC = "U8" ; +NET "ADCB_0_p" LOC = "AA2" ; +NET "ADCB_0_n" LOC = "AA3" ; +NET "ADCB_4_p" LOC = "AE1" ; +NET "ADCB_4_n" LOC = "AE2" ; +NET "ADCB_6_p" LOC = "W1" ; +NET "ADCB_6_n" LOC = "W2" ; +NET "ADCB_8_p" LOC = "U3" ; +NET "ADCB_8_n" LOC = "V4" ; +NET "ADCB_10_p" LOC = "J1" ; +NET "ADCB_10_n" LOC = "K1" ; +NET "ADCB_12_p" LOC = "J3" ; +NET "ADCB_12_n" LOC = "J2" ; + +## DAC +NET "DAC_LOCK" LOC = "P4" ; +NET "DACA<0>" LOC = "P8" ; +NET "DACA<1>" LOC = "P9" ; +NET "DACA<2>" LOC = "R5" ; +NET "DACA<3>" LOC = "R6" ; +NET "DACA<4>" LOC = "P7" ; +NET "DACA<5>" LOC = "P6" ; +NET "DACA<6>" LOC = "T3" ; +NET "DACA<7>" LOC = "T4" ; +NET "DACA<8>" LOC = "R3" ; +NET "DACA<9>" LOC = "R4" ; +NET "DACA<10>" LOC = "R2" ; +NET "DACA<11>" LOC = "N1" ; +NET "DACA<12>" LOC = "N2" ; +NET "DACA<13>" LOC = "N5" ; +NET "DACA<14>" LOC = "N4" ; +NET "DACA<15>" LOC = "M2" ; +NET "DACB<0>" LOC = "M5" ; +NET "DACB<1>" LOC = "M6" ; +NET "DACB<2>" LOC = "M4" ; +NET "DACB<3>" LOC = "M3" ; +NET "DACB<4>" LOC = "M8" ; +NET "DACB<5>" LOC = "M7" ; +NET "DACB<6>" LOC = "L4" ; +NET "DACB<7>" LOC = "L3" ; +NET "DACB<8>" LOC = "K3" ; +NET "DACB<9>" LOC = "K2" ; +NET "DACB<10>" LOC = "K5" ; +NET "DACB<11>" LOC = "K4" ; +NET "DACB<12>" LOC = "M10" ; +NET "DACB<13>" LOC = "M9" ; +NET "DACB<14>" LOC = "J5" ; +NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO NET "io_tx<15>" LOC = "K6" ; NET "io_tx<14>" LOC = "L7" ; NET "io_tx<13>" LOC = "H2" ; NET "io_tx<12>" LOC = "H1" ; NET "io_tx<11>" LOC = "L10" ; NET "io_tx<10>" LOC = "L9" ; -NET "io_tx<09>" LOC = "G3" ; -NET "io_tx<08>" LOC = "F3" ; -NET "io_tx<07>" LOC = "K7" ; -NET "io_tx<06>" LOC = "J6" ; -NET "io_tx<05>" LOC = "E1" ; -NET "io_tx<04>" LOC = "F2" ; -NET "io_tx<03>" LOC = "J7" ; -NET "io_tx<02>" LOC = "H6" ; -NET "io_tx<01>" LOC = "F5" ; -NET "io_tx<00>" LOC = "G4" ; -NET "MOSI_RX_ADC" LOC = "E3" ; -NET "SCLK_RX_ADC" LOC = "F4" ; -NET "SEN_RX_ADC" LOC = "D3" ; -NET "SCLK_RX_DAC" LOC = "E4" ; -NET "SEN_RX_DAC" LOC = "K9" ; -NET "MOSI_RX_DAC" LOC = "K8" ; -NET "SCLK_RX_DB" LOC = "G6" ; -NET "MOSI_RX_DB" LOC = "H7" ; -NET "SEN_RX_DB" LOC = "B2" ; -NET "SCLK_ADC" LOC = "B1" ; -NET "MOSI_ADC" LOC = "J8" ; -NET "SEN_ADC" LOC = "J9" ; -NET "ADCB_4_5_p" LOC = "AE1" ; -NET "ADCB_4_5_n" LOC = "AE2" ; -NET "ADCB_6_7_p" LOC = "W1" ; -NET "ADCB_6_7_n" LOC = "W2" ; -NET "ADCB_8_9_p" LOC = "U3" ; -NET "ADCB_8_9_n" LOC = "V4" ; -NET "ADCB_10_11_p" LOC = "J1" ; -NET "ADCB_10_11_n" LOC = "K1" ; -NET "ADCB_12_13_p" LOC = "J3" ; -NET "ADCB_12_13_n" LOC = "J2" ; -NET "MISO_RX_DB" LOC = "H4" ; -NET "MISO_RX_ADC" LOC = "C1" ; -NET "MISO_TX_DB" LOC = "AA5" ; -NET "MISO_DAC" LOC = "Y3" ; -NET "MISO_TX_ADC" LOC = "G1" ; -NET "io_rx<02>" LOC = "R10" ; -NET "io_rx<01>" LOC = "R1" ; -NET "io_rx<00>" LOC = "M1" ; -NET "exp_user_out_p" LOC = "AF14" ; -NET "exp_user_out_n" LOC = "AE14" ; -NET "exp_time_out_p" LOC = "Y14" ; -NET "exp_time_out_n" LOC = "AA14" ; -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; +NET "io_tx<9>" LOC = "G3" ; +NET "io_tx<8>" LOC = "F3" ; +NET "io_tx<7>" LOC = "K7" ; +NET "io_tx<6>" LOC = "J6" ; +NET "io_tx<5>" LOC = "E1" ; +NET "io_tx<4>" LOC = "F2" ; +NET "io_tx<3>" LOC = "J7" ; +NET "io_tx<2>" LOC = "H6" ; +NET "io_tx<1>" LOC = "F5" ; +NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +NET "io_rx<15>" LOC = "AD1" ; +NET "io_rx<14>" LOC = "AD2" ; +NET "io_rx<13>" LOC = "AC2" ; +NET "io_rx<12>" LOC = "AC3" ; +NET "io_rx<11>" LOC = "W7" ; +NET "io_rx<10>" LOC = "W6" ; +NET "io_rx<9>" LOC = "U9" ; +NET "io_rx<8>" LOC = "V8" ; +NET "io_rx<7>" LOC = "AB1" ; +NET "io_rx<6>" LOC = "AC1" ; +NET "io_rx<5>" LOC = "V7" ; +NET "io_rx<4>" LOC = "V6" ; +NET "io_rx<3>" LOC = "Y5" ; +NET "io_rx<2>" LOC = "R10" ; +NET "io_rx<1>" LOC = "R1" ; +NET "io_rx<0>" LOC = "M1" ; + +## MISC NET "leds<5>" LOC = "AF25" ; NET "leds<4>" LOC = "AE25" ; NET "leds<3>" LOC = "AF23" ; NET "leds<2>" LOC = "AE23" ; NET "leds<1>" LOC = "AB18" ; -NET "SEN_CLK" LOC = "AA18" ; -NET "MOSI_CLK" LOC = "W17" ; -NET "SCLK_CLK" LOC = "V17" ; -NET "CLK_STATUS" LOC = "AD22" ; -NET "CLK_FUNC" LOC = "AC21" ; -NET "clk_sel<0>" LOC = "AE21" ; -NET "clk_sel<1>" LOC = "AD21" ; -NET "clk_en<1>" LOC = "AA17" ; -NET "clk_en<0>" LOC = "Y17" ; -NET "SDA" LOC = "V16" ; -NET "SCL" LOC = "U16" ; -NET "TXD3" LOC = "AD20" ; -NET "TXD2" LOC = "AC20" ; -NET "TXD1" LOC = "AD19" ; -NET "debug<00>" LOC = "AC19" ; -NET "debug<01>" LOC = "AF20" ; -NET "debug<02>" LOC = "AE20" ; -NET "debug<03>" LOC = "AC16" ; -NET "debug<04>" LOC = "AB16" ; -NET "debug<05>" LOC = "AF19" ; -NET "debug<06>" LOC = "AE19" ; -NET "debug<07>" LOC = "V15" ; -NET "debug<08>" LOC = "U15" ; -NET "debug<09>" LOC = "AE17" ; +NET "FPGA_RESET" LOC = "K24" ; + +## Debug +NET "debug_clk<0>" LOC = "AA10" ; +NET "debug_clk<1>" LOC = "AD11" ; +NET "debug<0>" LOC = "AC19" ; +NET "debug<1>" LOC = "AF20" ; +NET "debug<2>" LOC = "AE20" ; +NET "debug<3>" LOC = "AC16" ; +NET "debug<4>" LOC = "AB16" ; +NET "debug<5>" LOC = "AF19" ; +NET "debug<6>" LOC = "AE19" ; +NET "debug<7>" LOC = "V15" ; +NET "debug<8>" LOC = "U15" ; +NET "debug<9>" LOC = "AE17" ; NET "debug<10>" LOC = "AD17" ; NET "debug<11>" LOC = "V14" ; NET "debug<12>" LOC = "W15" ; NET "debug<13>" LOC = "AC15" ; NET "debug<14>" LOC = "AD14" ; NET "debug<15>" LOC = "AC14" ; -NET "debug_clk<1>" LOC = "AD11" ; NET "debug<16>" LOC = "AC11" ; NET "debug<17>" LOC = "AB12" ; NET "debug<18>" LOC = "AC12" ; @@ -168,103 +148,183 @@ NET "debug<28>" LOC = "AB7" ; NET "debug<29>" LOC = "V11" ; NET "debug<30>" LOC = "U11" ; NET "debug<31>" LOC = "Y10" ; -NET "debug_clk<0>" LOC = "AA10" ; + +## UARTS +NET "TXD<3>" LOC = "AD20" ; +NET "TXD<2>" LOC = "AC20" ; +NET "TXD<1>" LOC = "AD19" ; +NET "RXD<3>" LOC = "AF17" ; +NET "RXD<2>" LOC = "AF15" ; +NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +NET "CLK_STATUS" LOC = "AD22" ; +NET "CLK_FUNC" LOC = "AC21" ; +NET "clk_sel<0>" LOC = "AE21" ; +NET "clk_sel<1>" LOC = "AD21" ; +NET "clk_en<1>" LOC = "AA17" ; +NET "clk_en<0>" LOC = "Y17" ; + +## I2C +NET "SDA" LOC = "V16" ; +NET "SCL" LOC = "U16" ; + +## Timing +NET "PPS_IN" LOC = "AB6" ; +NET "PPS2_IN" LOC = "AA20" ; + +## SPI +NET "SEN_CLK" LOC = "AA18" ; +NET "MOSI_CLK" LOC = "W17" ; +NET "SCLK_CLK" LOC = "V17" ; +NET "MISO_CLK" LOC = "AC10" ; + NET "SEN_DAC" LOC = "AE7" ; NET "SCLK_DAC" LOC = "AF5" ; NET "MOSI_DAC" LOC = "AE6" ; +NET "MISO_DAC" LOC = "Y3" ; + +NET "SCLK_ADC" LOC = "B1" ; +NET "MOSI_ADC" LOC = "J8" ; +NET "SEN_ADC" LOC = "J9" ; + NET "MOSI_TX_ADC" LOC = "V10" ; NET "SEN_TX_ADC" LOC = "W10" ; NET "SCLK_TX_ADC" LOC = "AC6" ; +NET "MISO_TX_ADC" LOC = "G1" ; + NET "MOSI_TX_DAC" LOC = "AD6" ; NET "SEN_TX_DAC" LOC = "AE4" ; NET "SCLK_TX_DAC" LOC = "AF4" ; + NET "SCLK_TX_DB" LOC = "AE3" ; NET "MOSI_TX_DB" LOC = "AF3" ; NET "SEN_TX_DB" LOC = "W9" ; -NET "RXD3" LOC = "AF17" ; -NET "RXD2" LOC = "AF15" ; -NET "RXD1" LOC = "AD12" ; -NET "MISO_CLK" LOC = "AC10" ; -NET "PPS_IN" LOC = "AB6" ; -NET "PPS2_IN" LOC = "AA20" ; -NET "ser_rx_clk" LOC = "P18" ; -NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +NET "MISO_TX_DB" LOC = "AA5" ; + +NET "MOSI_RX_ADC" LOC = "E3" ; +NET "SCLK_RX_ADC" LOC = "F4" ; +NET "SEN_RX_ADC" LOC = "D3" ; +NET "MISO_RX_ADC" LOC = "C1" ; + +NET "SCLK_RX_DAC" LOC = "E4" ; +NET "SEN_RX_DAC" LOC = "K9" ; +NET "MOSI_RX_DAC" LOC = "K8" ; + +NET "SCLK_RX_DB" LOC = "G6" ; +NET "MOSI_RX_DB" LOC = "H7" ; +NET "SEN_RX_DB" LOC = "B2" ; +NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY NET "CLK_TO_MAC" LOC = "P26" ; -NET "GMII_TX_CLK" LOC = "P25" ; -NET "GMII_RX_CLK" LOC = "P21" ; -NET "ETH_LED" LOC = "H20" ; -NET "GMII_TXD7" LOC = "G21" ; -NET "GMII_TXD6" LOC = "C26" ; -NET "GMII_TXD5" LOC = "C25" ; -NET "GMII_TXD4" LOC = "J21" ; -NET "GMII_TXD3" LOC = "H21" ; -NET "GMII_TXD2" LOC = "D25" ; -NET "GMII_TXD1" LOC = "D24" ; -NET "GMII_TXD0" LOC = "E26" ; + +NET "GMII_TXD<7>" LOC = "G21" ; +NET "GMII_TXD<6>" LOC = "C26" ; +NET "GMII_TXD<5>" LOC = "C25" ; +NET "GMII_TXD<4>" LOC = "J21" ; +NET "GMII_TXD<3>" LOC = "H21" ; +NET "GMII_TXD<2>" LOC = "D25" ; +NET "GMII_TXD<1>" LOC = "D24" ; +NET "GMII_TXD<0>" LOC = "E26" ; NET "GMII_TX_EN" LOC = "D26" ; NET "GMII_TX_ER" LOC = "J19" ; NET "GMII_GTX_CLK" LOC = "J20" ; -NET "GMII_RXD7" LOC = "G22" ; -NET "GMII_RXD6" LOC = "K19" ; -NET "GMII_RXD5" LOC = "K18" ; -NET "GMII_RXD4" LOC = "E24" ; -NET "GMII_RXD3" LOC = "F23" ; -NET "GMII_RXD2" LOC = "L18" ; -NET "GMII_RXD1" LOC = "L17" ; -NET "GMII_RXD0" LOC = "F25" ; +NET "GMII_TX_CLK" LOC = "P25" ; + +NET "GMII_RX_CLK" LOC = "P21" ; +NET "GMII_RXD<7>" LOC = "G22" ; +NET "GMII_RXD<6>" LOC = "K19" ; +NET "GMII_RXD<5>" LOC = "K18" ; +NET "GMII_RXD<4>" LOC = "E24" ; +NET "GMII_RXD<3>" LOC = "F23" ; +NET "GMII_RXD<2>" LOC = "L18" ; +NET "GMII_RXD<1>" LOC = "L17" ; +NET "GMII_RXD<0>" LOC = "F25" ; NET "GMII_RX_DV" LOC = "F24" ; NET "GMII_RX_ER" LOC = "L20" ; NET "GMII_CRS" LOC = "K20" ; NET "GMII_COL" LOC = "G23" ; + NET "PHY_INTn" LOC = "L22" ; NET "MDIO" LOC = "K21" ; NET "MDC" LOC = "J23" ; -NET "PHY_RESET" LOC = "J22" ; +NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" ; + +## MIMO Interface +NET "exp_time_out_p" LOC = "Y14" ; +NET "exp_time_out_n" LOC = "AA14" ; NET "exp_time_in_p" LOC = "N18" ; NET "exp_time_in_n" LOC = "N17" ; +NET "exp_user_out_p" LOC = "AF14" ; +NET "exp_user_out_n" LOC = "AE14" ; NET "exp_user_in_p" LOC = "L24" ; NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +NET "ser_enable" LOC = "R20" ; NET "ser_prbsen" LOC = "U23" ; NET "ser_loopen" LOC = "R19" ; -NET "ser_enable" LOC = "R20" ; +NET "ser_rx_en" LOC = "Y21" ; +NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK NET "ser_t<15>" LOC = "V23" ; NET "ser_t<14>" LOC = "U22" ; NET "ser_t<13>" LOC = "V24" ; NET "ser_t<12>" LOC = "V25" ; NET "ser_t<11>" LOC = "W23" ; NET "ser_t<10>" LOC = "V22" ; -NET "ser_t<09>" LOC = "T18" ; -NET "ser_t<08>" LOC = "T17" ; -NET "ser_t<07>" LOC = "Y24" ; -NET "ser_t<06>" LOC = "Y25" ; -NET "ser_t<05>" LOC = "U21" ; -NET "ser_t<04>" LOC = "T20" ; -NET "ser_t<03>" LOC = "Y22" ; -NET "ser_t<02>" LOC = "Y23" ; -NET "ser_t<01>" LOC = "U19" ; -NET "ser_t<00>" LOC = "U18" ; +NET "ser_t<9>" LOC = "T18" ; +NET "ser_t<8>" LOC = "T17" ; +NET "ser_t<7>" LOC = "Y24" ; +NET "ser_t<6>" LOC = "Y25" ; +NET "ser_t<5>" LOC = "U21" ; +NET "ser_t<4>" LOC = "T20" ; +NET "ser_t<3>" LOC = "Y22" ; +NET "ser_t<2>" LOC = "Y23" ; +NET "ser_t<1>" LOC = "U19" ; +NET "ser_t<0>" LOC = "U18" ; NET "ser_tkmsb" LOC = "AA24" ; NET "ser_tklsb" LOC = "AA25" ; +NET "ser_rx_clk" LOC = "P18" ; NET "ser_r<15>" LOC = "V21" ; NET "ser_r<14>" LOC = "U20" ; NET "ser_r<13>" LOC = "AA22" ; NET "ser_r<12>" LOC = "AA23" ; NET "ser_r<11>" LOC = "V18" ; NET "ser_r<10>" LOC = "V19" ; -NET "ser_r<09>" LOC = "AB23" ; -NET "ser_r<08>" LOC = "AC26" ; -NET "ser_r<07>" LOC = "AB26" ; -NET "ser_r<06>" LOC = "AD26" ; -NET "ser_r<05>" LOC = "AC25" ; -NET "ser_r<04>" LOC = "W20" ; -NET "ser_r<03>" LOC = "W21" ; -NET "ser_r<02>" LOC = "AC23" ; -NET "ser_r<01>" LOC = "AC24" ; -NET "ser_r<00>" LOC = "AE26" ; +NET "ser_r<9>" LOC = "AB23" ; +NET "ser_r<8>" LOC = "AC26" ; +NET "ser_r<7>" LOC = "AB26" ; +NET "ser_r<6>" LOC = "AD26" ; +NET "ser_r<5>" LOC = "AC25" ; +NET "ser_r<4>" LOC = "W20" ; +NET "ser_r<3>" LOC = "W21" ; +NET "ser_r<2>" LOC = "AC23" ; +NET "ser_r<1>" LOC = "AC24" ; +NET "ser_r<0>" LOC = "AE26" ; NET "ser_rkmsb" LOC = "AD25" ; NET "ser_rklsb" LOC = "Y20" ; -NET "ser_rx_en" LOC = "Y21" ; -NET "FPGA_RESET" LOC = "K24" ; + +## SRAM +NET "RAM_D<35>" LOC = "K16" ; +NET "RAM_D<34>" LOC = "D20" ; +NET "RAM_D<33>" LOC = "C20" ; +NET "RAM_D<32>" LOC = "E21" ; +NET "RAM_D<31>" LOC = "D21" ; +NET "RAM_D<30>" LOC = "C21" ; +NET "RAM_D<29>" LOC = "B21" ; +NET "RAM_D<28>" LOC = "H17" ; +NET "RAM_D<27>" LOC = "G17" ; +NET "RAM_D<26>" LOC = "B23" ; +NET "RAM_D<25>" LOC = "A22" ; +NET "RAM_D<24>" LOC = "D23" ; +NET "RAM_D<23>" LOC = "C23" ; +NET "RAM_D<22>" LOC = "D22" ; +NET "RAM_D<21>" LOC = "C22" ; +NET "RAM_D<20>" LOC = "F19" ; +NET "RAM_D<19>" LOC = "G20" ; +NET "RAM_D<18>" LOC = "F20" ; NET "RAM_D<17>" LOC = "F7" ; NET "RAM_D<16>" LOC = "E7" ; NET "RAM_D<15>" LOC = "G9" ; @@ -273,36 +333,26 @@ NET "RAM_D<13>" LOC = "G10" ; NET "RAM_D<12>" LOC = "H10" ; NET "RAM_D<11>" LOC = "A4" ; NET "RAM_D<10>" LOC = "B4" ; -NET "RAM_D<09>" LOC = "C5" ; -NET "RAM_D<08>" LOC = "D6" ; -NET "RAM_D<07>" LOC = "J11" ; -NET "RAM_D<06>" LOC = "K11" ; -NET "RAM_D<05>" LOC = "B7" ; -NET "RAM_D<04>" LOC = "C7" ; -NET "RAM_D<03>" LOC = "B6" ; -NET "RAM_D<02>" LOC = "C6" ; -NET "RAM_D<01>" LOC = "C8" ; -NET "RAM_D<00>" LOC = "D8" ; -NET "RAM_ZZ" LOC = "J12" ; -NET "RAM_BWn<3>" LOC = "D9" ; -NET "RAM_BWn<2>" LOC = "A9" ; -NET "RAM_BWn<1>" LOC = "B9" ; -NET "RAM_BWn<0>" LOC = "G12" ; -NET "RAM_LDn" LOC = "H12" ; -NET "RAM_OEn" LOC = "C10" ; -NET "RAM_WEn" LOC = "D10" ; -NET "RAM_CLK" LOC = "A10" ; -NET "RAM_CENn" LOC = "B10" ; -NET "RAM_A<00>" LOC = "C11" ; -NET "RAM_A<01>" LOC = "E12" ; -NET "RAM_A<02>" LOC = "F12" ; -NET "RAM_A<03>" LOC = "D13" ; -NET "RAM_A<04>" LOC = "C12" ; -NET "RAM_A<05>" LOC = "A12" ; -NET "RAM_A<06>" LOC = "B12" ; -NET "RAM_A<07>" LOC = "E14" ; -NET "RAM_A<08>" LOC = "F14" ; -NET "RAM_A<09>" LOC = "B15" ; +NET "RAM_D<9>" LOC = "C5" ; +NET "RAM_D<8>" LOC = "D6" ; +NET "RAM_D<7>" LOC = "J11" ; +NET "RAM_D<6>" LOC = "K11" ; +NET "RAM_D<5>" LOC = "B7" ; +NET "RAM_D<4>" LOC = "C7" ; +NET "RAM_D<3>" LOC = "B6" ; +NET "RAM_D<2>" LOC = "C6" ; +NET "RAM_D<1>" LOC = "C8" ; +NET "RAM_D<0>" LOC = "D8" ; +NET "RAM_A<0>" LOC = "C11" ; +NET "RAM_A<1>" LOC = "E12" ; +NET "RAM_A<2>" LOC = "F12" ; +NET "RAM_A<3>" LOC = "D13" ; +NET "RAM_A<4>" LOC = "C12" ; +NET "RAM_A<5>" LOC = "A12" ; +NET "RAM_A<6>" LOC = "B12" ; +NET "RAM_A<7>" LOC = "E14" ; +NET "RAM_A<8>" LOC = "F14" ; +NET "RAM_A<9>" LOC = "B15" ; NET "RAM_A<10>" LOC = "A15" ; NET "RAM_A<11>" LOC = "D16" ; NET "RAM_A<12>" LOC = "C15" ; @@ -314,41 +364,38 @@ NET "RAM_A<17>" LOC = "B17" ; NET "RAM_A<18>" LOC = "B18" ; NET "RAM_A<19>" LOC = "A18" ; NET "RAM_A<20>" LOC = "D18" ; -NET "RAM_D<35>" LOC = "K16" ; -NET "RAM_D<34>" LOC = "D20" ; -NET "RAM_D<33>" LOC = "C20" ; -NET "RAM_D<32>" LOC = "E21" ; -NET "RAM_D<31>" LOC = "D21" ; -NET "RAM_D<30>" LOC = "C21" ; -NET "RAM_D<29>" LOC = "B21" ; -NET "RAM_D<28>" LOC = "H17" ; -NET "RAM_D<27>" LOC = "G17" ; -NET "RAM_D<26>" LOC = "B23" ; -NET "RAM_D<25>" LOC = "A22" ; -NET "RAM_D<24>" LOC = "D23" ; -NET "RAM_D<23>" LOC = "C23" ; -NET "RAM_D<22>" LOC = "D22" ; -NET "RAM_D<21>" LOC = "C22" ; -NET "RAM_D<20>" LOC = "F19" ; -NET "RAM_D<19>" LOC = "G20" ; -NET "RAM_D<18>" LOC = "F20" ; -#NET "unnamed_net20" LOC = "V20" ; # SUSPEND -NET "PROG_B" LOC = "A2" ; -NET "PUDC_B" LOC = "G8" ; -NET "DONE" LOC = "AB21" ; +NET "RAM_BWn<3>" LOC = "D9" ; +NET "RAM_BWn<2>" LOC = "A9" ; +NET "RAM_BWn<1>" LOC = "B9" ; +NET "RAM_BWn<0>" LOC = "G12" ; +NET "RAM_ZZ" LOC = "J12" ; +NET "RAM_LDn" LOC = "H12" ; +NET "RAM_OEn" LOC = "C10" ; +NET "RAM_WEn" LOC = "D10" ; +NET "RAM_CENn" LOC = "B10" ; +NET "RAM_CLK" LOC = "A10" ; + +## SPI Flash NET "flash_miso" LOC = "AF24" ; NET "flash_clk" LOC = "AE24" ; -NET "INIT_B" LOC = "AA15" ; NET "flash_mosi" LOC = "AB15" ; +NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +#NET "PROG_B" LOC = "A2" ; +#NET "PUDC_B" LOC = "G8" ; +#NET "DONE" LOC = "AB21" ; +#NET "INIT_B" LOC = "AA15" ; + + #NET "unnamed_net19" LOC = "AE9" ; # VS1 #NET "unnamed_net18" LOC = "AF9" ; # VS0 #NET "unnamed_net17" LOC = "AA12" ; # VS2 #NET "unnamed_net16" LOC = "Y7" ; # M2 -NET "flash_cs" LOC = "AA7" ; #NET "unnamed_net15" LOC = "AC4" ; # M1 #NET "unnamed_net14" LOC = "AD4" ; # M0 #NET "unnamed_net13" LOC = "D4" ; # TMS #NET "unnamed_net12" LOC = "E23" ; # TDO #NET "unnamed_net11" LOC = "G7" ; # TDI #NET "unnamed_net10" LOC = "A25" ; # TCK - +#NET "unnamed_net20" LOC = "V20" ; # SUSPEND diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index e95445867..fef23af60 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -3,46 +3,93 @@ module u2plus ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + input ADC_clkout_p, input ADC_clkout_n, + input ADCA_12_p, input ADCA_12_n, + input ADCA_10_p, input ADCA_10_n, + input ADCA_8_p, input ADCA_8_n, + input ADCA_6_p, input ADCA_6_n, + input ADCA_4_p, input ADCA_4_n, + input ADCA_2_p, input ADCA_2_n, + input ADCA_0_p, input ADCA_0_n, + input ADCB_12_p, input ADCB_12_n, + input ADCB_10_p, input ADCB_10_n, + input ADCB_8_p, input ADCB_8_n, + input ADCB_6_p, input ADCB_6_n, + input ADCB_4_p, input ADCB_4_n, + input ADCB_2_p, input ADCB_2_n, + input ADCB_0_p, input ADCB_0_n, + + // DAC + output [15:0] DACA, + output [15:0] DACB, + input DAC_LOCK, // unused for now + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + // Misc, debug - output [4:0] leds, // LED4 is shared w/INIT_B - input [3:0] dipsw, - output [31:0] debug, + output [5:1] leds, // LED4 is shared w/INIT_B + input FPGA_RESET, output [1:0] debug_clk, - output uart_tx_o, - input uart_rx_i, - - // Expansion - input exp_pps_in_p, // Diff - input exp_pps_in_n, // Diff - output exp_pps_out_p, // Diff - output exp_pps_out_n, // Diff + output [31:0] debug, + output [3:1] TXD, input [3:1] RXD, // UARTs + //input [3:0] dipsw, // Forgot DIP Switches... - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input CLK_FUNC, // FIXME is an input to control the 9510 + input CLK_STATUS, + + inout SCL, inout SDA, // I2C + + // PPS + input PPS_IN, input PPS2_IN, + + // SPI + output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, + output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, + output SEN_ADC, output SCLK_ADC, output MOSI_ADC, + output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, + output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, + output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, + output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, + output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, + output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, + + // GigE PHY + input CLK_TO_MAC, - // GMII-TX output reg [7:0] GMII_TXD, output reg GMII_TX_EN, output reg GMII_TX_ER, output GMII_GTX_CLK, input GMII_TX_CLK, // 100mbps clk - // GMII-RX - input [7:0] GMII_RXD, input GMII_RX_CLK, + input [7:0] GMII_RXD, input GMII_RX_DV, input GMII_RX_ER, + input GMII_COL, + input GMII_CRS, - // GMII-Management + input PHY_INTn, // open drain inout MDIO, output MDC, - input PHY_INTn, // open drain output PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - input clk_to_mac, - output eth_led, + output ETH_LED, + + input POR, + + // Expansion + input exp_time_in_p, input exp_time_in_n, // Diff + output exp_time_out_p, output exp_time_out_n, // Diff + input exp_user_in_p, input exp_user_in_n, // Diff + output exp_user_out_p, output exp_user_out_n, // Diff // SERDES output ser_enable, @@ -59,75 +106,18 @@ module u2plus input [15:0] ser_r, input ser_rklsb, input ser_rkmsb, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - input dac_lock, // unused for now - - // I2C - inout SCL, - inout SDA, - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Clocks - input clk_fpga_p, // Diff - input clk_fpga_n, // Diff - input pps_in, - input POR, + // SRAM + inout [35:0] RAM_D, + output [20:0] RAM_A, + output [3:0] RAM_BWn, + output RAM_ZZ, + output RAM_LDn, + output RAM_OEn, + output RAM_WEn, + output RAM_CENn, + output RAM_CLK, - // AD9510 SPI - output sclk, - output sen_clk, - output sdi, - input sdo, - - // TX side SPI -- tx_db, tx_adc, tx_dac, 9777 - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output mosi_tx, - input miso_dac, - input miso_tx_db, - input miso_tx_adc, - output sclk_tx, - - // RX side SPI - output sen_rx_db, - output sclk_rx_db, - input sdo_rx_db, - output sdi_rx_db, - - output sen_rx_adc, - output sclk_rx_adc, - input sdo_rx_adc, - output sdi_rx_adc, - - output sen_rx_dac, - output sclk_rx_dac, - output sdi_rx_dac, - - // DB IO Pins - inout [15:0] io_tx, - inout [15:0] io_rx, - // SPI Flash output flash_cs, output flash_clk, @@ -136,37 +126,49 @@ module u2plus ); // FPGA-specific pins connections - wire aux_clk = PHY_CLK; - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - wire exp_pps_in; - IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); - defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - wire exp_pps_out; - OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); - defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge aux_clk) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - wire clk_muxed = clock_ready ? clk_fpga : aux_clk; + wire exp_user_in; + IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); + defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_out; + OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); + defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; - wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; - assign adc_oen_a = ~adc_oe_a; - assign adc_oen_b = ~adc_oe_b; - assign adc_pdn_a = ~adc_on_a; - assign adc_pdn_b = ~adc_on_b; + wire dcm_rst = 0; + wire [13:0] adc_a, adc_b; +`ifdef LVDS + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a,adc_b})); +`else + assign adc_a = {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; + assign adc_b = {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; + +`endif // !`ifdef LVDS + // Handle Clocks DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_muxed), + .CLKIN(clk_fpga), .DSSEN(0), .PSCLK(0), .PSEN(0), @@ -207,23 +209,26 @@ module u2plus IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds + wire [5:0] leds_int; + assign {leds,ETH_LED} = ~leds_int; // drive low to turn on leds // SPI - wire miso, mosi, sclk_int; - assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; - - assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | - (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | - (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + wire miso, mosi, sclk; + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; wire [7:0] GMII_TXD_unreg; wire GMII_GTX_CLK_int; @@ -289,8 +294,8 @@ module u2plus .leds (leds_int), .debug (debug[31:0]), .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), + .exp_pps_in (exp_time_in), + .exp_pps_out (exp_time_out), .GMII_COL (GMII_COL), .GMII_CRS (GMII_CRS), .GMII_TXD (GMII_TXD_unreg[7:0]), @@ -306,7 +311,6 @@ module u2plus .MDC (MDC), .PHY_INTn (PHY_INTn), .PHY_RESETn (PHY_RESETn), - .PHY_CLK (PHY_CLK), .ser_enable (ser_enable), .ser_prbsen (ser_prbsen), .ser_loopen (ser_loopen), @@ -333,8 +337,8 @@ module u2plus .adc_ovf_b (adc_ovf_b), .adc_on_b (adc_on_b), .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), + .dac_a (DACA[15:0]), + .dac_b (DACB[15:0]), .scl_pad_i (scl_pad_i), .scl_pad_o (scl_pad_o), .scl_pad_oen_o (scl_pad_oen_o), @@ -367,11 +371,17 @@ module u2plus .RAM_OEn (RAM_OEn), .RAM_LDn (RAM_LDn), .uart_tx_o (uart_tx_o), - //.uart_rx_i (uart_rx_i), - .uart_rx_i (), + .uart_rx_i (uart_rx_i), .uart_baud_o (), .sim_mode (1'b0), .clock_divider (2) ); + + assign RAM_ZZ = 1; + assign flash_clk = 0; + assign flash_cs = 1; + assign flash_mosi = 0; + assign RAM_BWn = 4'b1111; + assign TXD = 3'b111; endmodule // u2plus -- cgit v1.2.3 From 1f8934a3b3750eecf8f7c99938f064db27c83790 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 7 Jun 2010 12:12:44 -0700 Subject: works, leds on front count up. --- usrp2/top/safe_u2plus/safe_u2plus.v | 343 +----------------------------------- 1 file changed, 2 insertions(+), 341 deletions(-) diff --git a/usrp2/top/safe_u2plus/safe_u2plus.v b/usrp2/top/safe_u2plus/safe_u2plus.v index 38b276000..dca9688c5 100644 --- a/usrp2/top/safe_u2plus/safe_u2plus.v +++ b/usrp2/top/safe_u2plus/safe_u2plus.v @@ -4,130 +4,12 @@ module safe_u2plus ( input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - //input ADC_clkout_p, //input ADC_clkout_n, - //input ADCA_12_p, //input ADCA_12_n, - //input ADCA_10_p, //input ADCA_10_n, - //input ADCA_8_p, //input ADCA_8_n, - //input ADCA_6_p, //input ADCA_6_n, - //input ADCA_4_p, //input ADCA_4_n, - //input ADCA_2_p, //input ADCA_2_n, - //input ADCA_0_p, //input ADCA_0_n, - //input ADCB_12_p, //input ADCB_12_n, - //input ADCB_10_p, //input ADCB_10_n, - //input ADCB_8_p, //input ADCB_8_n, - //input ADCB_6_p, //input ADCB_6_n, - //input ADCB_4_p, //input ADCB_4_n, - //input ADCB_2_p, //input ADCB_2_n, - //input ADCB_0_p, //input ADCB_0_n, - - // DAC - //output [15:0] DACA, - //output [15:0] DACB, - //input DAC_LOCK, // unused for now - - // DB IO Pins - //inout [15:0] io_tx, - //inout [15:0] io_rx, - - // Misc, debug output [5:1] leds, // LED4 is shared w/INIT_B - //input FPGA_RESET, - //output [1:0] debug_clk, - //output [31:0] debug, - //output [3:1] TXD, //input [3:1] RXD, // UARTs - ////input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - //output [1:0] clk_en, - //output [1:0] clk_sel, - //input CLK_FUNC, // FIXME is an //input to control the 9510 - //input CLK_STATUS, - - //inout SCL, //inout SDA, // I2C - - // PPS - //input PPS_IN, //input PPS2_IN, - - // SPI - //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, - //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, - //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, - //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, - //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, - //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, - //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, - //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, - //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, - - // GigE PHY - //input CLK_TO_MAC, - - //output reg [7:0] GMII_TXD, - //output reg GMII_TX_EN, - //output reg GMII_TX_ER, - //output GMII_GTX_CLK, - //input GMII_TX_CLK, // 100mbps clk - - //input GMII_RX_CLK, - //input [7:0] GMII_RXD, - //input GMII_RX_DV, - //input GMII_RX_ER, - //input GMII_COL, - //input GMII_CRS, - - //input PHY_INTn, // open drain - //inout MDIO, - //output MDC, - //output PHY_RESETn, output ETH_LED - - //input POR, - - // Expansion - //input exp_time_in_p, //input exp_time_in_n, // Diff - //output exp_time_out_p, //output exp_time_out_n, // Diff - //input exp_user_in_p, //input exp_user_in_n, // Diff - //output exp_user_out_p, //output exp_user_out_n, // Diff - - // SERDES - //output ser_enable, - //output ser_prbsen, - //output ser_loopen, - //output ser_rx_en, - - //output ser_tx_clk, - //output reg [15:0] ser_t, - //output reg ser_tklsb, - //output reg ser_tkmsb, - - //input ser_rx_clk, - //input [15:0] ser_r, - //input ser_rklsb, - //input ser_rkmsb, - - // SRAM - //inout [35:0] RAM_D, - //output [20:0] RAM_A, - //output [3:0] RAM_BWn, - //output RAM_ZZ, - //output RAM_LDn, - //output RAM_OEn, - //output RAM_WEn, - //output RAM_CENn, - //output RAM_CLK, - - // SPI Flash - //output flash_cs, - //output flash_clk, - //output flash_mosi, - //input flash_miso ); - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - + wire clk_fpga; + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; @@ -138,225 +20,4 @@ module safe_u2plus assign {leds,ETH_LED} = ~ctr[29:24]; - -/* - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire dcm_rst = 0; - - wire [13:0] adc_a, adc_b; - - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a,adc_b})); - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; - - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - u2_core u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_time_in), - .exp_pps_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (DACA[15:0]), - .dac_b (DACB[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); -*/ endmodule // safe_u2plus -- cgit v1.2.3 From b7e1b9ce77a0df46a5b336fda1e1972aa8199488 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 7 Jun 2010 14:22:30 -0700 Subject: compiles now, added clock constraints --- usrp2/top/u2plus/Makefile | 28 +++++++++++++++++++++++++--- usrp2/top/u2plus/u2plus.ucf | 18 ++++++++++++++++++ 2 files changed, 43 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile index 305b5b9e3..29928e03e 100644 --- a/usrp2/top/u2plus/Makefile +++ b/usrp2/top/u2plus/Makefile @@ -70,6 +70,7 @@ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ control_lib/settings_bus.v \ +control_lib/settings_bus_crossclock.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ @@ -82,7 +83,18 @@ control_lib/sd_spi.v \ control_lib/sd_spi_wb.v \ control_lib/wb_bridge_16_32.v \ control_lib/reset_sync.v \ +control_lib/priority_enc.v \ +control_lib/pic.v \ +vrt/vita_rx_control.v \ +vrt/vita_rx_framer.v \ +vrt/vita_tx_control.v \ +vrt/vita_tx_deframer.v \ +udp/udp_wrapper.v \ +udp/fifo19_rxrealign.v \ +udp/prot_eng_tx.v \ +udp/add_onescomp.v \ simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac_wrapper19.v \ simple_gemac/simple_gemac.v \ simple_gemac/simple_gemac_wb.v \ simple_gemac/simple_gemac_tx.v \ @@ -103,11 +115,15 @@ control_lib/newfifo/buffer_pool.v \ control_lib/newfifo/fifo_2clock.v \ control_lib/newfifo/fifo_2clock_cascade.v \ control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo19_to_ll8.v \ +control_lib/newfifo/ll8_to_fifo19.v \ +control_lib/newfifo/fifo36_to_fifo19.v \ +control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ @@ -117,6 +133,10 @@ coregen/fifo_xlnx_512x36_2clk.v \ coregen/fifo_xlnx_512x36_2clk.xco \ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ +coregen/fifo_xlnx_16x19_2clk.v \ +coregen/fifo_xlnx_16x19_2clk.xco \ +coregen/fifo_xlnx_16x40_2clk.v \ +coregen/fifo_xlnx_16x40_2clk.xco \ extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ @@ -132,7 +152,6 @@ opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ opencores/i2c/rtl/verilog/i2c_master_defines.v \ opencores/i2c/rtl/verilog/i2c_master_top.v \ opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ opencores/spi/rtl/verilog/spi_clgen.v \ opencores/spi/rtl/verilog/spi_defines.v \ opencores/spi/rtl/verilog/spi_shift.v \ @@ -170,10 +189,13 @@ serdes/serdes_fc_rx.v \ serdes/serdes_fc_tx.v \ serdes/serdes_rx.v \ serdes/serdes_tx.v \ +timing/time_64bit.v \ +timing/time_compare.v \ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ +timing/simple_timer.v \ top/u2_core/u2_core.v \ top/u2plus/capture_ddrlvds.v \ top/u2plus/u2plus.ucf \ @@ -183,7 +205,7 @@ top/u2plus/u2plus.v # Process Properties ################################################## export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ +"Number of Clock Buffers" 8 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ "Optimize Instantiated Primitives" TRUE \ diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index 31404dda9..a3cd61906 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -399,3 +399,21 @@ NET "flash_cs" LOC = "AA7" ; #NET "unnamed_net11" LOC = "G7" ; # TDI #NET "unnamed_net10" LOC = "A25" ; # TCK #NET "unnamed_net20" LOC = "V20" ; # SUSPEND + + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; -- cgit v1.2.3 From 724af67a222aca01207cda9e0e4a8ce33217b7b8 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 8 Jun 2010 14:16:22 -0700 Subject: debug pins --- usrp2/gpmc/fifo_watcher.v | 4 +++- usrp2/gpmc/gpmc_async.v | 7 +++++-- usrp2/top/u1e/u1e_core.v | 3 ++- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index 4bba142b0..fe4e35de3 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -4,13 +4,15 @@ module fifo_watcher (input clk, input reset, input clear, input src_rdy1, input dst_rdy1, input sof1, input eof1, input src_rdy2, input dst_rdy2, input sof2, input eof2, - output reg have_packet, output [15:0] length, output reg bus_error); + output reg have_packet, output [15:0] length, output reg bus_error, + output [31:0] debug); wire write = src_rdy1 & dst_rdy1 & eof1; wire read = src_rdy2 & dst_rdy2 & eof2; wire have_packet_int; reg [15:0] counter; wire [4:0] pkt_count; + assign debug = pkt_count; fifo_short #(.WIDTH(16)) frame_lengths (.clk(clk), .reset(reset), .clear(clear), diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 1050cef7d..9f7b6dc4c 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -105,11 +105,14 @@ module gpmc_async .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), .frame_len(rx_frame_len) ); + wire [31:0] pkt_count; + fifo_watcher fifo_watcher (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), - .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) ); + .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx), + .debug(pkt_count)); // //////////////////////////////////////////// // Control path on CS6 @@ -122,6 +125,6 @@ module gpmc_async .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i) ); - assign debug = 0; + assign debug = pkt_count; endmodule // gpmc_async diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 6dae653ce..dde81df6b 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -430,6 +430,7 @@ module u1e_core assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, - {3'b0, bus_error, misc_gpio[11:0]} }; + {2'b0, bus_error, debug_gpmc[4:0] }, + {misc_gpio[7:0]} }; endmodule // u1e_core -- cgit v1.2.3 From c28838a4ecfc1b3051bb46cf28114eb85a8845c7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 8 Jun 2010 14:18:27 -0700 Subject: ignores --- usrp2/top/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/top/.gitignore b/usrp2/top/.gitignore index bf1b77066..0d90f1698 100644 --- a/usrp2/top/.gitignore +++ b/usrp2/top/.gitignore @@ -1 +1,2 @@ /*.sav +build* -- cgit v1.2.3 From fb704918b285a7d039cda27daf35f628442a7dca Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 9 Jun 2010 18:25:35 -0700 Subject: actually generates an image --- usrp2/top/u2plus/Makefile | 6 +++--- usrp2/top/u2plus/u2plus.ucf | 3 --- usrp2/top/u2plus/u2plus.v | 17 ++++++----------- 3 files changed, 9 insertions(+), 17 deletions(-) diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile index 29928e03e..777a03662 100644 --- a/usrp2/top/u2plus/Makefile +++ b/usrp2/top/u2plus/Makefile @@ -29,7 +29,7 @@ ISE_HELPER := ../tcl/ise_helper.tcl ################################################## # Project Setup ################################################## -BUILD_DIR := build/ +BUILD_DIR := build$(ISE)/ export TOP_MODULE := u2plus export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise @@ -172,7 +172,7 @@ sdr_lib/clip_reg.v \ sdr_lib/cordic.v \ sdr_lib/cordic_z24.v \ sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_rx_udp.v \ sdr_lib/dsp_core_tx.v \ sdr_lib/hb_dec.v \ sdr_lib/hb_interp.v \ @@ -196,7 +196,7 @@ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ timing/simple_timer.v \ -top/u2_core/u2_core.v \ +top/u2plus/u2plus_core.v \ top/u2plus/capture_ddrlvds.v \ top/u2plus/u2plus.ucf \ top/u2plus/u2plus.v diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index a3cd61906..00838e19d 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -407,9 +407,6 @@ TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; -NET "cpld_clk" TNM_NET = "cpld_clk"; -TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; - NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index fef23af60..13c7a811f 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -286,7 +286,7 @@ module u2plus .S(0) // Synchronous preset input ); */ - u2_core u2_core(.dsp_clk (dsp_clk), + u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), .clk_to_mac (clk_to_mac), @@ -323,12 +323,6 @@ module u2plus .ser_r (ser_r_int[15:0]), .ser_rklsb (ser_rklsb_int), .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), .adc_a (adc_a[13:0]), .adc_ovf_a (adc_ovf_a), .adc_on_a (adc_on_a), @@ -374,13 +368,14 @@ module u2plus .uart_rx_i (uart_rx_i), .uart_baud_o (), .sim_mode (1'b0), - .clock_divider (2) + .clock_divider (2), + .spiflash_cs (flash_cs), + .spiflash_clk (flash_clk), + .spiflash_miso (flash_miso), + .spiflash_mosi (flash_mosi) ); assign RAM_ZZ = 1; - assign flash_clk = 0; - assign flash_cs = 1; - assign flash_mosi = 0; assign RAM_BWn = 4'b1111; assign TXD = 3'b111; -- cgit v1.2.3 From aefcb65e7788a9fbb50b443dbd3f248e2d462107 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 12:03:45 -0700 Subject: proper overrun, underrun connections, debug pins. --- usrp2/top/u1e/u1e_core.v | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index dde81df6b..a6654906b 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -96,6 +96,9 @@ module u1e_core (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + assign tx_underrun = 0; + assign rx_overrun = 0; `endif // LOOPBACK `ifdef TIMED @@ -151,7 +154,7 @@ module u1e_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(wb_clk), .reset(wb_rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(overrun), + .vita_time(vita_time), .overrun(rx_overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); @@ -183,7 +186,7 @@ module u1e_core vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control (.clk(wb_clk), .reset(wb_rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.underrun(underrun), + .vita_time(vita_time),.underrun(tx_underrun), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_vtc) ); @@ -326,7 +329,6 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - //assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : @@ -426,7 +428,9 @@ module u1e_core //assign debug = { phase[23:8], txsync, txblank, tx }; - assign debug_gpio_0 = { debug_gpmc }; + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, rx_i[11:0]}, + {rx1_src_rdy, rx1_dst_rdy, rx_src_rdy, rx_dst_rdy, rx_q[11:0]} }; + assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, -- cgit v1.2.3 From 7d067d0109d4ee484a65caabcaf173082719f0d4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 12:19:41 -0700 Subject: left something out of the sensitivity list. --- usrp2/control_lib/nsgpio16LE.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v index 514b003ce..8aef0c7ae 100644 --- a/usrp2/control_lib/nsgpio16LE.v +++ b/usrp2/control_lib/nsgpio16LE.v @@ -111,7 +111,7 @@ module nsgpio16LE integer n; reg [31:0] igpio; // temporary internal signal - always @(ctrl or line or debug_1 or debug_0 or atr or ddr) + always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg) for(n=0;n<32;n=n+1) igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : (ctrl[n] ? atr[n] : line[n]) ) -- cgit v1.2.3 From b38a1db20233e6d23ffce831c38d67a500e87b51 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 14:50:32 -0700 Subject: much bigger fifos --- usrp2/top/u1e/u1e_core.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index a6654906b..8db995b17 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -25,8 +25,8 @@ module u1e_core input [11:0] misc_gpio, input pps_in ); - localparam TXFIFOSIZE = 11; - localparam RXFIFOSIZE = 11; + localparam TXFIFOSIZE = 13; + localparam RXFIFOSIZE = 13; localparam SR_RX_DSP = 0; // 5 regs localparam SR_RX_CTRL = 8; // 9 regs -- cgit v1.2.3 From a4b11332ab4f6a24bf4645c0b2770f9578a36f45 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 15:45:58 -0700 Subject: debug pins --- usrp2/top/u1e/u1e_core.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 8db995b17..64173ef2d 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -428,13 +428,16 @@ module u1e_core //assign debug = { phase[23:8], txsync, txblank, tx }; - assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, rx_i[11:0]}, - {rx1_src_rdy, rx1_dst_rdy, rx_src_rdy, rx_dst_rdy, rx_q[11:0]} }; + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, + {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; + + assign debug_gpio_1 = debug_vtd | debug_vtc; +/* assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, {2'b0, bus_error, debug_gpmc[4:0] }, {misc_gpio[7:0]} }; - + */ endmodule // u1e_core -- cgit v1.2.3 From 6c7c7e964ea9142c79f826b4407635760e6f01c5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 14 Jun 2010 12:14:23 -0700 Subject: build using new build system --- usrp2/top/u2plus/Makefile | 239 +++++++--------------------------------------- 1 file changed, 34 insertions(+), 205 deletions(-) diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile index 777a03662..23eb8908e 100644 --- a/usrp2/top/u2plus/Makefile +++ b/usrp2/top/u2plus/Makefile @@ -1,37 +1,29 @@ # # Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# +# ################################################## -# xtclsh Shell and tcl Script Path +# Project Setup ################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)) ################################################## -# Project Setup +# Include other makefiles ################################################## -BUILD_DIR := build$(ISE)/ -export TOP_MODULE := u2plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs ################################################## # Project Properties @@ -51,160 +43,20 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## # Sources ################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/settings_bus_crossclock.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -control_lib/priority_enc.v \ -control_lib/pic.v \ -vrt/vita_rx_control.v \ -vrt/vita_rx_framer.v \ -vrt/vita_tx_control.v \ -vrt/vita_tx_deframer.v \ -udp/udp_wrapper.v \ -udp/fifo19_rxrealign.v \ -udp/prot_eng_tx.v \ -udp/add_onescomp.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac_wrapper19.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo19_to_ll8.v \ -control_lib/newfifo/ll8_to_fifo19.v \ -control_lib/newfifo/fifo36_to_fifo19.v \ -control_lib/newfifo/fifo19_to_fifo36.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -coregen/fifo_xlnx_16x19_2clk.v \ -coregen/fifo_xlnx_16x19_2clk.xco \ -coregen/fifo_xlnx_16x40_2clk.v \ -coregen/fifo_xlnx_16x40_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx_udp.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_64bit.v \ -timing/time_compare.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -timing/simple_timer.v \ -top/u2plus/u2plus_core.v \ -top/u2plus/capture_ddrlvds.v \ -top/u2plus/u2plus.ucf \ -top/u2plus/u2plus.v +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) ################################################## # Process Properties ################################################## -export SYNTHESIZE_PROPERTIES := \ +SYNTHESIZE_PROPERTIES = \ "Number of Clock Buffers" 8 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ @@ -214,10 +66,10 @@ export SYNTHESIZE_PROPERTIES := \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto -export TRANSLATE_PROPERTIES := \ +TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" -export MAP_PROPERTIES := \ +MAP_PROPERTIES = \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ @@ -228,41 +80,18 @@ export MAP_PROPERTIES := \ "Combinatorial Logic Optimization" TRUE \ "Register Duplication" TRUE -export PLACE_ROUTE_PROPERTIES := \ +PLACE_ROUTE_PROPERTIES = \ "Place & Route Effort Level (Overall)" High -export STATIC_TIMING_PROPERTIES := \ +STATIC_TIMING_PROPERTIES = \ "Number of Paths in Error/Verbose Report" 10 \ "Report Type" "Error Report" -export GEN_PROG_FILE_PROPERTIES := \ +GEN_PROG_FILE_PROPERTIES = \ "Configuration Rate" 6 \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ "Enable Outputs (Output Events)" 6 -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - +SIM_MODEL_PROPERTIES = "" -- cgit v1.2.3 From afbcdb33f31a90fbdec08ecef98c9680f2bfa940 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 14 Jun 2010 12:15:58 -0700 Subject: new core for u2p, based on u2_core --- usrp2/top/u2plus/u2plus_core.v | 856 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 856 insertions(+) create mode 100644 usrp2/top/u2plus/u2plus_core.v diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v new file mode 100644 index 000000000..d4b138c54 --- /dev/null +++ b/usrp2/top/u2plus/u2plus_core.v @@ -0,0 +1,856 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2plus_core + #(parameter RAM_SIZE=32768) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + inout [35:0] RAM_D, + output [20:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider, + + output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi + ); + + localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_UDP_SM = 96; // 64 regs + localparam SR_RX_DSP = 160; // 16 + localparam SR_RX_CTRL = 176; // 16 + localparam SR_TIME64 = 192; // 3 + localparam SR_SIMTIMER = 198; // 2 + localparam SR_TX_DSP = 208; // 16 + localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), + // Read Interfaces + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + ); + + wire [31:0] status_enc; + priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + wire [35:0] udp_tx_data, udp_rx_data; + wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; + + udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), + .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), + .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), + .debug(debug_udp) ); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {clk_status,serdes_link_up}; + + setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {8'b0}, + {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + /* + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + */ + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + // Not used anymore + assign sd_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + wire [31:0] vrc_debug; + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); + + wire [3:0] vita_state; + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), + .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire [99:0] tx1_data; + wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; + + wire [31:0] debug_vtc, debug_vtd, debug_vt; + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + assign debug_vt = debug_vtc | debug_vtd; + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(dac_a),.dac_b(dac_b), + .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // External RAM Interface + + /* + localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes + + wire [15:0] bus2ram, ram2bus; + wire [15:0] bridge_adr; + wire [1:0] bridge_sel; + wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; + + wire [19:0] page; + wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; + setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(page),.changed()); + + wb_bridge_16_32 bridge + (.wb_clk(wb_clk),.wb_rst(wb_rst), + .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), + .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), + .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), + .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); + + wb_zbt16_b wb_zbt16_b + (.clk(wb_clk),.rst(wb_rst), + .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), + .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), + .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), + .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), + .sram_mode(),.sram_zz() ); + + assign RAM_CE1n = 0; + assign RAM_D[17:16] = 2'bzz; + */ + + // ///////////////////////////////////////////////////////////////////////// + // SPI for Flash -- Slave #2 + spi_top flash_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(sf_adr[4:0]),.wb_dat_i(sf_dat_o), + .wb_dat_o(sf_dat_i),.wb_sel_i(sf_sel),.wb_we_i(sf_we),.wb_stb_i(sf_stb), + .wb_cyc_i(sf_cyc),.wb_ack_o(sf_ack),.wb_err_o(sf_err),.wb_int_o(spiflash_int), + .ss_pad_o(spiflash_cs), + .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core + +/* + // FIFO Level Debugging + reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; + + always @(posedge dsp_clk) + serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, + {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; + + assign debug_clk[0] = GMII_RX_CLK; // wb_clk; + assign debug_clk[1] = dsp_clk; +*/ +/* + + wire mdio_cpy = MDIO; + assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, + { s6_adr[15:8] }, + { s6_adr[7:0] }, + { 6'd0, mdio_cpy, MDC } }; +*/ +/* + assign debug = { { GMII_TXD }, + { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, + { wr2_flags, rd2_flags }, + { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + assign debug = { { GMII_RXD }, + { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { wr2_flags, rd2_flags }, + { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + */ + +// assign debug = debug_udp; + // assign debug = vrc_debug; +/* + assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, + {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, + {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , + {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; +*/ +// assign debug_gpio_1 = {vita_time[63:32] }; + +/* + assign debug_gpio_1 = { { tx_f19_data[15:8] }, + { tx_f19_data[7:0] }, + { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, + { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; + */ + +// wire debug_mux; +// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), +// .in(set_data),.out(debug_mux),.changed()); + +//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; +//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; + +//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, +// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; + +//assign debug = debug_tx_dsp; +//assign debug = debug_serdes0; + +//assign debug_gpio_0 = 0; //debug_serdes0; +//assign debug_gpio_1 = 0; //debug_serdes1; + +// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, +// {8'b0}, +// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, +// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; + +//assign debug = {dac_a,dac_b}; + +/* + assign debug = {{ram_loader_done, takeover, 6'd0}, + {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, + {8'd0}, + {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ + +/*assign debug = host_to_dsp_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; + */ +// Assign various commonly used debug buses. +/* + wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, + irq[7:0], + GMII_RXD, + GMII_TXD}; + + wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; + + wire [31:0] debug_time = {uart_tx_o, 7'b0, + irq[7:0], + 6'b0, GMII_RX_DV, GMII_TX_EN, + 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; + + wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, + irq[7:0], + proc_int, 7'b0 }; + + wire [31:0] debug_eth = + {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, + {8'd0}, + {8'd0}, + {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; + + assign debug_serdes0 = { { rd0_dat[7:0] }, + { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, + { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, + { ser_r[15:8] }, + { ser_r[7:0] } }; + + assign debug_gpio_1 = {uart_tx_o,7'd0, + 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, + debug_txc[15:0]}; + assign debug_gpio_1 = debug_rx; + assign debug_gpio_1 = debug_serdes1; + assign debug_gpio_1 = debug_eth; + + */ + -- cgit v1.2.3 From 55e0d893e8a596e18c9eeb34e6f518e03c26dd80 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 17 Jun 2010 13:59:51 -0700 Subject: added ability to clear out fifos of tx and rx. --- usrp2/gpmc/gpmc_async.v | 22 +++++++++++----------- usrp2/gpmc/gpmc_to_fifo_async.v | 10 +++++----- usrp2/top/u1e/u1e_core.v | 33 +++++++++++++++++++++------------ 3 files changed, 37 insertions(+), 28 deletions(-) diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 9f7b6dc4c..23bad56ae 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -16,7 +16,7 @@ module gpmc_async output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, // FIFO interface - input fifo_clk, input fifo_rst, + input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, @@ -34,7 +34,7 @@ module gpmc_async wire bus_error_tx, bus_error_rx; always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear_tx | clear_rx) bus_error <= 0; else bus_error <= bus_error_tx | bus_error_rx; @@ -54,23 +54,23 @@ module gpmc_async gpmc_to_fifo_async gpmc_to_fifo_async (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx), .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), .bus_error(bus_error_tx) ); fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); @@ -85,22 +85,22 @@ module gpmc_async wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); fifo_to_gpmc_async fifo_to_gpmc_async - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), .frame_len(rx_frame_len) ); @@ -108,7 +108,7 @@ module gpmc_async wire [31:0] pkt_count; fifo_watcher fifo_watcher - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx), diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 3d29745a2..55c0cef50 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -2,7 +2,7 @@ module gpmc_to_fifo_async (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, - input fifo_clk, input fifo_rst, + input fifo_clk, input fifo_rst, input clear, output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready, @@ -37,7 +37,7 @@ module gpmc_to_fifo_async end always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear) src_rdy_o <= 0; else if(do_write) src_rdy_o <= 1; @@ -45,7 +45,7 @@ module gpmc_to_fifo_async src_rdy_o <= 0; // Assume it was taken always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear) counter <= 0; else if(do_write) if(last_write) @@ -54,13 +54,13 @@ module gpmc_to_fifo_async counter <= counter + 1; always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear) fifo_ready <= 0; else fifo_ready <= /* first_write & */ (fifo_space > 16'd1023); always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear) bus_error <= 0; else if(src_rdy_o & ~dst_rdy_i) bus_error <= 1; diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 64173ef2d..787bf016c 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -28,10 +28,11 @@ module u1e_core localparam TXFIFOSIZE = 13; localparam RXFIFOSIZE = 13; - localparam SR_RX_DSP = 0; // 5 regs - localparam SR_RX_CTRL = 8; // 9 regs - localparam SR_TX_DSP = 17; // 5 regs - localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_RX_DSP = 0; // 5 regs + localparam SR_CLEAR_FIFO = 6; // 1 reg + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs localparam SR_TIME64 = 28; // 4 regs wire wb_clk = clk_fpga; @@ -65,6 +66,14 @@ module u1e_core wire [7:0] rate; wire bus_error; + + wire clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear; + + setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear)); + assign clear_tx = clear_tx_int & do_clear; + assign clear_rx = clear_rx_int & do_clear; gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) gpmc (.arst(wb_rst), @@ -80,7 +89,7 @@ module u1e_core .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), .wb_ack_i(m0_ack), - .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), @@ -93,7 +102,7 @@ module u1e_core `ifdef LOOPBACK fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); @@ -113,7 +122,7 @@ module u1e_core .underrun(tx_underrun), .overrun()); packet_verifier32 pktver32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); @@ -121,7 +130,7 @@ module u1e_core wire rx_enable; packet_generator32 pktgen32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); fifo_pacer rx_pacer @@ -152,7 +161,7 @@ module u1e_core .debug(debug_rx_dsp) ); vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), @@ -160,7 +169,7 @@ module u1e_core .debug_rx(vrc_debug)); vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), @@ -177,14 +186,14 @@ module u1e_core wire run_tx; vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), .debug(debug_vtd) ); vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time),.underrun(tx_underrun), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), -- cgit v1.2.3 From c3ef4c04fd8d887a733fa9a8ed5b6702cf453a01 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 9 Jul 2010 14:20:30 -0700 Subject: point to new location for fifos --- usrp2/vrt/vita_rx.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build index f6d2d75a3..010d1be6e 100755 --- a/usrp2/vrt/vita_rx.build +++ b/usrp2/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v -- cgit v1.2.3 From dcdc873e90d8fbd79127d0a69783834339768467 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Jul 2010 13:23:48 -0700 Subject: updated to ise12 fixes from main development line --- usrp2/top/u2plus/u2plus_core.v | 44 +++++++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index d4b138c54..7b8cbb1bb 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -252,33 +252,33 @@ module u2plus_core // /////////////////////////////////////////////////////////////////// // RAM Loader - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; + wire [31:0] ram_loader_dat, if_dat; + wire [15:0] ram_loader_adr; + wire [14:0] if_adr; wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire ram_loader_stb, ram_loader_we; wire iwb_ack, iwb_stb; ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), + .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), + .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), + .wb_we(ram_loader_we), + .ram_loader_done(ram_loader_done), // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - + .cpld_clk(cpld_clk), + .cpld_din(cpld_din), + .cpld_start(cpld_start_int), + .cpld_mode(cpld_mode_int), + .cpld_done(cpld_done_int), + .cpld_detached(cpld_detached)); + // ///////////////////////////////////////////////////////////////////////// // Processor aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + .if_adr(if_adr), + .if_dat(if_dat), // Data Wishbone bus to system bus fabric .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), @@ -292,16 +292,16 @@ module u2plus_core // I-port connects directly to processor and ram loader wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + .if_adr(if_adr), + .if_data(if_dat), .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), -- cgit v1.2.3 From 41e7903589e4d47e82a3c49c738065a516204deb Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Jul 2010 15:05:35 -0700 Subject: remove ram loader --- usrp2/top/u2plus/u2plus_core.v | 37 ++++++++----------------------------- 1 file changed, 8 insertions(+), 29 deletions(-) diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 7b8cbb1bb..2b5ea4295 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -151,8 +151,7 @@ module u2plus_core wire [31:0] set_data, set_data_dsp; wire set_stb, set_stb_dsp; - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; + wire wb_rst, dsp_rst; wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; @@ -249,31 +248,11 @@ module u2plus_core ////////////////////////////////////////////////////////////////////////////////////////// // Reset Controller - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, if_dat; - wire [15:0] ram_loader_adr; - wire [14:0] if_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), - .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), - .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), - .wb_we(ram_loader_we), - .ram_loader_done(ram_loader_done), - // CPLD Interface - .cpld_clk(cpld_clk), - .cpld_din(cpld_din), - .cpld_start(cpld_start_int), - .cpld_mode(cpld_mode_int), - .cpld_done(cpld_done_int), - .cpld_detached(cpld_detached)); - // ///////////////////////////////////////////////////////////////////////// // Processor + wire [31:0] if_dat; + wire [14:0] if_adr; + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), // Instruction Wishbone bus to I-RAM @@ -295,10 +274,10 @@ module u2plus_core ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), - .ram_loader_done_i(ram_loader_done), + .ram_loader_adr_i(0), .ram_loader_dat_i(0), + .ram_loader_stb_i(0), .ram_loader_sel_i(0), + .ram_loader_we_i(0), + .ram_loader_done_i(1'b1), .if_adr(if_adr), .if_data(if_dat), -- cgit v1.2.3 From 825a9a04890017c24e561c39268157dbd4ef6adc Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Jul 2010 16:04:40 -0700 Subject: copied from quad radio --- usrp2/control_lib/v5icap_wb.v | 54 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 usrp2/control_lib/v5icap_wb.v diff --git a/usrp2/control_lib/v5icap_wb.v b/usrp2/control_lib/v5icap_wb.v new file mode 100644 index 000000000..c8800285a --- /dev/null +++ b/usrp2/control_lib/v5icap_wb.v @@ -0,0 +1,54 @@ + + +module v5icap_wb + (input clk, input reset, + input cyc_i, input stb_i, input we_i, output ack_o, + input [31:0] dat_i, output [31:0] dat_o); + + wire BUSY, CE, WRITE; + + reg [2:0] icap_state; + localparam ICAP_IDLE = 0; + localparam ICAP_WR0 = 1; + localparam ICAP_WR1 = 2; + localparam ICAP_RD0 = 3; + localparam ICAP_RD1 = 4; + + always @(posedge clk) + if(reset) + icap_state <= ICAP_IDLE; + else + case(icap_state) + ICAP_IDLE : + begin + if(stb_i & cyc_i) + if(we_i) + icap_state <= ICAP_WR0; + else + icap_state <= ICAP_RD0; + end + ICAP_WR0 : + icap_state <= ICAP_WR1; + ICAP_WR1 : + icap_state <= ICAP_IDLE; + ICAP_RD0 : + icap_state <= ICAP_RD1; + ICAP_RD1 : + icap_state <= ICAP_IDLE; + endcase // case (icap_state) + + assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1); + assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0); + + assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1); + + ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst + (.BUSY(BUSY), // Busy output + .O(dat_o), // 32-bit data output + .CE(~CE), // Clock enable input + .CLK(clk), // Clock input + .I(dat_i), // 32-bit data input + .WRITE(~WRITE) // Write input + ); + +endmodule // v5icap_wb -- cgit v1.2.3 From ed682e09b55a4f587077665e3ee62ecc7053ff53 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Jul 2010 16:10:12 -0700 Subject: very slight mods from v5 version --- usrp2/control_lib/s3a_icap_wb.v | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 usrp2/control_lib/s3a_icap_wb.v diff --git a/usrp2/control_lib/s3a_icap_wb.v b/usrp2/control_lib/s3a_icap_wb.v new file mode 100644 index 000000000..9a9db0f96 --- /dev/null +++ b/usrp2/control_lib/s3a_icap_wb.v @@ -0,0 +1,56 @@ + + +module s3a_icap_wb + (input clk, input reset, + input cyc_i, input stb_i, input we_i, output ack_o, + input [31:0] dat_i, output [31:0] dat_o); + + assign dat_o[31:8] = 24'd0; + + wire BUSY, CE, WRITE; + + reg [2:0] icap_state; + localparam ICAP_IDLE = 0; + localparam ICAP_WR0 = 1; + localparam ICAP_WR1 = 2; + localparam ICAP_RD0 = 3; + localparam ICAP_RD1 = 4; + + always @(posedge clk) + if(reset) + icap_state <= ICAP_IDLE; + else + case(icap_state) + ICAP_IDLE : + begin + if(stb_i & cyc_i) + if(we_i) + icap_state <= ICAP_WR0; + else + icap_state <= ICAP_RD0; + end + ICAP_WR0 : + icap_state <= ICAP_WR1; + ICAP_WR1 : + icap_state <= ICAP_IDLE; + ICAP_RD0 : + icap_state <= ICAP_RD1; + ICAP_RD1 : + icap_state <= ICAP_IDLE; + endcase // case (icap_state) + + assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1); + assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0); + + assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1); + + ICAP_SPARTAN3A ICAP_SPARTAN3A_inst + (.BUSY(BUSY), // Busy output + .O(dat_o[7:0]), // 32-bit data output + .CE(~CE), // Clock enable input + .CLK(clk), // Clock input + .I(dat_i[7:0]), // 32-bit data input + .WRITE(~WRITE) // Write input + ); + +endmodule // s3a_icap_wb -- cgit v1.2.3 From c9343570f681a042beb0cf231ddcfff950228095 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Jul 2010 16:28:19 -0700 Subject: ram_harvard2 is a workaround for a Xilinx bug that gets confused by an unused write port on a ram --- usrp2/control_lib/Makefile.srcs | 2 ++ usrp2/control_lib/ram_harvard2.v | 77 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) create mode 100644 usrp2/control_lib/ram_harvard2.v diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs index bc8e4d5bc..60fb2516d 100644 --- a/usrp2/control_lib/Makefile.srcs +++ b/usrp2/control_lib/Makefile.srcs @@ -21,6 +21,7 @@ nsgpio.v \ ram_2port.v \ ram_harv_cache.v \ ram_harvard.v \ +ram_harvard2.v \ ram_loader.v \ setting_reg.v \ settings_bus.v \ @@ -42,4 +43,5 @@ pic.v \ longfifo.v \ shortfifo.v \ medfifo.v \ +s3a_icap_wb.v \ )) diff --git a/usrp2/control_lib/ram_harvard2.v b/usrp2/control_lib/ram_harvard2.v new file mode 100644 index 000000000..67777af2a --- /dev/null +++ b/usrp2/control_lib/ram_harvard2.v @@ -0,0 +1,77 @@ + + +// Dual ported, Harvard architecture + +module ram_harvard2 + #(parameter AWIDTH=15, + parameter RAM_SIZE=32768) + (input wb_clk_i, + input wb_rst_i, + // Instruction fetch port. + input [AWIDTH-1:0] if_adr, + output reg [31:0] if_data, + // Data access port. + input [AWIDTH-1:0] dwb_adr_i, + input [31:0] dwb_dat_i, + output reg [31:0] dwb_dat_o, + input dwb_we_i, + output dwb_ack_o, + input dwb_stb_i, + input [3:0] dwb_sel_i); + + reg ack_d1; + reg stb_d1; + + assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1)); + + always @(posedge wb_clk_i) + if(wb_rst_i) + ack_d1 <= 1'b0; + else + ack_d1 <= dwb_ack_o; + + always @(posedge wb_clk_i) + if(wb_rst_i) + stb_d1 <= 0; + else + stb_d1 <= dwb_stb_i; + + reg [7:0] ram0 [0:(RAM_SIZE/4)-1]; + reg [7:0] ram1 [0:(RAM_SIZE/4)-1]; + reg [7:0] ram2 [0:(RAM_SIZE/4)-1]; + reg [7:0] ram3 [0:(RAM_SIZE/4)-1]; + + // Port 1, Read only + always @(posedge wb_clk_i) + if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]]; + + // Port 2, R/W + always @(posedge wb_clk_i) + if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]]; + + always @(posedge wb_clk_i) + if(dwb_we_i & dwb_stb_i & dwb_sel_i[3]) + ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24]; + always @(posedge wb_clk_i) + if(dwb_we_i & dwb_stb_i & dwb_sel_i[2]) + ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16]; + always @(posedge wb_clk_i) + if(dwb_we_i & dwb_stb_i & dwb_sel_i[1]) + ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8]; + always @(posedge wb_clk_i) + if(dwb_we_i & dwb_stb_i & dwb_sel_i[0]) + ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0]; + +endmodule // ram_harvard -- cgit v1.2.3 From 864096d9b717a557b9d84d562b0803bc491313c8 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Jul 2010 16:35:57 -0700 Subject: further cleanup --- usrp2/top/u2plus/u2plus.v | 6 +- usrp2/top/u2plus/u2plus_core.v | 237 +++++------------------------------------ 2 files changed, 27 insertions(+), 216 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 13c7a811f..32dfb0331 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -364,8 +364,8 @@ module u2plus .RAM_WEn (RAM_WEn), .RAM_OEn (RAM_OEn), .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), + .uart_tx_o (TXD[0]), + .uart_rx_i (RXD[0]), .uart_baud_o (), .sim_mode (1'b0), .clock_divider (2), @@ -377,6 +377,6 @@ module u2plus assign RAM_ZZ = 1; assign RAM_BWn = 4'b1111; - assign TXD = 3'b111; + assign TXD[2:1] = 2'b11; endmodule // u2plus diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 2b5ea4295..d49c461cb 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -268,27 +268,15 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader + // I-port connects directly to processor wire flush_icache; - ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(0), .ram_loader_dat_i(0), - .ram_loader_stb_i(0), .ram_loader_sel_i(0), - .ram_loader_we_i(0), - .ram_loader_done_i(1'b1), - - .if_adr(if_adr), - .if_data(if_dat), - + ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .if_adr(if_adr), .if_data(if_dat), .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - // ///////////////////////////////////////////////////////////////////////// // Buffer Pool, slave #1 wire rd0_ready_i, rd0_ready_o; @@ -486,14 +474,6 @@ module u2plus_core // Master Timer, Slave #9 // No longer used, replaced with simple_timer below - /* - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - */ assign s9_ack = 0; // ///////////////////////////////////////////////////////////////////////// @@ -535,11 +515,26 @@ module u2plus_core assign sc_ack = 0; // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 + // ICAP for reprogramming the FPGA, Slave #13 (D) + + s3a_icap_wb s3a_icap_wb + (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), + .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); + + // ///////////////////////////////////////////////////////////////////////// + // Unused -- Slave #14 (E) + + assign se_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // SPI for Flash -- Slave #15 (F) + spi_top flash_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(sf_adr[4:0]),.wb_dat_i(sf_dat_o), + .wb_dat_o(sf_dat_i),.wb_sel_i(sf_sel),.wb_we_i(sf_we),.wb_stb_i(sf_stb), + .wb_cyc_i(sf_cyc),.wb_ack_o(sf_ack),.wb_err_o(sf_err),.wb_int_o(spiflash_int), + .ss_pad_o(spiflash_cs), + .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); - // Not used anymore - assign sd_ack = 0; - // ///////////////////////////////////////////////////////////////////////// // DSP RX wire [31:0] sample_rx, sample_tx; @@ -633,50 +628,6 @@ module u2plus_core .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - /* - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), - .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; - */ - - // ///////////////////////////////////////////////////////////////////////// - // SPI for Flash -- Slave #2 - spi_top flash_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(sf_adr[4:0]),.wb_dat_i(sf_dat_o), - .wb_dat_o(sf_dat_i),.wb_sel_i(sf_sel),.wb_we_i(sf_we),.wb_stb_i(sf_stb), - .wb_cyc_i(sf_cyc),.wb_ack_o(sf_ack),.wb_err_o(sf_err),.wb_int_o(spiflash_int), - .ss_pad_o(spiflash_cs), - .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); - // ///////////////////////////////////////////////////////////////////////// // VITA Timing @@ -693,143 +644,3 @@ module u2plus_core assign debug_gpio_1 = 32'd0; endmodule // u2_core - -/* - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = GMII_RX_CLK; // wb_clk; - assign debug_clk[1] = dsp_clk; -*/ -/* - - wire mdio_cpy = MDIO; - assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, - { s6_adr[15:8] }, - { s6_adr[7:0] }, - { 6'd0, mdio_cpy, MDC } }; -*/ -/* - assign debug = { { GMII_TXD }, - { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, - { wr2_flags, rd2_flags }, - { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - assign debug = { { GMII_RXD }, - { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, - { wr2_flags, rd2_flags }, - { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - */ - -// assign debug = debug_udp; - // assign debug = vrc_debug; -/* - assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, - {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, - {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , - {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; -*/ -// assign debug_gpio_1 = {vita_time[63:32] }; - -/* - assign debug_gpio_1 = { { tx_f19_data[15:8] }, - { tx_f19_data[7:0] }, - { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, - { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; - */ - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - -- cgit v1.2.3 From 8bac5fc488db2123b5ac713c52bbaa01b616e0eb Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 13 Jul 2010 11:50:54 -0700 Subject: separate boot ram, redone memory map, connected uart --- usrp2/control_lib/Makefile.srcs | 1 + usrp2/control_lib/bootram.v | 246 ++++++++++++++++++++++++ usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v | 4 +- usrp2/top/u2plus/u2plus.v | 6 +- usrp2/top/u2plus/u2plus_core.v | 72 +++---- 5 files changed, 289 insertions(+), 40 deletions(-) create mode 100644 usrp2/control_lib/bootram.v diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs index 60fb2516d..ad491b83d 100644 --- a/usrp2/control_lib/Makefile.srcs +++ b/usrp2/control_lib/Makefile.srcs @@ -44,4 +44,5 @@ longfifo.v \ shortfifo.v \ medfifo.v \ s3a_icap_wb.v \ +bootram.v \ )) diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v new file mode 100644 index 000000000..648ccc9ed --- /dev/null +++ b/usrp2/control_lib/bootram.v @@ -0,0 +1,246 @@ + +// Boot RAM for S3A, 8KB, dual port + +// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM +// Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1 + +module bootram + (input clk, + input [12:0] if_adr, + output [31:0] if_data, + + input [12:0] dwb_adr_i, + input [31:0] dwb_dat_i, + output [31:0] dwb_dat_o, + input dwb_we_i, + output reg dwb_ack_o, + input dwb_stb_i, + input [3:0] dwb_sel_i); + + wire [31:0] DOA0, DOA1, DOA2, DOA3; + wire [31:0] DOB0, DOB1, DOB2, DOB3; + wire ENB0, ENB1, ENB2, ENB3; + wire [3:0] WEB; + + assign if_data = if_adr[12] ? (if_adr[11] ? DOA3 : DOA2) : (if_adr[11] ? DOA1 : DOA0); + assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOA3 : DOA2) : (dwb_adr_i[11] ? DOA1 : DOA0); + + always @(posedge clk) + if(dwb_stb_i & ~dwb_ack_o) + dwb_ack_o <= 1; + else + dwb_ack_o <= 0; + + assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00); + assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01); + assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10); + assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11); + + assign WEB = {4{dwb_we_i}} & dwb_sel_i; + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM0 + (.DOA(DOA0), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB0), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB0), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM1 + (.DOA(DOA1), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB1), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB1), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM2 + (.DOA(DOA2), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB2), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB2), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM3 + (.DOA(DOA3), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB3), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB3), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + +endmodule // bootram + +/* + // The following INIT_xx declarations specify the initial contents of the RAM + // Address 0 to 127 + .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + // Address 128 to 255 + .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + // Address 256 to 383 + .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + // Address 384 to 511 + .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + // The next set of INITP_xx are for the parity bits + // Address 0 to 127 + .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000), + // Address 128 to 255 + .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000), + // Address 256 to 383 + .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000), + // Address 384 to 511 + .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000) +*/ diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v index 38ca3a023..6c066d5d9 100644 --- a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v @@ -11,7 +11,7 @@ module aeMB_core_BE (input sys_clk_i, input sys_rst_i, // Instruction port - output [14:0] if_adr, + output [ISIZ-1:0] if_adr, input [31:0] if_dat, // Data port output dwb_we_o, @@ -34,7 +34,7 @@ module aeMB_core_BE assign dwb_cyc_o = dwb_stb_o; assign iwb_ack_i = 1'b1; - assign if_adr = iwb_adr_o[14:0]; + assign if_adr = iwb_adr_o[ISIZ-1:0]; assign iwb_dat_i = if_dat; // Note some "wishbone" instruction fetch signals pruned on external interface diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 32dfb0331..ac0f6bbd1 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -364,8 +364,8 @@ module u2plus .RAM_WEn (RAM_WEn), .RAM_OEn (RAM_OEn), .RAM_LDn (RAM_LDn), - .uart_tx_o (TXD[0]), - .uart_rx_i (RXD[0]), + .uart_tx_o (TXD[1]), + .uart_rx_i (RXD[1]), .uart_baud_o (), .sim_mode (1'b0), .clock_divider (2), @@ -377,6 +377,6 @@ module u2plus assign RAM_ZZ = 1; assign RAM_BWn = 4'b1111; - assign TXD[2:1] = 2'b11; + assign TXD[3:2] = 2'b11; endmodule // u2plus diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index d49c461cb..bf6bf8b3e 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -3,7 +3,6 @@ // //////////////////////////////////////////////////////////////////////////////// module u2plus_core - #(parameter RAM_SIZE=32768) (// Clocks input dsp_clk, input wb_clk, @@ -191,23 +190,23 @@ module u2plus_core wire m0_err, m0_rty; wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM + .s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool + .s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI + .s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C + .s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO + .s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback + .s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC + .s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K) + .s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC + .s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused + .sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART + .sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR + .sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused + .sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP + .se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash + .sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), @@ -251,7 +250,7 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // Processor wire [31:0] if_dat; - wire [14:0] if_adr; + wire [15:0] if_adr; aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), @@ -267,15 +266,23 @@ module u2plus_core assign bus_error = m0_err | m0_rty; // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone + // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone // I-port connects directly to processor - wire flush_icache; - ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .if_adr(if_adr), .if_data(if_dat), - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + wire [31:0] if_dat_boot, if_dat_main; + assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot; + + bootram bootram(.clk(wb_clk), + .if_adr(if_adr[12:0]), .if_data(if_dat_boot), + .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + + ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .if_adr(if_adr[14:0]), .if_data(if_dat_main), + .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool, slave #1 @@ -522,16 +529,11 @@ module u2plus_core .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); // ///////////////////////////////////////////////////////////////////////// - // Unused -- Slave #14 (E) - - assign se_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SPI for Flash -- Slave #15 (F) + // SPI for Flash -- Slave #14 (E) spi_top flash_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(sf_adr[4:0]),.wb_dat_i(sf_dat_o), - .wb_dat_o(sf_dat_i),.wb_sel_i(sf_sel),.wb_we_i(sf_we),.wb_stb_i(sf_stb), - .wb_cyc_i(sf_cyc),.wb_ack_o(sf_ack),.wb_err_o(sf_err),.wb_int_o(spiflash_int), + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), + .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), + .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), .ss_pad_o(spiflash_cs), .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); -- cgit v1.2.3 From 703c20be608b2a15ab68a6c15514facdeac527cc Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 13 Jul 2010 14:47:25 -0700 Subject: includes led blinker in bootram --- usrp2/top/u2plus/u2plus_core.v | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index bf6bf8b3e..601f1a1bb 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -277,7 +277,10 @@ module u2plus_core .if_adr(if_adr[12:0]), .if_data(if_dat_boot), .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - + +defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; +defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; + ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .if_adr(if_adr[14:0]), .if_data(if_dat_main), @@ -640,8 +643,9 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = 2'b00; - assign debug = 32'd0; + assign debug_clk = {dsp_clk, wb_clk}; + assign debug = if_dat; + assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; -- cgit v1.2.3 From ee7208f5ea0e3105c1a45d37cc7709a665dc07b2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 13 Jul 2010 20:24:25 -0700 Subject: attach the correct data port --- usrp2/control_lib/bootram.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index 648ccc9ed..00c604f20 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -23,14 +23,14 @@ module bootram wire [3:0] WEB; assign if_data = if_adr[12] ? (if_adr[11] ? DOA3 : DOA2) : (if_adr[11] ? DOA1 : DOA0); - assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOA3 : DOA2) : (dwb_adr_i[11] ? DOA1 : DOA0); + assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0); always @(posedge clk) - if(dwb_stb_i & ~dwb_ack_o) - dwb_ack_o <= 1; - else + if(reset) dwb_ack_o <= 0; - + else + dwb_ack_o <= dwb_stb_i & ~dwb_ack_o; + assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00); assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01); assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10); -- cgit v1.2.3 From eddfcda0a2c84edd4818836e812c6a95ea44cb99 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 13 Jul 2010 23:41:42 -0700 Subject: reset the ack signal --- usrp2/control_lib/bootram.v | 2 +- usrp2/top/u2plus/u2plus_core.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index 00c604f20..5e527de90 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -5,7 +5,7 @@ // Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1 module bootram - (input clk, + (input clk, input reset, input [12:0] if_adr, output [31:0] if_data, diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 601f1a1bb..0470e6e9e 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -273,7 +273,7 @@ module u2plus_core wire [31:0] if_dat_boot, if_dat_main; assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot; - bootram bootram(.clk(wb_clk), + bootram bootram(.clk(wb_clk), .reset(wb_rst), .if_adr(if_adr[12:0]), .if_data(if_dat_boot), .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); -- cgit v1.2.3 From 3ac97f05c32942ba06a88c39f5d16edd51ae6658 Mon Sep 17 00:00:00 2001 From: nick Date: Wed, 14 Jul 2010 09:35:40 -0700 Subject: just local commit before updating w/matt's fix --- usrp2/top/u2plus/u2plus_core.v | 50 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 601f1a1bb..579e946e8 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -278,8 +278,46 @@ module u2plus_core .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); -defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; -defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; +////blinkenlights v0.1 +//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; +//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; + +////ICAP test v0.1 +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b8080234_00000000_b8080348_00000000_b8080050; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8080350; +defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_304003f8_31a00430_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40198_80000000_b9f400cc; +defparam bootram.RAM0.INIT_04=256'he8830000_e8600400_80000000_99fc2000_f8600400_b8000044_bc030014_f9e10000; +defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a00428_bc030010_30600000_b0000000_30630004_be24ffec; +defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; +defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a00428_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a0042c_bc030014_30800000_b0000000_e860042c; +defparam bootram.RAM0.INIT_09=256'h06463800_20e00430_20c00430_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; +defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; +defparam bootram.RAM0.INIT_0B=256'hb9f401e4_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f81c; +defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4002c_20e00000_20c00000_80000000_b9f40224_80000000; +defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f401b0_80000000_b9f4022c; +defparam bootram.RAM0.INIT_0E=256'hbc32fff0_aa434b40_b000004c_30630001_80000000_10600000_a48500ff_10a00000; +defparam bootram.RAM0.INIT_0F=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; +defparam bootram.RAM0.INIT_10=256'hf8803500_30800012_f8603508_3060ffff_80000000_b9f4fe68_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_11=256'hf8610020_f9e10000_3021ffac_80000000_b60f0008_f860350c_f8a03504_30a0ffef; +defparam bootram.RAM0.INIT_12=256'hf9610040_f941003c_f9210038_f9010034_f8e10030_f8c1002c_f8a10028_f8810024; +defparam bootram.RAM0.INIT_13=256'he8603508_e880350c_f961001c_fa610050_95608001_fa41004c_fa210048_f9810044; +defparam bootram.RAM0.INIT_14=256'h30a50001_bc230060_84732000_32600001_84841800_a863ffff_10a00000_30c00404; +defparam bootram.RAM0.INIT_15=256'he8810024_e8610020_e961001c_e9e10000_30c60004_be32ffec_aa450008_12739800; +defparam bootram.RAM0.INIT_16=256'he9610040_e941003c_e9210038_e9010034_e8e10030_e8c1002c_e8a10028_940bc001; +defparam bootram.RAM0.INIT_17=256'h99fc1800_e8660000_30210054_b62e0000_ea610050_ea41004c_ea210048_e9810044; +defparam bootram.RAM0.INIT_18=256'h16459003_22400007_64e50402_44632c00_30600001_b800ffa8_fa60350c_80000000; +defparam bootram.RAM0.INIT_19=256'h80000000_b60f0008_f8603508_84632000_f8c70404_e8603508_a883ffff_be520018; +defparam bootram.RAM0.INIT_1A=256'h80000000_b60f0008_80000000_b6910000_80000000_b6110000_80000000_b60f0008; +defparam bootram.RAM0.INIT_1B=256'haa43ffff_326003e8_f9e10000_fa61001c_3021ffe0_e86003e8_80000000_b60f0008; +defparam bootram.RAM0.INIT_1C=256'hea61001c_e9e10000_bc32fff0_aa43ffff_e8730000_3273fffc_99fc1800_bc120018; +defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ffb0_80000000_b9f4fd28_d9e00800_3021fff8_30210020_b60f0008; +defparam bootram.RAM0.INIT_1E=256'hc9e00800_80000000_b9f4fca0_d9e00800_3021fff8_30210008_b60f0008_c9e00800; +defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_ffffffff_00000000_ffffffff_30210008_b60f0008; +defparam bootram.RAM0.INIT_20=256'h00000340_00000340_00000340_00000340_00000340_00000340_00000340_000003f4; +defparam bootram.RAM0.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000340; + ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), @@ -356,8 +394,9 @@ defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_ nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1) + //.gpio( {io_tx,io_rx} ) + ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -644,9 +683,10 @@ defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_ // Debug Pins assign debug_clk = {dsp_clk, wb_clk}; - assign debug = if_dat; + assign debug = m0_dat_o; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; + assign {io_tx,io_rx} = {if_adr, m0_adr}; endmodule // u2_core -- cgit v1.2.3 From 5922f348e19fd477c311c0cadef4eb5d3a17d4c6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Jul 2010 19:37:45 -0700 Subject: make loopback compile --- usrp2/top/u1e/u1e_core.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 787bf016c..5b60578ce 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -108,6 +108,9 @@ module u1e_core assign tx_underrun = 0; assign rx_overrun = 0; + + wire run_tx, run_rx, strobe_tx, strobe_rx, tx1_src_rdy, tx1_dst_rdy; + wire [31:0] debug_vtd, debug_vtc; `endif // LOOPBACK `ifdef TIMED -- cgit v1.2.3 From ed11f715c45ad129600e20849254e3899407002a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 19 Jul 2010 13:33:32 -0700 Subject: proper selection of bank of ram for instruction, since the address has already incremented by the time the data is returned --- usrp2/control_lib/bootram.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index 5e527de90..668012504 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -21,8 +21,12 @@ module bootram wire [31:0] DOB0, DOB1, DOB2, DOB3; wire ENB0, ENB1, ENB2, ENB3; wire [3:0] WEB; + + reg [1:0] delayed_if_bank; + always @(posedge clk) + delayed_if_bank <= if_adr[12:11]; - assign if_data = if_adr[12] ? (if_adr[11] ? DOA3 : DOA2) : (if_adr[11] ? DOA1 : DOA0); + assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0); assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0); always @(posedge clk) -- cgit v1.2.3 From 814b06dff3ffccdf7d8f80fcb93d21d740612804 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 19 Jul 2010 18:10:40 -0700 Subject: pushbutton now goes into interrupt controller, can be read from software. Normally high, goes low when pushed --- usrp2/top/u2plus/u2plus.v | 1 + usrp2/top/u2plus/u2plus_core.v | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index ac0f6bbd1..1feed1314 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -369,6 +369,7 @@ module u2plus .uart_baud_o (), .sim_mode (1'b0), .clock_divider (2), + .button (FPGA_RESET), .spiflash_cs (flash_cs), .spiflash_clk (flash_clk), .spiflash_miso (flash_miso), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 0470e6e9e..fa3fd9ff0 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -124,7 +124,8 @@ module u2plus_core output uart_baud_o, input sim_mode, input [3:0] clock_divider, - + input button, + output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi ); @@ -473,7 +474,7 @@ defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_ assign irq= {{8'b0}, {8'b0}, - {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {2'b0, button, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), -- cgit v1.2.3 From e73ffa9f830b070a6b897edfbcfadf35b6b1f0c6 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Tue, 20 Jul 2010 11:00:42 -0700 Subject: Fixed Makefile.common to correctly generate .mcs files. --- usrp2/top/Makefile.common | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index d0435fa1e..2f6b5fde3 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -15,6 +15,7 @@ BASE_DIR = $(abspath ..) ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin +BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs ################################################## @@ -53,6 +54,6 @@ $(BIN_FILE): $(ISE_FILE) touch $@ $(MCS_FILE): $(BIN_FILE) - promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE) + promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIT_FILE) .EXPORT_ALL_VARIABLES: -- cgit v1.2.3 From 3b6b6e153084bf1d57231c0a565e2a0204467b04 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 20 Jul 2010 11:16:41 -0700 Subject: connect SPI to adc, correct capitalization of SEN pins --- usrp2/top/u2plus/u2plus.v | 17 +++++++++-------- usrp2/top/u2plus/u2plus_core.v | 3 ++- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 1feed1314..efa1c9390 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -346,14 +346,15 @@ module u2plus .sclk (sclk_int), .mosi (mosi), .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), + .sen_clk (SEN_CLK), + .sen_dac (SEN_DAC), + .sen_adc (SEN_ADC), + .sen_tx_db (SEN_TX_DB), + .sen_tx_adc (SEN_TX_ADC), + .sen_tx_dac (SEN_TX_DAC), + .sen_rx_db (SEN_RX_DB), + .sen_rx_adc (SEN_RX_ADC), + .sen_rx_dac (SEN_RX_DAC), .io_tx (io_tx[15:0]), .io_rx (io_rx[15:0]), .RAM_D (RAM_D), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 9e197cfbb..b71b34e8d 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -97,6 +97,7 @@ module u2plus_core input miso, output sen_clk, output sen_dac, + output sen_adc, output sen_tx_db, output sen_tx_adc, output sen_tx_dac, @@ -375,7 +376,7 @@ defparam bootram.RAM0.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From e161ad7c61d88cac0ec85a972a64af8fe4449fce Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 20 Jul 2010 13:22:02 -0700 Subject: reconnect the serial clock --- usrp2/top/u2plus/u2plus.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index efa1c9390..e382b1aa4 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -343,7 +343,7 @@ module u2plus .clk_sel (clk_sel[1:0]), .clk_func (clk_func), .clk_status (clk_status), - .sclk (sclk_int), + .sclk (sclk), .mosi (mosi), .miso (miso), .sen_clk (SEN_CLK), -- cgit v1.2.3 From ef662b0c952f8e22ba760917f3781279471d69dc Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 21 Jul 2010 16:21:14 -0700 Subject: capitalization matching --- usrp2/top/u2plus/u2plus.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index e382b1aa4..d1a9166ac 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -125,6 +125,10 @@ module u2plus input flash_miso ); + wire CLK_TO_MAC_int, CLK_TO_MAC_int2; + IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); + BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); + // FPGA-specific pins connections wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; @@ -289,7 +293,7 @@ module u2plus u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), + .clk_to_mac (CLK_TO_MAC), .pps_in (pps_in), .leds (leds_int), .debug (debug[31:0]), -- cgit v1.2.3 From 0e98b9cfe5183f284da698243c6e91b61572c41e Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Tue, 27 Jul 2010 13:25:33 -0700 Subject: fix timing races on ADC and DAC pins --- usrp2/top/u2plus/u2plus.v | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index e382b1aa4..df91d8875 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -23,8 +23,8 @@ module u2plus input ADCB_0_p, input ADCB_0_n, // DAC - output [15:0] DACA, - output [15:0] DACB, + output reg [15:0] DACA, + output reg [15:0] DACB, input DAC_LOCK, // unused for now // DB IO Pins @@ -149,9 +149,10 @@ module u2plus wire dcm_rst = 0; - wire [13:0] adc_a, adc_b; + `ifdef LVDS - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + wire [13:0] adc_a, adc_b; + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), @@ -159,11 +160,14 @@ module u2plus {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), .out({adc_a,adc_b})); `else - assign adc_a = {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + reg [13:0] adc_a, adc_b; + always @(posedge dsp_clk) + begin + adc_a <= {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; - assign adc_b = {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; - + end `endif // !`ifdef LVDS // Handle Clocks @@ -286,10 +290,16 @@ module u2plus .S(0) // Synchronous preset input ); */ + + wire [15:0] dac_a_int, dac_b_int; + + always @(negedge dsp_clk) DACA <= dac_a_int; + always @(negedge dsp_clk) DACB <= dac_b_int; + u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), + .clk_to_mac (CLK_TO_MAC), .pps_in (pps_in), .leds (leds_int), .debug (debug[31:0]), @@ -331,8 +341,8 @@ module u2plus .adc_ovf_b (adc_ovf_b), .adc_on_b (adc_on_b), .adc_oe_b (adc_oe_b), - .dac_a (DACA[15:0]), - .dac_b (DACB[15:0]), + .dac_a (dac_a_int[15:0]), + .dac_b (dac_b_int[15:0]), .scl_pad_i (scl_pad_i), .scl_pad_o (scl_pad_o), .scl_pad_oen_o (scl_pad_oen_o), -- cgit v1.2.3 From fc99cdcb6c3980e386c5d0124086cbe13e345c97 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Wed, 28 Jul 2010 09:49:12 -0700 Subject: latest bootloader in core, fixed eth_led to be active high, connected eth clk --- usrp2/top/u2plus/u2plus.v | 4 +- usrp2/top/u2plus/u2plus_core.v | 202 +++++++++++++++++++++++++++++++++-------- 2 files changed, 167 insertions(+), 39 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index c4db0d6cd..b349175de 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -218,7 +218,7 @@ module u2plus // LEDs are active low outputs wire [5:0] leds_int; - assign {leds,ETH_LED} = ~leds_int; // drive low to turn on leds + assign {leds,ETH_LED} = {6'b111110 ^ leds_int}; // drive low to turn on leds // SPI wire miso, mosi, sclk; @@ -303,7 +303,7 @@ module u2plus u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), - .clk_to_mac (CLK_TO_MAC), + .clk_to_mac (CLK_TO_MAC_int2), .pps_in (pps_in), .leds (leds_int), .debug (debug[31:0]), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index b71b34e8d..6092f1ba3 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -285,41 +285,170 @@ module u2plus_core //defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; ////ICAP test v0.1 -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b8080234_00000000_b8080348_00000000_b8080050; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8080350; -defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_304003f8_31a00430_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40198_80000000_b9f400cc; -defparam bootram.RAM0.INIT_04=256'he8830000_e8600400_80000000_99fc2000_f8600400_b8000044_bc030014_f9e10000; -defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a00428_bc030010_30600000_b0000000_30630004_be24ffec; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b8080d54_00000000_b8080050; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8080d5c; +defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401448_31a01468_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f4047c_80000000_b9f400cc; +defparam bootram.RAM0.INIT_04=256'he8830000_e8601450_80000000_99fc2000_f8601450_b8000044_bc030014_f9e10000; +defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01460_bc030010_30600000_b0000000_30630004_be24ffec; defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; -defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a00428_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a0042c_bc030014_30800000_b0000000_e860042c; -defparam bootram.RAM0.INIT_09=256'h06463800_20e00430_20c00430_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; +defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01460_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01464_bc030014_30800000_b0000000_e8601464; +defparam bootram.RAM0.INIT_09=256'h06463800_20e01468_20c01468_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; -defparam bootram.RAM0.INIT_0B=256'hb9f401e4_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f81c; -defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4002c_20e00000_20c00000_80000000_b9f40224_80000000; -defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f401b0_80000000_b9f4022c; -defparam bootram.RAM0.INIT_0E=256'hbc32fff0_aa434b40_b000004c_30630001_80000000_10600000_a48500ff_10a00000; -defparam bootram.RAM0.INIT_0F=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; -defparam bootram.RAM0.INIT_10=256'hf8803500_30800012_f8603508_3060ffff_80000000_b9f4fe68_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_11=256'hf8610020_f9e10000_3021ffac_80000000_b60f0008_f860350c_f8a03504_30a0ffef; -defparam bootram.RAM0.INIT_12=256'hf9610040_f941003c_f9210038_f9010034_f8e10030_f8c1002c_f8a10028_f8810024; -defparam bootram.RAM0.INIT_13=256'he8603508_e880350c_f961001c_fa610050_95608001_fa41004c_fa210048_f9810044; -defparam bootram.RAM0.INIT_14=256'h30a50001_bc230060_84732000_32600001_84841800_a863ffff_10a00000_30c00404; -defparam bootram.RAM0.INIT_15=256'he8810024_e8610020_e961001c_e9e10000_30c60004_be32ffec_aa450008_12739800; -defparam bootram.RAM0.INIT_16=256'he9610040_e941003c_e9210038_e9010034_e8e10030_e8c1002c_e8a10028_940bc001; -defparam bootram.RAM0.INIT_17=256'h99fc1800_e8660000_30210054_b62e0000_ea610050_ea41004c_ea210048_e9810044; -defparam bootram.RAM0.INIT_18=256'h16459003_22400007_64e50402_44632c00_30600001_b800ffa8_fa60350c_80000000; -defparam bootram.RAM0.INIT_19=256'h80000000_b60f0008_f8603508_84632000_f8c70404_e8603508_a883ffff_be520018; -defparam bootram.RAM0.INIT_1A=256'h80000000_b60f0008_80000000_b6910000_80000000_b6110000_80000000_b60f0008; -defparam bootram.RAM0.INIT_1B=256'haa43ffff_326003e8_f9e10000_fa61001c_3021ffe0_e86003e8_80000000_b60f0008; -defparam bootram.RAM0.INIT_1C=256'hea61001c_e9e10000_bc32fff0_aa43ffff_e8730000_3273fffc_99fc1800_bc120018; -defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ffb0_80000000_b9f4fd28_d9e00800_3021fff8_30210020_b60f0008; -defparam bootram.RAM0.INIT_1E=256'hc9e00800_80000000_b9f4fca0_d9e00800_3021fff8_30210008_b60f0008_c9e00800; -defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_ffffffff_00000000_ffffffff_30210008_b60f0008; -defparam bootram.RAM0.INIT_20=256'h00000340_00000340_00000340_00000340_00000340_00000340_00000340_000003f4; -defparam bootram.RAM0.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000340; - +defparam bootram.RAM0.INIT_0B=256'hb9f40bf0_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f828; +defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4014c_20e00000_20c00000_80000000_b9f40d70_80000000; +defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f40bbc_80000000_b9f40d78; +defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; +defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; +defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; +defparam bootram.RAM0.INIT_11=256'hb9f402c0_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; +defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a00f7c_10b30000_b9f405cc_10d60000_10b30000; +defparam bootram.RAM0.INIT_13=256'h30a00f7c_bc120040_aa430001_30a00f44_e061001c_10a30000_be520034_16439003; +defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f40440_b800ffb4_80000000_b9f4044c; +defparam bootram.RAM0.INIT_15=256'h80000000_b9f40414_b800ff88_80000000_b9f40420_30a00f44_80000000_b9f40b54; +defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f403f8_30a00f48_80000000_b9f409a0_30a08000_b0000000; +defparam bootram.RAM0.INIT_17=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fa61001c_f9e10000_3021ffe0; +defparam bootram.RAM0.INIT_18=256'hb9f40750_80000000_b9f40408_f800200c_80000000_b9f4fef4_f860200c_306000ff; +defparam bootram.RAM0.INIT_19=256'h30a01048_bc04013c_a4842000_e8803334_80000000_b9f403a4_30a00f80_80000000; +defparam bootram.RAM0.INIT_1A=256'h30a010ac_bc23010c_80000000_b9f4099c_30a00000_b0000020_80000000_b9f4038c; +defparam bootram.RAM0.INIT_1B=256'h30a010fc_bc030058_80000000_b9f40930_30a00000_b0000040_80000000_b9f4036c; +defparam bootram.RAM0.INIT_1C=256'h30c07c00_b9f4070c_30a00000_b0000040_30e08000_b0000000_80000000_b9f4034c; +defparam bootram.RAM0.INIT_1D=256'he9e10000_80000000_b9f40318_30a01128_80000000_b9f408c0_30a08000_b0000000; +defparam bootram.RAM0.INIT_1E=256'hb000007f_80000000_b9f402f8_30a01164_30210020_b60f0008_30600001_ea61001c; +defparam bootram.RAM0.INIT_1F=256'h80000000_b9f402d4_30a00ff0_12630000_be230030_80000000_b9f408bc_30a00000; +defparam bootram.RAM0.INIT_20=256'hb0000000_30210020_b60f0008_ea61001c_e9e10000_10730000_80000000_b9f4fe1c; +defparam bootram.RAM0.INIT_21=256'hb9f4082c_30a08000_b0000000_30c07c00_b9f40678_30a00000_b000007f_30e08000; +defparam bootram.RAM0.INIT_22=256'hb60f0008_30600001_ea61001c_e9e10000_80000000_b9f40284_30a00fb4_80000000; +defparam bootram.RAM0.INIT_23=256'h80000000_b9f40254_30a00f94_b800feec_80000000_b9f40264_30a01074_30210020; +defparam bootram.RAM0.INIT_24=256'h80000000_b9f40234_30a00ff0_bc23001c_80000000_b9f40818_30a00000_b000007f; +defparam bootram.RAM0.INIT_25=256'hb9f405e8_30a00000_b000007f_30e08000_b0000000_b800fe94_80000000_b9f4fd7c; +defparam bootram.RAM0.INIT_26=256'h80000000_b9f401f4_30a00fb4_80000000_b9f4079c_30a08000_b0000000_30c07c00; +defparam bootram.RAM0.INIT_27=256'h3021ffdc_80000000_b60f0008_80000000_b9f4fb84_f9e10000_3021ffe4_b800fe5c; +defparam bootram.RAM0.INIT_28=256'h90630060_80000000_b9f402b0_12c50000_f9e10000_12650000_fac10020_fa61001c; +defparam bootram.RAM0.INIT_29=256'he9e10000_10760000_f0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000; +defparam bootram.RAM0.INIT_2A=256'h80000000_b9f4026c_f9e10000_3021ffe4_30210024_b60f0008_eac10020_ea61001c; +defparam bootram.RAM0.INIT_2B=256'h12650000_e0650000_f9e10000_fa61001c_3021ffe0_3021001c_b60f0008_e9e10000; +defparam bootram.RAM0.INIT_2C=256'he9e10000_bc25fff0_90a30060_e0730000_32730001_b9f401b8_bc050018_90a30060; +defparam bootram.RAM0.INIT_2D=256'hb9f40184_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_10600000_ea61001c; +defparam bootram.RAM0.INIT_2E=256'hf9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000_12c50000; +defparam bootram.RAM0.INIT_2F=256'h9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000_b9f4013c; +defparam bootram.RAM0.INIT_30=256'hb0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c_b0000000; +defparam bootram.RAM0.INIT_31=256'h80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002_f860f81c; +defparam bootram.RAM0.INIT_32=256'hb0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002_94608001; +defparam bootram.RAM0.INIT_33=256'h80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c; +defparam bootram.RAM0.INIT_34=256'h84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002_94e08001; +defparam bootram.RAM0.INIT_35=256'h80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020_80633000; +defparam bootram.RAM0.INIT_36=256'hb9f40064_80000000_b9f4fe98_f9e10000_3021ffe4_80000000_b60f0008_9404c001; +defparam bootram.RAM0.INIT_37=256'hb9f40044_f9e10000_3021ffe4_3021001c_b60f0008_10600000_e9e10000_30a0000a; +defparam bootram.RAM0.INIT_38=256'h3021ffe4_80000000_b60f0008_f0a01454_3021001c_b60f0008_e9e10000_30a0000a; +defparam bootram.RAM0.INIT_39=256'h3021001c_b60f0008_e9e10000_f8603700_306000d9_30a00001_b9f4ffec_f9e10000; +defparam bootram.RAM0.INIT_3A=256'hbc03fffc_e8603704_12650000_be120024_aa45000a_f9e10000_fa61001c_3021ffe0; +defparam bootram.RAM0.INIT_3B=256'hb800ffdc_30a0000d_b9f4ffcc_30210020_b60f0008_ea61001c_e9e10000_fa60370c; +defparam bootram.RAM0.INIT_3C=256'he8603704_30a0000d_be120024_aa53000a_f9e10000_12650000_fa61001c_3021ffe0; +defparam bootram.RAM0.INIT_3D=256'h80000000_b9f4ff88_30210020_b60f0008_ea61001c_e9e10000_fa60370c_bc030008; +defparam bootram.RAM0.INIT_3E=256'h3065ffa9_90a50060_80000000_b60f0008_e8603710_bc03fffc_e8603708_b800ffdc; +defparam bootram.RAM0.INIT_3F=256'h16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024_16459001_3240005a; +defparam bootram.RAM1.INIT_00=256'h13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff_3085ffd0_be52000c; +defparam bootram.RAM1.INIT_01=256'he0790000_fb410030_fb010028_fae10024_fac10020_fa61001c_f9e10000_fb610034; +defparam bootram.RAM1.INIT_02=256'heac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034_aa43003a_13660000; +defparam bootram.RAM1.INIT_03=256'he8c01458_30210038_b60f0008_eb610034_eb410030_eb21002c_eb010028_eae10024; +defparam bootram.RAM1.INIT_04=256'ha4630044_c0662000_a4a300ff_be04001c_90840060_30650001_c085c800_30a00001; +defparam bootram.RAM1.INIT_05=256'hb9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4; +defparam bootram.RAM1.INIT_06=256'hbe38ff74_93040060_e083000b_10791800_fa7b0004_10739800_12761800_66c30404; +defparam bootram.RAM1.INIT_07=256'he0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0_e0b90005_30a0fffd; +defparam bootram.RAM1.INIT_08=256'h12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8; +defparam bootram.RAM1.INIT_09=256'h1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0_e0b90007_fafb0008; +defparam bootram.RAM1.INIT_0A=256'ha6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000_be130060_f07b0000; +defparam bootram.RAM1.INIT_0B=256'hd0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800; +defparam bootram.RAM1.INIT_0C=256'hbe52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001_e8fb0004_ea7b000c; +defparam bootram.RAM1.INIT_0D=256'h10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000_eadb0008_a74300ff; +defparam bootram.RAM1.INIT_0E=256'h16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10_107a1800_12c7b000; +defparam bootram.RAM1.INIT_0F=256'h10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff_a6d600ff_1063c000; +defparam bootram.RAM1.INIT_10=256'ha1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8_a4630100_e8603b10; +defparam bootram.RAM1.INIT_11=256'ha46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10_a4a500ff_80884800; +defparam bootram.RAM1.INIT_12=256'hbc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10_a0840100_f8603b18; +defparam bootram.RAM1.INIT_13=256'h10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000_b60f0008_e8603b00; +defparam bootram.RAM1.INIT_14=256'hb60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001_31200400_31000008; +defparam bootram.RAM1.INIT_15=256'h13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030_3021ffc4_3021001c; +defparam bootram.RAM1.INIT_16=256'h3060000b_66d60408_f8603b10_f8003b18_30600400_12670000_b9f4ff3c_fae10034; +defparam bootram.RAM1.INIT_17=256'hf8603b10_30600528_f8803b10_30800428_f8603b18_30600001_fac03b00_f8603b04; +defparam bootram.RAM1.INIT_18=256'hf8603b10_30600400_3261001c_12e00000_12d30000_be18009c_80000000_b9f4ff00; +defparam bootram.RAM1.INIT_19=256'he8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8_f8803b10_30800500; +defparam bootram.RAM1.INIT_1A=256'hbeb20034_16459003_22400010_f8610028_e8603b00_f8810024_e8803b04_f8610020; +defparam bootram.RAM1.INIT_1B=256'h12f72800_bc32fff0_16442800_30840001_d0762000_c0732000_30a00010_10800000; +defparam bootram.RAM1.INIT_1C=256'hbe52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800_beb20020_1658b803; +defparam bootram.RAM1.INIT_1D=256'hb60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000_f8003b18_12d62800; +defparam bootram.RAM1.INIT_1E=256'hf9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000_b0009f00_3021003c; +defparam bootram.RAM1.INIT_1F=256'hb0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000_31200400_b9f4fe34; +defparam bootram.RAM1.INIT_20=256'hb9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824; +defparam bootram.RAM1.INIT_21=256'h80000000_b9f40100_a46300ff_be120010_aa440020_a48400ff_64830008_80000000; +defparam bootram.RAM1.INIT_22=256'hb0000000_e063118a_bc52ffe4_16439001_32400018_bcb2fff0_16439001_32400015; +defparam bootram.RAM1.INIT_23=256'hf9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_b800ffac_f860f824; +defparam bootram.RAM1.INIT_24=256'h30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40174; +defparam bootram.RAM1.INIT_25=256'h10b60000_30c00006_b9f4fdf0_f9e10000_10f60000_32c1001c_fac10028_3021ffd4; +defparam bootram.RAM1.INIT_26=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f400b0_30c011a4; +defparam bootram.RAM1.INIT_27=256'hf9e10000_10f60000_32c1001c_fac10028_3021ffd4_3021002c_b60f0008_6464001f; +defparam bootram.RAM1.INIT_28=256'h80841800_14830000_30e00006_b9f40064_30c011ac_10b60000_30c00006_b9f4fda4; +defparam bootram.RAM1.INIT_29=256'h3021ffe4_30a011b4_3021002c_b60f0008_6464001f_eac10028_e9e10000_a884ffff; +defparam bootram.RAM1.INIT_2A=256'hb6910000_80000000_b6110000_30a0ffff_b9f4f324_80000000_b9f4f828_f9e10000; +defparam bootram.RAM1.INIT_2B=256'hbeb2005c_16479003_22400003_80000000_b60f0008_80000000_b60f0008_80000000; +defparam bootram.RAM1.INIT_2C=256'h30e7fffc_bc320040_16432000_e8660000_e8850000_bc230050_a4630003_80653000; +defparam bootram.RAM1.INIT_2D=256'hbc120028_aa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004; +defparam bootram.RAM1.INIT_2E=256'haa47ffff_30e7ffff_30c60001_30a50001_be320020_16434000_e0660000_e1050000; +defparam bootram.RAM1.INIT_2F=256'hbeb20018_16479003_2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0; +defparam bootram.RAM1.INIT_30=256'h10e72000_11040000_bc070024_11050000_be030034_a4630003_80662800_10850000; +defparam bootram.RAM1.INIT_31=256'h10650000_b60f0008_30c60001_be32fff0_16474000_31080001_f0680000_e0660000; +defparam bootram.RAM1.INIT_32=256'he866000c_f8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000; +defparam bootram.RAM1.INIT_33=256'h16479003_22400003_31080010_be52ffd0_16479003_2240000f_f868000c_30c60010; +defparam bootram.RAM1.INIT_34=256'hbe52ffec_16479003_22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c; +defparam bootram.RAM1.INIT_35=256'hfa61001c_3021ffe0_e8600f34_10880000_b810ff68_11044000_10c43000_30840004; +defparam bootram.RAM1.INIT_36=256'haa43ffff_e8730000_3273fffc_99fc1800_bc120018_aa43ffff_32600f34_f9e10000; +defparam bootram.RAM1.INIT_37=256'hb9f4f1dc_d9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0; +defparam bootram.RAM1.INIT_38=256'hd9e00800_3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000; +defparam bootram.RAM1.INIT_39=256'hffffffff_00000000_ffffffff_30210008_b60f0008_c9e00800_80000000_b9f4f154; +defparam bootram.RAM1.INIT_3A=256'h7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000; +defparam bootram.RAM1.INIT_3B=256'h4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120; +defparam bootram.RAM1.INIT_3C=256'h20555352_74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062_55535250; +defparam bootram.RAM1.INIT_3D=256'h65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20; +defparam bootram.RAM1.INIT_3E=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; +defparam bootram.RAM1.INIT_3F=256'h66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068_206e6576; +defparam bootram.RAM2.INIT_00=256'h6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520_69726d77; +defparam bootram.RAM2.INIT_01=256'h5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963; +defparam bootram.RAM2.INIT_02=256'h726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000_2052414d; +defparam bootram.RAM2.INIT_03=256'h6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f; +defparam bootram.RAM2.INIT_04=256'h7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e; +defparam bootram.RAM2.INIT_05=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f; +defparam bootram.RAM2.INIT_06=256'h20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741; +defparam bootram.RAM2.INIT_07=256'h56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164; +defparam bootram.RAM2.INIT_08=256'h204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563_64207072; +defparam bootram.RAM2.INIT_09=256'h61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67; +defparam bootram.RAM2.INIT_0A=256'h61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67; +defparam bootram.RAM2.INIT_0B=256'h77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000; +defparam bootram.RAM2.INIT_0C=256'h2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75; +defparam bootram.RAM2.INIT_0D=256'h00000000_6f72740a_0a0a6162_aa990000_ffffffff_b8080000_b0000000_10101200; +defparam bootram.RAM2.INIT_0E=256'h20202020_20202020_20202020_20202020_28282820_20202828_20202020_00202020; +defparam bootram.RAM2.INIT_0F=256'h10101010_04040410_04040404_10040404_10101010_10101010_10101010_20881010; +defparam bootram.RAM2.INIT_10=256'h10101010_01010101_01010101_01010101_01010101_01010101_41414141_10104141; +defparam bootram.RAM2.INIT_11=256'h10101010_02020202_02020202_02020202_02020202_02020202_42424242_10104242; +defparam bootram.RAM2.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_20000000; +defparam bootram.RAM2.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_1A=256'h20202020_20202020_20202020_28282020_20282828_20202020_20202020_00000000; +defparam bootram.RAM2.INIT_1B=256'h04041010_04040404_04040404_10101010_10101010_10101010_88101010_20202020; +defparam bootram.RAM2.INIT_1C=256'h01010110_01010101_01010101_01010101_01010101_41414101_10414141_10101010; +defparam bootram.RAM2.INIT_1D=256'h02020210_02020202_02020202_02020202_02020202_42424202_10424242_10101010; +defparam bootram.RAM2.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_10101020; +defparam bootram.RAM2.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_22=256'h00000000_00001344_01000000_00000f40_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), @@ -396,8 +525,8 @@ defparam bootram.RAM0.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_ nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1) - //.gpio( {io_tx,io_rx} ) + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); // ///////////////////////////////////////////////////////////////////////// @@ -685,10 +814,9 @@ defparam bootram.RAM0.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_ // Debug Pins assign debug_clk = {dsp_clk, wb_clk}; - assign debug = m0_dat_o; + assign debug = debug_vt; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; - assign {io_tx,io_rx} = {if_adr, m0_adr}; endmodule // u2_core -- cgit v1.2.3 From ed2882e600832f6cb46d05bde7aa49d045e63895 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Wed, 28 Jul 2010 15:52:00 -0700 Subject: Fix for SPI SS > 8 bits wide --- usrp2/opencores/spi/rtl/verilog/spi_defines.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v index a6925918e..25c08214b 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -102,8 +102,8 @@ // Number of device select signals. Use SPI_SS_NB for fine tuning the // exact number. // -`define SPI_SS_NB_8 -//`define SPI_SS_NB_16 +//`define SPI_SS_NB_8 +`define SPI_SS_NB_16 //`define SPI_SS_NB_24 //`define SPI_SS_NB_32 -- cgit v1.2.3 From dcdab8c84ed9d4481ee929fdb13a11e2be930329 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 29 Jul 2010 10:59:53 -0700 Subject: Added DCM reset line to sr. --- usrp2/top/u2plus/u2plus.v | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index b349175de..d894631ac 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -151,9 +151,11 @@ module u2plus OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; - wire dcm_rst = 0; - - + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + `ifdef LVDS wire [13:0] adc_a, adc_b; capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds -- cgit v1.2.3 From 19974fa00b04280e52d3d644e8e12953c570c06d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 10 Aug 2010 09:59:33 -0700 Subject: enlarge loopback fifo --- usrp2/top/u1e/u1e_core.v | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 5b60578ce..516a5cf96 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -101,7 +101,7 @@ module u1e_core wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; `ifdef LOOPBACK - fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo + fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); @@ -437,9 +437,6 @@ module u1e_core { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; - //assign debug = { phase[23:8], txsync, txblank, tx }; - - assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; -- cgit v1.2.3 From f0e231396d6c512dc4a3fee0c186b3651327e9f2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 11 Aug 2010 14:34:35 -0700 Subject: quad uart instead of single, for the extra on board serial ports --- usrp2/control_lib/Makefile.srcs | 1 + usrp2/control_lib/quad_uart.v | 71 +++++++++++++++++++++++++++++++++++++++++ usrp2/top/u2plus/u2plus.v | 5 ++- usrp2/top/u2plus/u2plus_core.v | 15 +++++---- 4 files changed, 82 insertions(+), 10 deletions(-) create mode 100644 usrp2/control_lib/quad_uart.v diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs index ad491b83d..666ac344c 100644 --- a/usrp2/control_lib/Makefile.srcs +++ b/usrp2/control_lib/Makefile.srcs @@ -30,6 +30,7 @@ srl.v \ system_control.v \ wb_1master.v \ wb_readback_mux.v \ +quad_uart.v \ simple_uart.v \ simple_uart_tx.v \ simple_uart_rx.v \ diff --git a/usrp2/control_lib/quad_uart.v b/usrp2/control_lib/quad_uart.v new file mode 100644 index 000000000..afa6fae1d --- /dev/null +++ b/usrp2/control_lib/quad_uart.v @@ -0,0 +1,71 @@ + +module quad_uart + #(parameter TXDEPTH = 1, + parameter RXDEPTH = 1) + (input clk_i, input rst_i, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, + output [3:0] rx_int_o, output [3:0] tx_int_o, + output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o + ); + + // Register Map + localparam SUART_CLKDIV = 0; + localparam SUART_TXLEVEL = 1; + localparam SUART_RXLEVEL = 2; + localparam SUART_TXCHAR = 3; + localparam SUART_RXCHAR = 4; + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + reg [15:0] clkdiv[0:3]; + wire [7:0] rx_char[0:3]; + wire [3:0] tx_fifo_full, rx_fifo_empty; + wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3]; + + always @(posedge clk_i) + if (rst_i) + ack_o <= 1'b0; + else + ack_o <= wb_acc & ~ack_o; + + integer i; + always @(posedge clk_i) + if (rst_i) + for(i=0;i<4;i=i+1) + clkdiv[i] <= 0; + else if (wb_wr) + case(adr_i[2:0]) + SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0]; + endcase // case(adr_i) + + always @(posedge clk_i) + case (adr_i[2:0]) + SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]]; + SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]]; + SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]]; + endcase // case(adr_i) + + genvar j; + generate + for(j=0;j<4;j=j+1) + begin : gen_uarts + simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx + (.clk(clk_i),.rst(rst_i), + .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)), + .fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]), + .clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j])); + + simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx + (.clk(clk_i),.rst(rst_i), + .fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)), + .fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]), + .clkdiv(clkdiv[j]),.rx(rx_i[j])); + end // block: gen_uarts + endgenerate + + assign tx_int_o = ~tx_fifo_full; // Interrupt for those that have space + assign rx_int_o = ~rx_fifo_empty; // Interrupt for those that have data + +endmodule // quad_uart diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index d894631ac..a0ba4d4cc 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -381,8 +381,8 @@ module u2plus .RAM_WEn (RAM_WEn), .RAM_OEn (RAM_OEn), .RAM_LDn (RAM_LDn), - .uart_tx_o (TXD[1]), - .uart_rx_i (RXD[1]), + .uart_tx_o (TXD[3:1]), + .uart_rx_i ({1'b1,RXD[3:1]}), .uart_baud_o (), .sim_mode (1'b0), .clock_divider (2), @@ -395,6 +395,5 @@ module u2plus assign RAM_ZZ = 1; assign RAM_BWn = 4'b1111; - assign TXD[3:2] = 2'b11; endmodule // u2plus diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 6092f1ba3..79318aa27 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -120,9 +120,9 @@ module u2plus_core output RAM_LDn, // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, + output [3:0] uart_tx_o, + input [3:0] uart_rx_i, + output [3:0] uart_baud_o, input sim_mode, input [3:0] clock_divider, input button, @@ -156,7 +156,8 @@ module u2plus_core wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + wire proc_int, overrun, underrun; + wire [3:0] uart_tx_int, uart_rx_int; wire [31:0] debug_gpio_0, debug_gpio_1; wire [31:0] atr_lines; @@ -642,8 +643,8 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ // Interrupt Controller, Slave #8 assign irq= {{8'b0}, - {8'b0}, - {2'b0, button, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {uart_tx_int[3:0], uart_rx_int[3:0]}, + {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00}, {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), @@ -670,7 +671,7 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries (.clk_i(wb_clk),.rst_i(wb_rst), .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); -- cgit v1.2.3 From 9e97e773b9952ec3212e6c818bb40d785016afa4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 11 Aug 2010 16:26:58 -0700 Subject: connect the setting reg to the real clock and reset --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 516a5cf96..4561df173 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -70,7 +70,7 @@ module u1e_core wire clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear; setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear)); assign clear_tx = clear_tx_int & do_clear; assign clear_rx = clear_rx_int & do_clear; -- cgit v1.2.3 From fe9ff1691f632677573f1cb3737684cfd181a21d Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 12 Aug 2010 11:37:59 -0700 Subject: Fixed u2plus_core.v to use quad_uart instead of simple_uart. --- usrp2/top/u2plus/u2plus_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 79318aa27..1db7e5b79 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -668,7 +668,7 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ // ///////////////////////////////////////////////////////////////////////// // UART, Slave #10 - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries (.clk_i(wb_clk),.rst_i(wb_rst), .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), -- cgit v1.2.3 From 3091759d3f6a69bc0c56f2101b7b775de443212a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 13 Aug 2010 11:49:36 -0700 Subject: this is necessary for some reason --- usrp2/top/u1e/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index f4a643176..3cb9fd8f3 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -95,6 +95,7 @@ GEN_PROG_FILE_PROPERTIES = \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" SIM_MODEL_PROPERTIES = "" -- cgit v1.2.3 From 1d9d3dcc7b460e25881d182e74429f91cef31a50 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 17 Aug 2010 15:50:27 -0700 Subject: delay the q channel to make the channels line up on the AD9862 --- usrp2/top/u1e/u1e.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 523aae1b9..9536b5ced 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -99,6 +99,11 @@ module u1e TXSYNC <= 1; end `else // !`ifdef DCM + + reg[13:0] delay_q; + always @(posedge clk_fpga) + delay_q <= tx_q; + genvar i; generate for(i=0;i<14;i=i+1) @@ -111,7 +116,7 @@ module u1e .C1(~clk_fpga), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(tx_i[i]), // 1-bit data input (associated with C0) - .D1(tx_q[i]), // 1-bit data input (associated with C1) + .D1(delay_q[i]), // 1-bit data input (associated with C1) .R(1'b0), // 1-bit reset input .S(1'b0)); // 1-bit set input end // block: gen_dacout -- cgit v1.2.3 From 746f94409d12b6ab2a0e99260655b5a0460ba220 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 17 Aug 2010 16:37:55 -0700 Subject: connect atr --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4561df173..13e6f4b68 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -419,7 +419,7 @@ module u1e_core (.clk_i(wb_clk), .rst_i(wb_rst), .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(0), .run_tx(0), .ctrl_lines(atr_lines)); + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 02c2a3fd08b1ae1a306fa45d89b55dafeaffb508 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 17 Aug 2010 17:11:43 -0700 Subject: attach run_tx and run_rx to leds --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 13e6f4b68..63488f549 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -339,7 +339,7 @@ module u1e_core assign rx_enable = xfer_rate[14]; assign rate = xfer_rate[7:0]; - assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board + assign { debug_led[2],debug_led[0],debug_led[1] } = {run_rx,run_tx,reg_leds[0]}; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : -- cgit v1.2.3 From 50a2ccee65677ed855c1798185d963fde1607324 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 19 Aug 2010 13:08:04 -0700 Subject: catch up with tx_policy --- usrp2/fifo/fifo36_mux.v | 2 +- usrp2/fifo/fifo_new_tb.vcd | 5506 --------------------------------------- usrp2/fifo/fifo_tb.v | 25 +- usrp2/top/Makefile.common | 2 +- usrp2/top/u2_rev3/u2_core_udp.v | 56 +- usrp2/vrt/Makefile.srcs | 2 + usrp2/vrt/gen_context_pkt.v | 72 + usrp2/vrt/vita_rx_framer.v | 2 +- usrp2/vrt/vita_tx_chain.v | 71 + usrp2/vrt/vita_tx_control.v | 115 +- usrp2/vrt/vita_tx_deframer.v | 30 +- 11 files changed, 311 insertions(+), 5572 deletions(-) delete mode 100644 usrp2/fifo/fifo_new_tb.vcd create mode 100644 usrp2/vrt/gen_context_pkt.v create mode 100644 usrp2/vrt/vita_tx_chain.v diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 04ec5abe8..92bf13ff9 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -52,6 +52,6 @@ module fifo36_mux assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i; + assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; endmodule // fifo36_demux diff --git a/usrp2/fifo/fifo_new_tb.vcd b/usrp2/fifo/fifo_new_tb.vcd deleted file mode 100644 index 796889e7d..000000000 --- a/usrp2/fifo/fifo_new_tb.vcd +++ /dev/null @@ -1,5506 +0,0 @@ -$date - Thu Mar 19 17:21:11 2009 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module fifo_new_tb $end -$var wire 1 ! dst_rdy_f36i $end -$var wire 36 " f36_in [35:0] $end -$var wire 36 # i1 [35:0] $end -$var wire 1 $ i1_dr $end -$var wire 1 % i1_sr $end -$var wire 19 & i2 [18:0] $end -$var wire 1 ' i2_dr $end -$var wire 1 ( i2_sr $end -$var wire 19 ) i3 [18:0] $end -$var wire 1 * i3_dr $end -$var wire 1 + i3_sr $end -$var wire 36 , i4 [35:0] $end -$var wire 1 - i4_sr $end -$var wire 8 . ll_data [7:0] $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 0 ll_eof_n $end -$var wire 1 1 ll_sof_n $end -$var wire 1 2 ll_src_rdy_n $end -$var reg 1 3 clear $end -$var reg 1 4 clk $end -$var reg 16 5 count [15:0] $end -$var reg 1 6 dst_rdy_f36o $end -$var reg 32 7 f36_data [31:0] $end -$var reg 1 8 f36_eof $end -$var reg 2 9 f36_occ [1:0] $end -$var reg 1 : f36_sof $end -$var reg 1 ; i4_dr $end -$var reg 1 < rst $end -$var reg 1 = src_rdy_f36i $end -$scope module fifo_short1 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 36 @ datain [35:0] $end -$var wire 36 A dataout [35:0] $end -$var wire 1 $ dst_rdy_i $end -$var wire 1 ! dst_rdy_o $end -$var wire 1 B read $end -$var wire 1 C reset $end -$var wire 1 D src_rdy_i $end -$var wire 1 % src_rdy_o $end -$var wire 1 E write $end -$var reg 4 F a [3:0] $end -$var reg 1 G empty $end -$var reg 1 H full $end -$var reg 5 I occupied [4:0] $end -$var reg 5 J space [4:0] $end -$scope begin gen_srl16[0] $end -$scope module srl16e $end -$var wire 1 K A0 $end -$var wire 1 L A1 $end -$var wire 1 M A2 $end -$var wire 1 N A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 O D $end -$var wire 1 P Q $end -$var reg 16 Q data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[1] $end -$scope module srl16e $end -$var wire 1 R A0 $end -$var wire 1 S A1 $end -$var wire 1 T A2 $end -$var wire 1 U A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 V D $end -$var wire 1 W Q $end -$var reg 16 X data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[2] $end -$scope module srl16e $end -$var wire 1 Y A0 $end -$var wire 1 Z A1 $end -$var wire 1 [ A2 $end -$var wire 1 \ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ] D $end -$var wire 1 ^ Q $end -$var reg 16 _ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[3] $end -$scope module srl16e $end -$var wire 1 ` A0 $end -$var wire 1 a A1 $end -$var wire 1 b A2 $end -$var wire 1 c A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 d D $end -$var wire 1 e Q $end -$var reg 16 f data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[4] $end -$scope module srl16e $end -$var wire 1 g A0 $end -$var wire 1 h A1 $end -$var wire 1 i A2 $end -$var wire 1 j A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 k D $end -$var wire 1 l Q $end -$var reg 16 m data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[5] $end -$scope module srl16e $end -$var wire 1 n A0 $end -$var wire 1 o A1 $end -$var wire 1 p A2 $end -$var wire 1 q A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 r D $end -$var wire 1 s Q $end -$var reg 16 t data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[6] $end -$scope module srl16e $end -$var wire 1 u A0 $end -$var wire 1 v A1 $end -$var wire 1 w A2 $end -$var wire 1 x A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 y D $end -$var wire 1 z Q $end -$var reg 16 { data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[7] $end -$scope module srl16e $end -$var wire 1 | A0 $end -$var wire 1 } A1 $end -$var wire 1 ~ A2 $end -$var wire 1 !" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 "" D $end -$var wire 1 #" Q $end -$var reg 16 $" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[8] $end -$scope module srl16e $end -$var wire 1 %" A0 $end -$var wire 1 &" A1 $end -$var wire 1 '" A2 $end -$var wire 1 (" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 )" D $end -$var wire 1 *" Q $end -$var reg 16 +" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[9] $end -$scope module srl16e $end -$var wire 1 ," A0 $end -$var wire 1 -" A1 $end -$var wire 1 ." A2 $end -$var wire 1 /" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 0" D $end -$var wire 1 1" Q $end -$var reg 16 2" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[10] $end -$scope module srl16e $end -$var wire 1 3" A0 $end -$var wire 1 4" A1 $end -$var wire 1 5" A2 $end -$var wire 1 6" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 7" D $end -$var wire 1 8" Q $end -$var reg 16 9" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[11] $end -$scope module srl16e $end -$var wire 1 :" A0 $end -$var wire 1 ;" A1 $end -$var wire 1 <" A2 $end -$var wire 1 =" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 >" D $end -$var wire 1 ?" Q $end -$var reg 16 @" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[12] $end -$scope module srl16e $end -$var wire 1 A" A0 $end -$var wire 1 B" A1 $end -$var wire 1 C" A2 $end -$var wire 1 D" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 E" D $end -$var wire 1 F" Q $end -$var reg 16 G" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[13] $end -$scope module srl16e $end -$var wire 1 H" A0 $end -$var wire 1 I" A1 $end -$var wire 1 J" A2 $end -$var wire 1 K" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 L" D $end -$var wire 1 M" Q $end -$var reg 16 N" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[14] $end -$scope module srl16e $end -$var wire 1 O" A0 $end -$var wire 1 P" A1 $end -$var wire 1 Q" A2 $end -$var wire 1 R" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 S" D $end -$var wire 1 T" Q $end -$var reg 16 U" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[15] $end -$scope module srl16e $end -$var wire 1 V" A0 $end -$var wire 1 W" A1 $end -$var wire 1 X" A2 $end -$var wire 1 Y" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 Z" D $end -$var wire 1 [" Q $end -$var reg 16 \" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[16] $end -$scope module srl16e $end -$var wire 1 ]" A0 $end -$var wire 1 ^" A1 $end -$var wire 1 _" A2 $end -$var wire 1 `" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 a" D $end -$var wire 1 b" Q $end -$var reg 16 c" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[17] $end -$scope module srl16e $end -$var wire 1 d" A0 $end -$var wire 1 e" A1 $end -$var wire 1 f" A2 $end -$var wire 1 g" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 h" D $end -$var wire 1 i" Q $end -$var reg 16 j" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[18] $end -$scope module srl16e $end -$var wire 1 k" A0 $end -$var wire 1 l" A1 $end -$var wire 1 m" A2 $end -$var wire 1 n" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 o" D $end -$var wire 1 p" Q $end -$var reg 16 q" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[19] $end -$scope module srl16e $end -$var wire 1 r" A0 $end -$var wire 1 s" A1 $end -$var wire 1 t" A2 $end -$var wire 1 u" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 v" D $end -$var wire 1 w" Q $end -$var reg 16 x" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[20] $end -$scope module srl16e $end -$var wire 1 y" A0 $end -$var wire 1 z" A1 $end -$var wire 1 {" A2 $end -$var wire 1 |" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 }" D $end -$var wire 1 ~" Q $end -$var reg 16 !# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[21] $end -$scope module srl16e $end -$var wire 1 "# A0 $end -$var wire 1 ## A1 $end -$var wire 1 $# A2 $end -$var wire 1 %# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 &# D $end -$var wire 1 '# Q $end -$var reg 16 (# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[22] $end -$scope module srl16e $end -$var wire 1 )# A0 $end -$var wire 1 *# A1 $end -$var wire 1 +# A2 $end -$var wire 1 ,# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 -# D $end -$var wire 1 .# Q $end -$var reg 16 /# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[23] $end -$scope module srl16e $end -$var wire 1 0# A0 $end -$var wire 1 1# A1 $end -$var wire 1 2# A2 $end -$var wire 1 3# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 4# D $end -$var wire 1 5# Q $end -$var reg 16 6# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[24] $end -$scope module srl16e $end -$var wire 1 7# A0 $end -$var wire 1 8# A1 $end -$var wire 1 9# A2 $end -$var wire 1 :# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ;# D $end -$var wire 1 <# Q $end -$var reg 16 =# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[25] $end -$scope module srl16e $end -$var wire 1 ># A0 $end -$var wire 1 ?# A1 $end -$var wire 1 @# A2 $end -$var wire 1 A# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 B# D $end -$var wire 1 C# Q $end -$var reg 16 D# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[26] $end -$scope module srl16e $end -$var wire 1 E# A0 $end -$var wire 1 F# A1 $end -$var wire 1 G# A2 $end -$var wire 1 H# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 I# D $end -$var wire 1 J# Q $end -$var reg 16 K# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[27] $end -$scope module srl16e $end -$var wire 1 L# A0 $end -$var wire 1 M# A1 $end -$var wire 1 N# A2 $end -$var wire 1 O# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 P# D $end -$var wire 1 Q# Q $end -$var reg 16 R# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[28] $end -$scope module srl16e $end -$var wire 1 S# A0 $end -$var wire 1 T# A1 $end -$var wire 1 U# A2 $end -$var wire 1 V# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 W# D $end -$var wire 1 X# Q $end -$var reg 16 Y# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[29] $end -$scope module srl16e $end -$var wire 1 Z# A0 $end -$var wire 1 [# A1 $end -$var wire 1 \# A2 $end -$var wire 1 ]# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ^# D $end -$var wire 1 _# Q $end -$var reg 16 `# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[30] $end -$scope module srl16e $end -$var wire 1 a# A0 $end -$var wire 1 b# A1 $end -$var wire 1 c# A2 $end -$var wire 1 d# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 e# D $end -$var wire 1 f# Q $end -$var reg 16 g# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[31] $end -$scope module srl16e $end -$var wire 1 h# A0 $end -$var wire 1 i# A1 $end -$var wire 1 j# A2 $end -$var wire 1 k# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 l# D $end -$var wire 1 m# Q $end -$var reg 16 n# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[32] $end -$scope module srl16e $end -$var wire 1 o# A0 $end -$var wire 1 p# A1 $end -$var wire 1 q# A2 $end -$var wire 1 r# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 s# D $end -$var wire 1 t# Q $end -$var reg 16 u# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[33] $end -$scope module srl16e $end -$var wire 1 v# A0 $end -$var wire 1 w# A1 $end -$var wire 1 x# A2 $end -$var wire 1 y# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 z# D $end -$var wire 1 {# Q $end -$var reg 16 |# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[34] $end -$scope module srl16e $end -$var wire 1 }# A0 $end -$var wire 1 ~# A1 $end -$var wire 1 !$ A2 $end -$var wire 1 "$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 #$ D $end -$var wire 1 $$ Q $end -$var reg 16 %$ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[35] $end -$scope module srl16e $end -$var wire 1 &$ A0 $end -$var wire 1 '$ A1 $end -$var wire 1 ($ A2 $end -$var wire 1 )$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 *$ D $end -$var wire 1 +$ Q $end -$var reg 16 ,$ data [15:0] $end -$upscope $end -$upscope $end -$upscope $end -$scope module fifo36_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 -$ f19_dataout [18:0] $end -$var wire 1 ' f19_dst_rdy_i $end -$var wire 1 ( f19_src_rdy_o $end -$var wire 1 .$ f19_xfer $end -$var wire 36 /$ f36_datain [35:0] $end -$var wire 1 $ f36_dst_rdy_o $end -$var wire 1 0$ f36_eof $end -$var wire 1 1$ f36_occ $end -$var wire 1 2$ f36_sof $end -$var wire 1 % f36_src_rdy_i $end -$var wire 1 3$ f36_xfer $end -$var wire 1 4$ half_line $end -$var wire 1 C reset $end -$var reg 1 5$ phase $end -$upscope $end -$scope module fifo19_to_ll8 $end -$var wire 1 6$ advance $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 7$ f19_data [18:0] $end -$var wire 1 ' f19_dst_rdy_o $end -$var wire 1 8$ f19_eof $end -$var wire 1 9$ f19_occ $end -$var wire 1 :$ f19_sof $end -$var wire 1 ( f19_src_rdy_i $end -$var wire 1 ;$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 <$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 =$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 >$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var reg 8 ?$ ll_data [7:0] $end -$var reg 1 @$ state $end -$upscope $end -$scope module ll8_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 A$ f19_data [18:0] $end -$var wire 1 * f19_dst_rdy_i $end -$var wire 1 + f19_src_rdy_o $end -$var wire 8 B$ ll_data [7:0] $end -$var wire 1 C$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 D$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 E$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 F$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var wire 1 G$ xfer_out $end -$var reg 8 H$ dat0 [7:0] $end -$var reg 8 I$ dat1 [7:0] $end -$var reg 1 J$ f19_eof $end -$var reg 1 K$ f19_occ $end -$var reg 1 L$ f19_sof $end -$var reg 2 M$ state [1:0] $end -$upscope $end -$scope module fifo19_to_fifo36 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 N$ f19_datain [18:0] $end -$var wire 1 * f19_dst_rdy_o $end -$var wire 1 O$ f19_eof $end -$var wire 1 P$ f19_occ $end -$var wire 1 Q$ f19_sof $end -$var wire 1 + f19_src_rdy_i $end -$var wire 36 R$ f36_dataout [35:0] $end -$var wire 1 S$ f36_dst_rdy_i $end -$var wire 1 - f36_src_rdy_o $end -$var wire 1 C reset $end -$var wire 1 T$ xfer_out $end -$var reg 16 U$ dat0 [15:0] $end -$var reg 16 V$ dat1 [15:0] $end -$var reg 1 W$ f36_eof $end -$var reg 1 X$ f36_occ $end -$var reg 1 Y$ f36_sof $end -$var reg 2 Z$ state [1:0] $end -$upscope $end -$scope task PutPacketInFIFO36 $end -$var reg 32 [$ data_len [31:0] $end -$var reg 32 \$ data_start [31:0] $end -$upscope $end -$scope task ReadFromFIFO36 $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx \$ -bx [$ -bx Z$ -xY$ -xX$ -xW$ -bx V$ -bx U$ -0T$ -0S$ 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a/usrp2/fifo/fifo_tb.v +++ b/usrp2/fifo/fifo_tb.v @@ -24,20 +24,39 @@ module fifo_new_tb(); wire i1_sr, i1_dr; wire i2_sr, i2_dr; wire i3_sr, i3_dr; + wire i7_sr, i7_dr; + reg i4_dr = 0; wire i4_sr; - wire [35:0] i1, i4; + wire [35:0] i1, i4, i7; wire [18:0] i2, i3; wire [7:0] ll_data; wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n; + wire [35:0] err_dat; + wire err_src_rdy, err_dst_rdy; + + reg trigger = 0; + initial #10000 trigger = 1; fifo_short #(.WIDTH(36)) fifo_short1 (.clk(clk),.reset(rst),.clear(clear), .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), - .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) ); + .dataout(i7),.src_rdy_o(i7_sr),.dst_rdy_i(i7_dr) ); + gen_context_pkt #(.PROT_ENG_FLAGS(1)) gcp + (.clk(clk),.reset(rst),.clear(clear), + .trigger(trigger), .sent(), + .streamid(32'hDEAD_F00D), .vita_time(64'h01234567_89ABCDEF), .message(32'hBEEF_2940), + .data_o(err_dat), .src_rdy_o(err_src_rdy), .dst_rdy_i(err_dst_rdy)); + + fifo36_mux #(.prio(0)) fifo36_mux + (.clk(clk), .reset(rst), .clear(clear), + .data0_i(i7), .src0_rdy_i(i7_sr), .dst0_rdy_o(i7_dr), + .data1_i(err_dat), .src1_rdy_i(err_src_rdy), .dst1_rdy_o(err_dst_rdy), + .data_o(i1), .src_rdy_o(i1_sr), .dst_rdy_i(i1_dr)); + fifo36_to_fifo19 fifo36_to_fifo19 (.clk(clk),.reset(rst),.clear(clear), .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr), @@ -59,7 +78,7 @@ module fifo_new_tb(); (.clk(clk),.reset(rst),.clear(clear), .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr), .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) ); - + task ReadFromFIFO36; begin $display("Read from FIFO36"); diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index d0435fa1e..4da64ac28 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -47,7 +47,7 @@ $(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) @echo $@ $(ISE_HELPER) "" -$(BIN_FILE): $(ISE_FILE) +$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) @echo $@ $(ISE_HELPER) "Generate Programming File" touch $@ diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b034791a7..124930c23 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -423,7 +423,10 @@ module u2_core cycle_count <= 0; else cycle_count <= cycle_count + 1; - + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd1; + wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), @@ -431,7 +434,7 @@ module u2_core .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// @@ -466,11 +469,20 @@ module u2_core .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), .debug(debug_udp) ); + wire [35:0] tx_err_data, udp1_tx_data; + wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), @@ -639,40 +651,26 @@ module u2_core // DSP TX wire [35:0] tx_data; - wire [99:0] tx1_data; - wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; - - wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time),.underrun(underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); - - assign debug_vt = debug_vtc | debug_vtd; - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); - + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + assign dsp_rst = wb_rst; // /////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs index 07c62224b..dc4bd8c96 100644 --- a/usrp2/vrt/Makefile.srcs +++ b/usrp2/vrt/Makefile.srcs @@ -10,4 +10,6 @@ vita_rx_control.v \ vita_rx_framer.v \ vita_tx_control.v \ vita_tx_deframer.v \ +vita_tx_chain.v \ +gen_context_pkt.v \ )) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v new file mode 100644 index 000000000..780a027ba --- /dev/null +++ b/usrp2/vrt/gen_context_pkt.v @@ -0,0 +1,72 @@ + + +module gen_context_pkt + #(parameter PROT_ENG_FLAGS=1) + (input clk, input reset, input clear, + input trigger, output sent, + input [31:0] streamid, + input [63:0] vita_time, + input [31:0] message, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + localparam CTXT_IDLE = 0; + localparam CTXT_PROT_ENG = 1; + localparam CTXT_HEADER = 2; + localparam CTXT_STREAMID = 3; + localparam CTXT_SECS = 4; + localparam CTXT_TICS = 5; + localparam CTXT_TICS2 = 6; + localparam CTXT_MESSAGE = 7; + localparam CTXT_DONE = 8; + + reg [33:0] data_int; + wire src_rdy_int, dst_rdy_int; + wire [3:0] seqno = 0; + reg [3:0] ctxt_state; + reg [63:0] err_time; + + always @(posedge clk) + if(reset | clear) + ctxt_state <= CTXT_IDLE; + else + case(ctxt_state) + CTXT_IDLE : + if(trigger) + begin + err_time <= vita_time; + if(PROT_ENG_FLAGS) + ctxt_state <= CTXT_PROT_ENG; + else + ctxt_state <= CTXT_HEADER; + end + + CTXT_DONE : + if(~trigger) + ctxt_state <= CTXT_IDLE; + + default : + if(dst_rdy_int) + ctxt_state <= ctxt_state + 1; + endcase // case (ctxt_state) + + assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); + + always @* + case(ctxt_state) + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd24 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd6 }; + CTXT_STREAMID : data_int <= { 2'b00, streamid }; + CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; + CTXT_TICS : data_int <= { 2'b00, 32'd0 }; + CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; + CTXT_MESSAGE : data_int <= { 2'b10, message }; + default : data_int <= {2'b00, 32'b00}; + endcase // case (ctxt_state) + + fifo_short #(.WIDTH(34)) ctxt_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + assign data_o[35:34] = 2'b00; + +endmodule // gen_context_pkt diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v index fd82263d0..235817941 100644 --- a/usrp2/vrt/vita_rx_framer.v +++ b/usrp2/vrt/vita_rx_framer.v @@ -128,7 +128,7 @@ module vita_rx_framer VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0}; VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]}; - VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b11,28'd0,flags_fifo_o}; + VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o}; //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer}; default : pkt_fifo_line <= 34'h0_FFFF_FFFF; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v new file mode 100644 index 000000000..662cdca62 --- /dev/null +++ b/usrp2/vrt/vita_tx_chain.v @@ -0,0 +1,71 @@ + +module vita_tx_chain + #(parameter BASE_CTRL=0, + parameter BASE_DSP=0, + parameter REPORT_ERROR=0, + parameter PROT_ENG_FLAGS=0) + (input clk, input reset, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [63:0] vita_time, + input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, + output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i, + output [15:0] dac_a, output [15:0] dac_b, + output underrun, output run, + output [31:0] debug); + + localparam MAXCHAN = 1; + localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); + + wire [FIFOWIDTH-1:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire clear_vita; + wire [31:0] sample_tx; + wire [31:0] streamid, message; + wire trigger, sent; + wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; + + wire error; + wire [31:0] error_code; + wire clear_seqnum; + + assign underrun = error; + assign message = error_code; + + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(streamid),.changed(clear_seqnum)); + + vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer + (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time),.error(error),.error_code(error_code), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run), .strobe(strobe_tx), + .debug(debug_vtc) ); + + dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx + (.clk(clk),.rst(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample(sample_tx), .run(run), .strobe(strobe_tx), + .dac_a(dac_a),.dac_b(dac_b), + .debug(debug_tx_dsp) ); + + generate + if(REPORT_ERROR==1) + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(error), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + endgenerate + + assign debug = debug_vtc | debug_vtd; + +endmodule // vita_tx_chain diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index bffc64e52..d0516bec8 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -6,10 +6,11 @@ module vita_tx_control input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, - output underrun, + output error, + output reg [31:0] error_code, // From vita_tx_deframer - input [4+64+WIDTH-1:0] sample_fifo_i, + input [5+64+16+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, output sample_fifo_dst_rdy_o, @@ -20,14 +21,17 @@ module vita_tx_control output [31:0] debug ); - - assign sample = sample_fifo_i[4+64+WIDTH-1:4+64]; + + assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16]; wire [63:0] send_time = sample_fifo_i[63:0]; - wire eop = sample_fifo_i[64]; - wire eob = sample_fifo_i[65]; - wire sob = sample_fifo_i[66]; - wire send_at = sample_fifo_i[67]; + wire [15:0] seqnum = sample_fifo_i[79:64]; + wire eop = sample_fifo_i[80]; + wire eob = sample_fifo_i[81]; + wire sob = sample_fifo_i[82]; + wire send_at = sample_fifo_i[83]; + wire seqnum_err = sample_fifo_i[84]; + wire now, early, late, too_early; // FIXME ignore too_early for now for timing reasons @@ -40,8 +44,15 @@ module vita_tx_control localparam IBS_IDLE = 0; localparam IBS_RUN = 1; // FIXME do we need this? localparam IBS_CONT_BURST = 2; - localparam IBS_UNDERRUN = 3; - localparam IBS_UNDERRUN_DONE = 4; + localparam IBS_ERROR = 3; + localparam IBS_ERROR_DONE = 4; + localparam IBS_ERROR_WAIT = 5; + + wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; + wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; + wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8}; + wire [31:0] CODE_UNDERRUN_MIDPKT = {seqnum,16'd16}; + wire [31:0] CODE_SEQ_ERROR_MIDBURST = {seqnum,16'd32}; reg [2:0] ibs_state; @@ -50,22 +61,49 @@ module vita_tx_control (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_state)); + wire [31:0] error_policy; + setting_reg #(.my_addr(BASE+3)) sr_error_policy + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(error_policy),.changed()); + + wire policy_wait = error_policy[0]; + wire policy_next_packet = error_policy[1]; + wire policy_next_burst = error_policy[2]; + reg send_error; + always @(posedge clk) if(reset | clear_state) - ibs_state <= 0; + begin + ibs_state <= IBS_IDLE; + send_error <= 0; + end else case(ibs_state) IBS_IDLE : if(sample_fifo_src_rdy_i) - if(~send_at | now) + if(seqnum_err) + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_SEQ_ERROR; + send_error <= 1; + end + else if(~send_at | now) ibs_state <= IBS_RUN; else if(late | too_early) - ibs_state <= IBS_UNDERRUN; + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_TIME_ERROR; + send_error <= 1; + end IBS_RUN : if(strobe) if(~sample_fifo_src_rdy_i) - ibs_state <= IBS_UNDERRUN; + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_UNDERRUN_MIDPKT; + send_error <= 1; + end else if(eop) if(eob) ibs_state <= IBS_IDLE; @@ -74,24 +112,53 @@ module vita_tx_control IBS_CONT_BURST : if(strobe) - ibs_state <= IBS_UNDERRUN_DONE; + begin + if(policy_next_packet) + ibs_state <= IBS_ERROR_DONE; + else if(policy_wait) + ibs_state <= IBS_ERROR_WAIT; + else + ibs_state <= IBS_ERROR; + error_code <= CODE_UNDERRUN; + send_error <= 1; + end else if(sample_fifo_src_rdy_i) - ibs_state <= IBS_RUN; + if(seqnum_err) + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_SEQ_ERROR_MIDBURST; + send_error <= 1; + end + else + ibs_state <= IBS_RUN; - IBS_UNDERRUN : - if(sample_fifo_src_rdy_i & eop) - ibs_state <= IBS_UNDERRUN_DONE; + IBS_ERROR : + begin + send_error <= 0; + if(sample_fifo_src_rdy_i & eop) + if(policy_next_packet | (policy_next_burst & eob)) + ibs_state <= IBS_IDLE; + else if(policy_wait) + ibs_state <= IBS_ERROR_WAIT; + end - IBS_UNDERRUN_DONE : - ; + IBS_ERROR_DONE : + begin + send_error <= 0; + ibs_state <= IBS_IDLE; + end + + IBS_ERROR_WAIT : + send_error <= 0; endcase // case (ibs_state) - assign sample_fifo_dst_rdy_o = (ibs_state == IBS_UNDERRUN) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout + assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - assign underrun = (ibs_state == IBS_UNDERRUN_DONE); + //assign error = (ibs_state == IBS_ERROR_DONE); + assign error = send_error; assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, - { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, underrun, ibs_state[2:0] }, + { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, { 8'b0 } }; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 3b95f5902..f9cd7d00d 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -2,7 +2,7 @@ module vita_tx_deframer #(parameter BASE=0, parameter MAXCHAN=1) - (input clk, input reset, input clear, + (input clk, input reset, input clear, input clear_seqnum, input set_stb, input [7:0] set_addr, input [31:0] set_data, // To FIFO interface of Buffer Pool @@ -10,7 +10,7 @@ module vita_tx_deframer input src_rdy_i, output dst_rdy_o, - output [4+64+(32*MAXCHAN)-1:0] sample_fifo_o, + output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, @@ -21,6 +21,8 @@ module vita_tx_deframer output [31:0] debug ); + localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); + wire [1:0] numchan; setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), @@ -36,14 +38,18 @@ module vita_tx_deframer assign is_sob = data_i[25]; assign is_eob = data_i[24]; wire eof = data_i[33]; - reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg; reg has_trailer_reg, is_sob_reg, is_eob_reg; - + reg [15:0] pkt_len; reg [1:0] vector_phase; wire line_done; + reg seqnum_err; + reg [3:0] seqnum_reg; + wire [3:0] seqnum = data_i[19:16]; + wire [3:0] next_seqnum = seqnum_reg + 4'd1; + // Output FIFO for packetized data localparam VITA_HEADER = 0; localparam VITA_STREAMID = 1; @@ -61,6 +67,13 @@ module vita_tx_deframer wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets? wire fifo_space; + + always @(posedge clk) + if(reset | clear_seqnum) + seqnum_reg <= 4'hF; + else + if((vita_state==VITA_HEADER) & src_rdy_i) + seqnum_reg <= seqnum; always @(posedge clk) if(reset | clear) @@ -68,6 +81,7 @@ module vita_tx_deframer vita_state <= VITA_HEADER; {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; + seqnum_err <= 0; end else if((vita_state == VITA_STORE) & fifo_space) @@ -99,6 +113,7 @@ module vita_tx_deframer vita_state <= VITA_TICS; else vita_state <= VITA_PAYLOAD; + seqnum_err <= ~(seqnum == next_seqnum); end // case: VITA_HEADER VITA_STREAMID : if(has_classid_reg) @@ -145,7 +160,7 @@ module vita_tx_deframer assign line_done = (vector_phase == numchan); - wire [4+64+32*MAXCHAN-1:0] fifo_i; + wire [FIFOWIDTH-1:0] fifo_i; reg [63:0] send_time; reg [31:0] sample_a, sample_b, sample_c, sample_d; @@ -169,13 +184,14 @@ module vita_tx_deframer endcase // case (vector_phase) wire store = (vita_state == VITA_STORE); - fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q + fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) ); // sob, eob, has_secs (send_at) ignored on all lines except first - assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time}; + assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop, + 12'd0,seqnum_reg,send_time}; assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; -- cgit v1.2.3 From 7d602e283bc30669df6c155f1abe5196a272b9b4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 19 Aug 2010 13:08:23 -0700 Subject: properly integrate the new tx chain --- usrp2/top/u1e/u1e_core.v | 58 ++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 63488f549..33020ad5a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -59,8 +59,9 @@ module u1e_core wire [31:0] debug_gpmc; - wire [35:0] tx_data, rx_data; - wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; wire [7:0] rate; @@ -109,7 +110,7 @@ module u1e_core assign tx_underrun = 0; assign rx_overrun = 0; - wire run_tx, run_rx, strobe_tx, strobe_rx, tx1_src_rdy, tx1_dst_rdy; + wire run_tx, run_rx, strobe_tx, strobe_rx; wire [31:0] debug_vtd, debug_vtc; `endif // LOOPBACK @@ -154,8 +155,9 @@ module u1e_core wire rx1_dst_rdy, rx1_src_rdy; wire [99:0] rx1_data; wire run_rx; - - + wire [35:0] vita_rx_data; + wire vita_rx_src_rdy, vita_rx_dst_rdy; + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -175,41 +177,35 @@ module u1e_core (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), - .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), + .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), .fifo_occupied(), .fifo_full(), .fifo_empty(), .debug_rx(vrf_debug) ); - + + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + // /////////////////////////////////////////////////////////////////////////////////// // DSP TX - wire [99:0] tx1_data; - wire tx1_src_rdy, tx1_dst_rdy; wire [15:0] tx_i_int, tx_q_int; wire [31:0] debug_vtc, debug_vtd, debug_vt; wire run_tx; - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.underrun(tx_underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(wb_clk),.rst(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .debug(debug_tx_dsp) ); - + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; @@ -438,7 +434,7 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, - {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; + {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; assign debug_gpio_1 = debug_vtd | debug_vtc; -- cgit v1.2.3 From 2c70f2bdd17708321d0ce2010f8471900ca4349a Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Fri, 20 Aug 2010 15:29:53 -0700 Subject: Added 12mA current spec to eth phy LED pin. Changed debug pins to debug ICAP instead of VITA -- which makes it actually meet timing, too. Bonus. --- usrp2/top/u2plus/u2plus.ucf | 2 +- usrp2/top/u2plus/u2plus_core.v | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index 00838e19d..aee9e57bf 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -250,7 +250,7 @@ NET "PHY_INTn" LOC = "L22" ; NET "MDIO" LOC = "K21" ; NET "MDC" LOC = "J23" ; NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" ; +NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; ## MIMO Interface NET "exp_time_out_p" LOC = "Y14" ; diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 1db7e5b79..ee9d206d8 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -815,7 +815,8 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ // Debug Pins assign debug_clk = {dsp_clk, wb_clk}; - assign debug = debug_vt; +// assign debug = debug_vt; + assign debug = {wb_clk, wb_rst, sd_cyc, sd_stb, sd_we, sd_ack, sd_dat_o[7:0], sd_dat_i[7:0], 10'd0}; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; -- cgit v1.2.3 From 105efcdfc21f760e9615e9a3221ef6ae13b01f1c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 23 Aug 2010 17:12:43 -0700 Subject: debug pins cleanup --- usrp2/top/u1e/u1e_core.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 33020ad5a..ff9a846b5 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -111,7 +111,6 @@ module u1e_core assign rx_overrun = 0; wire run_tx, run_rx, strobe_tx, strobe_rx; - wire [31:0] debug_vtd, debug_vtc; `endif // LOOPBACK `ifdef TIMED @@ -191,7 +190,7 @@ module u1e_core // DSP TX wire [15:0] tx_i_int, tx_q_int; - wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire [31:0] debug_vt; wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), @@ -429,6 +428,7 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; @@ -436,7 +436,7 @@ module u1e_core assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; - assign debug_gpio_1 = debug_vtd | debug_vtc; + assign debug_gpio_1 = debug_vt; /* assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, -- cgit v1.2.3 From 87a64f5979e712fd0fa30cf0676f3c395599ff69 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 23 Aug 2010 19:20:02 -0700 Subject: match the signal names in this design --- usrp2/top/u1e/u1e_core.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ff9a846b5..eda4e463d 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -181,7 +181,7 @@ module u1e_core .debug_rx(vrf_debug) ); fifo36_mux #(.prio(0)) mux_err_stream - (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(0), .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); @@ -196,8 +196,8 @@ module u1e_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), -- cgit v1.2.3 From 743ea16da4eef07cf9956f4098fc4b959e689c00 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 24 Aug 2010 12:08:22 -0700 Subject: no need for protocol headers since we're not doing ethernet --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index eda4e463d..d7c4ff509 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -194,7 +194,7 @@ module u1e_core wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) vita_tx_chain (.clk(wb_clk), .reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), -- cgit v1.2.3 From e5c97b4a2cdccf0d87c585cf807945e4f58e58a7 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Tue, 24 Aug 2010 13:25:36 -0700 Subject: Ensure ethernet LED pin has 12mA output --- usrp2/top/u2plus/u2plus.ucf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index aee9e57bf..a9ff9413d 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -250,7 +250,7 @@ NET "PHY_INTn" LOC = "L22" ; NET "MDIO" LOC = "K21" ; NET "MDC" LOC = "J23" ; NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ETH_LEd" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; ## MIMO Interface NET "exp_time_out_p" LOC = "Y14" ; -- cgit v1.2.3 From d0815967a27d01059230679e2d635377ac8c18b3 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Tue, 24 Aug 2010 13:36:48 -0700 Subject: Added a sanity checker Python script. The script just looks for input/inout/outputs that are declared in the .v but not in the .ucf. If it finds an occurrence, it aborts the compile. Removed pin "POR" from u2plus.v due to the script. Also reverted an error I introduced to test the script, which I mistakenly committed earlier. --- usrp2/top/Makefile.common | 4 ++- usrp2/top/python/check_inout.py | 62 +++++++++++++++++++++++++++++++++++++++++ usrp2/top/u2plus/u2plus.ucf | 2 +- usrp2/top/u2plus/u2plus.v | 2 +- 4 files changed, 67 insertions(+), 3 deletions(-) create mode 100755 usrp2/top/python/check_inout.py diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index 2f6b5fde3..0e08b800e 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -13,6 +13,7 @@ else endif BASE_DIR = $(abspath ..) ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl +SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit @@ -26,12 +27,13 @@ all: bin proj: $(ISE_FILE) check: $(ISE_FILE) + $(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf $(ISE_HELPER) "Check Syntax" synth: $(ISE_FILE) $(ISE_HELPER) "Synthesize - XST" -bin: $(BIN_FILE) +bin: check $(BIN_FILE) mcs: $(MCS_FILE) diff --git a/usrp2/top/python/check_inout.py b/usrp2/top/python/check_inout.py new file mode 100755 index 000000000..ff371d378 --- /dev/null +++ b/usrp2/top/python/check_inout.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# Description: +# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf. +# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes + +import sys +import re + +if __name__=='__main__': + if len(sys.argv) == 2: + print "Usage: %s " + sys.exit(-1) + + verilog_filename = sys.argv[1] + ucf_filename = sys.argv[2] + + verilog_file = open(verilog_filename, 'r') + ucf_file = open(ucf_filename, 'r') + + verilog_iolist = list() + ucf_iolist = list() + + #read in all input, inout, and output declarations and compile a list + for line in verilog_file: + for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]): + verilog_iolist.append(match) + + for line in ucf_file: + m = re.search(r"""NET "(\w+).*" """, line.split("#")[0]) + if m is not None: + ucf_iolist.append(m.group(1)) + + #now find corresponding matches and error when you don't find one + #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem + err = False + + for item in verilog_iolist: + if item not in ucf_iolist: + print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item + err = True + + if err: + sys.exit(-1) + + print "No errors found." + sys.exit(0) diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index a9ff9413d..aee9e57bf 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -250,7 +250,7 @@ NET "PHY_INTn" LOC = "L22" ; NET "MDIO" LOC = "K21" ; NET "MDC" LOC = "J23" ; NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LEd" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; ## MIMO Interface NET "exp_time_out_p" LOC = "Y14" ; diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index a0ba4d4cc..3641ce962 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -83,7 +83,7 @@ module u2plus output PHY_RESETn, output ETH_LED, - input POR, +// input POR, // Expansion input exp_time_in_p, input exp_time_in_n, // Diff -- cgit v1.2.3 From 2e526a8411f97654a2e87bdd1e524729da71315e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 25 Aug 2010 18:44:56 -0700 Subject: Use new tx_policy stuff, reassigned leds to be just like U2 --- usrp2/top/u2plus/u2plus.v | 2 +- usrp2/top/u2plus/u2plus_core.v | 68 ++++++++++++++++++++---------------------- 2 files changed, 34 insertions(+), 36 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 3641ce962..d330e336b 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -220,7 +220,7 @@ module u2plus // LEDs are active low outputs wire [5:0] leds_int; - assign {leds,ETH_LED} = {6'b111110 ^ leds_int}; // drive low to turn on leds + assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds // SPI wire miso, mosi, sclk; diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index ee9d206d8..e394e68af 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -173,6 +173,7 @@ module u2plus_core wire epoch; wire [31:0] irq; wire [63:0] vita_time; + wire run_rx, run_tx; // /////////////////////////////////////////////////////////////////////////////////////////////// // Wishbone Single Master INTERCON @@ -527,8 +528,7 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) - ); + .gpio( {io_tx,io_rx} ) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -539,7 +539,10 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ cycle_count <= 0; else cycle_count <= cycle_count + 1; - + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd2; + wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), @@ -547,7 +550,7 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// @@ -582,11 +585,20 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), .debug(debug_udp) ); + wire [35:0] tx_err_data, udp1_tx_data; + wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), @@ -630,12 +642,13 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ // In Rev3 there are only 6 leds, and the highest one is on the ETH connector wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; + wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); + + setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); @@ -678,7 +691,6 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ // ///////////////////////////////////////////////////////////////////////// // ATR Controller, Slave #11 - wire run_rx, run_tx; reg run_rx_d1; always @(posedge dsp_clk) run_rx_d1 <= run_rx; @@ -755,40 +767,26 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_ // DSP TX wire [35:0] tx_data; - wire [99:0] tx1_data; - wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; - - wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time),.underrun(underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); - - assign debug_vt = debug_vtc | debug_vtd; - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); - + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + assign dsp_rst = wb_rst; // /////////////////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 9e2e78642251ee9e024461becfd70a75b11d818a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 25 Aug 2010 19:00:02 -0700 Subject: SWAP DAC A and B, invert B to match schematics --- usrp2/top/u2plus/u2plus.v | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index d330e336b..db31b4a68 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -298,10 +298,11 @@ module u2plus */ wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) DACA <= ~dac_b_int; + always @(negedge dsp_clk) DACB <= dac_a_int; - always @(negedge dsp_clk) DACA <= dac_a_int; - always @(negedge dsp_clk) DACB <= dac_b_int; - u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), -- cgit v1.2.3 From ea545df8aa9da7b647160d59a0f33a35d9ec1378 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 25 Aug 2010 19:04:47 -0700 Subject: invert adc_a because it is inverted on schematic. Also clean up extraneous adc signals from old adc on U2 --- usrp2/top/u2plus/u2plus.v | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index db31b4a68..66cb8005c 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -155,25 +155,28 @@ module u2plus always @(posedge clk_fpga) clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - + + // ADC A is inverted on the schematic to facilitate a clean layout + // We account for that here by inverting it `ifdef LVDS - wire [13:0] adc_a, adc_b; - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + wire [13:0] adc_a, adc_a_inv, adc_b; + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a,adc_b})); + .out({adc_a_inv,adc_b})); + assign adc_a = ~adc_a_inv; `else - reg [13:0] adc_a, adc_b; + reg [13:0] adc_a, adc_b; always @(posedge dsp_clk) - begin - adc_a <= {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + begin + adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; - adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; - end + end `endif // !`ifdef LVDS // Handle Clocks @@ -341,13 +344,13 @@ module u2plus .ser_rklsb (ser_rklsb_int), .ser_rkmsb (ser_rkmsb_int), .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), + .adc_ovf_a (1'b0), + .adc_on_a (), + .adc_oe_a (), .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), + .adc_ovf_b (1'b0), + .adc_on_b (), + .adc_oe_b (), .dac_a (dac_a_int[15:0]), .dac_b (dac_b_int[15:0]), .scl_pad_i (scl_pad_i), -- cgit v1.2.3 From 94e9baee9598f304b0e6918894876b16ffc8b2d7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 27 Aug 2010 14:59:33 -0700 Subject: move declaration to make loopback compile --- usrp2/top/u1e/u1e_core.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index d7c4ff509..4a80fe916 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -46,6 +46,8 @@ module u1e_core wire [31:0] set_data; wire set_stb; + wire [31:0] debug_vt; + // ///////////////////////////////////////////////////////////////////////////////////// // GPMC Slave to Wishbone Master localparam dw = 16; @@ -190,7 +192,6 @@ module u1e_core // DSP TX wire [15:0] tx_i_int, tx_q_int; - wire [31:0] debug_vt; wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), -- cgit v1.2.3 From f810520cc06401d535708b1d4d832309d7bc47f5 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Fri, 27 Aug 2010 16:09:20 -0700 Subject: Fixed PPS. Instantiation was miscapitalized. --- usrp2/top/u2plus/u2plus.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 66cb8005c..90dbe9d55 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -310,7 +310,7 @@ module u2plus .wb_clk (wb_clk), .clock_ready (clock_ready), .clk_to_mac (CLK_TO_MAC_int2), - .pps_in (pps_in), + .pps_in (PPS_IN), .leds (leds_int), .debug (debug[31:0]), .debug_clk (debug_clk[1:0]), -- cgit v1.2.3 From c3cd5ccbf38294a3dd4ae1e386ddefb2071f59b6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 30 Aug 2010 15:11:05 -0700 Subject: add register to tell host about compatibility level and which image we are using --- usrp2/top/u1e/u1e_core.v | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4a80fe916..5c4b6de6c 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -34,7 +34,9 @@ module u1e_core localparam SR_TX_DSP = 17; // 5 regs localparam SR_TX_CTRL = 24; // 2 regs localparam SR_TIME64 = 28; // 4 regs - + + wire COMPAT_NUM = 8'd2; + wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; @@ -104,6 +106,8 @@ module u1e_core wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; `ifdef LOOPBACK + wire [7:0] WHOAMI = 1; + fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), @@ -116,7 +120,8 @@ module u1e_core `endif // LOOPBACK `ifdef TIMED - + wire [7:0] WHOAMI = 2; + // TX side wire tx_enable; @@ -147,6 +152,8 @@ module u1e_core `endif // `ifdef TIMED `ifdef DSP + wire [7:0] WHOAMI = 0; + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; // ///////////////////////////////////////////////////////////////////////// @@ -303,9 +310,10 @@ module u1e_core localparam REG_CGEN_CTRL = 7'd4; // out localparam REG_CGEN_ST = 7'd6; // in localparam REG_TEST = 7'd8; // out - localparam REG_RX_FRAMELEN = 7'd10; // out - localparam REG_TX_FRAMELEN = 7'd12; // in - localparam REG_XFER_RATE = 7'd14; // in + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in always @(posedge wb_clk) if(wb_rst) @@ -344,6 +352,7 @@ module u1e_core (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : + (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 709d93fd675298c7d6fb3e97c60ae7258496efc4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 7 Sep 2010 19:07:34 -0700 Subject: fixed makefile to compile with our new system --- usrp2/top/u1e_passthru/Makefile | 80 +++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 44 deletions(-) diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile index 62923f87f..d1950629b 100644 --- a/usrp2/top/u1e_passthru/Makefile +++ b/usrp2/top/u1e_passthru/Makefile @@ -1,20 +1,30 @@ # # Copyright 2008 Ettus Research LLC -# +# ################################################## -# xtclsh Shell and tcl Script Path +# Project Setup ################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl +TOP_MODULE = passthru +BUILD_DIR = $(abspath build$(ISE)) ################################################## -# Project Setup +# Include other makefiles ################################################## -BUILD_DIR := build/ -export TOP_MODULE := passthru -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs ################################################## # Project Properties @@ -34,16 +44,21 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## # Sources ################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -top/u1e_passthru/passthru.ucf \ -top/u1e_passthru/passthru.v +TOP_SRCS = \ +passthru.v \ +passthru.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) ################################################## # Process Properties ################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ "Optimize Instantiated Primitives" TRUE \ @@ -52,10 +67,10 @@ export SYNTHESIZE_PROPERTIES := \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto -export TRANSLATE_PROPERTIES := \ +TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" -export MAP_PROPERTIES := \ +MAP_PROPERTIES = \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ @@ -66,14 +81,14 @@ export MAP_PROPERTIES := \ "Combinatorial Logic Optimization" TRUE \ "Register Duplication" TRUE -export PLACE_ROUTE_PROPERTIES := \ +PLACE_ROUTE_PROPERTIES = \ "Place & Route Effort Level (Overall)" High -export STATIC_TIMING_PROPERTIES := \ +STATIC_TIMING_PROPERTIES = \ "Number of Paths in Error/Verbose Report" 10 \ "Report Type" "Error Report" -export GEN_PROG_FILE_PROPERTIES := \ +GEN_PROG_FILE_PROPERTIES = \ "Configuration Rate" 6 \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ @@ -81,27 +96,4 @@ export GEN_PROG_FILE_PROPERTIES := \ "Enable Outputs (Output Events)" 6 \ "Unused IOB Pins" "Pull Up" -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - +SIM_MODEL_PROPERTIES = "" -- cgit v1.2.3 From 8db1a3901972745dfab310be77c409a82b63e941 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 9 Sep 2010 11:24:58 -0700 Subject: pins are different on rev2 --- usrp2/top/u1e_passthru/passthru.ucf | 268 +----------------------------------- 1 file changed, 4 insertions(+), 264 deletions(-) diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf index fcfce61b2..64e6f0440 100644 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -1,266 +1,6 @@ - -#NET "CLK_FPGA_P" LOC = "Y11" ; -#NET "CLK_FPGA_N" LOC = "Y10" ; - -## GPMC -#NET "EM_D<15>" LOC = "D13" ; -#NET "EM_D<14>" LOC = "D15" ; -#NET "EM_D<13>" LOC = "C16" ; -#NET "EM_D<12>" LOC = "B20" ; -#NET "EM_D<11>" LOC = "A19" ; -#NET "EM_D<10>" LOC = "A17" ; -#NET "EM_D<9>" LOC = "E15" ; -#NET "EM_D<8>" LOC = "F15" ; -#NET "EM_D<7>" LOC = "E16" ; -#NET "EM_D<6>" LOC = "F16" ; -#NET "EM_D<5>" LOC = "B17" ; -#NET "EM_D<4>" LOC = "C17" ; -#NET "EM_D<3>" LOC = "B19" ; -#NET "EM_D<2>" LOC = "D19" ; -#NET "EM_D<1>" LOC = "C19" ; -#NET "EM_D<0>" LOC = "A20" ; - -#NET "EM_A<10>" LOC = "C14" ; -#NET "EM_A<9>" LOC = "C10" ; -#NET "EM_A<8>" LOC = "C5" ; -#NET "EM_A<7>" LOC = "A18" ; -#NET "EM_A<6>" LOC = "A15" ; -#NET "EM_A<5>" LOC = "A12" ; -#NET "EM_A<4>" LOC = "A10" ; -#NET "EM_A<3>" LOC = "E7" ; -#NET "EM_A<2>" LOC = "A7" ; -#NET "EM_A<1>" LOC = "C15" ; - -#NET "EM_NCS6" LOC = "E17" ; -##NET "EM_NCS5" LOC = "E10" ; -#NET "EM_NCS4" LOC = "E6" ; -##NET "EM_NCS1" LOC = "D18" ; -##NET "EM_NCS0" LOC = "D17" ; - -#NET "EM_CLK" LOC = "F11" ; -#NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE<1>" LOC = "D14" ; -#NET "EM_NBE<0>" LOC = "A13" ; -#NET "EM_NWE" LOC = "B13" ; -#NET "EM_NOE" LOC = "A14" ; -##NET "EM_NADV_ALE" LOC = "B15" ; -##NET "EM_NWP" LOC = "F13" ; - -## Overo GPIO -#NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug -#NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug -#NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug -#NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug -#NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug -#NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug -#NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -#NET "overo_gpio127" LOC = "C8" ; # passed through as cgen_sen_b -#NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug -#NET "overo_gpio144" LOC = "A5" ; # tx_have_space -NET "overo_gpio145" LOC = "C7" ; # tx_underrun -#NET "overo_gpio146" LOC = "A6" ; # rx_have_data -#NET "overo_gpio147" LOC = "B6" ; # rx_overrun -#NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug -#NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug -#NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug - -## Overo UART -##NET "overo_txd1" LOC = "C6" ; -##NET "overo_rxd1" LOC = "D6" ; - -## FTDI UART to USB converter -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; - -##NET "SYSEN" LOC = "C11" ; - -## I2C -#NET "db_scl" LOC = "U4" ; -#NET "db_sda" LOC = "U5" ; - -## SPI -### DBoard SPI -#NET "db_sclk_rx" LOC = "W3" ; -#NET "db_miso_rx" LOC = "W2" ; -#NET "db_mosi_rx" LOC = "V4" ; -#NET "db_sen_rx" LOC = "V3" ; -#NET "db_sclk_tx" LOC = "Y1" ; -#NET "db_miso_tx" LOC = "W1" ; -#NET "db_mosi_tx" LOC = "R3" ; -#NET "db_sen_tx" LOC = "T4" ; - -### AD9862 SPI and aux SPI Interfaces -##NET "aux_sdi_codec" LOC = "F19" ; -##NET "aux_sdo_codec" LOC = "F18" ; -##NET "aux_sclk_codec" LOC = "D21" ; -#NET "sen_codec" LOC = "D20" ; -#NET "mosi_codec" LOC = "E19" ; -#NET "miso_codec" LOC = "F21" ; -#NET "sclk_codec" LOC = "E20" ; - -### Clock Gen SPI -#NET "cgen_miso" LOC = "U2" ; -NET "cgen_mosi" LOC = "V1" ; -NET "cgen_sclk" LOC = "R5" ; -NET "cgen_sen_b" LOC = "T1" ; - -## Clock gen control -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; - -## Debug pins -#NET "debug_led<2>" LOC = "T5" ; -#NET "debug_led<1>" LOC = "R2" ; -#NET "debug_led<0>" LOC = "R1" ; -#NET "debug<0>" LOC = "P6" ; -#NET "debug<1>" LOC = "R6" ; -#NET "debug<2>" LOC = "P1" ; -#NET "debug<3>" LOC = "P2" ; -#NET "debug<4>" LOC = "N6" ; -#NET "debug<5>" LOC = "N5" ; -#NET "debug<6>" LOC = "N1" ; -#NET "debug<7>" LOC = "K2" ; -#NET "debug<8>" LOC = "K3" ; -#NET "debug<9>" LOC = "K6" ; -#NET "debug<10>" LOC = "L5" ; -#NET "debug<11>" LOC = "H2" ; -#NET "debug<12>" LOC = "K4" ; -#NET "debug<13>" LOC = "K5" ; -#NET "debug<14>" LOC = "G1" ; -#NET "debug<15>" LOC = "H1" ; -#NET "debug<16>" LOC = "H5" ; -#NET "debug<17>" LOC = "H6" ; -#NET "debug<18>" LOC = "E3" ; -#NET "debug<19>" LOC = "E4" ; -#NET "debug<20>" LOC = "G5" ; -#NET "debug<21>" LOC = "G6" ; -#NET "debug<22>" LOC = "F2" ; -#NET "debug<23>" LOC = "F1" ; -#NET "debug<24>" LOC = "H3" ; -#NET "debug<25>" LOC = "H4" ; -#NET "debug<26>" LOC = "F4" ; -#NET "debug<27>" LOC = "F5" ; -#NET "debug<28>" LOC = "C2" ; -#NET "debug<29>" LOC = "C1" ; -#NET "debug<30>" LOC = "F3" ; -#NET "debug<31>" LOC = "G3" ; -#NET "debug_clk<0>" LOC = "L6" ; -#NET "debug_clk<1>" LOC = "M5" ; - -#NET "debug_pb<2>" LOC = "Y2" ; -#NET "debug_pb<1>" LOC = "AA1" ; -#NET "debug_pb<0>" LOC = "N3" ; - -#NET "dip_sw<7>" LOC = "T3" ; -#NET "dip_sw<6>" LOC = "U3" ; -#NET "dip_sw<5>" LOC = "M3" ; -#NET "dip_sw<4>" LOC = "N4" ; -#NET "dip_sw<3>" LOC = "J3" ; -#NET "dip_sw<2>" LOC = "J4" ; -#NET "dip_sw<1>" LOC = "J6" ; -#NET "dip_sw<0>" LOC = "J7" ; - -##NET "RXSYNC" LOC = "F22" ; -##NET "reset_codec" LOC = "D22" ; - -##NET "DB<11>" LOC = "E22" ; -##NET "DB<10>" LOC = "J19" ; -##NET "DB<9>" LOC = "H20" ; -##NET "DB<8>" LOC = "G19" ; -##NET "DB<7>" LOC = "F20" ; -##NET "DB<6>" LOC = "K16" ; -##NET "DB<5>" LOC = "J17" ; -##NET "DB<4>" LOC = "H22" ; -##NET "DB<3>" LOC = "G22" ; -##NET "DB<2>" LOC = "H17" ; -##NET "DB<1>" LOC = "H18" ; -##NET "DB<0>" LOC = "K20" ; -##NET "DA<11>" LOC = "J20" ; -##NET "DA<10>" LOC = "K19" ; -##NET "DA<9>" LOC = "K18" ; -##NET "DA<8>" LOC = "L22" ; -##NET "DA<7>" LOC = "K22" ; -##NET "DA<6>" LOC = "N22" ; -##NET "DA<5>" LOC = "M22" ; -##NET "DA<4>" LOC = "N20" ; -##NET "DA<3>" LOC = "N19" ; -##NET "DA<2>" LOC = "R22" ; -##NET "DA<1>" LOC = "P22" ; -##NET "DA<0>" LOC = "N17" ; - -#NET "TX<13>" LOC = "P19" ; -#NET "TX<12>" LOC = "R18" ; -#NET "TX<11>" LOC = "U20" ; -#NET "TX<10>" LOC = "T20" ; -#NET "TX<9>" LOC = "R19" ; -#NET "TX<8>" LOC = "R20" ; -#NET "TX<7>" LOC = "W22" ; -#NET "TX<6>" LOC = "Y22" ; -#NET "TX<5>" LOC = "T18" ; -#NET "TX<4>" LOC = "T17" ; -#NET "TX<3>" LOC = "W19" ; -#NET "TX<2>" LOC = "V20" ; -#NET "TX<1>" LOC = "Y21" ; -#NET "TX<0>" LOC = "AA22" ; -#NET "TXSYNC" LOC = "U18" ; -#NET "TXBLANK" LOC = "U19" ; - -#NET "PPS_IN" LOC = "M17" ; - -#NET "io_tx<0>" LOC = "AB20" ; -#NET "io_tx<1>" LOC = "Y17" ; -#NET "io_tx<2>" LOC = "Y16" ; -#NET "io_tx<3>" LOC = "U16" ; -#NET "io_tx<4>" LOC = "V16" ; -#NET "io_tx<5>" LOC = "AB19" ; -#NET "io_tx<6>" LOC = "AA19" ; -#NET "io_tx<7>" LOC = "U14" ; -#NET "io_tx<8>" LOC = "U15" ; -#NET "io_tx<9>" LOC = "AB17" ; -#NET "io_tx<10>" LOC = "AB18" ; -#NET "io_tx<11>" LOC = "Y13" ; -#NET "io_tx<12>" LOC = "W14" ; -#NET "io_tx<13>" LOC = "U13" ; -#NET "io_tx<14>" LOC = "AA15" ; -#NET "io_tx<15>" LOC = "AB14" ; - -#NET "io_rx<0>" LOC = "Y8" ; -#NET "io_rx<1>" LOC = "Y9" ; -#NET "io_rx<2>" LOC = "V7" ; -#NET "io_rx<3>" LOC = "U8" ; -#NET "io_rx<4>" LOC = "V10" ; -#NET "io_rx<5>" LOC = "U9" ; -#NET "io_rx<6>" LOC = "AB7" ; -#NET "io_rx<7>" LOC = "AA8" ; -#NET "io_rx<8>" LOC = "W8" ; -#NET "io_rx<9>" LOC = "V8" ; -#NET "io_rx<10>" LOC = "AB5" ; -#NET "io_rx<11>" LOC = "AB6" ; -#NET "io_rx<12>" LOC = "AB4" ; -#NET "io_rx<13>" LOC = "AA4" ; -#NET "io_rx<14>" LOC = "W5" ; -#NET "io_rx<15>" LOC = "Y4" ; - -##NET "CLKOUT2_CODEC" LOC = "U12" ; -##NET "CLKOUT1_CODEC" LOC = "V12" ; - -## FPGA Config Pins -##NET "fpga_cfg_prog_b" LOC = "A2" ; -##NET "fpga_cfg_done" LOC = "AB21" ; +NET "overo_gpio145" LOC = "C7" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; NET "fpga_cfg_din" LOC = "W17" ; NET "fpga_cfg_cclk" LOC = "V17" ; -##NET "fpga_cfg_init_b" LOC = "W15" ; - -## Unused -##NET "unnamed_net37" LOC = "B1" ; # TMS -##NET "unnamed_net36" LOC = "B22" ; # TDO -##NET "unnamed_net35" LOC = "D2" ; # TDI -##NET "unnamed_net34" LOC = "A21" ; # TCK -##NET "unnamed_net45" LOC = "F7" ; # PUDC_B -##NET "unnamed_net44" LOC = "V6" ; # M2 -##NET "unnamed_net43" LOC = "AA3" ; # M1 -##NET "unnamed_net42" LOC = "AB3" ; # M0 -##NET "GND" LOC = "V19" ; # Suspend, unused -- cgit v1.2.3 From 08eb9d2937c28edfb6d1fe7fb168ef77727406d5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 9 Sep 2010 14:19:14 -0700 Subject: updated pins to match rev2, removed dip switch, etc. seems to compile ok. --- usrp2/top/u1e/u1e.ucf | 251 +++++++++++++++++++++++------------------------ usrp2/top/u1e/u1e.v | 8 +- usrp2/top/u1e/u1e_core.v | 8 +- 3 files changed, 130 insertions(+), 137 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 659a9dce5..51968d24a 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -54,8 +54,10 @@ NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug, also used on the passthru image as the cgen_sen_b pin -NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug + +NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 +NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 + NET "overo_gpio144" LOC = "A5" ; # tx_have_space NET "overo_gpio145" LOC = "C7" ; # tx_underrun NET "overo_gpio146" LOC = "A6" ; # rx_have_data @@ -69,146 +71,137 @@ NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug #NET "overo_rxd1" LOC = "D6" ; ## FTDI UART to USB converter -NET "FPGA_TXD" LOC = "U1" ; -NET "FPGA_RXD" LOC = "T6" ; +NET "FPGA_TXD" LOC = "G19" ; +NET "FPGA_RXD" LOC = "F20" ; #NET "SYSEN" LOC = "C11" ; ## I2C -NET "db_scl" LOC = "U4" ; -NET "db_sda" LOC = "U5" ; +NET "db_scl" LOC = "F19" ; +NET "db_sda" LOC = "F18" ; ## SPI ### DBoard SPI -NET "db_sclk_rx" LOC = "W3" ; -NET "db_miso_rx" LOC = "W2" ; -NET "db_mosi_rx" LOC = "V4" ; -NET "db_sen_rx" LOC = "V3" ; -NET "db_sclk_tx" LOC = "Y1" ; -NET "db_miso_tx" LOC = "W1" ; -NET "db_mosi_tx" LOC = "R3" ; -NET "db_sen_tx" LOC = "T4" ; +NET "db_sclk_rx" LOC = "D21" ; +NET "db_miso_rx" LOC = "D22" ; +NET "db_mosi_rx" LOC = "D20" ; +NET "db_sen_rx" LOC = "E19" ; +NET "db_sclk_tx" LOC = "F21" ; +NET "db_miso_tx" LOC = "E20" ; +NET "db_mosi_tx" LOC = "G17" ; +NET "db_sen_tx" LOC = "G18" ; ### AD9862 SPI and aux SPI Interfaces -#NET "aux_sdi_codec" LOC = "F19" ; -#NET "aux_sdo_codec" LOC = "F18" ; -#NET "aux_sclk_codec" LOC = "D21" ; -NET "sen_codec" LOC = "D20" ; -NET "mosi_codec" LOC = "E19" ; -NET "miso_codec" LOC = "F21" ; -NET "sclk_codec" LOC = "E20" ; +#NET "aux_sdi_codec" LOC = "G3" ; +#NET "aux_sdo_codec" LOC = "F3" ; +#NET "aux_sclk_codec" LOC = "C1" ; +NET "sen_codec" LOC = "F5" ; +NET "mosi_codec" LOC = "F4" ; +NET "miso_codec" LOC = "H4" ; +NET "sclk_codec" LOC = "H3" ; ### Clock Gen SPI -NET "cgen_miso" LOC = "U2" ; -NET "cgen_mosi" LOC = "V1" ; -NET "cgen_sclk" LOC = "R5" ; -NET "cgen_sen_b" LOC = "T1" ; +NET "cgen_miso" LOC = "F22" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; ## Clock gen control -NET "cgen_st_status" LOC = "D4" ; -NET "cgen_st_ld" LOC = "D1" ; -NET "cgen_st_refmon" LOC = "E1" ; -NET "cgen_sync_b" LOC = "M1" ; -NET "cgen_ref_sel" LOC = "J1" ; +NET "cgen_st_status" LOC = "P20" ; +NET "cgen_st_ld" LOC = "R17" ; +NET "cgen_st_refmon" LOC = "P17" ; +NET "cgen_sync_b" LOC = "U18" ; +NET "cgen_ref_sel" LOC = "U19" ; ## Debug pins -NET "debug_led<2>" LOC = "T5" ; -NET "debug_led<1>" LOC = "R2" ; -NET "debug_led<0>" LOC = "R1" ; -NET "debug<0>" LOC = "P6" ; -NET "debug<1>" LOC = "R6" ; -NET "debug<2>" LOC = "P1" ; -NET "debug<3>" LOC = "P2" ; -NET "debug<4>" LOC = "N6" ; -NET "debug<5>" LOC = "N5" ; -NET "debug<6>" LOC = "N1" ; -NET "debug<7>" LOC = "K2" ; -NET "debug<8>" LOC = "K3" ; -NET "debug<9>" LOC = "K6" ; -NET "debug<10>" LOC = "L5" ; -NET "debug<11>" LOC = "H2" ; -NET "debug<12>" LOC = "K4" ; -NET "debug<13>" LOC = "K5" ; -NET "debug<14>" LOC = "G1" ; -NET "debug<15>" LOC = "H1" ; -NET "debug<16>" LOC = "H5" ; -NET "debug<17>" LOC = "H6" ; -NET "debug<18>" LOC = "E3" ; -NET "debug<19>" LOC = "E4" ; -NET "debug<20>" LOC = "G5" ; -NET "debug<21>" LOC = "G6" ; -NET "debug<22>" LOC = "F2" ; -NET "debug<23>" LOC = "F1" ; -NET "debug<24>" LOC = "H3" ; -NET "debug<25>" LOC = "H4" ; -NET "debug<26>" LOC = "F4" ; -NET "debug<27>" LOC = "F5" ; -NET "debug<28>" LOC = "C2" ; -NET "debug<29>" LOC = "C1" ; -NET "debug<30>" LOC = "F3" ; -NET "debug<31>" LOC = "G3" ; -NET "debug_clk<0>" LOC = "L6" ; -NET "debug_clk<1>" LOC = "M5" ; +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; -NET "debug_pb<2>" LOC = "Y2" ; -NET "debug_pb<1>" LOC = "AA1" ; -NET "debug_pb<0>" LOC = "N3" ; +NET "debug_pb" LOC = "C22" ; -NET "dip_sw<7>" LOC = "T3" ; -NET "dip_sw<6>" LOC = "U3" ; -NET "dip_sw<5>" LOC = "M3" ; -NET "dip_sw<4>" LOC = "N4" ; -NET "dip_sw<3>" LOC = "J3" ; -NET "dip_sw<2>" LOC = "J4" ; -NET "dip_sw<1>" LOC = "J6" ; -NET "dip_sw<0>" LOC = "J7" ; +#NET "reset_codec" LOC = "C2" ; -#NET "reset_codec" LOC = "D22" ; +NET "RXSYNC" LOC = "F2" ; +NET "DB<11>" LOC = "G6" ; +NET "DB<10>" LOC = "G5" ; +NET "DB<9>" LOC = "E4" ; +NET "DB<8>" LOC = "E3" ; +NET "DB<7>" LOC = "H6" ; +NET "DB<6>" LOC = "H5" ; +NET "DB<5>" LOC = "H1" ; +NET "DB<4>" LOC = "G1" ; +NET "DB<3>" LOC = "K5" ; +NET "DB<2>" LOC = "K4" ; +NET "DB<1>" LOC = "H2" ; +NET "DB<0>" LOC = "L5" ; -NET "RXSYNC" LOC = "F22" ; -NET "DB<11>" LOC = "E22" ; -NET "DB<10>" LOC = "J19" ; -NET "DB<9>" LOC = "H20" ; -NET "DB<8>" LOC = "G19" ; -NET "DB<7>" LOC = "F20" ; -NET "DB<6>" LOC = "K16" ; -NET "DB<5>" LOC = "J17" ; -NET "DB<4>" LOC = "H22" ; -NET "DB<3>" LOC = "G22" ; -NET "DB<2>" LOC = "H17" ; -NET "DB<1>" LOC = "H18" ; -NET "DB<0>" LOC = "K20" ; -NET "DA<11>" LOC = "J20" ; -NET "DA<10>" LOC = "K19" ; -NET "DA<9>" LOC = "K18" ; -NET "DA<8>" LOC = "L22" ; -NET "DA<7>" LOC = "K22" ; -NET "DA<6>" LOC = "N22" ; -NET "DA<5>" LOC = "M22" ; -NET "DA<4>" LOC = "N20" ; -NET "DA<3>" LOC = "N19" ; -NET "DA<2>" LOC = "R22" ; -NET "DA<1>" LOC = "P22" ; -NET "DA<0>" LOC = "N17" ; +NET "DA<11>" LOC = "K6" ; +NET "DA<10>" LOC = "K3" ; +NET "DA<9>" LOC = "K2" ; +NET "DA<8>" LOC = "N1" ; +NET "DA<7>" LOC = "N5" ; +NET "DA<6>" LOC = "N6" ; +NET "DA<5>" LOC = "P2" ; +NET "DA<4>" LOC = "P1" ; +NET "DA<3>" LOC = "R6" ; +NET "DA<2>" LOC = "P6" ; +NET "DA<1>" LOC = "R1" ; +NET "DA<0>" LOC = "R2" ; -NET "TX<13>" LOC = "P19" ; -NET "TX<12>" LOC = "R18" ; -NET "TX<11>" LOC = "U20" ; -NET "TX<10>" LOC = "T20" ; -NET "TX<9>" LOC = "R19" ; -NET "TX<8>" LOC = "R20" ; -NET "TX<7>" LOC = "W22" ; -NET "TX<6>" LOC = "Y22" ; -NET "TX<5>" LOC = "T18" ; -NET "TX<4>" LOC = "T17" ; -NET "TX<3>" LOC = "W19" ; -NET "TX<2>" LOC = "V20" ; -NET "TX<1>" LOC = "Y21" ; -NET "TX<0>" LOC = "AA22" ; -NET "TXSYNC" LOC = "U18" ; -NET "TXBLANK" LOC = "U19" ; +NET "TX<13>" LOC = "T6" ; +NET "TX<12>" LOC = "U1" ; +NET "TX<11>" LOC = "T1" ; +NET "TX<10>" LOC = "R5" ; +NET "TX<9>" LOC = "V1" ; +NET "TX<8>" LOC = "U2" ; +NET "TX<7>" LOC = "T4" ; +NET "TX<6>" LOC = "R3" ; +NET "TX<5>" LOC = "W1" ; +NET "TX<4>" LOC = "Y1" ; +NET "TX<3>" LOC = "V3" ; +NET "TX<2>" LOC = "V4" ; +NET "TX<1>" LOC = "W2" ; +NET "TX<0>" LOC = "W3" ; +NET "TXSYNC" LOC = "U5" ; +NET "TXBLANK" LOC = "U4" ; -NET "PPS_IN" LOC = "M17" ; +NET "PPS_IN" LOC = "M5" ; NET "io_tx<0>" LOC = "AB20" ; NET "io_tx<1>" LOC = "Y17" ; @@ -255,12 +248,12 @@ NET "io_rx<15>" LOC = "Y4" ; #NET "fpga_cfg_init_b" LOC = "W15" ; ## Unused -#NET "unnamed_net37" LOC = "B1" ; # TMS -#NET "unnamed_net36" LOC = "B22" ; # TDO -#NET "unnamed_net35" LOC = "D2" ; # TDI -#NET "unnamed_net34" LOC = "A21" ; # TCK -#NET "unnamed_net45" LOC = "F7" ; # PUDC_B -#NET "unnamed_net44" LOC = "V6" ; # M2 -#NET "unnamed_net43" LOC = "AA3" ; # M1 -#NET "unnamed_net42" LOC = "AB3" ; # M0 +#NET "unnamed_net53" LOC = "B1" ; # TMS +#NET "unnamed_net52" LOC = "B22" ; # TDO +#NET "unnamed_net51" LOC = "D2" ; # TDI +#NET "unnamed_net50" LOC = "A21" ; # TCK +#NET "unnamed_net59" LOC = "F7" ; # PUDC_B +#NET "unnamed_net58" LOC = "V6" ; # M2 +#NET "unnamed_net57" LOC = "AA3" ; # M1 +#NET "unnamed_net56" LOC = "AB3" ; # M0 #NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 9536b5ced..7ddbfd537 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -5,8 +5,8 @@ module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, output FPGA_TXD, input FPGA_RXD, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -137,9 +137,9 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Main U1E Core - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 5c4b6de6c..42333a722 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -6,8 +6,8 @@ module u1e_core (input clk_fpga, input rst_fpga, - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -343,11 +343,11 @@ module u1e_core assign rx_enable = xfer_rate[14]; assign rate = xfer_rate[7:0]; - assign { debug_led[2],debug_led[0],debug_led[1] } = {run_rx,run_tx,reg_leds[0]}; // LEDs are arranged funny on board + assign { debug_led[3:0] } = {run_rx,run_tx,reg_leds[1:0]}; assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : - (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } : (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : -- cgit v1.2.3 From f177ce94fb4d4d2bdb19339c24bf5dc6035f1411 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 16 Sep 2010 14:01:43 -0700 Subject: send all gpmc signals to mictor --- usrp2/top/u1e_ethdebug/.gitignore | 6 +++ usrp2/top/u1e_ethdebug/Makefile | 83 +++++++++++++++++++++++++++++++++++++ usrp2/top/u1e_ethdebug/u1e.ucf | 86 +++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e_ethdebug/u1e.v | 26 ++++++++++++ 4 files changed, 201 insertions(+) create mode 100644 usrp2/top/u1e_ethdebug/.gitignore create mode 100644 usrp2/top/u1e_ethdebug/Makefile create mode 100644 usrp2/top/u1e_ethdebug/u1e.ucf create mode 100644 usrp2/top/u1e_ethdebug/u1e.v diff --git a/usrp2/top/u1e_ethdebug/.gitignore b/usrp2/top/u1e_ethdebug/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/usrp2/top/u1e_ethdebug/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/usrp2/top/u1e_ethdebug/Makefile b/usrp2/top/u1e_ethdebug/Makefile new file mode 100644 index 000000000..751b52970 --- /dev/null +++ b/usrp2/top/u1e_ethdebug/Makefile @@ -0,0 +1,83 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e.v \ +u1e.ucf + +SOURCES = $(abspath $(TOP_SRCS)) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u1e_ethdebug/u1e.ucf b/usrp2/top/u1e_ethdebug/u1e.ucf new file mode 100644 index 000000000..0d4384a2a --- /dev/null +++ b/usrp2/top/u1e_ethdebug/u1e.ucf @@ -0,0 +1,86 @@ + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; +NET "EM_NWP" LOC = "F13" ; + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; diff --git a/usrp2/top/u1e_ethdebug/u1e.v b/usrp2/top/u1e_ethdebug/u1e.v new file mode 100644 index 000000000..c4740b941 --- /dev/null +++ b/usrp2/top/u1e_ethdebug/u1e.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +//`define DCM 1 + +module u1e + (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, + + // GPMC + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_NADV_ALE, input EM_NWP + ); + + assign debug_clk = {EM_CLK, EM_NADV_ALE}; + + assign debug_led = {EM_NWP, EM_A[9], EM_A[8], debug_pb}; + + assign debug = { { EM_NBE[1:0], EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, + { EM_A[10], EM_A[7:1] }, + { EM_D[15:8] }, + { EM_D[7:0] } }; + + +endmodule // u1e -- cgit v1.2.3 From d78fd935865e3ebece9163a85b4b8043beef4eee Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 21 Sep 2010 17:00:44 -0700 Subject: fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift --- usrp2/top/u1e/u1e.ucf | 38 +++++++++++++++++++------------------- usrp2/top/u1e/u1e.v | 37 ++++++------------------------------- 2 files changed, 25 insertions(+), 50 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 51968d24a..5581b1dbd 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -95,10 +95,10 @@ NET "db_sen_tx" LOC = "G18" ; #NET "aux_sdi_codec" LOC = "G3" ; #NET "aux_sdo_codec" LOC = "F3" ; #NET "aux_sclk_codec" LOC = "C1" ; -NET "sen_codec" LOC = "F5" ; -NET "mosi_codec" LOC = "F4" ; +NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; +NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; NET "miso_codec" LOC = "H4" ; -NET "sclk_codec" LOC = "H3" ; +NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; ### Clock Gen SPI NET "cgen_miso" LOC = "F22" ; @@ -184,22 +184,22 @@ NET "DA<2>" LOC = "P6" ; NET "DA<1>" LOC = "R1" ; NET "DA<0>" LOC = "R2" ; -NET "TX<13>" LOC = "T6" ; -NET "TX<12>" LOC = "U1" ; -NET "TX<11>" LOC = "T1" ; -NET "TX<10>" LOC = "R5" ; -NET "TX<9>" LOC = "V1" ; -NET "TX<8>" LOC = "U2" ; -NET "TX<7>" LOC = "T4" ; -NET "TX<6>" LOC = "R3" ; -NET "TX<5>" LOC = "W1" ; -NET "TX<4>" LOC = "Y1" ; -NET "TX<3>" LOC = "V3" ; -NET "TX<2>" LOC = "V4" ; -NET "TX<1>" LOC = "W2" ; -NET "TX<0>" LOC = "W3" ; -NET "TXSYNC" LOC = "U5" ; -NET "TXBLANK" LOC = "U4" ; +NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; NET "PPS_IN" LOC = "M5" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 7ddbfd537..ee087e59d 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -1,8 +1,6 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -//`define DCM 1 - module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -41,11 +39,10 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); -`ifdef DCM - wire clk_2x, dcm_rst, dcm_locked; + wire clk_2x, dcm_rst, dcm_locked, clk_fb; DCM #(.CLK_FEEDBACK ( "1X" ), - .CLKDV_DIVIDE ( 2.0 ), - .CLKFX_DIVIDE ( 1 ), + .CLKDV_DIVIDE ( 2 ), + .CLKFX_DIVIDE ( 2 ), .CLKFX_MULTIPLY ( 2 ), .CLKIN_DIVIDE_BY_2 ( "FALSE" ), .CLKIN_PERIOD ( 15.625 ), @@ -57,15 +54,12 @@ module u1e .FACTORY_JF ( 16'h8080 ), .PHASE_SHIFT ( 0 ), .STARTUP_WAIT ( "FALSE" )) - clk_doubler (.CLKFB(clk_fpga), .CLKIN(clk_fpga_in), .RST(dcm_rst), + clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), .CLKDV(), .CLKFX(), .CLKFX180(), - .CLK2X(clk_2x), .CLK2X180(), - .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), + .CLK2X(), .CLK2X180(), + .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); -`else // !`ifdef DCM - BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); -`endif // !`ifdef DCM // ///////////////////////////////////////////////////////////////////////// // SPI @@ -83,23 +77,6 @@ module u1e assign TXBLANK = 0; wire [13:0] tx_i, tx_q; -`ifdef DCM - reg [13:0] TX; - reg TXSYNC; - - always @(posedge clk_2x) - if(clk_fpga) - begin - TX <= tx_i; - TXSYNC <= 0; // Low indicates first data item - end - else - begin - TX <= tx_q; - TXSYNC <= 1; - end -`else // !`ifdef DCM - reg[13:0] delay_q; always @(posedge clk_fpga) delay_q <= tx_q; @@ -133,8 +110,6 @@ module u1e .R(1'b0), // 1-bit reset input .S(1'b0)); // 1-bit set input -`endif // !`ifdef DCM - // ///////////////////////////////////////////////////////////////////////// // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), -- cgit v1.2.3 From 27eb894c397f758528f59bc24f2ac645f0fccc4b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 23 Sep 2010 11:40:19 -0700 Subject: watch the ethernet chip select on our debug bus --- usrp2/top/u1e/u1e.ucf | 2 +- usrp2/top/u1e/u1e.v | 7 ++++--- usrp2/top/u1e/u1e_core.v | 5 +++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 5581b1dbd..0c487a601 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -32,7 +32,7 @@ NET "EM_A<2>" LOC = "A7" ; NET "EM_A<1>" LOC = "C15" ; NET "EM_NCS6" LOC = "E17" ; -#NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS5" LOC = "E10" ; NET "EM_NCS4" LOC = "E6" ; #NET "EM_NCS1" LOC = "D18" ; #NET "EM_NCS0" LOC = "D17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index ee087e59d..445b14a03 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -8,7 +8,8 @@ module u1e // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C @@ -116,8 +117,8 @@ module u1e .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), + .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 42333a722..619e44b8a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -11,7 +11,8 @@ module u1e_core // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, output sclk, output [7:0] sen, output mosi, input miso, @@ -439,7 +440,7 @@ module u1e_core assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; -- cgit v1.2.3 From 69992b4133145cd92629a0d15354b5d33f0c4973 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 23 Sep 2010 17:15:14 -0700 Subject: better debug pins --- usrp2/top/u1e_ethdebug/u1e.ucf | 8 +++++--- usrp2/top/u1e_ethdebug/u1e.v | 10 ++++++---- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/usrp2/top/u1e_ethdebug/u1e.ucf b/usrp2/top/u1e_ethdebug/u1e.ucf index 0d4384a2a..d6a2ea4ed 100644 --- a/usrp2/top/u1e_ethdebug/u1e.ucf +++ b/usrp2/top/u1e_ethdebug/u1e.ucf @@ -36,12 +36,14 @@ NET "EM_NCS4" LOC = "E6" ; NET "EM_CLK" LOC = "F11" ; NET "EM_WAIT0" LOC = "F14" ; -NET "EM_NBE<1>" LOC = "D14" ; -NET "EM_NBE<0>" LOC = "A13" ; +#NET "EM_NBE<1>" LOC = "D14" ; +#NET "EM_NBE<0>" LOC = "A13" ; NET "EM_NWE" LOC = "B13" ; NET "EM_NOE" LOC = "A14" ; NET "EM_NADV_ALE" LOC = "B15" ; -NET "EM_NWP" LOC = "F13" ; +#NET "EM_NWP" LOC = "F13" ; +NET "overo_gpio64" LOC = "A4" ; # nRESET +NET "overo_gpio176" LOC = "B4" ; # IRQ ## Debug pins NET "debug_led<3>" LOC = "Y15" ; diff --git a/usrp2/top/u1e_ethdebug/u1e.v b/usrp2/top/u1e_ethdebug/u1e.v index c4740b941..2a543a313 100644 --- a/usrp2/top/u1e_ethdebug/u1e.v +++ b/usrp2/top/u1e_ethdebug/u1e.v @@ -8,16 +8,18 @@ module u1e input debug_pb, // GPMC - input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, - input EM_NADV_ALE, input EM_NWP + input EM_NADV_ALE, + + input overo_gpio64, input overo_gpio176 ); assign debug_clk = {EM_CLK, EM_NADV_ALE}; - assign debug_led = {EM_NWP, EM_A[9], EM_A[8], debug_pb}; + assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; - assign debug = { { EM_NBE[1:0], EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, + assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, { EM_A[10], EM_A[7:1] }, { EM_D[15:8] }, { EM_D[7:0] } }; -- cgit v1.2.3 From 1f77494788fa4fa8450aaf170055553bd0e5fe8e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 24 Sep 2010 14:37:15 -0700 Subject: allow for CS to rise before, at the same time, or after OE --- usrp2/gpmc/fifo_to_gpmc_async.v | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v index 5ac8b19bd..cf8b6e861 100644 --- a/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -11,23 +11,22 @@ module fifo_to_gpmc_async input [15:0] frame_len); // Synchronize the async control signals - reg [1:0] cs_del, oe_del; + reg [2:0] cs_del, oe_del; reg [15:0] counter; always @(posedge clk) if(reset) begin - cs_del <= 2'b11; - oe_del <= 2'b11; + cs_del <= 3'b11; + oe_del <= 3'b11; end else begin - cs_del <= { cs_del[0], EM_NCS }; - oe_del <= { oe_del[0], EM_NOE }; + cs_del <= { cs_del[1:0], EM_NCS }; + oe_del <= { oe_del[1:0], EM_NOE }; end - //wire do_read = (~cs_del[0] & (oe_del == 2'b10)); - wire do_read = (~cs_del[1] & (oe_del == 2'b01)); // change output on trailing edge + wire do_read = ( (~cs_del[1] | ~cs_del[2]) & (oe_del[1:0] == 2'b01)); // change output on trailing edge wire first_read = (counter == 0); wire last_read = ((counter+1) == frame_len); -- cgit v1.2.3 From 4c85220512ed25ae87e26c1e550e8e2debd5e64e Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Tue, 5 Oct 2010 17:37:21 -0700 Subject: U2P: newest bootloader with support for 32Mbit flash --- usrp2/top/u2plus/u2plus_core.v | 353 +++++++++++++++++++++++------------------ 1 file changed, 196 insertions(+), 157 deletions(-) diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index e394e68af..3a6bf0f64 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -286,171 +286,210 @@ module u2plus_core //defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; //defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; -////ICAP test v0.1 -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b8080d54_00000000_b8080050; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8080d5c; -defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401448_31a01468_00000000_00000000_00000000_00000000; +////bootloader 10/5/10 for 32/64Mbit FLASH +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b8081210_00000000_b8080050; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081218; +defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401920_31a01948_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f4047c_80000000_b9f400cc; -defparam bootram.RAM0.INIT_04=256'he8830000_e8601450_80000000_99fc2000_f8601450_b8000044_bc030014_f9e10000; -defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01460_bc030010_30600000_b0000000_30630004_be24ffec; +defparam bootram.RAM0.INIT_04=256'he8830000_e8601928_80000000_99fc2000_f8601928_b8000044_bc030014_f9e10000; +defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a0193c_bc030010_30600000_b0000000_30630004_be24ffec; defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; -defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01460_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01464_bc030014_30800000_b0000000_e8601464; -defparam bootram.RAM0.INIT_09=256'h06463800_20e01468_20c01468_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; +defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a0193c_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01940_bc030014_30800000_b0000000_e8601940; +defparam bootram.RAM0.INIT_09=256'h06463800_20e01948_20c01948_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; -defparam bootram.RAM0.INIT_0B=256'hb9f40bf0_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f828; -defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4014c_20e00000_20c00000_80000000_b9f40d70_80000000; -defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f40bbc_80000000_b9f40d78; +defparam bootram.RAM0.INIT_0B=256'hb9f410ac_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; +defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4014c_20e00000_20c00000_80000000_b9f4122c_80000000; +defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f41078_80000000_b9f41234; defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; -defparam bootram.RAM0.INIT_11=256'hb9f402c0_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; -defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a00f7c_10b30000_b9f405cc_10d60000_10b30000; -defparam bootram.RAM0.INIT_13=256'h30a00f7c_bc120040_aa430001_30a00f44_e061001c_10a30000_be520034_16439003; -defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f40440_b800ffb4_80000000_b9f4044c; -defparam bootram.RAM0.INIT_15=256'h80000000_b9f40414_b800ff88_80000000_b9f40420_30a00f44_80000000_b9f40b54; -defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f403f8_30a00f48_80000000_b9f409a0_30a08000_b0000000; +defparam bootram.RAM0.INIT_11=256'hb9f40440_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; +defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01438_10b30000_b9f40a18_10d60000_10b30000; +defparam bootram.RAM0.INIT_13=256'h30a01438_bc120040_aa430001_30a01400_e061001c_10a30000_be520034_16439003; +defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f404d4_b800ffb4_80000000_b9f404e0; +defparam bootram.RAM0.INIT_15=256'h80000000_b9f404a8_b800ff88_80000000_b9f404b4_30a01400_80000000_b9f41010; +defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f4048c_30a01404_80000000_b9f40e5c_30a08000_b0000000; defparam bootram.RAM0.INIT_17=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fa61001c_f9e10000_3021ffe0; -defparam bootram.RAM0.INIT_18=256'hb9f40750_80000000_b9f40408_f800200c_80000000_b9f4fef4_f860200c_306000ff; -defparam bootram.RAM0.INIT_19=256'h30a01048_bc04013c_a4842000_e8803334_80000000_b9f403a4_30a00f80_80000000; -defparam bootram.RAM0.INIT_1A=256'h30a010ac_bc23010c_80000000_b9f4099c_30a00000_b0000020_80000000_b9f4038c; -defparam bootram.RAM0.INIT_1B=256'h30a010fc_bc030058_80000000_b9f40930_30a00000_b0000040_80000000_b9f4036c; -defparam bootram.RAM0.INIT_1C=256'h30c07c00_b9f4070c_30a00000_b0000040_30e08000_b0000000_80000000_b9f4034c; -defparam bootram.RAM0.INIT_1D=256'he9e10000_80000000_b9f40318_30a01128_80000000_b9f408c0_30a08000_b0000000; -defparam bootram.RAM0.INIT_1E=256'hb000007f_80000000_b9f402f8_30a01164_30210020_b60f0008_30600001_ea61001c; -defparam bootram.RAM0.INIT_1F=256'h80000000_b9f402d4_30a00ff0_12630000_be230030_80000000_b9f408bc_30a00000; +defparam bootram.RAM0.INIT_18=256'hb9f40b9c_80000000_b9f406c0_f800200c_80000000_b9f4fef4_f860200c_306000ff; +defparam bootram.RAM0.INIT_19=256'h30a01504_bc04013c_a4842000_e8803334_80000000_b9f40438_30a0143c_80000000; +defparam bootram.RAM0.INIT_1A=256'h30a01568_bc23010c_80000000_b9f40e58_30a00000_b0000018_80000000_b9f40420; +defparam bootram.RAM0.INIT_1B=256'h30a015b8_bc030058_80000000_b9f40dec_30a00000_b0000030_80000000_b9f40400; +defparam bootram.RAM0.INIT_1C=256'h30c07c00_b9f40b58_30a00000_b0000030_30e08000_b0000000_80000000_b9f403e0; +defparam bootram.RAM0.INIT_1D=256'he9e10000_80000000_b9f403ac_30a015e4_80000000_b9f40d7c_30a08000_b0000000; +defparam bootram.RAM0.INIT_1E=256'hb000003f_80000000_b9f4038c_30a01620_30210020_b60f0008_30600001_ea61001c; +defparam bootram.RAM0.INIT_1F=256'h80000000_b9f40368_30a014ac_12630000_be230030_80000000_b9f40d78_30a00000; defparam bootram.RAM0.INIT_20=256'hb0000000_30210020_b60f0008_ea61001c_e9e10000_10730000_80000000_b9f4fe1c; -defparam bootram.RAM0.INIT_21=256'hb9f4082c_30a08000_b0000000_30c07c00_b9f40678_30a00000_b000007f_30e08000; -defparam bootram.RAM0.INIT_22=256'hb60f0008_30600001_ea61001c_e9e10000_80000000_b9f40284_30a00fb4_80000000; -defparam bootram.RAM0.INIT_23=256'h80000000_b9f40254_30a00f94_b800feec_80000000_b9f40264_30a01074_30210020; -defparam bootram.RAM0.INIT_24=256'h80000000_b9f40234_30a00ff0_bc23001c_80000000_b9f40818_30a00000_b000007f; -defparam bootram.RAM0.INIT_25=256'hb9f405e8_30a00000_b000007f_30e08000_b0000000_b800fe94_80000000_b9f4fd7c; -defparam bootram.RAM0.INIT_26=256'h80000000_b9f401f4_30a00fb4_80000000_b9f4079c_30a08000_b0000000_30c07c00; -defparam bootram.RAM0.INIT_27=256'h3021ffdc_80000000_b60f0008_80000000_b9f4fb84_f9e10000_3021ffe4_b800fe5c; -defparam bootram.RAM0.INIT_28=256'h90630060_80000000_b9f402b0_12c50000_f9e10000_12650000_fac10020_fa61001c; -defparam bootram.RAM0.INIT_29=256'he9e10000_10760000_f0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000; -defparam bootram.RAM0.INIT_2A=256'h80000000_b9f4026c_f9e10000_3021ffe4_30210024_b60f0008_eac10020_ea61001c; -defparam bootram.RAM0.INIT_2B=256'h12650000_e0650000_f9e10000_fa61001c_3021ffe0_3021001c_b60f0008_e9e10000; -defparam bootram.RAM0.INIT_2C=256'he9e10000_bc25fff0_90a30060_e0730000_32730001_b9f401b8_bc050018_90a30060; -defparam bootram.RAM0.INIT_2D=256'hb9f40184_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_10600000_ea61001c; -defparam bootram.RAM0.INIT_2E=256'hf9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000_12c50000; -defparam bootram.RAM0.INIT_2F=256'h9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000_b9f4013c; -defparam bootram.RAM0.INIT_30=256'hb0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c_b0000000; -defparam bootram.RAM0.INIT_31=256'h80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002_f860f81c; -defparam bootram.RAM0.INIT_32=256'hb0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002_94608001; -defparam bootram.RAM0.INIT_33=256'h80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c; -defparam bootram.RAM0.INIT_34=256'h84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002_94e08001; -defparam bootram.RAM0.INIT_35=256'h80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020_80633000; -defparam bootram.RAM0.INIT_36=256'hb9f40064_80000000_b9f4fe98_f9e10000_3021ffe4_80000000_b60f0008_9404c001; -defparam bootram.RAM0.INIT_37=256'hb9f40044_f9e10000_3021ffe4_3021001c_b60f0008_10600000_e9e10000_30a0000a; -defparam bootram.RAM0.INIT_38=256'h3021ffe4_80000000_b60f0008_f0a01454_3021001c_b60f0008_e9e10000_30a0000a; -defparam bootram.RAM0.INIT_39=256'h3021001c_b60f0008_e9e10000_f8603700_306000d9_30a00001_b9f4ffec_f9e10000; -defparam bootram.RAM0.INIT_3A=256'hbc03fffc_e8603704_12650000_be120024_aa45000a_f9e10000_fa61001c_3021ffe0; -defparam bootram.RAM0.INIT_3B=256'hb800ffdc_30a0000d_b9f4ffcc_30210020_b60f0008_ea61001c_e9e10000_fa60370c; -defparam bootram.RAM0.INIT_3C=256'he8603704_30a0000d_be120024_aa53000a_f9e10000_12650000_fa61001c_3021ffe0; -defparam bootram.RAM0.INIT_3D=256'h80000000_b9f4ff88_30210020_b60f0008_ea61001c_e9e10000_fa60370c_bc030008; -defparam bootram.RAM0.INIT_3E=256'h3065ffa9_90a50060_80000000_b60f0008_e8603710_bc03fffc_e8603708_b800ffdc; -defparam bootram.RAM0.INIT_3F=256'h16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024_16459001_3240005a; -defparam bootram.RAM1.INIT_00=256'h13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff_3085ffd0_be52000c; -defparam bootram.RAM1.INIT_01=256'he0790000_fb410030_fb010028_fae10024_fac10020_fa61001c_f9e10000_fb610034; -defparam bootram.RAM1.INIT_02=256'heac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034_aa43003a_13660000; -defparam bootram.RAM1.INIT_03=256'he8c01458_30210038_b60f0008_eb610034_eb410030_eb21002c_eb010028_eae10024; -defparam bootram.RAM1.INIT_04=256'ha4630044_c0662000_a4a300ff_be04001c_90840060_30650001_c085c800_30a00001; -defparam bootram.RAM1.INIT_05=256'hb9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4; -defparam bootram.RAM1.INIT_06=256'hbe38ff74_93040060_e083000b_10791800_fa7b0004_10739800_12761800_66c30404; -defparam bootram.RAM1.INIT_07=256'he0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0_e0b90005_30a0fffd; -defparam bootram.RAM1.INIT_08=256'h12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8; -defparam bootram.RAM1.INIT_09=256'h1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0_e0b90007_fafb0008; -defparam bootram.RAM1.INIT_0A=256'ha6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000_be130060_f07b0000; -defparam bootram.RAM1.INIT_0B=256'hd0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800; -defparam bootram.RAM1.INIT_0C=256'hbe52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001_e8fb0004_ea7b000c; -defparam bootram.RAM1.INIT_0D=256'h10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000_eadb0008_a74300ff; -defparam bootram.RAM1.INIT_0E=256'h16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10_107a1800_12c7b000; -defparam bootram.RAM1.INIT_0F=256'h10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff_a6d600ff_1063c000; -defparam bootram.RAM1.INIT_10=256'ha1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8_a4630100_e8603b10; -defparam bootram.RAM1.INIT_11=256'ha46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10_a4a500ff_80884800; -defparam bootram.RAM1.INIT_12=256'hbc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10_a0840100_f8603b18; -defparam bootram.RAM1.INIT_13=256'h10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000_b60f0008_e8603b00; -defparam bootram.RAM1.INIT_14=256'hb60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001_31200400_31000008; -defparam bootram.RAM1.INIT_15=256'h13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030_3021ffc4_3021001c; -defparam bootram.RAM1.INIT_16=256'h3060000b_66d60408_f8603b10_f8003b18_30600400_12670000_b9f4ff3c_fae10034; -defparam bootram.RAM1.INIT_17=256'hf8603b10_30600528_f8803b10_30800428_f8603b18_30600001_fac03b00_f8603b04; -defparam bootram.RAM1.INIT_18=256'hf8603b10_30600400_3261001c_12e00000_12d30000_be18009c_80000000_b9f4ff00; -defparam bootram.RAM1.INIT_19=256'he8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8_f8803b10_30800500; -defparam bootram.RAM1.INIT_1A=256'hbeb20034_16459003_22400010_f8610028_e8603b00_f8810024_e8803b04_f8610020; -defparam bootram.RAM1.INIT_1B=256'h12f72800_bc32fff0_16442800_30840001_d0762000_c0732000_30a00010_10800000; -defparam bootram.RAM1.INIT_1C=256'hbe52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800_beb20020_1658b803; -defparam bootram.RAM1.INIT_1D=256'hb60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000_f8003b18_12d62800; -defparam bootram.RAM1.INIT_1E=256'hf9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000_b0009f00_3021003c; -defparam bootram.RAM1.INIT_1F=256'hb0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000_31200400_b9f4fe34; -defparam bootram.RAM1.INIT_20=256'hb9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824; -defparam bootram.RAM1.INIT_21=256'h80000000_b9f40100_a46300ff_be120010_aa440020_a48400ff_64830008_80000000; -defparam bootram.RAM1.INIT_22=256'hb0000000_e063118a_bc52ffe4_16439001_32400018_bcb2fff0_16439001_32400015; -defparam bootram.RAM1.INIT_23=256'hf9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_b800ffac_f860f824; -defparam bootram.RAM1.INIT_24=256'h30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40174; -defparam bootram.RAM1.INIT_25=256'h10b60000_30c00006_b9f4fdf0_f9e10000_10f60000_32c1001c_fac10028_3021ffd4; -defparam bootram.RAM1.INIT_26=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f400b0_30c011a4; -defparam bootram.RAM1.INIT_27=256'hf9e10000_10f60000_32c1001c_fac10028_3021ffd4_3021002c_b60f0008_6464001f; -defparam bootram.RAM1.INIT_28=256'h80841800_14830000_30e00006_b9f40064_30c011ac_10b60000_30c00006_b9f4fda4; -defparam bootram.RAM1.INIT_29=256'h3021ffe4_30a011b4_3021002c_b60f0008_6464001f_eac10028_e9e10000_a884ffff; -defparam bootram.RAM1.INIT_2A=256'hb6910000_80000000_b6110000_30a0ffff_b9f4f324_80000000_b9f4f828_f9e10000; -defparam bootram.RAM1.INIT_2B=256'hbeb2005c_16479003_22400003_80000000_b60f0008_80000000_b60f0008_80000000; -defparam bootram.RAM1.INIT_2C=256'h30e7fffc_bc320040_16432000_e8660000_e8850000_bc230050_a4630003_80653000; -defparam bootram.RAM1.INIT_2D=256'hbc120028_aa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004; -defparam bootram.RAM1.INIT_2E=256'haa47ffff_30e7ffff_30c60001_30a50001_be320020_16434000_e0660000_e1050000; -defparam bootram.RAM1.INIT_2F=256'hbeb20018_16479003_2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0; -defparam bootram.RAM1.INIT_30=256'h10e72000_11040000_bc070024_11050000_be030034_a4630003_80662800_10850000; -defparam bootram.RAM1.INIT_31=256'h10650000_b60f0008_30c60001_be32fff0_16474000_31080001_f0680000_e0660000; -defparam bootram.RAM1.INIT_32=256'he866000c_f8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000; -defparam bootram.RAM1.INIT_33=256'h16479003_22400003_31080010_be52ffd0_16479003_2240000f_f868000c_30c60010; -defparam bootram.RAM1.INIT_34=256'hbe52ffec_16479003_22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c; -defparam bootram.RAM1.INIT_35=256'hfa61001c_3021ffe0_e8600f34_10880000_b810ff68_11044000_10c43000_30840004; -defparam bootram.RAM1.INIT_36=256'haa43ffff_e8730000_3273fffc_99fc1800_bc120018_aa43ffff_32600f34_f9e10000; -defparam bootram.RAM1.INIT_37=256'hb9f4f1dc_d9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0; -defparam bootram.RAM1.INIT_38=256'hd9e00800_3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000; -defparam bootram.RAM1.INIT_39=256'hffffffff_00000000_ffffffff_30210008_b60f0008_c9e00800_80000000_b9f4f154; -defparam bootram.RAM1.INIT_3A=256'h7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000; -defparam bootram.RAM1.INIT_3B=256'h4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120; -defparam bootram.RAM1.INIT_3C=256'h20555352_74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062_55535250; -defparam bootram.RAM1.INIT_3D=256'h65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20; -defparam bootram.RAM1.INIT_3E=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; -defparam bootram.RAM1.INIT_3F=256'h66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068_206e6576; -defparam bootram.RAM2.INIT_00=256'h6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520_69726d77; -defparam bootram.RAM2.INIT_01=256'h5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963; -defparam bootram.RAM2.INIT_02=256'h726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000_2052414d; -defparam bootram.RAM2.INIT_03=256'h6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f; -defparam bootram.RAM2.INIT_04=256'h7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e; -defparam bootram.RAM2.INIT_05=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f; -defparam bootram.RAM2.INIT_06=256'h20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741; -defparam bootram.RAM2.INIT_07=256'h56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164; -defparam bootram.RAM2.INIT_08=256'h204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563_64207072; -defparam bootram.RAM2.INIT_09=256'h61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67; -defparam bootram.RAM2.INIT_0A=256'h61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67; -defparam bootram.RAM2.INIT_0B=256'h77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000; -defparam bootram.RAM2.INIT_0C=256'h2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75; -defparam bootram.RAM2.INIT_0D=256'h00000000_6f72740a_0a0a6162_aa990000_ffffffff_b8080000_b0000000_10101200; -defparam bootram.RAM2.INIT_0E=256'h20202020_20202020_20202020_20202020_28282820_20202828_20202020_00202020; -defparam bootram.RAM2.INIT_0F=256'h10101010_04040410_04040404_10040404_10101010_10101010_10101010_20881010; -defparam bootram.RAM2.INIT_10=256'h10101010_01010101_01010101_01010101_01010101_01010101_41414141_10104141; -defparam bootram.RAM2.INIT_11=256'h10101010_02020202_02020202_02020202_02020202_02020202_42424242_10104242; -defparam bootram.RAM2.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_20000000; -defparam bootram.RAM2.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_1A=256'h20202020_20202020_20202020_28282020_20282828_20202020_20202020_00000000; -defparam bootram.RAM2.INIT_1B=256'h04041010_04040404_04040404_10101010_10101010_10101010_88101010_20202020; -defparam bootram.RAM2.INIT_1C=256'h01010110_01010101_01010101_01010101_01010101_41414101_10414141_10101010; -defparam bootram.RAM2.INIT_1D=256'h02020210_02020202_02020202_02020202_02020202_42424202_10424242_10101010; -defparam bootram.RAM2.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_10101020; -defparam bootram.RAM2.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_22=256'h00000000_00001344_01000000_00000f40_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_21=256'hb9f40ce8_30a08000_b0000000_30c07c00_b9f40ac4_30a00000_b000003f_30e08000; +defparam bootram.RAM0.INIT_22=256'hb60f0008_30600001_ea61001c_e9e10000_80000000_b9f40318_30a01470_80000000; +defparam bootram.RAM0.INIT_23=256'h80000000_b9f402e8_30a01450_b800feec_80000000_b9f402f8_30a01530_30210020; +defparam bootram.RAM0.INIT_24=256'h80000000_b9f402c8_30a014ac_bc23001c_80000000_b9f40cd4_30a00000_b000003f; +defparam bootram.RAM0.INIT_25=256'hb9f40a34_30a00000_b000003f_30e08000_b0000000_b800fe94_80000000_b9f4fd7c; +defparam bootram.RAM0.INIT_26=256'h80000000_b9f40288_30a01470_80000000_b9f40c58_30a08000_b0000000_30c07c00; +defparam bootram.RAM0.INIT_27=256'h3021ffd0_80000000_b60f0008_80000000_b9f4fb84_f9e10000_3021ffe4_b800fe5c; +defparam bootram.RAM0.INIT_28=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; +defparam bootram.RAM0.INIT_29=256'hbcb2002c_16572001_bc120030_aa43ffff_12c00000_b810001c_f9e10000_fac10020; +defparam bootram.RAM0.INIT_2A=256'hbe32ffd4_aa43000a_f0730000_10960000_90630060_10b80000_b9f405ec_32730001; +defparam bootram.RAM0.INIT_2B=256'heae10024_eac10020_ea61001c_e9e10000_10640000_f0130000_14999800_32d60001; +defparam bootram.RAM0.INIT_2C=256'hfb010028_fae10024_fa61001c_3021ffd0_30210030_b60f0008_eb21002c_eb010028; +defparam bootram.RAM0.INIT_2D=256'hb8100014_f9e10000_fac10020_13260000_12e70000_13050000_12660000_fb21002c; +defparam bootram.RAM0.INIT_2E=256'h10960000_90630060_10b80000_b9f4051c_32730001_bcb2002c_16572001_12c00000; +defparam bootram.RAM0.INIT_2F=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffdc_aa43000a_f0730000; +defparam bootram.RAM0.INIT_30=256'h3021ffd8_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; +defparam bootram.RAM0.INIT_31=256'hb9f404b0_12660000_f9e10000_12e60000_12c50000_fae10024_fac10020_fa61001c; +defparam bootram.RAM0.INIT_32=256'hf0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000_90630060_10b60000; +defparam bootram.RAM0.INIT_33=256'h10c50000_30210028_b60f0008_eae10024_eac10020_ea61001c_e9e10000_10770000; +defparam bootram.RAM0.INIT_34=256'h3021ffe4_3021001c_b60f0008_e9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_35=256'hf9e10000_3021ffe4_3021001c_b60f0008_e9e10000_80000000_b9f40448_f9e10000; +defparam bootram.RAM0.INIT_36=256'hfac10020_fa61001c_3021ffdc_3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc; +defparam bootram.RAM0.INIT_37=256'hb9f40324_10b60000_12c50000_be060024_90c30060_12660000_e0660000_f9e10000; +defparam bootram.RAM0.INIT_38=256'heac10020_ea61001c_e9e10000_10b60000_be26fff0_90c30060_e0730000_32730001; +defparam bootram.RAM0.INIT_39=256'h12c50000_b9f4ff9c_f9e10000_fac1001c_3021ffe0_30210024_b60f0008_10600000; +defparam bootram.RAM0.INIT_3A=256'h30210020_b60f0008_10600000_eac1001c_e9e10000_30c0000a_b9f402dc_10b60000; +defparam bootram.RAM0.INIT_3B=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000; +defparam bootram.RAM0.INIT_3C=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000; +defparam bootram.RAM0.INIT_3D=256'h3021ffe0_3021001c_b60f0008_e9e10000_30c0000a_b9f40278_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_3E=256'he9e10000_10760000_10d60000_b9f40250_f9e10000_10a00000_12c50000_fac1001c; +defparam bootram.RAM0.INIT_3F=256'h12c60000_b9f40228_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_eac1001c; +defparam bootram.RAM1.INIT_00=256'hb9f401b8_f9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000; +defparam bootram.RAM1.INIT_01=256'hb0000000_9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000; +defparam bootram.RAM1.INIT_02=256'hf860f81c_b0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c; +defparam bootram.RAM1.INIT_03=256'h94608001_80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002; +defparam bootram.RAM1.INIT_04=256'hf8a0f81c_b0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002; +defparam bootram.RAM1.INIT_05=256'h94e08001_80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002; +defparam bootram.RAM1.INIT_06=256'h80633000_84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002; +defparam bootram.RAM1.INIT_07=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020; +defparam bootram.RAM1.INIT_08=256'hfac10020_f9e10000_fb010028_fae10024_fa61001c_3021ffd4_80000000_b60f0008; +defparam bootram.RAM1.INIT_09=256'h32600001_be670038_12660000_be060040_90c30060_13050000_12e60000_e0660000; +defparam bootram.RAM1.INIT_0A=256'hc0779800_10b80000_b9f400cc_10730000_be120028_16569800_32c70001_b8100014; +defparam bootram.RAM1.INIT_0B=256'heac10020_ea61001c_e9e10000_10730000_3273ffff_32730001_be26ffe4_90c30060; +defparam bootram.RAM1.INIT_0C=256'hb9f40084_f9e10000_10a00000_3021ffe4_3021002c_b60f0008_eb010028_eae10024; +defparam bootram.RAM1.INIT_0D=256'h10c63000_80000000_b60f0008_f0c5192c_3021001c_b60f0008_e9e10000_30c0000a; +defparam bootram.RAM1.INIT_0E=256'hf9e10000_fa61001c_3021ffe0_80000000_b60f0008_f8653700_64a50405_e4661660; +defparam bootram.RAM1.INIT_0F=256'h32730001_10b30000_e0d3165c_90c60060_b9f4ffc4_10b30000_e0d3192c_12600000; +defparam bootram.RAM1.INIT_10=256'h30210020_b60f0008_ea61001c_e9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc; +defparam bootram.RAM1.INIT_11=256'h12650000_be120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc; +defparam bootram.RAM1.INIT_12=256'heac10020_ea61001c_e9e10000_fac5000c_bc03fffc_e8650004_30a33700_64730405; +defparam bootram.RAM1.INIT_13=256'hb810ffc8_30c0000d_b9f4ffac_bc32ffd0_aa430001_e065192c_30210024_b60f0008; +defparam bootram.RAM1.INIT_14=256'hbe120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc_64730405; +defparam bootram.RAM1.INIT_15=256'hea61001c_e9e10000_fac3000c_bc040008_e8830004_30633700_64730405_12650000; +defparam bootram.RAM1.INIT_16=256'hb9f4ff44_30c0000d_be32ffd0_aa430001_e065192c_30210024_b60f0008_eac10020; +defparam bootram.RAM1.INIT_17=256'he8650010_bc03fffc_e8650008_30a53700_64a50405_64730405_b810ffc4_80000000; +defparam bootram.RAM1.INIT_18=256'he8850008_e8650010_bc030014_e8650008_30a53700_64a50405_80000000_b60f0008; +defparam bootram.RAM1.INIT_19=256'hf9e10000_fac10020_3021ffdc_64a50405_80000000_b60f0008_90630060_be24fff8; +defparam bootram.RAM1.INIT_1A=256'hbe120034_aa53012d_b8000010_32600001_be230040_e8760008_32c53700_fa61001c; +defparam bootram.RAM1.INIT_1B=256'h3240012b_3273ffff_32730001_be03ffe8_e8760008_30a00001_b9f40040_3060ffff; +defparam bootram.RAM1.INIT_1C=256'hb60f0008_eac10020_ea61001c_e9e10000_e8760010_3060ffff_be52000c_16539001; +defparam bootram.RAM1.INIT_1D=256'hbe650048_bc430054_e8601930_bc260054_a4c30000_b0008000_e8603324_30210024; +defparam bootram.RAM1.INIT_1E=256'h80000000_80000000_80000000_80000000_10800000_bc660030_e8c01930_10660000; +defparam bootram.RAM1.INIT_1F=256'h16432800_30630001_bc32ffdc_16443000_30840001_80000000_80000000_80000000; +defparam bootram.RAM1.INIT_20=256'hf8801930_e483166c_10631800_a4630007_e8603324_80000000_b60f0008_bc32ffc8; +defparam bootram.RAM1.INIT_21=256'h3065ffc9_a46300ff_be520024_16459001_3240005a_3065ffa9_90a50060_b800ff9c; +defparam bootram.RAM1.INIT_22=256'h80000000_b60f0008_a46400ff_3085ffd0_be52000c_16459001_32400039_a46300ff; +defparam bootram.RAM1.INIT_23=256'hfae10024_fac10020_fa61001c_f9e10000_fb610034_13250000_fb21002c_3021ffc8; +defparam bootram.RAM1.INIT_24=256'h10650000_30a0ffff_be120034_aa43003a_13660000_e0790000_fb410030_fb010028; +defparam bootram.RAM1.INIT_25=256'heb610034_eb410030_eb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_26=256'hbe04001c_90840060_30650001_c085c800_30a00001_e8c01934_30210038_b60f0008; +defparam bootram.RAM1.INIT_27=256'hb9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4_a4630044_c0662000_a4a300ff; +defparam bootram.RAM1.INIT_28=256'h10791800_fa7b0004_10739800_12761800_66c30404_b9f4ff1c_e0b90002_80000000; +defparam bootram.RAM1.INIT_29=256'he0b90003_13530000_b9f4fef0_e0b90005_30a0fffd_be38ff74_93040060_e083000b; +defparam bootram.RAM1.INIT_2A=256'hb9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4; +defparam bootram.RAM1.INIT_2B=256'he0b90008_80000000_b9f4feb0_e0b90007_fafb0008_12f7b000_12d61800_12d61800; +defparam bootram.RAM1.INIT_2C=256'hea7b000c_13580000_10f30000_be130060_f07b0000_1063b000_66c30404_b9f4fea4; +defparam bootram.RAM1.INIT_2D=256'hb9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000; +defparam bootram.RAM1.INIT_2E=256'ha70400ff_c073c000_30980001_e8fb0004_ea7b000c_d0789800_1063b800_66e30404; +defparam bootram.RAM1.INIT_2F=256'h64760008_12e73800_e09b0000_eadb0008_a74300ff_be52ffb8_1647c003_107a1800; +defparam bootram.RAM1.INIT_30=256'he0b7000a_12d61800_b9f4fe10_107a1800_12c7b000_10632000_e0b70009_12f9b800; +defparam bootram.RAM1.INIT_31=256'hbe32fe60_1643b000_a46300ff_a6d600ff_1063c000_16d60000_67030404_b9f4fe04; +defparam bootram.RAM1.INIT_32=256'h80000000_b60f0008_bc23fff8_a4630100_e8603b10_10a00000_b810fe58_30a0fffb; +defparam bootram.RAM1.INIT_33=256'hbc23fff8_a4630100_e8603b10_a4a500ff_80884800_a1292000_a508007f_a5290600; +defparam bootram.RAM1.INIT_34=256'h10650000_be050018_f8803b10_a0840100_f8603b18_a46600ff_f8803b10_f8e03b00; +defparam bootram.RAM1.INIT_35=256'h10e60000_10c00000_80000000_b60f0008_e8603b00_bc23fff8_a4630100_e8603b10; +defparam bootram.RAM1.INIT_36=256'hb9f4ff84_f8603b14_30600001_31200400_31000008_10a00000_f9e10000_3021ffe4; +defparam bootram.RAM1.INIT_37=256'hfa61002c_12c50000_fac10030_3021ffc4_3021001c_b60f0008_e9e10000_80000000; +defparam bootram.RAM1.INIT_38=256'hf8003b18_30600400_12670000_b9f4ff3c_fae10034_13060000_f9e10000_fb010038; +defparam bootram.RAM1.INIT_39=256'h30800428_f8603b18_30600001_fac03b00_f8603b04_3060000b_66d60408_f8603b10; +defparam bootram.RAM1.INIT_3A=256'h12e00000_12d30000_be18009c_80000000_b9f4ff00_f8603b10_30600528_f8803b10; +defparam bootram.RAM1.INIT_3B=256'he8803b0c_80000000_b9f4fed8_f8803b10_30800500_f8603b10_30600400_3261001c; +defparam bootram.RAM1.INIT_3C=256'hf8610028_e8603b00_f8810024_e8803b04_f8610020_e8603b08_f881001c_14b7c000; +defparam bootram.RAM1.INIT_3D=256'h30840001_d0762000_c0732000_30a00010_10800000_beb20034_16459003_22400010; +defparam bootram.RAM1.INIT_3E=256'hbc25ffd8_b800ff8c_12d62800_beb20020_1658b803_12f72800_bc32fff0_16442800; +defparam bootram.RAM1.INIT_3F=256'heac10030_ea61002c_e9e10000_f8003b18_12d62800_be52ff7c_1658b803_12f72800; +defparam bootram.RAM2.INIT_00=256'h30a00001_3021ffe4_30e00000_b0009f00_3021003c_b60f0008_eb010038_eae10034; +defparam bootram.RAM2.INIT_01=256'ha463ffff_b00000ff_e9e10000_31200400_b9f4fe34_f9e10000_31000020_30c00001; +defparam bootram.RAM2.INIT_02=256'he9e10000_bc030010_f9e10000_3021ffe4_e860f828_b0000000_3021001c_b60f0008; +defparam bootram.RAM2.INIT_03=256'hbe120010_aa440020_a48400ff_64830008_80000000_b9f4ffa8_3021001c_b60f0008; +defparam bootram.RAM2.INIT_04=256'h16439001_32400018_bcb2fff0_16439001_32400015_80000000_b9f40170_a46300ff; +defparam bootram.RAM2.INIT_05=256'hf9e10000_3021ffe4_e860f824_b0000000_b800ffb0_f860f828_b0000000_bc52ffe4; +defparam bootram.RAM2.INIT_06=256'ha48400ff_64830008_80000000_b9f4ff40_3021001c_b60f0008_e9e10000_bc030010; +defparam bootram.RAM2.INIT_07=256'hbcb2fff0_16459001_32400015_80000000_b9f40108_a4a300ff_be120010_aa440020; +defparam bootram.RAM2.INIT_08=256'hf860f824_b0000000_f8a0f828_b0000000_e0651666_bc52ffe4_16459001_32400018; +defparam bootram.RAM2.INIT_09=256'hb9f40174_f9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_b800ffa4; +defparam bootram.RAM2.INIT_0A=256'h3021ffd4_30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024; +defparam bootram.RAM2.INIT_0B=256'h30c01680_10b60000_30c00006_b9f4fd80_f9e10000_10f60000_32c1001c_fac10028; +defparam bootram.RAM2.INIT_0C=256'h6464001f_eac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f400b0; +defparam bootram.RAM2.INIT_0D=256'hb9f4fd34_f9e10000_10f60000_32c1001c_fac10028_3021ffd4_3021002c_b60f0008; +defparam bootram.RAM2.INIT_0E=256'ha884ffff_80841800_14830000_30e00006_b9f40064_30c01688_10b60000_30c00006; +defparam bootram.RAM2.INIT_0F=256'hf9e10000_3021ffe4_30a01690_3021002c_b60f0008_6464001f_eac10028_e9e10000; +defparam bootram.RAM2.INIT_10=256'h80000000_b6910000_80000000_b6110000_30a0ffff_b9f4ee68_80000000_b9f4f580; +defparam bootram.RAM2.INIT_11=256'h80653000_beb2005c_16479003_22400003_80000000_b60f0008_80000000_b60f0008; +defparam bootram.RAM2.INIT_12=256'h30a50004_30e7fffc_bc320040_16432000_e8660000_e8850000_bc230050_a4630003; +defparam bootram.RAM2.INIT_13=256'he1050000_bc120028_aa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003; +defparam bootram.RAM2.INIT_14=256'hbc32ffe0_aa47ffff_30e7ffff_30c60001_30a50001_be320020_16434000_e0660000; +defparam bootram.RAM2.INIT_15=256'h10850000_beb20018_16479003_2240000f_14634000_b60f0008_10600000_b60f0008; +defparam bootram.RAM2.INIT_16=256'he0660000_10e72000_11040000_bc070024_11050000_be030034_a4630003_80662800; +defparam bootram.RAM2.INIT_17=256'he8860000_10650000_b60f0008_30c60001_be32fff0_16474000_31080001_f0680000; +defparam bootram.RAM2.INIT_18=256'h30c60010_e866000c_f8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0; +defparam bootram.RAM2.INIT_19=256'hbcb2002c_16479003_22400003_31080010_be52ffd0_16479003_2240000f_f868000c; +defparam bootram.RAM2.INIT_1A=256'h30840004_be52ffec_16479003_22400003_d8682000_30e7fffc_c8662000_10800000; +defparam bootram.RAM2.INIT_1B=256'hf9e10000_fa61001c_3021ffe0_e86013f0_10880000_b810ff68_11044000_10c43000; +defparam bootram.RAM2.INIT_1C=256'hbc32fff0_aa43ffff_e8730000_3273fffc_99fc1800_bc120018_aa43ffff_326013f0; +defparam bootram.RAM2.INIT_1D=256'h80000000_b9f4ed20_d9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000; +defparam bootram.RAM2.INIT_1E=256'hb9f4ec98_d9e00800_3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0; +defparam bootram.RAM2.INIT_1F=256'h00000000_ffffffff_00000000_ffffffff_30210008_b60f0008_c9e00800_80000000; +defparam bootram.RAM2.INIT_20=256'h65642120_7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000; +defparam bootram.RAM2.INIT_21=256'h55535250_4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b; +defparam bootram.RAM2.INIT_22=256'h50322b20_20555352_74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062; +defparam bootram.RAM2.INIT_23=256'h6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073; +defparam bootram.RAM2.INIT_24=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; +defparam bootram.RAM2.INIT_25=256'h69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068; +defparam bootram.RAM2.INIT_26=256'h62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520; +defparam bootram.RAM2.INIT_27=256'h2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046; +defparam bootram.RAM2.INIT_28=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000; +defparam bootram.RAM2.INIT_29=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; +defparam bootram.RAM2.INIT_2A=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; +defparam bootram.RAM2.INIT_2B=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; +defparam bootram.RAM2.INIT_2C=256'h6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61; +defparam bootram.RAM2.INIT_2D=256'h64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f; +defparam bootram.RAM2.INIT_2E=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563; +defparam bootram.RAM2.INIT_2F=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00; +defparam bootram.RAM2.INIT_30=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; +defparam bootram.RAM2.INIT_31=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; +defparam bootram.RAM2.INIT_32=256'h05050400_2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20; +defparam bootram.RAM2.INIT_33=256'h10101200_06820594_09c407d0_13880d05_00002710_01b200d9_05160364_14580a2c; +defparam bootram.RAM2.INIT_34=256'h00202020_00000000_6f72740a_0a0a6162_aa990000_ffffffff_b8080000_b0000000; +defparam bootram.RAM2.INIT_35=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; +defparam bootram.RAM2.INIT_36=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; +defparam bootram.RAM2.INIT_37=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; +defparam bootram.RAM2.INIT_38=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; +defparam bootram.RAM2.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_01=256'h20202020_20202020_20202020_20202020_28282020_20282828_20202020_20202020; +defparam bootram.RAM3.INIT_02=256'h10101010_04041010_04040404_04040404_10101010_10101010_10101010_88101010; +defparam bootram.RAM3.INIT_03=256'h10101010_01010110_01010101_01010101_01010101_01010101_41414101_10414141; +defparam bootram.RAM3.INIT_04=256'h10101020_02020210_02020202_02020202_02020202_02020202_42424202_10424242; +defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00001820_ffffffff_01010100_000013fc_00000000_00000000; +defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), -- cgit v1.2.3 From dfbc0653beabe4ee1b9e8816a1932734d12b89d2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 7 Oct 2010 10:55:17 -0700 Subject: separate the bootloader image into another file --- usrp2/top/u2plus/bootloader.rmi | 204 +++++++++++++++++++++++++++++++++++++++ usrp2/top/u2plus/u2plus_core.v | 205 +--------------------------------------- 2 files changed, 205 insertions(+), 204 deletions(-) create mode 100644 usrp2/top/u2plus/bootloader.rmi diff --git a/usrp2/top/u2plus/bootloader.rmi b/usrp2/top/u2plus/bootloader.rmi new file mode 100644 index 000000000..02ec11060 --- /dev/null +++ b/usrp2/top/u2plus/bootloader.rmi @@ -0,0 +1,204 @@ +////bootloader 10/5/10 for 32/64Mbit FLASH +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b8081210_00000000_b8080050; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081218; +defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401920_31a01948_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f4047c_80000000_b9f400cc; +defparam bootram.RAM0.INIT_04=256'he8830000_e8601928_80000000_99fc2000_f8601928_b8000044_bc030014_f9e10000; +defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a0193c_bc030010_30600000_b0000000_30630004_be24ffec; +defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; +defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a0193c_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01940_bc030014_30800000_b0000000_e8601940; +defparam bootram.RAM0.INIT_09=256'h06463800_20e01948_20c01948_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; +defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; +defparam bootram.RAM0.INIT_0B=256'hb9f410ac_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; +defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4014c_20e00000_20c00000_80000000_b9f4122c_80000000; +defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f41078_80000000_b9f41234; +defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; +defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; +defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; +defparam bootram.RAM0.INIT_11=256'hb9f40440_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; +defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01438_10b30000_b9f40a18_10d60000_10b30000; +defparam bootram.RAM0.INIT_13=256'h30a01438_bc120040_aa430001_30a01400_e061001c_10a30000_be520034_16439003; +defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f404d4_b800ffb4_80000000_b9f404e0; +defparam bootram.RAM0.INIT_15=256'h80000000_b9f404a8_b800ff88_80000000_b9f404b4_30a01400_80000000_b9f41010; +defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f4048c_30a01404_80000000_b9f40e5c_30a08000_b0000000; +defparam bootram.RAM0.INIT_17=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fa61001c_f9e10000_3021ffe0; +defparam bootram.RAM0.INIT_18=256'hb9f40b9c_80000000_b9f406c0_f800200c_80000000_b9f4fef4_f860200c_306000ff; +defparam bootram.RAM0.INIT_19=256'h30a01504_bc04013c_a4842000_e8803334_80000000_b9f40438_30a0143c_80000000; +defparam bootram.RAM0.INIT_1A=256'h30a01568_bc23010c_80000000_b9f40e58_30a00000_b0000018_80000000_b9f40420; +defparam bootram.RAM0.INIT_1B=256'h30a015b8_bc030058_80000000_b9f40dec_30a00000_b0000030_80000000_b9f40400; +defparam bootram.RAM0.INIT_1C=256'h30c07c00_b9f40b58_30a00000_b0000030_30e08000_b0000000_80000000_b9f403e0; +defparam bootram.RAM0.INIT_1D=256'he9e10000_80000000_b9f403ac_30a015e4_80000000_b9f40d7c_30a08000_b0000000; +defparam bootram.RAM0.INIT_1E=256'hb000003f_80000000_b9f4038c_30a01620_30210020_b60f0008_30600001_ea61001c; +defparam bootram.RAM0.INIT_1F=256'h80000000_b9f40368_30a014ac_12630000_be230030_80000000_b9f40d78_30a00000; +defparam bootram.RAM0.INIT_20=256'hb0000000_30210020_b60f0008_ea61001c_e9e10000_10730000_80000000_b9f4fe1c; +defparam bootram.RAM0.INIT_21=256'hb9f40ce8_30a08000_b0000000_30c07c00_b9f40ac4_30a00000_b000003f_30e08000; +defparam bootram.RAM0.INIT_22=256'hb60f0008_30600001_ea61001c_e9e10000_80000000_b9f40318_30a01470_80000000; +defparam bootram.RAM0.INIT_23=256'h80000000_b9f402e8_30a01450_b800feec_80000000_b9f402f8_30a01530_30210020; +defparam bootram.RAM0.INIT_24=256'h80000000_b9f402c8_30a014ac_bc23001c_80000000_b9f40cd4_30a00000_b000003f; +defparam bootram.RAM0.INIT_25=256'hb9f40a34_30a00000_b000003f_30e08000_b0000000_b800fe94_80000000_b9f4fd7c; +defparam bootram.RAM0.INIT_26=256'h80000000_b9f40288_30a01470_80000000_b9f40c58_30a08000_b0000000_30c07c00; +defparam bootram.RAM0.INIT_27=256'h3021ffd0_80000000_b60f0008_80000000_b9f4fb84_f9e10000_3021ffe4_b800fe5c; +defparam bootram.RAM0.INIT_28=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; +defparam bootram.RAM0.INIT_29=256'hbcb2002c_16572001_bc120030_aa43ffff_12c00000_b810001c_f9e10000_fac10020; +defparam bootram.RAM0.INIT_2A=256'hbe32ffd4_aa43000a_f0730000_10960000_90630060_10b80000_b9f405ec_32730001; +defparam bootram.RAM0.INIT_2B=256'heae10024_eac10020_ea61001c_e9e10000_10640000_f0130000_14999800_32d60001; +defparam bootram.RAM0.INIT_2C=256'hfb010028_fae10024_fa61001c_3021ffd0_30210030_b60f0008_eb21002c_eb010028; +defparam bootram.RAM0.INIT_2D=256'hb8100014_f9e10000_fac10020_13260000_12e70000_13050000_12660000_fb21002c; +defparam bootram.RAM0.INIT_2E=256'h10960000_90630060_10b80000_b9f4051c_32730001_bcb2002c_16572001_12c00000; +defparam bootram.RAM0.INIT_2F=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffdc_aa43000a_f0730000; +defparam bootram.RAM0.INIT_30=256'h3021ffd8_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; +defparam bootram.RAM0.INIT_31=256'hb9f404b0_12660000_f9e10000_12e60000_12c50000_fae10024_fac10020_fa61001c; +defparam bootram.RAM0.INIT_32=256'hf0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000_90630060_10b60000; +defparam bootram.RAM0.INIT_33=256'h10c50000_30210028_b60f0008_eae10024_eac10020_ea61001c_e9e10000_10770000; +defparam bootram.RAM0.INIT_34=256'h3021ffe4_3021001c_b60f0008_e9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_35=256'hf9e10000_3021ffe4_3021001c_b60f0008_e9e10000_80000000_b9f40448_f9e10000; +defparam bootram.RAM0.INIT_36=256'hfac10020_fa61001c_3021ffdc_3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc; +defparam bootram.RAM0.INIT_37=256'hb9f40324_10b60000_12c50000_be060024_90c30060_12660000_e0660000_f9e10000; +defparam bootram.RAM0.INIT_38=256'heac10020_ea61001c_e9e10000_10b60000_be26fff0_90c30060_e0730000_32730001; +defparam bootram.RAM0.INIT_39=256'h12c50000_b9f4ff9c_f9e10000_fac1001c_3021ffe0_30210024_b60f0008_10600000; +defparam bootram.RAM0.INIT_3A=256'h30210020_b60f0008_10600000_eac1001c_e9e10000_30c0000a_b9f402dc_10b60000; +defparam bootram.RAM0.INIT_3B=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000; +defparam bootram.RAM0.INIT_3C=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000; +defparam bootram.RAM0.INIT_3D=256'h3021ffe0_3021001c_b60f0008_e9e10000_30c0000a_b9f40278_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_3E=256'he9e10000_10760000_10d60000_b9f40250_f9e10000_10a00000_12c50000_fac1001c; +defparam bootram.RAM0.INIT_3F=256'h12c60000_b9f40228_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_eac1001c; +defparam bootram.RAM1.INIT_00=256'hb9f401b8_f9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000; +defparam bootram.RAM1.INIT_01=256'hb0000000_9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000; +defparam bootram.RAM1.INIT_02=256'hf860f81c_b0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c; +defparam bootram.RAM1.INIT_03=256'h94608001_80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002; +defparam bootram.RAM1.INIT_04=256'hf8a0f81c_b0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002; +defparam bootram.RAM1.INIT_05=256'h94e08001_80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002; +defparam bootram.RAM1.INIT_06=256'h80633000_84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002; +defparam bootram.RAM1.INIT_07=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020; +defparam bootram.RAM1.INIT_08=256'hfac10020_f9e10000_fb010028_fae10024_fa61001c_3021ffd4_80000000_b60f0008; +defparam bootram.RAM1.INIT_09=256'h32600001_be670038_12660000_be060040_90c30060_13050000_12e60000_e0660000; +defparam bootram.RAM1.INIT_0A=256'hc0779800_10b80000_b9f400cc_10730000_be120028_16569800_32c70001_b8100014; +defparam bootram.RAM1.INIT_0B=256'heac10020_ea61001c_e9e10000_10730000_3273ffff_32730001_be26ffe4_90c30060; +defparam bootram.RAM1.INIT_0C=256'hb9f40084_f9e10000_10a00000_3021ffe4_3021002c_b60f0008_eb010028_eae10024; +defparam bootram.RAM1.INIT_0D=256'h10c63000_80000000_b60f0008_f0c5192c_3021001c_b60f0008_e9e10000_30c0000a; +defparam bootram.RAM1.INIT_0E=256'hf9e10000_fa61001c_3021ffe0_80000000_b60f0008_f8653700_64a50405_e4661660; +defparam bootram.RAM1.INIT_0F=256'h32730001_10b30000_e0d3165c_90c60060_b9f4ffc4_10b30000_e0d3192c_12600000; +defparam bootram.RAM1.INIT_10=256'h30210020_b60f0008_ea61001c_e9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc; +defparam bootram.RAM1.INIT_11=256'h12650000_be120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc; +defparam bootram.RAM1.INIT_12=256'heac10020_ea61001c_e9e10000_fac5000c_bc03fffc_e8650004_30a33700_64730405; +defparam bootram.RAM1.INIT_13=256'hb810ffc8_30c0000d_b9f4ffac_bc32ffd0_aa430001_e065192c_30210024_b60f0008; +defparam bootram.RAM1.INIT_14=256'hbe120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc_64730405; +defparam bootram.RAM1.INIT_15=256'hea61001c_e9e10000_fac3000c_bc040008_e8830004_30633700_64730405_12650000; +defparam bootram.RAM1.INIT_16=256'hb9f4ff44_30c0000d_be32ffd0_aa430001_e065192c_30210024_b60f0008_eac10020; +defparam bootram.RAM1.INIT_17=256'he8650010_bc03fffc_e8650008_30a53700_64a50405_64730405_b810ffc4_80000000; +defparam bootram.RAM1.INIT_18=256'he8850008_e8650010_bc030014_e8650008_30a53700_64a50405_80000000_b60f0008; +defparam bootram.RAM1.INIT_19=256'hf9e10000_fac10020_3021ffdc_64a50405_80000000_b60f0008_90630060_be24fff8; +defparam bootram.RAM1.INIT_1A=256'hbe120034_aa53012d_b8000010_32600001_be230040_e8760008_32c53700_fa61001c; +defparam bootram.RAM1.INIT_1B=256'h3240012b_3273ffff_32730001_be03ffe8_e8760008_30a00001_b9f40040_3060ffff; +defparam bootram.RAM1.INIT_1C=256'hb60f0008_eac10020_ea61001c_e9e10000_e8760010_3060ffff_be52000c_16539001; +defparam bootram.RAM1.INIT_1D=256'hbe650048_bc430054_e8601930_bc260054_a4c30000_b0008000_e8603324_30210024; +defparam bootram.RAM1.INIT_1E=256'h80000000_80000000_80000000_80000000_10800000_bc660030_e8c01930_10660000; +defparam bootram.RAM1.INIT_1F=256'h16432800_30630001_bc32ffdc_16443000_30840001_80000000_80000000_80000000; +defparam bootram.RAM1.INIT_20=256'hf8801930_e483166c_10631800_a4630007_e8603324_80000000_b60f0008_bc32ffc8; +defparam bootram.RAM1.INIT_21=256'h3065ffc9_a46300ff_be520024_16459001_3240005a_3065ffa9_90a50060_b800ff9c; +defparam bootram.RAM1.INIT_22=256'h80000000_b60f0008_a46400ff_3085ffd0_be52000c_16459001_32400039_a46300ff; +defparam bootram.RAM1.INIT_23=256'hfae10024_fac10020_fa61001c_f9e10000_fb610034_13250000_fb21002c_3021ffc8; +defparam bootram.RAM1.INIT_24=256'h10650000_30a0ffff_be120034_aa43003a_13660000_e0790000_fb410030_fb010028; +defparam bootram.RAM1.INIT_25=256'heb610034_eb410030_eb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_26=256'hbe04001c_90840060_30650001_c085c800_30a00001_e8c01934_30210038_b60f0008; +defparam bootram.RAM1.INIT_27=256'hb9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4_a4630044_c0662000_a4a300ff; +defparam bootram.RAM1.INIT_28=256'h10791800_fa7b0004_10739800_12761800_66c30404_b9f4ff1c_e0b90002_80000000; +defparam bootram.RAM1.INIT_29=256'he0b90003_13530000_b9f4fef0_e0b90005_30a0fffd_be38ff74_93040060_e083000b; +defparam bootram.RAM1.INIT_2A=256'hb9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4; +defparam bootram.RAM1.INIT_2B=256'he0b90008_80000000_b9f4feb0_e0b90007_fafb0008_12f7b000_12d61800_12d61800; +defparam bootram.RAM1.INIT_2C=256'hea7b000c_13580000_10f30000_be130060_f07b0000_1063b000_66c30404_b9f4fea4; +defparam bootram.RAM1.INIT_2D=256'hb9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000; +defparam bootram.RAM1.INIT_2E=256'ha70400ff_c073c000_30980001_e8fb0004_ea7b000c_d0789800_1063b800_66e30404; +defparam bootram.RAM1.INIT_2F=256'h64760008_12e73800_e09b0000_eadb0008_a74300ff_be52ffb8_1647c003_107a1800; +defparam bootram.RAM1.INIT_30=256'he0b7000a_12d61800_b9f4fe10_107a1800_12c7b000_10632000_e0b70009_12f9b800; +defparam bootram.RAM1.INIT_31=256'hbe32fe60_1643b000_a46300ff_a6d600ff_1063c000_16d60000_67030404_b9f4fe04; +defparam bootram.RAM1.INIT_32=256'h80000000_b60f0008_bc23fff8_a4630100_e8603b10_10a00000_b810fe58_30a0fffb; +defparam bootram.RAM1.INIT_33=256'hbc23fff8_a4630100_e8603b10_a4a500ff_80884800_a1292000_a508007f_a5290600; +defparam bootram.RAM1.INIT_34=256'h10650000_be050018_f8803b10_a0840100_f8603b18_a46600ff_f8803b10_f8e03b00; +defparam bootram.RAM1.INIT_35=256'h10e60000_10c00000_80000000_b60f0008_e8603b00_bc23fff8_a4630100_e8603b10; +defparam bootram.RAM1.INIT_36=256'hb9f4ff84_f8603b14_30600001_31200400_31000008_10a00000_f9e10000_3021ffe4; +defparam bootram.RAM1.INIT_37=256'hfa61002c_12c50000_fac10030_3021ffc4_3021001c_b60f0008_e9e10000_80000000; +defparam bootram.RAM1.INIT_38=256'hf8003b18_30600400_12670000_b9f4ff3c_fae10034_13060000_f9e10000_fb010038; +defparam bootram.RAM1.INIT_39=256'h30800428_f8603b18_30600001_fac03b00_f8603b04_3060000b_66d60408_f8603b10; +defparam bootram.RAM1.INIT_3A=256'h12e00000_12d30000_be18009c_80000000_b9f4ff00_f8603b10_30600528_f8803b10; +defparam bootram.RAM1.INIT_3B=256'he8803b0c_80000000_b9f4fed8_f8803b10_30800500_f8603b10_30600400_3261001c; +defparam bootram.RAM1.INIT_3C=256'hf8610028_e8603b00_f8810024_e8803b04_f8610020_e8603b08_f881001c_14b7c000; +defparam bootram.RAM1.INIT_3D=256'h30840001_d0762000_c0732000_30a00010_10800000_beb20034_16459003_22400010; +defparam bootram.RAM1.INIT_3E=256'hbc25ffd8_b800ff8c_12d62800_beb20020_1658b803_12f72800_bc32fff0_16442800; +defparam bootram.RAM1.INIT_3F=256'heac10030_ea61002c_e9e10000_f8003b18_12d62800_be52ff7c_1658b803_12f72800; +defparam bootram.RAM2.INIT_00=256'h30a00001_3021ffe4_30e00000_b0009f00_3021003c_b60f0008_eb010038_eae10034; +defparam bootram.RAM2.INIT_01=256'ha463ffff_b00000ff_e9e10000_31200400_b9f4fe34_f9e10000_31000020_30c00001; +defparam bootram.RAM2.INIT_02=256'he9e10000_bc030010_f9e10000_3021ffe4_e860f828_b0000000_3021001c_b60f0008; +defparam bootram.RAM2.INIT_03=256'hbe120010_aa440020_a48400ff_64830008_80000000_b9f4ffa8_3021001c_b60f0008; +defparam bootram.RAM2.INIT_04=256'h16439001_32400018_bcb2fff0_16439001_32400015_80000000_b9f40170_a46300ff; +defparam bootram.RAM2.INIT_05=256'hf9e10000_3021ffe4_e860f824_b0000000_b800ffb0_f860f828_b0000000_bc52ffe4; +defparam bootram.RAM2.INIT_06=256'ha48400ff_64830008_80000000_b9f4ff40_3021001c_b60f0008_e9e10000_bc030010; +defparam bootram.RAM2.INIT_07=256'hbcb2fff0_16459001_32400015_80000000_b9f40108_a4a300ff_be120010_aa440020; +defparam bootram.RAM2.INIT_08=256'hf860f824_b0000000_f8a0f828_b0000000_e0651666_bc52ffe4_16459001_32400018; +defparam bootram.RAM2.INIT_09=256'hb9f40174_f9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_b800ffa4; +defparam bootram.RAM2.INIT_0A=256'h3021ffd4_30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024; +defparam bootram.RAM2.INIT_0B=256'h30c01680_10b60000_30c00006_b9f4fd80_f9e10000_10f60000_32c1001c_fac10028; +defparam bootram.RAM2.INIT_0C=256'h6464001f_eac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f400b0; +defparam bootram.RAM2.INIT_0D=256'hb9f4fd34_f9e10000_10f60000_32c1001c_fac10028_3021ffd4_3021002c_b60f0008; +defparam bootram.RAM2.INIT_0E=256'ha884ffff_80841800_14830000_30e00006_b9f40064_30c01688_10b60000_30c00006; +defparam bootram.RAM2.INIT_0F=256'hf9e10000_3021ffe4_30a01690_3021002c_b60f0008_6464001f_eac10028_e9e10000; +defparam bootram.RAM2.INIT_10=256'h80000000_b6910000_80000000_b6110000_30a0ffff_b9f4ee68_80000000_b9f4f580; +defparam bootram.RAM2.INIT_11=256'h80653000_beb2005c_16479003_22400003_80000000_b60f0008_80000000_b60f0008; +defparam bootram.RAM2.INIT_12=256'h30a50004_30e7fffc_bc320040_16432000_e8660000_e8850000_bc230050_a4630003; +defparam bootram.RAM2.INIT_13=256'he1050000_bc120028_aa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003; +defparam bootram.RAM2.INIT_14=256'hbc32ffe0_aa47ffff_30e7ffff_30c60001_30a50001_be320020_16434000_e0660000; +defparam bootram.RAM2.INIT_15=256'h10850000_beb20018_16479003_2240000f_14634000_b60f0008_10600000_b60f0008; +defparam bootram.RAM2.INIT_16=256'he0660000_10e72000_11040000_bc070024_11050000_be030034_a4630003_80662800; +defparam bootram.RAM2.INIT_17=256'he8860000_10650000_b60f0008_30c60001_be32fff0_16474000_31080001_f0680000; +defparam bootram.RAM2.INIT_18=256'h30c60010_e866000c_f8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0; +defparam bootram.RAM2.INIT_19=256'hbcb2002c_16479003_22400003_31080010_be52ffd0_16479003_2240000f_f868000c; +defparam bootram.RAM2.INIT_1A=256'h30840004_be52ffec_16479003_22400003_d8682000_30e7fffc_c8662000_10800000; +defparam bootram.RAM2.INIT_1B=256'hf9e10000_fa61001c_3021ffe0_e86013f0_10880000_b810ff68_11044000_10c43000; +defparam bootram.RAM2.INIT_1C=256'hbc32fff0_aa43ffff_e8730000_3273fffc_99fc1800_bc120018_aa43ffff_326013f0; +defparam bootram.RAM2.INIT_1D=256'h80000000_b9f4ed20_d9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000; +defparam bootram.RAM2.INIT_1E=256'hb9f4ec98_d9e00800_3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0; +defparam bootram.RAM2.INIT_1F=256'h00000000_ffffffff_00000000_ffffffff_30210008_b60f0008_c9e00800_80000000; +defparam bootram.RAM2.INIT_20=256'h65642120_7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000; +defparam bootram.RAM2.INIT_21=256'h55535250_4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b; +defparam bootram.RAM2.INIT_22=256'h50322b20_20555352_74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062; +defparam bootram.RAM2.INIT_23=256'h6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073; +defparam bootram.RAM2.INIT_24=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; +defparam bootram.RAM2.INIT_25=256'h69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068; +defparam bootram.RAM2.INIT_26=256'h62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520; +defparam bootram.RAM2.INIT_27=256'h2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046; +defparam bootram.RAM2.INIT_28=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000; +defparam bootram.RAM2.INIT_29=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; +defparam bootram.RAM2.INIT_2A=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; +defparam bootram.RAM2.INIT_2B=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; +defparam bootram.RAM2.INIT_2C=256'h6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61; +defparam bootram.RAM2.INIT_2D=256'h64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f; +defparam bootram.RAM2.INIT_2E=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563; +defparam bootram.RAM2.INIT_2F=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00; +defparam bootram.RAM2.INIT_30=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; +defparam bootram.RAM2.INIT_31=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; +defparam bootram.RAM2.INIT_32=256'h05050400_2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20; +defparam bootram.RAM2.INIT_33=256'h10101200_06820594_09c407d0_13880d05_00002710_01b200d9_05160364_14580a2c; +defparam bootram.RAM2.INIT_34=256'h00202020_00000000_6f72740a_0a0a6162_aa990000_ffffffff_b8080000_b0000000; +defparam bootram.RAM2.INIT_35=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; +defparam bootram.RAM2.INIT_36=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; +defparam bootram.RAM2.INIT_37=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; +defparam bootram.RAM2.INIT_38=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; +defparam bootram.RAM2.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_01=256'h20202020_20202020_20202020_20202020_28282020_20282828_20202020_20202020; +defparam bootram.RAM3.INIT_02=256'h10101010_04041010_04040404_04040404_10101010_10101010_10101010_88101010; +defparam bootram.RAM3.INIT_03=256'h10101010_01010110_01010101_01010101_01010101_01010101_41414101_10414141; +defparam bootram.RAM3.INIT_04=256'h10101020_02020210_02020202_02020202_02020202_02020202_42424202_10424242; +defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00001820_ffffffff_01010100_000013fc_00000000_00000000; +defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 3a6bf0f64..237276fb6 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -286,210 +286,7 @@ module u2plus_core //defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; //defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; -////bootloader 10/5/10 for 32/64Mbit FLASH -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b8081210_00000000_b8080050; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081218; -defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401920_31a01948_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f4047c_80000000_b9f400cc; -defparam bootram.RAM0.INIT_04=256'he8830000_e8601928_80000000_99fc2000_f8601928_b8000044_bc030014_f9e10000; -defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a0193c_bc030010_30600000_b0000000_30630004_be24ffec; -defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; -defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a0193c_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01940_bc030014_30800000_b0000000_e8601940; -defparam bootram.RAM0.INIT_09=256'h06463800_20e01948_20c01948_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; -defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; -defparam bootram.RAM0.INIT_0B=256'hb9f410ac_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; -defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4014c_20e00000_20c00000_80000000_b9f4122c_80000000; -defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f41078_80000000_b9f41234; -defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; -defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; -defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; -defparam bootram.RAM0.INIT_11=256'hb9f40440_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; -defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01438_10b30000_b9f40a18_10d60000_10b30000; -defparam bootram.RAM0.INIT_13=256'h30a01438_bc120040_aa430001_30a01400_e061001c_10a30000_be520034_16439003; -defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f404d4_b800ffb4_80000000_b9f404e0; -defparam bootram.RAM0.INIT_15=256'h80000000_b9f404a8_b800ff88_80000000_b9f404b4_30a01400_80000000_b9f41010; -defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f4048c_30a01404_80000000_b9f40e5c_30a08000_b0000000; -defparam bootram.RAM0.INIT_17=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fa61001c_f9e10000_3021ffe0; -defparam bootram.RAM0.INIT_18=256'hb9f40b9c_80000000_b9f406c0_f800200c_80000000_b9f4fef4_f860200c_306000ff; -defparam bootram.RAM0.INIT_19=256'h30a01504_bc04013c_a4842000_e8803334_80000000_b9f40438_30a0143c_80000000; -defparam bootram.RAM0.INIT_1A=256'h30a01568_bc23010c_80000000_b9f40e58_30a00000_b0000018_80000000_b9f40420; -defparam bootram.RAM0.INIT_1B=256'h30a015b8_bc030058_80000000_b9f40dec_30a00000_b0000030_80000000_b9f40400; -defparam bootram.RAM0.INIT_1C=256'h30c07c00_b9f40b58_30a00000_b0000030_30e08000_b0000000_80000000_b9f403e0; -defparam bootram.RAM0.INIT_1D=256'he9e10000_80000000_b9f403ac_30a015e4_80000000_b9f40d7c_30a08000_b0000000; -defparam bootram.RAM0.INIT_1E=256'hb000003f_80000000_b9f4038c_30a01620_30210020_b60f0008_30600001_ea61001c; -defparam bootram.RAM0.INIT_1F=256'h80000000_b9f40368_30a014ac_12630000_be230030_80000000_b9f40d78_30a00000; -defparam bootram.RAM0.INIT_20=256'hb0000000_30210020_b60f0008_ea61001c_e9e10000_10730000_80000000_b9f4fe1c; -defparam bootram.RAM0.INIT_21=256'hb9f40ce8_30a08000_b0000000_30c07c00_b9f40ac4_30a00000_b000003f_30e08000; -defparam bootram.RAM0.INIT_22=256'hb60f0008_30600001_ea61001c_e9e10000_80000000_b9f40318_30a01470_80000000; -defparam bootram.RAM0.INIT_23=256'h80000000_b9f402e8_30a01450_b800feec_80000000_b9f402f8_30a01530_30210020; -defparam bootram.RAM0.INIT_24=256'h80000000_b9f402c8_30a014ac_bc23001c_80000000_b9f40cd4_30a00000_b000003f; -defparam bootram.RAM0.INIT_25=256'hb9f40a34_30a00000_b000003f_30e08000_b0000000_b800fe94_80000000_b9f4fd7c; -defparam bootram.RAM0.INIT_26=256'h80000000_b9f40288_30a01470_80000000_b9f40c58_30a08000_b0000000_30c07c00; -defparam bootram.RAM0.INIT_27=256'h3021ffd0_80000000_b60f0008_80000000_b9f4fb84_f9e10000_3021ffe4_b800fe5c; -defparam bootram.RAM0.INIT_28=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; -defparam bootram.RAM0.INIT_29=256'hbcb2002c_16572001_bc120030_aa43ffff_12c00000_b810001c_f9e10000_fac10020; -defparam bootram.RAM0.INIT_2A=256'hbe32ffd4_aa43000a_f0730000_10960000_90630060_10b80000_b9f405ec_32730001; -defparam bootram.RAM0.INIT_2B=256'heae10024_eac10020_ea61001c_e9e10000_10640000_f0130000_14999800_32d60001; -defparam bootram.RAM0.INIT_2C=256'hfb010028_fae10024_fa61001c_3021ffd0_30210030_b60f0008_eb21002c_eb010028; -defparam bootram.RAM0.INIT_2D=256'hb8100014_f9e10000_fac10020_13260000_12e70000_13050000_12660000_fb21002c; -defparam bootram.RAM0.INIT_2E=256'h10960000_90630060_10b80000_b9f4051c_32730001_bcb2002c_16572001_12c00000; -defparam bootram.RAM0.INIT_2F=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffdc_aa43000a_f0730000; -defparam bootram.RAM0.INIT_30=256'h3021ffd8_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; -defparam bootram.RAM0.INIT_31=256'hb9f404b0_12660000_f9e10000_12e60000_12c50000_fae10024_fac10020_fa61001c; -defparam bootram.RAM0.INIT_32=256'hf0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000_90630060_10b60000; -defparam bootram.RAM0.INIT_33=256'h10c50000_30210028_b60f0008_eae10024_eac10020_ea61001c_e9e10000_10770000; -defparam bootram.RAM0.INIT_34=256'h3021ffe4_3021001c_b60f0008_e9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_35=256'hf9e10000_3021ffe4_3021001c_b60f0008_e9e10000_80000000_b9f40448_f9e10000; -defparam bootram.RAM0.INIT_36=256'hfac10020_fa61001c_3021ffdc_3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc; -defparam bootram.RAM0.INIT_37=256'hb9f40324_10b60000_12c50000_be060024_90c30060_12660000_e0660000_f9e10000; -defparam bootram.RAM0.INIT_38=256'heac10020_ea61001c_e9e10000_10b60000_be26fff0_90c30060_e0730000_32730001; -defparam bootram.RAM0.INIT_39=256'h12c50000_b9f4ff9c_f9e10000_fac1001c_3021ffe0_30210024_b60f0008_10600000; -defparam bootram.RAM0.INIT_3A=256'h30210020_b60f0008_10600000_eac1001c_e9e10000_30c0000a_b9f402dc_10b60000; -defparam bootram.RAM0.INIT_3B=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000; -defparam bootram.RAM0.INIT_3C=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000; -defparam bootram.RAM0.INIT_3D=256'h3021ffe0_3021001c_b60f0008_e9e10000_30c0000a_b9f40278_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_3E=256'he9e10000_10760000_10d60000_b9f40250_f9e10000_10a00000_12c50000_fac1001c; -defparam bootram.RAM0.INIT_3F=256'h12c60000_b9f40228_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_eac1001c; -defparam bootram.RAM1.INIT_00=256'hb9f401b8_f9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000; -defparam bootram.RAM1.INIT_01=256'hb0000000_9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000; -defparam bootram.RAM1.INIT_02=256'hf860f81c_b0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c; -defparam bootram.RAM1.INIT_03=256'h94608001_80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002; -defparam bootram.RAM1.INIT_04=256'hf8a0f81c_b0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002; -defparam bootram.RAM1.INIT_05=256'h94e08001_80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002; -defparam bootram.RAM1.INIT_06=256'h80633000_84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002; -defparam bootram.RAM1.INIT_07=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020; -defparam bootram.RAM1.INIT_08=256'hfac10020_f9e10000_fb010028_fae10024_fa61001c_3021ffd4_80000000_b60f0008; -defparam bootram.RAM1.INIT_09=256'h32600001_be670038_12660000_be060040_90c30060_13050000_12e60000_e0660000; -defparam bootram.RAM1.INIT_0A=256'hc0779800_10b80000_b9f400cc_10730000_be120028_16569800_32c70001_b8100014; -defparam bootram.RAM1.INIT_0B=256'heac10020_ea61001c_e9e10000_10730000_3273ffff_32730001_be26ffe4_90c30060; -defparam bootram.RAM1.INIT_0C=256'hb9f40084_f9e10000_10a00000_3021ffe4_3021002c_b60f0008_eb010028_eae10024; -defparam bootram.RAM1.INIT_0D=256'h10c63000_80000000_b60f0008_f0c5192c_3021001c_b60f0008_e9e10000_30c0000a; -defparam bootram.RAM1.INIT_0E=256'hf9e10000_fa61001c_3021ffe0_80000000_b60f0008_f8653700_64a50405_e4661660; -defparam bootram.RAM1.INIT_0F=256'h32730001_10b30000_e0d3165c_90c60060_b9f4ffc4_10b30000_e0d3192c_12600000; -defparam bootram.RAM1.INIT_10=256'h30210020_b60f0008_ea61001c_e9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc; -defparam bootram.RAM1.INIT_11=256'h12650000_be120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc; -defparam bootram.RAM1.INIT_12=256'heac10020_ea61001c_e9e10000_fac5000c_bc03fffc_e8650004_30a33700_64730405; -defparam bootram.RAM1.INIT_13=256'hb810ffc8_30c0000d_b9f4ffac_bc32ffd0_aa430001_e065192c_30210024_b60f0008; -defparam bootram.RAM1.INIT_14=256'hbe120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc_64730405; -defparam bootram.RAM1.INIT_15=256'hea61001c_e9e10000_fac3000c_bc040008_e8830004_30633700_64730405_12650000; -defparam bootram.RAM1.INIT_16=256'hb9f4ff44_30c0000d_be32ffd0_aa430001_e065192c_30210024_b60f0008_eac10020; -defparam bootram.RAM1.INIT_17=256'he8650010_bc03fffc_e8650008_30a53700_64a50405_64730405_b810ffc4_80000000; -defparam bootram.RAM1.INIT_18=256'he8850008_e8650010_bc030014_e8650008_30a53700_64a50405_80000000_b60f0008; -defparam bootram.RAM1.INIT_19=256'hf9e10000_fac10020_3021ffdc_64a50405_80000000_b60f0008_90630060_be24fff8; -defparam bootram.RAM1.INIT_1A=256'hbe120034_aa53012d_b8000010_32600001_be230040_e8760008_32c53700_fa61001c; -defparam bootram.RAM1.INIT_1B=256'h3240012b_3273ffff_32730001_be03ffe8_e8760008_30a00001_b9f40040_3060ffff; -defparam bootram.RAM1.INIT_1C=256'hb60f0008_eac10020_ea61001c_e9e10000_e8760010_3060ffff_be52000c_16539001; -defparam bootram.RAM1.INIT_1D=256'hbe650048_bc430054_e8601930_bc260054_a4c30000_b0008000_e8603324_30210024; -defparam bootram.RAM1.INIT_1E=256'h80000000_80000000_80000000_80000000_10800000_bc660030_e8c01930_10660000; -defparam bootram.RAM1.INIT_1F=256'h16432800_30630001_bc32ffdc_16443000_30840001_80000000_80000000_80000000; -defparam bootram.RAM1.INIT_20=256'hf8801930_e483166c_10631800_a4630007_e8603324_80000000_b60f0008_bc32ffc8; -defparam bootram.RAM1.INIT_21=256'h3065ffc9_a46300ff_be520024_16459001_3240005a_3065ffa9_90a50060_b800ff9c; -defparam bootram.RAM1.INIT_22=256'h80000000_b60f0008_a46400ff_3085ffd0_be52000c_16459001_32400039_a46300ff; -defparam bootram.RAM1.INIT_23=256'hfae10024_fac10020_fa61001c_f9e10000_fb610034_13250000_fb21002c_3021ffc8; -defparam bootram.RAM1.INIT_24=256'h10650000_30a0ffff_be120034_aa43003a_13660000_e0790000_fb410030_fb010028; -defparam bootram.RAM1.INIT_25=256'heb610034_eb410030_eb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_26=256'hbe04001c_90840060_30650001_c085c800_30a00001_e8c01934_30210038_b60f0008; -defparam bootram.RAM1.INIT_27=256'hb9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4_a4630044_c0662000_a4a300ff; -defparam bootram.RAM1.INIT_28=256'h10791800_fa7b0004_10739800_12761800_66c30404_b9f4ff1c_e0b90002_80000000; -defparam bootram.RAM1.INIT_29=256'he0b90003_13530000_b9f4fef0_e0b90005_30a0fffd_be38ff74_93040060_e083000b; -defparam bootram.RAM1.INIT_2A=256'hb9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4; -defparam bootram.RAM1.INIT_2B=256'he0b90008_80000000_b9f4feb0_e0b90007_fafb0008_12f7b000_12d61800_12d61800; -defparam bootram.RAM1.INIT_2C=256'hea7b000c_13580000_10f30000_be130060_f07b0000_1063b000_66c30404_b9f4fea4; -defparam bootram.RAM1.INIT_2D=256'hb9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000; -defparam bootram.RAM1.INIT_2E=256'ha70400ff_c073c000_30980001_e8fb0004_ea7b000c_d0789800_1063b800_66e30404; -defparam bootram.RAM1.INIT_2F=256'h64760008_12e73800_e09b0000_eadb0008_a74300ff_be52ffb8_1647c003_107a1800; -defparam bootram.RAM1.INIT_30=256'he0b7000a_12d61800_b9f4fe10_107a1800_12c7b000_10632000_e0b70009_12f9b800; -defparam bootram.RAM1.INIT_31=256'hbe32fe60_1643b000_a46300ff_a6d600ff_1063c000_16d60000_67030404_b9f4fe04; -defparam bootram.RAM1.INIT_32=256'h80000000_b60f0008_bc23fff8_a4630100_e8603b10_10a00000_b810fe58_30a0fffb; -defparam bootram.RAM1.INIT_33=256'hbc23fff8_a4630100_e8603b10_a4a500ff_80884800_a1292000_a508007f_a5290600; -defparam bootram.RAM1.INIT_34=256'h10650000_be050018_f8803b10_a0840100_f8603b18_a46600ff_f8803b10_f8e03b00; -defparam bootram.RAM1.INIT_35=256'h10e60000_10c00000_80000000_b60f0008_e8603b00_bc23fff8_a4630100_e8603b10; -defparam bootram.RAM1.INIT_36=256'hb9f4ff84_f8603b14_30600001_31200400_31000008_10a00000_f9e10000_3021ffe4; -defparam bootram.RAM1.INIT_37=256'hfa61002c_12c50000_fac10030_3021ffc4_3021001c_b60f0008_e9e10000_80000000; -defparam bootram.RAM1.INIT_38=256'hf8003b18_30600400_12670000_b9f4ff3c_fae10034_13060000_f9e10000_fb010038; -defparam bootram.RAM1.INIT_39=256'h30800428_f8603b18_30600001_fac03b00_f8603b04_3060000b_66d60408_f8603b10; -defparam bootram.RAM1.INIT_3A=256'h12e00000_12d30000_be18009c_80000000_b9f4ff00_f8603b10_30600528_f8803b10; -defparam bootram.RAM1.INIT_3B=256'he8803b0c_80000000_b9f4fed8_f8803b10_30800500_f8603b10_30600400_3261001c; -defparam bootram.RAM1.INIT_3C=256'hf8610028_e8603b00_f8810024_e8803b04_f8610020_e8603b08_f881001c_14b7c000; -defparam bootram.RAM1.INIT_3D=256'h30840001_d0762000_c0732000_30a00010_10800000_beb20034_16459003_22400010; -defparam bootram.RAM1.INIT_3E=256'hbc25ffd8_b800ff8c_12d62800_beb20020_1658b803_12f72800_bc32fff0_16442800; -defparam bootram.RAM1.INIT_3F=256'heac10030_ea61002c_e9e10000_f8003b18_12d62800_be52ff7c_1658b803_12f72800; -defparam bootram.RAM2.INIT_00=256'h30a00001_3021ffe4_30e00000_b0009f00_3021003c_b60f0008_eb010038_eae10034; -defparam bootram.RAM2.INIT_01=256'ha463ffff_b00000ff_e9e10000_31200400_b9f4fe34_f9e10000_31000020_30c00001; -defparam bootram.RAM2.INIT_02=256'he9e10000_bc030010_f9e10000_3021ffe4_e860f828_b0000000_3021001c_b60f0008; -defparam bootram.RAM2.INIT_03=256'hbe120010_aa440020_a48400ff_64830008_80000000_b9f4ffa8_3021001c_b60f0008; -defparam bootram.RAM2.INIT_04=256'h16439001_32400018_bcb2fff0_16439001_32400015_80000000_b9f40170_a46300ff; -defparam bootram.RAM2.INIT_05=256'hf9e10000_3021ffe4_e860f824_b0000000_b800ffb0_f860f828_b0000000_bc52ffe4; -defparam bootram.RAM2.INIT_06=256'ha48400ff_64830008_80000000_b9f4ff40_3021001c_b60f0008_e9e10000_bc030010; -defparam bootram.RAM2.INIT_07=256'hbcb2fff0_16459001_32400015_80000000_b9f40108_a4a300ff_be120010_aa440020; -defparam bootram.RAM2.INIT_08=256'hf860f824_b0000000_f8a0f828_b0000000_e0651666_bc52ffe4_16459001_32400018; -defparam bootram.RAM2.INIT_09=256'hb9f40174_f9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_b800ffa4; -defparam bootram.RAM2.INIT_0A=256'h3021ffd4_30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024; -defparam bootram.RAM2.INIT_0B=256'h30c01680_10b60000_30c00006_b9f4fd80_f9e10000_10f60000_32c1001c_fac10028; -defparam bootram.RAM2.INIT_0C=256'h6464001f_eac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f400b0; -defparam bootram.RAM2.INIT_0D=256'hb9f4fd34_f9e10000_10f60000_32c1001c_fac10028_3021ffd4_3021002c_b60f0008; -defparam bootram.RAM2.INIT_0E=256'ha884ffff_80841800_14830000_30e00006_b9f40064_30c01688_10b60000_30c00006; -defparam bootram.RAM2.INIT_0F=256'hf9e10000_3021ffe4_30a01690_3021002c_b60f0008_6464001f_eac10028_e9e10000; -defparam bootram.RAM2.INIT_10=256'h80000000_b6910000_80000000_b6110000_30a0ffff_b9f4ee68_80000000_b9f4f580; -defparam bootram.RAM2.INIT_11=256'h80653000_beb2005c_16479003_22400003_80000000_b60f0008_80000000_b60f0008; -defparam bootram.RAM2.INIT_12=256'h30a50004_30e7fffc_bc320040_16432000_e8660000_e8850000_bc230050_a4630003; -defparam bootram.RAM2.INIT_13=256'he1050000_bc120028_aa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003; -defparam bootram.RAM2.INIT_14=256'hbc32ffe0_aa47ffff_30e7ffff_30c60001_30a50001_be320020_16434000_e0660000; -defparam bootram.RAM2.INIT_15=256'h10850000_beb20018_16479003_2240000f_14634000_b60f0008_10600000_b60f0008; -defparam bootram.RAM2.INIT_16=256'he0660000_10e72000_11040000_bc070024_11050000_be030034_a4630003_80662800; -defparam bootram.RAM2.INIT_17=256'he8860000_10650000_b60f0008_30c60001_be32fff0_16474000_31080001_f0680000; -defparam bootram.RAM2.INIT_18=256'h30c60010_e866000c_f8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0; -defparam bootram.RAM2.INIT_19=256'hbcb2002c_16479003_22400003_31080010_be52ffd0_16479003_2240000f_f868000c; -defparam bootram.RAM2.INIT_1A=256'h30840004_be52ffec_16479003_22400003_d8682000_30e7fffc_c8662000_10800000; -defparam bootram.RAM2.INIT_1B=256'hf9e10000_fa61001c_3021ffe0_e86013f0_10880000_b810ff68_11044000_10c43000; -defparam bootram.RAM2.INIT_1C=256'hbc32fff0_aa43ffff_e8730000_3273fffc_99fc1800_bc120018_aa43ffff_326013f0; -defparam bootram.RAM2.INIT_1D=256'h80000000_b9f4ed20_d9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000; -defparam bootram.RAM2.INIT_1E=256'hb9f4ec98_d9e00800_3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0; -defparam bootram.RAM2.INIT_1F=256'h00000000_ffffffff_00000000_ffffffff_30210008_b60f0008_c9e00800_80000000; -defparam bootram.RAM2.INIT_20=256'h65642120_7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000; -defparam bootram.RAM2.INIT_21=256'h55535250_4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b; -defparam bootram.RAM2.INIT_22=256'h50322b20_20555352_74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062; -defparam bootram.RAM2.INIT_23=256'h6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073; -defparam bootram.RAM2.INIT_24=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; -defparam bootram.RAM2.INIT_25=256'h69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068; -defparam bootram.RAM2.INIT_26=256'h62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520; -defparam bootram.RAM2.INIT_27=256'h2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046; -defparam bootram.RAM2.INIT_28=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000; -defparam bootram.RAM2.INIT_29=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; -defparam bootram.RAM2.INIT_2A=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; -defparam bootram.RAM2.INIT_2B=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; -defparam bootram.RAM2.INIT_2C=256'h6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61; -defparam bootram.RAM2.INIT_2D=256'h64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f; -defparam bootram.RAM2.INIT_2E=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563; -defparam bootram.RAM2.INIT_2F=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00; -defparam bootram.RAM2.INIT_30=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; -defparam bootram.RAM2.INIT_31=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; -defparam bootram.RAM2.INIT_32=256'h05050400_2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20; -defparam bootram.RAM2.INIT_33=256'h10101200_06820594_09c407d0_13880d05_00002710_01b200d9_05160364_14580a2c; -defparam bootram.RAM2.INIT_34=256'h00202020_00000000_6f72740a_0a0a6162_aa990000_ffffffff_b8080000_b0000000; -defparam bootram.RAM2.INIT_35=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; -defparam bootram.RAM2.INIT_36=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; -defparam bootram.RAM2.INIT_37=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; -defparam bootram.RAM2.INIT_38=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; -defparam bootram.RAM2.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_01=256'h20202020_20202020_20202020_20202020_28282020_20282828_20202020_20202020; -defparam bootram.RAM3.INIT_02=256'h10101010_04041010_04040404_04040404_10101010_10101010_10101010_88101010; -defparam bootram.RAM3.INIT_03=256'h10101010_01010110_01010101_01010101_01010101_01010101_41414101_10414141; -defparam bootram.RAM3.INIT_04=256'h10101020_02020210_02020202_02020202_02020202_02020202_42424202_10424242; -defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00001820_ffffffff_01010100_000013fc_00000000_00000000; -defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +`include "bootloader.rmi" ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), -- cgit v1.2.3 From 1ec89790b085e7be3d69c785c036ce4e66201357 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 7 Oct 2010 15:44:30 -0700 Subject: U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not asserted. which is the point of a CE, but... it works. Also committed latest bootloader, might not be final version. --- usrp2/control_lib/s3a_icap_wb.v | 17 +- usrp2/top/u2plus/bootloader.rmi | 427 +++++++++++++++++++++------------------- 2 files changed, 238 insertions(+), 206 deletions(-) diff --git a/usrp2/control_lib/s3a_icap_wb.v b/usrp2/control_lib/s3a_icap_wb.v index 9a9db0f96..73ddac385 100644 --- a/usrp2/control_lib/s3a_icap_wb.v +++ b/usrp2/control_lib/s3a_icap_wb.v @@ -3,18 +3,19 @@ module s3a_icap_wb (input clk, input reset, input cyc_i, input stb_i, input we_i, output ack_o, - input [31:0] dat_i, output [31:0] dat_o); + input [31:0] dat_i, output [31:0] dat_o)//, output [31:0] debug_out); assign dat_o[31:8] = 24'd0; - wire BUSY, CE, WRITE; + wire BUSY, CE, WRITE, ICAPCLK; + //changed this to gray-ish code to prevent glitching reg [2:0] icap_state; localparam ICAP_IDLE = 0; localparam ICAP_WR0 = 1; - localparam ICAP_WR1 = 2; - localparam ICAP_RD0 = 3; - localparam ICAP_RD1 = 4; + localparam ICAP_WR1 = 5; + localparam ICAP_RD0 = 2; + localparam ICAP_RD1 = 3; always @(posedge clk) if(reset) @@ -40,15 +41,17 @@ module s3a_icap_wb endcase // case (icap_state) assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1); - assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0); + assign CE = (icap_state == ICAP_WR0) | (icap_state == ICAP_RD0); + assign ICAPCLK = CE & (~clk); assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1); + //assign debug_out = {17'd0, BUSY, dat_i[7:0], ~CE, ICAPCLK, ~WRITE, icap_state}; ICAP_SPARTAN3A ICAP_SPARTAN3A_inst (.BUSY(BUSY), // Busy output .O(dat_o[7:0]), // 32-bit data output .CE(~CE), // Clock enable input - .CLK(clk), // Clock input + .CLK(ICAPCLK), // Clock input .I(dat_i[7:0]), // 32-bit data input .WRITE(~WRITE) // Write input ); diff --git a/usrp2/top/u2plus/bootloader.rmi b/usrp2/top/u2plus/bootloader.rmi index 02ec11060..9e3f99331 100644 --- a/usrp2/top/u2plus/bootloader.rmi +++ b/usrp2/top/u2plus/bootloader.rmi @@ -1,204 +1,233 @@ -////bootloader 10/5/10 for 32/64Mbit FLASH -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b8081210_00000000_b8080050; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081218; -defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401920_31a01948_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f4047c_80000000_b9f400cc; -defparam bootram.RAM0.INIT_04=256'he8830000_e8601928_80000000_99fc2000_f8601928_b8000044_bc030014_f9e10000; -defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a0193c_bc030010_30600000_b0000000_30630004_be24ffec; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b80815d8_00000000_b8080050; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b80815e0; +defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401ce0_31a01d08_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f4069c_80000000_b9f400cc; +defparam bootram.RAM0.INIT_04=256'he8830000_e8601ce8_80000000_99fc2000_f8601ce8_b8000044_bc030014_f9e10000; +defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01cfc_bc030010_30600000_b0000000_30630004_be24ffec; defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; -defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a0193c_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01940_bc030014_30800000_b0000000_e8601940; -defparam bootram.RAM0.INIT_09=256'h06463800_20e01948_20c01948_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; +defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01cfc_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01d00_bc030014_30800000_b0000000_e8601d00; +defparam bootram.RAM0.INIT_09=256'h06463800_20e01d08_20c01d08_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; -defparam bootram.RAM0.INIT_0B=256'hb9f410ac_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; -defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4014c_20e00000_20c00000_80000000_b9f4122c_80000000; -defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f41078_80000000_b9f41234; +defparam bootram.RAM0.INIT_0B=256'hb9f41474_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; +defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401a4_20e00000_20c00000_80000000_b9f415f4_80000000; +defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f41440_80000000_b9f415fc; defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; -defparam bootram.RAM0.INIT_11=256'hb9f40440_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; -defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01438_10b30000_b9f40a18_10d60000_10b30000; -defparam bootram.RAM0.INIT_13=256'h30a01438_bc120040_aa430001_30a01400_e061001c_10a30000_be520034_16439003; -defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f404d4_b800ffb4_80000000_b9f404e0; -defparam bootram.RAM0.INIT_15=256'h80000000_b9f404a8_b800ff88_80000000_b9f404b4_30a01400_80000000_b9f41010; -defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f4048c_30a01404_80000000_b9f40e5c_30a08000_b0000000; -defparam bootram.RAM0.INIT_17=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fa61001c_f9e10000_3021ffe0; -defparam bootram.RAM0.INIT_18=256'hb9f40b9c_80000000_b9f406c0_f800200c_80000000_b9f4fef4_f860200c_306000ff; -defparam bootram.RAM0.INIT_19=256'h30a01504_bc04013c_a4842000_e8803334_80000000_b9f40438_30a0143c_80000000; -defparam bootram.RAM0.INIT_1A=256'h30a01568_bc23010c_80000000_b9f40e58_30a00000_b0000018_80000000_b9f40420; -defparam bootram.RAM0.INIT_1B=256'h30a015b8_bc030058_80000000_b9f40dec_30a00000_b0000030_80000000_b9f40400; -defparam bootram.RAM0.INIT_1C=256'h30c07c00_b9f40b58_30a00000_b0000030_30e08000_b0000000_80000000_b9f403e0; -defparam bootram.RAM0.INIT_1D=256'he9e10000_80000000_b9f403ac_30a015e4_80000000_b9f40d7c_30a08000_b0000000; -defparam bootram.RAM0.INIT_1E=256'hb000003f_80000000_b9f4038c_30a01620_30210020_b60f0008_30600001_ea61001c; -defparam bootram.RAM0.INIT_1F=256'h80000000_b9f40368_30a014ac_12630000_be230030_80000000_b9f40d78_30a00000; -defparam bootram.RAM0.INIT_20=256'hb0000000_30210020_b60f0008_ea61001c_e9e10000_10730000_80000000_b9f4fe1c; -defparam bootram.RAM0.INIT_21=256'hb9f40ce8_30a08000_b0000000_30c07c00_b9f40ac4_30a00000_b000003f_30e08000; -defparam bootram.RAM0.INIT_22=256'hb60f0008_30600001_ea61001c_e9e10000_80000000_b9f40318_30a01470_80000000; -defparam bootram.RAM0.INIT_23=256'h80000000_b9f402e8_30a01450_b800feec_80000000_b9f402f8_30a01530_30210020; -defparam bootram.RAM0.INIT_24=256'h80000000_b9f402c8_30a014ac_bc23001c_80000000_b9f40cd4_30a00000_b000003f; -defparam bootram.RAM0.INIT_25=256'hb9f40a34_30a00000_b000003f_30e08000_b0000000_b800fe94_80000000_b9f4fd7c; -defparam bootram.RAM0.INIT_26=256'h80000000_b9f40288_30a01470_80000000_b9f40c58_30a08000_b0000000_30c07c00; -defparam bootram.RAM0.INIT_27=256'h3021ffd0_80000000_b60f0008_80000000_b9f4fb84_f9e10000_3021ffe4_b800fe5c; -defparam bootram.RAM0.INIT_28=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; -defparam bootram.RAM0.INIT_29=256'hbcb2002c_16572001_bc120030_aa43ffff_12c00000_b810001c_f9e10000_fac10020; -defparam bootram.RAM0.INIT_2A=256'hbe32ffd4_aa43000a_f0730000_10960000_90630060_10b80000_b9f405ec_32730001; -defparam bootram.RAM0.INIT_2B=256'heae10024_eac10020_ea61001c_e9e10000_10640000_f0130000_14999800_32d60001; -defparam bootram.RAM0.INIT_2C=256'hfb010028_fae10024_fa61001c_3021ffd0_30210030_b60f0008_eb21002c_eb010028; -defparam bootram.RAM0.INIT_2D=256'hb8100014_f9e10000_fac10020_13260000_12e70000_13050000_12660000_fb21002c; -defparam bootram.RAM0.INIT_2E=256'h10960000_90630060_10b80000_b9f4051c_32730001_bcb2002c_16572001_12c00000; -defparam bootram.RAM0.INIT_2F=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffdc_aa43000a_f0730000; -defparam bootram.RAM0.INIT_30=256'h3021ffd8_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; -defparam bootram.RAM0.INIT_31=256'hb9f404b0_12660000_f9e10000_12e60000_12c50000_fae10024_fac10020_fa61001c; -defparam bootram.RAM0.INIT_32=256'hf0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000_90630060_10b60000; -defparam bootram.RAM0.INIT_33=256'h10c50000_30210028_b60f0008_eae10024_eac10020_ea61001c_e9e10000_10770000; -defparam bootram.RAM0.INIT_34=256'h3021ffe4_3021001c_b60f0008_e9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_35=256'hf9e10000_3021ffe4_3021001c_b60f0008_e9e10000_80000000_b9f40448_f9e10000; -defparam bootram.RAM0.INIT_36=256'hfac10020_fa61001c_3021ffdc_3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc; -defparam bootram.RAM0.INIT_37=256'hb9f40324_10b60000_12c50000_be060024_90c30060_12660000_e0660000_f9e10000; -defparam bootram.RAM0.INIT_38=256'heac10020_ea61001c_e9e10000_10b60000_be26fff0_90c30060_e0730000_32730001; -defparam bootram.RAM0.INIT_39=256'h12c50000_b9f4ff9c_f9e10000_fac1001c_3021ffe0_30210024_b60f0008_10600000; -defparam bootram.RAM0.INIT_3A=256'h30210020_b60f0008_10600000_eac1001c_e9e10000_30c0000a_b9f402dc_10b60000; -defparam bootram.RAM0.INIT_3B=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000; -defparam bootram.RAM0.INIT_3C=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000; -defparam bootram.RAM0.INIT_3D=256'h3021ffe0_3021001c_b60f0008_e9e10000_30c0000a_b9f40278_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_3E=256'he9e10000_10760000_10d60000_b9f40250_f9e10000_10a00000_12c50000_fac1001c; -defparam bootram.RAM0.INIT_3F=256'h12c60000_b9f40228_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_eac1001c; -defparam bootram.RAM1.INIT_00=256'hb9f401b8_f9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000; -defparam bootram.RAM1.INIT_01=256'hb0000000_9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000; -defparam bootram.RAM1.INIT_02=256'hf860f81c_b0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c; -defparam bootram.RAM1.INIT_03=256'h94608001_80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002; -defparam bootram.RAM1.INIT_04=256'hf8a0f81c_b0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002; -defparam bootram.RAM1.INIT_05=256'h94e08001_80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002; -defparam bootram.RAM1.INIT_06=256'h80633000_84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002; -defparam bootram.RAM1.INIT_07=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020; -defparam bootram.RAM1.INIT_08=256'hfac10020_f9e10000_fb010028_fae10024_fa61001c_3021ffd4_80000000_b60f0008; -defparam bootram.RAM1.INIT_09=256'h32600001_be670038_12660000_be060040_90c30060_13050000_12e60000_e0660000; -defparam bootram.RAM1.INIT_0A=256'hc0779800_10b80000_b9f400cc_10730000_be120028_16569800_32c70001_b8100014; -defparam bootram.RAM1.INIT_0B=256'heac10020_ea61001c_e9e10000_10730000_3273ffff_32730001_be26ffe4_90c30060; -defparam bootram.RAM1.INIT_0C=256'hb9f40084_f9e10000_10a00000_3021ffe4_3021002c_b60f0008_eb010028_eae10024; -defparam bootram.RAM1.INIT_0D=256'h10c63000_80000000_b60f0008_f0c5192c_3021001c_b60f0008_e9e10000_30c0000a; -defparam bootram.RAM1.INIT_0E=256'hf9e10000_fa61001c_3021ffe0_80000000_b60f0008_f8653700_64a50405_e4661660; -defparam bootram.RAM1.INIT_0F=256'h32730001_10b30000_e0d3165c_90c60060_b9f4ffc4_10b30000_e0d3192c_12600000; -defparam bootram.RAM1.INIT_10=256'h30210020_b60f0008_ea61001c_e9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc; -defparam bootram.RAM1.INIT_11=256'h12650000_be120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc; -defparam bootram.RAM1.INIT_12=256'heac10020_ea61001c_e9e10000_fac5000c_bc03fffc_e8650004_30a33700_64730405; -defparam bootram.RAM1.INIT_13=256'hb810ffc8_30c0000d_b9f4ffac_bc32ffd0_aa430001_e065192c_30210024_b60f0008; -defparam bootram.RAM1.INIT_14=256'hbe120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc_64730405; -defparam bootram.RAM1.INIT_15=256'hea61001c_e9e10000_fac3000c_bc040008_e8830004_30633700_64730405_12650000; -defparam bootram.RAM1.INIT_16=256'hb9f4ff44_30c0000d_be32ffd0_aa430001_e065192c_30210024_b60f0008_eac10020; -defparam bootram.RAM1.INIT_17=256'he8650010_bc03fffc_e8650008_30a53700_64a50405_64730405_b810ffc4_80000000; -defparam bootram.RAM1.INIT_18=256'he8850008_e8650010_bc030014_e8650008_30a53700_64a50405_80000000_b60f0008; -defparam bootram.RAM1.INIT_19=256'hf9e10000_fac10020_3021ffdc_64a50405_80000000_b60f0008_90630060_be24fff8; -defparam bootram.RAM1.INIT_1A=256'hbe120034_aa53012d_b8000010_32600001_be230040_e8760008_32c53700_fa61001c; -defparam bootram.RAM1.INIT_1B=256'h3240012b_3273ffff_32730001_be03ffe8_e8760008_30a00001_b9f40040_3060ffff; -defparam bootram.RAM1.INIT_1C=256'hb60f0008_eac10020_ea61001c_e9e10000_e8760010_3060ffff_be52000c_16539001; -defparam bootram.RAM1.INIT_1D=256'hbe650048_bc430054_e8601930_bc260054_a4c30000_b0008000_e8603324_30210024; -defparam bootram.RAM1.INIT_1E=256'h80000000_80000000_80000000_80000000_10800000_bc660030_e8c01930_10660000; -defparam bootram.RAM1.INIT_1F=256'h16432800_30630001_bc32ffdc_16443000_30840001_80000000_80000000_80000000; -defparam bootram.RAM1.INIT_20=256'hf8801930_e483166c_10631800_a4630007_e8603324_80000000_b60f0008_bc32ffc8; -defparam bootram.RAM1.INIT_21=256'h3065ffc9_a46300ff_be520024_16459001_3240005a_3065ffa9_90a50060_b800ff9c; -defparam bootram.RAM1.INIT_22=256'h80000000_b60f0008_a46400ff_3085ffd0_be52000c_16459001_32400039_a46300ff; -defparam bootram.RAM1.INIT_23=256'hfae10024_fac10020_fa61001c_f9e10000_fb610034_13250000_fb21002c_3021ffc8; -defparam bootram.RAM1.INIT_24=256'h10650000_30a0ffff_be120034_aa43003a_13660000_e0790000_fb410030_fb010028; -defparam bootram.RAM1.INIT_25=256'heb610034_eb410030_eb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_26=256'hbe04001c_90840060_30650001_c085c800_30a00001_e8c01934_30210038_b60f0008; -defparam bootram.RAM1.INIT_27=256'hb9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4_a4630044_c0662000_a4a300ff; -defparam bootram.RAM1.INIT_28=256'h10791800_fa7b0004_10739800_12761800_66c30404_b9f4ff1c_e0b90002_80000000; -defparam bootram.RAM1.INIT_29=256'he0b90003_13530000_b9f4fef0_e0b90005_30a0fffd_be38ff74_93040060_e083000b; -defparam bootram.RAM1.INIT_2A=256'hb9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4; -defparam bootram.RAM1.INIT_2B=256'he0b90008_80000000_b9f4feb0_e0b90007_fafb0008_12f7b000_12d61800_12d61800; -defparam bootram.RAM1.INIT_2C=256'hea7b000c_13580000_10f30000_be130060_f07b0000_1063b000_66c30404_b9f4fea4; -defparam bootram.RAM1.INIT_2D=256'hb9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000; -defparam bootram.RAM1.INIT_2E=256'ha70400ff_c073c000_30980001_e8fb0004_ea7b000c_d0789800_1063b800_66e30404; -defparam bootram.RAM1.INIT_2F=256'h64760008_12e73800_e09b0000_eadb0008_a74300ff_be52ffb8_1647c003_107a1800; -defparam bootram.RAM1.INIT_30=256'he0b7000a_12d61800_b9f4fe10_107a1800_12c7b000_10632000_e0b70009_12f9b800; -defparam bootram.RAM1.INIT_31=256'hbe32fe60_1643b000_a46300ff_a6d600ff_1063c000_16d60000_67030404_b9f4fe04; -defparam bootram.RAM1.INIT_32=256'h80000000_b60f0008_bc23fff8_a4630100_e8603b10_10a00000_b810fe58_30a0fffb; -defparam bootram.RAM1.INIT_33=256'hbc23fff8_a4630100_e8603b10_a4a500ff_80884800_a1292000_a508007f_a5290600; -defparam bootram.RAM1.INIT_34=256'h10650000_be050018_f8803b10_a0840100_f8603b18_a46600ff_f8803b10_f8e03b00; -defparam bootram.RAM1.INIT_35=256'h10e60000_10c00000_80000000_b60f0008_e8603b00_bc23fff8_a4630100_e8603b10; -defparam bootram.RAM1.INIT_36=256'hb9f4ff84_f8603b14_30600001_31200400_31000008_10a00000_f9e10000_3021ffe4; -defparam bootram.RAM1.INIT_37=256'hfa61002c_12c50000_fac10030_3021ffc4_3021001c_b60f0008_e9e10000_80000000; -defparam bootram.RAM1.INIT_38=256'hf8003b18_30600400_12670000_b9f4ff3c_fae10034_13060000_f9e10000_fb010038; -defparam bootram.RAM1.INIT_39=256'h30800428_f8603b18_30600001_fac03b00_f8603b04_3060000b_66d60408_f8603b10; -defparam bootram.RAM1.INIT_3A=256'h12e00000_12d30000_be18009c_80000000_b9f4ff00_f8603b10_30600528_f8803b10; -defparam bootram.RAM1.INIT_3B=256'he8803b0c_80000000_b9f4fed8_f8803b10_30800500_f8603b10_30600400_3261001c; -defparam bootram.RAM1.INIT_3C=256'hf8610028_e8603b00_f8810024_e8803b04_f8610020_e8603b08_f881001c_14b7c000; -defparam bootram.RAM1.INIT_3D=256'h30840001_d0762000_c0732000_30a00010_10800000_beb20034_16459003_22400010; -defparam bootram.RAM1.INIT_3E=256'hbc25ffd8_b800ff8c_12d62800_beb20020_1658b803_12f72800_bc32fff0_16442800; -defparam bootram.RAM1.INIT_3F=256'heac10030_ea61002c_e9e10000_f8003b18_12d62800_be52ff7c_1658b803_12f72800; -defparam bootram.RAM2.INIT_00=256'h30a00001_3021ffe4_30e00000_b0009f00_3021003c_b60f0008_eb010038_eae10034; -defparam bootram.RAM2.INIT_01=256'ha463ffff_b00000ff_e9e10000_31200400_b9f4fe34_f9e10000_31000020_30c00001; -defparam bootram.RAM2.INIT_02=256'he9e10000_bc030010_f9e10000_3021ffe4_e860f828_b0000000_3021001c_b60f0008; -defparam bootram.RAM2.INIT_03=256'hbe120010_aa440020_a48400ff_64830008_80000000_b9f4ffa8_3021001c_b60f0008; -defparam bootram.RAM2.INIT_04=256'h16439001_32400018_bcb2fff0_16439001_32400015_80000000_b9f40170_a46300ff; -defparam bootram.RAM2.INIT_05=256'hf9e10000_3021ffe4_e860f824_b0000000_b800ffb0_f860f828_b0000000_bc52ffe4; -defparam bootram.RAM2.INIT_06=256'ha48400ff_64830008_80000000_b9f4ff40_3021001c_b60f0008_e9e10000_bc030010; -defparam bootram.RAM2.INIT_07=256'hbcb2fff0_16459001_32400015_80000000_b9f40108_a4a300ff_be120010_aa440020; -defparam bootram.RAM2.INIT_08=256'hf860f824_b0000000_f8a0f828_b0000000_e0651666_bc52ffe4_16459001_32400018; -defparam bootram.RAM2.INIT_09=256'hb9f40174_f9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_b800ffa4; -defparam bootram.RAM2.INIT_0A=256'h3021ffd4_30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024; -defparam bootram.RAM2.INIT_0B=256'h30c01680_10b60000_30c00006_b9f4fd80_f9e10000_10f60000_32c1001c_fac10028; -defparam bootram.RAM2.INIT_0C=256'h6464001f_eac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f400b0; -defparam bootram.RAM2.INIT_0D=256'hb9f4fd34_f9e10000_10f60000_32c1001c_fac10028_3021ffd4_3021002c_b60f0008; -defparam bootram.RAM2.INIT_0E=256'ha884ffff_80841800_14830000_30e00006_b9f40064_30c01688_10b60000_30c00006; -defparam bootram.RAM2.INIT_0F=256'hf9e10000_3021ffe4_30a01690_3021002c_b60f0008_6464001f_eac10028_e9e10000; -defparam bootram.RAM2.INIT_10=256'h80000000_b6910000_80000000_b6110000_30a0ffff_b9f4ee68_80000000_b9f4f580; -defparam bootram.RAM2.INIT_11=256'h80653000_beb2005c_16479003_22400003_80000000_b60f0008_80000000_b60f0008; -defparam bootram.RAM2.INIT_12=256'h30a50004_30e7fffc_bc320040_16432000_e8660000_e8850000_bc230050_a4630003; -defparam bootram.RAM2.INIT_13=256'he1050000_bc120028_aa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003; -defparam bootram.RAM2.INIT_14=256'hbc32ffe0_aa47ffff_30e7ffff_30c60001_30a50001_be320020_16434000_e0660000; -defparam bootram.RAM2.INIT_15=256'h10850000_beb20018_16479003_2240000f_14634000_b60f0008_10600000_b60f0008; -defparam bootram.RAM2.INIT_16=256'he0660000_10e72000_11040000_bc070024_11050000_be030034_a4630003_80662800; -defparam bootram.RAM2.INIT_17=256'he8860000_10650000_b60f0008_30c60001_be32fff0_16474000_31080001_f0680000; -defparam bootram.RAM2.INIT_18=256'h30c60010_e866000c_f8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0; -defparam bootram.RAM2.INIT_19=256'hbcb2002c_16479003_22400003_31080010_be52ffd0_16479003_2240000f_f868000c; -defparam bootram.RAM2.INIT_1A=256'h30840004_be52ffec_16479003_22400003_d8682000_30e7fffc_c8662000_10800000; -defparam bootram.RAM2.INIT_1B=256'hf9e10000_fa61001c_3021ffe0_e86013f0_10880000_b810ff68_11044000_10c43000; -defparam bootram.RAM2.INIT_1C=256'hbc32fff0_aa43ffff_e8730000_3273fffc_99fc1800_bc120018_aa43ffff_326013f0; -defparam bootram.RAM2.INIT_1D=256'h80000000_b9f4ed20_d9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000; -defparam bootram.RAM2.INIT_1E=256'hb9f4ec98_d9e00800_3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0; -defparam bootram.RAM2.INIT_1F=256'h00000000_ffffffff_00000000_ffffffff_30210008_b60f0008_c9e00800_80000000; -defparam bootram.RAM2.INIT_20=256'h65642120_7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000; -defparam bootram.RAM2.INIT_21=256'h55535250_4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b; -defparam bootram.RAM2.INIT_22=256'h50322b20_20555352_74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062; -defparam bootram.RAM2.INIT_23=256'h6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073; -defparam bootram.RAM2.INIT_24=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; -defparam bootram.RAM2.INIT_25=256'h69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068; -defparam bootram.RAM2.INIT_26=256'h62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520; -defparam bootram.RAM2.INIT_27=256'h2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046; -defparam bootram.RAM2.INIT_28=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000; -defparam bootram.RAM2.INIT_29=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; -defparam bootram.RAM2.INIT_2A=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; -defparam bootram.RAM2.INIT_2B=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; -defparam bootram.RAM2.INIT_2C=256'h6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61; -defparam bootram.RAM2.INIT_2D=256'h64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f; -defparam bootram.RAM2.INIT_2E=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563; -defparam bootram.RAM2.INIT_2F=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00; -defparam bootram.RAM2.INIT_30=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; -defparam bootram.RAM2.INIT_31=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; -defparam bootram.RAM2.INIT_32=256'h05050400_2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20; -defparam bootram.RAM2.INIT_33=256'h10101200_06820594_09c407d0_13880d05_00002710_01b200d9_05160364_14580a2c; -defparam bootram.RAM2.INIT_34=256'h00202020_00000000_6f72740a_0a0a6162_aa990000_ffffffff_b8080000_b0000000; -defparam bootram.RAM2.INIT_35=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; -defparam bootram.RAM2.INIT_36=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; -defparam bootram.RAM2.INIT_37=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; -defparam bootram.RAM2.INIT_38=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; -defparam bootram.RAM2.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_01=256'h20202020_20202020_20202020_20202020_28282020_20282828_20202020_20202020; -defparam bootram.RAM3.INIT_02=256'h10101010_04041010_04040404_04040404_10101010_10101010_10101010_88101010; -defparam bootram.RAM3.INIT_03=256'h10101010_01010110_01010101_01010101_01010101_01010101_41414101_10414141; -defparam bootram.RAM3.INIT_04=256'h10101020_02020210_02020202_02020202_02020202_02020202_42424202_10424242; -defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00001820_ffffffff_01010100_000013fc_00000000_00000000; -defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_11=256'hb9f40660_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; +defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01800_10b30000_b9f40c38_10d60000_10b30000; +defparam bootram.RAM0.INIT_13=256'h30a01800_bc120040_aa430001_30a017c8_e061001c_10a30000_be520034_16439003; +defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406f4_b800ffb4_80000000_b9f40700; +defparam bootram.RAM0.INIT_15=256'h80000000_b9f406c8_b800ff88_80000000_b9f406d4_30a017c8_80000000_b9f413d8; +defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f406ac_30a017cc_80000000_b9f410dc_30a08000_b0000000; +defparam bootram.RAM0.INIT_17=256'he9e10000_30e00001_b9f4035c_f9e10000_30a0fff7_30c1001c_f0a1001c_3021ffe0; +defparam bootram.RAM0.INIT_18=256'h30e00001_b9f40294_f9e10000_30c1001c_30a0fff7_3021ffe0_30210020_b60f0008; +defparam bootram.RAM0.INIT_19=256'hf9e10000_3021ffdc_30210020_b60f0008_6463001f_14630000_e9e10000_e061001c; +defparam bootram.RAM0.INIT_1A=256'h306000ff_30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c; +defparam bootram.RAM0.INIT_1B=256'h80000000_b9f40d60_80000000_b9f40884_f800200c_80000000_b9f4fe98_f860200c; +defparam bootram.RAM0.INIT_1C=256'hbe23017c_80000000_b9f4ff74_80000000_b9f405f4_30a01804_80000000_b9f4020c; +defparam bootram.RAM0.INIT_1D=256'hb9f41020_30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000; +defparam bootram.RAM0.INIT_1E=256'h30e08000_b0000000_80000000_b9f405b0_30a01980_12c30000_be030068_80000000; +defparam bootram.RAM0.INIT_1F=256'h80000000_b9f40fac_30a08000_b0000000_30c07c00_b9f40d28_30a00000_b0000030; +defparam bootram.RAM0.INIT_20=256'hea61001c_e9e10000_30600001_10a00000_b9f410e4_80000000_b9f4057c_30a019ac; +defparam bootram.RAM0.INIT_21=256'h30a00000_b000003f_80000000_b9f40550_30a019e8_30210024_b60f0008_eac10020; +defparam bootram.RAM0.INIT_22=256'hb9f4fdc0_80000000_b9f4052c_30a01874_12630000_be230024_80000000_b9f40f9c; +defparam bootram.RAM0.INIT_23=256'hb9f40c94_30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000; +defparam bootram.RAM0.INIT_24=256'h80000000_b9f404e8_30a01838_80000000_b9f40f18_30a08000_b0000000_30c07c00; +defparam bootram.RAM0.INIT_25=256'hb0000018_80000000_b9f404cc_30a018cc_30600001_b810ff70_10b60000_b9f41050; +defparam bootram.RAM0.INIT_26=256'hb800fed8_80000000_b9f404ac_30a01930_bc230098_80000000_b9f40e80_30a00000; +defparam bootram.RAM0.INIT_27=256'hbc230028_80000000_b9f40ee8_30a00000_b000003f_80000000_b9f4049c_30a01818; +defparam bootram.RAM0.INIT_28=256'h10a00000_b9f4fdc8_b800fe9c_80000000_b9f4fd10_80000000_b9f4047c_30a01874; +defparam bootram.RAM0.INIT_29=256'hb0000000_30c07c00_b9f40bdc_30a00000_b000003f_30e08000_b0000000_b800fe84; +defparam bootram.RAM0.INIT_2A=256'h10b30000_b9f40f98_80000000_b9f40430_30a01838_80000000_b9f40e60_30a08000; +defparam bootram.RAM0.INIT_2B=256'h30a00000_b0000018_30a00001_b9f4fd70_80000000_b9f40418_30a018f8_b800fe50; +defparam bootram.RAM0.INIT_2C=256'h30600080_f8003104_f8603100_30600012_f8003108_b800ff48_80000000_b9f40f70; +defparam bootram.RAM0.INIT_2D=256'hbe23fff8_a4630040_e8603110_a4a500ff_be070088_80000000_b60f0008_f8603108; +defparam bootram.RAM0.INIT_2E=256'hbc23fff8_a4630002_e8603110_f8803110_30800090_f860310c_a0630001_10652800; +defparam bootram.RAM0.INIT_2F=256'hf8603110_30600020_be120038_aa470001_10800000_be230058_a4630080_e8603110; +defparam bootram.RAM0.INIT_30=256'h30c60001_be07001c_f0660000_30e7ffff_e860310c_bc23fff8_a4630002_e8603110; +defparam bootram.RAM0.INIT_31=256'h10640000_b60f0008_30800001_30600068_b810ffd0_30600020_be32ffd8_aa470001; +defparam bootram.RAM0.INIT_32=256'hbe23fff8_a4630040_e8603110_a4a500ff_10640000_b60f0008_f8603110_30600040; +defparam bootram.RAM0.INIT_33=256'ha4630002_e8603110_f8603110_306000d0_30600090_be27000c_f860310c_10652800; +defparam bootram.RAM0.INIT_34=256'he0660000_30800001_be070068_10800000_be23005c_a4630080_e8603110_bc23fff8; +defparam bootram.RAM0.INIT_35=256'hbc23fff8_a4630002_e8603110_f8803110_bc120030_aa470001_f860310c_30800010; +defparam bootram.RAM0.INIT_36=256'hb810ffd4_b800ffc4_30c60001_be070028_30e7ffff_be23001c_a4630080_e8603110; +defparam bootram.RAM0.INIT_37=256'hb60f0008_30800001_10640000_b60f0008_f8603110_30600040_10800000_30800050; +defparam bootram.RAM0.INIT_38=256'h3021ffd0_80000000_b60f0008_80000000_b9f4f964_f9e10000_3021ffe4_10640000; +defparam bootram.RAM0.INIT_39=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; +defparam bootram.RAM0.INIT_3A=256'hbcb2002c_16572001_bc120030_aa43ffff_12c00000_b810001c_f9e10000_fac10020; +defparam bootram.RAM0.INIT_3B=256'hbe32ffd4_aa43000a_f0730000_10960000_90630060_10b80000_b9f405ec_32730001; +defparam bootram.RAM0.INIT_3C=256'heae10024_eac10020_ea61001c_e9e10000_10640000_f0130000_14999800_32d60001; +defparam bootram.RAM0.INIT_3D=256'hfb010028_fae10024_fa61001c_3021ffd0_30210030_b60f0008_eb21002c_eb010028; +defparam bootram.RAM0.INIT_3E=256'hb8100014_f9e10000_fac10020_13260000_12e70000_13050000_12660000_fb21002c; +defparam bootram.RAM0.INIT_3F=256'h10960000_90630060_10b80000_b9f4051c_32730001_bcb2002c_16572001_12c00000; +defparam bootram.RAM1.INIT_00=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffdc_aa43000a_f0730000; +defparam bootram.RAM1.INIT_01=256'h3021ffd8_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; +defparam bootram.RAM1.INIT_02=256'hb9f404b0_12660000_f9e10000_12e60000_12c50000_fae10024_fac10020_fa61001c; +defparam bootram.RAM1.INIT_03=256'hf0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000_90630060_10b60000; +defparam bootram.RAM1.INIT_04=256'h10c50000_30210028_b60f0008_eae10024_eac10020_ea61001c_e9e10000_10770000; +defparam bootram.RAM1.INIT_05=256'h3021ffe4_3021001c_b60f0008_e9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4; +defparam bootram.RAM1.INIT_06=256'hf9e10000_3021ffe4_3021001c_b60f0008_e9e10000_80000000_b9f40448_f9e10000; +defparam bootram.RAM1.INIT_07=256'hfac10020_fa61001c_3021ffdc_3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc; +defparam bootram.RAM1.INIT_08=256'hb9f40324_10b60000_12c50000_be060024_90c30060_12660000_e0660000_f9e10000; +defparam bootram.RAM1.INIT_09=256'heac10020_ea61001c_e9e10000_10b60000_be26fff0_90c30060_e0730000_32730001; +defparam bootram.RAM1.INIT_0A=256'h12c50000_b9f4ff9c_f9e10000_fac1001c_3021ffe0_30210024_b60f0008_10600000; +defparam bootram.RAM1.INIT_0B=256'h30210020_b60f0008_10600000_eac1001c_e9e10000_30c0000a_b9f402dc_10b60000; +defparam bootram.RAM1.INIT_0C=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000; +defparam bootram.RAM1.INIT_0D=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000; +defparam bootram.RAM1.INIT_0E=256'h3021ffe0_3021001c_b60f0008_e9e10000_30c0000a_b9f40278_f9e10000_3021ffe4; +defparam bootram.RAM1.INIT_0F=256'he9e10000_10760000_10d60000_b9f40250_f9e10000_10a00000_12c50000_fac1001c; +defparam bootram.RAM1.INIT_10=256'h12c60000_b9f40228_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_eac1001c; +defparam bootram.RAM1.INIT_11=256'hb9f401b8_f9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000; +defparam bootram.RAM1.INIT_12=256'hb0000000_9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000; +defparam bootram.RAM1.INIT_13=256'hf860f81c_b0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c; +defparam bootram.RAM1.INIT_14=256'h94608001_80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002; +defparam bootram.RAM1.INIT_15=256'hf8a0f81c_b0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002; +defparam bootram.RAM1.INIT_16=256'h94e08001_80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002; +defparam bootram.RAM1.INIT_17=256'h80633000_84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002; +defparam bootram.RAM1.INIT_18=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020; +defparam bootram.RAM1.INIT_19=256'hfac10020_f9e10000_fb010028_fae10024_fa61001c_3021ffd4_80000000_b60f0008; +defparam bootram.RAM1.INIT_1A=256'h32600001_be670038_12660000_be060040_90c30060_13050000_12e60000_e0660000; +defparam bootram.RAM1.INIT_1B=256'hc0779800_10b80000_b9f400cc_10730000_be120028_16569800_32c70001_b8100014; +defparam bootram.RAM1.INIT_1C=256'heac10020_ea61001c_e9e10000_10730000_3273ffff_32730001_be26ffe4_90c30060; +defparam bootram.RAM1.INIT_1D=256'hb9f40084_f9e10000_10a00000_3021ffe4_3021002c_b60f0008_eb010028_eae10024; +defparam bootram.RAM1.INIT_1E=256'h10c63000_80000000_b60f0008_f0c51cec_3021001c_b60f0008_e9e10000_30c0000a; +defparam bootram.RAM1.INIT_1F=256'hf9e10000_fa61001c_3021ffe0_80000000_b60f0008_f8653700_64a50405_e4661a28; +defparam bootram.RAM1.INIT_20=256'h32730001_10b30000_e0d31a24_90c60060_b9f4ffc4_10b30000_e0d31cec_12600000; +defparam bootram.RAM1.INIT_21=256'h30210020_b60f0008_ea61001c_e9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc; +defparam bootram.RAM1.INIT_22=256'h12650000_be120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc; +defparam bootram.RAM1.INIT_23=256'heac10020_ea61001c_e9e10000_fac5000c_bc03fffc_e8650004_30a33700_64730405; +defparam bootram.RAM1.INIT_24=256'hb810ffc8_30c0000d_b9f4ffac_bc32ffd0_aa430001_e0651cec_30210024_b60f0008; +defparam bootram.RAM1.INIT_25=256'hbe120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc_64730405; +defparam bootram.RAM1.INIT_26=256'hea61001c_e9e10000_fac3000c_bc040008_e8830004_30633700_64730405_12650000; +defparam bootram.RAM1.INIT_27=256'hb9f4ff44_30c0000d_be32ffd0_aa430001_e0651cec_30210024_b60f0008_eac10020; +defparam bootram.RAM1.INIT_28=256'he8650010_bc03fffc_e8650008_30a53700_64a50405_64730405_b810ffc4_80000000; +defparam bootram.RAM1.INIT_29=256'he8850008_e8650010_bc030014_e8650008_30a53700_64a50405_80000000_b60f0008; +defparam bootram.RAM1.INIT_2A=256'hf9e10000_fac10020_3021ffdc_64a50405_80000000_b60f0008_90630060_be24fff8; +defparam bootram.RAM1.INIT_2B=256'hbe120034_aa53012d_b8000010_32600001_be230040_e8760008_32c53700_fa61001c; +defparam bootram.RAM1.INIT_2C=256'h3240012b_3273ffff_32730001_be03ffe8_e8760008_30a00001_b9f40040_3060ffff; +defparam bootram.RAM1.INIT_2D=256'hb60f0008_eac10020_ea61001c_e9e10000_e8760010_3060ffff_be52000c_16539001; +defparam bootram.RAM1.INIT_2E=256'hbe650048_bc430054_e8601cf0_bc260054_a4c30000_b0008000_e8603324_30210024; +defparam bootram.RAM1.INIT_2F=256'h80000000_80000000_80000000_80000000_10800000_bc660030_e8c01cf0_10660000; +defparam bootram.RAM1.INIT_30=256'h16432800_30630001_bc32ffdc_16443000_30840001_80000000_80000000_80000000; +defparam bootram.RAM1.INIT_31=256'hf8801cf0_e4831a34_10631800_a4630007_e8603324_80000000_b60f0008_bc32ffc8; +defparam bootram.RAM1.INIT_32=256'h3065ffc9_a46300ff_be520024_16459001_3240005a_3065ffa9_90a50060_b800ff9c; +defparam bootram.RAM1.INIT_33=256'h80000000_b60f0008_a46400ff_3085ffd0_be52000c_16459001_32400039_a46300ff; +defparam bootram.RAM1.INIT_34=256'hfae10024_fac10020_fa61001c_f9e10000_fb610034_13250000_fb21002c_3021ffc8; +defparam bootram.RAM1.INIT_35=256'h10650000_30a0ffff_be120034_aa43003a_13660000_e0790000_fb410030_fb010028; +defparam bootram.RAM1.INIT_36=256'heb610034_eb410030_eb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_37=256'hbe04001c_90840060_30650001_c085c800_30a00001_e8c01cf4_30210038_b60f0008; +defparam bootram.RAM1.INIT_38=256'hb9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4_a4630044_c0662000_a4a300ff; +defparam bootram.RAM1.INIT_39=256'h10791800_fa7b0004_10739800_12761800_66c30404_b9f4ff1c_e0b90002_80000000; +defparam bootram.RAM1.INIT_3A=256'he0b90003_13530000_b9f4fef0_e0b90005_30a0fffd_be38ff74_93040060_e083000b; +defparam bootram.RAM1.INIT_3B=256'hb9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4; +defparam bootram.RAM1.INIT_3C=256'he0b90008_80000000_b9f4feb0_e0b90007_fafb0008_12f7b000_12d61800_12d61800; +defparam bootram.RAM1.INIT_3D=256'hea7b000c_13580000_10f30000_be130060_f07b0000_1063b000_66c30404_b9f4fea4; +defparam bootram.RAM1.INIT_3E=256'hb9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000; +defparam bootram.RAM1.INIT_3F=256'ha70400ff_c073c000_30980001_e8fb0004_ea7b000c_d0789800_1063b800_66e30404; +defparam bootram.RAM2.INIT_00=256'h64760008_12e73800_e09b0000_eadb0008_a74300ff_be52ffb8_1647c003_107a1800; +defparam bootram.RAM2.INIT_01=256'he0b7000a_12d61800_b9f4fe10_107a1800_12c7b000_10632000_e0b70009_12f9b800; +defparam bootram.RAM2.INIT_02=256'hbe32fe60_1643b000_a46300ff_a6d600ff_1063c000_16d60000_67030404_b9f4fe04; +defparam bootram.RAM2.INIT_03=256'h80000000_b60f0008_bc23fff8_a4630100_e8603b10_10a00000_b810fe58_30a0fffb; +defparam bootram.RAM2.INIT_04=256'hbc23fff8_a4630100_e8603b10_a4a500ff_80884800_a1292000_a508007f_a5290600; +defparam bootram.RAM2.INIT_05=256'h10650000_be050018_f8803b10_a0840100_f8603b18_a46600ff_f8803b10_f8e03b00; +defparam bootram.RAM2.INIT_06=256'h10e60000_10c00000_80000000_b60f0008_e8603b00_bc23fff8_a4630100_e8603b10; +defparam bootram.RAM2.INIT_07=256'hb9f4ff84_f8603b14_30600001_31200400_31000008_10a00000_f9e10000_3021ffe4; +defparam bootram.RAM2.INIT_08=256'hfa61002c_12c50000_fac10030_3021ffc4_3021001c_b60f0008_e9e10000_80000000; +defparam bootram.RAM2.INIT_09=256'hf8003b18_30600400_12670000_b9f4ff3c_fae10034_13060000_f9e10000_fb010038; +defparam bootram.RAM2.INIT_0A=256'h30800428_f8603b18_30600001_fac03b00_f8603b04_3060000b_66d60408_f8603b10; +defparam bootram.RAM2.INIT_0B=256'h12e00000_12d30000_be18009c_80000000_b9f4ff00_f8603b10_30600528_f8803b10; +defparam bootram.RAM2.INIT_0C=256'he8803b0c_80000000_b9f4fed8_f8803b10_30800500_f8603b10_30600400_3261001c; +defparam bootram.RAM2.INIT_0D=256'hf8610028_e8603b00_f8810024_e8803b04_f8610020_e8603b08_f881001c_14b7c000; +defparam bootram.RAM2.INIT_0E=256'h30840001_d0762000_c0732000_30a00010_10800000_beb20034_16459003_22400010; +defparam bootram.RAM2.INIT_0F=256'hbc25ffd8_b800ff8c_12d62800_beb20020_1658b803_12f72800_bc32fff0_16442800; +defparam bootram.RAM2.INIT_10=256'heac10030_ea61002c_e9e10000_f8003b18_12d62800_be52ff7c_1658b803_12f72800; +defparam bootram.RAM2.INIT_11=256'h30a00001_3021ffe4_30e00000_b0009f00_3021003c_b60f0008_eb010038_eae10034; +defparam bootram.RAM2.INIT_12=256'ha463ffff_b00000ff_e9e10000_31200400_b9f4fe34_f9e10000_31000020_30c00001; +defparam bootram.RAM2.INIT_13=256'he9e10000_bc030010_f9e10000_3021ffe4_e860f828_b0000000_3021001c_b60f0008; +defparam bootram.RAM2.INIT_14=256'hbe120010_aa440020_a48400ff_64830008_80000000_b9f4ffa8_3021001c_b60f0008; +defparam bootram.RAM2.INIT_15=256'h16439001_32400018_bcb2fff0_16439001_32400015_80000000_b9f40318_a46300ff; +defparam bootram.RAM2.INIT_16=256'hf9e10000_3021ffe4_e860f824_b0000000_b800ffb0_f860f828_b0000000_bc52ffe4; +defparam bootram.RAM2.INIT_17=256'ha48400ff_64830008_80000000_b9f4ff40_3021001c_b60f0008_e9e10000_bc030010; +defparam bootram.RAM2.INIT_18=256'hbcb2fff0_16459001_32400015_80000000_b9f402b0_a4a300ff_be120010_aa440020; +defparam bootram.RAM2.INIT_19=256'hf860f824_b0000000_f8a0f828_b0000000_e0651a2e_bc52ffe4_16459001_32400018; +defparam bootram.RAM2.INIT_1A=256'hbe520040_16459001_3240003e_30a50001_10a00000_b810001c_3021ffbc_b800ffa4; +defparam bootram.RAM2.INIT_1B=256'h30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff_e0630004_10612800_10600000; +defparam bootram.RAM2.INIT_1C=256'hb60f0008_30210044_b60f0008_30600001_be32ffc8_aa440099_e0830004_10612800; +defparam bootram.RAM2.INIT_1D=256'hb9f402bc_f9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_30210044; +defparam bootram.RAM2.INIT_1E=256'h3021ffd4_30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024; +defparam bootram.RAM2.INIT_1F=256'h30c01a48_10b60000_30c00006_b9f4fd20_f9e10000_10f60000_32c1001c_fac10028; +defparam bootram.RAM2.INIT_20=256'h6464001f_eac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8; +defparam bootram.RAM2.INIT_21=256'h65240405_65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008; +defparam bootram.RAM2.INIT_22=256'h10842000_a4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407; +defparam bootram.RAM2.INIT_23=256'h80634800_81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800; +defparam bootram.RAM2.INIT_24=256'h65050405_64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008; +defparam bootram.RAM2.INIT_25=256'h10a52800_a4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407; +defparam bootram.RAM2.INIT_26=256'h81294000_81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000; +defparam bootram.RAM2.INIT_27=256'ha6c5ffff_b00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff; +defparam bootram.RAM2.INIT_28=256'hb9f4ff6c_30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000; +defparam bootram.RAM2.INIT_29=256'hb9f4ff4c_30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99; +defparam bootram.RAM2.INIT_2A=256'hb9f4ff2c_30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008; +defparam bootram.RAM2.INIT_2B=256'hb9f4ff0c_30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b; +defparam bootram.RAM2.INIT_2C=256'hb9f4feec_10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000; +defparam bootram.RAM2.INIT_2D=256'h30a01a50_30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020; +defparam bootram.RAM2.INIT_2E=256'h80000000_b6110000_30a0ffff_b9f4eaa0_80000000_b9f4f3d8_f9e10000_3021ffe4; +defparam bootram.RAM2.INIT_2F=256'h16479003_22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000; +defparam bootram.RAM2.INIT_30=256'hbc320040_16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c; +defparam bootram.RAM2.INIT_31=256'haa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc; +defparam bootram.RAM2.INIT_32=256'h30e7ffff_30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028; +defparam bootram.RAM2.INIT_33=256'h16479003_2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff; +defparam bootram.RAM2.INIT_34=256'h11040000_bc070024_11050000_be030034_a4630003_80662800_10850000_beb20018; +defparam bootram.RAM2.INIT_35=256'hb60f0008_30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000; +defparam bootram.RAM2.INIT_36=256'hf8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000; +defparam bootram.RAM2.INIT_37=256'h22400003_31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c; +defparam bootram.RAM2.INIT_38=256'h16479003_22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003; +defparam bootram.RAM2.INIT_39=256'h3021ffe0_e86017b8_10880000_b810ff68_11044000_10c43000_30840004_be52ffec; +defparam bootram.RAM2.INIT_3A=256'he8730000_3273fffc_99fc1800_bc120018_aa43ffff_326017b8_f9e10000_fa61001c; +defparam bootram.RAM2.INIT_3B=256'hd9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff; +defparam bootram.RAM2.INIT_3C=256'h3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e958; +defparam bootram.RAM2.INIT_3D=256'h00000000_ffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e8d0_d9e00800; +defparam bootram.RAM2.INIT_3E=256'h65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff; +defparam bootram.RAM2.INIT_3F=256'h64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e; +defparam bootram.RAM3.INIT_00=256'h74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00; +defparam bootram.RAM3.INIT_01=256'h523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352; +defparam bootram.RAM3.INIT_02=256'h73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572; +defparam bootram.RAM3.INIT_03=256'h6f207361_523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64; +defparam bootram.RAM3.INIT_04=256'h20492061_626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066; +defparam bootram.RAM3.INIT_05=256'h20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120; +defparam bootram.RAM3.INIT_06=256'h69642070_2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f; +defparam bootram.RAM3.INIT_07=256'h64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475; +defparam bootram.RAM3.INIT_08=256'h7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563; +defparam bootram.RAM3.INIT_09=256'h64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e; +defparam bootram.RAM3.INIT_0A=256'h74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20; +defparam bootram.RAM3.INIT_0B=256'h2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20; +defparam bootram.RAM3.INIT_0C=256'h756e642e_6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69; +defparam bootram.RAM3.INIT_0D=256'h6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61; +defparam bootram.RAM3.INIT_0E=256'h65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20; +defparam bootram.RAM3.INIT_0F=256'h6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065; +defparam bootram.RAM3.INIT_10=256'h77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265; +defparam bootram.RAM3.INIT_11=256'h09c407d0_13880d05_00002710_01b200d9_05160364_14580a2c_05050400_2e2e2e00; +defparam bootram.RAM3.INIT_12=256'h00202020_00000000_6f72740a_0a0a6162_b8080000_b0000000_10101200_06820594; +defparam bootram.RAM3.INIT_13=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; +defparam bootram.RAM3.INIT_14=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; +defparam bootram.RAM3.INIT_15=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; +defparam bootram.RAM3.INIT_16=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; +defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_1F=256'h20202020_20202020_20202020_20202020_28282020_20282828_20202020_20202020; +defparam bootram.RAM3.INIT_20=256'h10101010_04041010_04040404_04040404_10101010_10101010_10101010_88101010; +defparam bootram.RAM3.INIT_21=256'h10101010_01010110_01010101_01010101_01010101_01010101_41414101_10414141; +defparam bootram.RAM3.INIT_22=256'h10101020_02020210_02020202_02020202_02020202_02020202_42424202_10424242; +defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00001be0_ffffffff_01010100_000017c4_00000000_00000000; +defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -- cgit v1.2.3 From d8563de88b6630014bcd38f8229f3be1f2c795a5 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 7 Oct 2010 15:48:10 -0700 Subject: U2P: remember your semicolons. --- usrp2/control_lib/s3a_icap_wb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/control_lib/s3a_icap_wb.v b/usrp2/control_lib/s3a_icap_wb.v index 73ddac385..83d9f775e 100644 --- a/usrp2/control_lib/s3a_icap_wb.v +++ b/usrp2/control_lib/s3a_icap_wb.v @@ -3,7 +3,7 @@ module s3a_icap_wb (input clk, input reset, input cyc_i, input stb_i, input we_i, output ack_o, - input [31:0] dat_i, output [31:0] dat_o)//, output [31:0] debug_out); + input [31:0] dat_i, output [31:0] dat_o);//, output [31:0] debug_out); assign dat_o[31:8] = 24'd0; -- cgit v1.2.3 From 0edd06b736fb55cc740c5cf1cbe1ba718b8f3ef0 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Fri, 8 Oct 2010 12:50:48 -0700 Subject: U2P: Working ICAP bootloader. Should be ready for release. --- usrp2/top/u2plus/bootloader.rmi | 460 +++++++++++++++++++++------------------- 1 file changed, 236 insertions(+), 224 deletions(-) diff --git a/usrp2/top/u2plus/bootloader.rmi b/usrp2/top/u2plus/bootloader.rmi index 9e3f99331..7c15699db 100644 --- a/usrp2/top/u2plus/bootloader.rmi +++ b/usrp2/top/u2plus/bootloader.rmi @@ -1,233 +1,245 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b80815d8_00000000_b8080050; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b80815e0; -defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401ce0_31a01d08_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f4069c_80000000_b9f400cc; -defparam bootram.RAM0.INIT_04=256'he8830000_e8601ce8_80000000_99fc2000_f8601ce8_b8000044_bc030014_f9e10000; -defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01cfc_bc030010_30600000_b0000000_30630004_be24ffec; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b808175c_00000000_b8080050; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081764; +defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401e70_31a01e98_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40668_80000000_b9f400cc; +defparam bootram.RAM0.INIT_04=256'he8830000_e8601e78_80000000_99fc2000_f8601e78_b8000044_bc030014_f9e10000; +defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01e8c_bc030010_30600000_b0000000_30630004_be24ffec; defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; -defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01cfc_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01d00_bc030014_30800000_b0000000_e8601d00; -defparam bootram.RAM0.INIT_09=256'h06463800_20e01d08_20c01d08_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; +defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01e8c_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01e90_bc030014_30800000_b0000000_e8601e90; +defparam bootram.RAM0.INIT_09=256'h06463800_20e01e98_20c01e98_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; -defparam bootram.RAM0.INIT_0B=256'hb9f41474_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; -defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401a4_20e00000_20c00000_80000000_b9f415f4_80000000; -defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f41440_80000000_b9f415fc; +defparam bootram.RAM0.INIT_0B=256'hb9f415f8_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; +defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401c8_20e00000_20c00000_80000000_b9f41778_80000000; +defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f415c4_80000000_b9f41780; defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; -defparam bootram.RAM0.INIT_11=256'hb9f40660_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; -defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01800_10b30000_b9f40c38_10d60000_10b30000; -defparam bootram.RAM0.INIT_13=256'h30a01800_bc120040_aa430001_30a017c8_e061001c_10a30000_be520034_16439003; -defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406f4_b800ffb4_80000000_b9f40700; -defparam bootram.RAM0.INIT_15=256'h80000000_b9f406c8_b800ff88_80000000_b9f406d4_30a017c8_80000000_b9f413d8; -defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f406ac_30a017cc_80000000_b9f410dc_30a08000_b0000000; -defparam bootram.RAM0.INIT_17=256'he9e10000_30e00001_b9f4035c_f9e10000_30a0fff7_30c1001c_f0a1001c_3021ffe0; -defparam bootram.RAM0.INIT_18=256'h30e00001_b9f40294_f9e10000_30c1001c_30a0fff7_3021ffe0_30210020_b60f0008; -defparam bootram.RAM0.INIT_19=256'hf9e10000_3021ffdc_30210020_b60f0008_6463001f_14630000_e9e10000_e061001c; -defparam bootram.RAM0.INIT_1A=256'h306000ff_30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c; -defparam bootram.RAM0.INIT_1B=256'h80000000_b9f40d60_80000000_b9f40884_f800200c_80000000_b9f4fe98_f860200c; -defparam bootram.RAM0.INIT_1C=256'hbe23017c_80000000_b9f4ff74_80000000_b9f405f4_30a01804_80000000_b9f4020c; -defparam bootram.RAM0.INIT_1D=256'hb9f41020_30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000; -defparam bootram.RAM0.INIT_1E=256'h30e08000_b0000000_80000000_b9f405b0_30a01980_12c30000_be030068_80000000; -defparam bootram.RAM0.INIT_1F=256'h80000000_b9f40fac_30a08000_b0000000_30c07c00_b9f40d28_30a00000_b0000030; -defparam bootram.RAM0.INIT_20=256'hea61001c_e9e10000_30600001_10a00000_b9f410e4_80000000_b9f4057c_30a019ac; -defparam bootram.RAM0.INIT_21=256'h30a00000_b000003f_80000000_b9f40550_30a019e8_30210024_b60f0008_eac10020; -defparam bootram.RAM0.INIT_22=256'hb9f4fdc0_80000000_b9f4052c_30a01874_12630000_be230024_80000000_b9f40f9c; -defparam bootram.RAM0.INIT_23=256'hb9f40c94_30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000; -defparam bootram.RAM0.INIT_24=256'h80000000_b9f404e8_30a01838_80000000_b9f40f18_30a08000_b0000000_30c07c00; -defparam bootram.RAM0.INIT_25=256'hb0000018_80000000_b9f404cc_30a018cc_30600001_b810ff70_10b60000_b9f41050; -defparam bootram.RAM0.INIT_26=256'hb800fed8_80000000_b9f404ac_30a01930_bc230098_80000000_b9f40e80_30a00000; -defparam bootram.RAM0.INIT_27=256'hbc230028_80000000_b9f40ee8_30a00000_b000003f_80000000_b9f4049c_30a01818; -defparam bootram.RAM0.INIT_28=256'h10a00000_b9f4fdc8_b800fe9c_80000000_b9f4fd10_80000000_b9f4047c_30a01874; -defparam bootram.RAM0.INIT_29=256'hb0000000_30c07c00_b9f40bdc_30a00000_b000003f_30e08000_b0000000_b800fe84; -defparam bootram.RAM0.INIT_2A=256'h10b30000_b9f40f98_80000000_b9f40430_30a01838_80000000_b9f40e60_30a08000; -defparam bootram.RAM0.INIT_2B=256'h30a00000_b0000018_30a00001_b9f4fd70_80000000_b9f40418_30a018f8_b800fe50; -defparam bootram.RAM0.INIT_2C=256'h30600080_f8003104_f8603100_30600012_f8003108_b800ff48_80000000_b9f40f70; -defparam bootram.RAM0.INIT_2D=256'hbe23fff8_a4630040_e8603110_a4a500ff_be070088_80000000_b60f0008_f8603108; -defparam bootram.RAM0.INIT_2E=256'hbc23fff8_a4630002_e8603110_f8803110_30800090_f860310c_a0630001_10652800; -defparam bootram.RAM0.INIT_2F=256'hf8603110_30600020_be120038_aa470001_10800000_be230058_a4630080_e8603110; -defparam bootram.RAM0.INIT_30=256'h30c60001_be07001c_f0660000_30e7ffff_e860310c_bc23fff8_a4630002_e8603110; -defparam bootram.RAM0.INIT_31=256'h10640000_b60f0008_30800001_30600068_b810ffd0_30600020_be32ffd8_aa470001; -defparam bootram.RAM0.INIT_32=256'hbe23fff8_a4630040_e8603110_a4a500ff_10640000_b60f0008_f8603110_30600040; -defparam bootram.RAM0.INIT_33=256'ha4630002_e8603110_f8603110_306000d0_30600090_be27000c_f860310c_10652800; -defparam bootram.RAM0.INIT_34=256'he0660000_30800001_be070068_10800000_be23005c_a4630080_e8603110_bc23fff8; -defparam bootram.RAM0.INIT_35=256'hbc23fff8_a4630002_e8603110_f8803110_bc120030_aa470001_f860310c_30800010; -defparam bootram.RAM0.INIT_36=256'hb810ffd4_b800ffc4_30c60001_be070028_30e7ffff_be23001c_a4630080_e8603110; -defparam bootram.RAM0.INIT_37=256'hb60f0008_30800001_10640000_b60f0008_f8603110_30600040_10800000_30800050; -defparam bootram.RAM0.INIT_38=256'h3021ffd0_80000000_b60f0008_80000000_b9f4f964_f9e10000_3021ffe4_10640000; -defparam bootram.RAM0.INIT_39=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; -defparam bootram.RAM0.INIT_3A=256'hbcb2002c_16572001_bc120030_aa43ffff_12c00000_b810001c_f9e10000_fac10020; -defparam bootram.RAM0.INIT_3B=256'hbe32ffd4_aa43000a_f0730000_10960000_90630060_10b80000_b9f405ec_32730001; -defparam bootram.RAM0.INIT_3C=256'heae10024_eac10020_ea61001c_e9e10000_10640000_f0130000_14999800_32d60001; -defparam bootram.RAM0.INIT_3D=256'hfb010028_fae10024_fa61001c_3021ffd0_30210030_b60f0008_eb21002c_eb010028; -defparam bootram.RAM0.INIT_3E=256'hb8100014_f9e10000_fac10020_13260000_12e70000_13050000_12660000_fb21002c; -defparam bootram.RAM0.INIT_3F=256'h10960000_90630060_10b80000_b9f4051c_32730001_bcb2002c_16572001_12c00000; -defparam bootram.RAM1.INIT_00=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffdc_aa43000a_f0730000; -defparam bootram.RAM1.INIT_01=256'h3021ffd8_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; -defparam bootram.RAM1.INIT_02=256'hb9f404b0_12660000_f9e10000_12e60000_12c50000_fae10024_fac10020_fa61001c; -defparam bootram.RAM1.INIT_03=256'hf0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000_90630060_10b60000; -defparam bootram.RAM1.INIT_04=256'h10c50000_30210028_b60f0008_eae10024_eac10020_ea61001c_e9e10000_10770000; -defparam bootram.RAM1.INIT_05=256'h3021ffe4_3021001c_b60f0008_e9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4; -defparam bootram.RAM1.INIT_06=256'hf9e10000_3021ffe4_3021001c_b60f0008_e9e10000_80000000_b9f40448_f9e10000; -defparam bootram.RAM1.INIT_07=256'hfac10020_fa61001c_3021ffdc_3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc; -defparam bootram.RAM1.INIT_08=256'hb9f40324_10b60000_12c50000_be060024_90c30060_12660000_e0660000_f9e10000; -defparam bootram.RAM1.INIT_09=256'heac10020_ea61001c_e9e10000_10b60000_be26fff0_90c30060_e0730000_32730001; -defparam bootram.RAM1.INIT_0A=256'h12c50000_b9f4ff9c_f9e10000_fac1001c_3021ffe0_30210024_b60f0008_10600000; -defparam bootram.RAM1.INIT_0B=256'h30210020_b60f0008_10600000_eac1001c_e9e10000_30c0000a_b9f402dc_10b60000; -defparam bootram.RAM1.INIT_0C=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000; -defparam bootram.RAM1.INIT_0D=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000; -defparam bootram.RAM1.INIT_0E=256'h3021ffe0_3021001c_b60f0008_e9e10000_30c0000a_b9f40278_f9e10000_3021ffe4; -defparam bootram.RAM1.INIT_0F=256'he9e10000_10760000_10d60000_b9f40250_f9e10000_10a00000_12c50000_fac1001c; -defparam bootram.RAM1.INIT_10=256'h12c60000_b9f40228_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_eac1001c; -defparam bootram.RAM1.INIT_11=256'hb9f401b8_f9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000; -defparam bootram.RAM1.INIT_12=256'hb0000000_9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000; -defparam bootram.RAM1.INIT_13=256'hf860f81c_b0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c; -defparam bootram.RAM1.INIT_14=256'h94608001_80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002; -defparam bootram.RAM1.INIT_15=256'hf8a0f81c_b0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002; -defparam bootram.RAM1.INIT_16=256'h94e08001_80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002; -defparam bootram.RAM1.INIT_17=256'h80633000_84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002; -defparam bootram.RAM1.INIT_18=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020; -defparam bootram.RAM1.INIT_19=256'hfac10020_f9e10000_fb010028_fae10024_fa61001c_3021ffd4_80000000_b60f0008; -defparam bootram.RAM1.INIT_1A=256'h32600001_be670038_12660000_be060040_90c30060_13050000_12e60000_e0660000; -defparam bootram.RAM1.INIT_1B=256'hc0779800_10b80000_b9f400cc_10730000_be120028_16569800_32c70001_b8100014; -defparam bootram.RAM1.INIT_1C=256'heac10020_ea61001c_e9e10000_10730000_3273ffff_32730001_be26ffe4_90c30060; -defparam bootram.RAM1.INIT_1D=256'hb9f40084_f9e10000_10a00000_3021ffe4_3021002c_b60f0008_eb010028_eae10024; -defparam bootram.RAM1.INIT_1E=256'h10c63000_80000000_b60f0008_f0c51cec_3021001c_b60f0008_e9e10000_30c0000a; -defparam bootram.RAM1.INIT_1F=256'hf9e10000_fa61001c_3021ffe0_80000000_b60f0008_f8653700_64a50405_e4661a28; -defparam bootram.RAM1.INIT_20=256'h32730001_10b30000_e0d31a24_90c60060_b9f4ffc4_10b30000_e0d31cec_12600000; -defparam bootram.RAM1.INIT_21=256'h30210020_b60f0008_ea61001c_e9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc; -defparam bootram.RAM1.INIT_22=256'h12650000_be120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc; -defparam bootram.RAM1.INIT_23=256'heac10020_ea61001c_e9e10000_fac5000c_bc03fffc_e8650004_30a33700_64730405; -defparam bootram.RAM1.INIT_24=256'hb810ffc8_30c0000d_b9f4ffac_bc32ffd0_aa430001_e0651cec_30210024_b60f0008; -defparam bootram.RAM1.INIT_25=256'hbe120030_aa46000a_12c60000_f9e10000_fac10020_fa61001c_3021ffdc_64730405; -defparam bootram.RAM1.INIT_26=256'hea61001c_e9e10000_fac3000c_bc040008_e8830004_30633700_64730405_12650000; -defparam bootram.RAM1.INIT_27=256'hb9f4ff44_30c0000d_be32ffd0_aa430001_e0651cec_30210024_b60f0008_eac10020; -defparam bootram.RAM1.INIT_28=256'he8650010_bc03fffc_e8650008_30a53700_64a50405_64730405_b810ffc4_80000000; -defparam bootram.RAM1.INIT_29=256'he8850008_e8650010_bc030014_e8650008_30a53700_64a50405_80000000_b60f0008; -defparam bootram.RAM1.INIT_2A=256'hf9e10000_fac10020_3021ffdc_64a50405_80000000_b60f0008_90630060_be24fff8; -defparam bootram.RAM1.INIT_2B=256'hbe120034_aa53012d_b8000010_32600001_be230040_e8760008_32c53700_fa61001c; -defparam bootram.RAM1.INIT_2C=256'h3240012b_3273ffff_32730001_be03ffe8_e8760008_30a00001_b9f40040_3060ffff; -defparam bootram.RAM1.INIT_2D=256'hb60f0008_eac10020_ea61001c_e9e10000_e8760010_3060ffff_be52000c_16539001; -defparam bootram.RAM1.INIT_2E=256'hbe650048_bc430054_e8601cf0_bc260054_a4c30000_b0008000_e8603324_30210024; -defparam bootram.RAM1.INIT_2F=256'h80000000_80000000_80000000_80000000_10800000_bc660030_e8c01cf0_10660000; -defparam bootram.RAM1.INIT_30=256'h16432800_30630001_bc32ffdc_16443000_30840001_80000000_80000000_80000000; -defparam bootram.RAM1.INIT_31=256'hf8801cf0_e4831a34_10631800_a4630007_e8603324_80000000_b60f0008_bc32ffc8; -defparam bootram.RAM1.INIT_32=256'h3065ffc9_a46300ff_be520024_16459001_3240005a_3065ffa9_90a50060_b800ff9c; -defparam bootram.RAM1.INIT_33=256'h80000000_b60f0008_a46400ff_3085ffd0_be52000c_16459001_32400039_a46300ff; -defparam bootram.RAM1.INIT_34=256'hfae10024_fac10020_fa61001c_f9e10000_fb610034_13250000_fb21002c_3021ffc8; -defparam bootram.RAM1.INIT_35=256'h10650000_30a0ffff_be120034_aa43003a_13660000_e0790000_fb410030_fb010028; -defparam bootram.RAM1.INIT_36=256'heb610034_eb410030_eb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_37=256'hbe04001c_90840060_30650001_c085c800_30a00001_e8c01cf4_30210038_b60f0008; -defparam bootram.RAM1.INIT_38=256'hb9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4_a4630044_c0662000_a4a300ff; -defparam bootram.RAM1.INIT_39=256'h10791800_fa7b0004_10739800_12761800_66c30404_b9f4ff1c_e0b90002_80000000; -defparam bootram.RAM1.INIT_3A=256'he0b90003_13530000_b9f4fef0_e0b90005_30a0fffd_be38ff74_93040060_e083000b; -defparam bootram.RAM1.INIT_3B=256'hb9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4; -defparam bootram.RAM1.INIT_3C=256'he0b90008_80000000_b9f4feb0_e0b90007_fafb0008_12f7b000_12d61800_12d61800; -defparam bootram.RAM1.INIT_3D=256'hea7b000c_13580000_10f30000_be130060_f07b0000_1063b000_66c30404_b9f4fea4; -defparam bootram.RAM1.INIT_3E=256'hb9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000; -defparam bootram.RAM1.INIT_3F=256'ha70400ff_c073c000_30980001_e8fb0004_ea7b000c_d0789800_1063b800_66e30404; -defparam bootram.RAM2.INIT_00=256'h64760008_12e73800_e09b0000_eadb0008_a74300ff_be52ffb8_1647c003_107a1800; -defparam bootram.RAM2.INIT_01=256'he0b7000a_12d61800_b9f4fe10_107a1800_12c7b000_10632000_e0b70009_12f9b800; -defparam bootram.RAM2.INIT_02=256'hbe32fe60_1643b000_a46300ff_a6d600ff_1063c000_16d60000_67030404_b9f4fe04; -defparam bootram.RAM2.INIT_03=256'h80000000_b60f0008_bc23fff8_a4630100_e8603b10_10a00000_b810fe58_30a0fffb; -defparam bootram.RAM2.INIT_04=256'hbc23fff8_a4630100_e8603b10_a4a500ff_80884800_a1292000_a508007f_a5290600; -defparam bootram.RAM2.INIT_05=256'h10650000_be050018_f8803b10_a0840100_f8603b18_a46600ff_f8803b10_f8e03b00; -defparam bootram.RAM2.INIT_06=256'h10e60000_10c00000_80000000_b60f0008_e8603b00_bc23fff8_a4630100_e8603b10; -defparam bootram.RAM2.INIT_07=256'hb9f4ff84_f8603b14_30600001_31200400_31000008_10a00000_f9e10000_3021ffe4; -defparam bootram.RAM2.INIT_08=256'hfa61002c_12c50000_fac10030_3021ffc4_3021001c_b60f0008_e9e10000_80000000; -defparam bootram.RAM2.INIT_09=256'hf8003b18_30600400_12670000_b9f4ff3c_fae10034_13060000_f9e10000_fb010038; -defparam bootram.RAM2.INIT_0A=256'h30800428_f8603b18_30600001_fac03b00_f8603b04_3060000b_66d60408_f8603b10; -defparam bootram.RAM2.INIT_0B=256'h12e00000_12d30000_be18009c_80000000_b9f4ff00_f8603b10_30600528_f8803b10; -defparam bootram.RAM2.INIT_0C=256'he8803b0c_80000000_b9f4fed8_f8803b10_30800500_f8603b10_30600400_3261001c; -defparam bootram.RAM2.INIT_0D=256'hf8610028_e8603b00_f8810024_e8803b04_f8610020_e8603b08_f881001c_14b7c000; -defparam bootram.RAM2.INIT_0E=256'h30840001_d0762000_c0732000_30a00010_10800000_beb20034_16459003_22400010; -defparam bootram.RAM2.INIT_0F=256'hbc25ffd8_b800ff8c_12d62800_beb20020_1658b803_12f72800_bc32fff0_16442800; -defparam bootram.RAM2.INIT_10=256'heac10030_ea61002c_e9e10000_f8003b18_12d62800_be52ff7c_1658b803_12f72800; -defparam bootram.RAM2.INIT_11=256'h30a00001_3021ffe4_30e00000_b0009f00_3021003c_b60f0008_eb010038_eae10034; -defparam bootram.RAM2.INIT_12=256'ha463ffff_b00000ff_e9e10000_31200400_b9f4fe34_f9e10000_31000020_30c00001; -defparam bootram.RAM2.INIT_13=256'he9e10000_bc030010_f9e10000_3021ffe4_e860f828_b0000000_3021001c_b60f0008; -defparam bootram.RAM2.INIT_14=256'hbe120010_aa440020_a48400ff_64830008_80000000_b9f4ffa8_3021001c_b60f0008; -defparam bootram.RAM2.INIT_15=256'h16439001_32400018_bcb2fff0_16439001_32400015_80000000_b9f40318_a46300ff; -defparam bootram.RAM2.INIT_16=256'hf9e10000_3021ffe4_e860f824_b0000000_b800ffb0_f860f828_b0000000_bc52ffe4; -defparam bootram.RAM2.INIT_17=256'ha48400ff_64830008_80000000_b9f4ff40_3021001c_b60f0008_e9e10000_bc030010; -defparam bootram.RAM2.INIT_18=256'hbcb2fff0_16459001_32400015_80000000_b9f402b0_a4a300ff_be120010_aa440020; -defparam bootram.RAM2.INIT_19=256'hf860f824_b0000000_f8a0f828_b0000000_e0651a2e_bc52ffe4_16459001_32400018; -defparam bootram.RAM2.INIT_1A=256'hbe520040_16459001_3240003e_30a50001_10a00000_b810001c_3021ffbc_b800ffa4; -defparam bootram.RAM2.INIT_1B=256'h30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff_e0630004_10612800_10600000; -defparam bootram.RAM2.INIT_1C=256'hb60f0008_30210044_b60f0008_30600001_be32ffc8_aa440099_e0830004_10612800; -defparam bootram.RAM2.INIT_1D=256'hb9f402bc_f9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_30210044; -defparam bootram.RAM2.INIT_1E=256'h3021ffd4_30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024; -defparam bootram.RAM2.INIT_1F=256'h30c01a48_10b60000_30c00006_b9f4fd20_f9e10000_10f60000_32c1001c_fac10028; -defparam bootram.RAM2.INIT_20=256'h6464001f_eac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8; -defparam bootram.RAM2.INIT_21=256'h65240405_65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008; -defparam bootram.RAM2.INIT_22=256'h10842000_a4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407; -defparam bootram.RAM2.INIT_23=256'h80634800_81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800; -defparam bootram.RAM2.INIT_24=256'h65050405_64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008; -defparam bootram.RAM2.INIT_25=256'h10a52800_a4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407; -defparam bootram.RAM2.INIT_26=256'h81294000_81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000; -defparam bootram.RAM2.INIT_27=256'ha6c5ffff_b00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff; -defparam bootram.RAM2.INIT_28=256'hb9f4ff6c_30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000; -defparam bootram.RAM2.INIT_29=256'hb9f4ff4c_30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99; -defparam bootram.RAM2.INIT_2A=256'hb9f4ff2c_30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008; -defparam bootram.RAM2.INIT_2B=256'hb9f4ff0c_30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b; -defparam bootram.RAM2.INIT_2C=256'hb9f4feec_10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000; -defparam bootram.RAM2.INIT_2D=256'h30a01a50_30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020; -defparam bootram.RAM2.INIT_2E=256'h80000000_b6110000_30a0ffff_b9f4eaa0_80000000_b9f4f3d8_f9e10000_3021ffe4; -defparam bootram.RAM2.INIT_2F=256'h16479003_22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000; -defparam bootram.RAM2.INIT_30=256'hbc320040_16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c; -defparam bootram.RAM2.INIT_31=256'haa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc; -defparam bootram.RAM2.INIT_32=256'h30e7ffff_30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028; -defparam bootram.RAM2.INIT_33=256'h16479003_2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff; -defparam bootram.RAM2.INIT_34=256'h11040000_bc070024_11050000_be030034_a4630003_80662800_10850000_beb20018; -defparam bootram.RAM2.INIT_35=256'hb60f0008_30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000; -defparam bootram.RAM2.INIT_36=256'hf8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000; -defparam bootram.RAM2.INIT_37=256'h22400003_31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c; -defparam bootram.RAM2.INIT_38=256'h16479003_22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003; -defparam bootram.RAM2.INIT_39=256'h3021ffe0_e86017b8_10880000_b810ff68_11044000_10c43000_30840004_be52ffec; -defparam bootram.RAM2.INIT_3A=256'he8730000_3273fffc_99fc1800_bc120018_aa43ffff_326017b8_f9e10000_fa61001c; -defparam bootram.RAM2.INIT_3B=256'hd9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff; -defparam bootram.RAM2.INIT_3C=256'h3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e958; -defparam bootram.RAM2.INIT_3D=256'h00000000_ffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e8d0_d9e00800; -defparam bootram.RAM2.INIT_3E=256'h65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff; -defparam bootram.RAM2.INIT_3F=256'h64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e; -defparam bootram.RAM3.INIT_00=256'h74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00; -defparam bootram.RAM3.INIT_01=256'h523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352; -defparam bootram.RAM3.INIT_02=256'h73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572; -defparam bootram.RAM3.INIT_03=256'h6f207361_523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64; -defparam bootram.RAM3.INIT_04=256'h20492061_626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066; -defparam bootram.RAM3.INIT_05=256'h20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120; -defparam bootram.RAM3.INIT_06=256'h69642070_2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f; -defparam bootram.RAM3.INIT_07=256'h64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475; -defparam bootram.RAM3.INIT_08=256'h7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563; -defparam bootram.RAM3.INIT_09=256'h64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e; -defparam bootram.RAM3.INIT_0A=256'h74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20; -defparam bootram.RAM3.INIT_0B=256'h2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20; -defparam bootram.RAM3.INIT_0C=256'h756e642e_6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69; -defparam bootram.RAM3.INIT_0D=256'h6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61; -defparam bootram.RAM3.INIT_0E=256'h65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20; -defparam bootram.RAM3.INIT_0F=256'h6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065; -defparam bootram.RAM3.INIT_10=256'h77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265; -defparam bootram.RAM3.INIT_11=256'h09c407d0_13880d05_00002710_01b200d9_05160364_14580a2c_05050400_2e2e2e00; -defparam bootram.RAM3.INIT_12=256'h00202020_00000000_6f72740a_0a0a6162_b8080000_b0000000_10101200_06820594; -defparam bootram.RAM3.INIT_13=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; -defparam bootram.RAM3.INIT_14=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; -defparam bootram.RAM3.INIT_15=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; -defparam bootram.RAM3.INIT_16=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; -defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1F=256'h20202020_20202020_20202020_20202020_28282020_20282828_20202020_20202020; -defparam bootram.RAM3.INIT_20=256'h10101010_04041010_04040404_04040404_10101010_10101010_10101010_88101010; -defparam bootram.RAM3.INIT_21=256'h10101010_01010110_01010101_01010101_01010101_01010101_41414101_10414141; -defparam bootram.RAM3.INIT_22=256'h10101020_02020210_02020202_02020202_02020202_02020202_42424202_10424242; -defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_11=256'hb9f4062c_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; +defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01984_10b30000_b9f40da4_10d60000_10b30000; +defparam bootram.RAM0.INIT_13=256'h30a01984_bc120040_aa430001_30a0194c_e061001c_10a30000_be520034_16439003; +defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406c0_b800ffb4_80000000_b9f406cc; +defparam bootram.RAM0.INIT_15=256'h80000000_b9f40694_b800ff88_80000000_b9f406a0_30a0194c_80000000_b9f4155c; +defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f40678_30a01950_80000000_b9f411e8_30a08000_b0000000; +defparam bootram.RAM0.INIT_17=256'hbe030020_30a00050_31000001_30e1001c_30c000f7_f9e10000_a46500ff_3021ffe0; +defparam bootram.RAM0.INIT_18=256'hb810ffe8_30210020_b60f0008_e9e10000_80000000_b9f40330_f081001c_3080005e; +defparam bootram.RAM0.INIT_19=256'h31000001_b9f40280_f9e10000_30e1001c_30c000f7_30a00050_3021ffe0_308000dc; +defparam bootram.RAM0.INIT_1A=256'h3021ffdc_30210020_b60f0008_6463001f_3063ffff_a863005e_e9e10000_e061001c; +defparam bootram.RAM0.INIT_1B=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c_f9e10000; +defparam bootram.RAM0.INIT_1C=256'hb9f40ea8_80000000_b9f4082c_f800200c_80000000_b9f4fe74_f860200c_306000ff; +defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ff6c_80000000_b9f4059c_30a01988_80000000_b9f409ec_80000000; +defparam bootram.RAM0.INIT_1E=256'h30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000_be23017c; +defparam bootram.RAM0.INIT_1F=256'hb0000000_80000000_b9f40558_30a01b04_12c30000_be030068_80000000_b9f41180; +defparam bootram.RAM0.INIT_20=256'hb9f41094_30a08000_b0000000_30c07c00_b9f40e70_30a00000_b0000030_30e08000; +defparam bootram.RAM0.INIT_21=256'he9e10000_30600001_10a00000_b9f41244_80000000_b9f40524_30a01b30_80000000; +defparam bootram.RAM0.INIT_22=256'hb000003f_80000000_b9f404f8_30a01b6c_30210024_b60f0008_eac10020_ea61001c; +defparam bootram.RAM0.INIT_23=256'h80000000_b9f404d4_30a019f8_12630000_be230024_80000000_b9f410fc_30a00000; +defparam bootram.RAM0.INIT_24=256'h30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000_b9f4fd9c; +defparam bootram.RAM0.INIT_25=256'hb9f40490_30a019bc_80000000_b9f41000_30a08000_b0000000_30c07c00_b9f40ddc; +defparam bootram.RAM0.INIT_26=256'h80000000_b9f40474_30a01a50_30600001_b810ff70_10b60000_b9f411b0_80000000; +defparam bootram.RAM0.INIT_27=256'h80000000_b9f40454_30a01ab4_bc230098_80000000_b9f41000_30a00000_b0000018; +defparam bootram.RAM0.INIT_28=256'h80000000_b9f41048_30a00000_b000003f_80000000_b9f40444_30a0199c_b800fed8; +defparam bootram.RAM0.INIT_29=256'hb9f4fda4_b800fe9c_80000000_b9f4fcec_80000000_b9f40424_30a019f8_bc230028; +defparam bootram.RAM0.INIT_2A=256'h30c07c00_b9f40d24_30a00000_b000003f_30e08000_b0000000_b800fe84_10a00000; +defparam bootram.RAM0.INIT_2B=256'hb9f410f8_80000000_b9f403d8_30a019bc_80000000_b9f40f48_30a08000_b0000000; +defparam bootram.RAM0.INIT_2C=256'hb9f4fc60_30a00001_b9f4fd4c_80000000_b9f403c0_30a01a7c_b800fe50_10b30000; +defparam bootram.RAM0.INIT_2D=256'hfa610020_3021ffd4_b800ff40_80000000_b9f410c8_30a00000_b0000018_30a07530; +defparam bootram.RAM0.INIT_2E=256'hfac10024_30e00001_30c1001c_12e70000_f0c1001c_fae10028_10b30000_a66500ff; +defparam bootram.RAM0.INIT_2F=256'h10b30000_10f60000_10d70000_10830000_be030030_12c80000_b9f40898_f9e10000; +defparam bootram.RAM0.INIT_30=256'h10640000_a8830001_6463001f_3063ffff_80000000_b9f407d0_30800001_be76001c; +defparam bootram.RAM0.INIT_31=256'hfac10024_3021ffcc_3021002c_b60f0008_eae10028_eac10024_ea610020_e9e10000; +defparam bootram.RAM0.INIT_32=256'hf9e10000_12c80000_12e70000_13250000_13060000_fb210030_fb01002c_fae10028; +defparam bootram.RAM0.INIT_33=256'h32d6ffff_e0770000_f301001c_30e00002_be76005c_30c1001c_10b90000_fa610020; +defparam bootram.RAM0.INIT_34=256'hbe33ffcc_32f70001_b9f4089c_30a0000a_12630000_33180001_b9f407f8_f061001d; +defparam bootram.RAM0.INIT_35=256'heb210030_eb01002c_eae10028_eac10024_ea610020_e9e10000_10730000_10b90000; +defparam bootram.RAM0.INIT_36=256'h80000000_b9f4f998_f9e10000_3021ffe4_30600001_b810ffe0_30210034_b60f0008; +defparam bootram.RAM0.INIT_37=256'h12660000_fb21002c_fb010028_fae10024_fa61001c_3021ffd0_80000000_b60f0008; +defparam bootram.RAM0.INIT_38=256'haa43ffff_12c00000_b810001c_f9e10000_fac10020_13260000_12e70000_13050000; +defparam bootram.RAM0.INIT_39=256'h10960000_90630060_10b80000_b9f405ec_32730001_bcb2002c_16572001_bc120030; +defparam bootram.RAM0.INIT_3A=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffd4_aa43000a_f0730000; +defparam bootram.RAM0.INIT_3B=256'h3021ffd0_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; +defparam bootram.RAM0.INIT_3C=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; +defparam bootram.RAM0.INIT_3D=256'hb9f4051c_32730001_bcb2002c_16572001_12c00000_b8100014_f9e10000_fac10020; +defparam bootram.RAM0.INIT_3E=256'h14999800_32d60001_be32ffdc_aa43000a_f0730000_10960000_90630060_10b80000; +defparam bootram.RAM0.INIT_3F=256'heb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000_10640000_f0130000; +defparam bootram.RAM1.INIT_00=256'h12e60000_12c50000_fae10024_fac10020_fa61001c_3021ffd8_30210030_b60f0008; +defparam bootram.RAM1.INIT_01=256'hbe32ffec_aa43000a_f0730000_90630060_10b60000_b9f404b0_12660000_f9e10000; +defparam bootram.RAM1.INIT_02=256'heae10024_eac10020_ea61001c_e9e10000_10770000_f0130000_3273ffff_32730001; +defparam bootram.RAM1.INIT_03=256'he9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4_10c50000_30210028_b60f0008; +defparam bootram.RAM1.INIT_04=256'hb60f0008_e9e10000_80000000_b9f40448_f9e10000_3021ffe4_3021001c_b60f0008; +defparam bootram.RAM1.INIT_05=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc_f9e10000_3021ffe4_3021001c; +defparam bootram.RAM1.INIT_06=256'hbe060024_90c30060_12660000_e0660000_f9e10000_fac10020_fa61001c_3021ffdc; +defparam bootram.RAM1.INIT_07=256'h10b60000_be26fff0_90c30060_e0730000_32730001_b9f40324_10b60000_12c50000; +defparam bootram.RAM1.INIT_08=256'hfac1001c_3021ffe0_30210024_b60f0008_10600000_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_09=256'heac1001c_e9e10000_30c0000a_b9f402dc_10b60000_12c50000_b9f4ff9c_f9e10000; +defparam bootram.RAM1.INIT_0A=256'h10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000_30210020_b60f0008_10600000; +defparam bootram.RAM1.INIT_0B=256'h10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000_3021001c_b60f0008_e9e10000; +defparam bootram.RAM1.INIT_0C=256'he9e10000_30c0000a_b9f40278_f9e10000_3021ffe4_3021001c_b60f0008_e9e10000; +defparam bootram.RAM1.INIT_0D=256'hb9f40250_f9e10000_10a00000_12c50000_fac1001c_3021ffe0_3021001c_b60f0008; +defparam bootram.RAM1.INIT_0E=256'hfac1001c_3021ffe0_30210020_b60f0008_eac1001c_e9e10000_10760000_10d60000; +defparam bootram.RAM1.INIT_0F=256'h30210020_b60f0008_eac1001c_e9e10000_10760000_12c60000_b9f40228_f9e10000; +defparam bootram.RAM1.INIT_10=256'h94e08001_3021001c_b60f0008_e9e10000_80000000_b9f401b8_f9e10000_3021ffe4; +defparam bootram.RAM1.INIT_11=256'h80633000_84632000_84c62800_a866ffff_e880f81c_b0000000_9404c001_ac870002; +defparam bootram.RAM1.INIT_12=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f81c_b0000000_f860200c; +defparam bootram.RAM1.INIT_13=256'h88a52000_e880f81c_b0000000_9406c001_acc30002_94608001_80000000_b60f0008; +defparam bootram.RAM1.INIT_14=256'h9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c_b0000000_f8a0200c; +defparam bootram.RAM1.INIT_15=256'ha866ffff_e880f820_b0000000_9404c001_ac870002_94e08001_80000000_b60f0008; +defparam bootram.RAM1.INIT_16=256'h94808001_a4e70002_f860f820_b0000000_f8602020_80633000_84632000_84c62800; +defparam bootram.RAM1.INIT_17=256'hfae10024_fa61001c_3021ffd4_80000000_b60f0008_9404c001_80843800_ac840002; +defparam bootram.RAM1.INIT_18=256'hbe060040_90c30060_13050000_12e60000_e0660000_fac10020_f9e10000_fb010028; +defparam bootram.RAM1.INIT_19=256'h10730000_be120028_16569800_32c70001_b8100014_32600001_be670038_12660000; +defparam bootram.RAM1.INIT_1A=256'h10730000_3273ffff_32730001_be26ffe4_90c30060_c0779800_10b80000_b9f400cc; +defparam bootram.RAM1.INIT_1B=256'h3021ffe4_3021002c_b60f0008_eb010028_eae10024_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_1C=256'hf0c51e7c_3021001c_b60f0008_e9e10000_30c0000a_b9f40084_f9e10000_10a00000; +defparam bootram.RAM1.INIT_1D=256'h80000000_b60f0008_f8653700_64a50405_e4661bac_10c63000_80000000_b60f0008; +defparam bootram.RAM1.INIT_1E=256'h90c60060_b9f4ffc4_10b30000_e0d31e7c_12600000_f9e10000_fa61001c_3021ffe0; +defparam bootram.RAM1.INIT_1F=256'he9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc_32730001_10b30000_e0d31ba8; +defparam bootram.RAM1.INIT_20=256'h12c60000_f9e10000_fac10020_fa61001c_3021ffdc_30210020_b60f0008_ea61001c; +defparam bootram.RAM1.INIT_21=256'hfac5000c_bc03fffc_e8650004_30a33700_64730405_12650000_be120030_aa46000a; +defparam bootram.RAM1.INIT_22=256'hbc32ffd0_aa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_23=256'hf9e10000_fac10020_fa61001c_3021ffdc_64730405_b810ffc8_30c0000d_b9f4ffac; +defparam bootram.RAM1.INIT_24=256'hbc040008_e8830004_30633700_64730405_12650000_be120030_aa46000a_12c60000; +defparam bootram.RAM1.INIT_25=256'haa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000_fac3000c; +defparam bootram.RAM1.INIT_26=256'h30a53700_64a50405_64730405_b810ffc4_80000000_b9f4ff44_30c0000d_be32ffd0; +defparam bootram.RAM1.INIT_27=256'he8650008_30a53700_64a50405_80000000_b60f0008_e8650010_bc03fffc_e8650008; +defparam bootram.RAM1.INIT_28=256'h64a50405_80000000_b60f0008_90630060_be24fff8_e8850008_e8650010_bc030014; +defparam bootram.RAM1.INIT_29=256'h32600001_be230040_e8760008_32c53700_fa61001c_f9e10000_fac10020_3021ffdc; +defparam bootram.RAM1.INIT_2A=256'hbe03ffe8_e8760008_30a00001_b9f401e0_3060ffff_be120034_aa53012d_b8000010; +defparam bootram.RAM1.INIT_2B=256'he9e10000_e8760010_3060ffff_be52000c_16539001_3240012b_3273ffff_32730001; +defparam bootram.RAM1.INIT_2C=256'h32400004_a463000f_e8603324_f8003108_30210024_b60f0008_eac10020_ea61001c; +defparam bootram.RAM1.INIT_2D=256'ha46300ff_64a30008_e4641bb8_10831800_30600004_10831800_beb20010_16439001; +defparam bootram.RAM1.INIT_2E=256'ha4a500ff_be070088_80000000_b60f0008_f8603108_30600080_f8a03104_f8603100; +defparam bootram.RAM1.INIT_2F=256'hf8803110_30800090_f860310c_a0630001_10652800_be23fff8_a4630040_e8603110; +defparam bootram.RAM1.INIT_30=256'haa470001_10800000_be230058_a4630080_e8603110_bc23fff8_a4630002_e8603110; +defparam bootram.RAM1.INIT_31=256'h30e7ffff_e860310c_bc23fff8_a4630002_e8603110_f8603110_30600020_be120038; +defparam bootram.RAM1.INIT_32=256'h30600068_b810ffd0_30600020_be32ffd8_aa470001_30c60001_be07001c_f0660000; +defparam bootram.RAM1.INIT_33=256'ha4a500ff_10640000_b60f0008_f8603110_30600040_10640000_b60f0008_30800001; +defparam bootram.RAM1.INIT_34=256'h306000d0_30600090_be27000c_f860310c_10652800_be23fff8_a4630040_e8603110; +defparam bootram.RAM1.INIT_35=256'h10800000_be23005c_a4630080_e8603110_bc23fff8_a4630002_e8603110_f8603110; +defparam bootram.RAM1.INIT_36=256'hf8803110_bc120030_aa470001_f860310c_30800010_e0660000_30800001_be070068; +defparam bootram.RAM1.INIT_37=256'hbe070028_30e7ffff_be23001c_a4630080_e8603110_bc23fff8_a4630002_e8603110; +defparam bootram.RAM1.INIT_38=256'hb60f0008_f8603110_30600040_10800000_30800050_b810ffd4_b800ffc4_30c60001; +defparam bootram.RAM1.INIT_39=256'hbc260054_a4c30000_b0008000_e8603324_10640000_b60f0008_30800001_10640000; +defparam bootram.RAM1.INIT_3A=256'h80000000_10800000_bc660030_e8c01e80_10660000_be650048_bc430054_e8601e80; +defparam bootram.RAM1.INIT_3B=256'h16443000_30840001_80000000_80000000_80000000_80000000_80000000_80000000; +defparam bootram.RAM1.INIT_3C=256'ha4630007_e8603324_80000000_b60f0008_bc32ffc8_16432800_30630001_bc32ffdc; +defparam bootram.RAM1.INIT_3D=256'h16459001_3240005a_3065ffa9_90a50060_b800ff9c_f8801e80_e4831bc4_10631800; +defparam bootram.RAM1.INIT_3E=256'h3085ffd0_be52000c_16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024; +defparam bootram.RAM1.INIT_3F=256'hf9e10000_fb610034_13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff; +defparam bootram.RAM2.INIT_00=256'haa43003a_13660000_e0790000_fb410030_fb010028_fae10024_fac10020_fa61001c; +defparam bootram.RAM2.INIT_01=256'heb010028_eae10024_eac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034; +defparam bootram.RAM2.INIT_02=256'hc085c800_30a00001_e8c01e84_30210038_b60f0008_eb610034_eb410030_eb21002c; +defparam bootram.RAM2.INIT_03=256'hb810ffac_bc23ffe4_a4630044_c0662000_a4a300ff_be04001c_90840060_30650001; +defparam bootram.RAM2.INIT_04=256'h12761800_66c30404_b9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe; +defparam bootram.RAM2.INIT_05=256'he0b90005_30a0fffd_be38ff74_93040060_e083000b_10791800_fa7b0004_10739800; +defparam bootram.RAM2.INIT_06=256'h66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0; +defparam bootram.RAM2.INIT_07=256'he0b90007_fafb0008_12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006; +defparam bootram.RAM2.INIT_08=256'hbe130060_f07b0000_1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0; +defparam bootram.RAM2.INIT_09=256'hb9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000; +defparam bootram.RAM2.INIT_0A=256'he8fb0004_ea7b000c_d0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000; +defparam bootram.RAM2.INIT_0B=256'headb0008_a74300ff_be52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001; +defparam bootram.RAM2.INIT_0C=256'h107a1800_12c7b000_10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000; +defparam bootram.RAM2.INIT_0D=256'ha6d600ff_1063c000_16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10; +defparam bootram.RAM2.INIT_0E=256'ha4630100_e8603b10_10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff; +defparam bootram.RAM2.INIT_0F=256'ha4a500ff_80884800_a1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8; +defparam bootram.RAM2.INIT_10=256'ha0840100_f8603b18_a46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10; +defparam bootram.RAM2.INIT_11=256'hb60f0008_e8603b00_bc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10; +defparam bootram.RAM2.INIT_12=256'h31200400_31000008_10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000; +defparam bootram.RAM2.INIT_13=256'h3021ffc4_3021001c_b60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001; +defparam bootram.RAM2.INIT_14=256'hb9f4ff3c_fae10034_13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030; +defparam bootram.RAM2.INIT_15=256'hfac03b00_f8603b04_3060000b_66d60408_f8603b10_f8003b18_30600400_12670000; +defparam bootram.RAM2.INIT_16=256'h80000000_b9f4ff00_f8603b10_30600528_f8803b10_30800428_f8603b18_30600001; +defparam bootram.RAM2.INIT_17=256'hf8803b10_30800500_f8603b10_30600400_3261001c_12e00000_12d30000_be18009c; +defparam bootram.RAM2.INIT_18=256'he8803b04_f8610020_e8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8; +defparam bootram.RAM2.INIT_19=256'h30a00010_10800000_beb20034_16459003_22400010_f8610028_e8603b00_f8810024; +defparam bootram.RAM2.INIT_1A=256'hbeb20020_1658b803_12f72800_bc32fff0_16442800_30840001_d0762000_c0732000; +defparam bootram.RAM2.INIT_1B=256'hf8003b18_12d62800_be52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800; +defparam bootram.RAM2.INIT_1C=256'hb0009f00_3021003c_b60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000; +defparam bootram.RAM2.INIT_1D=256'h31200400_b9f4fe34_f9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000; +defparam bootram.RAM2.INIT_1E=256'h3021ffe4_e860f828_b0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000; +defparam bootram.RAM2.INIT_1F=256'h64830008_80000000_b9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000; +defparam bootram.RAM2.INIT_20=256'h16439001_32400015_80000000_b9f40330_a46300ff_be120010_aa440020_a48400ff; +defparam bootram.RAM2.INIT_21=256'hb0000000_b800ffb0_f860f828_b0000000_bc52ffe4_16439001_32400018_bcb2fff0; +defparam bootram.RAM2.INIT_22=256'hb9f4ff40_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824; +defparam bootram.RAM2.INIT_23=256'h80000000_b9f402c8_a4a300ff_be120010_aa440020_a48400ff_64830008_80000000; +defparam bootram.RAM2.INIT_24=256'hb0000000_e0651bbe_bc52ffe4_16459001_32400018_bcb2fff0_16459001_32400015; +defparam bootram.RAM2.INIT_25=256'h10c50000_12c00000_fac1001c_3021ffe0_b800ffa4_f860f824_b0000000_f8a0f828; +defparam bootram.RAM2.INIT_26=256'heac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40334_f9e10000_10b60000; +defparam bootram.RAM2.INIT_27=256'hb810001c_30e1001c_b9f4fd88_f9e10000_30c00040_3021ffa4_30210020_b60f0008; +defparam bootram.RAM2.INIT_28=256'he063001c_10612800_10600000_be520044_16459001_3240003e_30a50001_10a00000; +defparam bootram.RAM2.INIT_29=256'haa440099_e083001c_10612800_30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff; +defparam bootram.RAM2.INIT_2A=256'h3021005c_b60f0008_e9e10000_3021005c_b60f0008_e9e10000_30600001_be32ffc8; +defparam bootram.RAM2.INIT_2B=256'h10b60000_30c00006_b9f4fd08_f9e10000_10f60000_32c1001c_fac10028_3021ffd4; +defparam bootram.RAM2.INIT_2C=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8_30c01bd8; +defparam bootram.RAM2.INIT_2D=256'h65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008_6464001f; +defparam bootram.RAM2.INIT_2E=256'ha4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407_65240405; +defparam bootram.RAM2.INIT_2F=256'h81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800_10842000; +defparam bootram.RAM2.INIT_30=256'h64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008_80634800; +defparam bootram.RAM2.INIT_31=256'ha4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407_65050405; +defparam bootram.RAM2.INIT_32=256'h81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000_10a52800; +defparam bootram.RAM2.INIT_33=256'hb00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff_81294000; +defparam bootram.RAM2.INIT_34=256'h30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000_a6c5ffff; +defparam bootram.RAM2.INIT_35=256'h30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99_b9f4ff6c; +defparam bootram.RAM2.INIT_36=256'h30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008_b9f4ff4c; +defparam bootram.RAM2.INIT_37=256'h30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b_b9f4ff2c; +defparam bootram.RAM2.INIT_38=256'h10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000_b9f4ff0c; +defparam bootram.RAM2.INIT_39=256'h30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020_b9f4feec; +defparam bootram.RAM2.INIT_3A=256'hb6110000_30a0ffff_b9f4e91c_80000000_b9f4f220_f9e10000_3021ffe4_30a01be0; +defparam bootram.RAM2.INIT_3B=256'h22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000_80000000; +defparam bootram.RAM2.INIT_3C=256'h16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c_16479003; +defparam bootram.RAM2.INIT_3D=256'h30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc_bc320040; +defparam bootram.RAM2.INIT_3E=256'h30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028_aa47ffff; +defparam bootram.RAM2.INIT_3F=256'h2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff_30e7ffff; +defparam bootram.RAM3.INIT_00=256'hbc070024_11050000_be030034_a4630003_80662800_10850000_beb20018_16479003; +defparam bootram.RAM3.INIT_01=256'h30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000_11040000; +defparam bootram.RAM3.INIT_02=256'he8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000_b60f0008; +defparam bootram.RAM3.INIT_03=256'h31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c_f8880008; +defparam bootram.RAM3.INIT_04=256'h22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003_22400003; +defparam bootram.RAM3.INIT_05=256'he860193c_10880000_b810ff68_11044000_10c43000_30840004_be52ffec_16479003; +defparam bootram.RAM3.INIT_06=256'h3273fffc_99fc1800_bc120018_aa43ffff_3260193c_f9e10000_fa61001c_3021ffe0; +defparam bootram.RAM3.INIT_07=256'h3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff_e8730000; +defparam bootram.RAM3.INIT_08=256'h30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e7d4_d9e00800; +defparam bootram.RAM3.INIT_09=256'hffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e74c_d9e00800_3021fff8; +defparam bootram.RAM3.INIT_0A=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff_00000000; +defparam bootram.RAM3.INIT_0B=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265; +defparam bootram.RAM3.INIT_0C=256'h53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00; +defparam bootram.RAM3.INIT_0D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; +defparam bootram.RAM3.INIT_0E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072; +defparam bootram.RAM3.INIT_0F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368; +defparam bootram.RAM3.INIT_10=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361; +defparam bootram.RAM3.INIT_11=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061; +defparam bootram.RAM3.INIT_12=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845; +defparam bootram.RAM3.INIT_13=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070; +defparam bootram.RAM3.INIT_14=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072; +defparam bootram.RAM3.INIT_15=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d; +defparam bootram.RAM3.INIT_16=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374; +defparam bootram.RAM3.INIT_17=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67; +defparam bootram.RAM3.INIT_18=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00; +defparam bootram.RAM3.INIT_19=256'h6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61_756e642e; +defparam bootram.RAM3.INIT_1A=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; +defparam bootram.RAM3.INIT_1B=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068; +defparam bootram.RAM3.INIT_1C=256'h6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d; +defparam bootram.RAM3.INIT_1D=256'h0018000f_ffff0031_01b200d9_05160364_14580a2c_05050400_2e2e2e00_77617265; +defparam bootram.RAM3.INIT_1E=256'hb8080000_b0000000_10101200_06820594_09c407d0_13880d05_00002710_000b0000; +defparam bootram.RAM3.INIT_1F=256'h20202020_28282820_20202828_20202020_00202020_00000000_6f72740a_0a0a6162; +defparam bootram.RAM3.INIT_20=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020; +defparam bootram.RAM3.INIT_21=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404; +defparam bootram.RAM3.INIT_22=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101; +defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202; defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00001be0_ffffffff_01010100_000017c4_00000000_00000000; +defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2B=256'h28282020_20282828_20202020_20202020_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2C=256'h10101010_10101010_10101010_88101010_20202020_20202020_20202020_20202020; +defparam bootram.RAM3.INIT_2D=256'h01010101_01010101_41414101_10414141_10101010_04041010_04040404_04040404; +defparam bootram.RAM3.INIT_2E=256'h02020202_02020202_42424202_10424242_10101010_01010110_01010101_01010101; +defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_10101020_02020210_02020202_02020202; +defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_33=256'h01010100_00001948_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001d70_ffffffff; -- cgit v1.2.3 From 57fcaa242088516813a178713f9316e8ef7657a1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 4 Nov 2010 14:26:16 -0700 Subject: duh --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 619e44b8a..256146a99 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -36,7 +36,7 @@ module u1e_core localparam SR_TX_CTRL = 24; // 2 regs localparam SR_TIME64 = 28; // 4 regs - wire COMPAT_NUM = 8'd2; + wire [7:0] COMPAT_NUM = 8'd2; wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; -- cgit v1.2.3 From 9cd8652b42b5afcba67ef0475e5681b951fe0bdc Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Nov 2010 18:26:02 -0800 Subject: invert led signals because they are active low --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 256146a99..e7e798b34 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -344,7 +344,7 @@ module u1e_core assign rx_enable = xfer_rate[14]; assign rate = xfer_rate[7:0]; - assign { debug_led[3:0] } = {run_rx,run_tx,reg_leds[1:0]}; + assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : -- cgit v1.2.3 From 76d2697276c067285135f444112d987ee53cb843 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 1 Oct 2010 15:18:26 -0700 Subject: fix timing problem on DAC output bus --- usrp2/top/u2_rev3/u2_rev3.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 4daa66212..bab5a7706 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -330,8 +330,8 @@ module u2_rev3 wire [15:0] dac_a_int, dac_b_int; // DAC A and B are swapped in schematic to facilitate clean layout // DAC A is also inverted in schematic to facilitate clean layout - always @(negedge dsp_clk) dac_a <= ~dac_b_int; - always @(negedge dsp_clk) dac_b <= dac_a_int; + always @(posedge dsp_clk) dac_a <= ~dac_b_int; + always @(posedge dsp_clk) dac_b <= dac_a_int; /* OFDDRRSE OFDDRRSE_serdes_inst -- cgit v1.2.3 From 98a4130707cf7cad9597b65504211343138391ad Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Nov 2010 19:08:13 -0800 Subject: remove old commented out code --- usrp2/top/u2_rev3/u2_core_udp.v | 180 ---------------------------------------- usrp2/top/u2plus/u2plus_core.v | 6 +- 2 files changed, 2 insertions(+), 184 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index c9502898b..3b565ba90 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -552,14 +552,6 @@ module u2_core // Master Timer, Slave #9 // No longer used, replaced with simple_timer below - /* - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - */ assign s9_ack = 0; // ///////////////////////////////////////////////////////////////////////// @@ -686,41 +678,6 @@ module u2_core .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - /* - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), - .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; - */ - // ///////////////////////////////////////////////////////////////////////// // VITA Timing @@ -737,140 +694,3 @@ module u2_core assign debug_gpio_1 = 32'd0; endmodule // u2_core - -/* - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = GMII_RX_CLK; // wb_clk; - assign debug_clk[1] = dsp_clk; -*/ -/* - - wire mdio_cpy = MDIO; - assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, - { s6_adr[15:8] }, - { s6_adr[7:0] }, - { 6'd0, mdio_cpy, MDC } }; - - assign debug = { { GMII_TXD }, - { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, - { wr2_flags, rd2_flags }, - { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - assign debug = { { GMII_RXD }, - { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, - { wr2_flags, rd2_flags }, - { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - -// assign debug = debug_udp; - // assign debug = vrc_debug; -/* - assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, - {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, - {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , - {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; -*/ -// assign debug_gpio_1 = {vita_time[63:32] }; -/* - assign debug_gpio_1 = { { tx_f19_data[15:8] }, - { tx_f19_data[7:0] }, - { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, - { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; - */ - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 237276fb6..4378436a6 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -648,10 +648,8 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = {dsp_clk, wb_clk}; -// assign debug = debug_vt; - assign debug = {wb_clk, wb_rst, sd_cyc, sd_stb, sd_we, sd_ack, sd_dat_o[7:0], sd_dat_i[7:0], 10'd0}; - + assign debug_clk = 2'b00; + assign debug = 32'd0; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; -- cgit v1.2.3 From ba36bdd2795b9ae4c11c8f65de92022a1d96bb0f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 10 Nov 2010 11:32:00 -0800 Subject: occ needs to be 2 bits wide on a 36 bit fifo interface. --- usrp2/fifo/fifo19_to_fifo36.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/fifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v index 0e6bcea68..2f530109f 100644 --- a/usrp2/fifo/fifo19_to_fifo36.v +++ b/usrp2/fifo/fifo19_to_fifo36.v @@ -16,7 +16,8 @@ module fifo19_to_fifo36 output [31:0] debug ); - reg f36_sof, f36_eof, f36_occ; + reg f36_sof, f36_eof; + reg [1:0] f36_occ; reg [1:0] state; reg [15:0] dat0, dat1; -- cgit v1.2.3 From a0dfafffbf64ba007fc8695e105c72c93c654319 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 10 Nov 2010 11:50:42 -0800 Subject: need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in u2 and u2p --- usrp2/opencores/Makefile.srcs | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/opencores/Makefile.srcs b/usrp2/opencores/Makefile.srcs index 1ccecf337..284578b39 100644 --- a/usrp2/opencores/Makefile.srcs +++ b/usrp2/opencores/Makefile.srcs @@ -23,5 +23,6 @@ i2c/rtl/verilog/timescale.v \ spi/rtl/verilog/spi_clgen.v \ spi/rtl/verilog/spi_defines.v \ spi/rtl/verilog/spi_shift.v \ +spi/rtl/verilog/spi_top.v \ spi/rtl/verilog/spi_top16.v \ )) -- cgit v1.2.3 From 7e20fa3db8e4990b47b346200f3c38bd8fa76f27 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 10 Nov 2010 16:28:50 -0800 Subject: u2p needs the bigger regs for some reason --- usrp2/opencores/spi/rtl/verilog/spi_defines.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v index 79509888b..86c301886 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -43,8 +43,8 @@ // low frequency of system clock this can be reduced. // Use SPI_DIVIDER_LEN for fine tuning theexact number. // -`define SPI_DIVIDER_LEN_8 -//`define SPI_DIVIDER_LEN_16 +//`define SPI_DIVIDER_LEN_8 +`define SPI_DIVIDER_LEN_16 //`define SPI_DIVIDER_LEN_24 //`define SPI_DIVIDER_LEN_32 @@ -66,9 +66,9 @@ // Use SPI_MAX_CHAR for fine tuning the exact number, when using // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. // -//`define SPI_MAX_CHAR_128 +`define SPI_MAX_CHAR_128 //`define SPI_MAX_CHAR_64 -`define SPI_MAX_CHAR_32 +//`define SPI_MAX_CHAR_32 //`define SPI_MAX_CHAR_24 //`define SPI_MAX_CHAR_16 //`define SPI_MAX_CHAR_8 -- cgit v1.2.3 From f64f1b5c86c605b7c769bbedd565e356d08e925d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 10 Nov 2010 17:24:29 -0800 Subject: reverting part of the reversion of the spi settings. --- usrp2/opencores/spi/rtl/verilog/spi_defines.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v index 86c301886..3e4dd0e3c 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -43,8 +43,8 @@ // low frequency of system clock this can be reduced. // Use SPI_DIVIDER_LEN for fine tuning theexact number. // -//`define SPI_DIVIDER_LEN_8 -`define SPI_DIVIDER_LEN_16 +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 //`define SPI_DIVIDER_LEN_24 //`define SPI_DIVIDER_LEN_32 -- cgit v1.2.3 From f9db9f4eed98a7538d73b5463e762441198526c1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Jul 2010 16:46:01 -0700 Subject: moved forward from the old branch --- usrp2/extramfifo/fifo_extram.v | 188 +++++++++++++ usrp2/extramfifo/fifo_extram36.v | 47 ++++ usrp2/extramfifo/fifo_extram36_tb.build | 1 + usrp2/extramfifo/fifo_extram36_tb.v | 475 ++++++++++++++++++++++++++++++++ usrp2/extramfifo/fifo_extram_tb.build | 1 + usrp2/extramfifo/fifo_extram_tb.v | 134 +++++++++ usrp2/fifo/fifo18_to_fifo36.v | 20 ++ usrp2/fifo/fifo_2clock_cascade.v | 14 +- 8 files changed, 876 insertions(+), 4 deletions(-) create mode 100644 usrp2/extramfifo/fifo_extram.v create mode 100644 usrp2/extramfifo/fifo_extram36.v create mode 100644 usrp2/extramfifo/fifo_extram36_tb.build create mode 100644 usrp2/extramfifo/fifo_extram36_tb.v create mode 100644 usrp2/extramfifo/fifo_extram_tb.build create mode 100644 usrp2/extramfifo/fifo_extram_tb.v create mode 100644 usrp2/fifo/fifo18_to_fifo36.v diff --git a/usrp2/extramfifo/fifo_extram.v b/usrp2/extramfifo/fifo_extram.v new file mode 100644 index 000000000..4e1f40371 --- /dev/null +++ b/usrp2/extramfifo/fifo_extram.v @@ -0,0 +1,188 @@ + +// Everything on sram_clk + +module fifo_extram + (input reset, input clear, + input [17:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input [15:0] occ_in, + output [17:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input [15:0] space_in, + input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we, + output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, + output sram_mode, output sram_zz); + + localparam AWIDTH = 19; // 1 MB in x18 + localparam RAMSIZE = ((1< 1); + else + can_store <= (occ_in > 2); + + reg can_retrieve; + always @* + if(empty | ~dst_rdy_i) + can_retrieve <= 0; + else if(do_retr_del == 0) + can_retrieve <= 1; + else if((do_retr_del == 1) || (do_retr_del == 2)) + can_retrieve <= (space_in > 1); + else + can_retrieve <= (space_in > 2); + + reg [1:0] state; + localparam IDLE_STORE_NEXT = 0; + localparam STORE = 1; + localparam IDLE_RETR_NEXT = 2; + localparam RETRIEVE = 3; + + reg [7:0] countdown; + wire countdown_done = (countdown == 0); + + localparam CYCLE_SIZE = 6; + + assign do_store = can_store & (state == STORE); + assign do_retrieve = can_retrieve & (state == RETRIEVE); + always @(posedge sram_clk) + if(reset) + do_store_del <= 0; + else + do_store_del <= {do_store_del[0],do_store}; + + always @(posedge sram_clk) + if(reset) + do_retr_del <= 0; + else + do_retr_del <= {do_retr_del[0],do_retrieve}; + + always @(posedge sram_clk) + if(reset | clear) + begin + state <= IDLE_STORE_NEXT; + countdown <= 0; + end + else + case(state) + IDLE_STORE_NEXT : + if(can_store) + begin + state <= STORE; + countdown <= CYCLE_SIZE; + end + else if(can_retrieve) + begin + state <= RETRIEVE; + countdown <= CYCLE_SIZE; + end + STORE : + if(~can_store | (can_retrieve & countdown_done)) + state <= IDLE_RETR_NEXT; + else if(~countdown_done) + countdown <= countdown - 1; + IDLE_RETR_NEXT : + if(can_retrieve) + begin + state <= RETRIEVE; + countdown <= CYCLE_SIZE; + end + else if(can_store) + begin + state <= STORE; + countdown <= CYCLE_SIZE; + end + RETRIEVE : + if(~can_retrieve | (can_store & countdown_done)) + state <= IDLE_STORE_NEXT; + else if(~countdown_done) + countdown <= countdown - 1; + endcase // case (state) + + // RAM wires + assign sram_bw = 0; + assign sram_adv = 0; + assign sram_mode = 0; + assign sram_zz = 0; + assign sram_ce = 0; + + assign sram_a = (state==STORE) ? addr_store : addr_retrieve; + assign sram_we = ~do_store; + assign sram_oe = ~do_retr_del[1]; + assign my_oe = do_store_del[1] & sram_oe; + assign sram_d = my_oe ? datain : 18'bz; + + // FIFO wires + assign dataout = sram_d; + assign src_rdy_o = do_retr_del[1]; + assign dst_rdy_o = do_store_del[1]; + +endmodule // fifo_extram + + + //wire have_1 = (fullness == 1); + //wire have_2 = (fullness == 2); + //wire have_atleast_1 = ~empty; + //wire have_atleast_2 = ~(empty | have_1); + //wire have_atleast_3 = ~(empty | have_1 | have_2); + //wire full_minus_1 = (fullness == (RAMSIZE-1)); // 19'h7FE); + //wire full_minus_2 = (fullness == (RAMSIZE-2)); // 19'h7FD); + //wire spacefor_atleast_1 = ~full; + //wire spacefor_atleast_2 = ~(full | full_minus_1); + //wire spacefor_atleast_3 = ~(full | full_minus_1 | full_minus_2); diff --git a/usrp2/extramfifo/fifo_extram36.v b/usrp2/extramfifo/fifo_extram36.v new file mode 100644 index 000000000..29342fdc4 --- /dev/null +++ b/usrp2/extramfifo/fifo_extram36.v @@ -0,0 +1,47 @@ + +// 18 bit interface means we either can't handle errors or can't handle odd lengths +// unless we go to heroic measures + +module fifo_extram36 + (input clk, input reset, input clear, + input [35:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we, + output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, output sram_mode, + output sram_zz); + + wire [17:0] f18_data_1, f18_data_2, f18_data_3, f18_data_4; + wire f18_src_rdy_1, f18_dst_rdy_1, f18_src_rdy_2, f18_dst_rdy_2; + wire f18_src_rdy_3, f18_dst_rdy_3, f18_src_rdy_4, f18_dst_rdy_4; + + fifo36_to_fifo18 f36_to_f18 + (.clk(clk), .reset(reset), .clear(clear), + .f36_datain(datain), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .f18_dataout(f18_data_1), .f18_src_rdy_o(f18_src_rdy_1), .f18_dst_rdy_i(f18_dst_rdy_1) ); + + wire [15:0] f1_occ, f2_space; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_in + (.wclk(clk), .datain(f18_data_1), .src_rdy_i(f18_src_rdy_1), .dst_rdy_o(f18_dst_rdy_1), .space(), + .rclk(sram_clk), .dataout(f18_data_2), .src_rdy_o(f18_src_rdy_2), .dst_rdy_i(f18_dst_rdy_2), .short_occupied(f1_occ), + .arst(reset) ); + + fifo_extram fifo_extram + (.reset(reset), .clear(clear), + .datain(f18_data_2), .src_rdy_i(f18_src_rdy_2), .dst_rdy_o(f18_dst_rdy_2), .space(), .occ_in(f1_occ), + .dataout(f18_data_3), .src_rdy_o(f18_src_rdy_3), .dst_rdy_i(f18_dst_rdy_3), .occupied(), .space_in(f2_space), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_out + (.wclk(sram_clk), .datain(f18_data_3), .src_rdy_i(f18_src_rdy_3), .dst_rdy_o(f18_dst_rdy_3), .short_space(f2_space), + .rclk(clk), .dataout(f18_data_4), .src_rdy_o(f18_src_rdy_4), .dst_rdy_i(f18_dst_rdy_4), .occupied(), + .arst(reset) ); + + fifo18_to_fifo36 f18_to_f36 + (.clk(clk), .reset(reset), .clear(clear), + .f18_datain(f18_data_4), .f18_src_rdy_i(f18_src_rdy_4), .f18_dst_rdy_o(f18_dst_rdy_4), + .f36_dataout(dataout), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i) ); + +endmodule // fifo_extram36 diff --git a/usrp2/extramfifo/fifo_extram36_tb.build b/usrp2/extramfifo/fifo_extram36_tb.build new file mode 100644 index 000000000..699591889 --- /dev/null +++ b/usrp2/extramfifo/fifo_extram36_tb.build @@ -0,0 +1 @@ +iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v diff --git a/usrp2/extramfifo/fifo_extram36_tb.v b/usrp2/extramfifo/fifo_extram36_tb.v new file mode 100644 index 000000000..f28c35e4f --- /dev/null +++ b/usrp2/extramfifo/fifo_extram36_tb.v @@ -0,0 +1,475 @@ +`timescale 1ns/1ns + +module fifo_extram36_tb(); + + reg clk = 0; + reg sram_clk = 0; + reg rst = 1; + reg clear = 0; + + reg Verbose = 0; // + integer ErrorCount = 0; + + initial #1000 rst = 0; +// always #125 clk = ~clk; + task task_CLK; + reg [7:0] ran; + begin + while (1) begin + ran = $random; + if (ran[1]) + #62 clk = ~clk; + else + #63 clk = !clk; + end + end + endtask // task_CLK + initial task_CLK; + +// always #100 sram_clk = ~sram_clk; + task task_SSRAM_clk; + reg [7:0] ran; + begin + while (1) begin + ran = $random; + if (ran[0]) + #49 sram_clk = ~sram_clk; + else + #51 sram_clk = ~sram_clk; + end + end + endtask // task_SSRAM_clk + initial task_SSRAM_clk; + + reg [31:0] f36_data = 32'hX; + reg [1:0] f36_occ = 0; + reg f36_sof = 0, f36_eof = 0; + + wire [35:0] f36_in = {1'b0,f36_occ,f36_eof,f36_sof,f36_data}; + reg src_rdy_f36i = 0; + wire dst_rdy_f36i; + + wire [35:0] f36_out; + wire src_rdy_f36o; + reg dst_rdy_f36o = 0; + + wire [17:0] sram_d; + wire [18:0] sram_a; + wire [1:0] sram_bw; + wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz; + + reg [31:0] ScoreBoard [524288:0]; + reg [18:0] put_index = 0; + reg [18:0] get_index = 0; + +// integer put_index = 0; +// integer get_index = 0; + + wire [15:0] DUT_space, DUT_occupied; + + fifo_extram36 fifo_extram36 + (.clk(clk), .reset(rst), .clear(clear), + .datain(f36_in), .src_rdy_i(src_rdy_f36i), .dst_rdy_o(dst_rdy_f36i), .space(DUT_space), + .dataout(f36_out), .src_rdy_o(src_rdy_f36o), .dst_rdy_i(dst_rdy_f36o), .occupied(DUT_occupied), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + +`define idt 1 +`ifdef idt + wire [15:0] dummy16; + wire [1:0] dummy2; + + idt71v65603s150 + ram_model(.A(sram_a[17:0]), + .adv_ld_(sram_adv), // advance (high) / load (low) + .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low) + .ce1_(0), .ce2(1), .ce2_(0), // chip enables + .cen_(sram_ce), // clock enable (low) + .clk(sram_clk), // clock + .IO({dummy16,sram_d[15:0]}), + .IOP({dummy2,sram_d[17:16]}), // data bus + .lbo_(sram_mode), // linear burst order (low) + .oe_(sram_oe), // output enable (low) + .r_w_(sram_we)); // read (high) / write (low) +`else + cy1356 ram_model(.d(sram_d),.clk(~sram_clk),.a(sram_a), + .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv), + .ce1b(0),.ce2(1),.ce3b(0), + .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) ); +`endif + + task task_SSRAMMonitor; + reg last_mode; + reg last_clock; + reg last_load; + reg [18:0] sram_addr; + + begin + last_mode = 1'bX; + last_clock = 1'bX; + last_load = 1'bX; + + @ (posedge Verbose); + $dumpvars(0,fifo_extram36_tb); + + $display("%t:%m\t*** Task Started",$time); + while (1) @ (posedge sram_clk) begin + if (sram_mode !== last_mode) begin + $display("%t:%m\tSSRAM mode: %b",$time,sram_mode); + last_mode = sram_mode; + end + if (sram_adv !== last_load) begin + $display("%t:%m\tSSRAM adv/load: %b",$time,sram_adv); + last_load = sram_adv; + end + if (sram_ce !== last_clock) begin + $display("%t:%m\tSSRAM clock enable: %b",$time,sram_ce); + last_clock = sram_ce; + end + if (sram_ce == 1'b0) begin + if (sram_adv == 1'b0) begin +// $display("%t:%m\tSSRAM Address Load A=%h",$time,sram_a); + sram_addr = sram_a; + end else begin + sram_addr = sram_addr + 1; + end + if (sram_oe == 1'b0) begin + $display("%t:%m\tSSRAM Read Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d); + end + if (sram_we == 1'b0) begin + $display("%t:%m\tSSRAM Write Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d); + end + if ((sram_we == 1'b0) && (sram_oe == 1'b0)) begin + $display("%t:%m\t*** ERROR: _oe and _we both active",$time); + end + + end // if (sram_ce == 1'b0) + + end // always @ (posedge sram_clk) + end + endtask // task_SSRAMMonitor + + task ReadFromFIFO36; + begin + $display("%t: Read from FIFO36",$time); + #1 dst_rdy_f36o <= 1; + while(1) + begin + while(~src_rdy_f36o) + @(posedge clk); + $display("%t: Read: %h>",$time,f36_out); + @(posedge clk); + end + end + endtask // ReadFromFIFO36 + + initial dst_rdy_f36o = 0; + + task task_ReadFIFO36; + reg [7:0] ran; + begin + $display("%t:%m\t*** Task Started",$time); + while (1) begin + // Read on one of four clocks + #5 dst_rdy_f36o <= 1; + @(posedge clk); + if (src_rdy_f36o) begin + if (f36_out[31:0] != ScoreBoard[get_index]) begin + $display("%t:%m\tFIFO Get Error: R:%h, E:%h (%h)",$time,f36_out[31:0],ScoreBoard[get_index],get_index); + ErrorCount = ErrorCount + 1; + end else begin + if (Verbose) + $display("%t:%m\t(%5h) %o>",$time,get_index,f36_out); + end + get_index = get_index+1; + end else begin + if (ErrorCount >= 192) + $finish; + end // else: !if(src_rdy_f36o) + + #10; + ran = $random; + if (ran[2:0] != 3'b000) begin + dst_rdy_f36o <= 0; + if (ran[2] != 1'b0) begin + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + if (ran[1] != 1'b0) begin + @(posedge clk); + @(posedge clk); + end + if (ran[0] != 1'b0) begin + @(posedge clk); + end + end + end // while (1) + end + + endtask // task_ReadFIFO36 + + + reg [15:0] count; + + task PutPacketInFIFO36; + input [31:0] data_start; + input [31:0] data_len; + + begin + count = 4; + src_rdy_f36i = 1; + f36_data = data_start; + f36_sof = 1; + f36_eof = 0; + f36_occ = 0; + + $display("%t: Put Packet in FIFO36",$time); + while(~dst_rdy_f36i) + #1; //@(posedge clk); + @(posedge clk); + + $display("%t: <%h PPI_FIFO36: Entered First Line",$time,f36_data); + f36_sof <= 0; + while(count+4 < data_len) + begin + f36_data = f36_data + 32'h01010101; + count = count + 4; + while(~dst_rdy_f36i) + #1; //@(posedge clk); + @(posedge clk); + $display("%t: <%h PPI_FIFO36: Entered New Line",$time,f36_data); + end + f36_data <= f36_data + 32'h01010101; + f36_eof <= 1; + if(count + 4 == data_len) + f36_occ <= 0; + else if(count + 3 == data_len) + f36_occ <= 3; + else if(count + 2 == data_len) + f36_occ <= 2; + else + f36_occ <= 1; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + f36_occ <= 0; + f36_eof <= 0; + f36_data <= 0; + src_rdy_f36i <= 0; + $display("%t: <%h PPI_FIFO36: Entered Last Line",$time,f36_data); + end + endtask // PutPacketInFIFO36 + + task task_WriteFIFO36; + integer i; + reg [7:0] ran; + + begin + f36_data = 32'bX; + if (rst != 1'b0) + @ (negedge rst); + $display("%t:%m\t*** Task Started",$time); + #10; + src_rdy_f36i = 1; + f36_data = $random; + for (i=0; i<64; i=i+0 ) begin + @ (posedge clk) ; + if (dst_rdy_f36i) begin + if (Verbose) + $display("%t:%m\t(%5h) %o<",$time,put_index,f36_in); + ScoreBoard[put_index] = f36_in[31:0]; + put_index = put_index + 1; + #5; + f36_data = $random; + i = i + 1; + end + ran = $random; + if (ran[1:0] != 2'b00) begin + @ (negedge clk); + src_rdy_f36i = 0; + #5; + @ (negedge clk) ; + src_rdy_f36i = 1; + end + end + src_rdy_f36i = 0; + f36_data = 32'bX; +//* if (put_index > 19'h3ff00) +//* Verbose = 1'b1; + + end + endtask // task_WriteFIFO36 + + initial $dumpfile("fifo_extram36_tb.vcd"); +// initial $dumpvars(0,fifo_extram36_tb); + initial $timeformat(-9, 0, " ns", 10); + initial task_SSRAMMonitor; + + initial + begin + @(negedge rst); + #40000; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); +// ReadFromFIFO36; + task_ReadFIFO36; + + end + + integer i; + + initial + begin + @(negedge rst); + @(posedge clk); + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + @(posedge clk); + @(posedge clk); +// PutPacketInFIFO36(32'hA0B0C0D0,12); + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); +// PutPacketInFIFO36(32'hE0F0A0B0,36); + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; +// @(posedge clk); +// #30000; +// @(posedge clk); +// @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + for (i=0; i<8192; i = i+1) begin + @(posedge clk); + #10000; + @(posedge clk); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + end + +// $dumpvars(0,fifo_extram36_tb); + @(posedge clk); + task_WriteFIFO36; + @(posedge clk); + + #100000000; + $finish; + + end + */ + + initial + begin + @(negedge rst); + f36_occ <= 0; + repeat (100) + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= 32'h10203040; + f36_sof <= 1; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= f36_data + 32'h01010101; + f36_sof <= 0; + f36_eof <= 0; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 1; + f36_data <= 32'h1F2F3F4F; + f36_sof <= 0; + f36_eof <= 1; + @(posedge clk); + @(posedge clk); + src_rdy_f36i <= 0; + + + + end + +// initial #500000 $finish; +endmodule // fifo_extram_tb diff --git a/usrp2/extramfifo/fifo_extram_tb.build b/usrp2/extramfifo/fifo_extram_tb.build new file mode 100644 index 000000000..e87217e5c --- /dev/null +++ b/usrp2/extramfifo/fifo_extram_tb.build @@ -0,0 +1 @@ +iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v diff --git a/usrp2/extramfifo/fifo_extram_tb.v b/usrp2/extramfifo/fifo_extram_tb.v new file mode 100644 index 000000000..73550d9ca --- /dev/null +++ b/usrp2/extramfifo/fifo_extram_tb.v @@ -0,0 +1,134 @@ +module fifo_extram_tb(); + + reg clk = 0; + reg sram_clk = 0; + reg reset = 1; + reg clear = 0; + + initial #1000 reset = 0; + always #125 clk = ~clk; + always #100 sram_clk = ~sram_clk; + + reg [15:0] f18_data = 0; + reg f18_sof = 0, f18_eof = 0; + + wire [17:0] f18_in = {f18_eof,f18_sof,f18_data}; + reg src_rdy_f18i = 0; + wire dst_rdy_f18i; + + wire [17:0] f18_out; + wire src_rdy_f18o; + reg dst_rdy_f18o = 0; + + wire [17:0] f18_int; + wire src_rdy_f18int, dst_rdy_f18int; + + wire [17:0] sram_d; + wire [18:0] sram_a; + wire [1:0] sram_bw; + wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz; + wire [15:0] f1_occ; + + fifo_short #(.WIDTH(18)) fifo_short + (.clk(sram_clk), .reset(reset), .clear(clear), + .datain(f18_in), .src_rdy_i(src_rdy_f18i), .dst_rdy_o(dst_rdy_f18i), .space(), + .dataout(f18_int), .src_rdy_o(src_rdy_f18int), .dst_rdy_i(dst_rdy_f18int), .occupied(f1_occ[4:0]) ); + + assign f1_occ[15:5] = 0; + + fifo_extram fifo_extram + (.reset(reset), .clear(clear), + .datain(f18_int), .src_rdy_i(src_rdy_f18int), .dst_rdy_o(dst_rdy_f18int), .space(), .occ_in(f1_occ), + .dataout(f18_out), .src_rdy_o(src_rdy_f18o), .dst_rdy_i(dst_rdy_f18o), .occupied(), .space_in(7), + .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), + .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), + .sram_mode(sram_mode), .sram_zz(sram_zz)); + +`define idt 1 +`ifdef idt + wire [15:0] dummy16; + wire [1:0] dummy2; + + idt71v65603s150 + ram_model(.A(sram_a[17:0]), + .adv_ld_(sram_adv), // advance (high) / load (low) + .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low) + .ce1_(0), .ce2(1), .ce2_(0), // chip enables + .cen_(sram_ce), // clock enable (low) + .clk(sram_clk), // clock + .IO({dummy16,sram_d[15:0]}), + .IOP({dummy2,sram_d[17:16]}), // data bus + .lbo_(sram_mode), // linear burst order (low) + .oe_(sram_oe), // output enable (low) + .r_w_(sram_we)); // read (high) / write (low) +`else + cy1356 ram_model(.d(sram_d),.clk(sram_clk),.a(sram_a), + .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv), + .ce1b(0),.ce2(1),.ce3b(0), + .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) ); +`endif // !`ifdef idt + + always @(posedge sram_clk) + if(dst_rdy_f18o & src_rdy_f18o) + $display("Read: %h",f18_out); + + always @(posedge sram_clk) + if(dst_rdy_f18int & src_rdy_f18int) + $display("Write: %h",f18_int); + + initial $dumpfile("fifo_extram_tb.vcd"); + initial $dumpvars(0,fifo_extram_tb); + + task SendPkt; + input [15:0] data_start; + input [31:0] data_len; + begin + @(posedge sram_clk); + f18_data = data_start; + f18_sof = 1; + f18_eof = 0; + src_rdy_f18i = 1; + while(~dst_rdy_f18i) + #1; + @(posedge sram_clk); + repeat(data_len - 2) + begin + f18_data = f18_data + 16'h0101; + f18_sof = 0; + while(~dst_rdy_f18i) + @(posedge sram_clk); + + @(posedge sram_clk); + end + f18_data = f18_data + 16'h0101; + f18_eof = 1; + while(~dst_rdy_f18i) + #1; + @(posedge sram_clk); + src_rdy_f18i = 0; + f18_data = 0; + f18_eof = 0; + end + endtask // SendPkt + + initial + begin + @(negedge reset); + @(posedge sram_clk); + @(posedge sram_clk); + #10000; + @(posedge sram_clk); + SendPkt(16'hA0B0, 100); + #10000; + //SendPkt(16'hC0D0, 220); + end + + initial + begin + #20000; + dst_rdy_f18o = 1; + end + + initial #200000 $finish; +endmodule // fifo_extram_tb + diff --git a/usrp2/fifo/fifo18_to_fifo36.v b/usrp2/fifo/fifo18_to_fifo36.v new file mode 100644 index 000000000..25bb215a1 --- /dev/null +++ b/usrp2/fifo/fifo18_to_fifo36.v @@ -0,0 +1,20 @@ + +// For now just assume FIFO18 is same as FIFO19 without occupancy bit + +module fifo18_to_fifo36 + (input clk, input reset, input clear, + input [17:0] f18_datain, + input f18_src_rdy_i, + output f18_dst_rdy_o, + + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i + ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk), .reset(reset), .clear(clear), + .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o), + .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) ); + +endmodule // fifo18_to_fifo36 diff --git a/usrp2/fifo/fifo_2clock_cascade.v b/usrp2/fifo/fifo_2clock_cascade.v index 5ce726977..4e8c244c2 100644 --- a/usrp2/fifo/fifo_2clock_cascade.v +++ b/usrp2/fifo/fifo_2clock_cascade.v @@ -1,8 +1,10 @@ module fifo_2clock_cascade #(parameter WIDTH=32, SIZE=9) - (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, - input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, + output [15:0] space, output [15:0] short_space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, + output [15:0] occupied, output [15:0] short_occupied, input arst); wire [WIDTH-1:0] data_int1, data_int2; @@ -29,7 +31,11 @@ module fifo_2clock_cascade .space(s2_space), .occupied(s2_occupied)); // Be conservative -- Only advertise space from input side of fifo, occupied from output side - assign space = {11'b0,s1_space} + l_space; - assign occupied = {11'b0,s2_occupied} + l_occupied; + assign space = {11'b0,s1_space} + l_space; + assign occupied = {11'b0,s2_occupied} + l_occupied; + + // For the fifo_extram, we only want to know the immediately adjacent space + assign short_space = {11'b0,s1_space}; + assign short_occupied = {11'b0,s2_occupied}; endmodule // fifo_2clock_cascade -- cgit v1.2.3 From d0742cf2a5285ed08d49e16948d8227414247f6a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Jul 2010 17:01:25 -0700 Subject: get it to build --- usrp2/extramfifo/.gitignore | 3 + usrp2/extramfifo/fifo_extram36_tb.build | 2 +- usrp2/extramfifo/fifo_extram36_tb.v | 6 +- usrp2/extramfifo/fifo_extram_tb.build | 2 +- usrp2/models/idt71v65603s150.v | 301 ++++++++++++++++++++++++++++++++ 5 files changed, 309 insertions(+), 5 deletions(-) create mode 100644 usrp2/extramfifo/.gitignore mode change 100644 => 100755 usrp2/extramfifo/fifo_extram36_tb.build mode change 100644 => 100755 usrp2/extramfifo/fifo_extram_tb.build create mode 100755 usrp2/models/idt71v65603s150.v diff --git a/usrp2/extramfifo/.gitignore b/usrp2/extramfifo/.gitignore new file mode 100644 index 000000000..94bbf6dcc --- /dev/null +++ b/usrp2/extramfifo/.gitignore @@ -0,0 +1,3 @@ +fifo_extram36_tb +fifo_extram_tb +*.vcd diff --git a/usrp2/extramfifo/fifo_extram36_tb.build b/usrp2/extramfifo/fifo_extram36_tb.build old mode 100644 new mode 100755 index 699591889..ac9369758 --- a/usrp2/extramfifo/fifo_extram36_tb.build +++ b/usrp2/extramfifo/fifo_extram36_tb.build @@ -1 +1 @@ -iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v diff --git a/usrp2/extramfifo/fifo_extram36_tb.v b/usrp2/extramfifo/fifo_extram36_tb.v index f28c35e4f..e5f8cef4c 100644 --- a/usrp2/extramfifo/fifo_extram36_tb.v +++ b/usrp2/extramfifo/fifo_extram36_tb.v @@ -296,8 +296,8 @@ module fifo_extram36_tb(); end src_rdy_f36i = 0; f36_data = 32'bX; -//* if (put_index > 19'h3ff00) -//* Verbose = 1'b1; +// if (put_index > 19'h3ff00) +// Verbose = 1'b1; end endtask // task_WriteFIFO36 @@ -385,7 +385,7 @@ module fifo_extram36_tb(); $finish; end - */ + initial begin diff --git a/usrp2/extramfifo/fifo_extram_tb.build b/usrp2/extramfifo/fifo_extram_tb.build old mode 100644 new mode 100755 index e87217e5c..5607c8691 --- a/usrp2/extramfifo/fifo_extram_tb.build +++ b/usrp2/extramfifo/fifo_extram_tb.build @@ -1 +1 @@ -iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v diff --git a/usrp2/models/idt71v65603s150.v b/usrp2/models/idt71v65603s150.v new file mode 100755 index 000000000..457dfa6dd --- /dev/null +++ b/usrp2/models/idt71v65603s150.v @@ -0,0 +1,301 @@ +/******************************************************************************* + * + * File Name : idt71v65603s150.v + * Product : IDT71V65603 + * Function : 256K x 36 pipeline ZBT Static RAM + * Simulation Tool/Version : Verilog-XL 2.5 + * Date : 07/19/00 + * + * Copyright 1999 Integrated Device Technology, Inc. + * + * Revision Notes: 07/19/00 Rev00 + * + ******************************************************************************/ +/******************************************************************************* + * Module Name: idt71v65603s150 + * + * Notes : This model is believed to be functionally + * accurate. Please direct any inquiries to + * IDT SRAM Applications at: sramhelp@idt.com + * + *******************************************************************************/ + + /*************************************************************** + * + * Integrated Device Technology, Inc. ("IDT") hereby grants the + * user of this Verilog/VCS model a non-exclusive, nontransferable + * license to use this Verilog/VCS model under the following terms. + * The user is granted this license only to use the Verilog/VCS + * model and is not granted rights to sell, copy (except as needed + * to run the IBIS model), rent, lease or sub-license the Verilog/VCS + * model in whole or in part, or in modified form to anyone. The User + * may modify the Verilog/VCS model to suit its specific applications, + * but rights to derivative works and such modifications shall belong + * to IDT. + * + * This Verilog/VCS model is provided on an "AS IS" basis and + * IDT makes absolutely no warranty with respect to the information + * contained herein. IDT DISCLAIMS AND CUSTOMER WAIVES ALL + * WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE + * ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE + * USER ACCORDINGLY, IN NO EVENT SHALL IDT BE LIABLE + * FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN CONTRACT OR + * TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, + * CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF + * THE USE OR APPLICATION OF THE VERILOG/VCS model. Further, + * IDT reserves the right to make changes without notice to any + * product herein to improve reliability, function, or design. + * IDT does not convey any license under patent rights or + * any other intellectual property rights, including those of + * third parties. IDT is not obligated to provide maintenance + * or support for the licensed Verilog/VCS model. + * + ***************************************************************/ + + `timescale 1ns/100ps + +module idt71v65603s150 (A, + adv_ld_, // advance (high) / load (low) + bw1_, bw2_, bw3_, bw4_, // byte write enables (low) + ce1_, ce2, ce2_, // chip enables + cen_, // clock enable (low) + clk, // clock + IO, IOP, // data bus + lbo_, // linear burst order (low) + oe_, // output enable (low) + r_w_); // read (high) / write (low) + +initial +begin + $write("\n********************************************************\n"); + $write(" idt71v65603s150, 256K x 36 Pipelined burst ZBT SRAM \n"); + $write(" Rev: 00 July 2000 \n"); + $write(" copyright 1997,1998,1999,2000 by IDT, Inc. \n"); + $write("********************************************************\n\n"); +end + +input [17:0] A; +inout [31:0] IO; +inout [4:1] IOP; +input adv_ld_, bw1_, bw2_, bw3_, bw4_, ce1_, ce2, ce2_, + cen_, clk, lbo_, oe_, r_w_; + + +//internal registers for data, address, etc +reg [8:0] mem1[0:262143]; //memory array +reg [8:0] mem2[0:262143]; //memory array +reg [8:0] mem3[0:262143]; //memory array +reg [8:0] mem4[0:262143]; //memory array + +reg [35:0] dout; +reg [17:0] addr_a, + addr_b; +reg wren_a, wren_b; +reg cs_a, cs_b; +reg bw_a1, bw_b1; +reg bw_a2, bw_b2; +reg bw_a3, bw_b3; +reg bw_a4, bw_b4; +reg [1:0] brst_cnt; + +wire[35:0] data_out; +wire doe; +wire cs = (~ce1_ & ce2 & ~ce2_); +wire baddr0, baddr1; + + +parameter regdelay = 0.2; +parameter outdly = 0.2; + +specify +specparam +//Clock Parameters + tCYC = 6.7, //clock cycle time + tCH = 2.0, //clock high time + tCL = 2.0, //clock low time + +//Output Parameters + tCD = 3.8, //clk to data valid + tCLZ = 1.5, //clk to output Low-Z + tCHZ = 3.0, //clk to data Hi-Z + tOE = 3.8, //OE to output valid + tOLZ = 0.0, //OE to output Hi-Z + tOHZ = 3.8, //OE to output Hi-Z + +//Set up times + tSE = 1.5, //clock enable set-up + tSA = 1.5, //address set-up + tSD = 1.5, //data set-up + tSW = 1.5, //Read/Write set-up + tSADV = 1.5, //Advance/Load set-up + tSC = 1.5, //Chip enable set-up + tSB = 1.5, //Byte write enable set-up + +//Hold times + tHE = 0.5, //clock enable hold + tHA = 0.5, //address hold + tHD = 0.5, //data hold + tHW = 0.5, //Read/Write hold + tHADV = 0.5, //Advance/Load hold + tHC = 0.5, //Chip enable hold + tHB = 0.5; //Byte write enable hold + + + (oe_ *> IO) = (tOE,tOE,tOHZ,tOLZ,tOHZ,tOLZ); //(01,10,0z,z1,1z,z0) + (clk *> IO) = (tCD,tCD,tCHZ,tCLZ,tCHZ,tCLZ); //(01,10,0z,z1,1z,z0) + + (oe_ *> IOP) = (tOE,tOE,tOHZ,tOLZ,tOHZ,tOLZ); //(01,10,0z,z1,1z,z0) + (clk *> IOP) = (tCD,tCD,tCHZ,tCLZ,tCHZ,tCLZ); //(01,10,0z,z1,1z,z0) + +//timing checks + + $period(posedge clk, tCYC ); + $width (posedge clk, tCH ); + $width (negedge clk, tCL ); + + + $setuphold(posedge clk, A, tSA, tHA); + $setuphold(posedge clk, IO, tSD, tHD); + $setuphold(posedge clk, IOP, tSD, tHD); + $setuphold(posedge clk, adv_ld_, tSADV, tHADV); + $setuphold(posedge clk, bw1_, tSB, tHB); + $setuphold(posedge clk, bw2_, tSB, tHB); + $setuphold(posedge clk, bw3_, tSB, tHB); + $setuphold(posedge clk, bw4_, tSB, tHB); + $setuphold(posedge clk, ce1_, tSC, tHC); + $setuphold(posedge clk, ce2, tSC, tHC); + $setuphold(posedge clk, ce2_, tSC, tHC); + $setuphold(posedge clk, cen_, tSE, tHE); + $setuphold(posedge clk, r_w_, tSW, tHW); + +endspecify + +initial begin + cs_a = 0; + cs_b = 0; +end + + +///////////////////////////////////////////////////////////////////////// +//input registers +//-------------------- +always @(posedge clk) +begin + if ( ~cen_ & ~adv_ld_ ) cs_a <= #regdelay cs; + if ( ~cen_ ) cs_b <= #regdelay cs_a; + + if ( ~cen_ & ~adv_ld_ ) wren_a <= #regdelay (cs & ~r_w_); + if ( ~cen_ ) wren_b <= #regdelay wren_a; + + if ( ~cen_ ) bw_a1 <= #regdelay ~bw1_; + if ( ~cen_ ) bw_a2 <= #regdelay ~bw2_; + if ( ~cen_ ) bw_a3 <= #regdelay ~bw3_; + if ( ~cen_ ) bw_a4 <= #regdelay ~bw4_; + + if ( ~cen_ ) bw_b1 <= #regdelay bw_a1; + if ( ~cen_ ) bw_b2 <= #regdelay bw_a2; + if ( ~cen_ ) bw_b3 <= #regdelay bw_a3; + if ( ~cen_ ) bw_b4 <= #regdelay bw_a4; + + if ( ~cen_ & ~adv_ld_ ) addr_a[17:0] <= #regdelay A[17:0]; + if ( ~cen_ ) addr_b[17:0] <= #regdelay {addr_a[17:2], baddr1, baddr0}; +end + + +///////////////////////////////////////////////////////////////////////// +//burst counter +//-------------------- +always @(posedge clk) +begin + if ( lbo_ & ~cen_ & ~adv_ld_) brst_cnt <= #regdelay 0; + else if (~lbo_ & ~cen_ & ~adv_ld_) brst_cnt <= #regdelay A[1:0]; + else if ( ~cen_ & adv_ld_) brst_cnt <= #regdelay brst_cnt + 1; +end + + +///////////////////////////////////////////////////////////////////////// +//address logic +//-------------------- +assign baddr1 = lbo_ ? (brst_cnt[1] ^ addr_a[1]) : brst_cnt[1]; +assign baddr0 = lbo_ ? (brst_cnt[0] ^ addr_a[0]) : brst_cnt[0]; + + +///////////////////////////////////////////////////////////////////////// +//data output register +//-------------------- +always @(posedge clk) +begin + #regdelay; + #regdelay; + dout[8:0] = mem1[addr_b]; + dout[17:9] = mem2[addr_b]; + dout[26:18] = mem3[addr_b]; + dout[35:27] = mem4[addr_b]; +end + +assign data_out = dout; + + +///////////////////////////////////////////////////////////////////////// +//Output buffers: using a bufif1 has the same effect as... +// +// assign D = doe ? data_out : 36'hz; +// +//It was coded this way to support SPECIFY delays in the specparam section. +//-------------------- +bufif1 #outdly (IO[0],data_out[0],doe); +bufif1 #outdly (IO[1],data_out[1],doe); +bufif1 #outdly (IO[2],data_out[2],doe); +bufif1 #outdly (IO[3],data_out[3],doe); +bufif1 #outdly (IO[4],data_out[4],doe); +bufif1 #outdly (IO[5],data_out[5],doe); +bufif1 #outdly (IO[6],data_out[6],doe); +bufif1 #outdly (IO[7],data_out[7],doe); +bufif1 #outdly (IOP[1],data_out[8],doe); + +bufif1 #outdly (IO[8],data_out[9],doe); +bufif1 #outdly (IO[9],data_out[10],doe); +bufif1 #outdly (IO[10],data_out[11],doe); +bufif1 #outdly (IO[11],data_out[12],doe); +bufif1 #outdly (IO[12],data_out[13],doe); +bufif1 #outdly (IO[13],data_out[14],doe); +bufif1 #outdly (IO[14],data_out[15],doe); +bufif1 #outdly (IO[15],data_out[16],doe); +bufif1 #outdly (IOP[2],data_out[17],doe); + +bufif1 #outdly (IO[16],data_out[18],doe); +bufif1 #outdly (IO[17],data_out[19],doe); +bufif1 #outdly (IO[18],data_out[20],doe); +bufif1 #outdly (IO[19],data_out[21],doe); +bufif1 #outdly (IO[20],data_out[22],doe); +bufif1 #outdly (IO[21],data_out[23],doe); +bufif1 #outdly (IO[22],data_out[24],doe); +bufif1 #outdly (IO[23],data_out[25],doe); +bufif1 #outdly (IOP[3],data_out[26],doe); + +bufif1 #outdly (IO[24],data_out[27],doe); +bufif1 #outdly (IO[25],data_out[28],doe); +bufif1 #outdly (IO[26],data_out[29],doe); +bufif1 #outdly (IO[27],data_out[30],doe); +bufif1 #outdly (IO[28],data_out[31],doe); +bufif1 #outdly (IO[29],data_out[32],doe); +bufif1 #outdly (IO[30],data_out[33],doe); +bufif1 #outdly (IO[31],data_out[34],doe); +bufif1 #outdly (IOP[4],data_out[35],doe); + +assign doe = cs_b & ~wren_b & ~oe_ ; + + +///////////////////////////////////////////////////////////////////////// +// write to ram +//------------- +always @(posedge clk) +begin + if (wren_b & bw_b1 & ~cen_) mem1[addr_b] = {IOP[1], IO[7:0]}; + if (wren_b & bw_b2 & ~cen_) mem2[addr_b] = {IOP[2], IO[15:8]}; + if (wren_b & bw_b3 & ~cen_) mem3[addr_b] = {IOP[3], IO[23:16]}; + if (wren_b & bw_b4 & ~cen_) mem4[addr_b] = {IOP[4], IO[31:24]}; +end + +endmodule -- cgit v1.2.3 From fb73ea172526319803756b985dd3c104881304b1 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 29 Jul 2010 21:25:26 -0700 Subject: Checkpoint checkin. Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet. --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 165 ++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 82 +++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v | 165 ++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco | 82 +++++++ usrp2/extramfifo/Makefile.srcs | 16 ++ usrp2/extramfifo/ext_fifo.v | 120 +++++++++++ usrp2/extramfifo/ext_fifo_tb.cmd | 11 + usrp2/extramfifo/ext_fifo_tb.prj | 9 + usrp2/extramfifo/ext_fifo_tb.sh | 1 + usrp2/extramfifo/ext_fifo_tb.v | 285 +++++++++++++++++++++++++ usrp2/extramfifo/nobl_fifo.v | 264 +++++++++++++++++++++++ usrp2/extramfifo/nobl_if.v | 136 ++++++++++++ usrp2/extramfifo/test_sram_if.v | 171 +++++++++++++++ 13 files changed, 1507 insertions(+) create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco create mode 100644 usrp2/extramfifo/Makefile.srcs create mode 100644 usrp2/extramfifo/ext_fifo.v create mode 100644 usrp2/extramfifo/ext_fifo_tb.cmd create mode 100644 usrp2/extramfifo/ext_fifo_tb.prj create mode 100644 usrp2/extramfifo/ext_fifo_tb.sh create mode 100644 usrp2/extramfifo/ext_fifo_tb.v create mode 100644 usrp2/extramfifo/nobl_fifo.v create mode 100644 usrp2/extramfifo/nobl_if.v create mode 100644 usrp2/extramfifo/test_sram_if.v diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v new file mode 100644 index 000000000..1d7a5ca2a --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v @@ -0,0 +1,165 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating +// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_18to36( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full); + + +input [17 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; + +// synthesis translate_off + + FIFO_GENERATOR_V4_4 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(10), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(18), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(0), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("1kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(1022), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(1024), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(10), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .RD_DATA_COUNT(), + .UNDERFLOW(), + .WR_ACK(), + .WR_DATA_COUNT(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco new file mode 100644 index 000000000..df97fd0e0 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Jul 29 23:02:41 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk_18to36 +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=1023 +CSET full_threshold_negate_value=1022 +CSET input_data_width=18 +CSET input_depth=1024 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=10 +# END Parameters +GENERATE +# CRC: 117ae77f + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v new file mode 100644 index 000000000..f7f6e7e9f --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v @@ -0,0 +1,165 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating +// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_36to18( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [17 : 0] dout; +output empty; +output full; + +// synthesis translate_off + + FIFO_GENERATOR_V4_4 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(18), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(0), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(509), + .C_PROG_FULL_THRESH_NEGATE_VAL(508), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(1024), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(10), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .RD_DATA_COUNT(), + .UNDERFLOW(), + .WR_ACK(), + .WR_DATA_COUNT(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco new file mode 100644 index 000000000..a1c75dc39 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Jul 29 18:10:59 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk_36to18 +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=509 +CSET full_threshold_negate_value=508 +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=18 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: 392ad537 + diff --git a/usrp2/extramfifo/Makefile.srcs b/usrp2/extramfifo/Makefile.srcs new file mode 100644 index 000000000..7cd49f4f6 --- /dev/null +++ b/usrp2/extramfifo/Makefile.srcs @@ -0,0 +1,16 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Extram Sources +################################################## +EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extramfifo/, \ +ext_fifo.v \ +nobl_if.v \ +nobl_fifo.v \ +icon.v \ +icon.xco \ +ila.v \ +ila.xco \ +)) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v new file mode 100644 index 000000000..55935146a --- /dev/null +++ b/usrp2/extramfifo/ext_fifo.v @@ -0,0 +1,120 @@ +module ext_fifo + #(parameter INT_WIDTH=36,EXT_WIDTH=18,DEPTH=19) + ( + input int_clk, + input ext_clk, + input rst, + input [EXT_WIDTH-1:0] RAM_D_pi, + output [EXT_WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + input [INT_WIDTH-1:0] datain, + input src_rdy_i, // WRITE + output dst_rdy_o, // not FULL + output [INT_WIDTH-1:0] dataout, + output src_rdy_o, // not EMPTY + input dst_rdy_i // READ + ); + + wire [EXT_WIDTH-1:0] write_data; + wire [EXT_WIDTH-1:0] read_data; + wire full1, empty1; + wire full2, empty2; + + + // FIFO buffers data from UDP engine into external FIFO clock domain. + fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( + .rst(rst), + .wr_clk(int_clk), + .rd_clk(ext_clk), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(space_avail&~empty1), + // .rd_en(~full2&~empty1), + .dout(write_data), // Bus [17 : 0] + .full(full1), + .empty(empty1)); + assign dst_rdy_o = ~full1; + + + + // External FIFO running at ext clock rate and 18 bit width. + nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH)) + nobl_fifo_i1 + ( + .clk(ext_clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .write_data(write_data), + .write_strobe(space_avail & ~empty1 ), + .space_avail(space_avail), + .read_data(read_data), + .read_strobe(data_avail & ~full2), + .data_avail(data_avail) + ); + + + + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. + fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [17 : 0] + // .din(write_data), // Bus [17 : 0] + .wr_en(data_avail & ~full2 ), + // .wr_en(~full2&~empty1), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .empty(empty2)); + assign src_rdy_o = ~empty2; + + + + wire [35:0] CONTROL0; + reg [7:0] datain_reg,write_data_reg,read_data_reg ; + reg space_avail_reg,data_avail_reg,empty1_reg,full2_reg ; + + always @(posedge ext_clk) + begin + //datain_reg <= datain[7:0]; + write_data_reg <= write_data[7:0]; + read_data_reg <= read_data[7:0]; + space_avail_reg <= space_avail; + data_avail_reg <= data_avail; + empty1_reg <= empty1; + full2_reg <= full2; + end + + + icon icon_i1 + ( + .CONTROL0(CONTROL0) + ); + + ila ila_i1 + ( + .CLK(ext_clk), + .CONTROL(CONTROL0), + // .TRIG0(address_reg), + .TRIG0(write_data_reg[7:0]), + .TRIG1(read_data_reg[7:0]), + .TRIG2(0), + .TRIG3({space_avail_reg,data_avail_reg,empty1_reg,full2_reg}) + ); + +endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.cmd b/usrp2/extramfifo/ext_fifo_tb.cmd new file mode 100644 index 000000000..b0ab830dc --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.cmd @@ -0,0 +1,11 @@ +/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v +-y . +-y ../coregen/ +-y ../models +-y /home/ianb/usrp-fpga/usrp2/sdr_lib +-y /home/ianb/usrp-fpga/usrp2/control_lib +-y /home/ianb/usrp-fpga/usrp2/models +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib + diff --git a/usrp2/extramfifo/ext_fifo_tb.prj b/usrp2/extramfifo/ext_fifo_tb.prj new file mode 100644 index 000000000..a11a15b2f --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.prj @@ -0,0 +1,9 @@ +verilog work "./ext_fifo_tb.v" +verilog work "./ext_fifo.v" +verilog work "./nobl_fifo.v" +verilog work "./nobl_if.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v" +verilog work "../models/CY7C1356C/cy1356.v" +verilog work "../models/idt71v65603s150.v" +verilog work "$XILINX/verilog/src/glbl.v" diff --git a/usrp2/extramfifo/ext_fifo_tb.sh b/usrp2/extramfifo/ext_fifo_tb.sh new file mode 100644 index 000000000..a56574102 --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.sh @@ -0,0 +1 @@ +fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v new file mode 100644 index 000000000..aa1fd6e3c --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -0,0 +1,285 @@ +`timescale 1ns / 1ps +`define INT_WIDTH 36 +`define EXT_WIDTH 18 +`define DEPTH 19 +`define DUMP_VCD_FULL + +module ext_fifo_tb(); + + + reg int_clk; + reg ext_clk; + reg rst; + + + + wire [`EXT_WIDTH-1:0] RAM_D_pi; + wire [`EXT_WIDTH-1:0] RAM_D_po; + wire [`EXT_WIDTH-1:0] RAM_D; + wire RAM_D_poe; + wire [`DEPTH-1:0] RAM_A; + wire RAM_WEn; + wire RAM_CENn; + wire RAM_LDn; + wire RAM_OEn; + wire RAM_CE1n; + reg [`INT_WIDTH-1:0] datain; + reg src_rdy_i; // WRITE + wire dst_rdy_o; // not FULL + wire [`INT_WIDTH-1:0] dataout; + reg [`INT_WIDTH-1:0] ref_dataout; + wire src_rdy_o; // not EMPTY + reg dst_rdy_i; + + + // Clocks + // Int clock is 100MHz + // Ext clock is 125MHz + initial + begin + int_clk <= 0; + ext_clk <= 0; + datain <= 0; + ref_dataout <= 1; + src_rdy_i <= 0; + dst_rdy_i <= 0; + end + + always + #5 int_clk <= ~int_clk; + + always + #4 ext_clk <= ~ext_clk; + + + initial + begin + rst <= 1; + repeat (5) @(negedge int_clk); + rst <= 0; + @(negedge int_clk); + repeat (1000) + begin + @(negedge int_clk); + datain <= datain + 1; + src_rdy_i <= 1; + @(negedge int_clk); + src_rdy_i <= 0; +// @(negedge int_clk); +// dst_rdy_i <= src_rdy_o; +// @(negedge int_clk); +// dst_rdy_i <= 0; + repeat (2) @(negedge int_clk); + end // repeat (1000) + // Fall through fifo, first output already valid + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + repeat (1000) + begin + @(negedge int_clk); + datain <= datain + 1; + src_rdy_i <= 1; + @(negedge int_clk); + src_rdy_i <= 0; + @(negedge int_clk); + ref_dataout <= ref_dataout + 1; + dst_rdy_i <= src_rdy_o; + @(negedge int_clk); + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + dst_rdy_i <= 0; +// repeat (2) @(negedge int_clk); + end // repeat (1000) + repeat (1000) + begin +// @(negedge int_clk); +// datain <= datain + 1; +// src_rdy_i <= 1; +// @(negedge int_clk); +// src_rdy_i <= 0; + @(negedge int_clk); + ref_dataout <= ref_dataout + 1; + dst_rdy_i <= src_rdy_o; + @(negedge int_clk); + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + dst_rdy_i <= 0; +// repeat (2) @(negedge int_clk); + end // repeat (1000) + + $finish; + + end // initial begin + + + /////////////////////////////////////////////////////////////////////////////////// + // Simulation control // + /////////////////////////////////////////////////////////////////////////////////// + `ifdef DUMP_LX2_TOP + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.lx2"); + $dumpvars(1,ext_fifo_tb); + end + `endif + + `ifdef DUMP_LX2_FULL + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.lx2"); + $dumpvars(0,ext_fifo_tb); + end + `endif + + `ifdef DUMP_VCD_TOP + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(1,ext_fifo_tb); + end + `endif + + `ifdef DUMP_VCD_TOP_PLUS_NEXT + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(2,ext_fifo_tb); + end + `endif + + + `ifdef DUMP_VCD_FULL + // Set up output files + initial begin + $dumpfile("ext_fifo_tb.vcd"); + $dumpvars(0,ext_fifo_tb); + end + `endif + + // Update display every 10 us + always #10000 $monitor("Time in uS ",$time/1000); + + wire [`EXT_WIDTH-1:0] RAM_D_pi_ext; + wire [`EXT_WIDTH-1:0] RAM_D_po_ext; + wire [`EXT_WIDTH-1:0] RAM_D_ext; + wire RAM_D_poe_ext; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi_ext[i]), + .I(RAM_D_po_ext[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe_ext) + ); + end // block: gen_RAM_D_IO + + endgenerate + + wire [`DEPTH-1:0] RAM_A_ext; + wire RAM_WEn_ext,RAM_LDn_ext,RAM_CE1n_ext,RAM_OEn_ext,RAM_CENn_ext; + + assign #1 RAM_D_pi = RAM_D_pi_ext; + + assign #1 RAM_D_po_ext = RAM_D_po; + + assign #1 RAM_D_poe_ext = RAM_D_poe; + + assign #2 RAM_WEn_ext = RAM_WEn; + + assign #2 RAM_LDn_ext = RAM_LDn; + + assign #2 RAM_CE1n_ext = RAM_CE1n; + + assign #2 RAM_OEn_ext = RAM_OEn; + + assign #2 RAM_CENn_ext = RAM_CENn; + + assign #2 RAM_A_ext = RAM_A; + +/* -----\/----- EXCLUDED -----\/----- + wire [13:0] temp1; + assign temp1 = 14'h0; + wire [3:0] temp2; + assign temp2 = 4'h0; + -----/\----- EXCLUDED -----/\----- */ + + + idt71v65603s150 idt71v65603s150_i1 + ( + .A(RAM_A_ext[17:0]), + .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) + .bw1_(1'b0), + .bw2_(1'b0), + .bw3_(1'b1), + .bw4_(1'b1), // byte write enables (low) + .ce1_(RAM_CE1n_ext), + .ce2(1'b1), + .ce2_(1'b0), // chip enables + .cen_(RAM_CENn_ext), // clock enable (low) + .clk(ext_clk), // clock + .IO({RAM_D[16:9],RAM_D[7:0]}), + .IOP({RAM_D[17],RAM_D[8]}), // data bus + .lbo_(1'b0), // linear burst order (low) + .oe_(RAM_OEn_ext), // output enable (low) + .r_w_(RAM_WEn_ext) + ); // read (high) / write (low) + +/* -----\/----- EXCLUDED -----\/----- + + + cy1356 cy1356_i1 + ( .d(RAM_D), + .clk(ext_clk), + .a(RAM_A_ext), + .bws(2'b00), + .we_b(RAM_WEn_ext), + .adv_lb(RAM_LDn_ext), + .ce1b(RAM_CE1n_ext), + .ce2(1'b1), + .ce3b(1'b0), + .oeb(RAM_OEn_ext), + .cenb(RAM_CENn_ext), + .mode(1'b0) + ); + -----/\----- EXCLUDED -----/\----- */ + + + ext_fifo + #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.DEPTH(`DEPTH)) + ext_fifo_i1 + ( + .int_clk(int_clk), + .ext_clk(ext_clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain(datain), + .src_rdy_i(src_rdy_i), // WRITE + .dst_rdy_o(dst_rdy_o), // not FULL + .dataout(dataout), + .src_rdy_o(src_rdy_o), // not EMPTY + .dst_rdy_i(dst_rdy_i) + ); + +endmodule // ext_fifo_tb diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v new file mode 100644 index 000000000..1bd7439ad --- /dev/null +++ b/usrp2/extramfifo/nobl_fifo.v @@ -0,0 +1,264 @@ +module nobl_fifo + #(parameter WIDTH=18,DEPTH=19) + ( + input clk, + input rst, + input [WIDTH-1:0] RAM_D_pi, + output [WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + input [WIDTH-1:0] write_data, + input write_strobe, + output reg space_avail, + output reg [WIDTH-1:0] read_data, + input read_strobe, + output reg data_avail + ); + + reg [DEPTH-1:0] capacity; + reg [DEPTH-1:0] wr_pointer; + reg [DEPTH-1:0] rd_pointer; + wire [DEPTH-1:0] address; + + reg supress; + reg data_avail_int; // Data available with high latency from ext FIFO flag + wire [WIDTH-1:0] data_in; + wire data_in_valid; + reg [WIDTH-1:0] read_data_pending; + reg pending_avail; + wire read_strobe_int; + + + + assign read = read_strobe_int && data_avail_int; + assign write = write_strobe && space_avail; + + // When a read and write collision occur, supress availability flags next cycle + // and complete write followed by read over 2 cycles. This forces balanced arbitration + // and makes for a simple logic design. + + always @(posedge clk) + if (rst) + begin + capacity <= 1 << (DEPTH-1); + wr_pointer <= 0; + rd_pointer <= 0; + space_avail <= 0; + data_avail_int <= 0; + supress <= 0; + end + else + begin + space_avail <= ~((capacity == 0) || (read&&write) || (capacity == 1 && write) ); + // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. + data_avail_int <= ~((capacity == (1 << (DEPTH-1))) || (read&&write) || (capacity == ((1 << (DEPTH-1))-1) && read) ); + supress <= read && write; + wr_pointer <= wr_pointer + write; + rd_pointer <= rd_pointer + ((~write && read) || supress); + capacity <= capacity - write + ((~write && read) || supress); // REVISIT + end // else: !if(rst) + + assign address = write ? wr_pointer : rd_pointer; + assign enable = write || read || supress; + + // + // Need to have first item in external FIFO moved into local registers for single cycle latency and throughput on read. + // 2 local registers are provided so that a read every other clock cycle can be sustained. + // No fowarding logic is provided to bypass the external FIFO as latency is of no concern. + // + always @(posedge clk) + if (rst) + begin + read_data <= 0; + data_avail <= 0; + read_data_pending <= 0; + pending_avail <= 0; + end + else + begin + case({read_strobe,data_in_valid}) + // No read externally, no new data arriving from external FIFO + 2'b00: begin + case({data_avail,pending_avail}) + // Start Data empty, Pending empty. + // + // End Data full, Pending empty + 2'b00: begin + read_data <= read_data; + data_avail <= data_avail; + read_data_pending <= read_data_pending ; + pending_avail <= pending_avail; + end + // Start Data empty, Pending full. + // Data <= Pending, + // End Data full, Penidng empty. + 2'b01: begin + read_data <= read_data_pending; + data_avail <= 1'b1; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + // Start Data full, Pending empty. + // + // End Data full, Pending empty + 2'b10: begin + read_data <= read_data; + data_avail <= data_avail; + read_data_pending <= read_data_pending ; + pending_avail <= pending_avail; + end + // Start Data full, Pending full. + // + // End Data full, Pending full. + 2'b11: begin + read_data <= read_data; + data_avail <= data_avail; + read_data_pending <= read_data_pending ; + pending_avail <= pending_avail; + end + endcase + end + // No read externally, new data arriving from external FIFO + 2'b01: begin + case({data_avail,pending_avail}) + // Start Data empty, Pending empty. + // Data <= FIFO + // End Data full, Pending empty + 2'b00: begin + read_data <= data_in; + data_avail <= 1'b1; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + // Start Data empty, Pending full. + // Data <= Pending, Pending <= FIFO + // End Data full, Penidng full. + 2'b01: begin + read_data <= read_data_pending; + data_avail <= 1'b1; + read_data_pending <= data_in ; + pending_avail <= 1'b1; + end + // Start Data full, Pending empty. + // Pending <= FIFO + // End Data full, Pending full + 2'b10: begin + read_data <= read_data; + data_avail <= 1'b1; + read_data_pending <= data_in ; + pending_avail <= 1'b1; + end + // Data full, Pending full. + // *ILLEGAL STATE* + 2'b11: begin + + end + endcase + end + // Read externally, no new data arriving from external FIFO + 2'b10: begin + case({data_avail,pending_avail}) + // Start Data empty, Pending empty. + // *ILLEGAL STATE* + 2'b00: begin + + end + // Start Data empty, Pending full. + // *ILLEGAL STATE* + 2'b01: begin + + end + // Start Data full, Pending empty. + // Out <= Data + // End Data empty, Pending empty. + 2'b10: begin + read_data <= read_data; + data_avail <= 1'b0; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + // Start Data full, Pending full. + // Out <= Data, + // End Data full, Pending empty + 2'b11: begin + read_data <= read_data_pending; + data_avail <= 1'b1; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + endcase + end + // Read externally, new data arriving from external FIFO + 2'b11: begin + case({data_avail,pending_avail}) + // Start Data empty, Pending empty. + // *ILLEGAL STATE* + 2'b00: begin + + end + // Start Data empty, Pending full. + // *ILLEGAL STATE* + 2'b01: begin + + end + // Start Data full, Pending empty. + // Out <= Data, Data <= FIFO + // End Data full, Pending empty. + 2'b10: begin + read_data <= data_in; + data_avail <= 1'b1; + read_data_pending <= read_data_pending ; + pending_avail <= 1'b0; + end + // Start Data full, Pending full. + // Out <= Data, Data <= Pending, Pending <= FIFO + // End Data full, Pending full + 2'b11: begin + read_data <= read_data_pending; + data_avail <= 1'b1; + read_data_pending <= data_in ; + pending_avail <= 1'b1; + end + endcase + end + endcase + end + + // Start an external FIFO read as soon as a read of the buffer reg is strobed to minimise refill latency. + // If the buffer reg or the pending buffer reg is already empty also pre-emptively start a read. + // However there must be something in ext FIFO to read. + // This means that there can be 2 outstanding reads to the ext FIFO active at any time helping to hide latency. + assign read_strobe_int = (read_strobe & data_avail & ~pending_avail) || (~data_avail && ~pending_avail); + + + // + // Simple NoBL SRAM interface, 4 cycle read latency. + // Read/Write arbitration via temprary application of empty/full flags. + // + nobl_if nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(write_data), + .data_in(data_in), + .data_in_valid(data_in_valid), + .write(write), + .enable(enable) + ); + +endmodule // nobl_fifo diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v new file mode 100644 index 000000000..3143ce5ba --- /dev/null +++ b/usrp2/extramfifo/nobl_if.v @@ -0,0 +1,136 @@ +module nobl_if + #(parameter WIDTH=18,DEPTH=19) + ( + input clk, + input rst, + input [WIDTH-1:0] RAM_D_pi, + output [WIDTH-1:0] RAM_D_po, + output reg RAM_D_poe, + output [DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + input [DEPTH-1:0] address, + input [WIDTH-1:0] data_out, + output reg [WIDTH-1:0] data_in, + output reg data_in_valid, + input write, + input enable + ); + + + reg enable_pipe1; + reg [DEPTH-1:0] address_pipe1; + reg write_pipe1; + reg [WIDTH-1:0] data_out_pipe1; + + reg enable_pipe2; + reg write_pipe2; + reg [WIDTH-1:0] data_out_pipe2; + + reg enable_pipe3; + reg write_pipe3; + reg [WIDTH-1:0] data_out_pipe3; + + assign RAM_LDn = 0; + assign RAM_OEn = 0; + + + // + // Pipeline stage 1 + // + always @(posedge clk) + if (rst) + begin + enable_pipe1 <= 0; + address_pipe1 <= 0; + write_pipe1 <= 0; + data_out_pipe1 <= 0; + end + else + begin + enable_pipe1 <= enable; + + if (enable) + begin + address_pipe1 <= address; + write_pipe1 <= write; + + if (write) + data_out_pipe1 <= data_out; + end + end // always @ (posedge clk) + + // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM + assign RAM_A = address_pipe1; + assign RAM_CENn = 1'b0; + assign RAM_WEn = ~write_pipe1; + assign RAM_CE1n = ~enable_pipe1; + + // + // Pipeline stage2 + // + always @(posedge clk) + if (rst) + begin + enable_pipe2 <= 0; + data_out_pipe2 <= 0; + write_pipe2 <= 0; + end + else + begin + data_out_pipe2 <= data_out_pipe1; + write_pipe2 <= write_pipe1; + enable_pipe2 <= enable_pipe1; + end + + // + // Pipeline stage3 + // + always @(posedge clk) + if (rst) + begin + enable_pipe3 <= 0; + data_out_pipe3 <= 0; + write_pipe3 <= 0; + RAM_D_poe <= 0; + end + else + begin + data_out_pipe3 <= data_out_pipe2; + write_pipe3 <= write_pipe2; + enable_pipe3 <= enable_pipe2; + RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx. + end + + // Pipeline 3 drives write data on NoBL SRAM + assign RAM_D_po = data_out_pipe3; + + + // + // Pipeline stage4 + // + always @(posedge clk) + if (rst) + begin + data_in_valid <= 0; + data_in <= 0; + end + else + begin + data_in <= RAM_D_pi; + if (enable_pipe3 & ~write_pipe3) + begin + // Read data now available to be registered. + data_in_valid <= 1'b1; + end + else + data_in_valid <= 1'b0; + end // always @ (posedge clk) + + + + +endmodule // nobl_if diff --git a/usrp2/extramfifo/test_sram_if.v b/usrp2/extramfifo/test_sram_if.v new file mode 100644 index 000000000..9f36b409c --- /dev/null +++ b/usrp2/extramfifo/test_sram_if.v @@ -0,0 +1,171 @@ +`define WIDTH 18 +`define DEPTH 19 + +module test_sram_if + ( + input clk, + input rst, + input [`WIDTH-1:0] RAM_D_pi, + output [`WIDTH-1:0] RAM_D_po, + output RAM_D_poe, + output [`DEPTH-1:0] RAM_A, + output RAM_WEn, + output RAM_CENn, + output RAM_LDn, + output RAM_OEn, + output RAM_CE1n, + output reg correct + ); + + reg [`DEPTH-1:0] write_count; + reg [`DEPTH-1:0] read_count; + reg enable; + reg write; + reg write_cycle; + reg read_cycle; + reg enable_reads; + reg [18:0] address; + reg [17:0] data_out; + wire [17:0] data_in; + wire data_in_valid; + + reg [17:0] check_data; + reg [17:0] check_data_old; + reg [17:0] check_data_old2; + + // + // Create counter that generates both external modulo 2^19 address and modulo 2^18 data to test RAM. + // + + always @(posedge clk) + if (rst) + begin + write_count <= 19'h0; + read_count <= 19'h0; + end + else if (write_cycle) // Write cycle + if (write_count == 19'h7FFFF) + begin + write_count <= 19'h0; + end + else + begin + write_count <= write_count + 1'b1; + end + else if (read_cycle) // Read cycle + if (read_count == 19'h7FFFF) + begin + read_count <= 19'h0; + end + else + begin + read_count <= read_count + 1'b1; + end + + always @(posedge clk) + if (rst) + begin + enable_reads <= 0; + read_cycle <= 0; + write_cycle <= 0; + end + else + begin + write_cycle <= ~write_cycle; + if (enable_reads) + read_cycle <= write_cycle; + if (write_count == 15) // Enable reads 15 writes after reset terminates. + enable_reads <= 1; + end // else: !if(rst) + + always @(posedge clk) + if (rst) + begin + enable <= 0; + end + else if (write_cycle) + begin + address <= write_count; + data_out <= write_count[17:0]; + enable <= 1; + write <= 1; + end + else if (read_cycle) + begin + address <= read_count; + check_data <= read_count[17:0]; + check_data_old <= check_data; + check_data_old2 <= check_data_old; + enable <= 1; + write <= 0; + end + else + enable <= 0; + + always @(posedge clk) + if (data_in_valid) + begin + correct <= (data_in == check_data_old2); + end + + + nobl_if nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(data_out), + .data_in(data_in), + .data_in_valid(data_in_valid), + .write(write), + .enable(enable) + ); + + + wire [35:0] CONTROL0; + reg [7:0] data_in_reg, data_out_reg, address_reg; + reg data_in_valid_reg,write_reg,enable_reg,correct_reg; + + always @(posedge clk) + begin + data_in_reg <= data_in[7:0]; + data_out_reg <= data_out[7:0]; + data_in_valid_reg <= data_in_valid; + write_reg <= write; + enable_reg <= enable; + correct_reg <= correct; + address_reg <= address; + + end + + + icon icon_i1 + ( + .CONTROL0(CONTROL0) + ); + + ila ila_i1 + ( + .CLK(clk), + .CONTROL(CONTROL0), + // .TRIG0(address_reg), + .TRIG0(data_in_reg[7:0]), + .TRIG1(data_out_reg[7:0]), + .TRIG2(address_reg[7:0]), + .TRIG3({data_in_valid_reg,write_reg,enable_reg,correct_reg}) + ); + + + +endmodule // test_sram_if + + \ No newline at end of file -- cgit v1.2.3 From b48b0f171b9e24c161efc6d2b1d2b1a1dbb0324d Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Sat, 31 Jul 2010 00:15:16 -0700 Subject: External FIFO tested in simulation and on USRP2 from decimation 64->8 with current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched. --- usrp2/coregen/Makefile.srcs | 4 + usrp2/coregen/coregen.cgp | 22 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 6 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 6 +- usrp2/extramfifo/ext_fifo.v | 76 +- usrp2/extramfifo/ext_fifo_tb.v | 36 +- usrp2/extramfifo/icon.v | 1286 ++++++ usrp2/extramfifo/icon.xco | 47 + usrp2/extramfifo/ila.v | 5544 ++++++++++++++++++++++++ usrp2/extramfifo/ila.xco | 130 + usrp2/extramfifo/nobl_fifo.v | 20 +- usrp2/extramfifo/nobl_if.v | 9 +- usrp2/extramfifo/test_sram_if.v | 4 + usrp2/top/Makefile.common | 1 + usrp2/top/u2_rev3/Makefile.udp | 2 + usrp2/top/u2_rev3/u2_core_udp.v | 33 +- usrp2/top/u2_rev3/u2_rev3.ucf | 86 +- usrp2/top/u2_rev3/u2_rev3.v | 221 +- 18 files changed, 7297 insertions(+), 236 deletions(-) create mode 100644 usrp2/extramfifo/icon.v create mode 100644 usrp2/extramfifo/icon.xco create mode 100644 usrp2/extramfifo/ila.v create mode 100644 usrp2/extramfifo/ila.xco diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs index 7b29225ca..a59696d15 100644 --- a/usrp2/coregen/Makefile.srcs +++ b/usrp2/coregen/Makefile.srcs @@ -16,4 +16,8 @@ fifo_xlnx_16x19_2clk.v \ fifo_xlnx_16x19_2clk.xco \ fifo_xlnx_16x40_2clk.v \ fifo_xlnx_16x40_2clk.xco \ +fifo_xlnx_512x36_2clk_36to18.v \ +fifo_xlnx_512x36_2clk_36to18.xco \ +fifo_xlnx_512x36_2clk_18to36.v \ +fifo_xlnx_512x36_2clk_18to36.xco \ )) diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp index 810d64dac..4c9201aff 100644 --- a/usrp2/coregen/coregen.cgp +++ b/usrp2/coregen/coregen.cgp @@ -1,20 +1,22 @@ -# Date: Thu Sep 3 17:40:48 2009 -SET addpads = False -SET asysymbol = False +# Date: Mon Jul 26 21:55:33 2010 + +SET addpads = false +SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False +SET createndf = false SET designentry = Verilog SET device = xc3s2000 SET devicefamily = spartan3 SET flowvendor = Other -SET formalverification = False -SET foundationsym = False +SET formalverification = false +SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 -SET removerpms = False +SET removerpms = false SET simulationfiles = Behavioral SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/matt/coregen/tmp +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = /tmp/ +# CRC: 394da717 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v index 1d7a5ca2a..32de19e8a 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v @@ -44,6 +44,7 @@ module fifo_xlnx_512x36_2clk_18to36( rst, wr_clk, wr_en, + almost_full, dout, empty, full); @@ -55,6 +56,7 @@ input rd_en; input rst; input wr_clk; input wr_en; +output almost_full; output [35 : 0] dout; output empty; output full; @@ -73,7 +75,7 @@ output full; .C_FAMILY("spartan3"), .C_FULL_FLAGS_RST_VAL(0), .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), + .C_HAS_ALMOST_FULL(1), .C_HAS_BACKUP(0), .C_HAS_DATA_COUNT(0), .C_HAS_INT_CLK(0), @@ -128,6 +130,7 @@ output full; .RST(rst), .WR_CLK(wr_clk), .WR_EN(wr_en), + .ALMOST_FULL(almost_full), .DOUT(dout), .EMPTY(empty), .FULL(full), @@ -145,7 +148,6 @@ output full; .SRST(), .WR_RST(), .ALMOST_EMPTY(), - .ALMOST_FULL(), .DATA_COUNT(), .OVERFLOW(), .PROG_EMPTY(), diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco index df97fd0e0..05ceffbe9 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version K.39 -# Date: Thu Jul 29 23:02:41 2010 +# Date: Fri Jul 30 20:43:00 2010 # ############################################################## # @@ -36,7 +36,7 @@ SELECT Fifo_Generator family Xilinx,_Inc. 4.4 # END Select # BEGIN Parameters CSET almost_empty_flag=false -CSET almost_full_flag=false +CSET almost_full_flag=true CSET component_name=fifo_xlnx_512x36_2clk_18to36 CSET data_count=false CSET data_count_width=10 @@ -78,5 +78,5 @@ CSET write_data_count=false CSET write_data_count_width=10 # END Parameters GENERATE -# CRC: 117ae77f +# CRC: 9b689ee4 diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 55935146a..a506d71e2 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -1,3 +1,20 @@ +// +// FIFO backed by an off chip ZBT/NoBL SRAM. +// +// This module and its sub-hierarchy implment a FIFO capable of sustaining +// a data throughput rate of at least int_clk/2 * 36bits and bursts of int_clk * 36bits. +// +// This has been designed and tested for an int_clk of 100MHz and an ext_clk of 125MHz, +// your milage may vary with other clock ratio's especially those where int_clk < ext_clk. +// Testing has also exclusively used a rst signal synchronized to int_clk. +// +// Interface operation mimics a Xilinx FIFO configured as "First Word Fall Through", +// though signal naming differs. +// +// For FPGA use registers interfacing directly with signals prefixed "RAM_*" should be +// packed into the IO ring. +// + module ext_fifo #(parameter INT_WIDTH=36,EXT_WIDTH=18,DEPTH=19) ( @@ -24,25 +41,24 @@ module ext_fifo wire [EXT_WIDTH-1:0] write_data; wire [EXT_WIDTH-1:0] read_data; wire full1, empty1; - wire full2, empty2; - + wire almost_full2, full2, empty2; + wire [INT_WIDTH-1:0] data_to_fifo; + wire [INT_WIDTH-1:0] data_from_fifo; + // FIFO buffers data from UDP engine into external FIFO clock domain. fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( .rst(rst), .wr_clk(int_clk), .rd_clk(ext_clk), - .din(datain), // Bus [35 : 0] - .wr_en(src_rdy_i), - .rd_en(space_avail&~empty1), - // .rd_en(~full2&~empty1), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(space_avail&~empty1), .dout(write_data), // Bus [17 : 0] .full(full1), .empty(empty1)); assign dst_rdy_o = ~full1; - - // External FIFO running at ext clock rate and 18 bit width. nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH)) nobl_fifo_i1 @@ -63,10 +79,10 @@ module ext_fifo .space_avail(space_avail), .read_data(read_data), .read_strobe(data_avail & ~full2), - .data_avail(data_avail) + .data_avail(data_avail), + .upstream_full(almost_full2) ); - - + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( @@ -74,47 +90,13 @@ module ext_fifo .wr_clk(ext_clk), .rd_clk(int_clk), .din(read_data), // Bus [17 : 0] - // .din(write_data), // Bus [17 : 0] .wr_en(data_avail & ~full2 ), - // .wr_en(~full2&~empty1), .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] + .dout(dataout), // Bus [35 : 0] .full(full2), + .almost_full(almost_full2), .empty(empty2)); assign src_rdy_o = ~empty2; - - wire [35:0] CONTROL0; - reg [7:0] datain_reg,write_data_reg,read_data_reg ; - reg space_avail_reg,data_avail_reg,empty1_reg,full2_reg ; - - always @(posedge ext_clk) - begin - //datain_reg <= datain[7:0]; - write_data_reg <= write_data[7:0]; - read_data_reg <= read_data[7:0]; - space_avail_reg <= space_avail; - data_avail_reg <= data_avail; - empty1_reg <= empty1; - full2_reg <= full2; - end - - - icon icon_i1 - ( - .CONTROL0(CONTROL0) - ); - - ila ila_i1 - ( - .CLK(ext_clk), - .CONTROL(CONTROL0), - // .TRIG0(address_reg), - .TRIG0(write_data_reg[7:0]), - .TRIG1(read_data_reg[7:0]), - .TRIG2(0), - .TRIG3({space_avail_reg,data_avail_reg,empty1_reg,full2_reg}) - ); - endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index aa1fd6e3c..38df4a285 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -58,18 +58,18 @@ module ext_fifo_tb(); repeat (5) @(negedge int_clk); rst <= 0; @(negedge int_clk); - repeat (1000) + repeat (4000) begin @(negedge int_clk); - datain <= datain + 1; - src_rdy_i <= 1; - @(negedge int_clk); - src_rdy_i <= 0; + datain <= datain + dst_rdy_o; + src_rdy_i <= dst_rdy_o; +// @(negedge int_clk); +// src_rdy_i <= 0; // @(negedge int_clk); // dst_rdy_i <= src_rdy_o; // @(negedge int_clk); // dst_rdy_i <= 0; - repeat (2) @(negedge int_clk); +// repeat (2) @(negedge int_clk); end // repeat (1000) // Fall through fifo, first output already valid if (dataout !== ref_dataout) @@ -77,16 +77,16 @@ module ext_fifo_tb(); repeat (1000) begin @(negedge int_clk); - datain <= datain + 1; - src_rdy_i <= 1; + datain <= datain + dst_rdy_o ; + src_rdy_i <= dst_rdy_o; @(negedge int_clk); src_rdy_i <= 0; @(negedge int_clk); - ref_dataout <= ref_dataout + 1; + ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; - @(negedge int_clk); - if (dataout !== ref_dataout) + if ((dataout !== ref_dataout) && src_rdy_o) $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); dst_rdy_i <= 0; // repeat (2) @(negedge int_clk); end // repeat (1000) @@ -98,11 +98,11 @@ module ext_fifo_tb(); // @(negedge int_clk); // src_rdy_i <= 0; @(negedge int_clk); - ref_dataout <= ref_dataout + 1; + ref_dataout <= ref_dataout + src_rdy_o; dst_rdy_i <= src_rdy_o; - @(negedge int_clk); - if (dataout !== ref_dataout) + if ((dataout !== ref_dataout) && src_rdy_o) $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); dst_rdy_i <= 0; // repeat (2) @(negedge int_clk); end // repeat (1000) @@ -210,13 +210,7 @@ module ext_fifo_tb(); assign #2 RAM_A_ext = RAM_A; -/* -----\/----- EXCLUDED -----\/----- - wire [13:0] temp1; - assign temp1 = 14'h0; - wire [3:0] temp2; - assign temp2 = 4'h0; - -----/\----- EXCLUDED -----/\----- */ - + idt71v65603s150 idt71v65603s150_i1 ( diff --git a/usrp2/extramfifo/icon.v b/usrp2/extramfifo/icon.v new file mode 100644 index 000000000..6537e9340 --- /dev/null +++ b/usrp2/extramfifo/icon.v @@ -0,0 +1,1286 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.53d +// \ \ Application: netgen +// / / Filename: icon.v +// /___/ /\ Timestamp: Tue Jul 20 20:31:15 2010 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v +// Device : xc3s2000-fg456-5 +// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc +// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v +// # of Modules : 1 +// Design Name : icon +// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module icon ( +CONTROL0 +)/* synthesis syn_black_box syn_noprune=1 */; + inout [35 : 0] CONTROL0; + + // synthesis translate_off + + wire N1; + wire \U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ; + wire \U0/U_ICON/U_CMD/iSEL_n ; + wire \U0/U_ICON/U_CMD/iTARGET_CE ; + wire \U0/U_ICON/U_CTRL_OUT/iDATA_VALID ; + wire \U0/U_ICON/U_STAT/iCMD_GRP0_SEL ; + wire \U0/U_ICON/U_STAT/iDATA_VALID ; + wire \U0/U_ICON/U_STAT/iSTATCMD_CE ; + wire \U0/U_ICON/U_STAT/iSTATCMD_CE_n ; + wire \U0/U_ICON/U_STAT/iSTAT_HIGH ; + wire \U0/U_ICON/U_STAT/iSTAT_LOW ; + wire \U0/U_ICON/U_STAT/iTDO_next ; + wire \U0/U_ICON/U_SYNC/iDATA_CMD_n ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ; + wire \U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ; + wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ; + wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ; + wire \U0/U_ICON/iCORE_ID_SEL[0] ; + wire \U0/U_ICON/iCORE_ID_SEL[15] ; + wire \U0/U_ICON/iDATA_CMD ; + wire \U0/U_ICON/iDATA_CMD_n ; + wire \U0/U_ICON/iSEL ; + wire \U0/U_ICON/iSEL_n ; + wire \U0/U_ICON/iSYNC ; + wire \U0/U_ICON/iTDI ; + wire \U0/U_ICON/iTDO ; + wire \U0/U_ICON/iTDO_next ; + wire \U0/iSHIFT_OUT ; + wire \U0/iUPDATE_OUT ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ; + wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ; + wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ; + wire [11 : 8] \U0/U_ICON/U_CMD/iTARGET ; + wire [1 : 0] \U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL ; + wire [5 : 1] \U0/U_ICON/U_STAT/U_STAT_CNT/CI ; + wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/D ; + wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/S ; + wire [3 : 0] \U0/U_ICON/U_STAT/iSTAT ; + wire [5 : 0] \U0/U_ICON/U_STAT/iSTAT_CNT ; + wire [6 : 0] \U0/U_ICON/U_SYNC/iSYNC_WORD ; + wire [1 : 0] \U0/U_ICON/iCOMMAND_GRP ; + wire [15 : 0] \U0/U_ICON/iCOMMAND_SEL ; + wire [3 : 0] \U0/U_ICON/iCORE_ID ; + wire [15 : 15] \U0/U_ICON/iTDO_VEC ; + GND XST_GND ( + .G(CONTROL0[2]) + ); + VCC XST_VCC ( + .P(N1) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_TDI_reg ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/iTDI ), + .Q(CONTROL0[1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_TDO_reg ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/iTDO_next ), + .Q(\U0/U_ICON/iTDO ) + ); + FDC #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_iDATA_CMD ( + .C(\U0/iUPDATE_OUT ), + .CLR(\U0/U_ICON/iSEL_n ), + .D(\U0/U_ICON/iDATA_CMD_n ), + .Q(\U0/U_ICON/iDATA_CMD ) + ); + MUXF5 \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5 ( + .I0(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ), + .I1(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ), + .S(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iTDO_next ) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4 ( + .I0(CONTROL0[3]), + .I1(\U0/U_ICON/iCORE_ID [0]), + .I2(\U0/U_ICON/iCORE_ID [1]), + .I3(\U0/U_ICON/iCORE_ID [2]), + .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3 ( + .I0(\U0/U_ICON/iTDO_VEC [15]), + .I1(\U0/U_ICON/iCORE_ID [0]), + .I2(\U0/U_ICON/iCORE_ID [1]), + .I3(\U0/U_ICON/iCORE_ID [2]), + .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ) + ); + INV \U0/U_ICON/U_iSEL_n ( + .I(\U0/U_ICON/iSEL ), + .O(\U0/U_ICON/iSEL_n ) + ); + INV \U0/U_ICON/U_iDATA_CMD_n ( + .I(\U0/U_ICON/iDATA_CMD ), + .O(\U0/U_ICON/iDATA_CMD_n ) + ); + BSCAN_SPARTAN3 \U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS ( + .TDI(\U0/U_ICON/iTDI ), + .SHIFT(\U0/iSHIFT_OUT ), + .DRCK1(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ), + .DRCK2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ), + .RESET(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ), + .UPDATE(\U0/iUPDATE_OUT ), + .TDO1(\U0/U_ICON/iTDO ), + .TDO2(CONTROL0[2]), + .CAPTURE(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ), + .SEL1(\U0/U_ICON/iSEL ), + .SEL2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ) + ); + icon_bscan_bufg \U0/U_ICON/I_YES_BSCAN.U_BS/I_USE_SOFTBSCAN_EQ0.I_USE_XST_TCK_WORKAROUND_EQ1.U_ICON_BSCAN_BUFG ( + .DRCK_LOCAL_I(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ), + .DRCK_LOCAL_O(CONTROL0[0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC ( + .I0(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ), + .I1(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC ) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC_L ( + .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]), + .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]), + .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]), + .I3(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_SYNC/U_GOT_SYNC_H ( + .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]), + .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]), + .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]), + .I3(CONTROL0[1]), + .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ) + ); + INV \U0/U_ICON/U_SYNC/U_iDATA_CMD_n ( + .I(\U0/U_ICON/iDATA_CMD ), + .O(\U0/U_ICON/U_SYNC/iDATA_CMD_n ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/U_SYNC ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_SYNC/iGOT_SYNC ), + .D(N1), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/iSYNC ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[2].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR ( + .C(CONTROL0[0]), + .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR ( + .C(CONTROL0[0]), + .D(CONTROL0[1]), + .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ), + .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[20]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[4]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [1]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[21]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [1]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[5]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [2]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[22]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [2]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [3]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[23]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [3]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[7]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [4]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[24]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [4]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[8]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [5]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[25]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [5]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[9]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [6]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[26]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [6]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[10]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [7]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[27]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [7]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[11]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [8]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[28]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [8]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[12]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [9]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[29]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [9]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[13]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [10]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[30]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [10]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[14]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [11]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[31]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [11]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[15]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [12]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[32]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [12]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[16]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [13]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[33]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [13]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[17]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [14]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[34]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [14]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[18]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_HCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [15]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]), + .O(CONTROL0[35]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE ( + .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [15]), + .I2(\U0/U_ICON/iCORE_ID_SEL[0] ), + .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]), + .O(CONTROL0[19]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/U_ICON/U_CTRL_OUT/U_CMDGRP1 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]) + ); + LUT2 #( + .INIT ( 4'h1 )) + \U0/U_ICON/U_CTRL_OUT/U_CMDGRP0 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_CTRL_OUT/U_DATA_VALID ( + .I0(\U0/U_ICON/iSYNC ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iCORE_ID_SEL[0] ) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0008 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0010 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0020 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0040 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0080 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0100 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h2000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h4000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[15].U_LUT ( + .I0(\U0/U_ICON/iCORE_ID [0]), + .I1(\U0/U_ICON/iCORE_ID [1]), + .I2(\U0/U_ICON/iCORE_ID [2]), + .I3(\U0/U_ICON/iCORE_ID [3]), + .O(\U0/U_ICON/iCORE_ID_SEL[15] ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[0].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [0]) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[1].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [1]) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[2].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [2]) + ); + LUT4 #( + .INIT ( 16'h0008 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[3].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [3]) + ); + LUT4 #( + .INIT ( 16'h0010 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[4].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [4]) + ); + LUT4 #( + .INIT ( 16'h0020 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[5].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [5]) + ); + LUT4 #( + .INIT ( 16'h0040 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[6].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [6]) + ); + LUT4 #( + .INIT ( 16'h0080 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[7].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [7]) + ); + LUT4 #( + .INIT ( 16'h0100 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[8].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [8]) + ); + LUT4 #( + .INIT ( 16'h0200 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [9]) + ); + LUT4 #( + .INIT ( 16'h0400 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[10].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [10]) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[11].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [11]) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[12].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [12]) + ); + LUT4 #( + .INIT ( 16'h2000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[13].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [13]) + ); + LUT4 #( + .INIT ( 16'h4000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[14].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [14]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[15].U_LUT ( + .I0(\U0/U_ICON/U_CMD/iTARGET [8]), + .I1(\U0/U_ICON/U_CMD/iTARGET [9]), + .I2(\U0/U_ICON/U_CMD/iTARGET [10]), + .I3(\U0/U_ICON/U_CMD/iTARGET [11]), + .O(\U0/U_ICON/iCOMMAND_SEL [15]) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/U_ICON/U_CMD/U_TARGET_CE ( + .I0(\U0/U_ICON/iDATA_CMD ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_CMD/iTARGET_CE ) + ); + INV \U0/U_ICON/U_CMD/U_SEL_n ( + .I(\U0/U_ICON/iSEL ), + .O(\U0/U_ICON/U_CMD/iSEL_n ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCOMMAND_GRP [1]), + .Q(\U0/U_ICON/iCOMMAND_GRP [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [8]), + .Q(\U0/U_ICON/iCOMMAND_GRP [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [9]), + .Q(\U0/U_ICON/U_CMD/iTARGET [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [10]), + .Q(\U0/U_ICON/U_CMD/iTARGET [9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/U_CMD/iTARGET [11]), + .Q(\U0/U_ICON/U_CMD/iTARGET [10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [0]), + .Q(\U0/U_ICON/U_CMD/iTARGET [11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [1]), + .Q(\U0/U_ICON/iCORE_ID [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [2]), + .Q(\U0/U_ICON/iCORE_ID [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(\U0/U_ICON/iCORE_ID [3]), + .Q(\U0/U_ICON/iCORE_ID [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET ( + .C(CONTROL0[0]), + .CE(\U0/U_ICON/U_CMD/iTARGET_CE ), + .CLR(\U0/U_ICON/U_CMD/iSEL_n ), + .D(CONTROL0[1]), + .Q(\U0/U_ICON/iCORE_ID [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]), + .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [5]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_XORCY ( + .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_LUT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]) + ); + MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(CONTROL0[2]), + .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]), + .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]) + ); + XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]), + .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]) + ); + MUXF6 \U0/U_ICON/U_STAT/U_TDO_next ( + .I0(\U0/U_ICON/U_STAT/iSTAT_LOW ), + .I1(\U0/U_ICON/U_STAT/iSTAT_HIGH ), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [5]), + .O(\U0/U_ICON/U_STAT/iTDO_next ) + ); + MUXF5 \U0/U_ICON/U_STAT/U_STAT_LOW ( + .I0(\U0/U_ICON/U_STAT/iSTAT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT [1]), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/iSTAT_LOW ) + ); + MUXF5 \U0/U_ICON/U_STAT/U_STAT_HIGH ( + .I0(\U0/U_ICON/U_STAT/iSTAT [2]), + .I1(\U0/U_ICON/U_STAT/iSTAT [3]), + .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]), + .O(\U0/U_ICON/U_STAT/iSTAT_HIGH ) + ); + LUT4 #( + .INIT ( 16'h0101 )) + \U0/U_ICON/U_STAT/F_STAT[0].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [0]) + ); + LUT4 #( + .INIT ( 16'hC101 )) + \U0/U_ICON/U_STAT/F_STAT[1].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [1]) + ); + LUT4 #( + .INIT ( 16'h2100 )) + \U0/U_ICON/U_STAT/F_STAT[2].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [2]) + ); + LUT4 #( + .INIT ( 16'h1610 )) + \U0/U_ICON/U_STAT/F_STAT[3].U_STAT ( + .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]), + .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]), + .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]), + .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]), + .O(\U0/U_ICON/U_STAT/iSTAT [3]) + ); + INV \U0/U_ICON/U_STAT/U_STATCMD_n ( + .I(\U0/U_ICON/U_STAT/iSTATCMD_CE ), + .O(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_ICON/U_STAT/U_STATCMD ( + .I0(\U0/U_ICON/U_STAT/iDATA_VALID ), + .I1(\U0/U_ICON/iCOMMAND_SEL [0]), + .I2(\U0/U_ICON/iCORE_ID_SEL[15] ), + .I3(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ), + .O(\U0/U_ICON/U_STAT/iSTATCMD_CE ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \U0/U_ICON/U_STAT/U_CMDGRP0 ( + .I0(\U0/U_ICON/iCOMMAND_GRP [0]), + .I1(\U0/U_ICON/iCOMMAND_GRP [1]), + .O(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_ICON/U_STAT/U_DATA_VALID ( + .I0(\U0/U_ICON/iSYNC ), + .I1(\U0/iSHIFT_OUT ), + .O(\U0/U_ICON/U_STAT/iDATA_VALID ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/U_ICON/U_STAT/U_TDO ( + .C(CONTROL0[0]), + .CE(N1), + .D(\U0/U_ICON/U_STAT/iTDO_next ), + .Q(\U0/U_ICON/iTDO_VEC [15]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/usrp2/extramfifo/icon.xco b/usrp2/extramfifo/icon.xco new file mode 100644 index 000000000..fda273149 --- /dev/null +++ b/usrp2/extramfifo/icon.xco @@ -0,0 +1,47 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Wed Jul 21 03:31:19 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a +# END Select +# BEGIN Parameters +CSET component_name=icon +CSET enable_jtag_bufg=true +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +GENERATE +# CRC: 799ba5a1 diff --git a/usrp2/extramfifo/ila.v b/usrp2/extramfifo/ila.v new file mode 100644 index 000000000..b0d8f8d0c --- /dev/null +++ b/usrp2/extramfifo/ila.v @@ -0,0 +1,5544 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.53d +// \ \ Application: netgen +// / / Filename: ila.v +// /___/ /\ Timestamp: Wed Jul 21 11:51:09 2010 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v +// Device : xc3s2000-fg456-5 +// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc +// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v +// # of Modules : 1 +// Design Name : ila +// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module ila ( + CLK, CONTROL, TRIG0, TRIG1, TRIG2, TRIG3 +)/* synthesis syn_black_box syn_noprune=1 */; + input CLK; + inout [35 : 0] CONTROL; + input [7 : 0] TRIG0; + input [7 : 0] TRIG1; + input [7 : 0] TRIG2; + input [3 : 0] TRIG3; + + // synthesis translate_off + + wire N0; + wire N1; + wire N38; + wire N39; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ; + wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ; + wire \U0/I_NO_D.U_ILA/U_RST/HALT_pulse ; + wire \U0/I_NO_D.U_ILA/U_RST/POR ; + wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ; + wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ; + wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ; + wire \U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ; + wire \U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ; + wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ; + wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ; + wire \U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/NS_load ; + wire \U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ; + wire \U0/I_NO_D.U_ILA/U_STAT/TDO_next ; + wire \U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ; + wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ; + wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ; + wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ; + wire \U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ; + wire \U0/I_NO_D.U_ILA/iARM ; + wire \U0/I_NO_D.U_ILA/iCAPTURE ; + wire \U0/I_NO_D.U_ILA/iCAP_DONE ; + wire \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ; + wire \U0/I_NO_D.U_ILA/iCAP_WR_EN ; + wire \U0/I_NO_D.U_ILA/iDATA_DOUT ; + wire \U0/I_NO_D.U_ILA/iSTAT_DOUT ; + wire \U0/I_NO_D.U_ILA/iTRIGGER ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED ; + wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED ; + wire [27 : 0] \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp ; + wire [13 : 1] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S ; + wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO ; + wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO ; + wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO ; + wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next ; + wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S ; + wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData ; + wire [4 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data ; + wire [16 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN ; + wire [0 : 0] \U0/I_NO_D.U_ILA/U_RST/iRESET ; + wire [8 : 0] \U0/I_NO_D.U_ILA/U_STAT/NS_dstat ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/STATE_dstat ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly ; + wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT ; + wire [9 : 1] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S ; + wire [16 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT ; + wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT ; + wire [1 : 1] \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA ; + wire [3 : 0] \U0/I_NO_D.U_ILA/U_TRIG/trigCondIn ; + wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES ; + wire [1 : 0] \U0/I_NO_D.U_ILA/iCAP_STATE ; + wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_WR_ADDR ; + wire [27 : 0] \U0/I_NO_D.U_ILA/iDATA ; + wire [7 : 0] \U0/I_NO_D.U_ILA/iRESET ; + wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy ; + wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut ; + wire [27 : 0] \U0/iTRIG_IN ; + GND XST_GND ( + .G(N0) + ); + VCC XST_VCC ( + .P(N1) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_HCMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_LCMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_SCNT_CMP_Q ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE0 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ), + .R(\U0/I_NO_D.U_ILA/iRESET [7]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_EN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG0 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG1 ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [7]), + .Q(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [1]) + ); + LUT3 #( + .INIT ( 8'h20 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG ( + .I0(\U0/I_NO_D.U_ILA/iTRIGGER ), + .I1(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .I2(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]), + .Q15(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF6 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 ( + .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .A2(\U0/I_NO_D.U_ILA/iTRIGGER ), + .A3(\U0/I_NO_D.U_ILA/iCAPTURE ), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ), + .R(N0), + .Q(\U0/I_NO_D.U_ILA/iCAP_DONE ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]), + .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_FDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ) +, + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]), + .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ) +, + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ), + .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK1 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK0 ( + .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]), + .I1(CONTROL[9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR_MUX ( + .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]), + .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]), + .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[9]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]), + .R(\U0/I_NO_D.U_ILA/iRESET [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[14].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[13].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[12].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[10].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[9].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[7].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[4].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[1].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL ( + .C(CONTROL[0]), + .CE(CONTROL[9]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL2 ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL3 ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_CR ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[8].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[6].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[5].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[4].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[3].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[2].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATE1 ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_STATE [1]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATE0 ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ), + .D(\U0/I_NO_D.U_ILA/iCAP_STATE [0]), + .R(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_ARM ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ), + .R(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_TRIGGER ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ), + .R(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_FULL ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ), + .R(\U0/I_NO_D.U_ILA/iARM ), + .S(\U0/I_NO_D.U_ILA/iCAP_DONE ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ) + ); + FDRS #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_ECR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ), + .R(\U0/I_NO_D.U_ILA/iARM ), + .S(N1), + .Q(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE ( + .C(CONTROL[0]), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/iARM ), + .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .PRE(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ) + ); + LDC #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC ( + .CLR(\U0/I_NO_D.U_ILA/iARM ), + .D(N1), + .G(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RISING ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ), + .D(N1), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_TDO ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ), + .Q(\U0/I_NO_D.U_ILA/iSTAT_DOUT ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[5]), + .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ), + .D(CONTROL[5]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/I_H2L.U_DOUT ( + .C(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]), + .R(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT1 ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT0 ( + .C(CONTROL[0]), + .CE(N1), + .D(CONTROL[5]), + .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ) + ); + LUT4 #( + .INIT ( 16'hFBEA )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ) + ); + LUT3 #( + .INIT ( 8'h53 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ) + ); + MUXF7 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_0 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ) + ); + MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD ( + .I0(CONTROL[4]), + .I1(CONTROL[5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ) + ); + INV \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD_n ( + .I(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSR ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .O(\NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ) + ); + LUT4 #( + .INIT ( 16'h0F22 )) + \U0/I_NO_D.U_ILA/U_STAT/U_NSL ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ), + .I3(\U0/I_NO_D.U_ILA/iRESET [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/NS_load ) + ); + LUT4 #( + .INIT ( 16'h0030 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[16].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]) + ); + LUT4 #( + .INIT ( 16'h1030 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[15].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[14].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]) + ); + LUT4 #( + .INIT ( 16'h1020 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[13].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[12].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]) + ); + LUT4 #( + .INIT ( 16'h1010 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[11].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]) + ); + LUT4 #( + .INIT ( 16'h0070 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[10].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]) + ); + LUT4 #( + .INIT ( 16'h100F )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[9].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]) + ); + LUT4 #( + .INIT ( 16'hFFF0 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[8].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]) + ); + LUT4 #( + .INIT ( 16'h0004 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[7].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]) + ); + LUT4 #( + .INIT ( 16'h3000 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[6].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]) + ); + LUT4 #( + .INIT ( 16'h001F )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[5].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]) + ); + LUT4 #( + .INIT ( 16'hF001 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[4].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]) + ); + LUT4 #( + .INIT ( 16'hB610 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[3].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]) + ); + LUT4 #( + .INIT ( 16'h2100 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[2].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]) + ); + LUT4 #( + .INIT ( 16'hC102 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[1].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]) + ); + LUT4 #( + .INIT ( 16'h0101 )) + \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[0].I_STAT.U_STAT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]), + .I1(CONTROL[5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]), + .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_FDRE ( + .C(CONTROL[0]), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]), + .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ), + .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/U_POR ( + .C(CLK), + .D(N0), + .PRE(N0), + .Q(\U0/I_NO_D.U_ILA/U_RST/POR ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [0]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[1].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [0]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [1]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[2].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [1]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [2]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[3].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [2]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [3]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[4].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [3]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [4]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[5].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [4]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [5]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[6].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [5]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [6]) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_RST/G_RST[7].U_RST ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/iRESET [6]), + .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ), + .Q(\U0/I_NO_D.U_ILA/iRESET [7]) + ); + LUT3 #( + .INIT ( 8'hEF )) + \U0/I_NO_D.U_ILA/U_RST/U_PRST1 ( + .I0(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ), + .I1(\U0/I_NO_D.U_ILA/U_RST/POR ), + .I2(N1), + .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ) + ); + LUT4 #( + .INIT ( 16'hFFFE )) + \U0/I_NO_D.U_ILA/U_RST/U_PRST0 ( + .I0(N0), + .I1(\U0/I_NO_D.U_ILA/iCAP_DONE ), + .I2(N0), + .I3(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ), + .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \U0/I_NO_D.U_ILA/U_RST/U_RST0 ( + .I0(\U0/I_NO_D.U_ILA/iARM ), + .I1(\U0/I_NO_D.U_ILA/iRESET [0]), + .O(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ), + .I1(CONTROL[13]), + .O(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[2].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[13]), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ), + .D(CONTROL[13]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR ( + .I0(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ), + .I1(CONTROL[12]), + .O(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[4].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/iARM ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ), + .Q(\U0/I_NO_D.U_ILA/iARM ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[2].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ) + ); + FDE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[1].U_FD ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE ( + .C(CLK), + .CE(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]), + .R(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT1 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0 ( + .C(CLK), + .CE(N1), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE ( + .C(CONTROL[0]), + .CE(CONTROL[12]), + .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ), + .D(CONTROL[12]), + .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_FDRE ( + .C(CONTROL[0]), + .CE(CONTROL[6]), + .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]), + .R(CONTROL[14]), + .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].GnH.U_MUXCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_XORCY ( + .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]) + ); + LUT1 #( + .INIT ( 2'h2 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].GnH.U_MUXCY ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]), + .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]) + ); + XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_XORCY ( + .CI(N1), + .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]), + .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [24]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [25]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [26]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [27]), + .PRE(CONTROL[23]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N1), + .CE(CONTROL[23]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[23]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_YES_MUXH.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [0]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [1]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [2]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [3]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [4]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [5]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [6]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [7]), + .PRE(CONTROL[20]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[20]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[20]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [8]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [9]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [10]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [11]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [12]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [13]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [14]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [15]), + .PRE(CONTROL[21]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[21]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[21]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [16]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [17]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [18]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [19]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [20]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [21]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [22]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG ( + .C(CLK), + .CE(N1), + .D(\U0/iTRIG_IN [23]), + .PRE(CONTROL[22]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ), + .S(\U0/I_NO_D.U_ILA/iRESET [0]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ), + .CE(CONTROL[22]), + .CLK(CONTROL[0]), + .D(CONTROL[1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ), + .CE(CONTROL[22]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ) + + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ) + ); + MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL ( + .CI(N1), + .DI(N0), + .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ), + .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ) + ); + XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH ( + .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ), + .LI(N0), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]), + .Q(\U0/I_NO_D.U_ILA/iDATA [0]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]), + .Q(\U0/I_NO_D.U_ILA/iDATA [1]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]), + .Q(\U0/I_NO_D.U_ILA/iDATA [2]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]), + .Q(\U0/I_NO_D.U_ILA/iDATA [3]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]), + .Q(\U0/I_NO_D.U_ILA/iDATA [4]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]), + .Q(\U0/I_NO_D.U_ILA/iDATA [5]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]), + .Q(\U0/I_NO_D.U_ILA/iDATA [6]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]), + .Q(\U0/I_NO_D.U_ILA/iDATA [7]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]), + .Q(\U0/I_NO_D.U_ILA/iDATA [8]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]), + .Q(\U0/I_NO_D.U_ILA/iDATA [9]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]), + .Q(\U0/I_NO_D.U_ILA/iDATA [10]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]), + .Q(\U0/I_NO_D.U_ILA/iDATA [11]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]), + .Q(\U0/I_NO_D.U_ILA/iDATA [12]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]), + .Q(\U0/I_NO_D.U_ILA/iDATA [13]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]), + .Q(\U0/I_NO_D.U_ILA/iDATA [14]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]), + .Q(\U0/I_NO_D.U_ILA/iDATA [15]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]), + .Q(\U0/I_NO_D.U_ILA/iDATA [16]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]), + .Q(\U0/I_NO_D.U_ILA/iDATA [17]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]), + .Q(\U0/I_NO_D.U_ILA/iDATA [18]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]), + .Q(\U0/I_NO_D.U_ILA/iDATA [19]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]), + .Q(\U0/I_NO_D.U_ILA/iDATA [20]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]), + .Q(\U0/I_NO_D.U_ILA/iDATA [21]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]), + .Q(\U0/I_NO_D.U_ILA/iDATA [22]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]), + .Q(\U0/I_NO_D.U_ILA/iDATA [23]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]), + .Q(\U0/I_NO_D.U_ILA/iDATA [24]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]), + .Q(\U0/I_NO_D.U_ILA/iDATA [25]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]), + .Q(\U0/I_NO_D.U_ILA/iDATA [26]) + ); + FD #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.FF ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]), + .Q(\U0/I_NO_D.U_ILA/iDATA [27]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [0]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [1]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [2]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [3]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [4]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [5]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [6]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [7]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [8]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [9]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [10]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [11]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [12]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [13]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [14]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [15]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [16]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [17]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [18]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [19]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [20]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [21]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [22]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [23]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [24]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [25]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [26]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.DLY9 ( + .A0(N1), + .A1(N1), + .A2(N1), + .A3(N0), + .CLK(CLK), + .D(\U0/iTRIG_IN [27]), + .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]) + ); + LUT3 #( + .INIT ( 8'hCA )) + \U0/I_NO_D.U_ILA/U_DOUT ( + .I0(\U0/I_NO_D.U_ILA/iSTAT_DOUT ), + .I1(\U0/I_NO_D.U_ILA/iDATA_DOUT ), + .I2(CONTROL[6]), + .O(CONTROL[3]) + ); + LUT1 #( + .INIT ( 2'h1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B ( + .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ), + .O(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]), + .CE(CONTROL[8]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .Q15 +(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ) + + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]), + .I1(CONTROL[8]), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E ( + .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]), + .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]), + .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]), + .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]), + .CE(CONTROL[8]), + .CLK(CONTROL[0]), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT ( + .I0(CONTROL[1]), + .I1(CONTROL[8]), + .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG ( + .C(CLK), + .CE(N1), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ), + .PRE(\U0/I_NO_D.U_ILA/iRESET [1]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ) + ); + FDS #( + .INIT ( 1'b1 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_NO.U_NO_MC_REG ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ), + .S(\U0/I_NO_D.U_ILA/iRESET [2]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_DLY ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/iCAPTURE ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ), + .R(\U0/I_NO_D.U_ILA/iRESET [4]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ), + .R(\U0/I_NO_D.U_ILA/iRESET [3]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ), + .R(\U0/I_NO_D.U_ILA/iRESET [4]), + .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ) + ); + FDR #( + .INIT ( 1'b0 )) + \U0/I_NO_D.U_ILA/U_TRIG/F_NO_TCMC.U_FDR ( + .C(CLK), + .D(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ), + .R(\U0/I_NO_D.U_ILA/iRESET [5]), + .Q(\U0/I_NO_D.U_ILA/iTRIGGER ) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG3[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [27]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG3[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [26]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG3[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [25]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ3.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG3[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [24]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG2[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [23]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG2[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [22]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG2[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [21]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG2[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [20]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG2[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [19]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG2[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [18]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG2[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [17]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ2.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG2[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [16]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG1[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [15]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG1[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [14]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG1[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [13]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG1[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [12]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG1[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [11]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG1[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [10]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG1[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [9]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ1.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG1[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [8]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[7].U_TQ ( + .C(CLK), + .D(TRIG0[7]), + .PRE(N0), + .Q(\U0/iTRIG_IN [7]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[6].U_TQ ( + .C(CLK), + .D(TRIG0[6]), + .PRE(N0), + .Q(\U0/iTRIG_IN [6]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[5].U_TQ ( + .C(CLK), + .D(TRIG0[5]), + .PRE(N0), + .Q(\U0/iTRIG_IN [5]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[4].U_TQ ( + .C(CLK), + .D(TRIG0[4]), + .PRE(N0), + .Q(\U0/iTRIG_IN [4]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[3].U_TQ ( + .C(CLK), + .D(TRIG0[3]), + .PRE(N0), + .Q(\U0/iTRIG_IN [3]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[2].U_TQ ( + .C(CLK), + .D(TRIG0[2]), + .PRE(N0), + .Q(\U0/iTRIG_IN [2]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[1].U_TQ ( + .C(CLK), + .D(TRIG0[1]), + .PRE(N0), + .Q(\U0/iTRIG_IN [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \U0/I_TQ0.G_TW[0].U_TQ ( + .C(CLK), + .D(TRIG0[0]), + .PRE(N0), + .Q(\U0/iTRIG_IN [0]) + ); + LUT2 #( + .INIT ( 4'h8 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<0> ( + .I0(CONTROL[10]), + .I1(CONTROL[11]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<0> ( + .CI(N1), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1> ( + .I0(CONTROL[12]), + .I1(CONTROL[13]), + .I2(CONTROL[9]), + .I3(CONTROL[14]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<2> ( + .I0(CONTROL[15]), + .I1(CONTROL[16]), + .I2(CONTROL[8]), + .I3(CONTROL[17]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3> ( + .I0(CONTROL[18]), + .I1(CONTROL[21]), + .I2(CONTROL[7]), + .I3(CONTROL[19]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<4> ( + .I0(CONTROL[20]), + .I1(CONTROL[22]), + .I2(CONTROL[6]), + .I3(CONTROL[23]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<5> ( + .I0(CONTROL[24]), + .I1(CONTROL[25]), + .I2(CONTROL[5]), + .I3(CONTROL[26]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<6> ( + .I0(CONTROL[27]), + .I1(CONTROL[28]), + .I2(CONTROL[2]), + .I3(CONTROL[29]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<7> ( + .I0(CONTROL[30]), + .I1(CONTROL[31]), + .I2(CONTROL[1]), + .I3(CONTROL[32]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<8> ( + .I0(CONTROL[33]), + .I1(CONTROL[34]), + .I2(CONTROL[4]), + .I3(CONTROL[35]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]) + ); + MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8> ( + .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]), + .DI(N0), + .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]), + .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]) + ); + LUT4 #( + .INIT ( 16'hFEFF )) + \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ) + ); + LUT4 #( + .INIT ( 16'hFFFE )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ) + ); + LUT4 #( + .INIT ( 16'hF222 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ), + .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ) + ); + LUT4 #( + .INIT ( 16'hAF8D )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O129 ( + .I0(CONTROL[4]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ), + .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ) + ); + MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91 ( + .I0(N38), + .I1(N39), + .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ) + ); + LUT3 #( + .INIT ( 8'h15 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ), + .O(N38) + ); + LUT4 #( + .INIT ( 16'h0145 )) + \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_G ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ), + .O(N39) + ); + LUT4_L #( + .INIT ( 16'h3F50 )) + \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ), + .I1(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ), + .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]), + .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]), + .LO(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ) + ); + LUT4_L #( + .INIT ( 16'h3120 )) + \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82 ( + .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]), + .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]), + .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ), + .I3(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ), + .LO(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ) + ); + RAMB16_S1_S36 #( + .INIT_B ( 36'h000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_A ( 1'h0 ), + .SIM_COLLISION_CHECK ( "ALL" ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .SRVAL_A ( 1'h0 ), + .WRITE_MODE_A ( "WRITE_FIRST" ), + .WRITE_MODE_B ( "WRITE_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i ( + .CLKA(CONTROL[0]), + .CLKB(CLK), + .ENA(CONTROL[6]), + .ENB(N1), + .WEB(\U0/I_NO_D.U_ILA/iCAP_WR_EN ), + .SSRA(N0), + .SSRB(N0), + .WEA(N0), + .DIPB({N0, N0, N0, N0}), + .ADDRA({\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2], +\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]}), + .ADDRB({\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5] +, \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1], +\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]}), + .DIB({N0, N0, N0, \U0/I_NO_D.U_ILA/iDATA [27], \U0/I_NO_D.U_ILA/iDATA [26], \U0/I_NO_D.U_ILA/iDATA [25], \U0/I_NO_D.U_ILA/iDATA [24], +\U0/I_NO_D.U_ILA/iDATA [23], \U0/I_NO_D.U_ILA/iDATA [22], \U0/I_NO_D.U_ILA/iDATA [21], \U0/I_NO_D.U_ILA/iDATA [20], \U0/I_NO_D.U_ILA/iDATA [19], +\U0/I_NO_D.U_ILA/iDATA [18], \U0/I_NO_D.U_ILA/iDATA [17], \U0/I_NO_D.U_ILA/iDATA [16], \U0/I_NO_D.U_ILA/iDATA [15], \U0/I_NO_D.U_ILA/iDATA [14], +\U0/I_NO_D.U_ILA/iDATA [13], \U0/I_NO_D.U_ILA/iDATA [12], \U0/I_NO_D.U_ILA/iDATA [11], \U0/I_NO_D.U_ILA/iDATA [10], \U0/I_NO_D.U_ILA/iDATA [9], +\U0/I_NO_D.U_ILA/iDATA [8], \U0/I_NO_D.U_ILA/iDATA [7], \U0/I_NO_D.U_ILA/iDATA [6], \U0/I_NO_D.U_ILA/iDATA [5], \U0/I_NO_D.U_ILA/iDATA [4], +\U0/I_NO_D.U_ILA/iDATA [3], \U0/I_NO_D.U_ILA/iDATA [2], \U0/I_NO_D.U_ILA/iDATA [1], \U0/I_NO_D.U_ILA/iDATA [0], \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT }), + .DOA({\U0/I_NO_D.U_ILA/iDATA_DOUT }), + .DIA({N0}), + .DOB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED }), + .DOPB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED , +\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED }) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/usrp2/extramfifo/ila.xco b/usrp2/extramfifo/ila.xco new file mode 100644 index 000000000..c8d4d2f75 --- /dev/null +++ b/usrp2/extramfifo/ila.xco @@ -0,0 +1,130 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Wed Jul 21 18:51:14 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a +# END Select +# BEGIN Parameters +CSET component_name=ila +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic +CSET match_type_10=basic +CSET match_type_11=basic +CSET match_type_12=basic +CSET match_type_13=basic +CSET match_type_14=basic +CSET match_type_15=basic +CSET match_type_16=basic +CSET match_type_2=basic +CSET match_type_3=basic +CSET match_type_4=basic +CSET match_type_5=basic +CSET match_type_6=basic +CSET match_type_7=basic +CSET match_type_8=basic +CSET match_type_9=basic +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=4 +CSET sample_data_depth=512 +CSET sample_on=Rising +CSET trigger_port_width_1=8 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=4 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=true +# END Parameters +GENERATE +# CRC: 66151c7c diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 1bd7439ad..7ddb517c7 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -1,3 +1,9 @@ +// Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port +// device it can only sustain data throughput at half the RAM clock rate. +// Fair arbitration to ensure this occurs is included in this logic and +// requests for transactions that can not be completed are held off by (re)using the +// "full" and "empty" flags. + module nobl_fifo #(parameter WIDTH=18,DEPTH=19) ( @@ -17,14 +23,14 @@ module nobl_fifo output reg space_avail, output reg [WIDTH-1:0] read_data, input read_strobe, - output reg data_avail + output reg data_avail, + input upstream_full // (Connect to almost full flag upstream) ); reg [DEPTH-1:0] capacity; reg [DEPTH-1:0] wr_pointer; reg [DEPTH-1:0] rd_pointer; wire [DEPTH-1:0] address; - reg supress; reg data_avail_int; // Data available with high latency from ext FIFO flag wire [WIDTH-1:0] data_in; @@ -38,7 +44,7 @@ module nobl_fifo assign read = read_strobe_int && data_avail_int; assign write = write_strobe && space_avail; - // When a read and write collision occur, supress availability flags next cycle + // When a read and write collision occur, supress the availability flags next cycle // and complete write followed by read over 2 cycles. This forces balanced arbitration // and makes for a simple logic design. @@ -231,9 +237,11 @@ module nobl_fifo // Start an external FIFO read as soon as a read of the buffer reg is strobed to minimise refill latency. // If the buffer reg or the pending buffer reg is already empty also pre-emptively start a read. - // However there must be something in ext FIFO to read. - // This means that there can be 2 outstanding reads to the ext FIFO active at any time helping to hide latency. - assign read_strobe_int = (read_strobe & data_avail & ~pending_avail) || (~data_avail && ~pending_avail); + // However there must be something in the main external FIFO to read for this to occur!. + // Pay special attention to upstream devices signalling full due to the number of potential in-flight reads\ that need + // to be stalled and stored somewhere. + // This means that there can be 3 outstanding reads to the ext FIFO active at any time helping to hide latency. + assign read_strobe_int = (read_strobe && data_avail && ~pending_avail && ~upstream_full) || (~data_avail && ~pending_avail && ~upstream_full); // diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index 3143ce5ba..24d463b1e 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -1,3 +1,5 @@ +// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world. + module nobl_if #(parameter WIDTH=18,DEPTH=19) ( @@ -35,9 +37,9 @@ module nobl_if reg [WIDTH-1:0] data_out_pipe3; assign RAM_LDn = 0; + // ZBT/NoBL RAM actually manages its own output enables very well. assign RAM_OEn = 0; - // // Pipeline stage 1 // @@ -129,8 +131,5 @@ module nobl_if else data_in_valid <= 1'b0; end // always @ (posedge clk) - - - - + endmodule // nobl_if diff --git a/usrp2/extramfifo/test_sram_if.v b/usrp2/extramfifo/test_sram_if.v index 9f36b409c..0e74b49eb 100644 --- a/usrp2/extramfifo/test_sram_if.v +++ b/usrp2/extramfifo/test_sram_if.v @@ -1,3 +1,7 @@ +// Instantiate this block at the core level to conduct closed +// loop testing of the AC performance of the USRP2 SRAM interface + + `define WIDTH 18 `define DEPTH 19 diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index 1114c731e..6f855a070 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -34,6 +34,7 @@ synth: $(ISE_FILE) $(ISE_HELPER) "Synthesize - XST" bin: check $(BIN_FILE) + $(ISE_HELPER) "Generate Programming File" mcs: $(MCS_FILE) diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp index 9962887d4..99effb038 100644 --- a/usrp2/top/u2_rev3/Makefile.udp +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + ################################################## # Project Properties diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 3b565ba90..b0c8e6d52 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -119,7 +119,9 @@ module u2_core inout [15:0] io_rx, // External RAM - inout [17:0] RAM_D, + input [17:0] RAM_D_pi, + output [17:0] RAM_D_po, + output RAM_D_poe, output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, @@ -646,10 +648,28 @@ module u2_core wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; - fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.DEPTH(19)) + ext_fifo_i1 + ( + .int_clk(dsp_clk), + .ext_clk(clk_to_mac), + .rst(dsp_rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain({rd1_flags,rd1_dat}), + .src_rdy_i(rd1_ready_o), // WRITE + .dst_rdy_o(rd1_ready_i), // not FULL + .dataout(tx_data), + .src_rdy_o(tx_src_rdy), // not EMPTY + .dst_rdy_i(tx_dst_rdy) + ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) @@ -678,6 +698,9 @@ module u2_core .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + assign RAM_CLK = clk_to_mac; + + // ///////////////////////////////////////////////////////////////////////// // VITA Timing diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 6aa699d2a..82d879446 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -74,49 +74,49 @@ NET "MDC" LOC = "V18" ; NET "PHY_INTn" LOC = "AB13" ; NET "PHY_RESETn" LOC = "AA19" ; NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" ; -NET "RAM_D[1]" LOC = "N21" ; -NET "RAM_D[2]" LOC = "N22" ; -NET "RAM_D[3]" LOC = "M17" ; -NET "RAM_D[4]" LOC = "M18" ; -NET "RAM_D[5]" LOC = "M19" ; -NET "RAM_D[6]" LOC = "M20" ; -NET "RAM_D[7]" LOC = "M21" ; -NET "RAM_D[8]" LOC = "M22" ; -NET "RAM_D[9]" LOC = "Y22" ; -NET "RAM_D[10]" LOC = "Y21" ; -NET "RAM_D[11]" LOC = "Y20" ; -NET "RAM_D[12]" LOC = "Y19" ; -NET "RAM_D[13]" LOC = "W22" ; -NET "RAM_D[14]" LOC = "W21" ; -NET "RAM_D[15]" LOC = "W20" ; -NET "RAM_D[16]" LOC = "W19" ; -NET "RAM_D[17]" LOC = "V22" ; -NET "RAM_A[0]" LOC = "U21" ; -NET "RAM_A[1]" LOC = "T19" ; -NET "RAM_A[2]" LOC = "V21" ; -NET "RAM_A[3]" LOC = "V20" ; -NET "RAM_A[4]" LOC = "T20" ; -NET "RAM_A[5]" LOC = "T21" ; -NET "RAM_A[6]" LOC = "T22" ; -NET "RAM_A[7]" LOC = "T18" ; -NET "RAM_A[8]" LOC = "R18" ; -NET "RAM_A[9]" LOC = "P19" ; -NET "RAM_A[10]" LOC = "P21" ; -NET "RAM_A[11]" LOC = "P22" ; -NET "RAM_A[12]" LOC = "N19" ; -NET "RAM_A[13]" LOC = "N17" ; -NET "RAM_A[14]" LOC = "N18" ; -NET "RAM_A[15]" LOC = "T17" ; -NET "RAM_A[16]" LOC = "U19" ; -NET "RAM_A[17]" LOC = "U18" ; -NET "RAM_A[18]" LOC = "V19" ; -NET "RAM_CE1n" LOC = "U20" ; -NET "RAM_CENn" LOC = "P18" ; -NET "RAM_CLK" LOC = "P17" ; -NET "RAM_WEn" LOC = "R22" ; -NET "RAM_OEn" LOC = "R21" ; -NET "RAM_LDn" LOC = "R19" ; +NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; NET "ser_enable" LOC = "W11" ; NET "ser_prbsen" LOC = "AA3" ; NET "ser_loopen" LOC = "Y4" ; diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index bab5a7706..5e32b368a 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -345,100 +345,133 @@ module u2_rev3 .S(0) // Synchronous preset input ); */ + + wire [17:0] RAM_D_pi; + wire [17:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + + u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk_buf), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_misc (cpld_misc), - .cpld_init_b (cpld_init_b), - .por (~POR), - .config_success (config_success), - .adc_a (adc_a_reg2), - .adc_ovf_a (adc_ovf_a_reg2), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b_reg2), - .adc_ovf_b (adc_ovf_b_reg2), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a_int), - .dac_b (dac_b_int), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk_buf), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_pi (RAM_D_pi), + .RAM_D_po (RAM_D_po), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); endmodule // u2_rev2 -- cgit v1.2.3 From 408fac953746c8da3d476f294afdbf578df68754 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 11 Aug 2010 13:59:06 -0700 Subject: checkin of generated coregen files --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 3 + usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo | 52 +++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 6 +- ...12x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso | 3 + ...k_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 102 +++++++++++++++++++++ .../coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt | 8 ++ .../fifo_xlnx_512x36_2clk_18to36_readme.txt | 39 ++++++++ .../coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl | 68 ++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc | 3 + usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo | 51 +++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco | 6 +- ...12x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso | 3 + ...k_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 101 ++++++++++++++++++++ .../coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt | 8 ++ .../fifo_xlnx_512x36_2clk_36to18_readme.txt | 39 ++++++++ .../coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl | 68 ++++++++++++++ 18 files changed, 556 insertions(+), 8 deletions(-) create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc new file mode 100644 index 000000000..376e18c57 --- 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v index 32de19e8a..531d56c08 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v @@ -63,7 +63,7 @@ output full; // synthesis translate_off - FIFO_GENERATOR_V4_4 #( + FIFO_GENERATOR_V4_3 #( .C_COMMON_CLOCK(0), .C_COUNT_TYPE(0), .C_DATA_COUNT_WIDTH(10), diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo new file mode 100644 index 000000000..cd949ccaa --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo @@ -0,0 +1,52 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_18to36 YourInstanceName ( + .din(din), // Bus [17 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .almost_full(almost_full), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating +// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco index 05ceffbe9..12b88da39 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version K.39 -# Date: Fri Jul 30 20:43:00 2010 +# Date: Tue Aug 10 23:12:53 2010 # ############################################################## # @@ -32,7 +32,7 @@ SET verilogsim = true SET vhdlsim = false # END Project Options # BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 # END Select # BEGIN Parameters CSET almost_empty_flag=false @@ -78,5 +78,5 @@ CSET write_data_count=false CSET write_data_count_width=10 # END Parameters GENERATE -# CRC: 9b689ee4 +# CRC: 6866170 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..f718bb394 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,102 @@ + + + + + + +
+ + + + + + + + + + + + + + + +
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+ + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt new file mode 100644 index 000000000..18ba3e664 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_512x36_2clk_18to36.ngc +fifo_xlnx_512x36_2clk_18to36.v +fifo_xlnx_512x36_2clk_18to36.veo +fifo_xlnx_512x36_2clk_18to36.xco +fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_18to36_flist.txt +fifo_xlnx_512x36_2clk_18to36_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt new file mode 100644 index 000000000..e0d45849d --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory +/home/matt/fpgapriv/usrp2/coregen/: + +fifo_xlnx_512x36_2clk_18to36.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_18to36.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_18to36.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_18to36.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_18to36_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_512x36_2clk_18to36_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_18to36_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl new file mode 100644 index 000000000..f20d53f64 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_18to36_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_18to36_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_18to36 +} +# ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_18to36 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc new file mode 100644 index 000000000..d76e4c3db --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$5ca4g<,[o}e~g`n;"2*413&;$>"9 > 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v index f7f6e7e9f..6f849b24c 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v @@ -61,7 +61,7 @@ output full; // synthesis translate_off - FIFO_GENERATOR_V4_4 #( + FIFO_GENERATOR_V4_3 #( .C_COMMON_CLOCK(0), .C_COUNT_TYPE(0), .C_DATA_COUNT_WIDTH(9), diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo new file mode 100644 index 000000000..5c2da4b97 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo @@ -0,0 +1,51 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_36to18 YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [17 : 0] + .empty(empty), + .full(full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating +// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco index a1c75dc39..9f47c073c 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version K.39 -# Date: Thu Jul 29 18:10:59 2010 +# Date: Tue Aug 10 23:09:39 2010 # ############################################################## # @@ -32,7 +32,7 @@ SET verilogsim = true SET vhdlsim = false # END Project Options # BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 # END Select # BEGIN Parameters CSET almost_empty_flag=false @@ -78,5 +78,5 @@ CSET write_data_count=false CSET write_data_count_width=9 # END Parameters GENERATE -# CRC: 392ad537 +# CRC: b2f58113 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..3abf04253 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,101 @@ + + + + + + +
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+
+ + + +
+ + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt new file mode 100644 index 000000000..aadac46c0 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_512x36_2clk_36to18.ngc +fifo_xlnx_512x36_2clk_36to18.v +fifo_xlnx_512x36_2clk_36to18.veo +fifo_xlnx_512x36_2clk_36to18.xco +fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_36to18_flist.txt +fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt new file mode 100644 index 000000000..568c757ec --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory +/home/matt/fpgapriv/usrp2/coregen/: + +fifo_xlnx_512x36_2clk_36to18.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_36to18.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_36to18.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_36to18.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_36to18_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_512x36_2clk_36to18_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_36to18_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl new file mode 100644 index 000000000..09248b321 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_36to18_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_36to18_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_36to18 +} +# ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_36to18 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams -- cgit v1.2.3 From ff21cc7592573249938022fdcf118d73928a037e Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 12:00:01 -0700 Subject: Found bug due to not accounting for the correct number of possible in flight READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 4 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 68 ++++++++++++++------------ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 18 ++++--- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc | 2 +- usrp2/extramfifo/ext_fifo.v | 15 ++++-- usrp2/extramfifo/ext_fifo_tb.v | 39 +++++++++++++++ usrp2/extramfifo/nobl_fifo.v | 16 +++--- 7 files changed, 110 insertions(+), 52 deletions(-) diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc index 376e18c57..657b1aa98 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$4264g<,[o}e~g`n;"2*413&;$>"9 > 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diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index a506d71e2..c7e8f6cfb 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -57,10 +57,18 @@ module ext_fifo .dout(write_data), // Bus [17 : 0] .full(full1), .empty(empty1)); - assign dst_rdy_o = ~full1; + + assign dst_rdy_o = ~full1; + +/* -----\/----- EXCLUDED -----\/----- + assign space_avail = ~full2; + assign data_avail = ~empty1; + assign read_data = write_data; + -----/\----- EXCLUDED -----/\----- */ + // External FIFO running at ext clock rate and 18 bit width. - nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH)) + nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH),.FDEPTH(DEPTH)) nobl_fifo_i1 ( .clk(ext_clk), @@ -94,7 +102,8 @@ module ext_fifo .rd_en(dst_rdy_i), .dout(dataout), // Bus [35 : 0] .full(full2), - .almost_full(almost_full2), + .almost_full(), + .prog_full(almost_full2), .empty(empty2)); assign src_rdy_o = ~empty2; diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index 38df4a285..a93d524d5 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -51,6 +51,44 @@ module ext_fifo_tb(); always #4 ext_clk <= ~ext_clk; + initial + begin + rst <= 1; + repeat (5) @(negedge int_clk); + rst <= 0; + @(negedge int_clk); + while (datain < 10000) + begin + @(negedge int_clk); + datain <= datain + dst_rdy_o; + src_rdy_i <= dst_rdy_o; + end + end // initial begin + + + initial + begin + repeat (20) @(negedge int_clk); + + // Fall through fifo, first output already valid + if (dataout !== ref_dataout) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + + while (ref_dataout < 10000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(6) @(negedge int_clk); + end + end + + +/* -----\/----- EXCLUDED -----\/----- initial begin @@ -112,6 +150,7 @@ module ext_fifo_tb(); end // initial begin + -----/\----- EXCLUDED -----/\----- */ /////////////////////////////////////////////////////////////////////////////////// // Simulation control // /////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 7ddb517c7..03e3f5223 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -5,7 +5,7 @@ // "full" and "empty" flags. module nobl_fifo - #(parameter WIDTH=18,DEPTH=19) + #(parameter WIDTH=18,DEPTH=19,FDEPTH=10) ( input clk, input rst, @@ -27,9 +27,9 @@ module nobl_fifo input upstream_full // (Connect to almost full flag upstream) ); - reg [DEPTH-1:0] capacity; - reg [DEPTH-1:0] wr_pointer; - reg [DEPTH-1:0] rd_pointer; + reg [FDEPTH-1:0] capacity; + reg [FDEPTH-1:0] wr_pointer; + reg [FDEPTH-1:0] rd_pointer; wire [DEPTH-1:0] address; reg supress; reg data_avail_int; // Data available with high latency from ext FIFO flag @@ -51,7 +51,7 @@ module nobl_fifo always @(posedge clk) if (rst) begin - capacity <= 1 << (DEPTH-1); + capacity <= 1 << (FDEPTH-1); wr_pointer <= 0; rd_pointer <= 0; space_avail <= 0; @@ -60,9 +60,11 @@ module nobl_fifo end else begin - space_avail <= ~((capacity == 0) || (read&&write) || (capacity == 1 && write) ); + // No space available if: + // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) + space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == (1 << (DEPTH-1))) || (read&&write) || (capacity == ((1 << (DEPTH-1))-1) && read) ); + data_avail_int <= ~((capacity == (1 << (FDEPTH-1))) || (read&&write) || ((capacity == ((1 << (FDEPTH-1))-1)) && read) ); supress <= read && write; wr_pointer <= wr_pointer + write; rd_pointer <= rd_pointer + ((~write && read) || supress); -- cgit v1.2.3 From 04e5b7128d4e40766ca5dbf3a9abc294464de721 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 12:28:13 -0700 Subject: Bringing all coregen files checked in into sync --- usrp2/coregen/fifo_generator_ug175.pdf | Bin 1069823 -> 2895895 bytes usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo | 12 +-- .../coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt | 6 +- .../fifo_xlnx_512x36_2clk_18to36_readme.txt | 22 +++-- .../coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl | 8 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo | 12 +-- ...k_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 101 --------------------- .../coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt | 6 +- .../fifo_xlnx_512x36_2clk_36to18_readme.txt | 22 +++-- .../coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl | 8 +- 10 files changed, 60 insertions(+), 137 deletions(-) delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt diff --git a/usrp2/coregen/fifo_generator_ug175.pdf b/usrp2/coregen/fifo_generator_ug175.pdf index 2c3e3c200..5fba6029c 100644 Binary files a/usrp2/coregen/fifo_generator_ug175.pdf and b/usrp2/coregen/fifo_generator_ug175.pdf differ diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo index cd949ccaa..c962fddfa 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo @@ -23,7 +23,7 @@ * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * -* (c) Copyright 1995-2007 Xilinx, Inc. * +* (c) Copyright 1995-2009 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // The following must be inserted into your Verilog file for this @@ -32,16 +32,16 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG fifo_xlnx_512x36_2clk_18to36 YourInstanceName ( - .din(din), // Bus [17 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [17 : 0] .wr_en(wr_en), - .almost_full(almost_full), + .rd_en(rd_en), .dout(dout), // Bus [35 : 0] + .full(full), .empty(empty), - .full(full)); + .prog_full(prog_full)); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt index 18ba3e664..2f8d522f6 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt @@ -1,8 +1,12 @@ # Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_18to36.gise fifo_xlnx_512x36_2clk_18to36.ngc fifo_xlnx_512x36_2clk_18to36.v fifo_xlnx_512x36_2clk_18to36.veo fifo_xlnx_512x36_2clk_18to36.xco -fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_18to36.xise fifo_xlnx_512x36_2clk_18to36_flist.txt +fifo_xlnx_512x36_2clk_18to36_readme.txt fifo_xlnx_512x36_2clk_18to36_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt index e0d45849d..03829e876 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt @@ -1,5 +1,12 @@ The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory -/home/matt/fpgapriv/usrp2/coregen/: +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_18to36.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. fifo_xlnx_512x36_2clk_18to36.ngc: Binary Xilinx implementation netlist file containing the information @@ -18,12 +25,9 @@ fifo_xlnx_512x36_2clk_18to36.xco: CORE Generator input file containing the parameters used to regenerate a core. -fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_18to36_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. +fifo_xlnx_512x36_2clk_18to36.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. fifo_xlnx_512x36_2clk_18to36_readme.txt: Text file indicating the files generated and how they are used. @@ -33,6 +37,10 @@ fifo_xlnx_512x36_2clk_18to36_xmdf.tcl: how the files output by CORE Generator for the core can be integrated into your ISE project. +fifo_xlnx_512x36_2clk_18to36_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + Please see the Xilinx CORE Generator online help for further details on generated files and how to use them. diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl index f20d53f64..9b9b1f37a 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl @@ -36,6 +36,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim incr fcount +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc incr fcount @@ -52,10 +56,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_51 utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView incr fcount diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo index 5c2da4b97..e93be1591 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo @@ -23,7 +23,7 @@ * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * -* (c) Copyright 1995-2007 Xilinx, Inc. * +* (c) Copyright 1995-2009 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // The following must be inserted into your Verilog file for this @@ -32,15 +32,15 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG fifo_xlnx_512x36_2clk_36to18 YourInstanceName ( - .din(din), // Bus [35 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] .wr_en(wr_en), + .rd_en(rd_en), .dout(dout), // Bus [17 : 0] - .empty(empty), - .full(full)); + .full(full), + .empty(empty)); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index 3abf04253..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,101 +0,0 @@ - - - - - - -

- - - - - - - - - - - - - - -
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- - - diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt index aadac46c0..54c85b15e 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt @@ -1,8 +1,12 @@ # Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_36to18.gise fifo_xlnx_512x36_2clk_36to18.ngc fifo_xlnx_512x36_2clk_36to18.v fifo_xlnx_512x36_2clk_36to18.veo fifo_xlnx_512x36_2clk_36to18.xco -fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_36to18.xise fifo_xlnx_512x36_2clk_36to18_flist.txt +fifo_xlnx_512x36_2clk_36to18_readme.txt fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt index 568c757ec..3efc586bf 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt @@ -1,5 +1,12 @@ The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory -/home/matt/fpgapriv/usrp2/coregen/: +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_36to18.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. fifo_xlnx_512x36_2clk_36to18.ngc: Binary Xilinx implementation netlist file containing the information @@ -18,12 +25,9 @@ fifo_xlnx_512x36_2clk_36to18.xco: CORE Generator input file containing the parameters used to regenerate a core. -fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_36to18_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. +fifo_xlnx_512x36_2clk_36to18.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. fifo_xlnx_512x36_2clk_36to18_readme.txt: Text file indicating the files generated and how they are used. @@ -33,6 +37,10 @@ fifo_xlnx_512x36_2clk_36to18_xmdf.tcl: how the files output by CORE Generator for the core can be integrated into your ISE project. +fifo_xlnx_512x36_2clk_36to18_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + Please see the Xilinx CORE Generator online help for further details on generated files and how to use them. diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl index 09248b321..5161c1826 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl @@ -36,6 +36,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim incr fcount +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc incr fcount @@ -52,10 +56,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_51 utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView incr fcount -- cgit v1.2.3 From 7977684b907f0e6e963929fe7c43afca3f9c93f8 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 12:57:02 -0700 Subject: Adding in files that probably didn;t exist in the ISE10.1 version of coregen --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise | 30 ++ usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf | 0 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise | 374 ++++++++++++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise | 30 ++ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise | 374 ++++++++++++++++++++++++ 5 files changed, 808 insertions(+) create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise new file mode 100644 index 000000000..c18cf3bf0 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise new file mode 100644 index 000000000..05048a43b --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise @@ -0,0 +1,374 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise new file mode 100644 index 000000000..d0c862319 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise new file mode 100644 index 000000000..d9013a131 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise @@ -0,0 +1,374 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3 From 65b671865ebf8a9541379e794ba624f038524f52 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 13:05:55 -0700 Subject: Edited FIFO instance to delete port that was not regenerated after reconfiguration --- usrp2/extramfifo/ext_fifo.v | 1 - 1 file changed, 1 deletion(-) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index c7e8f6cfb..398e5ef81 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -102,7 +102,6 @@ module ext_fifo .rd_en(dst_rdy_i), .dout(dataout), // Bus [35 : 0] .full(full2), - .almost_full(), .prog_full(almost_full2), .empty(empty2)); assign src_rdy_o = ~empty2; -- cgit v1.2.3 From e5cae33e3c5e9ae1821e06af8bf57bc0444605de Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 14:35:06 -0700 Subject: Regenerated FIFO's for extfifo. There are problems with certain configurations it seems. It is important that the fifo_xlnx_512x36_2clk_18to36 is generated with the "almost_full" pin even though it is not used in the application. if this pin is omitted the FPGA image doesn't work correctly --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf | 0 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo | 1 + usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise | 310 +-------------------- ...12x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso | 3 - ...k_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 102 ------- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc | 4 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco | 4 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise | 310 +-------------------- ...12x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso | 3 - 11 files changed, 15 insertions(+), 726 deletions(-) delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt delete mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf deleted file mode 100644 index e69de29bb..000000000 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc index 657b1aa98..b583362cd 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index f718bb394..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,102 +0,0 @@ - - - - - - -

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- - - diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc index 0ce18d60a..f8afe5bb5 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$5cg4g<,[o}e~g`n;"2*413&;$>"9 > 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diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco index 9f47c073c..cee995891 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -1,7 +1,7 @@ ############################################################## # -# Xilinx Core Generator version K.39 -# Date: Tue Aug 10 23:09:39 2010 +# Xilinx Core Generator version 12.1 +# Date: Thu Aug 12 21:06:13 2010 # ############################################################## # diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise index d9013a131..cfe983130 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise @@ -29,331 +29,29 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 -- cgit v1.2.3 From d4b6fa72eb3fec872a41dea136a5845d3c6ff1ec Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 19 Aug 2010 12:46:04 -0700 Subject: Regenerated FIFO with lower trigger level for almost full flag to reflect logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code. --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 4 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco | 8 +- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise | 4 +- usrp2/extramfifo/ext_fifo.v | 29 +-- usrp2/extramfifo/ext_fifo_tb.v | 70 +++++++- usrp2/extramfifo/nobl_fifo.v | 229 +++--------------------- usrp2/top/u2_rev3/u2_core_udp.v | 3 +- 8 files changed, 113 insertions(+), 236 deletions(-) diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc index b583362cd..608a5f2fb 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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- - + + diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 398e5ef81..c6a64fc65 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -15,8 +15,10 @@ // packed into the IO ring. // + //`define NO_EXT_FIFO + module ext_fifo - #(parameter INT_WIDTH=36,EXT_WIDTH=18,DEPTH=19) + #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) ( input int_clk, input ext_clk, @@ -24,7 +26,7 @@ module ext_fifo input [EXT_WIDTH-1:0] RAM_D_pi, output [EXT_WIDTH-1:0] RAM_D_po, output RAM_D_poe, - output [DEPTH-1:0] RAM_A, + output [RAM_DEPTH-1:0] RAM_A, output RAM_WEn, output RAM_CENn, output RAM_LDn, @@ -59,16 +61,15 @@ module ext_fifo .empty(empty1)); assign dst_rdy_o = ~full1; - -/* -----\/----- EXCLUDED -----\/----- + +`ifdef NO_EXT_FIFO assign space_avail = ~full2; assign data_avail = ~empty1; assign read_data = write_data; - -----/\----- EXCLUDED -----/\----- */ +`else - // External FIFO running at ext clock rate and 18 bit width. - nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH),.FDEPTH(DEPTH)) + nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH)) nobl_fifo_i1 ( .clk(ext_clk), @@ -83,14 +84,14 @@ module ext_fifo .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), .write_data(write_data), - .write_strobe(space_avail & ~empty1 ), + .write_strobe(~empty1 ), .space_avail(space_avail), .read_data(read_data), - .read_strobe(data_avail & ~full2), - .data_avail(data_avail), - .upstream_full(almost_full2) + .read_strobe(~almost_full2), + .data_avail(data_avail) ); - +`endif // !`ifdef NO_EXT_FIFO + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( @@ -98,7 +99,7 @@ module ext_fifo .wr_clk(ext_clk), .rd_clk(int_clk), .din(read_data), // Bus [17 : 0] - .wr_en(data_avail & ~full2 ), + .wr_en(data_avail), .rd_en(dst_rdy_i), .dout(dataout), // Bus [35 : 0] .full(full2), @@ -106,5 +107,5 @@ module ext_fifo .empty(empty2)); assign src_rdy_o = ~empty2; - + endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index a93d524d5..db5f31a9d 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -1,7 +1,8 @@ `timescale 1ns / 1ps `define INT_WIDTH 36 `define EXT_WIDTH 18 -`define DEPTH 19 +`define RAM_DEPTH 19 +`define FIFO_DEPTH 8 `define DUMP_VCD_FULL module ext_fifo_tb(); @@ -17,7 +18,7 @@ module ext_fifo_tb(); wire [`EXT_WIDTH-1:0] RAM_D_po; wire [`EXT_WIDTH-1:0] RAM_D; wire RAM_D_poe; - wire [`DEPTH-1:0] RAM_A; + wire [`RAM_DEPTH-1:0] RAM_A; wire RAM_WEn; wire RAM_CENn; wire RAM_LDn; @@ -30,6 +31,7 @@ module ext_fifo_tb(); reg [`INT_WIDTH-1:0] ref_dataout; wire src_rdy_o; // not EMPTY reg dst_rdy_i; + integer ether_frame; // Clocks @@ -39,7 +41,6 @@ module ext_fifo_tb(); begin int_clk <= 0; ext_clk <= 0; - datain <= 0; ref_dataout <= 1; src_rdy_i <= 0; dst_rdy_i <= 0; @@ -53,6 +54,9 @@ module ext_fifo_tb(); initial begin + datain <= 0; + ether_frame <= 0; + rst <= 1; repeat (5) @(negedge int_clk); rst <= 0; @@ -62,6 +66,18 @@ module ext_fifo_tb(); @(negedge int_clk); datain <= datain + dst_rdy_o; src_rdy_i <= dst_rdy_o; + // Simulate inter-frame time + if (ether_frame == 1500) + begin + ether_frame <= 0; + repeat(1600) + begin + @(negedge int_clk); + src_rdy_i <= 0; + end + end + else + ether_frame <= ether_frame + dst_rdy_o; end end // initial begin @@ -73,8 +89,20 @@ module ext_fifo_tb(); // Fall through fifo, first output already valid if (dataout !== ref_dataout) $display("Error: Expected %x, got %x",ref_dataout, dataout); - - while (ref_dataout < 10000) + // Decimate by 16 rate + while (ref_dataout < 2000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(14) @(negedge int_clk); + end // while (ref_dataout < 10000) + // Decimate by 8 rate + while (ref_dataout < 4000) begin @(negedge int_clk); ref_dataout <= ref_dataout + src_rdy_o ; @@ -84,7 +112,33 @@ module ext_fifo_tb(); @(negedge int_clk); dst_rdy_i <= 0; repeat(6) @(negedge int_clk); - end + end // while (ref_dataout < 10000) + // Decimate by 4 rate + while (ref_dataout < 6000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + @(negedge int_clk); + dst_rdy_i <= 0; + repeat(2) @(negedge int_clk); + end // while (ref_dataout < 10000) + // Max rate + while (ref_dataout < 10000) + begin + @(negedge int_clk); + ref_dataout <= ref_dataout + src_rdy_o ; + dst_rdy_i <= src_rdy_o; + if ((dataout !== ref_dataout) && src_rdy_o) + $display("Error: Expected %x, got %x",ref_dataout, dataout); + + end // while (ref_dataout < 10000) + + @(negedge int_clk); + $finish; + end @@ -228,7 +282,7 @@ module ext_fifo_tb(); endgenerate - wire [`DEPTH-1:0] RAM_A_ext; + wire [`RAM_DEPTH-1:0] RAM_A_ext; wire RAM_WEn_ext,RAM_LDn_ext,RAM_CE1n_ext,RAM_OEn_ext,RAM_CENn_ext; assign #1 RAM_D_pi = RAM_D_pi_ext; @@ -292,7 +346,7 @@ module ext_fifo_tb(); ext_fifo - #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.DEPTH(`DEPTH)) + #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.RAM_DEPTH(`RAM_DEPTH),.FIFO_DEPTH(`FIFO_DEPTH)) ext_fifo_i1 ( .int_clk(int_clk), diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 03e3f5223..19f5fb84e 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -1,18 +1,19 @@ // Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port // device it can only sustain data throughput at half the RAM clock rate. // Fair arbitration to ensure this occurs is included in this logic and -// requests for transactions that can not be completed are held off by (re)using the -// "full" and "empty" flags. +// requests for transactions that can not be completed are held off. +// This FIFO requires a an external signal driving read_strobe that assures space for at least 6 +// reads since this the theopretical maximum number in flight due to pipeling. module nobl_fifo - #(parameter WIDTH=18,DEPTH=19,FDEPTH=10) + #(parameter WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) ( input clk, input rst, input [WIDTH-1:0] RAM_D_pi, output [WIDTH-1:0] RAM_D_po, output RAM_D_poe, - output [DEPTH-1:0] RAM_A, + output [RAM_DEPTH-1:0] RAM_A, output RAM_WEn, output RAM_CENn, output RAM_LDn, @@ -21,42 +22,32 @@ module nobl_fifo input [WIDTH-1:0] write_data, input write_strobe, output reg space_avail, - output reg [WIDTH-1:0] read_data, - input read_strobe, - output reg data_avail, - input upstream_full // (Connect to almost full flag upstream) + output [WIDTH-1:0] read_data, + input read_strobe, // Triggers a read, result in approximately 6 cycles. + output data_avail // Qulaifys read data available this cycle on read_data. ); - reg [FDEPTH-1:0] capacity; - reg [FDEPTH-1:0] wr_pointer; - reg [FDEPTH-1:0] rd_pointer; - wire [DEPTH-1:0] address; - reg supress; - reg data_avail_int; // Data available with high latency from ext FIFO flag - wire [WIDTH-1:0] data_in; - wire data_in_valid; - reg [WIDTH-1:0] read_data_pending; - reg pending_avail; - wire read_strobe_int; + reg [FIFO_DEPTH-1:0] capacity; + reg [FIFO_DEPTH-1:0] wr_pointer; + reg [FIFO_DEPTH-1:0] rd_pointer; + wire [RAM_DEPTH-1:0] address; + reg data_avail_int; // Internal not empty flag. - - - assign read = read_strobe_int && data_avail_int; - assign write = write_strobe && space_avail; + assign read = read_strobe && data_avail_int; + assign write = write_strobe && space_avail; - // When a read and write collision occur, supress the availability flags next cycle + // When a read and write collision occur, supress the space_avail flag next cycle // and complete write followed by read over 2 cycles. This forces balanced arbitration // and makes for a simple logic design. always @(posedge clk) if (rst) begin - capacity <= 1 << (FDEPTH-1); + capacity <= 1 << (FIFO_DEPTH-1); wr_pointer <= 0; rd_pointer <= 0; space_avail <= 0; data_avail_int <= 0; - supress <= 0; end else begin @@ -64,187 +55,15 @@ module nobl_fifo // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == (1 << (FDEPTH-1))) || (read&&write) || ((capacity == ((1 << (FDEPTH-1))-1)) && read) ); - supress <= read && write; + data_avail_int <= ~((capacity == (1 << (FIFO_DEPTH-1))) || ((capacity == ((1 << (FIFO_DEPTH-1))-1)) && read) ); wr_pointer <= wr_pointer + write; - rd_pointer <= rd_pointer + ((~write && read) || supress); - capacity <= capacity - write + ((~write && read) || supress); // REVISIT + rd_pointer <= rd_pointer + (~write && read); + capacity <= capacity - write + (~write && read) ; end // else: !if(rst) assign address = write ? wr_pointer : rd_pointer; - assign enable = write || read || supress; - - // - // Need to have first item in external FIFO moved into local registers for single cycle latency and throughput on read. - // 2 local registers are provided so that a read every other clock cycle can be sustained. - // No fowarding logic is provided to bypass the external FIFO as latency is of no concern. - // - always @(posedge clk) - if (rst) - begin - read_data <= 0; - data_avail <= 0; - read_data_pending <= 0; - pending_avail <= 0; - end - else - begin - case({read_strobe,data_in_valid}) - // No read externally, no new data arriving from external FIFO - 2'b00: begin - case({data_avail,pending_avail}) - // Start Data empty, Pending empty. - // - // End Data full, Pending empty - 2'b00: begin - read_data <= read_data; - data_avail <= data_avail; - read_data_pending <= read_data_pending ; - pending_avail <= pending_avail; - end - // Start Data empty, Pending full. - // Data <= Pending, - // End Data full, Penidng empty. - 2'b01: begin - read_data <= read_data_pending; - data_avail <= 1'b1; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - // Start Data full, Pending empty. - // - // End Data full, Pending empty - 2'b10: begin - read_data <= read_data; - data_avail <= data_avail; - read_data_pending <= read_data_pending ; - pending_avail <= pending_avail; - end - // Start Data full, Pending full. - // - // End Data full, Pending full. - 2'b11: begin - read_data <= read_data; - data_avail <= data_avail; - read_data_pending <= read_data_pending ; - pending_avail <= pending_avail; - end - endcase - end - // No read externally, new data arriving from external FIFO - 2'b01: begin - case({data_avail,pending_avail}) - // Start Data empty, Pending empty. - // Data <= FIFO - // End Data full, Pending empty - 2'b00: begin - read_data <= data_in; - data_avail <= 1'b1; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - // Start Data empty, Pending full. - // Data <= Pending, Pending <= FIFO - // End Data full, Penidng full. - 2'b01: begin - read_data <= read_data_pending; - data_avail <= 1'b1; - read_data_pending <= data_in ; - pending_avail <= 1'b1; - end - // Start Data full, Pending empty. - // Pending <= FIFO - // End Data full, Pending full - 2'b10: begin - read_data <= read_data; - data_avail <= 1'b1; - read_data_pending <= data_in ; - pending_avail <= 1'b1; - end - // Data full, Pending full. - // *ILLEGAL STATE* - 2'b11: begin - - end - endcase - end - // Read externally, no new data arriving from external FIFO - 2'b10: begin - case({data_avail,pending_avail}) - // Start Data empty, Pending empty. - // *ILLEGAL STATE* - 2'b00: begin - - end - // Start Data empty, Pending full. - // *ILLEGAL STATE* - 2'b01: begin - - end - // Start Data full, Pending empty. - // Out <= Data - // End Data empty, Pending empty. - 2'b10: begin - read_data <= read_data; - data_avail <= 1'b0; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - // Start Data full, Pending full. - // Out <= Data, - // End Data full, Pending empty - 2'b11: begin - read_data <= read_data_pending; - data_avail <= 1'b1; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - endcase - end - // Read externally, new data arriving from external FIFO - 2'b11: begin - case({data_avail,pending_avail}) - // Start Data empty, Pending empty. - // *ILLEGAL STATE* - 2'b00: begin - - end - // Start Data empty, Pending full. - // *ILLEGAL STATE* - 2'b01: begin - - end - // Start Data full, Pending empty. - // Out <= Data, Data <= FIFO - // End Data full, Pending empty. - 2'b10: begin - read_data <= data_in; - data_avail <= 1'b1; - read_data_pending <= read_data_pending ; - pending_avail <= 1'b0; - end - // Start Data full, Pending full. - // Out <= Data, Data <= Pending, Pending <= FIFO - // End Data full, Pending full - 2'b11: begin - read_data <= read_data_pending; - data_avail <= 1'b1; - read_data_pending <= data_in ; - pending_avail <= 1'b1; - end - endcase - end - endcase - end + assign enable = write || read; - // Start an external FIFO read as soon as a read of the buffer reg is strobed to minimise refill latency. - // If the buffer reg or the pending buffer reg is already empty also pre-emptively start a read. - // However there must be something in the main external FIFO to read for this to occur!. - // Pay special attention to upstream devices signalling full due to the number of potential in-flight reads\ that need - // to be stalled and stored somewhere. - // This means that there can be 3 outstanding reads to the ext FIFO active at any time helping to hide latency. - assign read_strobe_int = (read_strobe && data_avail && ~pending_avail && ~upstream_full) || (~data_avail && ~pending_avail && ~upstream_full); - // // Simple NoBL SRAM interface, 4 cycle read latency. @@ -265,10 +84,12 @@ module nobl_fifo .RAM_CE1n(RAM_CE1n), .address(address), .data_out(write_data), - .data_in(data_in), - .data_in_valid(data_in_valid), + .data_in(read_data), + .data_in_valid(data_avail), .write(write), .enable(enable) ); + + endmodule // nobl_fifo diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b0c8e6d52..c2811c833 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -648,11 +648,12 @@ module u2_core wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.DEPTH(19)) + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(8)) ext_fifo_i1 ( .int_clk(dsp_clk), .ext_clk(clk_to_mac), +// .ext_clk(wb_clk), .rst(dsp_rst), .RAM_D_pi(RAM_D_pi), .RAM_D_po(RAM_D_po), -- cgit v1.2.3 From 9bfab308d55c2b253f1ec9f0c998ee9920e0468f Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 19 Aug 2010 17:28:07 -0700 Subject: Added a bunch of debug signals. --- usrp2/extramfifo/ext_fifo.v | 14 +++++++++++--- usrp2/extramfifo/ext_fifo_tb.cmd | 1 + usrp2/top/u2_rev3/u2_core_udp.v | 9 +++++---- usrp2/vrt/vita_tx_deframer.v | 4 ++-- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index c6a64fc65..b17fde10b 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -37,7 +37,8 @@ module ext_fifo output dst_rdy_o, // not FULL output [INT_WIDTH-1:0] dataout, output src_rdy_o, // not EMPTY - input dst_rdy_i // READ + input dst_rdy_i, // READ + output reg [31:0] debug ); wire [EXT_WIDTH-1:0] write_data; @@ -46,7 +47,8 @@ module ext_fifo wire almost_full2, full2, empty2; wire [INT_WIDTH-1:0] data_to_fifo; wire [INT_WIDTH-1:0] data_from_fifo; - + wire [FIFO_DEPTH-1:0] capacity; + // FIFO buffers data from UDP engine into external FIFO clock domain. fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( @@ -88,7 +90,8 @@ module ext_fifo .space_avail(space_avail), .read_data(read_data), .read_strobe(~almost_full2), - .data_avail(data_avail) + .data_avail(data_avail), + .capacity(capacity) ); `endif // !`ifdef NO_EXT_FIFO @@ -107,5 +110,10 @@ module ext_fifo .empty(empty2)); assign src_rdy_o = ~empty2; + always @ (posedge int_clk) + debug[31:16] = {12'h0,empty2,full1,dst_rdy_i,src_rdy_i }; + + always @ (posedge ext_clk) + debug[15:0] = {3'h0,empty1,space_avail,data_avail,full2,almost_full2,capacity[7:0] }; endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.cmd b/usrp2/extramfifo/ext_fifo_tb.cmd index b0ab830dc..521f88f21 100644 --- a/usrp2/extramfifo/ext_fifo_tb.cmd +++ b/usrp2/extramfifo/ext_fifo_tb.cmd @@ -1,6 +1,7 @@ /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v -y . -y ../coregen/ +-y ../fifo -y ../models -y /home/ianb/usrp-fpga/usrp2/sdr_lib -y /home/ianb/usrp-fpga/usrp2/control_lib diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index c2811c833..f8ea5330b 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -171,7 +171,7 @@ module u2_core wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -669,7 +669,8 @@ module u2_core .dst_rdy_o(rd1_ready_i), // not FULL .dataout(tx_data), .src_rdy_o(tx_src_rdy), // not EMPTY - .dst_rdy_i(tx_dst_rdy) + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo) ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), @@ -712,8 +713,8 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = 2'b00; - assign debug = 32'd0; + assign debug_clk = {dsp_clk, clk_to_mac}; + assign debug = debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index f9cd7d00d..b62507092 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -84,7 +84,7 @@ module vita_tx_deframer seqnum_err <= 0; end else - if((vita_state == VITA_STORE) & fifo_space) + if((vita_state == VITA_STORE) & fifo_space ) //& src_rdy_i) if(eop) if(has_trailer_reg) vita_state <= VITA_TRAILER; @@ -183,7 +183,7 @@ module vita_tx_deframer 3: sample_d <= data_i[31:0]; endcase // case (vector_phase) - wire store = (vita_state == VITA_STORE); + wire store = (vita_state == VITA_STORE) ; //& src_rdy_i; fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), -- cgit v1.2.3 From 9d4fa0e2980766cafa51f3dc6d1b1a2e257ad58d Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 19 Aug 2010 17:30:31 -0700 Subject: Added capacity to the module pinout --- usrp2/extramfifo/nobl_fifo.v | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 19f5fb84e..cec2a5c4b 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -24,10 +24,11 @@ module nobl_fifo output reg space_avail, output [WIDTH-1:0] read_data, input read_strobe, // Triggers a read, result in approximately 6 cycles. - output data_avail // Qulaifys read data available this cycle on read_data. + output data_avail, // Qulaifys read data available this cycle on read_data. + output reg [FIFO_DEPTH-1:0] capacity ); - reg [FIFO_DEPTH-1:0] capacity; + //reg [FIFO_DEPTH-1:0] capacity; reg [FIFO_DEPTH-1:0] wr_pointer; reg [FIFO_DEPTH-1:0] rd_pointer; wire [RAM_DEPTH-1:0] address; @@ -43,7 +44,7 @@ module nobl_fifo always @(posedge clk) if (rst) begin - capacity <= 1 << (FIFO_DEPTH-1); + capacity <= (1 << FIFO_DEPTH) - 1; wr_pointer <= 0; rd_pointer <= 0; space_avail <= 0; -- cgit v1.2.3 From a782395e91a9d2e22369ca35f74421a91f266060 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 19 Aug 2010 20:25:15 -0700 Subject: capacity logic fix --- usrp2/extramfifo/nobl_fifo.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index cec2a5c4b..62229e6c2 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -56,7 +56,7 @@ module nobl_fifo // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == (1 << (FIFO_DEPTH-1))) || ((capacity == ((1 << (FIFO_DEPTH-1))-1)) && read) ); + data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && read) ); wr_pointer <= wr_pointer + write; rd_pointer <= rd_pointer + (~write && read); capacity <= capacity - write + (~write && read) ; -- cgit v1.2.3 From b4d3dba56fd7dd709ec26b89a2e17002e77b202a Mon Sep 17 00:00:00 2001 From: ianb Date: Wed, 25 Aug 2010 16:32:43 -0700 Subject: Corrected extfifo code so that all registers that are on SRAM signals are packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly --- usrp2/extramfifo/ext_fifo.v | 10 +++++-- usrp2/extramfifo/nobl_fifo.v | 4 +-- usrp2/extramfifo/nobl_if.v | 12 +++++--- usrp2/top/u2_rev3/u2_core_udp.v | 15 ++++++---- usrp2/top/u2_rev3/u2_rev3.ucf | 64 ++++++++++++++++++++--------------------- 5 files changed, 59 insertions(+), 46 deletions(-) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index b17fde10b..2af59a75d 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -38,7 +38,8 @@ module ext_fifo output [INT_WIDTH-1:0] dataout, output src_rdy_o, // not EMPTY input dst_rdy_i, // READ - output reg [31:0] debug + output reg [31:0] debug, + output reg [31:0] debug2 ); wire [EXT_WIDTH-1:0] write_data; @@ -111,9 +112,12 @@ module ext_fifo assign src_rdy_o = ~empty2; always @ (posedge int_clk) - debug[31:16] = {12'h0,empty2,full1,dst_rdy_i,src_rdy_i }; + debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; always @ (posedge ext_clk) - debug[15:0] = {3'h0,empty1,space_avail,data_avail,full2,almost_full2,capacity[7:0] }; + debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; + always@ (posedge ext_clk) +// debug2[31:0] <= {write_data[15:0],read_data[15:0]}; + debug2[31:0] <= 0; endmodule // ext_fifo diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 62229e6c2..4c009d980 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -47,7 +47,7 @@ module nobl_fifo capacity <= (1 << FIFO_DEPTH) - 1; wr_pointer <= 0; rd_pointer <= 0; - space_avail <= 0; + space_avail <= 1; data_avail_int <= 0; end else @@ -56,7 +56,7 @@ module nobl_fifo // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && read) ); + data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read)) ); wr_pointer <= wr_pointer + write; rd_pointer <= rd_pointer + (~write && read); capacity <= capacity - write + (~write && read) ; diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index 24d463b1e..391a841e8 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -9,11 +9,11 @@ module nobl_if output [WIDTH-1:0] RAM_D_po, output reg RAM_D_poe, output [DEPTH-1:0] RAM_A, - output RAM_WEn, + output reg RAM_WEn, output RAM_CENn, output RAM_LDn, output RAM_OEn, - output RAM_CE1n, + output reg RAM_CE1n, input [DEPTH-1:0] address, input [WIDTH-1:0] data_out, output reg [WIDTH-1:0] data_in, @@ -54,11 +54,15 @@ module nobl_if else begin enable_pipe1 <= enable; + RAM_CE1n <= ~enable; // Creates IOB flob + if (enable) begin address_pipe1 <= address; write_pipe1 <= write; + RAM_WEn <= ~write; // Creates IOB flob + if (write) data_out_pipe1 <= data_out; @@ -68,8 +72,8 @@ module nobl_if // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM assign RAM_A = address_pipe1; assign RAM_CENn = 1'b0; - assign RAM_WEn = ~write_pipe1; - assign RAM_CE1n = ~enable_pipe1; + // assign RAM_WEn = ~write_pipe1; +// assign RAM_CE1n = ~enable_pipe1; // // Pipeline stage2 diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index f8ea5330b..38c840bc1 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -171,7 +171,7 @@ module u2_core wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo; + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -414,7 +414,7 @@ module u2_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .gpio(/* {io_tx,io_rx}*/ ) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -664,13 +664,16 @@ module u2_core .RAM_LDn(RAM_LDn), .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), - .datain({rd1_flags,rd1_dat}), +// .datain({rd1_flags,rd1_dat}), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), .src_rdy_i(rd1_ready_o), // WRITE .dst_rdy_o(rd1_ready_i), // not FULL - .dataout(tx_data), +// .dataout(tx_data), + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), .src_rdy_o(tx_src_rdy), // not EMPTY .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo) + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), @@ -717,5 +720,7 @@ module u2_core assign debug = debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; + assign {io_tx,io_rx} = debug_extfifo2; + endmodule // u2_core diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 82d879446..bf9569fe4 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -264,22 +264,22 @@ NET "sdi_tx_adc" LOC = "J4" ; NET "sen_tx_dac" LOC = "H4" ; NET "sclk_tx_dac" LOC = "J5" ; NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" ; -NET "io_tx[1]" LOC = "K3" ; -NET "io_tx[2]" LOC = "G1" ; -NET "io_tx[3]" LOC = "G5" ; -NET "io_tx[4]" LOC = "H5" ; -NET "io_tx[5]" LOC = "F3" ; -NET "io_tx[6]" LOC = "F2" ; -NET "io_tx[7]" LOC = "F5" ; -NET "io_tx[8]" LOC = "G6" ; -NET "io_tx[9]" LOC = "E2" ; -NET "io_tx[10]" LOC = "E1" ; -NET "io_tx[11]" LOC = "E3" ; -NET "io_tx[12]" LOC = "F4" ; -NET "io_tx[13]" LOC = "D2" ; -NET "io_tx[14]" LOC = "D4" ; -NET "io_tx[15]" LOC = "E4" ; +NET "io_tx[0]" LOC = "K4" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[1]" LOC = "K3" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[2]" LOC = "G1" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[3]" LOC = "G5" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[4]" LOC = "H5" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[5]" LOC = "F3" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[6]" LOC = "F2" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[7]" LOC = "F5" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[8]" LOC = "G6" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[9]" LOC = "E2" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[10]" LOC = "E1" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[11]" LOC = "E3" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[12]" LOC = "F4" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[13]" LOC = "D2" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[14]" LOC = "D4" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[15]" LOC = "E4" |DRIVE = 12 |SLEW = FAST ; NET "sen_rx_db" LOC = "D22" ; NET "sclk_rx_db" LOC = "F19" ; NET "sdo_rx_db" LOC = "G20" ; @@ -291,22 +291,22 @@ NET "sdi_rx_adc" LOC = "H22" ; NET "sen_rx_dac" LOC = "J18" ; NET "sclk_rx_dac" LOC = "J19" ; NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" ; -NET "io_rx[1]" LOC = "L20" ; -NET "io_rx[2]" LOC = "L19" ; -NET "io_rx[3]" LOC = "L18" ; -NET "io_rx[4]" LOC = "L17" ; -NET "io_rx[5]" LOC = "K22" ; -NET "io_rx[6]" LOC = "K21" ; -NET "io_rx[7]" LOC = "K20" ; -NET "io_rx[8]" LOC = "G22" ; -NET "io_rx[9]" LOC = "G21" ; -NET "io_rx[10]" LOC = "F21" ; -NET "io_rx[11]" LOC = "F20" ; -NET "io_rx[12]" LOC = "G19" ; -NET "io_rx[13]" LOC = "G18" ; -NET "io_rx[14]" LOC = "G17" ; -NET "io_rx[15]" LOC = "E22" ; +NET "io_rx[0]" LOC = "L21" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[1]" LOC = "L20" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[2]" LOC = "L19" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[3]" LOC = "L18" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[4]" LOC = "L17" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[5]" LOC = "K22" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[6]" LOC = "K21" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[7]" LOC = "K20" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[8]" LOC = "G22" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[9]" LOC = "G21" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[10]" LOC = "F21" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[11]" LOC = "F20" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[12]" LOC = "G19" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[13]" LOC = "G18" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[14]" LOC = "G17" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[15]" LOC = "E22" |DRIVE = 12 |SLEW = FAST ; NET "clk_to_mac" TNM_NET = "clk_to_mac"; TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; -- cgit v1.2.3 From c81569139be394d514994833644ef710be1c886c Mon Sep 17 00:00:00 2001 From: ianb Date: Wed, 25 Aug 2010 18:54:51 -0700 Subject: hangedddddddextrnal fifo size to use full NoBL SRAM --- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 38c840bc1..189c4966f 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -648,7 +648,7 @@ module u2_core wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(8)) + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) ext_fifo_i1 ( .int_clk(dsp_clk), -- cgit v1.2.3 From 0a272630e605b1ba71c0b7c8de9011c047cc578c Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Wed, 1 Sep 2010 00:44:39 -0700 Subject: Enhanced test bench to be more like real world application --- usrp2/extramfifo/ext_fifo_tb.sh | 3 ++- usrp2/extramfifo/ext_fifo_tb.v | 18 ++++++++++++------ 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/usrp2/extramfifo/ext_fifo_tb.sh b/usrp2/extramfifo/ext_fifo_tb.sh index a56574102..dcfede37a 100644 --- a/usrp2/extramfifo/ext_fifo_tb.sh +++ b/usrp2/extramfifo/ext_fifo_tb.sh @@ -1 +1,2 @@ -fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb +#fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb +iverilog -c ext_fifo_tb.cmd -o ext_fifo_tb ext_fifo_tb.v diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index db5f31a9d..0eda89769 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -84,11 +84,17 @@ module ext_fifo_tb(); initial begin - repeat (20) @(negedge int_clk); + repeat (5) @(negedge int_clk); + dst_rdy_i <= 1; + + while (src_rdy_o !== 1) + @(negedge int_clk); // Fall through fifo, first output already valid if (dataout !== ref_dataout) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); + ref_dataout <= ref_dataout + src_rdy_o ; + // Decimate by 16 rate while (ref_dataout < 2000) begin @@ -96,7 +102,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(14) @(negedge int_clk); @@ -108,7 +114,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(6) @(negedge int_clk); @@ -120,7 +126,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(2) @(negedge int_clk); @@ -132,7 +138,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); end // while (ref_dataout < 10000) -- cgit v1.2.3 From 0a28cb5e7fbe81009e50fe03c4ffc3ce8db5052a Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Wed, 1 Sep 2010 03:08:11 -0700 Subject: Added to DCM's and some BUFG's to align the internal 125MHz clock edge with its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet. --- usrp2/top/u2_rev3/u2_core.v | 2 +- usrp2/top/u2_rev3/u2_core_udp.v | 3 +- usrp2/top/u2_rev3/u2_rev3.ucf | 1 + usrp2/top/u2_rev3/u2_rev3.v | 99 ++++++++++++++++++++++++++++++++++++++++- 4 files changed, 100 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 9ba3cc136..a5963f6b1 100755 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -123,7 +123,7 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - output RAM_CLK, + // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 189c4966f..b5d0ed72f 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -125,7 +125,7 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - output RAM_CLK, + // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -705,7 +705,6 @@ module u2_core assign RAM_CLK = clk_to_mac; - // ///////////////////////////////////////////////////////////////////////// // VITA Timing diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index bf9569fe4..175fbec8d 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -324,6 +324,7 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 5e32b368a..cef868df9 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -373,14 +373,109 @@ module u2_rev3 ); end // block: gen_RAM_D_IO endgenerate + + // + // DCM edits start here + // + + + wire RAM_CLK_buf; + wire clk_to_mac_buf; + wire clk125_ext_clk0; + wire clk125_ext_clk180; + wire clk125_ext_clk0_buf; + wire clk125_ext_clk180_buf; + wire clk125_int_buf; + wire clk125_int; + + IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), + .O(clk_to_mac_buf)); + DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(clk125_ext_RST_IN), + .CLK0(clk125_ext_clk0), + .CLK180(clk125_ext_clk180) ); + defparam DCM_INST1.CLK_FEEDBACK = "1X"; + defparam DCM_INST1.CLKDV_DIVIDE = 2.0; + defparam DCM_INST1.CLKFX_DIVIDE = 1; + defparam DCM_INST1.CLKFX_MULTIPLY = 4; + defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST1.CLKIN_PERIOD = 8.000; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST1.FACTORY_JF = 16'h8080; + defparam DCM_INST1.PHASE_SHIFT = 0; + defparam DCM_INST1.STARTUP_WAIT = "FALSE"; + + IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), + .O(RAM_CLK_buf)); + BUFG clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), + .O(clk125_ext_clk0_buf)); + BUFG clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), + .O(clk125_ext_clk180_buf)); + + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk125_ext_clk0_buf), + .C1(clk125_ext_clk180_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + + SRL16 dcm2_rst_i1 (.D(1'b0), + .CLK(clk_to_mac_buf), + .Q(dcm2_rst), + .A0(1'b1), + .A1(1'b1), + .A2(1'b1), + .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i2 is "000F"; + + DCM DCM_INST2 (.CLKFB(clk125_int_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(clk125_int_RST_IN), + .CLK0(clk125_int)); + defparam DCM_INST2.CLK_FEEDBACK = "1X"; + defparam DCM_INST2.CLKDV_DIVIDE = 2.0; + defparam DCM_INST2.CLKFX_DIVIDE = 1; + defparam DCM_INST2.CLKFX_MULTIPLY = 4; + defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST2.CLKIN_PERIOD = 8.000; + defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST2.FACTORY_JF = 16'h8080; + defparam DCM_INST2.PHASE_SHIFT = 0; + defparam DCM_INST2.STARTUP_WAIT = "FALSE"; + + BUFG clk125_int_buf_i1 (.I(clk125_int), + .O(clk125_int_buf)); + + // + // DCM edits end here + // u2_core #(.RAM_SIZE(32768)) u2_core(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), + .clk_to_mac (clk125_int_buf), .pps_in (pps_in), .leds (leds_int), .debug (debug[31:0]), @@ -463,7 +558,7 @@ module u2_rev3 .RAM_A (RAM_A), .RAM_CE1n (RAM_CE1n), .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), + // .RAM_CLK (RAM_CLK), .RAM_WEn (RAM_WEn), .RAM_OEn (RAM_OEn), .RAM_LDn (RAM_LDn), -- cgit v1.2.3 From 60a22a5273b58da49aec5c66f46738be2b7499ba Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Tue, 14 Sep 2010 11:46:58 -0700 Subject: Enabled phase offset adjustment on DCM_INST1 which drives the external Fast SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions. --- usrp2/top/u2_rev3/u2_rev3.v | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index cef868df9..faf35d12f 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -397,7 +397,7 @@ module u2_rev3 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), - .RST(clk125_ext_RST_IN), + .RST(1'b0), .CLK0(clk125_ext_clk0), .CLK180(clk125_ext_clk180) ); defparam DCM_INST1.CLK_FEEDBACK = "1X"; @@ -406,13 +406,13 @@ module u2_rev3 defparam DCM_INST1.CLKFX_MULTIPLY = 4; defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM_INST1.CLKIN_PERIOD = 8.000; - defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = 0; + defparam DCM_INST1.PHASE_SHIFT = -12; defparam DCM_INST1.STARTUP_WAIT = "FALSE"; IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), @@ -431,14 +431,14 @@ module u2_rev3 .R(1'b0), .S(1'b0)); - SRL16 dcm2_rst_i1 (.D(1'b0), - .CLK(clk_to_mac_buf), - .Q(dcm2_rst), - .A0(1'b1), - .A1(1'b1), - .A2(1'b1), - .A3(1'b1)); - // synthesis attribute init of dcm2_rst_i2 is "000F"; +// SRL16 dcm2_rst_i1 (.D(1'b0), +// .CLK(clk_to_mac_buf), +// .Q(dcm2_rst), +// .A0(1'b1), +// .A1(1'b1), +// .A2(1'b1), +// .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i1 is "000F"; DCM DCM_INST2 (.CLKFB(clk125_int_buf), .CLKIN(clk_to_mac_buf), @@ -446,7 +446,7 @@ module u2_rev3 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), - .RST(clk125_int_RST_IN), + .RST(1'b0), .CLK0(clk125_int)); defparam DCM_INST2.CLK_FEEDBACK = "1X"; defparam DCM_INST2.CLKDV_DIVIDE = 2.0; -- cgit v1.2.3 From 84b42223ce7d119ef89ffa4030c904c1b8efc243 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 30 Sep 2010 15:54:03 -0700 Subject: Modified phase shift of DCM1 to -64 which is intended to give more timing margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock. --- usrp2/top/u2_rev3/u2_rev3.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index faf35d12f..4f7f9bf1a 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -412,7 +412,7 @@ module u2_rev3 defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = -12; + defparam DCM_INST1.PHASE_SHIFT = -64; defparam DCM_INST1.STARTUP_WAIT = "FALSE"; IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), -- cgit v1.2.3 From 2261035e69c033b37d9fe784ef8d1150f39f0e47 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 6 Oct 2010 18:15:17 -0700 Subject: reconnect GPIOs, remove debug pins, meets timing now --- usrp2/top/u2_rev3/u2_core_udp.v | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b5d0ed72f..067a75759 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -414,7 +414,7 @@ module u2_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio(/* {io_tx,io_rx}*/ ) ); + .gpio({io_tx,io_rx}) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -715,11 +715,9 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = {dsp_clk, clk_to_mac}; - assign debug = debug_extfifo; + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; - assign {io_tx,io_rx} = debug_extfifo2; - endmodule // u2_core -- cgit v1.2.3 From 8507271de44aadc564354a77c8b9259e24f0d246 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 7 Oct 2010 11:10:00 -0700 Subject: revert unneeded changes and incorrect comments --- usrp2/top/u2_rev3/u2_rev3.ucf | 64 +++++++++++++++++++++---------------------- usrp2/vrt/vita_tx_deframer.v | 4 +-- 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 175fbec8d..6e0caedd5 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -264,22 +264,22 @@ NET "sdi_tx_adc" LOC = "J4" ; NET "sen_tx_dac" LOC = "H4" ; NET "sclk_tx_dac" LOC = "J5" ; NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[1]" LOC = "K3" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[2]" LOC = "G1" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[3]" LOC = "G5" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[4]" LOC = "H5" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[5]" LOC = "F3" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[6]" LOC = "F2" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[7]" LOC = "F5" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[8]" LOC = "G6" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[9]" LOC = "E2" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[10]" LOC = "E1" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[11]" LOC = "E3" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[12]" LOC = "F4" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[13]" LOC = "D2" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[14]" LOC = "D4" |DRIVE = 12 |SLEW = FAST ; -NET "io_tx[15]" LOC = "E4" |DRIVE = 12 |SLEW = FAST ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; NET "sen_rx_db" LOC = "D22" ; NET "sclk_rx_db" LOC = "F19" ; NET "sdo_rx_db" LOC = "G20" ; @@ -291,22 +291,22 @@ NET "sdi_rx_adc" LOC = "H22" ; NET "sen_rx_dac" LOC = "J18" ; NET "sclk_rx_dac" LOC = "J19" ; NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[1]" LOC = "L20" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[2]" LOC = "L19" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[3]" LOC = "L18" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[4]" LOC = "L17" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[5]" LOC = "K22" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[6]" LOC = "K21" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[7]" LOC = "K20" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[8]" LOC = "G22" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[9]" LOC = "G21" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[10]" LOC = "F21" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[11]" LOC = "F20" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[12]" LOC = "G19" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[13]" LOC = "G18" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[14]" LOC = "G17" |DRIVE = 12 |SLEW = FAST ; -NET "io_rx[15]" LOC = "E22" |DRIVE = 12 |SLEW = FAST ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; NET "clk_to_mac" TNM_NET = "clk_to_mac"; TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index b62507092..f9cd7d00d 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -84,7 +84,7 @@ module vita_tx_deframer seqnum_err <= 0; end else - if((vita_state == VITA_STORE) & fifo_space ) //& src_rdy_i) + if((vita_state == VITA_STORE) & fifo_space) if(eop) if(has_trailer_reg) vita_state <= VITA_TRAILER; @@ -183,7 +183,7 @@ module vita_tx_deframer 3: sample_d <= data_i[31:0]; endcase // case (vector_phase) - wire store = (vita_state == VITA_STORE) ; //& src_rdy_i; + wire store = (vita_state == VITA_STORE); fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), -- cgit v1.2.3 From 7e75951d263c00e9f84bdf14d6176680cb3de833 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Fri, 15 Oct 2010 11:37:23 -0700 Subject: Added external RAM FIFO to u2plus. Added code branch to ext_fifo.v using generate that instantiates different input and out fifo's and touched nobl_fifo code so that it works at 18 and 36bit widths. Added 2nd DCM to top level to generate off chip RAMCLK. Added explicit I/O instances to top level for tristate drivers and changed signals to core as needed. Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3 --- usrp2/coregen/Makefile.srcs | 2 + usrp2/coregen/coregen.cgp | 6 +- usrp2/coregen/fifo_xlnx_32x36_2clk.gise | 30 + usrp2/coregen/fifo_xlnx_32x36_2clk.ncf | 0 usrp2/coregen/fifo_xlnx_32x36_2clk.ngc | 3 + usrp2/coregen/fifo_xlnx_32x36_2clk.v | 3839 +++++++++++++++++++++++++ usrp2/coregen/fifo_xlnx_32x36_2clk.veo | 47 + usrp2/coregen/fifo_xlnx_32x36_2clk.xco | 84 + usrp2/coregen/fifo_xlnx_32x36_2clk.xise | 72 + usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt | 12 + usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt | 46 + usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl | 68 + usrp2/extramfifo/ext_fifo.v | 115 +- usrp2/extramfifo/ext_fifo_tb.sh | 0 usrp2/extramfifo/ext_fifo_tb.v | 103 +- usrp2/extramfifo/nobl_fifo.v | 41 +- usrp2/top/u2plus/Makefile | 2 + usrp2/top/u2plus/u2plus.ucf | 8 + usrp2/top/u2plus/u2plus.v | 83 +- usrp2/top/u2plus/u2plus_core.v | 37 +- 20 files changed, 4498 insertions(+), 100 deletions(-) create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk.gise create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk.ncf create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk.ngc create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk.v create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk.veo create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk.xco create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk.xise create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt create mode 100644 usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl mode change 100644 => 100755 usrp2/extramfifo/ext_fifo_tb.sh diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs index a59696d15..f163877a9 100644 --- a/usrp2/coregen/Makefile.srcs +++ b/usrp2/coregen/Makefile.srcs @@ -16,6 +16,8 @@ fifo_xlnx_16x19_2clk.v \ fifo_xlnx_16x19_2clk.xco \ fifo_xlnx_16x40_2clk.v \ fifo_xlnx_16x40_2clk.xco \ +fifo_xlnx_32x36_2clk.v \ +fifo_xlnx_32x36_2clk.xco \ fifo_xlnx_512x36_2clk_36to18.v \ fifo_xlnx_512x36_2clk_36to18.xco \ fifo_xlnx_512x36_2clk_18to36.v \ diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp index 4c9201aff..dd85a7f50 100644 --- a/usrp2/coregen/coregen.cgp +++ b/usrp2/coregen/coregen.cgp @@ -1,4 +1,4 @@ -# Date: Mon Jul 26 21:55:33 2010 +# Date: Fri Oct 15 07:50:19 2010 SET addpads = false SET asysymbol = false @@ -13,10 +13,10 @@ SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 SET removerpms = false -SET simulationfiles = Behavioral +SET simulationfiles = Structural SET speedgrade = -5 SET verilogsim = true SET vhdlsim = false SET workingdirectory = /tmp/ -# CRC: 394da717 +# CRC: 983b9b45 diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.gise b/usrp2/coregen/fifo_xlnx_32x36_2clk.gise new file mode 100644 index 000000000..70ee54054 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf b/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc b/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc new file mode 100644 index 000000000..d1ed419a7 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$56140<,[o}e~g`n;"2*726&;$9,)<>;.vnt*Ydo&lbjbQwloz\77~4>V8h`f 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6202>80q~:>5;296~X39<16>o4;149'711=?<1vqcm50;0xL62?3tdh8<4?:3yK71>7>52zJ00==zfj>86=4={I17<>{ik=>1<73:1>vF<499~jf202909wE=;8:mg1>=838pD>:7;|l`0<<72;qC?964}oa7e?6=:rB8855rnb6a>5<5sA9?46sac5a94?4|@:>37p`l4e83>7}O;=20qcm;e;296~N4<11vbn:i:181M5302weo8>50;0xL62?3tdh9<4?:3yK71>>7>52zJ00==zfj?86=4={I17<>{ik<>1<73:1>vF<499~jf302909wE=;8:mg0>=838pD>:7;|l`1<<72;qC?964}oa6e?6=:rB8855rnb7a>5<5sA9?46sac4a94?4|@:>37p`l5e83>7}O;=20qcm:e;296~N4<11vbn;i:181M5302weo;>50;0xL62?3tdh:<4?:3yK71>7>52zJ00==zfj<86=4={I17<>{ik?>1<7<0;6?uG35:8yke1>3:1>vF<499~jf002909wE=;8:mg3>=838pD>:7;|l`2<<72;qC?964}oa5e?6=:rB8855rnb4a>5<5sA9?46sac7a94?4|@:>37p`l6e83>7}O;=20qcm9e;296~N4<11vbn8i:181M5302weo:>50;0xL62?3tdh;<4?:3yK71>7>52zJ00==zfj=86=4={I17<>{ik>>1<73:1>vF<499~jf102909wE=;8:mg2>=838pD>:7;|l`3<<72;qC?964}oa4e?6=:rB8855rnb5a>5<5sA9?46sac6a94?4|@:>37p`l7e83>7}O;=20qcm8e;296~N4<11vbn9i:181M5302weo5>50;0xL62?3tdh4<4?:3yK71>7>52zJ00==zfj286=4={I17<>{ik1>1<73:1>vF<499~jf>02909wE=;8:mg=>=838pD>:7;|l`<<<72;qC?964}oa;e?6=:rB8855rnb:a>5<5sA9?46sac9a94?4|@:>37p`l8e83>7}O;=20qcm7e;296~N4<11vbll9:182M5302wen=950;3xL62?3tdi<54?:0yK71>51zJ00==zfk:j6=4>{I17<>{ij9h1<7?tH26;?xhe8j0;6:7;|la55<728qC?964}o`25?6=9rB8855rnc31>5<6sA9?46sab0194?7|@:>37p`m1583>4}O;=20qcl>5;295~N4<11vbo?9:182M5302wen<950;3xL62?3tdi=54?:0yK71>51zJ00==zfk;j6=4>{I17<>{ij8h1<7?tH26;?xhe9j0;6:7;|la65<728qC?964}o`15?6=9rB8855rnc01>5<6sA9?46sab3194?7|@:>37p`m2583>4}O;=20qcl=5;295~N4<11vbo<9:182M5302wen?950;3xL62?3tdi>54?:0yK71>51zJ00==zfk8j6=4>{I17<>{ij;h1<7?tH26;?xhe:j0;6:7;|la75<728qC?964}o`05?6=9rB8855rnc11>5<6sA9?46sab2194?7|@:>37p`m3583>4}O;=20qcl<5;295~N4<11vbo=9:182M5302wen>950;3xL62?3tdi?54?:0yK71>51zJ00==zfk9j6=4>{I17<>{ij:h1<7?tH26;?xhe;j0;6:7;|la05<728qC?964}o`75?6=9rB8855rnc61>5<6sA9?46sab5194?7|@:>37p`m4583>4}O;=20qcl;5;295~N4<11vbo:9:182M5302wen9950;3xL62?3tdi854?:0yK71>51zJ00==zfk>j6=4>{I17<>{ij=h1<7?tH26;?xhe:7;|la15<728qC?964}o`65?6=9rB8855rnc71>5<6sA9?46sab4194?7|@:>37p`m5583>4}O;=20qcl:5;295~N4<11vbo;9:182M5302wen8950;3xL62?3tdi954?:0yK71>57>51zJ00==zfk?j6=4>{I17<>{ij:7;|la25<728qC?964}o`55?6=9rB8855rnc41>5<6sA9?46sab7194?7|@:>37p`m6583>4}O;=20qcl95;295~N4<11vbo89:182M5302wen;950;3xL62?3tdi:54?:0yK71>51zJ00==zfk{I17<>{ij?h1<7?tH26;?xhe>j0;6:7;|la35<728qC?964}o`45?6=9rB8855rnc51>5<6sA9?46sab6194?7|@:>37p`m7583>4}O;=20qcl85;295~N4<11vbo99:182M5302wen:950;3xL62?3tdi;54?:0yK71>51zJ00==zfk=j6=4>{I17<>{ij>h1<7?tH26;?xhe?j0;6:7;|la<5<728qC?964}o`;5?6=9rB8855rnc:1>5<6sA9?46sab9194?7|@:>37p`m8583>4}O;=20qcl75;295~N4<11vbo69:182M5302wen5950;3xL62?3tdi454?:0yK71>51zJ00==zfk2j6=4>{I17<>{ij1h1<7?tH26;?xhe0j0;6b290:wE=;8:mf=`=83;pD>:7;|la=5<728qC?964}o`:5?6=9rB8855rnc;1>5<6sA9?46sab8194?7|@:>37p`m9583>4}O;=20qcl65;295~N4<11vbo79:182M5302wen4950;3xL62?3tdi554?:0yK71>51zJ00==zfk3j6=4>{I17<>{ij0h1<7?tH26;?xhe1j0;6l3:1=vF<499~jg?b290:wE=;8:mf<`=83;pD>:7;|lae5<728qC?964}o`b5?6=9rB8855rncc1>5<6sA9?46sab`194?7|@:>37p`ma583>4}O;=20qcln5;295~N4<11vboo9:182M5302wenl950;3xL62?3tdim54?:0yK71>51zJ00==zfkkj6=4>{I17<>{ijhh1<7?tH26;?xheij0;6:7;|laf5<728qC?964}o`a5?6=9rB8855rnc`1>5<6sA9?46sabc194?7|@:>37p`mb583>4}O;=20qclm5;295~N4<11vbol9:182M5302weno950;3xL62?3tdin54?:0yK71>51zJ00==zfkhj6=4>{I17<>{ijkh1<7?tH26;?xhejj0;6:7;|lag5<728qC?964}o``5?6=9rB8855rnca1>5<6sA9?46sabb194?7|@:>37p`mc583>4}O;=20qcll5;295~N4<11vbom9:182M5302wenn950;3xL62?3tdio54?:0yK71>51zJ00==zfkij6=4>{I17<>{ijjh1<7?tH26;?xhekj0;6:7;|la`5<728qC?964}o`g5?6=9rB8855rncf1>5<6sA9?46sabe194?7|@:>37p`md583>4}O;=20qclk5;295~N4<11vboj9:182M5302weni950;3xL62?3tdih54?:0yK71>51zJ00==zfknj6=4>{I17<>{ijmh1<7?tH26;?xhelj0;6:7;|laa5<728qC?964}o`f5?6=9rB8855rncg1>5<6sA9?46sabd194?7|@:>37p`me583>4}O;=20qclj5;295~N4<11vbok9:182M5302wenh950;3xL62?3tdii54?:0yK71>51zJ00==zfkoj6=4>{I17<>{ijlh1<7?tH26;?xhemj0;6:7;|lab5<728qC?964}o`e5?6=9rB8855rncd1>5<6sA9?46sabg194?7|@:>37p`mf583>4}O;=20qcli5;295~N4<11vboh9:182M5302wenk950;3xL62?3tdij54?:0yK71>51zJ00==zfklj6=4>{I17<>{ijoh1<7?tH26;?xhenj0;6:7;|l`45<728qC?964}oa35?6=9rB8855rnb21>5<6sA9?46sac1194?7|@:>37p`l0583>4}O;=20qcm?5;295~N4<11vbn>9:182M5302weo=950;3xL62?3tdh<54?:0yK71>51zJ00==zfj:j6=4>{I17<>{ik9h1<7?tH26;?xhd8j0;6:7;|l`55<728qC?964}oa25?6=9rB8855rnb31>5<6sA9?46sac0194?7|@:>37p`l1583>4}O;=20qcm>5;295~N4<11vbn?9:182M5302weo<950;3xL62?3tdh=54?:0yK71>51zJ00==zfj;j6=4>{I17<>{ik8h1<7?tH26;?xhd9j0;6:7;|l`65<728qC?964}oa15?6=9rB8855rnb01>5<6sA9?46sac3194?7|@:>37p`l2583>4}O;=20qcm=5;295~N4<11vbn<9:182M5302weo?950;3xL62?3tdh>54?:0yK71>51zJ00==zfj8j6=4>{I17<>{ik;h1<7?tH26;?xhd:j0;6:7;|l`75<728qC?964}oa05?6=9rB8855rnb11>5<6sA9?46sac2194?7|@:>37p`l3583>4}O;=20qcm<5;295~N4<11vbn=9:182M5302weo>950;3xL62?3tdh?54?:0yK71>51zJ00==zfj9j6=4>{I17<>{ik:h1<7?tH26;?xhd;j0;6111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ) + ); + LUT3_L #( + .INIT ( 8'h7F )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ) + ); + LUT2_L #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .LO(\BU2/N16 ) + ); + LUT2_L #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .LO(\BU2/N14 ) + ); + INV \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0 ( + .I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ) + ); + INV \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0 ( + .I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ) + ); + LUT4 #( + .INIT ( 16'h2333 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I2(wr_en), + .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]) + ); + LUT4 #( + .INIT ( 16'h9000 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ) + ); + LUT4 #( + .INIT ( 16'h9000 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]) + ); + LUT4 #( + .INIT ( 16'h5450 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105 ( + .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ) + ); + LUT4 #( + .INIT ( 16'h8421 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ) + ); + LUT4 #( + .INIT ( 16'h5450 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107 ( + .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ) + ); + LUT4 #( + .INIT ( 16'hECA0 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ) + ); + LUT4 #( + .INIT ( 16'h8421 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ) + ); + LUT4 #( + .INIT ( 16'h8241 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ) + ); + LUT4 #( + .INIT ( 16'h2333 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ) + ); + LUT3 #( + .INIT ( 8'hA6 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ) + ); + LUT3 #( + .INIT ( 8'hA6 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I3(\BU2/N16 ), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I3(\BU2/N14 ), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ) + ); + LUT3 #( + .INIT ( 8'hA2 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(rd_en), + .O(\BU2/U0/grf.rf/mem/dout_i_not0001 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ) + ); + LUT4 #( + .INIT ( 16'h8E8A )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(rd_en), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ) + ); + LUT4 #( + .INIT ( 16'h40FF )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]) + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ) + ); + LUT3 #( + .INIT ( 8'hF2 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I1(rd_en), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]) + ); + LUT3 #( + .INIT ( 8'h08 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]), + .I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/rstblk/rd_rst_comb1 ( + .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ), + .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ), + .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/rstblk/wr_rst_comb1 ( + .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ), + .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ), + .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb ) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(almost_full) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(full) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]), + .Q(dout_3[0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]), + .Q(dout_3[1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]), + .Q(dout_3[2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]), + .Q(dout_3[3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]), + .Q(dout_3[4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]), + .Q(dout_3[5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]), + .Q(dout_3[6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]), + .Q(dout_3[7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]), + .Q(dout_3[8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]), + .Q(dout_3[9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_10 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]), + .Q(dout_3[10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_11 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]), + .Q(dout_3[11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_12 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]), + .Q(dout_3[12]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_13 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]), + .Q(dout_3[13]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_14 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]), + .Q(dout_3[14]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_15 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]), + .Q(dout_3[15]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_16 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]), + .Q(dout_3[16]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_17 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]), + .Q(dout_3[17]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_18 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]), + .Q(dout_3[18]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_19 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]), + .Q(dout_3[19]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_20 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]), + .Q(dout_3[20]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_21 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]), + .Q(dout_3[21]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_22 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]), + .Q(dout_3[22]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_23 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]), + .Q(dout_3[23]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_24 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]), + .Q(dout_3[24]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_25 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]), + .Q(dout_3[25]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_26 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]), + .Q(dout_3[26]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_27 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]), + .Q(dout_3[27]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_28 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]), + .Q(dout_3[28]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_29 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]), + .Q(dout_3[29]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_30 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]), + .Q(dout_3[30]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_31 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]), + .Q(dout_3[31]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_32 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]), + .Q(dout_3[32]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_33 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]), + .Q(dout_3[33]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_34 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]), + .Q(dout_3[34]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_35 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]), + .Q(dout_3[35]) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[35]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[35]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[34]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[34]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[33]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[32]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[33]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[32]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[31]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[31]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[30]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[29]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[29]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[30]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[28]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[28]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[27]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[27]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[26]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[25]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[26]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[24]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[24]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[25]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[23]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[22]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[23]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[22]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[21]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[21]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[20]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[19]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[19]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[20]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[18]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[18]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[17]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[17]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[16]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[15]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[16]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[15]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[14]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[14]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[13]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[12]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[12]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[13]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[11]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[11]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[10]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[10]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[9]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[8]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[9]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[8]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[7]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[7]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[6]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[5]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[5]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[6]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[4]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[4]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[3]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[3]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[2]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[1]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[2]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[1]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[0]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[0]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_35 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_34 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_33 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_32 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_31 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_30 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_29 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_28 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_27 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_26 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_25 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_24 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_22 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_21 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_20 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_19 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_18 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_17 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_16 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_15 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_14 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_12 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_11 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(prog_full) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0> ( + .CI(\BU2/N1 ), + .DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .S(\BU2/rd_data_count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(empty) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d1 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 ) + ); + FDPE \BU2/U0/grf.rf/rstblk/rd_rst_asreg ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ) + ); + FDPE \BU2/U0/grf.rf/rstblk/wr_rst_asreg ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d2 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d3 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 ) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/RST_FULL_GEN ( + .C(wr_clk), + .CLR(rst), + .D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ), + .Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ) + ); + VCC \BU2/XST_VCC ( + .P(\BU2/N1 ) + ); + GND \BU2/XST_GND ( + .G(\BU2/rd_data_count [0]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.veo b/usrp2/coregen/fifo_xlnx_32x36_2clk.veo new file mode 100644 index 000000000..eb98a2b70 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.veo @@ -0,0 +1,47 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_32x36_2clk YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .almost_full(almost_full), + .empty(empty), + .prog_full(prog_full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.xco b/usrp2/coregen/fifo_xlnx_32x36_2clk.xco new file mode 100644 index 000000000..1cf4c8ba5 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.2 +# Date: Fri Oct 15 07:50:15 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=true +CSET component_name=fifo_xlnx_32x36_2clk +CSET data_count=false +CSET data_count_width=5 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=24 +CSET full_threshold_negate_value=23 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=32 +CSET output_data_width=36 +CSET output_depth=32 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=5 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=5 +# END Parameters +GENERATE +# CRC: 8e84ee7f diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/usrp2/coregen/fifo_xlnx_32x36_2clk.xise new file mode 100644 index 000000000..0c3544a33 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.xise @@ -0,0 +1,72 @@ + + + +

+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt new file mode 100644 index 000000000..b8c69a9f7 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_32x36_2clk.gise +fifo_xlnx_32x36_2clk.ngc +fifo_xlnx_32x36_2clk.v +fifo_xlnx_32x36_2clk.veo +fifo_xlnx_32x36_2clk.xco +fifo_xlnx_32x36_2clk.xise +fifo_xlnx_32x36_2clk_flist.txt +fifo_xlnx_32x36_2clk_readme.txt +fifo_xlnx_32x36_2clk_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt new file mode 100644 index 000000000..8ab5679fd --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt @@ -0,0 +1,46 @@ +The following files were generated for 'fifo_xlnx_32x36_2clk' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_32x36_2clk.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_32x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_32x36_2clk.v: + Unisim Verilog file containing the information required to simulate + the module. + +fifo_xlnx_32x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_32x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_32x36_2clk.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_32x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_32x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_32x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl new file mode 100644 index 000000000..ec9426357 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_32x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_32x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_32x36_2clk +} +# ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_32x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 2af59a75d..2a8d57448 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -18,7 +18,7 @@ //`define NO_EXT_FIFO module ext_fifo - #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) + #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19) ( input int_clk, input ext_clk, @@ -44,34 +44,29 @@ module ext_fifo wire [EXT_WIDTH-1:0] write_data; wire [EXT_WIDTH-1:0] read_data; - wire full1, empty1; - wire almost_full2, full2, empty2; + wire full1, empty1; + wire almost_full2, full2, empty2; wire [INT_WIDTH-1:0] data_to_fifo; wire [INT_WIDTH-1:0] data_from_fifo; wire [FIFO_DEPTH-1:0] capacity; - + wire space_avail; + wire data_avail; + + // These next 2 lines here purely because ICARUS is crap at handling generate statements. + // Empirically this has been determined to make simulations work. + wire read_input_fifo = space_avail & ~empty1; + wire write_output_fifo = data_avail; - // FIFO buffers data from UDP engine into external FIFO clock domain. - fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( - .rst(rst), - .wr_clk(int_clk), - .rd_clk(ext_clk), - .din(datain), // Bus [35 : 0] - .wr_en(src_rdy_i), - .rd_en(space_avail&~empty1), - .dout(write_data), // Bus [17 : 0] - .full(full1), - .empty(empty1)); - - assign dst_rdy_o = ~full1; + assign src_rdy_o = ~empty2; + assign dst_rdy_o = ~full1; `ifdef NO_EXT_FIFO - assign space_avail = ~full2; - assign data_avail = ~empty1; - assign read_data = write_data; + assign space_avail = ~full2; + assign data_avail = ~empty1; + assign read_data = write_data; `else - // External FIFO running at ext clock rate and 18 bit width. + // External FIFO running at ext clock rate and 18 or 36 bit width. nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH)) nobl_fifo_i1 ( @@ -95,22 +90,67 @@ module ext_fifo .capacity(capacity) ); `endif // !`ifdef NO_EXT_FIFO + - - // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. - fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( - .rst(rst), - .wr_clk(ext_clk), - .rd_clk(int_clk), - .din(read_data), // Bus [17 : 0] - .wr_en(data_avail), - .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] - .full(full2), - .prog_full(almost_full2), - .empty(empty2)); - assign src_rdy_o = ~empty2; + generate + if (EXT_WIDTH == 18 && INT_WIDTH == 36) begin: fifo_g1 + // FIFO buffers data from UDP engine into external FIFO clock domain. + fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 ( + .rst(rst), + .wr_clk(int_clk), + .rd_clk(ext_clk), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(read_input_fifo), + .dout(write_data), // Bus [17 : 0] + .full(full1), + .empty(empty1)); + + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. + fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [17 : 0] + .wr_en(write_output_fifo), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .prog_full(almost_full2), + .empty(empty2)); + end // block: fifo_g1 + else if (EXT_WIDTH == 36 && INT_WIDTH == 36) begin: fifo_g1 + // FIFO buffers data from UDP engine into external FIFO clock domain. + fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i1 ( + .rst(rst), + .wr_clk(int_clk), + .rd_clk(ext_clk), + .din(datain), // Bus [35 : 0] + .wr_en(src_rdy_i), + .rd_en(read_input_fifo), + .dout(write_data), // Bus [35 : 0] + .full(full1), + .empty(empty1)); + + // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. + fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [35 : 0] + .wr_en(write_output_fifo), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .empty(empty2), + .prog_full(almost_full2)); + + end + endgenerate + + + always @ (posedge int_clk) debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; @@ -118,6 +158,7 @@ module ext_fifo debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; always@ (posedge ext_clk) -// debug2[31:0] <= {write_data[15:0],read_data[15:0]}; - debug2[31:0] <= 0; + // debug2[31:0] <= {write_data[15:0],read_data[15:0]}; + debug2[31:0] <= 0; + endmodule // ext_fifo diff --git a/usrp2/extramfifo/ext_fifo_tb.sh b/usrp2/extramfifo/ext_fifo_tb.sh old mode 100644 new mode 100755 diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index 0eda89769..5f4e28719 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -1,18 +1,31 @@ `timescale 1ns / 1ps -`define INT_WIDTH 36 -`define EXT_WIDTH 18 -`define RAM_DEPTH 19 -`define FIFO_DEPTH 8 -`define DUMP_VCD_FULL - -module ext_fifo_tb(); +//`define USRP2 +`define USRP2PLUS +`ifdef USRP2 + `define INT_WIDTH 36 + `define EXT_WIDTH 18 + `define RAM_DEPTH 19 + `define FIFO_DEPTH 8 + `define DUMP_VCD_FULL + `define INT_CLK_PERIOD 5 + `define EXT_CLK_PERIOD 4 +`elsif USRP2PLUS + `define INT_WIDTH 36 + `define EXT_WIDTH 36 + `define RAM_DEPTH 18 + `define FIFO_DEPTH 8 + `define DUMP_VCD_FULL + `define INT_CLK_PERIOD 5 + `define EXT_CLK_PERIOD 5 +`endif // `ifdef USRP2 + +module ext_fifo_tb(); + reg int_clk; reg ext_clk; reg rst; - - wire [`EXT_WIDTH-1:0] RAM_D_pi; wire [`EXT_WIDTH-1:0] RAM_D_po; @@ -33,7 +46,6 @@ module ext_fifo_tb(); reg dst_rdy_i; integer ether_frame; - // Clocks // Int clock is 100MHz // Ext clock is 125MHz @@ -47,10 +59,10 @@ module ext_fifo_tb(); end always - #5 int_clk <= ~int_clk; + #(`INT_CLK_PERIOD/2) int_clk <= ~int_clk; always - #4 ext_clk <= ~ext_clk; + #(`EXT_CLK_PERIOD/2) ext_clk <= ~ext_clk; initial begin @@ -270,7 +282,7 @@ module ext_fifo_tb(); // generate - for (i=0;i<18;i=i+1) + for (i=0;i<`EXT_WIDTH;i=i+1) begin : gen_RAM_D_IO IOBUF #( @@ -309,28 +321,53 @@ module ext_fifo_tb(); assign #2 RAM_A_ext = RAM_A; - - idt71v65603s150 idt71v65603s150_i1 - ( - .A(RAM_A_ext[17:0]), - .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) - .bw1_(1'b0), - .bw2_(1'b0), - .bw3_(1'b1), - .bw4_(1'b1), // byte write enables (low) - .ce1_(RAM_CE1n_ext), - .ce2(1'b1), - .ce2_(1'b0), // chip enables - .cen_(RAM_CENn_ext), // clock enable (low) - .clk(ext_clk), // clock - .IO({RAM_D[16:9],RAM_D[7:0]}), - .IOP({RAM_D[17],RAM_D[8]}), // data bus - .lbo_(1'b0), // linear burst order (low) - .oe_(RAM_OEn_ext), // output enable (low) - .r_w_(RAM_WEn_ext) - ); // read (high) / write (low) + generate + if (`EXT_WIDTH==18) begin: ram_tb_g1 + idt71v65603s150 idt71v65603s150_i1 + ( + .A(RAM_A_ext[17:0]), + .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) + .bw1_(1'b0), + .bw2_(1'b0), + .bw3_(1'b1), + .bw4_(1'b1), // byte write enables (low) + .ce1_(RAM_CE1n_ext), + .ce2(1'b1), + .ce2_(1'b0), // chip enables + .cen_(RAM_CENn_ext), // clock enable (low) + .clk(ext_clk), // clock + .IO({RAM_D[16:9],RAM_D[7:0]}), + .IOP({RAM_D[17],RAM_D[8]}), // data bus + .lbo_(1'b0), // linear burst order (low) + .oe_(RAM_OEn_ext), // output enable (low) + .r_w_(RAM_WEn_ext) + ); // read (high) / write (low) + end // block: ram_tb_g1 + else if (`EXT_WIDTH==36) begin: ram_tb_g1 + idt71v65603s150 idt71v65603s150_i1 + ( + .A(RAM_A_ext[17:0]), + .adv_ld_(RAM_LDn_ext), // advance (high) / load (low) + .bw1_(1'b0), + .bw2_(1'b0), + .bw3_(1'b0), + .bw4_(1'b0), // byte write enables (low) + .ce1_(RAM_CE1n_ext), + .ce2(1'b1), + .ce2_(1'b0), // chip enables + .cen_(RAM_CENn_ext), // clock enable (low) + .clk(ext_clk), // clock + .IO(RAM_D[31:0]), + .IOP(RAM_D[35:32]), // data bus + .lbo_(1'b0), // linear burst order (low) + .oe_(RAM_OEn_ext), // output enable (low) + .r_w_(RAM_WEn_ext) + ); // read (high) / write (low) + end // block: ram_tb_g1 + endgenerate + /* -----\/----- EXCLUDED -----\/----- diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 4c009d980..0b63768fc 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -70,26 +70,27 @@ module nobl_fifo // Simple NoBL SRAM interface, 4 cycle read latency. // Read/Write arbitration via temprary application of empty/full flags. // - nobl_if nobl_if_i1 - ( - .clk(clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .address(address), - .data_out(write_data), - .data_in(read_data), - .data_in_valid(data_avail), - .write(write), - .enable(enable) - ); + nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH)) + nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(write_data), + .data_in(read_data), + .data_in_valid(data_avail), + .write(write), + .enable(enable) + ); diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile index 23eb8908e..c38bd3ec1 100644 --- a/usrp2/top/u2plus/Makefile +++ b/usrp2/top/u2plus/Makefile @@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + ################################################## # Project Properties diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index aee9e57bf..3717b3d91 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -414,3 +414,11 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; + +NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; +PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; + +NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; + + diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 90dbe9d55..55b5bd8f4 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -216,7 +216,49 @@ module u2plus BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - + + wire RAM_CLK_buf; + wire clk100_ext; + wire clk100_ext_buf; + + DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), + .CLKIN(clk_fpga), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk100_ext) ); + defparam DCM_INST1.CLK_FEEDBACK = "1X"; + defparam DCM_INST1.CLKDV_DIVIDE = 2.0; + defparam DCM_INST1.CLKFX_DIVIDE = 1; + defparam DCM_INST1.CLKFX_MULTIPLY = 4; + defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST1.CLKIN_PERIOD = 10.000; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; + defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST1.FACTORY_JF = 16'h8080; + defparam DCM_INST1.PHASE_SHIFT = -64; + defparam DCM_INST1.STARTUP_WAIT = "FALSE"; + + IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), + .O(RAM_CLK_buf)); + + BUFG clk100_ext_buf_i1 (.I(clk100_ext), + .O(clk100_ext_buf)); + + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk100_ext_buf), + .C1(~clk100_ext_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + // I2C -- Don't use external transistors for open drain, the FPGA implements this IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); @@ -299,6 +341,36 @@ module u2plus .S(0) // Synchronous preset input ); */ + + + // + // Instantiate IO for Bidirectional bus to SRAM + // + wire [35:0] RAM_D_pi; + wire [35:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + generate + for (i=0;i<36;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + wire [15:0] dac_a_int, dac_b_int; // DAC A and B are swapped in schematic to facilitate clean layout @@ -377,11 +449,12 @@ module u2plus .sen_rx_dac (SEN_RX_DAC), .io_tx (io_tx[15:0]), .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), + .RAM_D_po (RAM_D_po), + .RAM_D_pi (RAM_D_pi), + .RAM_D_poe (RAM_D_poe), .RAM_A (RAM_A), .RAM_CE1n (RAM_CE1n), .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), .RAM_WEn (RAM_WEn), .RAM_OEn (RAM_OEn), .RAM_LDn (RAM_LDn), @@ -398,6 +471,8 @@ module u2plus ); assign RAM_ZZ = 1; - assign RAM_BWn = 4'b1111; + // Byte Writes are qualified by the global write enable + // Always do 36bit operations to extram. + assign RAM_BWn = 4'b0000; endmodule // u2plus diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 4378436a6..9b177390a 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -110,11 +110,12 @@ module u2plus_core inout [15:0] io_rx, // External RAM - inout [35:0] RAM_D, + input [35:0] RAM_D_pi, + output [35:0] RAM_D_po, + output RAM_D_poe, output [20:0] RAM_A, output RAM_CE1n, output RAM_CENn, - output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -606,11 +607,41 @@ module u2plus_core wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; +/* -----\/----- EXCLUDED -----\/----- fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - + -----/\----- EXCLUDED -----/\----- */ + // External and internal clock run at 100MHz for USRP2+ because ext RAM is 36bits wide + // and provides ample bandwidth. + assign RAM_A[20:18] = 3'b0; + + ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) + ext_fifo_i1 + ( + .int_clk(dsp_clk), + .ext_clk(dsp_clk), + .rst(dsp_rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A[17:0]), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .src_rdy_i(rd1_ready_o), // WRITE + .dst_rdy_o(rd1_ready_i), // not FULL + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .src_rdy_o(tx_src_rdy), // not EMPTY + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) + ); + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) vita_tx_chain -- cgit v1.2.3 From aa9643f60e91d00cd7990acde44efad17c2509ed Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Wed, 20 Oct 2010 15:45:44 -0700 Subject: Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by default Derived RAMCLK from 270degree offset of principle core DCM giving theoretical 2.5nS timing advance on RAM_CLK relative to RAM_* signals. --- usrp2/top/u2plus/u2plus.ucf | 8 ++++---- usrp2/top/u2plus/u2plus.v | 22 +++++++++++++++++++--- 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index 3717b3d91..54dfd2a33 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -415,10 +415,10 @@ TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; -NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; -PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; +#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; -NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; -PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; +#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 55b5bd8f4..5396ae6cd 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -1,4 +1,5 @@ `timescale 1ns / 1ps +//`define DCM_FOR_RAMCLK ////////////////////////////////////////////////////////////////////////////////// module u2plus @@ -195,7 +196,7 @@ module u2plus .CLK2X180(), .CLK90(), .CLK180(), - .CLK270(), + .CLK270(clk270_100), .LOCKED(LOCKED_OUT), .PSDONE(), .STATUS()); @@ -216,7 +217,8 @@ module u2plus BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - + +`ifdef DCM_FOR_RAMCLK wire RAM_CLK_buf; wire clk100_ext; wire clk100_ext_buf; @@ -258,7 +260,21 @@ module u2plus .D1(1'b0), .R(1'b0), .S(1'b0)); - + +`else // !`ifdef DCM_FOR_RAMCLK + // assign RAM_CLK = dcm_out; + BUFG clk270_100_buf_i1 (.I(clk270_100), + .O(clk270_100_buf)); + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk270_100_buf), + .C1(~clk270_100_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); +`endif + // I2C -- Don't use external transistors for open drain, the FPGA implements this IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); -- cgit v1.2.3 From ddb380141841b56fa0720915db7f91f5a28f936c Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 21 Oct 2010 10:55:07 -0700 Subject: Defaulted all SRAM pins to LVCMOS25 8mA FAST --- usrp2/top/u2plus/u2plus.ucf | 134 ++++++++++++++++++++++---------------------- 1 file changed, 67 insertions(+), 67 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index 54dfd2a33..25267a67e 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -307,73 +307,73 @@ NET "ser_rkmsb" LOC = "AD25" ; NET "ser_rklsb" LOC = "Y20" ; ## SRAM -NET "RAM_D<35>" LOC = "K16" ; -NET "RAM_D<34>" LOC = "D20" ; -NET "RAM_D<33>" LOC = "C20" ; -NET "RAM_D<32>" LOC = "E21" ; -NET "RAM_D<31>" LOC = "D21" ; -NET "RAM_D<30>" LOC = "C21" ; -NET "RAM_D<29>" LOC = "B21" ; -NET "RAM_D<28>" LOC = "H17" ; -NET "RAM_D<27>" LOC = "G17" ; -NET "RAM_D<26>" LOC = "B23" ; -NET "RAM_D<25>" LOC = "A22" ; -NET "RAM_D<24>" LOC = "D23" ; -NET "RAM_D<23>" LOC = "C23" ; -NET "RAM_D<22>" LOC = "D22" ; -NET "RAM_D<21>" LOC = "C22" ; -NET "RAM_D<20>" LOC = "F19" ; -NET "RAM_D<19>" LOC = "G20" ; -NET "RAM_D<18>" LOC = "F20" ; -NET "RAM_D<17>" LOC = "F7" ; -NET "RAM_D<16>" LOC = "E7" ; -NET "RAM_D<15>" LOC = "G9" ; -NET "RAM_D<14>" LOC = "H9" ; -NET "RAM_D<13>" LOC = "G10" ; -NET "RAM_D<12>" LOC = "H10" ; -NET "RAM_D<11>" LOC = "A4" ; -NET "RAM_D<10>" LOC = "B4" ; -NET "RAM_D<9>" LOC = "C5" ; -NET "RAM_D<8>" LOC = "D6" ; -NET "RAM_D<7>" LOC = "J11" ; -NET "RAM_D<6>" LOC = "K11" ; -NET "RAM_D<5>" LOC = "B7" ; -NET "RAM_D<4>" LOC = "C7" ; -NET "RAM_D<3>" LOC = "B6" ; -NET "RAM_D<2>" LOC = "C6" ; -NET "RAM_D<1>" LOC = "C8" ; -NET "RAM_D<0>" LOC = "D8" ; -NET "RAM_A<0>" LOC = "C11" ; -NET "RAM_A<1>" LOC = "E12" ; -NET "RAM_A<2>" LOC = "F12" ; -NET "RAM_A<3>" LOC = "D13" ; -NET "RAM_A<4>" LOC = "C12" ; -NET "RAM_A<5>" LOC = "A12" ; -NET "RAM_A<6>" LOC = "B12" ; -NET "RAM_A<7>" LOC = "E14" ; -NET "RAM_A<8>" LOC = "F14" ; -NET "RAM_A<9>" LOC = "B15" ; -NET "RAM_A<10>" LOC = "A15" ; -NET "RAM_A<11>" LOC = "D16" ; -NET "RAM_A<12>" LOC = "C15" ; -NET "RAM_A<13>" LOC = "D17" ; -NET "RAM_A<14>" LOC = "C16" ; -NET "RAM_A<15>" LOC = "F15" ; -NET "RAM_A<16>" LOC = "C17" ; -NET "RAM_A<17>" LOC = "B17" ; -NET "RAM_A<18>" LOC = "B18" ; -NET "RAM_A<19>" LOC = "A18" ; -NET "RAM_A<20>" LOC = "D18" ; -NET "RAM_BWn<3>" LOC = "D9" ; -NET "RAM_BWn<2>" LOC = "A9" ; -NET "RAM_BWn<1>" LOC = "B9" ; -NET "RAM_BWn<0>" LOC = "G12" ; -NET "RAM_ZZ" LOC = "J12" ; -NET "RAM_LDn" LOC = "H12" ; -NET "RAM_OEn" LOC = "C10" ; -NET "RAM_WEn" LOC = "D10" ; -NET "RAM_CENn" LOC = "B10" ; -NET "RAM_CLK" LOC = "A10" ; +NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; ## SPI Flash NET "flash_miso" LOC = "AF24" ; -- cgit v1.2.3 From 4e5f4e137e70728116536ac19f1bf946fa890b7d Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Wed, 10 Nov 2010 09:45:12 -0800 Subject: 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZ which allows the SRAM to be placed in a sleep mode. This pin was erroniously pulled high at the top level rendering the SRAM unusable. 2) Added declaration for extramfifo debug bus which had got deleted at some point in the past 3) Created a debug bundle of signals from extsramfifo to help diagnose problem 1) 4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a code change so that control logic does not rely on the presence of this pin and ensuring that the SRAM is always placed in READ mode in any idle cycles. --- usrp2/extramfifo/ext_fifo.v | 12 ++++++------ usrp2/extramfifo/nobl_if.v | 9 ++++++--- usrp2/top/u2plus/u2plus.v | 3 ++- usrp2/top/u2plus/u2plus_core.v | 4 +++- 4 files changed, 17 insertions(+), 11 deletions(-) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 2a8d57448..44229f846 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -46,8 +46,6 @@ module ext_fifo wire [EXT_WIDTH-1:0] read_data; wire full1, empty1; wire almost_full2, full2, empty2; - wire [INT_WIDTH-1:0] data_to_fifo; - wire [INT_WIDTH-1:0] data_from_fifo; wire [FIFO_DEPTH-1:0] capacity; wire space_avail; wire data_avail; @@ -151,12 +149,14 @@ module ext_fifo - always @ (posedge int_clk) - debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; +// always @ (posedge int_clk) +// debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; always @ (posedge ext_clk) - debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; - + // debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; + debug[31:0] <= {7'h0,src_rdy_i,read_input_fifo,write_output_fifo,dst_rdy_i,full2,almost_full2,empty2,full1,empty1,write_data[7:0],read_data[7:0]}; + + always@ (posedge ext_clk) // debug2[31:0] <= {write_data[15:0],read_data[15:0]}; debug2[31:0] <= 0; diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index 391a841e8..7ff7eaa03 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -50,18 +50,21 @@ module nobl_if address_pipe1 <= 0; write_pipe1 <= 0; data_out_pipe1 <= 0; + RAM_WEn <= 1; + RAM_CE1n <= 1; + end else begin enable_pipe1 <= enable; - RAM_CE1n <= ~enable; // Creates IOB flob - + RAM_CE1n <= ~enable; // Creates IOB flop + RAM_WEn <= ~write; // Creates IOB flop if (enable) begin address_pipe1 <= address; write_pipe1 <= write; - RAM_WEn <= ~write; // Creates IOB flob +// RAM_WEn <= ~write; // Creates IOB flop if (write) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 5396ae6cd..d4a681731 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -486,7 +486,8 @@ module u2plus .spiflash_mosi (flash_mosi) ); - assign RAM_ZZ = 1; + // Drive low so that RAM does not sleep. + assign RAM_ZZ = 0; // Byte Writes are qualified by the global write enable // Always do 36bit operations to extram. assign RAM_BWn = 4'b0000; diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 9b177390a..081ffe4c6 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -164,7 +164,9 @@ module u2plus_core wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, + debug_extfifo; + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; -- cgit v1.2.3 From 51d68f095f2341e93232683bd6e3660285478196 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 11 Nov 2010 10:06:36 -0800 Subject: 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable full watermark 2) Put larger FIFO on output of u2plus extramfifo that is compatable with u2_rev3 EMI fixes. --- usrp2/coregen/Makefile.srcs | 2 + usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise | 30 ++++ usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc | 3 + usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v | 173 +++++++++++++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo | 53 +++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco | 84 ++++++++++ usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise | 72 +++++++++ .../fifo_xlnx_512x36_2clk_prog_full_flist.txt | 12 ++ .../fifo_xlnx_512x36_2clk_prog_full_readme.txt | 47 ++++++ .../fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl | 68 ++++++++ usrp2/extramfifo/ext_fifo.v | 22 +-- 11 files changed, 555 insertions(+), 11 deletions(-) create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt create mode 100644 usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs index f163877a9..a3a5d826d 100644 --- a/usrp2/coregen/Makefile.srcs +++ b/usrp2/coregen/Makefile.srcs @@ -22,4 +22,6 @@ fifo_xlnx_512x36_2clk_36to18.v \ fifo_xlnx_512x36_2clk_36to18.xco \ fifo_xlnx_512x36_2clk_18to36.v \ fifo_xlnx_512x36_2clk_18to36.xco \ +fifo_xlnx_512x36_2clk_prog_full.v \ +fifo_xlnx_512x36_2clk_prog_full.xco \ )) diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise new file mode 100644 index 000000000..9abec8c3e --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc new file mode 100644 index 000000000..9cb73d5ce --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v new file mode 100644 index 000000000..6ec1e3f88 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating +// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_prog_full( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + almost_full, + empty, + prog_full); + + +input rst; +input wr_clk; +input rd_clk; +input [35 : 0] din; +input wr_en; +input rd_en; +output [35 : 0] dout; +output full; +output almost_full; +output empty; +output prog_full; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(1), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(500), + .C_PROG_FULL_THRESH_NEGATE_VAL(499), + .C_PROG_FULL_TYPE(1), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .ALMOST_FULL(almost_full), + .EMPTY(empty), + .PROG_FULL(prog_full), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .RD_DATA_COUNT(), + .WR_DATA_COUNT(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo new file mode 100644 index 000000000..64e6769d6 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_prog_full YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .almost_full(almost_full), + .empty(empty), + .prog_full(prog_full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating +// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco new file mode 100644 index 000000000..f99c3c6fb --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.2 +# Date: Thu Nov 11 17:27:10 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=true +CSET component_name=fifo_xlnx_512x36_2clk_prog_full +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=500 +CSET full_threshold_negate_value=499 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: 6b9f6232 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise new file mode 100644 index 000000000..8bf460ac7 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise @@ -0,0 +1,72 @@ + + + +

+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt new file mode 100644 index 000000000..2eb837a3f --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_prog_full.gise +fifo_xlnx_512x36_2clk_prog_full.ngc +fifo_xlnx_512x36_2clk_prog_full.v +fifo_xlnx_512x36_2clk_prog_full.veo +fifo_xlnx_512x36_2clk_prog_full.xco +fifo_xlnx_512x36_2clk_prog_full.xise +fifo_xlnx_512x36_2clk_prog_full_flist.txt +fifo_xlnx_512x36_2clk_prog_full_readme.txt +fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt new file mode 100644 index 000000000..33d50a91d --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt @@ -0,0 +1,47 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_prog_full' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_prog_full.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_prog_full.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_prog_full.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_prog_full.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_prog_full.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_prog_full.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_prog_full_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_512x36_2clk_prog_full_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl new file mode 100644 index 000000000..e1aecccff --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_prog_full_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_prog_full_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_prog_full +} +# ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_prog_full +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 44229f846..daf7140bc 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -132,17 +132,17 @@ module ext_fifo .empty(empty1)); // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. - fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 ( - .rst(rst), - .wr_clk(ext_clk), - .rd_clk(int_clk), - .din(read_data), // Bus [35 : 0] - .wr_en(write_output_fifo), - .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] - .full(full2), - .empty(empty2), - .prog_full(almost_full2)); + fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_32x36_2clk_prog_full_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [35 : 0] + .wr_en(write_output_fifo), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .empty(empty2), + .prog_full(almost_full2)); end endgenerate -- cgit v1.2.3 From 08ace12b12136e002bf283b6ca7af20bdccaab57 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 11 Nov 2010 10:12:43 -0800 Subject: Removed 'ifdef for second DCM that was a deign idea for external SRAM on u2plus. Hardcoded -90 degree clcok from first DCM as final solution --- usrp2/top/u2plus/u2plus.v | 53 ++++------------------------------------------- 1 file changed, 4 insertions(+), 49 deletions(-) diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index d4a681731..270655a8d 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -217,55 +217,11 @@ module u2plus BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - -`ifdef DCM_FOR_RAMCLK - wire RAM_CLK_buf; - wire clk100_ext; - wire clk100_ext_buf; - - DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), - .CLKIN(clk_fpga), - .DSSEN(1'b0), - .PSCLK(1'b0), - .PSEN(1'b0), - .PSINCDEC(1'b0), - .RST(1'b0), - .CLK0(clk100_ext) ); - defparam DCM_INST1.CLK_FEEDBACK = "1X"; - defparam DCM_INST1.CLKDV_DIVIDE = 2.0; - defparam DCM_INST1.CLKFX_DIVIDE = 1; - defparam DCM_INST1.CLKFX_MULTIPLY = 4; - defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST1.CLKIN_PERIOD = 10.000; - defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; - defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = -64; - defparam DCM_INST1.STARTUP_WAIT = "FALSE"; - - IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), - .O(RAM_CLK_buf)); - - BUFG clk100_ext_buf_i1 (.I(clk100_ext), - .O(clk100_ext_buf)); - + + // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. + BUFG clk270_100_buf_i1 (.I(clk270_100), + .O(clk270_100_buf)); OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), - .C0(clk100_ext_buf), - .C1(~clk100_ext_buf), - .CE(1'b1), - .D0(1'b1), - .D1(1'b0), - .R(1'b0), - .S(1'b0)); - -`else // !`ifdef DCM_FOR_RAMCLK - // assign RAM_CLK = dcm_out; - BUFG clk270_100_buf_i1 (.I(clk270_100), - .O(clk270_100_buf)); - OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), .C0(clk270_100_buf), .C1(~clk270_100_buf), .CE(1'b1), @@ -273,7 +229,6 @@ module u2plus .D1(1'b0), .R(1'b0), .S(1'b0)); -`endif // I2C -- Don't use external transistors for open drain, the FPGA implements this IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); -- cgit v1.2.3 From 6ead587793fc9ddeb3daff8725fe8c95bf6abfe7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 11 Nov 2010 13:32:08 -0800 Subject: these got dropped during the rebase --- usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v | 56 ++++++++++++++------------ usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco | 8 ++-- 4 files changed, 37 insertions(+), 31 deletions(-) diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc index 608a5f2fb..d9277b0c3 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc +++ 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v index 6f849b24c..b3d994ae8 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v @@ -23,7 +23,7 @@ * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * -* (c) Copyright 1995-2007 Xilinx, Inc. * +* (c) Copyright 1995-2009 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // The synthesis directives "translate_off/translate_on" specified below are @@ -38,30 +38,30 @@ `timescale 1ns/1ps module fifo_xlnx_512x36_2clk_36to18( - din, - rd_clk, - rd_en, rst, wr_clk, + rd_clk, + din, wr_en, + rd_en, dout, - empty, - full); + full, + empty); -input [35 : 0] din; -input rd_clk; -input rd_en; input rst; input wr_clk; +input rd_clk; +input [35 : 0] din; input wr_en; +input rd_en; output [17 : 0] dout; -output empty; output full; +output empty; // synthesis translate_off - FIFO_GENERATOR_V4_3 #( + FIFO_GENERATOR_V6_1 #( .C_COMMON_CLOCK(0), .C_COUNT_TYPE(0), .C_DATA_COUNT_WIDTH(9), @@ -70,6 +70,8 @@ output full; .C_DOUT_RST_VAL("0"), .C_DOUT_WIDTH(18), .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), .C_FAMILY("spartan3"), .C_FULL_FLAGS_RST_VAL(0), .C_HAS_ALMOST_EMPTY(0), @@ -122,39 +124,41 @@ output full; .C_WR_PNTR_WIDTH(9), .C_WR_RESPONSE_LATENCY(1)) inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), .RST(rst), .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), .WR_EN(wr_en), + .RD_EN(rd_en), .DOUT(dout), - .EMPTY(empty), .FULL(full), - .CLK(), - .INT_CLK(), + .EMPTY(empty), .BACKUP(), .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), .PROG_EMPTY_THRESH(), .PROG_EMPTY_THRESH_ASSERT(), .PROG_EMPTY_THRESH_NEGATE(), .PROG_FULL_THRESH(), .PROG_FULL_THRESH_ASSERT(), .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), .ALMOST_FULL(), - .DATA_COUNT(), + .WR_ACK(), .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), + .ALMOST_EMPTY(), .VALID(), - .RD_DATA_COUNT(), .UNDERFLOW(), - .WR_ACK(), + .DATA_COUNT(), + .RD_DATA_COUNT(), .WR_DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), .SBITERR(), .DBITERR()); diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco index cee995891..d3115e7d5 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco @@ -32,7 +32,7 @@ SET verilogsim = true SET vhdlsim = false # END Project Options # BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 # END Select # BEGIN Parameters CSET almost_empty_flag=false @@ -46,10 +46,13 @@ CSET empty_threshold_assert_value=4 CSET empty_threshold_negate_value=5 CSET enable_ecc=false CSET enable_int_clk=false +CSET enable_reset_synchronization=true CSET fifo_implementation=Independent_Clocks_Block_RAM CSET full_flags_reset_value=0 CSET full_threshold_assert_value=509 CSET full_threshold_negate_value=508 +CSET inject_dbit_error=false +CSET inject_sbit_error=false CSET input_data_width=36 CSET input_depth=512 CSET output_data_width=18 @@ -78,5 +81,4 @@ CSET write_data_count=false CSET write_data_count_width=9 # END Parameters GENERATE -# CRC: b2f58113 - +# CRC: a4e70980 -- cgit v1.2.3 From 4139894fe6d0031897422c46b59746fe6bf0074f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 14:01:33 -0700 Subject: checkpoint in flow control packet generation --- usrp2/vrt/gen_context_pkt.v | 37 +++++++++++++++++------- usrp2/vrt/trigger_context_pkt.v | 52 ++++++++++++++++++++++++++++++++++ usrp2/vrt/vita_tx_chain.v | 28 +++++++++++++------ usrp2/vrt/vita_tx_control.v | 10 +++++-- usrp2/vrt/vita_tx_deframer.v | 62 +++++++++++++++++++++++++++-------------- 5 files changed, 147 insertions(+), 42 deletions(-) create mode 100644 usrp2/vrt/trigger_context_pkt.v diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 780a027ba..f840ec6e1 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -3,10 +3,12 @@ module gen_context_pkt #(parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, - input trigger, output sent, + input trigger, input error, output sent, input [31:0] streamid, input [63:0] vita_time, input [31:0] message, + input [15:0] seqnum0, + input [15:0] seqnum1, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); localparam CTXT_IDLE = 0; @@ -17,17 +19,30 @@ module gen_context_pkt localparam CTXT_TICS = 5; localparam CTXT_TICS2 = 6; localparam CTXT_MESSAGE = 7; - localparam CTXT_DONE = 8; + localparam CTXT_FLOWCTRL = 8; + localparam CTXT_DONE = 9; reg [33:0] data_int; wire src_rdy_int, dst_rdy_int; - wire [3:0] seqno = 0; + reg [3:0] seqno; reg [3:0] ctxt_state; reg [63:0] err_time; + + always @(posedge clk) + if(reset | clear) + stored_message <= 0; + else + if(error) + stored_message <= message; + else if(state == CTXT_FLOWCTRL) + stored_message <= 0; always @(posedge clk) if(reset | clear) - ctxt_state <= CTXT_IDLE; + begin + ctxt_state <= CTXT_IDLE; + seqno <= 0; + end else case(ctxt_state) CTXT_IDLE : @@ -41,9 +56,10 @@ module gen_context_pkt end CTXT_DONE : - if(~trigger) - ctxt_state <= CTXT_IDLE; - + begin + ctxt_state <= CTXT_IDLE; + seqno <= seqno + 4'd1; + end default : if(dst_rdy_int) ctxt_state <= ctxt_state + 1; @@ -53,13 +69,14 @@ module gen_context_pkt always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd24 }; - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd6 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; - CTXT_MESSAGE : data_int <= { 2'b10, message }; + CTXT_MESSAGE : data_int <= { 2'b00, message }; + CTXT_FLOWCTRL : data_int <= { 2'b10, {seqnum1,seqnum0} }; default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) diff --git a/usrp2/vrt/trigger_context_pkt.v b/usrp2/vrt/trigger_context_pkt.v new file mode 100644 index 000000000..51790dfae --- /dev/null +++ b/usrp2/vrt/trigger_context_pkt.v @@ -0,0 +1,52 @@ + + +module trigger_context_pkt + #(parameter BASE=0) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input packet_consumed, output reg trigger); + + wire [23:0] cycles; + wire [15:0] packets; + wire [6:0] dummy1; + wire [14:0] dummy2; + wire enable_timed, enable_consumed; + reg [30:0] cycle_count, packet_count; + + + setting_reg #(.my_addr(BASE_CTRL+X), .at_reset(0)) sr_settings + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_cycle,dummy1,cycles}),.changed()); + + setting_reg #(.my_addr(BASE_CTRL+X), .at_reset(0)) sr_settings + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_consumed,dummy2,packets}),.changed()); + + always @(posedge clk) + if(reset | clear) + cycle_count <= 0; + else + if(trigger) + cycle_count <= 0; + else if(enable_cycle) + cycle_count <= cycle_count + 1; + + always @(posedge clk) + if(reset | clear) + packet_count <= 0; + else + if(trigger) + packet_count <= 0; + else if(packet_consumed & enable_consumed) + packet_count <= packet_count + 1; + + always @(posedge clk) + if(reset | clear) + trigger <= 0; + else + if((cycle_count > cycles)|(packet_count > packets)) + trigger <= 1; + else + trigger <= 0; + +endmodule // trigger_context_pkt diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 662cdca62..12e94b1a8 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -24,9 +24,10 @@ module vita_tx_chain wire trigger, sent; wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire error; + wire error, packet_consumed; wire [31:0] error_code; wire clear_seqnum; + wire [15:0] current_seqnum; assign underrun = error; assign message = error_code; @@ -40,6 +41,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .current_seqnum(current_seqnum), .debug(debug_vtd) ); vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control @@ -47,7 +49,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time),.error(error),.error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run), .strobe(strobe_tx), + .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed), .debug(debug_vtc) ); dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx @@ -59,13 +61,21 @@ module vita_tx_chain generate if(REPORT_ERROR==1) - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt - (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(error), .sent(), - .streamid(streamid), .vita_time(vita_time), .message(message), - .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + begin + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(trigger),.error(error), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .seqnum0(current_seqnum), .seqnum1(16'd0), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .packet_consumed(packet_consumed), .trigger(trigger)); + end endgenerate - - assign debug = debug_vtc | debug_vtd; + + //assign debug = debug_vtc | debug_vtd; + assign debug = { debug_vtd[15:0], current_seqnum }; endmodule // vita_tx_chain diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index d0516bec8..61cd9edb5 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -8,7 +8,8 @@ module vita_tx_control input [63:0] vita_time, output error, output reg [31:0] error_code, - + output reg packet_consumed, + // From vita_tx_deframer input [5+64+16+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, @@ -154,9 +155,14 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - //assign error = (ibs_state == IBS_ERROR_DONE); assign error = send_error; + always @(posedge clk) + if(reset) + packet_consumed <= 0; + else + packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; + assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index f9cd7d00d..f7902e645 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -13,6 +13,8 @@ module vita_tx_deframer output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, + + output [15:0] current_seqnum, // FIFO Levels output [15:0] fifo_occupied, @@ -45,23 +47,29 @@ module vita_tx_deframer reg [1:0] vector_phase; wire line_done; - reg seqnum_err; - reg [3:0] seqnum_reg; - wire [3:0] seqnum = data_i[19:16]; - wire [3:0] next_seqnum = seqnum_reg + 4'd1; + wire [15:0] seqnum = data_i[15:0]; + reg [15:0] seqnum_reg; + wire [15:0] next_seqnum = seqnum_reg + 16'd1; + wire [3:0] vita_seqnum = data_i[19:16]; + reg [3:0] vita_seqnum_reg; + wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; + reg seqnum_err; + + assign curren_seqnum = seqnum_reg; // Output FIFO for packetized data - localparam VITA_HEADER = 0; - localparam VITA_STREAMID = 1; - localparam VITA_CLASSID = 2; - localparam VITA_CLASSID2 = 3; - localparam VITA_SECS = 4; - localparam VITA_TICS = 5; - localparam VITA_TICS2 = 6; - localparam VITA_PAYLOAD = 7; - localparam VITA_STORE = 8; - localparam VITA_TRAILER = 9; - + localparam VITA_TRANS_HEADER = 0; + localparam VITA_HEADER = 1; + localparam VITA_STREAMID = 2; + localparam VITA_CLASSID = 3; + localparam VITA_CLASSID2 = 4; + localparam VITA_SECS = 5; + localparam VITA_TICS = 6; + localparam VITA_TICS2 = 7; + localparam VITA_PAYLOAD = 8; + localparam VITA_STORE = 9; + localparam VITA_TRAILER = 10; + wire [15:0] hdr_len = 2 + has_streamid_reg + has_classid_reg + has_classid_reg + has_secs_reg + has_tics_reg + has_tics_reg + has_trailer_reg; @@ -70,15 +78,22 @@ module vita_tx_deframer always @(posedge clk) if(reset | clear_seqnum) - seqnum_reg <= 4'hF; + begin + seqnum_reg <= 16'hFFFF; + vita_seqnum_reg <= 4'hF; + end else - if((vita_state==VITA_HEADER) & src_rdy_i) - seqnum_reg <= seqnum; + begin + if((vita_state==VITA_TRANS_HEADER) & src_rdy_i) + seqnum_reg <= seqnum; + if((vita_state==VITA_HEADER) & src_rdy_i) + vita_seqnum_reg <= vita_seqnum; + end // else: !if(reset | clear_seqnum) always @(posedge clk) if(reset | clear) begin - vita_state <= VITA_HEADER; + vita_state <= VITA_TRANS_HEADER; {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; seqnum_err <= 0; @@ -97,6 +112,11 @@ module vita_tx_deframer end else if(src_rdy_i) case(vita_state) + VITA_TRANS_HEADER : + begin + seqnum_err <= ~(seqnum == next_seqnum); + vita_state <= VITA_HEADER; + end VITA_HEADER : begin {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} @@ -113,7 +133,7 @@ module vita_tx_deframer vita_state <= VITA_TICS; else vita_state <= VITA_PAYLOAD; - seqnum_err <= ~(seqnum == next_seqnum); + seqnum_err <= seqnum_err | ~(vita_seqnum == next_vita_seqnum); end // case: VITA_HEADER VITA_STREAMID : if(has_classid_reg) @@ -191,7 +211,7 @@ module vita_tx_deframer // sob, eob, has_secs (send_at) ignored on all lines except first assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop, - 12'd0,seqnum_reg,send_time}; + 12'd0,seqnum_reg[3:0],send_time}; assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; -- cgit v1.2.3 From f622553254eab637f3ec7ac2a9c4d6e3345d9a9c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 14:07:26 -0700 Subject: declarations --- usrp2/vrt/gen_context_pkt.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index f840ec6e1..0ea2797ec 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -27,14 +27,15 @@ module gen_context_pkt reg [3:0] seqno; reg [3:0] ctxt_state; reg [63:0] err_time; - + reg [31:0] stored_message; + always @(posedge clk) if(reset | clear) stored_message <= 0; else if(error) stored_message <= message; - else if(state == CTXT_FLOWCTRL) + else if(ctxt_state == CTXT_FLOWCTRL) stored_message <= 0; always @(posedge clk) -- cgit v1.2.3 From d50a17c0df782231caa18ac66c9f0240f0936560 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 14:33:06 -0700 Subject: assign setting reg addresses --- usrp2/vrt/trigger_context_pkt.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/vrt/trigger_context_pkt.v b/usrp2/vrt/trigger_context_pkt.v index 51790dfae..226ec45f2 100644 --- a/usrp2/vrt/trigger_context_pkt.v +++ b/usrp2/vrt/trigger_context_pkt.v @@ -14,11 +14,11 @@ module trigger_context_pkt reg [30:0] cycle_count, packet_count; - setting_reg #(.my_addr(BASE_CTRL+X), .at_reset(0)) sr_settings + setting_reg #(.my_addr(BASE+4), .at_reset(0)) sr_cycles (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_cycle,dummy1,cycles}),.changed()); - setting_reg #(.my_addr(BASE_CTRL+X), .at_reset(0)) sr_settings + setting_reg #(.my_addr(BASE+5), .at_reset(0)) sr_packets (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_consumed,dummy2,packets}),.changed()); -- cgit v1.2.3 From c868b37abecb9676a7efcc5072e4c0938e442905 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 15:17:49 -0700 Subject: add trigger to makefile --- usrp2/vrt/Makefile.srcs | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs index dc4bd8c96..aa1356d82 100644 --- a/usrp2/vrt/Makefile.srcs +++ b/usrp2/vrt/Makefile.srcs @@ -12,4 +12,5 @@ vita_tx_control.v \ vita_tx_deframer.v \ vita_tx_chain.v \ gen_context_pkt.v \ +trigger_context_pkt.v \ )) -- cgit v1.2.3 From 336afd8b8bb6a655b6297f86cffc05d8e46d1a4a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 16:01:42 -0700 Subject: add a fifo to the end of the mux to help in timing. --- usrp2/fifo/fifo36_mux.v | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 92bf13ff9..c6fd40f27 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -20,6 +20,9 @@ module fifo36_mux wire eof0 = data0_i[33]; wire eof1 = data1_i[33]; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + always @(posedge clk) if(reset | clear) state <= MUX_IDLE0; @@ -32,7 +35,7 @@ module fifo36_mux state <= MUX_DATA1; MUX_DATA0 : - if(src0_rdy_i & dst_rdy_i & eof0) + if(src0_rdy_i & dst_rdy_int & eof0) state <= prio ? MUX_IDLE0 : MUX_IDLE1; MUX_IDLE1 : @@ -42,16 +45,20 @@ module fifo36_mux state <= MUX_DATA0; MUX_DATA1 : - if(src1_rdy_i & dst_rdy_i & eof1) + if(src1_rdy_i & dst_rdy_int & eof1) state <= MUX_IDLE0; default : state <= MUX_IDLE0; endcase // case (state) - assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; - assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; - assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; + assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; + assign data_int = (state==MUX_DATA0) ? data0_i : data1_i; + fifo_short #(.WIDTH(36)) mux_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); endmodule // fifo36_demux -- cgit v1.2.3 From c7accc5a2e04c6bb2f620896ef4ba52b8ec56e72 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Oct 2010 18:01:10 -0700 Subject: go to the correct state --- usrp2/vrt/vita_tx_deframer.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index f7902e645..e12747cd5 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -104,7 +104,7 @@ module vita_tx_deframer if(has_trailer_reg) vita_state <= VITA_TRAILER; else - vita_state <= VITA_HEADER; + vita_state <= VITA_TRANS_HEADER; else begin vita_state <= VITA_PAYLOAD; @@ -171,11 +171,11 @@ module vita_tx_deframer else vector_phase <= vector_phase + 1; VITA_TRAILER : - vita_state <= VITA_HEADER; + vita_state <= VITA_TRANS_HEADER; VITA_STORE : ; default : - vita_state <= VITA_HEADER; + vita_state <= VITA_TRANS_HEADER; endcase // case (vita_state) assign line_done = (vector_phase == numchan); -- cgit v1.2.3 From cdcc710b11376bad327cebe89de6004056a18e1a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 10 Oct 2010 23:38:56 -0700 Subject: separated flow control and error reporting on tx path. should work with and without flow control --- usrp2/top/u2_rev3/u2_core_udp.v | 3 ++- usrp2/vrt/gen_context_pkt.v | 4 ++-- usrp2/vrt/vita_tx_chain.v | 50 +++++++++++++++++++++++++++-------------- usrp2/vrt/vita_tx_deframer.v | 11 ++++----- 4 files changed, 43 insertions(+), 25 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 067a75759..a2a5d045e 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -677,7 +677,8 @@ module u2_core ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 0ea2797ec..31c2a53e1 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -3,7 +3,7 @@ module gen_context_pkt #(parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, - input trigger, input error, output sent, + input trigger, output sent, input [31:0] streamid, input [63:0] vita_time, input [31:0] message, @@ -33,7 +33,7 @@ module gen_context_pkt if(reset | clear) stored_message <= 0; else - if(error) + if(trigger) stored_message <= message; else if(ctxt_state == CTXT_FLOWCTRL) stored_message <= 0; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 12e94b1a8..09da377f8 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -3,7 +3,9 @@ module vita_tx_chain #(parameter BASE_CTRL=0, parameter BASE_DSP=0, parameter REPORT_ERROR=0, - parameter PROT_ENG_FLAGS=0) + parameter DO_FLOW_CONTROL=0, + parameter PROT_ENG_FLAGS=0, + parameter USE_TRANS_HEADER=0) (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, @@ -36,7 +38,10 @@ module vita_tx_chain (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed(clear_seqnum)); - vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer + vita_tx_deframer #(.BASE(BASE_CTRL), + .MAXCHAN(MAXCHAN), + .USE_TRANS_HEADER(USE_TRANS_HEADER)) + vita_tx_deframer (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), @@ -59,23 +64,34 @@ module vita_tx_chain .dac_a(dac_a),.dac_b(dac_b), .debug(debug_tx_dsp) ); - generate - if(REPORT_ERROR==1) - begin - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt - (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(trigger),.error(error), .sent(), - .streamid(streamid), .vita_time(vita_time), .message(message), - .seqnum0(current_seqnum), .seqnum1(16'd0), - .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); - trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt - (.clk(clk), .reset(reset), .clear(clear_vita), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .packet_consumed(packet_consumed), .trigger(trigger)); - end - endgenerate + wire [35:0] flow_data, err_data_int; + wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int; + + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(32'd0), + .seqnum0(current_seqnum), .seqnum1(16'd0), + .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy)); + trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .packet_consumed(packet_consumed), .trigger(trigger)); + + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(error & (REPORT_ERROR==1)), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .seqnum0(current_seqnum), .seqnum1(16'd0), + .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); //assign debug = debug_vtc | debug_vtd; assign debug = { debug_vtd[15:0], current_seqnum }; + fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages + (.clk(clk), .reset(reset), .clear(clear_vita), + .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int), + .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + endmodule // vita_tx_chain diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index e12747cd5..c55f43373 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -1,7 +1,8 @@ module vita_tx_deframer #(parameter BASE=0, - parameter MAXCHAN=1) + parameter MAXCHAN=1, + parameter USE_TRANS_HEADER=0) (input clk, input reset, input clear, input clear_seqnum, input set_stb, input [7:0] set_addr, input [31:0] set_data, @@ -93,7 +94,7 @@ module vita_tx_deframer always @(posedge clk) if(reset | clear) begin - vita_state <= VITA_TRANS_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; seqnum_err <= 0; @@ -104,7 +105,7 @@ module vita_tx_deframer if(has_trailer_reg) vita_state <= VITA_TRAILER; else - vita_state <= VITA_TRANS_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; else begin vita_state <= VITA_PAYLOAD; @@ -171,11 +172,11 @@ module vita_tx_deframer else vector_phase <= vector_phase + 1; VITA_TRAILER : - vita_state <= VITA_TRANS_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; VITA_STORE : ; default : - vita_state <= VITA_TRANS_HEADER; + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; endcase // case (vita_state) assign line_done = (vector_phase == numchan); -- cgit v1.2.3 From 709174b5eebcee5130302426be921a4e457165a4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 13:57:17 -0700 Subject: typo which isn't caught by xilinx --- usrp2/vrt/vita_tx_deframer.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index c55f43373..d8575b745 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -56,7 +56,7 @@ module vita_tx_deframer wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; reg seqnum_err; - assign curren_seqnum = seqnum_reg; + assign current_seqnum = seqnum_reg; // Output FIFO for packetized data localparam VITA_TRANS_HEADER = 0; -- cgit v1.2.3 From f39dc8ef3113edaf96000c61f1d481f53bb23bda Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 15:53:24 -0700 Subject: send message on eob to ack the end of transmission --- usrp2/vrt/vita_tx_control.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 61cd9edb5..ed470418b 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -49,6 +49,7 @@ module vita_tx_control localparam IBS_ERROR_DONE = 4; localparam IBS_ERROR_WAIT = 5; + wire [31:0] CODE_EOB_ACK = {seqnum,16'd1}; wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8}; @@ -107,7 +108,11 @@ module vita_tx_control end else if(eop) if(eob) - ibs_state <= IBS_IDLE; + begin + ibs_state <= IBS_ERROR; // Not really an error + error_code <= CODE_EOB_ACK; + send_error <= 1; + end else ibs_state <= IBS_CONT_BURST; -- cgit v1.2.3 From 5c3073e9a8fcf17e2fc0897c1a0380c96216e346 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 16:39:31 -0700 Subject: switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate --- usrp2/vrt/gen_context_pkt.v | 18 ++++++++++-------- usrp2/vrt/vita_tx_chain.v | 2 +- usrp2/vrt/vita_tx_deframer.v | 10 +++++----- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 31c2a53e1..0eb035f3e 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -7,8 +7,8 @@ module gen_context_pkt input [31:0] streamid, input [63:0] vita_time, input [31:0] message, - input [15:0] seqnum0, - input [15:0] seqnum1, + input [31:0] seqnum0, + input [31:0] seqnum1, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); localparam CTXT_IDLE = 0; @@ -19,8 +19,9 @@ module gen_context_pkt localparam CTXT_TICS = 5; localparam CTXT_TICS2 = 6; localparam CTXT_MESSAGE = 7; - localparam CTXT_FLOWCTRL = 8; - localparam CTXT_DONE = 9; + localparam CTXT_FLOWCTRL0 = 8; + localparam CTXT_FLOWCTRL1 = 9; + localparam CTXT_DONE = 10; reg [33:0] data_int; wire src_rdy_int, dst_rdy_int; @@ -35,7 +36,7 @@ module gen_context_pkt else if(trigger) stored_message <= message; - else if(ctxt_state == CTXT_FLOWCTRL) + else if(ctxt_state == CTXT_FLOWCTRL1) stored_message <= 0; always @(posedge clk) @@ -70,14 +71,15 @@ module gen_context_pkt always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd32 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd8 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; CTXT_MESSAGE : data_int <= { 2'b00, message }; - CTXT_FLOWCTRL : data_int <= { 2'b10, {seqnum1,seqnum0} }; + CTXT_FLOWCTRL0 : data_int <= { 2'b00, seqnum0 }; + CTXT_FLOWCTRL1 : data_int <= { 2'b10, seqnum1 }; default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 09da377f8..eee19bebf 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -29,7 +29,7 @@ module vita_tx_chain wire error, packet_consumed; wire [31:0] error_code; wire clear_seqnum; - wire [15:0] current_seqnum; + wire [31:0] current_seqnum; assign underrun = error; assign message = error_code; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index d8575b745..40867cc55 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -15,7 +15,7 @@ module vita_tx_deframer output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, - output [15:0] current_seqnum, + output [31:0] current_seqnum, // FIFO Levels output [15:0] fifo_occupied, @@ -48,9 +48,9 @@ module vita_tx_deframer reg [1:0] vector_phase; wire line_done; - wire [15:0] seqnum = data_i[15:0]; - reg [15:0] seqnum_reg; - wire [15:0] next_seqnum = seqnum_reg + 16'd1; + wire [31:0] seqnum = data_i; + reg [31:0] seqnum_reg; + wire [31:0] next_seqnum = seqnum_reg + 32'd1; wire [3:0] vita_seqnum = data_i[19:16]; reg [3:0] vita_seqnum_reg; wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; @@ -80,7 +80,7 @@ module vita_tx_deframer always @(posedge clk) if(reset | clear_seqnum) begin - seqnum_reg <= 16'hFFFF; + seqnum_reg <= 32'hFFFF_FFFF; vita_seqnum_reg <= 4'hF; end else -- cgit v1.2.3 From 7e973c0b3a3c37df81064ae34641882313f89a6f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 16:40:25 -0700 Subject: increase compatibility number for flow control --- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index a2a5d045e..1e4030f0c 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -427,7 +427,7 @@ module u2_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd2; + localparam compat_num = 32'd3; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), -- cgit v1.2.3 From 9e54a36664edb9c5641959c65f51c81e43e098c2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 16:41:41 -0700 Subject: cleanup for 32 bit seqnum --- usrp2/vrt/vita_tx_chain.v | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index eee19bebf..6cfbdf763 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -71,7 +71,7 @@ module vita_tx_chain (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(32'd0), - .seqnum0(current_seqnum), .seqnum1(16'd0), + .seqnum0(current_seqnum), .seqnum1(32'd0), .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy)); trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt (.clk(clk), .reset(reset), .clear(clear_vita), @@ -82,11 +82,10 @@ module vita_tx_chain (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(error & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), - .seqnum0(current_seqnum), .seqnum1(16'd0), + .seqnum0(current_seqnum), .seqnum1(32'd0), .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); - //assign debug = debug_vtc | debug_vtd; - assign debug = { debug_vtd[15:0], current_seqnum }; + assign debug = debug_vtc | debug_vtd; fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages (.clk(clk), .reset(reset), .clear(clear_vita), -- cgit v1.2.3 From 1304ca07e855843f98e6efda71fde402a3c43d49 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 12 Oct 2010 13:16:35 -0700 Subject: proper triggering for interrupts generated on the dsp_clk --- usrp2/top/u2_rev3/u2_core_udp.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 1e4030f0c..ea4dd314f 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -541,10 +541,17 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Interrupt Controller, Slave #8 + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + assign irq= {{8'b0}, {8'b0}, {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), -- cgit v1.2.3 From 4bac44e009329f6019bb2aec0e181293e049b781 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 12 Oct 2010 23:02:30 -0700 Subject: don't flag an error on eob ack --- usrp2/vrt/vita_tx_chain.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 6cfbdf763..00da4c6e1 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -31,7 +31,7 @@ module vita_tx_chain wire clear_seqnum; wire [31:0] current_seqnum; - assign underrun = error; + assign underrun = error & ~(error_code == 1); assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid -- cgit v1.2.3 From 10427284e0e270a5b5bdc735da09d8fde9040537 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 12 Oct 2010 23:05:47 -0700 Subject: don't clear out following packets on an eob ack --- usrp2/vrt/vita_tx_control.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index ed470418b..936762212 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -109,7 +109,7 @@ module vita_tx_control else if(eop) if(eob) begin - ibs_state <= IBS_ERROR; // Not really an error + ibs_state <= IBS_ERROR_DONE; // Not really an error error_code <= CODE_EOB_ACK; send_error <= 1; end -- cgit v1.2.3 From 7fd21927c3c5d8d95eed7ff66ed1a060c9affad2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 12 Oct 2010 23:21:39 -0700 Subject: now handles frames larger than the vita packet (i.e. with padding) --- usrp2/vrt/vita_tx_deframer.v | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 40867cc55..7fb8e3893 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -70,11 +70,13 @@ module vita_tx_deframer localparam VITA_PAYLOAD = 8; localparam VITA_STORE = 9; localparam VITA_TRAILER = 10; + localparam VITA_DUMP = 11; wire [15:0] hdr_len = 2 + has_streamid_reg + has_classid_reg + has_classid_reg + has_secs_reg + has_tics_reg + has_tics_reg + has_trailer_reg; - wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets? + wire vita_eof = (pkt_len==hdr_len); + wire eop = eof | vita_eof; // FIXME would ignoring eof allow larger VITA packets? wire fifo_space; always @(posedge clk) @@ -101,12 +103,14 @@ module vita_tx_deframer end else if((vita_state == VITA_STORE) & fifo_space) - if(eop) - if(has_trailer_reg) + if(vita_eof) + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; + else if(has_trailer_reg) vita_state <= VITA_TRAILER; else - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; - else + vita_state <= VITA_DUMP; + else begin vita_state <= VITA_PAYLOAD; pkt_len <= pkt_len - 1; @@ -172,7 +176,13 @@ module vita_tx_deframer else vector_phase <= vector_phase + 1; VITA_TRAILER : - vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; + else + vita_state <= VITA_DUMP; + VITA_DUMP : + if(eof) + vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER; VITA_STORE : ; default : -- cgit v1.2.3 From 12c8995014a625aab9a7614d9b146876fbf81268 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 11 Nov 2010 18:44:43 -0800 Subject: fifo randomizer for emi --- usrp2/extramfifo/Makefile.srcs | 1 + usrp2/extramfifo/ext_fifo.v | 11 ++++-- usrp2/extramfifo/ext_fifo_tb.sav | 30 ++++++++++++++++ usrp2/extramfifo/ext_fifo_tb.v | 4 +-- usrp2/extramfifo/refill_randomizer.v | 66 ++++++++++++++++++++++++++++++++++++ 5 files changed, 108 insertions(+), 4 deletions(-) create mode 100644 usrp2/extramfifo/ext_fifo_tb.sav create mode 100644 usrp2/extramfifo/refill_randomizer.v diff --git a/usrp2/extramfifo/Makefile.srcs b/usrp2/extramfifo/Makefile.srcs index 7cd49f4f6..b255ef916 100644 --- a/usrp2/extramfifo/Makefile.srcs +++ b/usrp2/extramfifo/Makefile.srcs @@ -13,4 +13,5 @@ icon.v \ icon.xco \ ila.v \ ila.xco \ +refill_randomizer.v \ )) diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index daf7140bc..80f82fc63 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -45,7 +45,7 @@ module ext_fifo wire [EXT_WIDTH-1:0] write_data; wire [EXT_WIDTH-1:0] read_data; wire full1, empty1; - wire almost_full2, full2, empty2; + wire almost_full2, almost_full2_spread, full2, empty2; wire [FIFO_DEPTH-1:0] capacity; wire space_avail; wire data_avail; @@ -83,7 +83,7 @@ module ext_fifo .write_strobe(~empty1 ), .space_avail(space_avail), .read_data(read_data), - .read_strobe(~almost_full2), + .read_strobe(~almost_full2_spread), .data_avail(data_avail), .capacity(capacity) ); @@ -148,6 +148,13 @@ module ext_fifo endgenerate + refill_randomizer #(.BITS(7)) + refill_randomizer_i1 ( + .clk(ext_clk), + .rst(rst), + .full_in(almost_full2), + .full_out(almost_full2_spread) + ); // always @ (posedge int_clk) // debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; diff --git a/usrp2/extramfifo/ext_fifo_tb.sav b/usrp2/extramfifo/ext_fifo_tb.sav new file mode 100644 index 000000000..a54b40fc5 --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.sav @@ -0,0 +1,30 @@ +[timestart] 0 +[size] 1523 832 +[pos] -1 -1 +*-15.000000 66300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] ext_fifo_tb. +[treeopen] ext_fifo_tb.ext_fifo_i1. +[treeopen] ext_fifo_tb.ext_fifo_i1.nobl_fifo_i1. +@28 +ext_fifo_tb.ext_fifo_i1.src_rdy_i +ext_fifo_tb.ext_fifo_i1.dst_rdy_o +@22 +ext_fifo_tb.ext_fifo_i1.datain[35:0] +@28 +ext_fifo_tb.ext_fifo_i1.src_rdy_o +ext_fifo_tb.ext_fifo_i1.dst_rdy_i +@22 +ext_fifo_tb.ext_fifo_i1.dataout[35:0] +ext_fifo_tb.ext_fifo_i1.RAM_A[17:0] +@28 +ext_fifo_tb.ext_fifo_i1.RAM_WEn +ext_fifo_tb.ext_fifo_i1.RAM_CE1n +@22 +ext_fifo_tb.ext_fifo_i1.RAM_D_pi[35:0] +ext_fifo_tb.ext_fifo_i1.RAM_D_po[35:0] +ext_fifo_tb.ext_fifo_i1.write_data[35:0] +@28 +ext_fifo_tb.ext_fifo_i1.full1 +ext_fifo_tb.ext_fifo_i1.empty1 +@29 +ext_fifo_tb.ext_fifo_i1.space_avail diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index 5f4e28719..395ad2884 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -1,6 +1,6 @@ `timescale 1ns / 1ps -//`define USRP2 -`define USRP2PLUS +`define USRP2 +//`define USRP2PLUS `ifdef USRP2 `define INT_WIDTH 36 diff --git a/usrp2/extramfifo/refill_randomizer.v b/usrp2/extramfifo/refill_randomizer.v new file mode 100644 index 000000000..0b30f4049 --- /dev/null +++ b/usrp2/extramfifo/refill_randomizer.v @@ -0,0 +1,66 @@ +// +// EMI mitigation. +// Process FULL flag from FIFO so that de-assertion +// (FIFO now not FULL) is delayed by a pseudo random +// value, but assertion is passed straight through. +// + + +module refill_randomizer + #(parameter BITS=7) + ( + input clk, + input rst, + input full_in, + output full_out + ); + + wire feedback; + reg full_last; + wire full_deasserts; + reg [6:0] shift_reg; + reg [6:0] count; + reg delayed_fall; + + + always @(posedge clk) + full_last <= full_in; + + assign full_deasserts = full_last & ~full_in; + + // 7 bit LFSR + always @(posedge clk) + if (rst) + shift_reg <= 7'b1; + else + if (full_deasserts) + shift_reg <= {shift_reg[5:0],feedback}; + + assign feedback = ^(shift_reg & 7'h41); + + always @(posedge clk) + if (rst) + begin + count <= 1; + delayed_fall <= 1; + end + else if (full_deasserts) + begin + count <= shift_reg; + delayed_fall <= 1; + end + else if (count == 1) + begin + count <= 1; + delayed_fall <= 0; + end + else + begin + count <= count - 1; + delayed_fall <= 1; + end + + // Full_out goes instantly high if full_in does. However its fall is delayed. + assign full_out = (full_in == 1) || (full_last == 1) || delayed_fall; + +endmodule \ No newline at end of file -- cgit v1.2.3 From 78abd7d98a5dc42aeafa89ed29a3ab8a1f9475f4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 11 Nov 2010 18:50:49 -0800 Subject: gray code address for emi --- usrp2/extramfifo/nobl_if.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index 7ff7eaa03..b5ebe9c6b 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -39,6 +39,12 @@ module nobl_if assign RAM_LDn = 0; // ZBT/NoBL RAM actually manages its own output enables very well. assign RAM_OEn = 0; + + // gray code the address to reduce EMI + wire [DEPTH-1:0] address_gray; + + bin2gray #(.WIDTH(DEPTH)) bin2gray (.bin(address),.gray(address_gray)); + // // Pipeline stage 1 @@ -62,7 +68,7 @@ module nobl_if if (enable) begin - address_pipe1 <= address; + address_pipe1 <= address_gray; write_pipe1 <= write; // RAM_WEn <= ~write; // Creates IOB flop -- cgit v1.2.3 From 823f04cf0046fb61109bd10b8fd41942a7359a06 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 6 Nov 2010 12:18:21 -0700 Subject: added ability to truly clear out the entire rx chain. also removed old style fifo in rx. --- usrp2/top/u2_rev3/u2_core_udp.v | 12 +++++++++--- usrp2/vrt/vita_rx_control.v | 31 +++++++++++++++---------------- usrp2/vrt/vita_rx_framer.v | 13 +++---------- 3 files changed, 27 insertions(+), 29 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index ea4dd314f..ec973df8d 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -624,9 +624,15 @@ module u2_core .debug(debug_rx_dsp) ); wire [31:0] vrc_debug; + wire clear_rx; + setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx)); + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), @@ -636,7 +642,7 @@ module u2_core wire [3:0] vita_state; vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), @@ -644,7 +650,7 @@ module u2_core .debug_rx(vita_state) ); fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 93673d292..ba63181f1 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -25,16 +25,14 @@ module vita_rx_control wire [63:0] new_time; wire [31:0] new_command; - wire sc_pre1, clear_int, clear_reg; + wire sc_pre1; - assign clear_int = clear | clear_reg; - wire [63:0] rcvtime_pre; reg [63:0] rcvtime; wire [28:0] numlines_pre; wire send_imm_pre, chain_pre, reload_pre; reg send_imm, chain, reload; - wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl; + wire read_ctrl, empty_ctrl, write_ctrl; reg sc_pre2; wire [33:0] fifo_line; reg [28:0] lines_left, lines_total; @@ -54,21 +52,22 @@ module vita_rx_control (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(new_time[31:0]),.changed(sc_pre1)); - setting_reg #(.my_addr(BASE+3)) sr_clear - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_reg)); - // FIFO to store commands sent from the settings bus always @(posedge clk) - sc_pre2 <= sc_pre1; + if(reset | clear) + sc_pre2 <= 0; + else + sc_pre2 <= sc_pre1; + assign write_ctrl = sc_pre1 & ~sc_pre2; wire [4:0] command_queue_len; - shortfifo #(.WIDTH(96)) commandfifo - (.clk(clk),.rst(reset),.clear(clear_int), - .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl), + + fifo_short #(.WIDTH(96)) commandfifo + (.clk(clk),.reset(reset),.clear(clear), + .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(), .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}), - .read(read_ctrl), .empty(empty_ctrl), + .src_rdy_o(empty_ctrl), .dst_rdy_i(read_ctrl), .occupied(command_queue_len), .space() ); reg [33:0] pkt_fifo_line; @@ -92,7 +91,7 @@ module vita_rx_control (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD)); fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo - (.clk(clk),.reset(reset),.clear(clear_int), + (.clk(clk),.reset(reset),.clear(clear), .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy), .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i), @@ -107,7 +106,7 @@ module vita_rx_control wire full = ~sample_fifo_in_rdy; always @(posedge clk) - if(reset | clear_int) + if(reset | clear) begin ibs_state <= IBS_IDLE; lines_left <= 0; @@ -185,7 +184,7 @@ module vita_rx_control assign debug_rx = { { ibs_state[2:0], command_queue_len }, { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, full_ctrl, empty_ctrl }, + { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, empty_ctrl }, { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // rx_control diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v index 235817941..1065ce637 100644 --- a/usrp2/vrt/vita_rx_framer.v +++ b/usrp2/vrt/vita_rx_framer.v @@ -57,13 +57,6 @@ module vita_rx_framer wire [15:0] vita_pkt_len = samples_per_packet + 6; //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; - wire clear_reg; - wire clear_int = clear | clear_reg; - - setting_reg #(.my_addr(BASE+3)) sr_clear - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_reg)); - setting_reg #(.my_addr(BASE+4)) sr_header (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(vita_header),.changed()); @@ -102,7 +95,7 @@ module vita_rx_framer localparam VITA_ERR_TRAILER = 15; // Extension context packets have no trailer always @(posedge clk) - if(reset | clear_pkt_count) + if(reset | clear | clear_pkt_count) pkt_count <= 0; else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy) pkt_count <= pkt_count + 1; @@ -135,7 +128,7 @@ module vita_rx_framer endcase // case (vita_state) always @(posedge clk) - if(reset) + if(reset | clear) begin vita_state <= VITA_IDLE; sample_ctr <= 0; @@ -203,7 +196,7 @@ module vita_rx_framer // Short FIFO to buffer between us and the FIFOs outside fifo_short #(.WIDTH(34)) rx_pkt_fifo - (.clk(clk), .reset(reset), .clear(clear_int), + (.clk(clk), .reset(reset), .clear(clear), .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .space(),.occupied(fifo_occupied[4:0]) ); -- cgit v1.2.3 From 587dfe7db4b4749ffedb5e7e3a0a36a83dd90c6a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 7 Nov 2010 11:51:28 -0800 Subject: clear out the vita tx chain and the tx fifo. need to check the fifo reset to make sure it is in the correct clock domain. --- usrp2/top/u2_rev3/u2_core_udp.v | 23 ++++++++++++----------- usrp2/vrt/gen_context_pkt.v | 7 ++++--- usrp2/vrt/vita_tx_chain.v | 8 ++++++-- usrp2/vrt/vita_tx_control.v | 9 ++------- usrp2/vrt/vita_tx_deframer.v | 2 +- 5 files changed, 25 insertions(+), 24 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index ec973df8d..3c31d33a9 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -162,6 +162,7 @@ module u2_core wire ram_loader_done; wire ram_loader_rst, wb_rst, dsp_rst; + assign dsp_rst = wb_rst; wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; @@ -660,14 +661,17 @@ module u2_core wire [35:0] tx_data; wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; + wire clear_tx; + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) ext_fifo_i1 - ( - .int_clk(dsp_clk), + (.int_clk(dsp_clk), .ext_clk(clk_to_mac), -// .ext_clk(wb_clk), - .rst(dsp_rst), + .rst(dsp_rst | clear_tx), .RAM_D_pi(RAM_D_pi), .RAM_D_po(RAM_D_po), .RAM_D_poe(RAM_D_poe), @@ -679,15 +683,14 @@ module u2_core .RAM_CE1n(RAM_CE1n), // .datain({rd1_flags,rd1_dat}), .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), - .src_rdy_i(rd1_ready_o), // WRITE - .dst_rdy_o(rd1_ready_i), // not FULL + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), // .dataout(tx_data), .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), - .src_rdy_o(tx_src_rdy), // not EMPTY + .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy), .debug(debug_extfifo), - .debug2(debug_extfifo2) - ); + .debug2(debug_extfifo2) ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), @@ -702,8 +705,6 @@ module u2_core .underrun(underrun), .run(run_tx), .debug(debug_vt)); - assign dsp_rst = wb_rst; - // /////////////////////////////////////////////////////////////////////////////////// // SERDES diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 0eb035f3e..efc170743 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -38,9 +38,10 @@ module gen_context_pkt stored_message <= message; else if(ctxt_state == CTXT_FLOWCTRL1) stored_message <= 0; - + + // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe always @(posedge clk) - if(reset | clear) + if(reset) begin ctxt_state <= CTXT_IDLE; seqno <= 0; @@ -84,7 +85,7 @@ module gen_context_pkt endcase // case (ctxt_state) fifo_short #(.WIDTH(34)) ctxt_fifo - (.clk(clk), .reset(reset), .clear(clear), + (.clk(clk), .reset(reset), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); assign data_o[35:34] = 2'b00; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 00da4c6e1..21e826f1c 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -33,7 +33,11 @@ module vita_tx_chain assign underrun = error & ~(error_code == 1); assign message = error_code; - + + setting_reg #(.my_addr(BASE_CTRL+1)) sr + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_vita)); + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed(clear_seqnum)); @@ -88,7 +92,7 @@ module vita_tx_chain assign debug = debug_vtc | debug_vtd; fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages - (.clk(clk), .reset(reset), .clear(clear_vita), + (.clk(clk), .reset(reset), .clear(0), // Don't clear this or it could get clogged .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int), .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy), .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 936762212..eb41c54c0 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -58,11 +58,6 @@ module vita_tx_control reg [2:0] ibs_state; - wire clear_state; - setting_reg #(.my_addr(BASE+1)) sr - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_state)); - wire [31:0] error_policy; setting_reg #(.my_addr(BASE+3)) sr_error_policy (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -74,7 +69,7 @@ module vita_tx_control reg send_error; always @(posedge clk) - if(reset | clear_state) + if(reset | clear) begin ibs_state <= IBS_IDLE; send_error <= 0; @@ -163,7 +158,7 @@ module vita_tx_control assign error = send_error; always @(posedge clk) - if(reset) + if(reset | clear) packet_consumed <= 0; else packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 7fb8e3893..7697be367 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -80,7 +80,7 @@ module vita_tx_deframer wire fifo_space; always @(posedge clk) - if(reset | clear_seqnum) + if(reset | clear | clear_seqnum) begin seqnum_reg <= 32'hFFFF_FFFF; vita_seqnum_reg <= 4'hF; -- cgit v1.2.3 From ae0d02442ab892e9800b127d6ba1eed70716bb99 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 7 Nov 2010 14:08:53 -0800 Subject: handle zero-length packets properly --- usrp2/vrt/vita_rx_control.v | 39 ++++++++++++++++---------- usrp2/vrt/vita_rx_framer.v | 25 +++++++++-------- usrp2/vrt/vita_rx_tb.v | 67 ++++++++++++++++++++++++++------------------- 3 files changed, 76 insertions(+), 55 deletions(-) diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index ba63181f1..0769f3a24 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -9,7 +9,7 @@ module vita_rx_control output overrun, // To vita_rx_framer - output [4+64+WIDTH-1:0] sample_fifo_o, + output [5+64+WIDTH-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, @@ -32,7 +32,7 @@ module vita_rx_control wire [28:0] numlines_pre; wire send_imm_pre, chain_pre, reload_pre; reg send_imm, chain, reload; - wire read_ctrl, empty_ctrl, write_ctrl; + wire read_ctrl, not_empty_ctrl, write_ctrl; reg sc_pre2; wire [33:0] fifo_line; reg [28:0] lines_left, lines_total; @@ -62,12 +62,12 @@ module vita_rx_control assign write_ctrl = sc_pre1 & ~sc_pre2; wire [4:0] command_queue_len; - + fifo_short #(.WIDTH(96)) commandfifo (.clk(clk),.reset(reset),.clear(clear), .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(), .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}), - .src_rdy_o(empty_ctrl), .dst_rdy_i(read_ctrl), + .src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl), .occupied(command_queue_len), .space() ); reg [33:0] pkt_fifo_line; @@ -78,19 +78,22 @@ module vita_rx_control localparam IBS_OVERRUN = 4; localparam IBS_BROKENCHAIN = 5; localparam IBS_LATECMD = 6; - - wire signal_cmd_done = (lines_left == 1) & (~chain | (~empty_ctrl & (numlines_pre==0))); + localparam IBS_ZEROLEN = 7; + + wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & (numlines_pre==0))); wire signal_overrun = (ibs_state == IBS_OVERRUN); wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN); wire signal_latecmd = (ibs_state == IBS_LATECMD); + wire signal_zerolen = (ibs_state == IBS_ZEROLEN); // Buffer of samples for while we're writing the packet headers - wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; + wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; wire attempt_sample_write = ((run & strobe) | (ibs_state==IBS_OVERRUN) | - (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD)); + (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD) | + (ibs_state==IBS_ZEROLEN)); - fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo + fifo_short #(.WIDTH(5+64+WIDTH)) rx_sample_fifo (.clk(clk),.reset(reset),.clear(clear), .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy), .dataout(sample_fifo_o), @@ -119,12 +122,15 @@ module vita_rx_control else case(ibs_state) IBS_IDLE : - if(~empty_ctrl) + if(not_empty_ctrl) begin lines_left <= numlines_pre; lines_total <= numlines_pre; rcvtime <= rcvtime_pre; - ibs_state <= IBS_WAITING; + if(numlines_pre == 0) + ibs_state <= IBS_ZEROLEN; + else + ibs_state <= IBS_WAITING; send_imm <= send_imm_pre; chain <= chain_pre; reload <= reload_pre; @@ -144,12 +150,12 @@ module vita_rx_control if(lines_left == 1) if(~chain) ibs_state <= IBS_IDLE; - else if(empty_ctrl & reload) + else if(~not_empty_ctrl & reload) begin ibs_state <= IBS_RUNNING; lines_left <= lines_total; end - else if(empty_ctrl) + else if(~not_empty_ctrl) ibs_state <= IBS_BROKENCHAIN; else begin @@ -174,17 +180,20 @@ module vita_rx_control IBS_BROKENCHAIN : if(sample_fifo_in_rdy) ibs_state <= IBS_IDLE; + IBS_ZEROLEN : + if(sample_fifo_in_rdy) + ibs_state <= IBS_IDLE; endcase // case(ibs_state) assign overrun = (ibs_state == IBS_OVERRUN); assign run = (ibs_state == IBS_RUNNING); assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) - & ~empty_ctrl; + & not_empty_ctrl; assign debug_rx = { { ibs_state[2:0], command_queue_len }, { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, empty_ctrl }, + { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // rx_control diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v index 1065ce637..bce8fe334 100644 --- a/usrp2/vrt/vita_rx_framer.v +++ b/usrp2/vrt/vita_rx_framer.v @@ -11,7 +11,7 @@ module vita_rx_framer output src_rdy_o, // From vita_rx_control - input [4+64+(32*MAXCHAN)-1:0] sample_fifo_i, + input [5+64+(32*MAXCHAN)-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, output sample_fifo_dst_rdy_o, @@ -23,11 +23,11 @@ module vita_rx_framer output [31:0] debug_rx ); - localparam SAMP_WIDTH = 4+64+(32*MAXCHAN); + localparam SAMP_WIDTH = 5+64+(32*MAXCHAN); reg [3:0] sample_phase; wire [3:0] numchan; - wire [3:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4]; - wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68]; + wire [4:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-5]; + wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-6:SAMP_WIDTH-69]; reg [31:0] data_fifo_o; @@ -55,7 +55,7 @@ module vita_rx_framer reg [3:0] pkt_count; wire [15:0] vita_pkt_len = samples_per_packet + 6; - //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; + //wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; setting_reg #(.my_addr(BASE+4)) sr_header (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), @@ -69,11 +69,11 @@ module vita_rx_framer (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(vita_trailer),.changed()); - setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt + setting_reg #(.my_addr(BASE+7),.width(16)) sr_samples_per_pkt (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(samples_per_packet),.changed()); - setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan + setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(1)) sr_numchan (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(numchan),.changed()); @@ -107,7 +107,8 @@ module vita_rx_framer always @* case(vita_state) // Data packets are IF Data packets with or w/o streamid, no classid, with trailer - VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:20],pkt_count,vita_pkt_len}; + VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:24], + vita_header[23:20],pkt_count[3:0],vita_pkt_len[15:0]}; VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid}; VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; VITA_TICS : pkt_fifo_line <= {2'b00,32'd0}; @@ -121,7 +122,7 @@ module vita_rx_framer VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0}; VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]}; - VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o}; + VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,27'd0,flags_fifo_o}; //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer}; default : pkt_fifo_line <= 34'h0_FFFF_FFFF; @@ -140,7 +141,7 @@ module vita_rx_framer sample_ctr <= 1; sample_phase <= 0; if(sample_fifo_src_rdy_i) - if(|flags_fifo_o[3:1]) + if(|flags_fifo_o[4:1]) vita_state <= VITA_ERR_HEADER; else vita_state <= VITA_HEADER; @@ -185,7 +186,7 @@ module vita_rx_framer req_write_pkt_fifo <= 1; VITA_PAYLOAD : // Write if sample ready and no error flags - req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]); + req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[4:1]); VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD : req_write_pkt_fifo <= 1; default : @@ -205,7 +206,7 @@ module vita_rx_framer assign sample_fifo_dst_rdy_o = pkt_fifo_rdy & ( ((vita_state==VITA_PAYLOAD) & (sample_phase == (numchan-4'd1)) & - ~|flags_fifo_o[3:1]) | + ~|flags_fifo_o[4:1]) | (vita_state==VITA_ERR_PAYLOAD)); assign debug_rx = vita_state; diff --git a/usrp2/vrt/vita_rx_tb.v b/usrp2/vrt/vita_rx_tb.v index 3e01e2ee2..023934f39 100644 --- a/usrp2/vrt/vita_rx_tb.v +++ b/usrp2/vrt/vita_rx_tb.v @@ -37,7 +37,7 @@ module vita_rx_tb; wire sample_dst_rdy, sample_src_rdy; //wire [99:0] sample_data_o; - wire [64+4+(MAXCHAN*32)-1:0] sample_data_o; + wire [64+5+(MAXCHAN*32)-1:0] sample_data_o; vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control (.clk(clk), .reset(reset), .clear(0), @@ -92,58 +92,68 @@ module vita_rx_tb; begin @(negedge reset); @(posedge clk); - write_setting(4,32'hDEADBEEF); // VITA header + write_setting(4,32'h15F00000); // VITA header write_setting(5,32'hF00D1234); // VITA streamid - write_setting(6,32'hF0000000); // VITA trailer + write_setting(6,32'hE0000000); // VITA trailer write_setting(7,8); // Samples per VITA packet - write_setting(8,NUMCHAN); // Samples per VITA packet - queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet - queue_rx_cmd(1,0,16,32'h0,32'h0); // send imm, 2 packets worth - queue_rx_cmd(1,0,7,32'h0,32'h0); // send imm, 1 short packet worth - queue_rx_cmd(1,0,9,32'h0,32'h0); // send imm, just longer than 1 packet + write_setting(8,NUMCHAN); // Vector length + + queue_rx_cmd(1,1,0,10,32'h0,32'h0); // send imm, single packet + #10000; + + queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet + //queue_rx_cmd(1,1,0,0,32'h0,32'h0); // send imm, single packet + + //queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet + + /* + queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet + queue_rx_cmd(1,0,0,16,32'h0,32'h0); // send imm, 2 packets worth + queue_rx_cmd(1,0,0,7,32'h0,32'h0); // send imm, 1 short packet worth + queue_rx_cmd(1,0,0,9,32'h0,32'h0); // send imm, just longer than 1 packet - queue_rx_cmd(1,1,16,32'h0,32'h0); // chained - queue_rx_cmd(0,0,8,32'h0,32'h0); // 2nd in chain + queue_rx_cmd(1,1,0,16,32'h0,32'h0); // chained + queue_rx_cmd(0,0,0,8,32'h0,32'h0); // 2nd in chain - queue_rx_cmd(1,1,17,32'h0,32'h0); // chained, odd length - queue_rx_cmd(0,0,9,32'h0,32'h0); // 2nd in chain, also odd length + queue_rx_cmd(1,1,0,17,32'h0,32'h0); // chained, odd length + queue_rx_cmd(0,0,0,9,32'h0,32'h0); // 2nd in chain, also odd length - queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time - queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late + queue_rx_cmd(0,0,0,8,32'h0,32'h340); // send at, on time + queue_rx_cmd(0,0,0,8,32'h0,32'h100); // send at, but late #100000; $display("\nChained, break chain\n"); - queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain + queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained, but break chain #100000; $display("\nSingle packet\n"); - queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet + queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet #100000; $display("\nEnd chain with zero samples, shouldn't error\n"); - queue_rx_cmd(1,1,8,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error + queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained + queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error #100000; $display("\nEnd chain with zero samples on odd-length, shouldn't error\n"); - queue_rx_cmd(1,1,14,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error + queue_rx_cmd(1,1,0,14,32'h0,32'h0); // chained + queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error #100000; $display("Should have gotten 14 samples and EOF by now\n"); - queue_rx_cmd(1,1,9,32'h0,32'h0); // chained, but break chain, odd length + queue_rx_cmd(1,1,0,9,32'h0,32'h0); // chained, but break chain, odd length #100000; dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,0,100,32'h0,32'h0); // long enough to fill the fifos - queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent + queue_rx_cmd(1,0,0,100,32'h0,32'h0); // long enough to fill the fifos + queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent #100000; dst_rdy <= 1; // restart the reads so we can see what we got #100000; dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,1,100,32'h0,32'h0); // long enough to fill the fifos - //queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent + queue_rx_cmd(1,1,0,100,32'h0,32'h0); // long enough to fill the fifos + //queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent #100000; @(posedge clk); dst_rdy <= 1; - + */ #100000 $finish; end @@ -164,11 +174,12 @@ module vita_rx_tb; task queue_rx_cmd; input send_imm; input chain; - input [29:0] lines; + input reload; + input [28:0] lines; input [31:0] secs; input [31:0] tics; begin - write_setting(0,{send_imm,chain,lines}); + write_setting(0,{send_imm,chain,reload,lines}); write_setting(1,secs); write_setting(2,tics); end -- cgit v1.2.3 From a78ace9e161a0fc30a6cc6de38b9eea45230a4b6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 7 Nov 2010 14:32:01 -0800 Subject: compiles with new file locations --- usrp2/vrt/vita_tx.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_tx.build b/usrp2/vrt/vita_tx.build index 902929c08..e7106aa10 100755 --- a/usrp2/vrt/vita_tx.build +++ b/usrp2/vrt/vita_tx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v +iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v -- cgit v1.2.3 From 048dd370496dd128f7d12ac5c40426490c5d6233 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 7 Nov 2010 14:32:35 -0800 Subject: reset properly --- usrp2/vrt/vita_tx_control.v | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index eb41c54c0..967847d36 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -73,6 +73,7 @@ module vita_tx_control begin ibs_state <= IBS_IDLE; send_error <= 0; + error_code <= 0; end else case(ibs_state) -- cgit v1.2.3 From ee48c9abebf25d42301d19767e876405a3b533bb Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 11 Nov 2010 19:21:36 -0800 Subject: Add flow control and other small vrt fixes to u2p, minor cleanups --- usrp2/top/u2_rev3/u2_core_udp.v | 5 +-- usrp2/top/u2plus/u2plus_core.v | 67 +++++++++++++++++++++++------------------ 2 files changed, 38 insertions(+), 34 deletions(-) diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 3c31d33a9..9e62ee1cc 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -125,7 +125,6 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -662,7 +661,7 @@ module u2_core wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; wire clear_tx; - + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_tx)); @@ -681,11 +680,9 @@ module u2_core .RAM_LDn(RAM_LDn), .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), -// .datain({rd1_flags,rd1_dat}), .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), -// .dataout(tx_data), .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 081ffe4c6..8426826e2 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -164,9 +164,7 @@ module u2plus_core wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, - debug_extfifo; - + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -367,7 +365,7 @@ module u2plus_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .gpio({io_tx,io_rx}) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -380,7 +378,7 @@ module u2plus_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd2; + localparam compat_num = 32'd3; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -494,10 +492,17 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // Interrupt Controller, Slave #8 + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + assign irq= {{8'b0}, {uart_tx_int[3:0], uart_rx_int[3:0]}, {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), @@ -578,9 +583,15 @@ module u2plus_core .debug(debug_rx_dsp) ); wire [31:0] vrc_debug; + wire clear_rx; + setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx)); + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), @@ -590,7 +601,7 @@ module u2plus_core wire [3:0] vita_state; vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), @@ -598,7 +609,7 @@ module u2plus_core .debug_rx(vita_state) ); fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); @@ -608,23 +619,19 @@ module u2plus_core wire [35:0] tx_data; wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; - -/* -----\/----- EXCLUDED -----\/----- - fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - -----/\----- EXCLUDED -----/\----- */ - // External and internal clock run at 100MHz for USRP2+ because ext RAM is 36bits wide - // and provides ample bandwidth. + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + assign RAM_A[20:18] = 3'b0; ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) ext_fifo_i1 - ( - .int_clk(dsp_clk), + (.int_clk(dsp_clk), .ext_clk(dsp_clk), - .rst(dsp_rst), + .rst(dsp_rst | clear_tx), .RAM_D_pi(RAM_D_pi), .RAM_D_po(RAM_D_po), .RAM_D_poe(RAM_D_poe), @@ -635,17 +642,17 @@ module u2plus_core .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), - .src_rdy_i(rd1_ready_o), // WRITE - .dst_rdy_o(rd1_ready_i), // not FULL + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), - .src_rdy_o(tx_src_rdy), // not EMPTY + .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy), .debug(debug_extfifo), - .debug2(debug_extfifo2) - ); - + .debug2(debug_extfifo2) ); + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), @@ -681,8 +688,8 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = 2'b00; - assign debug = 32'd0; + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; -- cgit v1.2.3 From 00297596c28df8d5ffd454f95f71b290dcbe07ef Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 13 Nov 2010 18:18:51 -0800 Subject: we're still on version 12.1 --- usrp2/coregen/fifo_xlnx_32x36_2clk.xise | 2 +- usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/usrp2/coregen/fifo_xlnx_32x36_2clk.xise index 0c3544a33..b9eb7bd1a 100644 --- a/usrp2/coregen/fifo_xlnx_32x36_2clk.xise +++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.xise @@ -12,7 +12,7 @@ - + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise index 8bf460ac7..91dbf5819 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise @@ -12,7 +12,7 @@ - + -- cgit v1.2.3 From f04a49aabfce58fa57e5dcc727b7a13143fb92a4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 13 Nov 2010 18:19:37 -0800 Subject: simplify time comparison to speed up logic and meet fpga timing --- usrp2/timing/time_compare.v | 26 +++++++++++++++++++++++++- usrp2/vrt/vita_tx_control.v | 5 ++--- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/usrp2/timing/time_compare.v b/usrp2/timing/time_compare.v index a21c9f8e0..cb2b6d860 100644 --- a/usrp2/timing/time_compare.v +++ b/usrp2/timing/time_compare.v @@ -14,10 +14,34 @@ module time_compare wire tick_match = (time_now[31:0] == trigger_time[31:0]); wire tick_late = (time_now[31:0] > trigger_time[31:0]); - +/* assign now = sec_match & tick_match; assign late = sec_late | (sec_match & tick_late); assign early = ~now & ~late; +*/ + + /* + assign now = (time_now == trigger_time); + assign late = (time_now > trigger_time); + assign early = (time_now < trigger_time); + */ + + // Compare fewer bits instead of 64 to speed up logic + // Unused bits are not significant + // Top bit of seconds would put us in year 2038, long after + // the warranty has run out :) + // Top 5 bits of ticks are always zero for clocks less than 134MHz + // "late" can drop bottom few bits of ticks, and just delay signaling + // of late. + // "now" cannot drop those bits, it needs to be exact. + + wire [57:0] short_now = {time_now[62:32],time_now[26:0]}; + wire [57:0] short_trig = {trigger_time[62:32],trigger_time[26:0]}; + + assign now = (short_now == short_trig); + assign late = (short_now[57:5] > short_trig[57:5]); + assign early = (short_now < short_trig); + assign too_early = (trigger_time[63:32] > (time_now[63:32] + 4)); // Don't wait too long endmodule // time_compare diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 967847d36..ddcb6a2d2 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -38,9 +38,8 @@ module vita_tx_control // FIXME ignore too_early for now for timing reasons assign too_early = 0; time_compare - time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early), - .late(late), .too_early()); -// .late(late), .too_early(too_early)); + time_compare (.time_now(vita_time), .trigger_time(send_time), + .now(now), .early(early), .late(late), .too_early()); localparam IBS_IDLE = 0; localparam IBS_RUN = 1; // FIXME do we need this? -- cgit v1.2.3 From 7383ff07f482f8dcf37f2c1464f6a29d1b0bdf0b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Nov 2010 18:39:24 -0800 Subject: fix problem with consecutive timed packets on tx --- usrp2/vrt/vita_tx_deframer.v | 2 -- 1 file changed, 2 deletions(-) diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 7697be367..eb39feaec 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -201,8 +201,6 @@ module vita_tx_deframer send_time[63:32] <= data_i[31:0]; VITA_TICS2 : send_time[31:0] <= data_i[31:0]; - VITA_STORE, VITA_HEADER : - send_time[63:0] <= 64'd0; endcase // case (vita_state) always @(posedge clk) -- cgit v1.2.3 From e7fbdbce6809698e10a9d6e18326ab572a280811 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Nov 2010 19:13:42 -0800 Subject: get rid of extraneous U messages when we actually had an ACK --- usrp2/vrt/vita_tx_chain.v | 6 +++--- usrp2/vrt/vita_tx_control.v | 11 +++++++---- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 21e826f1c..264b6e98a 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -31,7 +31,7 @@ module vita_tx_chain wire clear_seqnum; wire [31:0] current_seqnum; - assign underrun = error & ~(error_code == 1); + assign underrun = error; assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+1)) sr @@ -56,7 +56,7 @@ module vita_tx_chain vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control (.clk(clk), .reset(reset), .clear(clear_vita), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.error(error),.error_code(error_code), + .vita_time(vita_time), .error(error), .ack(ack), .error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed), .debug(debug_vtc) ); @@ -84,7 +84,7 @@ module vita_tx_chain gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(error & (REPORT_ERROR==1)), .sent(), + .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), .seqnum0(current_seqnum), .seqnum1(32'd0), .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index ddcb6a2d2..20ad6b995 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -6,7 +6,7 @@ module vita_tx_control input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, - output error, + output error, output ack, output reg [31:0] error_code, output reg packet_consumed, @@ -65,13 +65,14 @@ module vita_tx_control wire policy_wait = error_policy[0]; wire policy_next_packet = error_policy[1]; wire policy_next_burst = error_policy[2]; - reg send_error; + reg send_error, send_ack; always @(posedge clk) if(reset | clear) begin ibs_state <= IBS_IDLE; send_error <= 0; + send_ack <= 0; error_code <= 0; end else @@ -106,7 +107,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR_DONE; // Not really an error error_code <= CODE_EOB_ACK; - send_error <= 1; + send_ack <= 1; end else ibs_state <= IBS_CONT_BURST; @@ -146,6 +147,7 @@ module vita_tx_control IBS_ERROR_DONE : begin send_error <= 0; + send_ack <= 0; ibs_state <= IBS_IDLE; end @@ -156,6 +158,7 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); assign error = send_error; + assign ack = send_ack; always @(posedge clk) if(reset | clear) @@ -163,7 +166,7 @@ module vita_tx_control else packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; - assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, + assign debug = { { now,early,late,ack,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, { 8'b0 } }; -- cgit v1.2.3 From 18076097477a5d6f26ab69a23c4d27062490aeb0 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 19 Nov 2010 11:53:58 -0800 Subject: modernize the testbench --- usrp2/vrt/vita_tx_tb.v | 48 ++++++++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/usrp2/vrt/vita_tx_tb.v b/usrp2/vrt/vita_tx_tb.v index 0223d6850..a118ffd4e 100644 --- a/usrp2/vrt/vita_tx_tb.v +++ b/usrp2/vrt/vita_tx_tb.v @@ -33,7 +33,7 @@ module vita_tx_tb; wire [31:0] set_data_dsp; wire sample_dst_rdy, sample_src_rdy; - wire [64+4+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx; + wire [5+64+16+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx; time_64bit #(.TICKS_PER_SEC(100000000), .BASE(0)) time_64bit (.clk(clk), .rst(reset), @@ -49,8 +49,8 @@ module vita_tx_tb; .datain(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), .dataout(data_tx), .src_rdy_o(src_rdy_tx), .dst_rdy_i(dst_rdy_tx)); - vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN)) vita_tx_deframer - (.clk(clk), .reset(reset), .clear(0), + vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN), .USE_TRANS_HEADER(0)) vita_tx_deframer + (.clk(clk), .reset(reset), .clear(0), .clear_seqnum(0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .data_i(data_tx), .dst_rdy_o(dst_rdy_tx), .src_rdy_i(src_rdy_tx), .sample_fifo_o(sample_data_tx), @@ -60,7 +60,7 @@ module vita_tx_tb; vita_tx_control #(.BASE(16), .WIDTH(MAXCHAN*32)) vita_tx_control (.clk(clk), .reset(reset), .clear(0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .vita_time(vita_time), .underrun(underrun), + .vita_time(vita_time), .error(underrun), .error_code(), .sample_fifo_i(sample_data_tx), .sample_fifo_dst_rdy_o(sample_dst_rdy_tx), .sample_fifo_src_rdy_i(sample_src_rdy_tx), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx)); @@ -92,35 +92,47 @@ module vita_tx_tb; write_setting(7,8); // Samples per VITA packet write_setting(8,NUMCHAN); // Samples per VITA packet #10000; - queue_vita_packets(32'h300, 106, 32'hF00D_1234, 32'h55AA_AA55); - //queue_vita_packets(32'h300, 6, 32'hF00D_1234, 32'h0); - queue_vita_packets(32'h600, 9, 32'h9876_ABCD, 32'h0); - + queue_vita_packets(0, 32'h300, 5, 32'h0000_1000, 32'h0, 4'h0, 1, 0, 1); + queue_vita_packets(0, 32'h0, 5, 32'h0000_2000, 32'h0, 4'h1, 0, 0, 0); + queue_vita_packets(0, 32'h0, 5, 32'h0000_3000, 32'h0, 4'h2, 0, 0, 0); + + queue_vita_packets(0, 32'h400, 3, 32'h0000_4000, 32'h0, 4'h3, 1, 0, 1); + queue_vita_packets(0, 32'h0, 3, 32'h0000_5000, 32'h0, 4'h4, 0, 0, 0); + queue_vita_packets(0, 32'h0, 3, 32'h0000_6000, 32'h0, 4'h5, 0, 1, 0); + #300000 $finish; end task queue_vita_packets; + input [31:0] send_secs; input [31:0] sendtime; input [15:0] samples; input [15:0] word; input [31:0] trailer; + input [3:0] seqnum; + input sob; + input eob; + input sendat; reg [15:0] i; begin + src_rdy <= 0; @(posedge clk); src_rdy <= 1; - data_o <= {4'b0001,4'h1,1'b0,|trailer,2'h3,8'hF0,(16'd5+samples+|trailer)}; // header - @(posedge clk); - data_o <= {4'b0000,32'h0}; // streamid - @(posedge clk); - data_o <= {4'b0000,32'h0}; // SECS - @(posedge clk); - data_o <= {4'b0000,32'h0}; // TICS + data_o <= {4'b0001,4'h0,1'b0,|trailer,sob,eob,{2{sendat}},1'b0,sendat,seqnum,(16'd1+samples+|trailer+sendat+sendat+sendat)}; // header @(posedge clk); - data_o <= {4'b0000,sendtime}; // TICS - @(posedge clk); - + //data_o <= {4'b0000,32'h0}; // streamid + //@(posedge clk); + if(sendat) + begin + data_o <= {4'b0000,send_secs}; // SECS + @(posedge clk); + data_o <= {4'b0000,32'h0}; // TICS + @(posedge clk); + data_o <= {4'b0000,sendtime}; // TICS + @(posedge clk); + end for(i=0;i Date: Sat, 20 Nov 2010 13:03:23 -0800 Subject: shouldn't be executable --- usrp2/top/u2_rev3/u2_core.v | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 usrp2/top/u2_rev3/u2_core.v diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v old mode 100755 new mode 100644 -- cgit v1.2.3 From 503a69dd734be4502078b32d8aca027b0c56368f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 21 Nov 2010 19:04:59 -0800 Subject: no need for second sequence number anymore. Each dsp tx chain generates its own flow control packets now. --- usrp2/vrt/gen_context_pkt.v | 15 ++++++--------- usrp2/vrt/vita_tx_chain.v | 4 ++-- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index efc170743..bf83aeae5 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -7,8 +7,7 @@ module gen_context_pkt input [31:0] streamid, input [63:0] vita_time, input [31:0] message, - input [31:0] seqnum0, - input [31:0] seqnum1, + input [31:0] seqnum, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); localparam CTXT_IDLE = 0; @@ -19,9 +18,8 @@ module gen_context_pkt localparam CTXT_TICS = 5; localparam CTXT_TICS2 = 6; localparam CTXT_MESSAGE = 7; - localparam CTXT_FLOWCTRL0 = 8; - localparam CTXT_FLOWCTRL1 = 9; - localparam CTXT_DONE = 10; + localparam CTXT_FLOWCTRL = 8; + localparam CTXT_DONE = 9; reg [33:0] data_int; wire src_rdy_int, dst_rdy_int; @@ -36,7 +34,7 @@ module gen_context_pkt else if(trigger) stored_message <= message; - else if(ctxt_state == CTXT_FLOWCTRL1) + else if(ctxt_state == CTXT_DONE) stored_message <= 0; // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe @@ -73,14 +71,13 @@ module gen_context_pkt always @* case(ctxt_state) CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd32 }; - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd8 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; CTXT_MESSAGE : data_int <= { 2'b00, message }; - CTXT_FLOWCTRL0 : data_int <= { 2'b00, seqnum0 }; - CTXT_FLOWCTRL1 : data_int <= { 2'b10, seqnum1 }; + CTXT_FLOWCTRL : data_int <= { 2'b10, seqnum }; default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 264b6e98a..2ec78189b 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -75,7 +75,7 @@ module vita_tx_chain (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(32'd0), - .seqnum0(current_seqnum), .seqnum1(32'd0), + .seqnum(current_seqnum), .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy)); trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt (.clk(clk), .reset(reset), .clear(clear_vita), @@ -86,7 +86,7 @@ module vita_tx_chain (.clk(clk), .reset(reset), .clear(clear_vita), .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), - .seqnum0(current_seqnum), .seqnum1(32'd0), + .seqnum(current_seqnum), .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); assign debug = debug_vtc | debug_vtd; -- cgit v1.2.3