From 6c2418b0347fdff3bb82d44307bf440bb91395d0 Mon Sep 17 00:00:00 2001 From: Michael West Date: Mon, 25 Mar 2019 09:42:10 -0700 Subject: Revert "RFNoC: Remove incorrect flush" This reverts commit c8e01d4bd5bef30ef6e6080c60bc8b4706eb1200. The commit introduced random phase offsets for TwinRX phase alignment. --- host/lib/rfnoc/source_block_ctrl_base.cpp | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/host/lib/rfnoc/source_block_ctrl_base.cpp b/host/lib/rfnoc/source_block_ctrl_base.cpp index efdf94e9f..656ab26af 100644 --- a/host/lib/rfnoc/source_block_ctrl_base.cpp +++ b/host/lib/rfnoc/source_block_ctrl_base.cpp @@ -102,6 +102,25 @@ void source_block_ctrl_base::configure_flow_control_out(const bool enable_fc_out % buf_size_bytes % unique_id())); } + // Disable flow control entirely and let all upstream data flush out + // We need to do this every time the window is changed because + // a) We don't know what state the flow-control module was left in + // in the previous run (it should still be enabled) + // b) Changing the window size where data is buffered upstream may + // result in stale packets entering the stream. + sr_write(SR_FLOW_CTRL_EN, 0, block_port); + + // Wait for data to flush out. + // In the FPGA we are guaranteed that all buffered packets are more-or-less + // consecutive. 1ms@200MHz = 200,000 cycles of "flush time". 200k cycles = 200k * 8 + // bytes (64 bits) = 1.6MB of data that can be flushed. Typically in the FPGA we have + // buffering in the order of kilobytes so waiting for 1MB to flush is more than enough + // time. + // TODO: Enhancement. We should get feedback from the FPGA about when the + // source_flow_control + // module is done flushing. + std::this_thread::sleep_for(std::chrono::milliseconds(1)); + // Enable source flow control module and conditionally enable byte based and/or packet // count based flow control const bool enable_byte_fc = (buf_size_bytes != 0); -- cgit v1.2.3