From 657cc4c06249aa9897e6d286fa5eadb1a3506b4b Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 28 Jan 2020 13:12:32 -0800 Subject: fixup! mpm: e320/e310: Expose APIs to drive GPIO source via UHD --- mpm/python/usrp_mpm/periph_manager/e31x.py | 1 + mpm/python/usrp_mpm/periph_manager/e320.py | 2 +- mpm/python/usrp_mpm/periph_manager/n3xx.py | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/mpm/python/usrp_mpm/periph_manager/e31x.py b/mpm/python/usrp_mpm/periph_manager/e31x.py index d2e22b498..75dcf2126 100644 --- a/mpm/python/usrp_mpm/periph_manager/e31x.py +++ b/mpm/python/usrp_mpm/periph_manager/e31x.py @@ -37,6 +37,7 @@ E310_GPIO_SRC_PS = "PS" # We use the index positions of RFA and RFB to map between name and radio index E310_GPIO_SRCS = ("RFA", "RFB", E310_GPIO_SRC_PS) E310_FPGPIO_WIDTH = 6 +E310_GPIO_BANKS = ["INT0",] ############################################################################### # Transport managers diff --git a/mpm/python/usrp_mpm/periph_manager/e320.py b/mpm/python/usrp_mpm/periph_manager/e320.py index 8e698250e..f982155db 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320.py +++ b/mpm/python/usrp_mpm/periph_manager/e320.py @@ -35,7 +35,7 @@ E320_DEFAULT_ENABLE_FPGPIO = True E320_FPGA_COMPAT = (5, 0) E320_MONITOR_THREAD_INTERVAL = 1.0 # seconds E320_DBOARD_SLOT_IDX = 0 -E320_GPIO_BANKS = "FP0" +E320_GPIO_BANKS = ["FP0",] E320_GPIO_SRC_PS = "PS" # We use the index positions of RFA and RFB to map between name and radio index E320_GPIO_SRCS = ("RFA", "RFB", E320_GPIO_SRC_PS) diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py index d7b50a5f9..b87edfac0 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py @@ -44,7 +44,7 @@ N32X_QSFP_I2C_LABEL = 'qsfp-i2c' N3XX_FPGA_COMPAT = (7, 0) N3XX_MONITOR_THREAD_INTERVAL = 1.0 # seconds N3XX_BUS_CLK = 200e6 -N3XX_GPIO_BANKS = "FP0" +N3XX_GPIO_BANKS = ["FP0",] N3XX_GPIO_SRC_PS = "PS" N3XX_FPGPIO_WIDTH = 12 -- cgit v1.2.3