From 5fa9cd632b0d889256985b61ec67184c3a98909c Mon Sep 17 00:00:00 2001
From: matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5>
Date: Sat, 11 Oct 2008 23:04:06 +0000
Subject: New serdes status interrupt, clk_status interrupt.  New capability to
 flush the ICache.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9779 221aa14e-8319-0410-a670-987f0aec2ac5
---
 control_lib/icache.v         |  5 +++--
 control_lib/ram_harv_cache.v |  7 +++++--
 top/u2_core/u2_core.v        | 11 ++++++++---
 top/u2_rev3/Makefile         |  1 -
 4 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/control_lib/icache.v b/control_lib/icache.v
index dd93c88ed..bd21f47cc 100644
--- a/control_lib/icache.v
+++ b/control_lib/icache.v
@@ -11,7 +11,8 @@ module icache
      output iwb_ack_o,
      input [31:0] iram_dat_i,
      output [AWIDTH-1:0] iram_adr_o,
-     output iram_en_o );
+     output iram_en_o,
+     input flush);
 
    localparam TAGWIDTH = AWIDTH-CWIDTH-2;
    reg 	      stb_d1, ack_d1, miss_d1;
@@ -28,7 +29,7 @@ module icache
    // Write into cache
    integer 	      i;
    always @(posedge wb_clk_i)
-     if(wb_rst_i)
+     if(wb_rst_i | flush)
        for(i=0;i<(1<<CWIDTH);i=i+1)
 	 ivalid[i] <= 0;
      else
diff --git a/control_lib/ram_harv_cache.v b/control_lib/ram_harv_cache.v
index 933f9ba1a..29fdebf7a 100644
--- a/control_lib/ram_harv_cache.v
+++ b/control_lib/ram_harv_cache.v
@@ -25,7 +25,9 @@ module ram_harv_cache
      input dwb_we_i,
      output dwb_ack_o,
      input dwb_stb_i,
-     input [3:0] dwb_sel_i );
+     input [3:0] dwb_sel_i,
+
+     input flush_icache );
 
    wire [31:0] 	 iram_dat, dram_dat_i, dram_dat_o;
    wire [AWIDTH-1:0] iram_adr, dram_adr;
@@ -60,7 +62,8 @@ module ram_harv_cache
      icache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
 	    .iwb_adr_i(iwb_adr_i),.iwb_stb_i(iwb_stb_i),
 	    .iwb_dat_o(iwb_dat_o),.iwb_ack_o(iwb_ack_o),
-	    .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en) );
+	    .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en),
+	    .flush(flush_icache));
 
    // RAM loader
    assign 	 ram_loader_ack_o = ram_loader_stb_i;
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index 7d749684c..33daf8251 100755
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -283,6 +283,7 @@ module u2_core
    // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
    // I-port connects directly to processor and ram loader
 
+   wire 	 flush_icache;
    ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
      sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
 	     
@@ -295,11 +296,15 @@ module u2_core
 	     .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
 	     
 	     .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
-	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
+	     .flush_icache(flush_icache));
    
    assign 	 s0_err = 1'b0;
    assign 	 s0_rty = 1'b0;
 
+   setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					 .in(set_data),.out(),.changed(flush_icache));
+
    // Buffer Pool, slave #1
    wire 	 rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
    wire 	 rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
@@ -388,7 +393,7 @@ module u2_core
       
       .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
       .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
-      .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10({30'b0,clk_func,clk_status}),
+      .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
       .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
       );
 
@@ -479,7 +484,7 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // Interrupt Controller, Slave #8
 
-   wire [15:0] 	 irq={{5'b0, serdes_link_up, uart_tx_int, uart_rx_int},
+   wire [15:0] 	 irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
 		      {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
    
    simple_pic #(.is(16),.dwidth(32)) simple_pic
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
index a86ee71b3..9de6b55cc 100644
--- a/top/u2_rev3/Makefile
+++ b/top/u2_rev3/Makefile
@@ -62,7 +62,6 @@ control_lib/cascadefifo2.v \
 control_lib/dcache.v \
 control_lib/decoder_3_8.v \
 control_lib/dpram32.v \
-control_lib/extram_interface.v \
 control_lib/fifo_2clock.v \
 control_lib/fifo_2clock_casc.v \
 control_lib/gray2bin.v \
-- 
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