From 5ce99ee61bad4f9c421a873aa2f3144e8e2aebe7 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 3 Sep 2009 14:13:44 -0700
Subject: MAC transmit seems to work now.  The root cause of the problem was
 accidentally using the rx_clk in one stage of the fifos on the tx side.

---
 control_lib/newfifo/fifo_2clock.v      | 33 ++++++++++++++------
 simple_gemac/simple_gemac_wrapper.v    | 31 ++++++++++++-------
 simple_gemac/simple_gemac_wrapper_tb.v | 17 ++++++-----
 top/u2_rev3/Makefile                   | 56 +++++++++++-----------------------
 4 files changed, 70 insertions(+), 67 deletions(-)

diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 40c479db7..2ada39fb0 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -2,26 +2,39 @@
 // FIXME ignores the AWIDTH (fifo size) parameter
 
 module fifo_2clock
-  #(parameter WIDTH=32, SIZE=9)
+  #(parameter WIDTH=36, SIZE=6)
    (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
     input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
     input arst);
    
-   wire [SIZE-1:0] level_rclk, level_wclk;
-   wire 	   full, empty, write, read;
+   wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels
+   wire 	 full, empty, write, read;
 
    assign dst_rdy_o  = ~full;
    assign src_rdy_o  = ~empty;
    assign write      = src_rdy_i & dst_rdy_o;
    assign read 	     = src_rdy_o & dst_rdy_i;
-   
-   fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
-     (.rst(rst),
-      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
-      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
 
-   assign occupied  = {{(16-SIZE){1'b0}},level_rclk};
-   assign space = ((1<<SIZE)-1)-level_wclk;
+   generate
+      if(SIZE==9)
+	fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
+	      (.rst(rst),
+	       .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+	       .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      else if(SIZE==11)
+	fifo_xlnx_2Kx36_2clk mac_tx_fifo_2clk
+	      (.rst(rst),
+	       .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+	       .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      else if(SIZE==6)
+	fifo_xlnx_64x36_2clk mac_tx_fifo_2clk
+		   (.rst(rst),
+		    .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		    .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+   endgenerate
+   
+   assign occupied  = {{(16-SIZE-1){1'b0}},level_rclk};
+   assign space     = ((1<<SIZE)+1)-level_wclk;
    
 endmodule // fifo_2clock
 
diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v
index 31bc02ebb..b9bc05848 100644
--- a/simple_gemac/simple_gemac_wrapper.v
+++ b/simple_gemac/simple_gemac_wrapper.v
@@ -59,8 +59,12 @@ module simple_gemac_wrapper
 
    // RX FIFO Chain
    wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
-   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2_n, rx_ll_dst_rdy2;
+
+   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
+   wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
+
    wire [7:0] rx_ll_data, rx_ll_data2;
+
    wire [35:0] rx_f36_data_int1;
    wire        rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
    
@@ -75,19 +79,24 @@ module simple_gemac_wrapper
       .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
       .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
       .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
-      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(~rx_ll_dst_rdy2_n));
+      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
 
+   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
+   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
+   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
+   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
+   
    ll8_to_fifo36 ll8_to_fifo36
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2),
-      .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
+      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
       .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
 
-   cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) rx_2clk_fifo
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) rx_2clk_fifo
      (.wclk(rx_clk), .datain(rx_f36_data_int1), 
-      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .level_wclk(),
+      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(),
       .rclk(sys_clk), .dataout(rx_f36_data), 
-      .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .level_rclk(), .arst(reset));
+      .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
    
    // TX FIFO Chain
    wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
@@ -97,11 +106,11 @@ module simple_gemac_wrapper
    wire [35:0] tx_f36_data_int1;
    wire        tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
 
-   cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) tx_2clk_fifo
+   fifo_2clock #(.WIDTH(36), .SIZE(6)) tx_2clk_fifo
      (.wclk(sys_clk), .datain(tx_f36_data), 
-      .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .level_wclk(),
+      .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
       .rclk(tx_clk), .dataout(tx_f36_data_int1), 
-      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .level_rclk(), .arst(reset));
+      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
    
    fifo36_to_ll8 fifo36_to_ll8
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
@@ -115,7 +124,7 @@ module simple_gemac_wrapper
    assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
    
    ll8_shortfifo tx_sfifo
-     (.clk(rx_clk), .reset(tx_reset), .clear(clear),
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
       .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
       .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
diff --git a/simple_gemac/simple_gemac_wrapper_tb.v b/simple_gemac/simple_gemac_wrapper_tb.v
index 164b50724..26a471a49 100644
--- a/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/simple_gemac/simple_gemac_wrapper_tb.v
@@ -45,8 +45,11 @@ module simple_gemac_wrapper_tb;
    wire        wb_ack;
 
    reg [35:0]  tx_f36_data=0;
-   reg 	       tx_f36_src_rdy=0;
+   reg 	       tx_f36_src_rdy = 0;
    wire        tx_f36_dst_rdy;
+   wire        rx_f36_data;
+   wire        rx_f36_src_rdy;
+   wire        rx_f36_dst_rdy = 1;
    
    simple_gemac_wrapper simple_gemac_wrapper
      (.clk125(eth_clk),  .reset(reset),
@@ -56,11 +59,11 @@ module simple_gemac_wrapper_tb;
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       .pause_req(pause_req), .pause_time(pause_time),
 
-      .sys_clk(sys_clk), .rx_f36_data(), .rx_f36_src_rdy(), .rx_f36_dst_rdy(),
+      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
       .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
 
       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
-      .wb_adr(), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
 
       .mdio(), .mdc(),
       .debug() );
@@ -81,9 +84,9 @@ module simple_gemac_wrapper_tb;
 	@(negedge reset);
 	repeat (10)
 	  @(posedge wb_clk);
-	WishboneWR(0,6'b111001);
-	WishboneWR(4,16'hF1F2);
-	WishboneWR(8,32'hF3F4_F5F6);
+	WishboneWR(0,6'b111101); 
+	WishboneWR(4,16'hA0B0);
+	WishboneWR(8,32'hC0D0_A1B1);
 	WishboneWR(12,16'h0000);
 	WishboneWR(16,32'h0000_0000);
 	
@@ -100,7 +103,7 @@ module simple_gemac_wrapper_tb;
 
 	repeat (1000)
 	  @(posedge sys_clk);
-	SendPacket_to_fifo36(32'hAABBCCDD,10);    // This packet gets dropped by the filters
+	SendPacket_to_fifo36(32'hA0B0C0D0,10);    // This packet gets dropped by the filters
 	repeat (1000)
 	  @(posedge sys_clk);
 
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
index 5d782b610..7847b8c72 100644
--- a/top/u2_rev3/Makefile
+++ b/top/u2_rev3/Makefile
@@ -56,20 +56,12 @@ export SOURCES := \
 control_lib/CRC16_D16.v \
 control_lib/atr_controller.v \
 control_lib/bin2gray.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/cascadefifo2.v \
 control_lib/dcache.v \
 control_lib/decoder_3_8.v \
 control_lib/dpram32.v \
-control_lib/fifo_2clock.v \
-control_lib/fifo_2clock_casc.v \
-control_lib/newfifo/newfifo_2clock.v \
-control_lib/newfifo/cascadefifo_2clock.v \
 control_lib/gray2bin.v \
 control_lib/gray_send.v \
 control_lib/icache.v \
-control_lib/longfifo.v \
 control_lib/mux4.v \
 control_lib/mux8.v \
 control_lib/nsgpio.v \
@@ -78,8 +70,6 @@ control_lib/ram_harv_cache.v \
 control_lib/ram_loader.v \
 control_lib/setting_reg.v \
 control_lib/settings_bus.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
 control_lib/srl.v \
 control_lib/system_control.v \
 control_lib/wb_1master.v \
@@ -101,43 +91,31 @@ simple_gemac/crc.v \
 simple_gemac/delay_line.v \
 simple_gemac/flow_ctrl_tx.v \
 simple_gemac/address_filter.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/ll8_to_fifo36.v \
 simple_gemac/ll8_to_txmac.v \
 simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
 control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
 control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
 coregen/fifo_xlnx_2Kx36_2clk.v \
 coregen/fifo_xlnx_2Kx36_2clk.xco \
 coregen/fifo_xlnx_512x36_2clk.v \
 coregen/fifo_xlnx_512x36_2clk.xco \
-eth/mac_rxfifo_int.v \
-eth/mac_txfifo_int.v \
-eth/rtl/verilog/Clk_ctrl.v \
-eth/rtl/verilog/MAC_rx.v \
-eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
-eth/rtl/verilog/MAC_rx/CRC_chk.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
-eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
-eth/rtl/verilog/MAC_top.v \
-eth/rtl/verilog/MAC_tx.v \
-eth/rtl/verilog/MAC_tx/CRC_gen.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
-eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
-eth/rtl/verilog/MAC_tx/Random_gen.v \
-eth/rtl/verilog/Phy_int.v \
-eth/rtl/verilog/RMON.v \
-eth/rtl/verilog/RMON/RMON_addr_gen.v \
-eth/rtl/verilog/RMON/RMON_ctrl.v \
-eth/rtl/verilog/Reg_int.v \
-eth/rtl/verilog/eth_miim.v \
-eth/rtl/verilog/flow_ctrl_rx.v \
-eth/rtl/verilog/flow_ctrl_tx.v \
-eth/rtl/verilog/miim/eth_clockgen.v \
-eth/rtl/verilog/miim/eth_outputcontrol.v \
-eth/rtl/verilog/miim/eth_shiftreg.v \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
 extram/wb_zbt16_b.v \
 opencores/8b10b/decode_8b10b.v \
 opencores/8b10b/encode_8b10b.v \
-- 
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