From 57681c7659992eb6b7d78db91f888487d4e2a260 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 27 Dec 2010 16:53:59 -0800 Subject: packet_router: code tweaks, renamed instances of buffer pool, removed unused ctrl reg --- firmware/zpu/apps/txrx_uhd.c | 2 +- firmware/zpu/lib/pkt_ctrl.c | 33 +++++++++++----------------- firmware/zpu/lib/pkt_ctrl.h | 2 +- firmware/zpu/usrp2/memory_map.h | 47 +++++++++++++++++++--------------------- firmware/zpu/usrp2p/memory_map.h | 45 ++++++++++++++++++-------------------- 5 files changed, 58 insertions(+), 71 deletions(-) diff --git a/firmware/zpu/apps/txrx_uhd.c b/firmware/zpu/apps/txrx_uhd.c index ea74f032e..b16d177d7 100644 --- a/firmware/zpu/apps/txrx_uhd.c +++ b/firmware/zpu/apps/txrx_uhd.c @@ -360,7 +360,7 @@ main(void) //1) register the addresses into the network stack register_addrs(ethernet_mac_addr(), get_ip_addr()); - pkt_ctrl_program_inspector(get_ip_addr(), USRP2_UDP_CTRL_PORT, USRP2_UDP_DATA_PORT); + pkt_ctrl_program_inspector(get_ip_addr(), USRP2_UDP_DATA_PORT); //2) register callbacks for udp ports we service init_udp_listeners(); diff --git a/firmware/zpu/lib/pkt_ctrl.c b/firmware/zpu/lib/pkt_ctrl.c index a5659eb33..ebda35049 100644 --- a/firmware/zpu/lib/pkt_ctrl.c +++ b/firmware/zpu/lib/pkt_ctrl.c @@ -20,52 +20,45 @@ #include void pkt_ctrl_program_inspector( - const struct ip_addr *ip_addr, uint16_t ctrl_port, uint16_t data_port + const struct ip_addr *ip_addr, uint16_t data_port ){ - buffer_pool_ctrl->ip_addr = ip_addr->addr; - buffer_pool_ctrl->ctrl_ports = ctrl_port; - buffer_pool_ctrl->data_ports = data_port; + router_ctrl->ip_addr = ip_addr->addr; + router_ctrl->data_ports = data_port; } void pkt_ctrl_set_routing_mode(pkt_ctrl_routing_mode_t mode){ switch(mode){ - case PKT_CTRL_ROUTING_MODE_SLAVE: - buffer_pool_ctrl->misc_ctrl = 0; - break; - case PKT_CTRL_ROUTING_MODE_MASTER: - buffer_pool_ctrl->misc_ctrl = 1; - break; + case PKT_CTRL_ROUTING_MODE_SLAVE: router_ctrl->mode_ctrl = 0; break; + case PKT_CTRL_ROUTING_MODE_MASTER: router_ctrl->mode_ctrl = 1; break; } } static inline bool is_status_bit_set(int bit){ - return buffer_pool_status->status & (1 << bit); + return router_status->status & (1 << bit); } #define CPU_OUT_HS_BIT 0 //from packet router to CPU #define CPU_INP_HS_BIT 1 //from CPU to packet router void *pkt_ctrl_claim_incoming_buffer(size_t *num_lines){ - buffer_pool_ctrl->cpu_out_ctrl = 0; if (!is_status_bit_set(CPU_OUT_HS_BIT)) return NULL; - *num_lines = (buffer_pool_status->status >> 16) & 0xffff; - return buffer_ram(0); + *num_lines = (router_status->status >> 16) & 0xffff; + return router_ram(0); } void pkt_ctrl_release_incoming_buffer(void){ - buffer_pool_ctrl->cpu_out_ctrl = 1; + router_ctrl->cpu_out_ctrl = 1; while (is_status_bit_set(CPU_OUT_HS_BIT)){} - buffer_pool_ctrl->cpu_out_ctrl = 0; + router_ctrl->cpu_out_ctrl = 0; } void *pkt_ctrl_claim_outgoing_buffer(void){ - buffer_pool_ctrl->cpu_inp_ctrl = 0; while (!is_status_bit_set(CPU_INP_HS_BIT)){} - return buffer_ram(1); + return router_ram(1); } void pkt_ctrl_commit_outgoing_buffer(size_t num_lines){ - buffer_pool_ctrl->cpu_inp_ctrl = ((num_lines & 0xffff) << 16) | 1; + router_ctrl->cpu_inp_ctrl = ((num_lines & 0xffff) << 16) | 1; while (is_status_bit_set(CPU_INP_HS_BIT)){} - buffer_pool_ctrl->cpu_inp_ctrl = 0; + router_ctrl->cpu_inp_ctrl = 0; } diff --git a/firmware/zpu/lib/pkt_ctrl.h b/firmware/zpu/lib/pkt_ctrl.h index 346e22094..410ffdaa4 100644 --- a/firmware/zpu/lib/pkt_ctrl.h +++ b/firmware/zpu/lib/pkt_ctrl.h @@ -30,7 +30,7 @@ typedef enum { //! Program the decision values into the packet inspector void pkt_ctrl_program_inspector( - const struct ip_addr *ip_addr, uint16_t ctrl_port, uint16_t data_port + const struct ip_addr *ip_addr, uint16_t data_port ); //! Set the routing mode for this device diff --git a/firmware/zpu/usrp2/memory_map.h b/firmware/zpu/usrp2/memory_map.h index a2de29cdb..ca7453c24 100644 --- a/firmware/zpu/usrp2/memory_map.h +++ b/firmware/zpu/usrp2/memory_map.h @@ -18,7 +18,7 @@ /* Overall Memory Map * 0000-7FFF 32K RAM space (16K on 1500, 24K on 2000, 32K on DSP) - * 8000-BFFF 16K Buffer Pool + * 8000-BFFF 16K Packet Router * C000-FFFF 16K Peripherals */ @@ -45,20 +45,18 @@ #define RAM_BASE 0x0000 //////////////////////////////////////////////////////////////// -// Buffer Pool RAM, Slave 1 +// Packet Router RAM, Slave 1 // -// The buffers themselves are located in Slave 1, Buffer Pool RAM. -// The status registers are in Slave 5, Buffer Pool Status. +// The buffers themselves are located in Slave 1, Packet Router RAM. +// The status registers are in Slave 5, Packet Router Status. // The control register is in Slave 7, Settings Bus. -#define BUFFER_POOL_RAM_BASE 0x8000 +#define ROUTER_RAM_BASE 0x8000 -#define BP_NLINES 0x0200 // number of 32-bit lines in a buffer +#define RAM_NLINES 0x0200 // number of 32-bit lines in a buffer -#define buffer_pool_ram \ - ((uint32_t *) BUFFER_POOL_RAM_BASE) - -#define buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES]) +#define _router_ram ((uint32_t *) ROUTER_RAM_BASE) +#define router_ram(n) (&_router_ram[(n) * RAM_NLINES]) ///////////////////////////////////////////////////// @@ -162,13 +160,13 @@ typedef struct { #define gpio_base ((gpio_regs_t *) GPIO_BASE) /////////////////////////////////////////////////// -// Buffer Pool Status, Slave 5 +// Packet Router Status, Slave 5 // -// The buffers themselves are located in Slave 1, Buffer Pool RAM. -// The status registers are in Slave 5, Buffer Pool Status. +// The buffers themselves are located in Slave 1, Packet Router RAM. +// The status registers are in Slave 5, Packet Router Status. // The control register is in Slave 7, Settings Bus. -#define BUFFER_POOL_STATUS_BASE 0xCC00 +#define ROUTER_STATUS_BASE 0xCC00 typedef struct { volatile uint32_t _padding[8]; @@ -178,9 +176,9 @@ typedef struct { volatile uint32_t irqs; volatile uint32_t pri_enc_bp_status; volatile uint32_t cycle_count; -} buffer_pool_status_t; +} router_status_t; -#define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE) +#define router_status ((router_status_t *) ROUTER_STATUS_BASE) // The hw_config register @@ -193,7 +191,7 @@ typedef struct { inline static int hwconfig_simulation_p(void) { - return buffer_pool_status->hw_config & HWC_SIMULATION; + return router_status->hw_config & HWC_SIMULATION; } /*! @@ -203,7 +201,7 @@ hwconfig_simulation_p(void) inline static int hwconfig_wishbone_divisor(void) { - return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK; + return router_status->hw_config & HWC_WB_CLK_DIV_MASK; } /////////////////////////////////////////////////// @@ -225,13 +223,13 @@ hwconfig_wishbone_divisor(void) #define MISC_OUTPUT_BASE 0xD400 #define TX_PROTOCOL_ENGINE_BASE 0xD480 #define RX_PROTOCOL_ENGINE_BASE 0xD4C0 -#define BUFFER_POOL_CTRL_BASE 0xD500 +#define ROUTER_CTRL_BASE 0xD500 #define LAST_SETTING_REG 0xD7FC // last valid setting register #define SR_MISC 0 #define SR_TX_PROT_ENG 32 #define SR_RX_PROT_ENG 48 -#define SR_BUFFER_POOL_CTRL 64 +#define SR_ROUTER_CTRL 64 #define SR_UDP_SM 96 #define SR_TX_DSP 208 #define SR_TX_CTRL 224 @@ -243,18 +241,17 @@ hwconfig_wishbone_divisor(void) #define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) -// --- buffer pool control regs --- +// --- packet router control regs --- typedef struct { - volatile uint32_t misc_ctrl; + volatile uint32_t mode_ctrl; volatile uint32_t ip_addr; - volatile uint32_t ctrl_ports; //ctrl (low 16) other (high 16) volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16) volatile uint32_t cpu_out_ctrl; volatile uint32_t cpu_inp_ctrl; -} buffer_pool_ctrl_t; +} router_ctrl_t; -#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE) +#define router_ctrl ((router_ctrl_t *) ROUTER_CTRL_BASE) // --- misc outputs --- diff --git a/firmware/zpu/usrp2p/memory_map.h b/firmware/zpu/usrp2p/memory_map.h index 6f5c577e6..151c71237 100644 --- a/firmware/zpu/usrp2p/memory_map.h +++ b/firmware/zpu/usrp2p/memory_map.h @@ -38,20 +38,18 @@ //////////////////////////////////////////////////////////////// -// Buffer Pool RAM, Slave 1 +// Packet Router RAM, Slave 1 // -// The buffers themselves are located in Slave 1, Buffer Pool RAM. -// The status registers are in Slave 5, Buffer Pool Status. +// The buffers themselves are located in Slave 1, Packet Router RAM. +// The status registers are in Slave 5, Packet Router Status. // The control register is in Slave 7, Settings Bus. -#define BUFFER_POOL_RAM_BASE 0x4000 +#define ROUTER_RAM_BASE 0x4000 -#define BP_NLINES 0x0200 // number of 32-bit lines in a buffer +#define RAM_NLINES 0x0200 // number of 32-bit lines in a buffer -#define buffer_pool_ram \ - ((uint32_t *) BUFFER_POOL_RAM_BASE) - -#define buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES]) +#define _router_ram ((uint32_t *) ROUTER_RAM_BASE) +#define router_ram(n) (&_router_ram[(n) * RAM_NLINES]) ///////////////////////////////////////////////////// @@ -155,13 +153,13 @@ typedef struct { #define gpio_base ((gpio_regs_t *) GPIO_BASE) /////////////////////////////////////////////////// -// Buffer Pool Status, Slave 5 +// Packet Router Status, Slave 5 // -// The buffers themselves are located in Slave 1, Buffer Pool RAM. -// The status registers are in Slave 5, Buffer Pool Status. +// The buffers themselves are located in Slave 1, Packet Router RAM. +// The status registers are in Slave 5, Packet Router Status. // The control register is in Slave 7, Settings Bus. -#define BUFFER_POOL_STATUS_BASE 0x6300 +#define ROUTER_STATUS_BASE 0x6300 typedef struct { volatile uint32_t _padding[8]; @@ -171,11 +169,11 @@ typedef struct { volatile uint32_t irqs; volatile uint32_t pri_enc_bp_status; volatile uint32_t cycle_count; -} buffer_pool_status_t; +} router_status_t; -#define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE) +#define router_status ((router_status_t *) ROUTER_STATUS_BASE) -#define BUTTON_PUSHED ((buffer_pool_status->irqs & PIC_BUTTON) ? 0 : 1) +#define BUTTON_PUSHED ((router_status->irqs & PIC_BUTTON) ? 0 : 1) // The hw_config register @@ -188,7 +186,7 @@ typedef struct { inline static int hwconfig_simulation_p(void) { - return buffer_pool_status->hw_config & HWC_SIMULATION; + return router_status->hw_config & HWC_SIMULATION; } /*! @@ -198,7 +196,7 @@ hwconfig_simulation_p(void) inline static int hwconfig_wishbone_divisor(void) { - return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK; + return router_status->hw_config & HWC_WB_CLK_DIV_MASK; } /////////////////////////////////////////////////// @@ -222,7 +220,7 @@ hwconfig_wishbone_divisor(void) #define SR_MISC 0 #define SR_TX_PROT_ENG 32 #define SR_RX_PROT_ENG 48 -#define SR_BUFFER_POOL_CTRL 64 +#define SR_ROUTER_CTRL 64 #define SR_UDP_SM 96 #define SR_TX_DSP 208 #define SR_TX_CTRL 224 @@ -236,18 +234,17 @@ hwconfig_wishbone_divisor(void) #define SR_ADDR_BLDRDONE _SR_ADDR(5) -// --- buffer pool control regs --- +// --- packet router control regs --- typedef struct { - volatile uint32_t misc_ctrl; + volatile uint32_t mode_ctrl; volatile uint32_t ip_addr; - volatile uint32_t ctrl_ports; //ctrl (low 16) other (high 16) volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16) volatile uint32_t cpu_out_ctrl; volatile uint32_t cpu_inp_ctrl; -} buffer_pool_ctrl_t; +} router_ctrl_t; -#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) _SR_ADDR(SR_BUFFER_POOL_CTRL)) +#define router_ctrl ((router_ctrl_t *) _SR_ADDR(SR_ROUTER_CTRL)) // --- misc outputs --- -- cgit v1.2.3