From aa23e88769c572ab50ecc0460301790a03574729 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 8 Jul 2011 13:05:13 -0700 Subject: b100: fix for fpga syntax error on xfer_rate --- usrp2/top/B100/u1plus_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 3c861fe08..4683f653c 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -318,7 +318,7 @@ module u1plus_core reg_leds <= 0; reg_cgen_ctrl <= 2'b11; reg_test <= 0; - xfer_rate <= 0; + //xfer_rate <= 0; frames_per_packet <= 0; end else -- cgit v1.2.3 From dd6d11c2255c646a48ff0c866b74c80869d94eac Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 8 Jul 2011 09:46:29 -0700 Subject: dsp: reset the interpolator when the rate changes, to prevent oscillation --- usrp2/sdr_lib/dsp_core_tx.v | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v index f02c63b42..4e0163e0a 100644 --- a/usrp2/sdr_lib/dsp_core_tx.v +++ b/usrp2/sdr_lib/dsp_core_tx.v @@ -36,7 +36,8 @@ module dsp_core_tx wire [7:0] interp_rate; wire [3:0] dacmux_a, dacmux_b; wire enable_hb1, enable_hb2; - + wire rate_change; + setting_reg #(.my_addr(BASE+0)) sr_0 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_inc),.changed()); @@ -47,7 +48,7 @@ module dsp_core_tx setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed()); + .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change)); // Strobes are all now delayed by 1 cycle for timing reasons wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre; @@ -56,13 +57,13 @@ module dsp_core_tx reg strobe_hb2 = 1; cic_strober #(.WIDTH(8)) - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + cic_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate), .strobe_fast(1),.strobe_slow(strobe_cic_pre) ); cic_strober #(.WIDTH(2)) - hb2_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb2 ? 2 : 1), + hb2_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb2 ? 2 : 1), .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) ); cic_strober #(.WIDTH(2)) - hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb1 ? 2 : 1), + hb1_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb1 ? 2 : 1), .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) ); always @(posedge clk) strobe_hb1 <= strobe_hb1_pre; @@ -104,12 +105,12 @@ module dsp_core_tx .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q)); cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) - cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + cic_interp_i(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate), .strobe_in(strobe_cic),.strobe_out(1), .signal_in(hb2_i),.signal_out(i_interp)); cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) - cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + cic_interp_q(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate), .strobe_in(strobe_cic),.strobe_out(1), .signal_in(hb2_q),.signal_out(q_interp)); -- cgit v1.2.3 From 049376f205d560c98da779eee6903b8a8f71ebb5 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 18 Jul 2011 14:25:23 -0700 Subject: fpga: print timing report after generate bin file --- usrp2/top/Makefile.common | 5 ++++- usrp2/top/python/check_timing.py | 30 ++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100755 usrp2/top/python/check_timing.py diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index 6f855a070..3a35e71e7 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -1,5 +1,5 @@ # -# Copyright 2008, 2009, 2010 Ettus Research LLC +# Copyright 2008-2011 Ettus Research LLC # ################################################## @@ -14,10 +14,12 @@ endif BASE_DIR = $(abspath ..) ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py +TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs +TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr ################################################## # Global Targets @@ -35,6 +37,7 @@ synth: $(ISE_FILE) bin: check $(BIN_FILE) $(ISE_HELPER) "Generate Programming File" + $(TIMING_CHECKER) $(TWR_FILE) mcs: $(MCS_FILE) diff --git a/usrp2/top/python/check_timing.py b/usrp2/top/python/check_timing.py new file mode 100755 index 000000000..c57e889d0 --- /dev/null +++ b/usrp2/top/python/check_timing.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python +# +# Copyright 2011 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +import sys +import re + +def print_timing_constraint_summary(twr_file): + output = "" + keep = False + for line in open(twr_file).readlines(): + if 'Derived Constraint Report' in line: keep = True + if keep: output += line + if 'constraint' in line and 'met' in line: break + print("\n\n"+output) + +if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:]) -- cgit v1.2.3 From fea1298b21364deaff26d57973dd34ad0e13a12e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 18 Jul 2011 18:03:20 -0700 Subject: dsp: reduce bitwidth to help timing --- usrp2/sdr_lib/small_hb_dec.v | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/usrp2/sdr_lib/small_hb_dec.v b/usrp2/sdr_lib/small_hb_dec.v index a7f93e056..c05a48b81 100644 --- a/usrp2/sdr_lib/small_hb_dec.v +++ b/usrp2/sdr_lib/small_hb_dec.v @@ -103,22 +103,24 @@ module small_hb_dec wire [17:0] coeff = go_d1 ? coeff_b : coeff_a; wire [35:0] prod; MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) ); + + localparam ACCWIDTH = 30; + reg [ACCWIDTH-1:0] accum; - reg [35:0] accum; always @(posedge clk) if(rst) accum <= 0; else if(go_d2) - accum <= {middle_d1[17],middle_d1[17],middle_d1,16'd0} + {prod}; + accum <= {middle_d1[17],middle_d1[17],middle_d1,{(16+ACCWIDTH-36){1'b0}}} + {prod[35:36-ACCWIDTH]}; else if(go_d3) - accum <= accum + {prod}; + accum <= accum + {prod[35:36-ACCWIDTH]}; wire [WIDTH:0] accum_rnd; wire [WIDTH-1:0] accum_rnd_clip; wire stb_round; - round_sd #(.WIDTH_IN(36),.WIDTH_OUT(WIDTH+1)) round_acc + round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round)); clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip (.in(accum_rnd), .out(accum_rnd_clip)); -- cgit v1.2.3 From 374bf86dd1d11dd4165c8da0ce317194d17ba89a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 19 Jul 2011 10:32:27 -0700 Subject: N200: detailed map report allows you to see what takes up too much space --- usrp2/top/N2x0/Makefile.N200R3 | 1 + usrp2/top/N2x0/Makefile.N200R4 | 1 + usrp2/top/N2x0/Makefile.N210R3 | 1 + usrp2/top/N2x0/Makefile.N210R4 | 1 + 4 files changed, 4 insertions(+) diff --git a/usrp2/top/N2x0/Makefile.N200R3 b/usrp2/top/N2x0/Makefile.N200R3 index a525836ed..9ed5ece00 100644 --- a/usrp2/top/N2x0/Makefile.N200R3 +++ b/usrp2/top/N2x0/Makefile.N200R3 @@ -71,6 +71,7 @@ TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4 index 0ca40e1bd..f8640224f 100644 --- a/usrp2/top/N2x0/Makefile.N200R4 +++ b/usrp2/top/N2x0/Makefile.N200R4 @@ -73,6 +73,7 @@ TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3 index e29251e1c..2937dc409 100644 --- a/usrp2/top/N2x0/Makefile.N210R3 +++ b/usrp2/top/N2x0/Makefile.N210R3 @@ -71,6 +71,7 @@ TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 index 01a9e19fd..39a2508f9 100644 --- a/usrp2/top/N2x0/Makefile.N210R4 +++ b/usrp2/top/N2x0/Makefile.N210R4 @@ -73,6 +73,7 @@ TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ -- cgit v1.2.3 From dbeea34b66c939c15eaaa0a9f805ee9286d0a878 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 19 Jul 2011 10:29:57 -0700 Subject: removed wb readback of ATR, allowing it to be synthesized as luts --- usrp2/control_lib/atr_controller.v | 7 +++++-- usrp2/control_lib/atr_controller16.v | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v index 2cef8ba2b..1f8d75d00 100644 --- a/usrp2/control_lib/atr_controller.v +++ b/usrp2/control_lib/atr_controller.v @@ -44,8 +44,11 @@ module atr_controller atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; end // if (we_i & stb_i & cyc_i) - always @(posedge clk_i) - dat_o <= atr_ram[adr_i[5:2]]; + // Removing readback allows ram to be synthesized as LUTs instead of regs + //always @(posedge clk_i) + // dat_o <= atr_ram[adr_i[5:2]]; + always @* + dat_o <= 32'd0; always @(posedge clk_i) ack_o <= stb_i & cyc_i & ~ack_o; diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v index ff4f634c7..a2ebd1dde 100644 --- a/usrp2/control_lib/atr_controller16.v +++ b/usrp2/control_lib/atr_controller16.v @@ -47,8 +47,11 @@ module atr_controller16 atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; end // if (we_i & stb_i & cyc_i) - always @(posedge clk_i) - dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + // Removing readback allows ram to be synthesized as LUTs instead of regs + //always @(posedge clk_i) + // dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + always @* + dat_o <= 16'd0; always @(posedge clk_i) ack_o <= stb_i & cyc_i & ~ack_o; -- cgit v1.2.3 From 7e085dae07589a6d8f926c8bcb8ae811f4debdd2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 19 Jul 2011 11:40:11 -0700 Subject: appease the ISE gods --- usrp2/control_lib/atr_controller.v | 2 +- usrp2/control_lib/atr_controller16.v | 2 +- usrp2/top/B100/Makefile | 1 + usrp2/top/E1x0/Makefile | 1 + usrp2/top/USRP2/Makefile | 1 + 5 files changed, 5 insertions(+), 2 deletions(-) diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v index 1f8d75d00..ee8b260c5 100644 --- a/usrp2/control_lib/atr_controller.v +++ b/usrp2/control_lib/atr_controller.v @@ -47,7 +47,7 @@ module atr_controller // Removing readback allows ram to be synthesized as LUTs instead of regs //always @(posedge clk_i) // dat_o <= atr_ram[adr_i[5:2]]; - always @* + always dat_o <= 32'd0; always @(posedge clk_i) diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v index a2ebd1dde..727f8c630 100644 --- a/usrp2/control_lib/atr_controller16.v +++ b/usrp2/control_lib/atr_controller16.v @@ -50,7 +50,7 @@ module atr_controller16 // Removing readback allows ram to be synthesized as LUTs instead of regs //always @(posedge clk_i) // dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; - always @* + always dat_o <= 16'd0; always @(posedge clk_i) diff --git a/usrp2/top/B100/Makefile b/usrp2/top/B100/Makefile index ca6ec9320..7ab56f9bd 100644 --- a/usrp2/top/B100/Makefile +++ b/usrp2/top/B100/Makefile @@ -69,6 +69,7 @@ TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ diff --git a/usrp2/top/E1x0/Makefile b/usrp2/top/E1x0/Makefile index 5d721979b..19fb93ebf 100644 --- a/usrp2/top/E1x0/Makefile +++ b/usrp2/top/E1x0/Makefile @@ -72,6 +72,7 @@ TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile index e9b43491a..8ebb43639 100644 --- a/usrp2/top/USRP2/Makefile +++ b/usrp2/top/USRP2/Makefile @@ -71,6 +71,7 @@ TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ -- cgit v1.2.3 From 0f50e9de3a2bb65b170aa5d1e450ce7996ce0ec3 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 19 Jul 2011 13:33:21 -0700 Subject: usrp2: split inspection logic into each relevant cycle --- usrp2/fifo/packet_dispatcher36_x3.v | 46 ++++++++++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 11 deletions(-) diff --git a/usrp2/fifo/packet_dispatcher36_x3.v b/usrp2/fifo/packet_dispatcher36_x3.v index fd762d061..0f9e752c8 100644 --- a/usrp2/fifo/packet_dispatcher36_x3.v +++ b/usrp2/fifo/packet_dispatcher36_x3.v @@ -93,13 +93,12 @@ module packet_dispatcher36_x3 wire pd_dreg_counter_done = (pd_dreg_count_next == PD_MAX_NUM_DREGS)? 1'b1 : 1'b0; reg [35:0] pd_dregs [PD_MAX_NUM_DREGS-1:0]; - //extract various packet components: - wire [47:0] pd_dregs_eth_dst_mac = {pd_dregs[0][15:0], pd_dregs[1][31:0]}; - wire [15:0] pd_dregs_eth_type = pd_dregs[3][15:0]; - wire [7:0] pd_dregs_ipv4_proto = pd_dregs[6][23:16]; - wire [31:0] pd_dregs_ipv4_dst_addr = pd_dregs[8][31:0]; - wire [15:0] pd_dregs_udp_dst_port = pd_dregs[9][15:0]; - wire [15:0] pd_dregs_vrt_size = com_inp_data[15:0]; + reg is_eth_dst_mac_bcast; + reg is_eth_type_ipv4; + reg is_eth_ipv4_proto_udp; + reg is_eth_ipv4_dst_addr_here; + reg is_eth_udp_dst_port_here; + wire is_vrt_size_zero = (com_inp_data[15:0] == 16'h0); //needed on the same cycle, so it cant be registered //Inspector output flags special case: //Inject SOF into flags at first DSP line. @@ -150,6 +149,31 @@ module packet_dispatcher36_x3 (pd_state == PD_STATE_WRITE_LIVE) ? pd_out_ready : ( 1'b0))); + //inspect the incoming data and mark register booleans + always @(posedge clk) + if (com_inp_ready & com_inp_valid) begin + case(pd_dreg_count) + 0: begin + is_eth_dst_mac_bcast <= (com_inp_data[15:0] == 16'hffff); + end + 1: begin + is_eth_dst_mac_bcast <= is_eth_dst_mac_bcast && (com_inp_data[31:0] == 32'hffffffff); + end + 3: begin + is_eth_type_ipv4 <= (com_inp_data[15:0] == 16'h800); + end + 6: begin + is_eth_ipv4_proto_udp <= (com_inp_data[23:16] == 8'h11); + end + 8: begin + is_eth_ipv4_dst_addr_here <= (com_inp_data[31:0] == my_ip_addr); + end + 9: begin + is_eth_udp_dst_port_here <= (com_inp_data[15:0] == dsp_udp_port); + end + endcase //pd_dreg_count + end + always @(posedge clk) if(rst | clr) begin pd_state <= PD_STATE_READ_COM_PRE; @@ -175,19 +199,19 @@ module packet_dispatcher36_x3 //---------- begin inspection decision -----------// //EOF or bcast or not IPv4 or not UDP: if ( - com_inp_data[33] || (pd_dregs_eth_dst_mac == 48'hffffffffffff) || - (pd_dregs_eth_type != 16'h800) || (pd_dregs_ipv4_proto != 8'h11) + com_inp_data[33] || is_eth_dst_mac_bcast || + ~is_eth_type_ipv4 || ~is_eth_ipv4_proto_udp ) begin pd_dest <= PD_DEST_BOF; end //not my IP address: - else if (pd_dregs_ipv4_dst_addr != my_ip_addr) begin + else if (~is_eth_ipv4_dst_addr_here) begin pd_dest <= PD_DEST_EXT; end //UDP data port and VRT: - else if ((pd_dregs_udp_dst_port == dsp_udp_port) && (pd_dregs_vrt_size != 16'h0)) begin + else if (is_eth_udp_dst_port_here && ~is_vrt_size_zero) begin pd_dest <= PD_DEST_DSP; pd_dreg_count <= PD_DREGS_DSP_OFFSET; end -- cgit v1.2.3