From 38ec062b628e39397999d86fb3a68438aa586d5a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 15 Jul 2012 22:50:19 -0700 Subject: e100: offset gpmc to fifo writes by 2 transfers This effectivly works around bus initial transaction issues. --- usrp2/gpmc/gpmc_to_fifo.v | 8 ++++---- usrp2/top/E1x0/u1e_core.v | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v index 4aa55953a..cfc5aaa8b 100644 --- a/usrp2/gpmc/gpmc_to_fifo.v +++ b/usrp2/gpmc/gpmc_to_fifo.v @@ -70,9 +70,9 @@ module gpmc_to_fifo case(gpmc_state) GPMC_STATE_START: begin - if (EM_A == 0) begin + if (EM_A == 2) begin gpmc_state <= GPMC_STATE_FILL; - last_addr <= {EM_D[ADDR_WIDTH-2:0], 1'b0} - 1'b1; + last_addr <= {EM_D[ADDR_WIDTH-2:0], 1'b0} - 1'b1 + 2; next_gpmc_ptr <= gpmc_ptr + 1; end end @@ -116,14 +116,14 @@ module gpmc_to_fifo if (reset | clear) begin fifo_state <= FIFO_STATE_CLAIM; fifo_ptr <= 0; - counter <= 0; + counter <= 2; end else begin case(fifo_state) FIFO_STATE_CLAIM: begin if (bram_available_to_empty) fifo_state <= FIFO_STATE_EMPTY; - counter <= 0; + counter <= 2; end FIFO_STATE_EMPTY: begin diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index e3d1656a6..bd19d6076 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -454,7 +454,7 @@ module u1e_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd2}; //major, minor + localparam compat_num = {16'd9, 16'd3}; //major, minor wire [31:0] reg_test32; -- cgit v1.2.3