From 16f33c73b3a3303d183ebaabcb5fe968bb31c4e8 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 28 Jul 2011 12:08:23 -0700
Subject: vrt: delay the late signal to help with timing

---
 usrp2/vrt/vita_rx_control.v | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v
index b6b55d9d0..daec734a8 100644
--- a/usrp2/vrt/vita_rx_control.v
+++ b/usrp2/vrt/vita_rx_control.v
@@ -121,10 +121,19 @@ module vita_rx_control
    time_compare 
      time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late));
    
-   wire too_late 	    = late & ~send_imm;
    wire go_now 		    = now | send_imm;
    wire full 		    = ~sample_fifo_in_rdy;
    
+   reg 	too_late;
+
+   always @(posedge clk)
+     if(reset | clear)
+       too_late <= 0;
+     else
+       too_late <= late & ~send_imm;
+
+   reg 	late_valid;
+   
    always @(posedge clk)
      if(reset | clear)
        begin
@@ -135,6 +144,7 @@ module vita_rx_control
 	  send_imm 	   <= 0;
 	  chain 	   <= 0;
 	  reload	   <= 0;
+	  late_valid       <= 0;
        end
      else
        case(ibs_state)
@@ -144,6 +154,7 @@ module vita_rx_control
 		lines_left <= numlines_pre;
 		lines_total <= numlines_pre;
 		rcvtime <= rcvtime_pre;
+		late_valid <= 0;
 		if(stop_pre)
 		  ibs_state <= IBS_ZEROLEN;
 		else
@@ -153,10 +164,14 @@ module vita_rx_control
 		reload <= reload_pre;
 	     end
 	 IBS_WAITING :
-	   if(go_now)
-	     ibs_state <= IBS_RUNNING;
-	   else if(too_late)
-	     ibs_state <= IBS_LATECMD;
+	   begin
+	      late_valid <= 1;
+	      if(late_valid)
+		if(go_now)
+		  ibs_state <= IBS_RUNNING;
+		else if(too_late)
+		  ibs_state <= IBS_LATECMD;
+	   end
 	 IBS_RUNNING :
 	   if(strobe)
 	     if(full)
-- 
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