From 4f523681b7e786694969bcb7bfddb68b976c8ab7 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Thu, 3 Aug 2006 04:51:51 +0000 Subject: Houston, we have a trunk. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.am | 24 + Makefile.extra | 150 + TODO | 23 + gen_makefile_extra.py | 67 + megacells/accum32.bsf | 86 + megacells/accum32.cmp | 31 + megacells/accum32.inc | 32 + megacells/accum32.v | 765 +++++ megacells/accum32_bb.v | 35 + megacells/accum32_inst.v | 7 + megacells/add32.bsf | 62 + megacells/add32.cmp | 29 + megacells/add32.inc | 30 + megacells/add32.v | 221 ++ megacells/add32_bb.v | 31 + megacells/add32_inst.v | 5 + megacells/addsub16.bsf | 96 + megacells/addsub16.cmp | 33 + megacells/addsub16.inc | 34 + megacells/addsub16.v | 438 +++ megacells/addsub16_bb.v | 39 + megacells/addsub16_inst.v | 9 + megacells/bustri.bsf | 62 + megacells/bustri.cmp | 29 + megacells/bustri.inc | 30 + megacells/bustri.v | 71 + megacells/bustri_bb.v | 31 + megacells/bustri_inst.v | 5 + megacells/clk_doubler.v | 198 ++ megacells/clk_doubler_bb.v | 143 + megacells/dspclkpll.v | 237 ++ megacells/dspclkpll_bb.v | 31 + megacells/fifo_2k.v | 3343 +++++++++++++++++++ megacells/fifo_2k_bb.v | 131 + megacells/fifo_4k.v | 3495 ++++++++++++++++++++ megacells/fifo_4k_bb.v | 131 + megacells/mylpm_addsub.bsf | 80 + megacells/mylpm_addsub.cmp | 31 + megacells/mylpm_addsub.inc | 32 + megacells/mylpm_addsub.v | 102 + megacells/mylpm_addsub_bb.v | 35 + megacells/mylpm_addsub_inst.v | 7 + megacells/pll.v | 207 ++ megacells/pll_bb.v | 29 + megacells/pll_inst.v | 4 + megacells/sub32.bsf | 87 + megacells/sub32.cmp | 32 + megacells/sub32.inc | 33 + megacells/sub32.v | 675 ++++ megacells/sub32_bb.v | 37 + megacells/sub32_inst.v | 8 + models/bustri.v | 17 + models/fifo.v | 81 + models/fifo_1c_1k.v | 81 + models/fifo_1c_2k.v | 81 + models/fifo_1c_4k.v | 76 + models/fifo_1k.v | 24 + models/fifo_2k.v | 24 + models/fifo_4k.v | 24 + models/pll.v | 33 + models/ssram.v | 38 + rbf/Makefile.am | 49 + rbf/rev2/multi_2rxhb_2tx.rbf | Bin 0 -> 180809 bytes rbf/rev2/multi_4rx_0tx.rbf | Bin 0 -> 180537 bytes rbf/rev2/std_2rxhb_2tx.rbf | Bin 0 -> 175896 bytes rbf/rev2/std_4rx_0tx.rbf | Bin 0 -> 171213 bytes rbf/rev4/multi_2rxhb_2tx.rbf | Bin 0 -> 180809 bytes rbf/rev4/multi_4rx_0tx.rbf | Bin 0 -> 180537 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 0 -> 175896 bytes rbf/rev4/std_4rx_0tx.rbf | Bin 0 -> 171213 bytes sdr_lib/adc_interface.v | 71 + sdr_lib/bidir_reg.v | 29 + sdr_lib/bus_interface.v | 213 ++ sdr_lib/cic_decim.v | 106 + sdr_lib/cic_int_shifter.v | 98 + sdr_lib/cic_interp.v | 88 + sdr_lib/clk_divider.v | 43 + sdr_lib/cordic.v | 109 + sdr_lib/cordic_stage.v | 60 + sdr_lib/ddc.v | 97 + sdr_lib/dpram.v | 47 + sdr_lib/duc.v | 95 + sdr_lib/ext_fifo.v | 126 + sdr_lib/gen_cordic_consts.py | 10 + sdr_lib/gen_sync.v | 43 + sdr_lib/hb/acc.v | 22 + sdr_lib/hb/coeff_ram.v | 26 + sdr_lib/hb/coeff_rom.v | 19 + sdr_lib/hb/halfband_decim.v | 163 + sdr_lib/hb/halfband_interp.v | 121 + sdr_lib/hb/hbd_tb/HBD | 80 + sdr_lib/hb/hbd_tb/really_golden | 142 + sdr_lib/hb/hbd_tb/regression | 95 + sdr_lib/hb/hbd_tb/run_hbd | 4 + sdr_lib/hb/hbd_tb/test_hbd.v | 75 + sdr_lib/hb/mac.v | 58 + sdr_lib/hb/mult.v | 16 + sdr_lib/hb/ram16_2port.v | 22 + sdr_lib/hb/ram16_2sum.v | 27 + sdr_lib/hb/ram32_2sum.v | 22 + sdr_lib/io_pins.v | 52 + sdr_lib/master_control.v | 155 + sdr_lib/master_control_multi.v | 73 + sdr_lib/phase_acc.v | 52 + sdr_lib/ram.v | 16 + sdr_lib/ram16.v | 17 + sdr_lib/ram32.v | 17 + sdr_lib/ram64.v | 16 + sdr_lib/rssi.v | 30 + sdr_lib/rx_buffer.v | 182 + sdr_lib/rx_chain.v | 105 + sdr_lib/rx_chain_dual.v | 103 + sdr_lib/rx_dcoffset.v | 22 + sdr_lib/serial_io.v | 118 + sdr_lib/setting_reg.v | 23 + sdr_lib/setting_reg_masked.v | 26 + sdr_lib/sign_extend.v | 35 + sdr_lib/strobe_gen.v | 44 + sdr_lib/tx_buffer.v | 138 + sdr_lib/tx_chain.v | 65 + sdr_lib/tx_chain_hb.v | 76 + tb/cbus_tb.v | 71 + tb/cordic_tb.v | 61 + tb/decim_tb.v | 108 + tb/fullchip_tb.v | 174 + tb/interp_tb.v | 108 + tb/justinterp_tb.v | 73 + tb/makesine.pl | 14 + tb/run_cordic | 4 + tb/run_fullchip | 4 + tb/usrp_tasks.v | 145 + toplevel/mrfm/biquad_2stage.v | 131 + toplevel/mrfm/biquad_6stage.v | 137 + toplevel/mrfm/mrfm.csf | 444 +++ toplevel/mrfm/mrfm.esf | 14 + toplevel/mrfm/mrfm.psf | 312 ++ toplevel/mrfm/mrfm.py | 129 + toplevel/mrfm/mrfm.qpf | 29 + toplevel/mrfm/mrfm.qsf | 411 +++ toplevel/mrfm/mrfm.v | 199 ++ toplevel/mrfm/mrfm.vh | 21 + toplevel/mrfm/mrfm_compensator.v | 80 + toplevel/mrfm/mrfm_fft.py | 319 ++ toplevel/mrfm/mrfm_proc.v | 96 + toplevel/mrfm/shifter.v | 106 + toplevel/sizetest/sizetest.csf | 160 + toplevel/sizetest/sizetest.psf | 228 ++ toplevel/sizetest/sizetest.quartus | 19 + toplevel/sizetest/sizetest.ssf | 14 + toplevel/sizetest/sizetest.v | 39 + toplevel/usrp_multi/usrp_multi.csf | 444 +++ toplevel/usrp_multi/usrp_multi.esf | 14 + toplevel/usrp_multi/usrp_multi.psf | 312 ++ toplevel/usrp_multi/usrp_multi.qpf | 29 + toplevel/usrp_multi/usrp_multi.qsf | 408 +++ toplevel/usrp_multi/usrp_multi.v | 379 +++ toplevel/usrp_multi/usrp_multi.vh | 141 + toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh | 62 + toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh | 62 + toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh | 62 + toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh | 62 + toplevel/usrp_multi/usrp_std.vh | 29 + toplevel/usrp_std/usrp_std.csf | 444 +++ toplevel/usrp_std/usrp_std.esf | 14 + toplevel/usrp_std/usrp_std.psf | 312 ++ toplevel/usrp_std/usrp_std.qpf | 29 + toplevel/usrp_std/usrp_std.qsf | 406 +++ toplevel/usrp_std/usrp_std.v | 324 ++ toplevel/usrp_std/usrp_std.vh | 119 + toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh | 61 + toplevel/usrp_std/usrp_std_config_4rx_0tx.vh | 61 + 171 files changed, 23027 insertions(+) create mode 100644 Makefile.am create mode 100644 Makefile.extra create mode 100644 TODO create mode 100755 gen_makefile_extra.py create mode 100755 megacells/accum32.bsf create mode 100755 megacells/accum32.cmp create mode 100755 megacells/accum32.inc create mode 100755 megacells/accum32.v create mode 100755 megacells/accum32_bb.v create mode 100755 megacells/accum32_inst.v create mode 100755 megacells/add32.bsf create mode 100755 megacells/add32.cmp create mode 100755 megacells/add32.inc create mode 100755 megacells/add32.v create mode 100755 megacells/add32_bb.v create mode 100755 megacells/add32_inst.v create mode 100755 megacells/addsub16.bsf create mode 100755 megacells/addsub16.cmp create mode 100755 megacells/addsub16.inc create mode 100755 megacells/addsub16.v create mode 100755 megacells/addsub16_bb.v create mode 100755 megacells/addsub16_inst.v create mode 100755 megacells/bustri.bsf create mode 100755 megacells/bustri.cmp create mode 100755 megacells/bustri.inc create mode 100755 megacells/bustri.v create mode 100755 megacells/bustri_bb.v create mode 100755 megacells/bustri_inst.v create mode 100644 megacells/clk_doubler.v create mode 100644 megacells/clk_doubler_bb.v create mode 100644 megacells/dspclkpll.v create mode 100644 megacells/dspclkpll_bb.v create mode 100644 megacells/fifo_2k.v create mode 100644 megacells/fifo_2k_bb.v create mode 100644 megacells/fifo_4k.v create mode 100644 megacells/fifo_4k_bb.v create mode 100755 megacells/mylpm_addsub.bsf create mode 100755 megacells/mylpm_addsub.cmp create mode 100755 megacells/mylpm_addsub.inc create mode 100755 megacells/mylpm_addsub.v create mode 100755 megacells/mylpm_addsub_bb.v create mode 100755 megacells/mylpm_addsub_inst.v create mode 100644 megacells/pll.v create mode 100644 megacells/pll_bb.v create mode 100644 megacells/pll_inst.v create mode 100755 megacells/sub32.bsf create mode 100755 megacells/sub32.cmp create mode 100755 megacells/sub32.inc create mode 100755 megacells/sub32.v create mode 100755 megacells/sub32_bb.v create mode 100755 megacells/sub32_inst.v create mode 100644 models/bustri.v create mode 100644 models/fifo.v create mode 100644 models/fifo_1c_1k.v create mode 100644 models/fifo_1c_2k.v create mode 100644 models/fifo_1c_4k.v create mode 100644 models/fifo_1k.v create mode 100644 models/fifo_2k.v create mode 100644 models/fifo_4k.v create mode 100644 models/pll.v create mode 100644 models/ssram.v create mode 100644 rbf/Makefile.am create mode 100755 rbf/rev2/multi_2rxhb_2tx.rbf create mode 100755 rbf/rev2/multi_4rx_0tx.rbf create mode 100755 rbf/rev2/std_2rxhb_2tx.rbf create mode 100755 rbf/rev2/std_4rx_0tx.rbf create mode 100755 rbf/rev4/multi_2rxhb_2tx.rbf create mode 100755 rbf/rev4/multi_4rx_0tx.rbf create mode 100755 rbf/rev4/std_2rxhb_2tx.rbf create mode 100755 rbf/rev4/std_4rx_0tx.rbf create mode 100644 sdr_lib/adc_interface.v create mode 100644 sdr_lib/bidir_reg.v create mode 100755 sdr_lib/bus_interface.v create mode 100755 sdr_lib/cic_decim.v create mode 100644 sdr_lib/cic_int_shifter.v create mode 100755 sdr_lib/cic_interp.v create mode 100755 sdr_lib/clk_divider.v create mode 100755 sdr_lib/cordic.v create mode 100755 sdr_lib/cordic_stage.v create mode 100755 sdr_lib/ddc.v create mode 100644 sdr_lib/dpram.v create mode 100755 sdr_lib/duc.v create mode 100644 sdr_lib/ext_fifo.v create mode 100755 sdr_lib/gen_cordic_consts.py create mode 100644 sdr_lib/gen_sync.v create mode 100644 sdr_lib/hb/acc.v create mode 100644 sdr_lib/hb/coeff_ram.v create mode 100644 sdr_lib/hb/coeff_rom.v create mode 100644 sdr_lib/hb/halfband_decim.v create mode 100644 sdr_lib/hb/halfband_interp.v create mode 100644 sdr_lib/hb/hbd_tb/HBD create mode 100644 sdr_lib/hb/hbd_tb/really_golden create mode 100644 sdr_lib/hb/hbd_tb/regression create mode 100755 sdr_lib/hb/hbd_tb/run_hbd create mode 100644 sdr_lib/hb/hbd_tb/test_hbd.v create mode 100644 sdr_lib/hb/mac.v create mode 100644 sdr_lib/hb/mult.v create mode 100644 sdr_lib/hb/ram16_2port.v create mode 100644 sdr_lib/hb/ram16_2sum.v create mode 100644 sdr_lib/hb/ram32_2sum.v create mode 100644 sdr_lib/io_pins.v create mode 100644 sdr_lib/master_control.v create mode 100644 sdr_lib/master_control_multi.v create mode 100755 sdr_lib/phase_acc.v create mode 100644 sdr_lib/ram.v create mode 100644 sdr_lib/ram16.v create mode 100644 sdr_lib/ram32.v create mode 100644 sdr_lib/ram64.v create mode 100644 sdr_lib/rssi.v create mode 100644 sdr_lib/rx_buffer.v create mode 100644 sdr_lib/rx_chain.v create mode 100644 sdr_lib/rx_chain_dual.v create mode 100644 sdr_lib/rx_dcoffset.v create mode 100644 sdr_lib/serial_io.v create mode 100644 sdr_lib/setting_reg.v create mode 100644 sdr_lib/setting_reg_masked.v create mode 100644 sdr_lib/sign_extend.v create mode 100644 sdr_lib/strobe_gen.v create mode 100644 sdr_lib/tx_buffer.v create mode 100644 sdr_lib/tx_chain.v create mode 100644 sdr_lib/tx_chain_hb.v create mode 100644 tb/cbus_tb.v create mode 100644 tb/cordic_tb.v create mode 100644 tb/decim_tb.v create mode 100755 tb/fullchip_tb.v create mode 100755 tb/interp_tb.v create mode 100644 tb/justinterp_tb.v create mode 100755 tb/makesine.pl create mode 100755 tb/run_cordic create mode 100755 tb/run_fullchip create mode 100755 tb/usrp_tasks.v create mode 100644 toplevel/mrfm/biquad_2stage.v create mode 100644 toplevel/mrfm/biquad_6stage.v create mode 100644 toplevel/mrfm/mrfm.csf create mode 100644 toplevel/mrfm/mrfm.esf create mode 100644 toplevel/mrfm/mrfm.psf create mode 100644 toplevel/mrfm/mrfm.py create mode 100644 toplevel/mrfm/mrfm.qpf create mode 100644 toplevel/mrfm/mrfm.qsf create mode 100644 toplevel/mrfm/mrfm.v create mode 100644 toplevel/mrfm/mrfm.vh create mode 100644 toplevel/mrfm/mrfm_compensator.v create mode 100755 toplevel/mrfm/mrfm_fft.py create mode 100644 toplevel/mrfm/mrfm_proc.v create mode 100644 toplevel/mrfm/shifter.v create mode 100644 toplevel/sizetest/sizetest.csf create mode 100644 toplevel/sizetest/sizetest.psf create mode 100644 toplevel/sizetest/sizetest.quartus create mode 100644 toplevel/sizetest/sizetest.ssf create mode 100644 toplevel/sizetest/sizetest.v create mode 100644 toplevel/usrp_multi/usrp_multi.csf create mode 100644 toplevel/usrp_multi/usrp_multi.esf create mode 100644 toplevel/usrp_multi/usrp_multi.psf create mode 100644 toplevel/usrp_multi/usrp_multi.qpf create mode 100644 toplevel/usrp_multi/usrp_multi.qsf create mode 100644 toplevel/usrp_multi/usrp_multi.v create mode 100644 toplevel/usrp_multi/usrp_multi.vh create mode 100644 toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh create mode 100644 toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh create mode 100644 toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh create mode 100644 toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh create mode 100644 toplevel/usrp_multi/usrp_std.vh create mode 100644 toplevel/usrp_std/usrp_std.csf create mode 100644 toplevel/usrp_std/usrp_std.esf create mode 100644 toplevel/usrp_std/usrp_std.psf create mode 100644 toplevel/usrp_std/usrp_std.qpf create mode 100644 toplevel/usrp_std/usrp_std.qsf create mode 100644 toplevel/usrp_std/usrp_std.v create mode 100644 toplevel/usrp_std/usrp_std.vh create mode 100644 toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh create mode 100644 toplevel/usrp_std/usrp_std_config_4rx_0tx.vh diff --git a/Makefile.am b/Makefile.am new file mode 100644 index 000000000..61227f056 --- /dev/null +++ b/Makefile.am @@ -0,0 +1,24 @@ +# +# Copyright 2004,2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# + +SUBDIRS = rbf + +include Makefile.extra diff --git a/Makefile.extra b/Makefile.extra new file mode 100644 index 000000000..c3ccaa043 --- /dev/null +++ b/Makefile.extra @@ -0,0 +1,150 @@ +EXTRA_DIST = \ + gen_makefile_extra.py \ + megacells/accum32.bsf \ + megacells/accum32.cmp \ + megacells/accum32.inc \ + megacells/accum32.v \ + megacells/accum32_bb.v \ + megacells/accum32_inst.v \ + megacells/add32.bsf \ + megacells/add32.cmp \ + megacells/add32.inc \ + megacells/add32.v \ + megacells/add32_bb.v \ + megacells/add32_inst.v \ + megacells/addsub16.bsf \ + megacells/addsub16.cmp \ + megacells/addsub16.inc \ + megacells/addsub16.v \ + megacells/addsub16_bb.v \ + megacells/addsub16_inst.v \ + megacells/bustri.bsf \ + megacells/bustri.cmp \ + megacells/bustri.inc \ + megacells/bustri.v \ + megacells/bustri_bb.v \ + megacells/bustri_inst.v \ + megacells/clk_doubler.v \ + megacells/clk_doubler_bb.v \ + megacells/dspclkpll.v \ + megacells/dspclkpll_bb.v \ + megacells/fifo_2k.v \ + megacells/fifo_2k_bb.v \ + megacells/fifo_4k.v \ + megacells/fifo_4k_bb.v \ + megacells/mylpm_addsub.bsf \ + megacells/mylpm_addsub.cmp \ + megacells/mylpm_addsub.inc \ + megacells/mylpm_addsub.v \ + megacells/mylpm_addsub_bb.v \ + megacells/mylpm_addsub_inst.v \ + megacells/pll.v \ + megacells/pll_bb.v \ + megacells/pll_inst.v \ + megacells/sub32.bsf \ + megacells/sub32.cmp \ + megacells/sub32.inc \ + megacells/sub32.v \ + megacells/sub32_bb.v \ + megacells/sub32_inst.v \ + models/bustri.v \ + models/fifo.v \ + models/fifo_1c_1k.v \ + models/fifo_1c_2k.v \ + models/fifo_1c_4k.v \ + models/fifo_1k.v \ + models/fifo_2k.v \ + models/fifo_4k.v \ + models/pll.v \ + models/ssram.v \ + sdr_lib/adc_interface.v \ + sdr_lib/bidir_reg.v \ + sdr_lib/bus_interface.v \ + sdr_lib/cic_decim.v \ + sdr_lib/cic_int_shifter.v \ + sdr_lib/cic_interp.v \ + sdr_lib/clk_divider.v \ + sdr_lib/cordic.v \ + sdr_lib/cordic_stage.v \ + sdr_lib/ddc.v \ + sdr_lib/dpram.v \ + sdr_lib/duc.v \ + sdr_lib/ext_fifo.v \ + sdr_lib/gen_cordic_consts.py \ + sdr_lib/gen_sync.v \ + sdr_lib/hb/acc.v \ + sdr_lib/hb/coeff_ram.v \ + sdr_lib/hb/coeff_rom.v \ + sdr_lib/hb/halfband_decim.v \ + sdr_lib/hb/halfband_interp.v \ + sdr_lib/hb/hbd_tb/test_hbd.v \ + sdr_lib/hb/mac.v \ + sdr_lib/hb/mult.v \ + sdr_lib/hb/ram16_2port.v \ + sdr_lib/hb/ram16_2sum.v \ + sdr_lib/hb/ram32_2sum.v \ + sdr_lib/io_pins.v \ + sdr_lib/master_control.v \ + sdr_lib/master_control_multi.v \ + sdr_lib/phase_acc.v \ + sdr_lib/ram.v \ + sdr_lib/ram16.v \ + sdr_lib/ram32.v \ + sdr_lib/ram64.v \ + sdr_lib/rx_buffer.v \ + sdr_lib/rx_chain.v \ + sdr_lib/rx_chain_dual.v \ + sdr_lib/rx_dcoffset.v \ + sdr_lib/serial_io.v \ + sdr_lib/setting_reg.v \ + sdr_lib/setting_reg_masked.v \ + sdr_lib/sign_extend.v \ + sdr_lib/strobe_gen.v \ + sdr_lib/tx_buffer.v \ + sdr_lib/tx_chain.v \ + sdr_lib/tx_chain_hb.v \ + tb/cbus_tb.v \ + tb/cordic_tb.v \ + tb/decim_tb.v \ + tb/fullchip_tb.v \ + tb/interp_tb.v \ + tb/justinterp_tb.v \ + tb/usrp_tasks.v \ + toplevel/mrfm/biquad_2stage.v \ + toplevel/mrfm/biquad_6stage.v \ + toplevel/mrfm/mrfm.csf \ + toplevel/mrfm/mrfm.esf \ + toplevel/mrfm/mrfm.psf \ + toplevel/mrfm/mrfm.py \ + toplevel/mrfm/mrfm.qpf \ + toplevel/mrfm/mrfm.qsf \ + toplevel/mrfm/mrfm.v \ + toplevel/mrfm/mrfm.vh \ + toplevel/mrfm/mrfm_compensator.v \ + toplevel/mrfm/mrfm_fft.py \ + toplevel/mrfm/mrfm_proc.v \ + toplevel/mrfm/shifter.v \ + toplevel/sizetest/sizetest.csf \ + toplevel/sizetest/sizetest.psf \ + toplevel/sizetest/sizetest.v \ + toplevel/usrp_multi/usrp_multi.csf \ + toplevel/usrp_multi/usrp_multi.esf \ + toplevel/usrp_multi/usrp_multi.psf \ + toplevel/usrp_multi/usrp_multi.qpf \ + toplevel/usrp_multi/usrp_multi.qsf \ + toplevel/usrp_multi/usrp_multi.v \ + toplevel/usrp_multi/usrp_multi.vh \ + toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh \ + toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh \ + toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh \ + toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh \ + toplevel/usrp_multi/usrp_std.vh \ + toplevel/usrp_std/usrp_std.csf \ + toplevel/usrp_std/usrp_std.esf \ + toplevel/usrp_std/usrp_std.psf \ + toplevel/usrp_std/usrp_std.qpf \ + toplevel/usrp_std/usrp_std.qsf \ + toplevel/usrp_std/usrp_std.v \ + toplevel/usrp_std/usrp_std.vh \ + toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh \ + toplevel/usrp_std/usrp_std_config_4rx_0tx.vh diff --git a/TODO b/TODO new file mode 100644 index 000000000..76287c3d4 --- /dev/null +++ b/TODO @@ -0,0 +1,23 @@ + + +Area Reduction +============== +Reduce one or both stages of dec/interp to max rate of 8 instead of 16 +Optimize CICs to minimize registers +Reduce width of RX CORDIC +Fix CORDIC wasted logic cells from bad synthesis +Progressively narrow x,y,z on CORDIC +16-bit wide FIFOs, split IQ/channels on other side (?) + +Enhancements +============ +Halfband filter in Spartan 3 +Muxing of inputs +Switch over to newfc +RAM interface? + +Other +===== +Capture/Transmit straight samples (no DUC/DDC) + + diff --git a/gen_makefile_extra.py b/gen_makefile_extra.py new file mode 100755 index 000000000..165a84940 --- /dev/null +++ b/gen_makefile_extra.py @@ -0,0 +1,67 @@ +#!/usr/bin/env python +# +# Copyright 2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# + +""" +Generate Makefile.extra +""" + +import sys +import os.path + +extensions_we_like = ( + '.v', '.vh', + '.csf', '.esf', '.psf', '.qpf', '.qsf', + '.inc', '.cmp', '.bsf', + '.py') + +def visit(keepers, dirname, names): + if 'rbf' in names: + names.remove('rbf') + if 'CVS' in names: + names.remove('CVS') + + if dirname == '.': + dirname = '' + if dirname.startswith('./'): + dirname = dirname[2:] + + for n in names: + base, ext = os.path.splitext(n) + if ext in extensions_we_like: + keepers.append(os.path.join(dirname, n)) + +def generate(f): + keepers = [] + os.path.walk('.', visit, keepers) + keepers.sort() + write_keepers(keepers, f) + +def write_keepers(files, outf): + m = reduce(max, map(len, files), 0) + e = 'EXTRA_DIST =' + outf.write('%s%s \\\n' % (e, (m-len(e)+8) * ' ')) + for f in files[:-1]: + outf.write('\t%s%s \\\n' % (f, (m-len(f)) * ' ')) + outf.write('\t%s\n' % (files[-1],)) + +if __name__ == '__main__': + generate(open('Makefile.extra','w')) diff --git a/megacells/accum32.bsf b/megacells/accum32.bsf new file mode 100755 index 000000000..494a8200f --- /dev/null +++ b/megacells/accum32.bsf @@ -0,0 +1,86 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 240 120) + (text "accum32" (rect 87 2 166 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 101 31 116)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 24 82 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 16 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 20 40 51 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clken" (rect 20 56 51 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 80 41 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 240 56) + (output) + (text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "result[31..0]" (rect 152 40 221 56)(font "Arial" (font_size 8))) + (line (pt 240 56)(pt 224 56)(line_width 3)) + ) + (drawing + (text "acc" (rect 102 48 123 64)(font "Arial" (font_size 8))) + (text "SIGNED" (rect 177 18 214 32)(font "Arial" )) + (line (pt 16 16)(pt 224 16)(line_width 1)) + (line (pt 16 16)(pt 16 104)(line_width 1)) + (line (pt 16 104)(pt 224 104)(line_width 1)) + (line (pt 224 16)(pt 224 104)(line_width 1)) + (line (pt 88 24)(pt 136 48)(line_width 1)) + (line (pt 136 64)(pt 136 48)(line_width 1)) + (line (pt 88 88)(pt 136 64)(line_width 1)) + (line (pt 88 24)(pt 88 88)(line_width 1)) + (line (pt 16 40)(pt 88 40)(line_width 1)) + (line (pt 16 56)(pt 88 56)(line_width 1)) + (line (pt 136 56)(pt 224 56)(line_width 1)) + (line (pt 16 72)(pt 88 72)(line_width 1)) + (line (pt 16 72)(pt 88 72)(line_width 1)) + (line (pt 16 96)(pt 104 96)(line_width 1)) + (line (pt 104 96)(pt 104 80)(line_width 1)) + ) +) diff --git a/megacells/accum32.cmp b/megacells/accum32.cmp new file mode 100755 index 000000000..55b5fdc22 --- /dev/null +++ b/megacells/accum32.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component accum32 + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + clock : IN STD_LOGIC := '0'; + clken : IN STD_LOGIC := '1'; + aclr : IN STD_LOGIC := '0'; + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/megacells/accum32.inc b/megacells/accum32.inc new file mode 100755 index 000000000..6c6690025 --- /dev/null +++ b/megacells/accum32.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION accum32 +( + data[31..0], + clock, + clken, + aclr +) + +RETURNS ( + result[31..0] +); diff --git a/megacells/accum32.v b/megacells/accum32.v new file mode 100755 index 000000000..ce50cbbf1 --- /dev/null +++ b/megacells/accum32.v @@ -0,0 +1,765 @@ +// megafunction wizard: %ALTACCUMULATE%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altaccumulate + +// ============================================================ +// File Name: accum32.v +// Megafunction Name(s): +// altaccumulate +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result +//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END + +//synthesis_resources = lut 32 +module accum32_accum_nta + ( + aclr, + clken, + clock, + data, + result) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clken; + input clock; + input [31:0] data; + output [31:0] result; + + wire [0:0] wire_acc_cella_0cout; + wire [0:0] wire_acc_cella_1cout; + wire [0:0] wire_acc_cella_2cout; + wire [0:0] wire_acc_cella_3cout; + wire [0:0] wire_acc_cella_4cout; + wire [0:0] wire_acc_cella_5cout; + wire [0:0] wire_acc_cella_6cout; + wire [0:0] wire_acc_cella_7cout; + wire [0:0] wire_acc_cella_8cout; + wire [0:0] wire_acc_cella_9cout; + wire [0:0] wire_acc_cella_10cout; + wire [0:0] wire_acc_cella_11cout; + wire [0:0] wire_acc_cella_12cout; + wire [0:0] wire_acc_cella_13cout; + wire [0:0] wire_acc_cella_14cout; + wire [0:0] wire_acc_cella_15cout; + wire [0:0] wire_acc_cella_16cout; + wire [0:0] wire_acc_cella_17cout; + wire [0:0] wire_acc_cella_18cout; + wire [0:0] wire_acc_cella_19cout; + wire [0:0] wire_acc_cella_20cout; + wire [0:0] wire_acc_cella_21cout; + wire [0:0] wire_acc_cella_22cout; + wire [0:0] wire_acc_cella_23cout; + wire [0:0] wire_acc_cella_24cout; + wire [0:0] wire_acc_cella_25cout; + wire [0:0] wire_acc_cella_26cout; + wire [0:0] wire_acc_cella_27cout; + wire [0:0] wire_acc_cella_28cout; + wire [0:0] wire_acc_cella_29cout; + wire [0:0] wire_acc_cella_30cout; + wire [31:0] wire_acc_cella_dataa; + wire [31:0] wire_acc_cella_datab; + wire [31:0] wire_acc_cella_datac; + wire [31:0] wire_acc_cella_regout; + wire sload; + + stratix_lcell acc_cella_0 + ( + .aclr(aclr), + .cin(1'b0), + .clk(clock), + .cout(wire_acc_cella_0cout[0:0]), + .dataa(wire_acc_cella_dataa[0:0]), + .datab(wire_acc_cella_datab[0:0]), + .datac(wire_acc_cella_datac[0:0]), + .ena(clken), + .regout(wire_acc_cella_regout[0:0]), + .sload(sload)); + defparam + acc_cella_0.cin_used = "true", + acc_cella_0.lut_mask = "96e8", + acc_cella_0.operation_mode = "arithmetic", + acc_cella_0.sum_lutc_input = "cin", + acc_cella_0.synch_mode = "on", + acc_cella_0.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_1 + ( + .aclr(aclr), + .cin(wire_acc_cella_0cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_1cout[0:0]), + .dataa(wire_acc_cella_dataa[1:1]), + .datab(wire_acc_cella_datab[1:1]), + .datac(wire_acc_cella_datac[1:1]), + .ena(clken), + .regout(wire_acc_cella_regout[1:1]), + .sload(sload)); + defparam + acc_cella_1.cin_used = "true", + acc_cella_1.lut_mask = "96e8", + acc_cella_1.operation_mode = "arithmetic", + acc_cella_1.sum_lutc_input = "cin", + acc_cella_1.synch_mode = "on", + acc_cella_1.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_2 + ( + .aclr(aclr), + .cin(wire_acc_cella_1cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_2cout[0:0]), + .dataa(wire_acc_cella_dataa[2:2]), + .datab(wire_acc_cella_datab[2:2]), + .datac(wire_acc_cella_datac[2:2]), + .ena(clken), + .regout(wire_acc_cella_regout[2:2]), + .sload(sload)); + defparam + acc_cella_2.cin_used = "true", + acc_cella_2.lut_mask = "96e8", + acc_cella_2.operation_mode = "arithmetic", + acc_cella_2.sum_lutc_input = "cin", + acc_cella_2.synch_mode = "on", + acc_cella_2.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_3 + ( + .aclr(aclr), + .cin(wire_acc_cella_2cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_3cout[0:0]), + .dataa(wire_acc_cella_dataa[3:3]), + .datab(wire_acc_cella_datab[3:3]), + .datac(wire_acc_cella_datac[3:3]), + .ena(clken), + .regout(wire_acc_cella_regout[3:3]), + .sload(sload)); + defparam + acc_cella_3.cin_used = "true", + acc_cella_3.lut_mask = "96e8", + acc_cella_3.operation_mode = "arithmetic", + acc_cella_3.sum_lutc_input = "cin", + acc_cella_3.synch_mode = "on", + acc_cella_3.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_4 + ( + .aclr(aclr), + .cin(wire_acc_cella_3cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_4cout[0:0]), + .dataa(wire_acc_cella_dataa[4:4]), + .datab(wire_acc_cella_datab[4:4]), + .datac(wire_acc_cella_datac[4:4]), + .ena(clken), + .regout(wire_acc_cella_regout[4:4]), + .sload(sload)); + defparam + acc_cella_4.cin_used = "true", + acc_cella_4.lut_mask = "96e8", + acc_cella_4.operation_mode = "arithmetic", + acc_cella_4.sum_lutc_input = "cin", + acc_cella_4.synch_mode = "on", + acc_cella_4.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_5 + ( + .aclr(aclr), + .cin(wire_acc_cella_4cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_5cout[0:0]), + .dataa(wire_acc_cella_dataa[5:5]), + .datab(wire_acc_cella_datab[5:5]), + .datac(wire_acc_cella_datac[5:5]), + .ena(clken), + .regout(wire_acc_cella_regout[5:5]), + .sload(sload)); + defparam + acc_cella_5.cin_used = "true", + acc_cella_5.lut_mask = "96e8", + acc_cella_5.operation_mode = "arithmetic", + acc_cella_5.sum_lutc_input = "cin", + acc_cella_5.synch_mode = "on", + acc_cella_5.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_6 + ( + .aclr(aclr), + .cin(wire_acc_cella_5cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_6cout[0:0]), + .dataa(wire_acc_cella_dataa[6:6]), + .datab(wire_acc_cella_datab[6:6]), + .datac(wire_acc_cella_datac[6:6]), + .ena(clken), + .regout(wire_acc_cella_regout[6:6]), + .sload(sload)); + defparam + acc_cella_6.cin_used = "true", + acc_cella_6.lut_mask = "96e8", + acc_cella_6.operation_mode = "arithmetic", + acc_cella_6.sum_lutc_input = "cin", + acc_cella_6.synch_mode = "on", + acc_cella_6.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_7 + ( + .aclr(aclr), + .cin(wire_acc_cella_6cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_7cout[0:0]), + .dataa(wire_acc_cella_dataa[7:7]), + .datab(wire_acc_cella_datab[7:7]), + .datac(wire_acc_cella_datac[7:7]), + .ena(clken), + .regout(wire_acc_cella_regout[7:7]), + .sload(sload)); + defparam + acc_cella_7.cin_used = "true", + acc_cella_7.lut_mask = "96e8", + acc_cella_7.operation_mode = "arithmetic", + acc_cella_7.sum_lutc_input = "cin", + acc_cella_7.synch_mode = "on", + acc_cella_7.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_8 + ( + .aclr(aclr), + .cin(wire_acc_cella_7cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_8cout[0:0]), + .dataa(wire_acc_cella_dataa[8:8]), + .datab(wire_acc_cella_datab[8:8]), + .datac(wire_acc_cella_datac[8:8]), + .ena(clken), + .regout(wire_acc_cella_regout[8:8]), + .sload(sload)); + defparam + acc_cella_8.cin_used = "true", + acc_cella_8.lut_mask = "96e8", + acc_cella_8.operation_mode = "arithmetic", + acc_cella_8.sum_lutc_input = "cin", + acc_cella_8.synch_mode = "on", + acc_cella_8.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_9 + ( + .aclr(aclr), + .cin(wire_acc_cella_8cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_9cout[0:0]), + .dataa(wire_acc_cella_dataa[9:9]), + .datab(wire_acc_cella_datab[9:9]), + .datac(wire_acc_cella_datac[9:9]), + .ena(clken), + .regout(wire_acc_cella_regout[9:9]), + .sload(sload)); + defparam + acc_cella_9.cin_used = "true", + acc_cella_9.lut_mask = "96e8", + acc_cella_9.operation_mode = "arithmetic", + acc_cella_9.sum_lutc_input = "cin", + acc_cella_9.synch_mode = "on", + acc_cella_9.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_10 + ( + .aclr(aclr), + .cin(wire_acc_cella_9cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_10cout[0:0]), + .dataa(wire_acc_cella_dataa[10:10]), + .datab(wire_acc_cella_datab[10:10]), + .datac(wire_acc_cella_datac[10:10]), + .ena(clken), + .regout(wire_acc_cella_regout[10:10]), + .sload(sload)); + defparam + acc_cella_10.cin_used = "true", + acc_cella_10.lut_mask = "96e8", + acc_cella_10.operation_mode = "arithmetic", + acc_cella_10.sum_lutc_input = "cin", + acc_cella_10.synch_mode = "on", + acc_cella_10.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_11 + ( + .aclr(aclr), + .cin(wire_acc_cella_10cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_11cout[0:0]), + .dataa(wire_acc_cella_dataa[11:11]), + .datab(wire_acc_cella_datab[11:11]), + .datac(wire_acc_cella_datac[11:11]), + .ena(clken), + .regout(wire_acc_cella_regout[11:11]), + .sload(sload)); + defparam + acc_cella_11.cin_used = "true", + acc_cella_11.lut_mask = "96e8", + acc_cella_11.operation_mode = "arithmetic", + acc_cella_11.sum_lutc_input = "cin", + acc_cella_11.synch_mode = "on", + acc_cella_11.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_12 + ( + .aclr(aclr), + .cin(wire_acc_cella_11cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_12cout[0:0]), + .dataa(wire_acc_cella_dataa[12:12]), + .datab(wire_acc_cella_datab[12:12]), + .datac(wire_acc_cella_datac[12:12]), + .ena(clken), + .regout(wire_acc_cella_regout[12:12]), + .sload(sload)); + defparam + acc_cella_12.cin_used = "true", + acc_cella_12.lut_mask = "96e8", + acc_cella_12.operation_mode = "arithmetic", + acc_cella_12.sum_lutc_input = "cin", + acc_cella_12.synch_mode = "on", + acc_cella_12.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_13 + ( + .aclr(aclr), + .cin(wire_acc_cella_12cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_13cout[0:0]), + .dataa(wire_acc_cella_dataa[13:13]), + .datab(wire_acc_cella_datab[13:13]), + .datac(wire_acc_cella_datac[13:13]), + .ena(clken), + .regout(wire_acc_cella_regout[13:13]), + .sload(sload)); + defparam + acc_cella_13.cin_used = "true", + acc_cella_13.lut_mask = "96e8", + acc_cella_13.operation_mode = "arithmetic", + acc_cella_13.sum_lutc_input = "cin", + acc_cella_13.synch_mode = "on", + acc_cella_13.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_14 + ( + .aclr(aclr), + .cin(wire_acc_cella_13cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_14cout[0:0]), + .dataa(wire_acc_cella_dataa[14:14]), + .datab(wire_acc_cella_datab[14:14]), + .datac(wire_acc_cella_datac[14:14]), + .ena(clken), + .regout(wire_acc_cella_regout[14:14]), + .sload(sload)); + defparam + acc_cella_14.cin_used = "true", + acc_cella_14.lut_mask = "96e8", + acc_cella_14.operation_mode = "arithmetic", + acc_cella_14.sum_lutc_input = "cin", + acc_cella_14.synch_mode = "on", + acc_cella_14.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_15 + ( + .aclr(aclr), + .cin(wire_acc_cella_14cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_15cout[0:0]), + .dataa(wire_acc_cella_dataa[15:15]), + .datab(wire_acc_cella_datab[15:15]), + .datac(wire_acc_cella_datac[15:15]), + .ena(clken), + .regout(wire_acc_cella_regout[15:15]), + .sload(sload)); + defparam + acc_cella_15.cin_used = "true", + acc_cella_15.lut_mask = "96e8", + acc_cella_15.operation_mode = "arithmetic", + acc_cella_15.sum_lutc_input = "cin", + acc_cella_15.synch_mode = "on", + acc_cella_15.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_16 + ( + .aclr(aclr), + .cin(wire_acc_cella_15cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_16cout[0:0]), + .dataa(wire_acc_cella_dataa[16:16]), + .datab(wire_acc_cella_datab[16:16]), + .datac(wire_acc_cella_datac[16:16]), + .ena(clken), + .regout(wire_acc_cella_regout[16:16]), + .sload(sload)); + defparam + acc_cella_16.cin_used = "true", + acc_cella_16.lut_mask = "96e8", + acc_cella_16.operation_mode = "arithmetic", + acc_cella_16.sum_lutc_input = "cin", + acc_cella_16.synch_mode = "on", + acc_cella_16.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_17 + ( + .aclr(aclr), + .cin(wire_acc_cella_16cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_17cout[0:0]), + .dataa(wire_acc_cella_dataa[17:17]), + .datab(wire_acc_cella_datab[17:17]), + .datac(wire_acc_cella_datac[17:17]), + .ena(clken), + .regout(wire_acc_cella_regout[17:17]), + .sload(sload)); + defparam + acc_cella_17.cin_used = "true", + acc_cella_17.lut_mask = "96e8", + acc_cella_17.operation_mode = "arithmetic", + acc_cella_17.sum_lutc_input = "cin", + acc_cella_17.synch_mode = "on", + acc_cella_17.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_18 + ( + .aclr(aclr), + .cin(wire_acc_cella_17cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_18cout[0:0]), + .dataa(wire_acc_cella_dataa[18:18]), + .datab(wire_acc_cella_datab[18:18]), + .datac(wire_acc_cella_datac[18:18]), + .ena(clken), + .regout(wire_acc_cella_regout[18:18]), + .sload(sload)); + defparam + acc_cella_18.cin_used = "true", + acc_cella_18.lut_mask = "96e8", + acc_cella_18.operation_mode = "arithmetic", + acc_cella_18.sum_lutc_input = "cin", + acc_cella_18.synch_mode = "on", + acc_cella_18.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_19 + ( + .aclr(aclr), + .cin(wire_acc_cella_18cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_19cout[0:0]), + .dataa(wire_acc_cella_dataa[19:19]), + .datab(wire_acc_cella_datab[19:19]), + .datac(wire_acc_cella_datac[19:19]), + .ena(clken), + .regout(wire_acc_cella_regout[19:19]), + .sload(sload)); + defparam + acc_cella_19.cin_used = "true", + acc_cella_19.lut_mask = "96e8", + acc_cella_19.operation_mode = "arithmetic", + acc_cella_19.sum_lutc_input = "cin", + acc_cella_19.synch_mode = "on", + acc_cella_19.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_20 + ( + .aclr(aclr), + .cin(wire_acc_cella_19cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_20cout[0:0]), + .dataa(wire_acc_cella_dataa[20:20]), + .datab(wire_acc_cella_datab[20:20]), + .datac(wire_acc_cella_datac[20:20]), + .ena(clken), + .regout(wire_acc_cella_regout[20:20]), + .sload(sload)); + defparam + acc_cella_20.cin_used = "true", + acc_cella_20.lut_mask = "96e8", + acc_cella_20.operation_mode = "arithmetic", + acc_cella_20.sum_lutc_input = "cin", + acc_cella_20.synch_mode = "on", + acc_cella_20.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_21 + ( + .aclr(aclr), + .cin(wire_acc_cella_20cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_21cout[0:0]), + .dataa(wire_acc_cella_dataa[21:21]), + .datab(wire_acc_cella_datab[21:21]), + .datac(wire_acc_cella_datac[21:21]), + .ena(clken), + .regout(wire_acc_cella_regout[21:21]), + .sload(sload)); + defparam + acc_cella_21.cin_used = "true", + acc_cella_21.lut_mask = "96e8", + acc_cella_21.operation_mode = "arithmetic", + acc_cella_21.sum_lutc_input = "cin", + acc_cella_21.synch_mode = "on", + acc_cella_21.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_22 + ( + .aclr(aclr), + .cin(wire_acc_cella_21cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_22cout[0:0]), + .dataa(wire_acc_cella_dataa[22:22]), + .datab(wire_acc_cella_datab[22:22]), + .datac(wire_acc_cella_datac[22:22]), + .ena(clken), + .regout(wire_acc_cella_regout[22:22]), + .sload(sload)); + defparam + acc_cella_22.cin_used = "true", + acc_cella_22.lut_mask = "96e8", + acc_cella_22.operation_mode = "arithmetic", + acc_cella_22.sum_lutc_input = "cin", + acc_cella_22.synch_mode = "on", + acc_cella_22.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_23 + ( + .aclr(aclr), + .cin(wire_acc_cella_22cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_23cout[0:0]), + .dataa(wire_acc_cella_dataa[23:23]), + .datab(wire_acc_cella_datab[23:23]), + .datac(wire_acc_cella_datac[23:23]), + .ena(clken), + .regout(wire_acc_cella_regout[23:23]), + .sload(sload)); + defparam + acc_cella_23.cin_used = "true", + acc_cella_23.lut_mask = "96e8", + acc_cella_23.operation_mode = "arithmetic", + acc_cella_23.sum_lutc_input = "cin", + acc_cella_23.synch_mode = "on", + acc_cella_23.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_24 + ( + .aclr(aclr), + .cin(wire_acc_cella_23cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_24cout[0:0]), + .dataa(wire_acc_cella_dataa[24:24]), + .datab(wire_acc_cella_datab[24:24]), + .datac(wire_acc_cella_datac[24:24]), + .ena(clken), + .regout(wire_acc_cella_regout[24:24]), + .sload(sload)); + defparam + acc_cella_24.cin_used = "true", + acc_cella_24.lut_mask = "96e8", + acc_cella_24.operation_mode = "arithmetic", + acc_cella_24.sum_lutc_input = "cin", + acc_cella_24.synch_mode = "on", + acc_cella_24.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_25 + ( + .aclr(aclr), + .cin(wire_acc_cella_24cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_25cout[0:0]), + .dataa(wire_acc_cella_dataa[25:25]), + .datab(wire_acc_cella_datab[25:25]), + .datac(wire_acc_cella_datac[25:25]), + .ena(clken), + .regout(wire_acc_cella_regout[25:25]), + .sload(sload)); + defparam + acc_cella_25.cin_used = "true", + acc_cella_25.lut_mask = "96e8", + acc_cella_25.operation_mode = "arithmetic", + acc_cella_25.sum_lutc_input = "cin", + acc_cella_25.synch_mode = "on", + acc_cella_25.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_26 + ( + .aclr(aclr), + .cin(wire_acc_cella_25cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_26cout[0:0]), + .dataa(wire_acc_cella_dataa[26:26]), + .datab(wire_acc_cella_datab[26:26]), + .datac(wire_acc_cella_datac[26:26]), + .ena(clken), + .regout(wire_acc_cella_regout[26:26]), + .sload(sload)); + defparam + acc_cella_26.cin_used = "true", + acc_cella_26.lut_mask = "96e8", + acc_cella_26.operation_mode = "arithmetic", + acc_cella_26.sum_lutc_input = "cin", + acc_cella_26.synch_mode = "on", + acc_cella_26.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_27 + ( + .aclr(aclr), + .cin(wire_acc_cella_26cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_27cout[0:0]), + .dataa(wire_acc_cella_dataa[27:27]), + .datab(wire_acc_cella_datab[27:27]), + .datac(wire_acc_cella_datac[27:27]), + .ena(clken), + .regout(wire_acc_cella_regout[27:27]), + .sload(sload)); + defparam + acc_cella_27.cin_used = "true", + acc_cella_27.lut_mask = "96e8", + acc_cella_27.operation_mode = "arithmetic", + acc_cella_27.sum_lutc_input = "cin", + acc_cella_27.synch_mode = "on", + acc_cella_27.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_28 + ( + .aclr(aclr), + .cin(wire_acc_cella_27cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_28cout[0:0]), + .dataa(wire_acc_cella_dataa[28:28]), + .datab(wire_acc_cella_datab[28:28]), + .datac(wire_acc_cella_datac[28:28]), + .ena(clken), + .regout(wire_acc_cella_regout[28:28]), + .sload(sload)); + defparam + acc_cella_28.cin_used = "true", + acc_cella_28.lut_mask = "96e8", + acc_cella_28.operation_mode = "arithmetic", + acc_cella_28.sum_lutc_input = "cin", + acc_cella_28.synch_mode = "on", + acc_cella_28.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_29 + ( + .aclr(aclr), + .cin(wire_acc_cella_28cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_29cout[0:0]), + .dataa(wire_acc_cella_dataa[29:29]), + .datab(wire_acc_cella_datab[29:29]), + .datac(wire_acc_cella_datac[29:29]), + .ena(clken), + .regout(wire_acc_cella_regout[29:29]), + .sload(sload)); + defparam + acc_cella_29.cin_used = "true", + acc_cella_29.lut_mask = "96e8", + acc_cella_29.operation_mode = "arithmetic", + acc_cella_29.sum_lutc_input = "cin", + acc_cella_29.synch_mode = "on", + acc_cella_29.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_30 + ( + .aclr(aclr), + .cin(wire_acc_cella_29cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_30cout[0:0]), + .dataa(wire_acc_cella_dataa[30:30]), + .datab(wire_acc_cella_datab[30:30]), + .datac(wire_acc_cella_datac[30:30]), + .ena(clken), + .regout(wire_acc_cella_regout[30:30]), + .sload(sload)); + defparam + acc_cella_30.cin_used = "true", + acc_cella_30.lut_mask = "96e8", + acc_cella_30.operation_mode = "arithmetic", + acc_cella_30.sum_lutc_input = "cin", + acc_cella_30.synch_mode = "on", + acc_cella_30.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_31 + ( + .aclr(aclr), + .cin(wire_acc_cella_30cout[0:0]), + .clk(clock), + .dataa(wire_acc_cella_dataa[31:31]), + .datab(wire_acc_cella_datab[31:31]), + .datac(wire_acc_cella_datac[31:31]), + .ena(clken), + .regout(wire_acc_cella_regout[31:31]), + .sload(sload)); + defparam + acc_cella_31.cin_used = "true", + acc_cella_31.lut_mask = "9696", + acc_cella_31.operation_mode = "normal", + acc_cella_31.sum_lutc_input = "cin", + acc_cella_31.synch_mode = "on", + acc_cella_31.lpm_type = "stratix_lcell"; + assign + wire_acc_cella_dataa = data, + wire_acc_cella_datab = wire_acc_cella_regout, + wire_acc_cella_datac = data; + assign + result = wire_acc_cella_regout, + sload = 1'b0; +endmodule //accum32_accum_nta +//VALID FILE + + +module accum32 ( + data, + clock, + clken, + aclr, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] data; + input clock; + input clken; + input aclr; + output [31:0] result; + + wire [31:0] sub_wire0; + wire [31:0] result = sub_wire0[31:0]; + + accum32_accum_nta accum32_accum_nta_component ( + .clken (clken), + .aclr (aclr), + .clock (clock), + .data (data), + .result (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32" +// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0" +// Retrieval info: PRIVATE: SLOAD NUMERIC "0" +// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0" +// Retrieval info: PRIVATE: CIN NUMERIC "0" +// Retrieval info: PRIVATE: CLKEN NUMERIC "1" +// Retrieval info: PRIVATE: ACLR NUMERIC "1" +// Retrieval info: PRIVATE: COUT NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0" +// Retrieval info: PRIVATE: LATENCY NUMERIC "0" +// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32" +// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all diff --git a/megacells/accum32_bb.v b/megacells/accum32_bb.v new file mode 100755 index 000000000..142bde88c --- /dev/null +++ b/megacells/accum32_bb.v @@ -0,0 +1,35 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module accum32 ( + data, + clock, + clken, + aclr, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] data; + input clock; + input clken; + input aclr; + output [31:0] result; + +endmodule + diff --git a/megacells/accum32_inst.v b/megacells/accum32_inst.v new file mode 100755 index 000000000..c354accae --- /dev/null +++ b/megacells/accum32_inst.v @@ -0,0 +1,7 @@ +accum32 accum32_inst ( + .data ( data_sig ), + .clock ( clock_sig ), + .clken ( clken_sig ), + .aclr ( aclr_sig ), + .result ( result_sig ) + ); diff --git a/megacells/add32.bsf b/megacells/add32.bsf new file mode 100755 index 000000000..b2da9fc2a --- /dev/null +++ b/megacells/add32.bsf @@ -0,0 +1,62 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 96) + (text "add32" (rect 58 2 111 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 77 31 92)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "dataa[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) + (text "dataa[7..0]" (rect 4 24 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 64 40)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "datab[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) + (text "datab[7..0]" (rect 4 56 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 3)) + ) + (port + (pt 160 56) + (output) + (text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) + (text "result[7..0]" (rect 95 40 157 56)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 96 56)(line_width 3)) + ) + (drawing + (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8))) + (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8))) + (text "A+B" (rect 68 48 94 64)(font "Arial" (font_size 8))) + (line (pt 64 32)(pt 96 40)(line_width 1)) + (line (pt 96 40)(pt 96 72)(line_width 1)) + (line (pt 96 72)(pt 64 80)(line_width 1)) + (line (pt 64 80)(pt 64 32)(line_width 1)) + ) +) diff --git a/megacells/add32.cmp b/megacells/add32.cmp new file mode 100755 index 000000000..3b120176d --- /dev/null +++ b/megacells/add32.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component add32 + PORT + ( + dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/megacells/add32.inc b/megacells/add32.inc new file mode 100755 index 000000000..675525713 --- /dev/null +++ b/megacells/add32.inc @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION add32 +( + dataa[7..0], + datab[7..0] +) + +RETURNS ( + result[7..0] +); diff --git a/megacells/add32.v b/megacells/add32.v new file mode 100755 index 000000000..d8090617a --- /dev/null +++ b/megacells/add32.v @@ -0,0 +1,221 @@ +// megafunction wizard: %LPM_ADD_SUB%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_add_sub + +// ============================================================ +// File Name: add32.v +// Megafunction Name(s): +// lpm_add_sub +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result +//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END + +//synthesis_resources = lut 8 +module add32_add_sub_nq7 + ( + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input [7:0] dataa; + input [7:0] datab; + output [7:0] result; + + wire [7:0] wire_add_sub_cella_combout; + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [7:0] wire_add_sub_cella_dataa; + wire [7:0] wire_add_sub_cella_datab; + + stratix_lcell add_sub_cella_0 + ( + .cin(1'b0), + .combout(wire_add_sub_cella_combout[0:0]), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0])); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "96e8", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_1 + ( + .cin(wire_add_sub_cella_0cout[0:0]), + .combout(wire_add_sub_cella_combout[1:1]), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1])); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "96e8", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_2 + ( + .cin(wire_add_sub_cella_1cout[0:0]), + .combout(wire_add_sub_cella_combout[2:2]), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2])); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "96e8", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_3 + ( + .cin(wire_add_sub_cella_2cout[0:0]), + .combout(wire_add_sub_cella_combout[3:3]), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3])); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "96e8", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_4 + ( + .cin(wire_add_sub_cella_3cout[0:0]), + .combout(wire_add_sub_cella_combout[4:4]), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4])); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "96e8", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_5 + ( + .cin(wire_add_sub_cella_4cout[0:0]), + .combout(wire_add_sub_cella_combout[5:5]), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5])); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "96e8", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_6 + ( + .cin(wire_add_sub_cella_5cout[0:0]), + .combout(wire_add_sub_cella_combout[6:6]), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6])); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "96e8", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_7 + ( + .cin(wire_add_sub_cella_6cout[0:0]), + .combout(wire_add_sub_cella_combout[7:7]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7])); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "9696", + add_sub_cella_7.operation_mode = "normal", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "stratix_lcell"; + assign + wire_add_sub_cella_dataa = dataa, + wire_add_sub_cella_datab = datab; + assign + result = wire_add_sub_cella_combout; +endmodule //add32_add_sub_nq7 +//VALID FILE + + +module add32 ( + dataa, + datab, + result)/* synthesis synthesis_clearbox = 1 */; + + input [7:0] dataa; + input [7:0] datab; + output [7:0] result; + + wire [7:0] sub_wire0; + wire [7:0] result = sub_wire0[7:0]; + + add32_add_sub_nq7 add32_add_sub_nq7_component ( + .dataa (dataa), + .datab (datab), + .result (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "8" +// Retrieval info: PRIVATE: Function NUMERIC "0" +// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantA NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Overflow NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "0" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] +// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0] +// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0] +// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 +// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0 +// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/add32_bb.v b/megacells/add32_bb.v new file mode 100755 index 000000000..8d1588cc6 --- /dev/null +++ b/megacells/add32_bb.v @@ -0,0 +1,31 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module add32 ( + dataa, + datab, + result)/* synthesis synthesis_clearbox = 1 */; + + input [7:0] dataa; + input [7:0] datab; + output [7:0] result; + +endmodule + diff --git a/megacells/add32_inst.v b/megacells/add32_inst.v new file mode 100755 index 000000000..bc7e6d441 --- /dev/null +++ b/megacells/add32_inst.v @@ -0,0 +1,5 @@ +add32 add32_inst ( + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .result ( result_sig ) + ); diff --git a/megacells/addsub16.bsf b/megacells/addsub16.bsf new file mode 100755 index 000000000..9ed6b72ae --- /dev/null +++ b/megacells/addsub16.bsf @@ -0,0 +1,96 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 144) + (text "addsub16" (rect 45 2 128 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 125 31 140)(font "Arial" )) + (port + (pt 0 56) + (input) + (text "dataa[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "datab[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 64 88)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 1)) + ) + (port + (pt 0 32) + (input) + (text "add_sub" (rect 0 0 57 16)(font "Arial" (font_size 8))) + (text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 80 32)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clken" (rect 4 96 35 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 74 112)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) + (text "aclr" (rect 4 112 25 128)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 85 128)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "result[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 96 72)(line_width 3)) + ) + (drawing + (text "A" (rect 66 48 75 64)(font "Arial" (font_size 8))) + (text "B" (rect 66 80 75 96)(font "Arial" (font_size 8))) + (text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8))) + (line (pt 64 48)(pt 96 56)(line_width 1)) + (line (pt 96 56)(pt 96 88)(line_width 1)) + (line (pt 96 88)(pt 64 96)(line_width 1)) + (line (pt 64 96)(pt 64 48)(line_width 1)) + (line (pt 80 32)(pt 80 52)(line_width 1)) + (line (pt 106 40)(pt 125 40)(line_width 1)) + (line (pt 74 112)(pt 74 93)(line_width 1)) + (line (pt 85 128)(pt 85 90)(line_width 1)) + (line (pt 64 66)(pt 70 72)(line_width 1)) + (line (pt 70 72)(pt 64 78)(line_width 1)) + ) +) diff --git a/megacells/addsub16.cmp b/megacells/addsub16.cmp new file mode 100755 index 000000000..e32e01b31 --- /dev/null +++ b/megacells/addsub16.cmp @@ -0,0 +1,33 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component addsub16 + PORT + ( + add_sub : IN STD_LOGIC ; + dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + clock : IN STD_LOGIC ; + aclr : IN STD_LOGIC ; + clken : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/megacells/addsub16.inc b/megacells/addsub16.inc new file mode 100755 index 000000000..846f301d2 --- /dev/null +++ b/megacells/addsub16.inc @@ -0,0 +1,34 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION addsub16 +( + add_sub, + dataa[15..0], + datab[15..0], + clock, + aclr, + clken +) + +RETURNS ( + result[15..0] +); diff --git a/megacells/addsub16.v b/megacells/addsub16.v new file mode 100755 index 000000000..431af3e43 --- /dev/null +++ b/megacells/addsub16.v @@ -0,0 +1,438 @@ +// megafunction wizard: %LPM_ADD_SUB%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_add_sub + +// ============================================================ +// File Name: addsub16.v +// Megafunction Name(s): +// lpm_add_sub +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result +//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END + +//synthesis_resources = lut 17 +module addsub16_add_sub_gp9 + ( + aclr, + add_sub, + clken, + clock, + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input aclr; + input add_sub; + input clken; + input clock; + input [15:0] dataa; + input [15:0] datab; + output [15:0] result; + + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [0:0] wire_add_sub_cella_7cout; + wire [0:0] wire_add_sub_cella_8cout; + wire [0:0] wire_add_sub_cella_9cout; + wire [0:0] wire_add_sub_cella_10cout; + wire [0:0] wire_add_sub_cella_11cout; + wire [0:0] wire_add_sub_cella_12cout; + wire [0:0] wire_add_sub_cella_13cout; + wire [0:0] wire_add_sub_cella_14cout; + wire [15:0] wire_add_sub_cella_dataa; + wire [15:0] wire_add_sub_cella_datab; + wire [15:0] wire_add_sub_cella_regout; + wire wire_strx_lcell1_cout; + + stratix_lcell add_sub_cella_0 + ( + .aclr(aclr), + .cin(wire_strx_lcell1_cout), + .clk(clock), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[0:0])); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "96e8", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_1 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_0cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[1:1])); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "96e8", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_2 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_1cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[2:2])); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "96e8", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_3 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_2cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[3:3])); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "96e8", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_4 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_3cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[4:4])); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "96e8", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_5 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_4cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[5:5])); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "96e8", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_6 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_5cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[6:6])); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "96e8", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_7 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_6cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_7cout[0:0]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[7:7])); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "96e8", + add_sub_cella_7.operation_mode = "arithmetic", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_8 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_7cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_8cout[0:0]), + .dataa(wire_add_sub_cella_dataa[8:8]), + .datab(wire_add_sub_cella_datab[8:8]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[8:8])); + defparam + add_sub_cella_8.cin_used = "true", + add_sub_cella_8.lut_mask = "96e8", + add_sub_cella_8.operation_mode = "arithmetic", + add_sub_cella_8.sum_lutc_input = "cin", + add_sub_cella_8.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_9 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_8cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_9cout[0:0]), + .dataa(wire_add_sub_cella_dataa[9:9]), + .datab(wire_add_sub_cella_datab[9:9]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[9:9])); + defparam + add_sub_cella_9.cin_used = "true", + add_sub_cella_9.lut_mask = "96e8", + add_sub_cella_9.operation_mode = "arithmetic", + add_sub_cella_9.sum_lutc_input = "cin", + add_sub_cella_9.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_10 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_9cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_10cout[0:0]), + .dataa(wire_add_sub_cella_dataa[10:10]), + .datab(wire_add_sub_cella_datab[10:10]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[10:10])); + defparam + add_sub_cella_10.cin_used = "true", + add_sub_cella_10.lut_mask = "96e8", + add_sub_cella_10.operation_mode = "arithmetic", + add_sub_cella_10.sum_lutc_input = "cin", + add_sub_cella_10.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_11 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_10cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_11cout[0:0]), + .dataa(wire_add_sub_cella_dataa[11:11]), + .datab(wire_add_sub_cella_datab[11:11]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[11:11])); + defparam + add_sub_cella_11.cin_used = "true", + add_sub_cella_11.lut_mask = "96e8", + add_sub_cella_11.operation_mode = "arithmetic", + add_sub_cella_11.sum_lutc_input = "cin", + add_sub_cella_11.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_12 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_11cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_12cout[0:0]), + .dataa(wire_add_sub_cella_dataa[12:12]), + .datab(wire_add_sub_cella_datab[12:12]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[12:12])); + defparam + add_sub_cella_12.cin_used = "true", + add_sub_cella_12.lut_mask = "96e8", + add_sub_cella_12.operation_mode = "arithmetic", + add_sub_cella_12.sum_lutc_input = "cin", + add_sub_cella_12.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_13 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_12cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_13cout[0:0]), + .dataa(wire_add_sub_cella_dataa[13:13]), + .datab(wire_add_sub_cella_datab[13:13]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[13:13])); + defparam + add_sub_cella_13.cin_used = "true", + add_sub_cella_13.lut_mask = "96e8", + add_sub_cella_13.operation_mode = "arithmetic", + add_sub_cella_13.sum_lutc_input = "cin", + add_sub_cella_13.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_14 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_13cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_14cout[0:0]), + .dataa(wire_add_sub_cella_dataa[14:14]), + .datab(wire_add_sub_cella_datab[14:14]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[14:14])); + defparam + add_sub_cella_14.cin_used = "true", + add_sub_cella_14.lut_mask = "96e8", + add_sub_cella_14.operation_mode = "arithmetic", + add_sub_cella_14.sum_lutc_input = "cin", + add_sub_cella_14.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_15 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_14cout[0:0]), + .clk(clock), + .dataa(wire_add_sub_cella_dataa[15:15]), + .datab(wire_add_sub_cella_datab[15:15]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[15:15])); + defparam + add_sub_cella_15.cin_used = "true", + add_sub_cella_15.lut_mask = "9696", + add_sub_cella_15.operation_mode = "normal", + add_sub_cella_15.sum_lutc_input = "cin", + add_sub_cella_15.lpm_type = "stratix_lcell"; + assign + wire_add_sub_cella_dataa = datab, + wire_add_sub_cella_datab = dataa; + stratix_lcell strx_lcell1 + ( + .cout(wire_strx_lcell1_cout), + .dataa(1'b0), + .datab((~ add_sub)), + .inverta((~ add_sub))); + defparam + strx_lcell1.cin_used = "false", + strx_lcell1.lut_mask = "00cc", + strx_lcell1.operation_mode = "arithmetic", + strx_lcell1.lpm_type = "stratix_lcell"; + assign + result = wire_add_sub_cella_regout; +endmodule //addsub16_add_sub_gp9 +//VALID FILE + + +module addsub16 ( + add_sub, + dataa, + datab, + clock, + aclr, + clken, + result)/* synthesis synthesis_clearbox = 1 */; + + input add_sub; + input [15:0] dataa; + input [15:0] datab; + input clock; + input aclr; + input clken; + output [15:0] result; + + wire [15:0] sub_wire0; + wire [15:0] result = sub_wire0[15:0]; + + addsub16_add_sub_gp9 addsub16_add_sub_gp9_component ( + .dataa (dataa), + .add_sub (add_sub), + .datab (datab), + .clken (clken), + .aclr (aclr), + .clock (clock), + .result (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "16" +// Retrieval info: PRIVATE: Function NUMERIC "2" +// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantA NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Overflow NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "1" +// Retrieval info: PRIVATE: aclr NUMERIC "1" +// Retrieval info: PRIVATE: clken NUMERIC "1" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub +// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] +// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0] +// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0] +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken +// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0 +// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 +// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0 +// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/addsub16_bb.v b/megacells/addsub16_bb.v new file mode 100755 index 000000000..8e1e7c69f --- /dev/null +++ b/megacells/addsub16_bb.v @@ -0,0 +1,39 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module addsub16 ( + add_sub, + dataa, + datab, + clock, + aclr, + clken, + result)/* synthesis synthesis_clearbox = 1 */; + + input add_sub; + input [15:0] dataa; + input [15:0] datab; + input clock; + input aclr; + input clken; + output [15:0] result; + +endmodule + diff --git a/megacells/addsub16_inst.v b/megacells/addsub16_inst.v new file mode 100755 index 000000000..4a81ff2ee --- /dev/null +++ b/megacells/addsub16_inst.v @@ -0,0 +1,9 @@ +addsub16 addsub16_inst ( + .add_sub ( add_sub_sig ), + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .clock ( clock_sig ), + .aclr ( aclr_sig ), + .clken ( clken_sig ), + .result ( result_sig ) + ); diff --git a/megacells/bustri.bsf b/megacells/bustri.bsf new file mode 100755 index 000000000..f1bc3ca7f --- /dev/null +++ b/megacells/bustri.bsf @@ -0,0 +1,62 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "bustri" (rect 24 1 61 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[15..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "16" (rect 61 25 71 37)(font "Arial" )) + (text "16" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 56 28)(pt 64 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/megacells/bustri.cmp b/megacells/bustri.cmp new file mode 100755 index 000000000..87599ca66 --- /dev/null +++ b/megacells/bustri.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component bustri + PORT + ( + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/megacells/bustri.inc b/megacells/bustri.inc new file mode 100755 index 000000000..399950389 --- /dev/null +++ b/megacells/bustri.inc @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION bustri +( + data[15..0], + enabledt +) + +RETURNS ( + tridata[15..0] +); diff --git a/megacells/bustri.v b/megacells/bustri.v new file mode 100755 index 000000000..e40c69476 --- /dev/null +++ b/megacells/bustri.v @@ -0,0 +1,71 @@ +// megafunction wizard: %LPM_BUSTRI% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_bustri + +// ============================================================ +// File Name: bustri.v +// Megafunction Name(s): +// lpm_bustri +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +module bustri ( + data, + enabledt, + tridata); + + input [15:0] data; + input enabledt; + inout [15:0] tridata; + + + lpm_bustri lpm_bustri_component ( + .tridata (tridata), + .enabledt (enabledt), + .data (data)); + defparam + lpm_bustri_component.lpm_width = 16, + lpm_bustri_component.lpm_type = "LPM_BUSTRI"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "16" +// Retrieval info: PRIVATE: BiDir NUMERIC "0" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0] +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0 +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/bustri_bb.v b/megacells/bustri_bb.v new file mode 100755 index 000000000..4cbc1609c --- /dev/null +++ b/megacells/bustri_bb.v @@ -0,0 +1,31 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module bustri ( + data, + enabledt, + tridata); + + input [15:0] data; + input enabledt; + inout [15:0] tridata; + +endmodule + diff --git a/megacells/bustri_inst.v b/megacells/bustri_inst.v new file mode 100755 index 000000000..2b4e49638 --- /dev/null +++ b/megacells/bustri_inst.v @@ -0,0 +1,5 @@ +bustri bustri_inst ( + .data ( data_sig ), + .enabledt ( enabledt_sig ), + .tridata ( tridata_sig ) + ); diff --git a/megacells/clk_doubler.v b/megacells/clk_doubler.v new file mode 100644 index 000000000..b3762a960 --- /dev/null +++ b/megacells/clk_doubler.v @@ -0,0 +1,198 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_doubler.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 156 11/29/2004 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_doubler ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [5:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0) + // synopsys translate_off + , + .activeclock (), + .areset (), + .clkbad (), + .clkena (), + .clkloss (), + .clkswitch (), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena (), + .fbin (), + .locked (), + .pfdena (), + .pllena (), + .scanaclr (), + .scanclk (), + .scandata (), + .scandataout (), + .scandone (), + .scanread (), + .scanwrite (), + .sclkout0 (), + .sclkout1 () + // synopsys translate_on + ); + defparam + altpll_component.clk0_duty_cycle = 50, + altpll_component.lpm_type = "altpll", + altpll_component.clk0_multiply_by = 2, + altpll_component.inclk0_input_frequency = 15625, + altpll_component.clk0_divide_by = 1, + altpll_component.pll_type = "AUTO", + altpll_component.intended_device_family = "Cyclone", + altpll_component.operation_mode = "NORMAL", + altpll_component.compensate_clock = "CLK0", + altpll_component.clk0_phase_shift = "0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE diff --git a/megacells/clk_doubler_bb.v b/megacells/clk_doubler_bb.v new file mode 100644 index 000000000..48c52e795 --- /dev/null +++ b/megacells/clk_doubler_bb.v @@ -0,0 +1,143 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_doubler.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 156 11/29/2004 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module clk_doubler ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE diff --git a/megacells/dspclkpll.v b/megacells/dspclkpll.v new file mode 100644 index 000000000..81e622137 --- /dev/null +++ b/megacells/dspclkpll.v @@ -0,0 +1,237 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: dspclkpll.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module dspclkpll ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + + wire [5:0] sub_wire0; + wire [0:0] sub_wire5 = 1'h0; + wire [1:1] sub_wire2 = sub_wire0[1:1]; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire c1 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0) + // synopsys translate_off +, + .fbin (), + .pllena (), + .clkswitch (), + .areset (), + .pfdena (), + .clkena (), + .extclkena (), + .scanclk (), + .scanaclr (), + .scandata (), + .scanread (), + .scanwrite (), + .extclk (), + .clkbad (), + .activeclock (), + .locked (), + .clkloss (), + .scandataout (), + .scandone (), + .sclkout1 (), + .sclkout0 (), + .enable0 (), + .enable1 () + // synopsys translate_on + +); + defparam + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk0_duty_cycle = 50, + altpll_component.lpm_type = "altpll", + altpll_component.clk0_multiply_by = 1, + altpll_component.inclk0_input_frequency = 15625, + altpll_component.clk0_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.pll_type = "AUTO", + altpll_component.clk1_multiply_by = 2, + altpll_component.clk0_time_delay = "0", + altpll_component.intended_device_family = "Cyclone", + altpll_component.operation_mode = "NORMAL", + altpll_component.compensate_clock = "CLK0", + altpll_component.clk1_time_delay = "0", + altpll_component.clk0_phase_shift = "0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE diff --git a/megacells/dspclkpll_bb.v b/megacells/dspclkpll_bb.v new file mode 100644 index 000000000..489be7bd4 --- /dev/null +++ b/megacells/dspclkpll_bb.v @@ -0,0 +1,31 @@ +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module dspclkpll ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + +endmodule + diff --git a/megacells/fifo_2k.v b/megacells/fifo_2k.v new file mode 100644 index 000000000..5e2a38520 --- /dev/null +++ b/megacells/fifo_2k.v @@ -0,0 +1,3343 @@ +// megafunction wizard: %FIFO%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_2k.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + + +//a_gray2bin device_family="Cyclone" WIDTH=11 bin gray +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END + +//synthesis_resources = +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_a_gray2bin_8m4 + ( + bin, + gray) /* synthesis synthesis_clearbox=1 */; + output [10:0] bin; + input [10:0] gray; + + wire xor0; + wire xor1; + wire xor2; + wire xor3; + wire xor4; + wire xor5; + wire xor6; + wire xor7; + wire xor8; + wire xor9; + + assign + bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, + xor0 = (gray[0] ^ xor1), + xor1 = (gray[1] ^ xor2), + xor2 = (gray[2] ^ xor3), + xor3 = (gray[3] ^ xor4), + xor4 = (gray[4] ^ xor5), + xor5 = (gray[5] ^ xor6), + xor6 = (gray[6] ^ xor7), + xor7 = (gray[7] ^ xor8), + xor8 = (gray[8] ^ xor9), + xor9 = (gray[10] ^ gray[9]); +endmodule //fifo_2k_a_gray2bin_8m4 + + +//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_a_graycounter_726 + ( + aclr, + clock, + cnt_en, + q) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clock; + input cnt_en; + output [10:0] q; + + wire [0:0] wire_countera_0cout; + wire [0:0] wire_countera_1cout; + wire [0:0] wire_countera_2cout; + wire [0:0] wire_countera_3cout; + wire [0:0] wire_countera_4cout; + wire [0:0] wire_countera_5cout; + wire [0:0] wire_countera_6cout; + wire [0:0] wire_countera_7cout; + wire [0:0] wire_countera_8cout; + wire [0:0] wire_countera_9cout; + wire [10:0] wire_countera_regout; + wire wire_parity_cout; + wire wire_parity_regout; + wire [10:0] power_modified_counter_values; + wire sclr; + wire updown; + + cyclone_lcell countera_0 + ( + .aclr(aclr), + .cin(wire_parity_cout), + .clk(clock), + .combout(), + .cout(wire_countera_0cout[0:0]), + .dataa(cnt_en), + .datab(wire_countera_regout[0:0]), + .ena(1'b1), + .regout(wire_countera_regout[0:0]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_0.cin_used = "true", + countera_0.lut_mask = "c6a0", + countera_0.operation_mode = "arithmetic", + countera_0.sum_lutc_input = "cin", + countera_0.synch_mode = "on", + countera_0.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_1 + ( + .aclr(aclr), + .cin(wire_countera_0cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_1cout[0:0]), + .dataa(power_modified_counter_values[0]), + .datab(power_modified_counter_values[1]), + .ena(1'b1), + .regout(wire_countera_regout[1:1]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_1.cin_used = "true", + countera_1.lut_mask = "6c50", + countera_1.operation_mode = "arithmetic", + countera_1.sum_lutc_input = "cin", + countera_1.synch_mode = "on", + countera_1.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_2 + ( + .aclr(aclr), + .cin(wire_countera_1cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_2cout[0:0]), + .dataa(power_modified_counter_values[1]), + .datab(power_modified_counter_values[2]), + .ena(1'b1), + .regout(wire_countera_regout[2:2]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_2.cin_used = "true", + countera_2.lut_mask = "6c50", + countera_2.operation_mode = "arithmetic", + countera_2.sum_lutc_input = "cin", + countera_2.synch_mode = "on", + countera_2.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_3 + ( + .aclr(aclr), + .cin(wire_countera_2cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_3cout[0:0]), + .dataa(power_modified_counter_values[2]), + .datab(power_modified_counter_values[3]), + .ena(1'b1), + .regout(wire_countera_regout[3:3]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_3.cin_used = "true", + countera_3.lut_mask = "6c50", + countera_3.operation_mode = "arithmetic", + countera_3.sum_lutc_input = "cin", + countera_3.synch_mode = "on", + countera_3.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_4 + ( + .aclr(aclr), + .cin(wire_countera_3cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_4cout[0:0]), + .dataa(power_modified_counter_values[3]), + .datab(power_modified_counter_values[4]), + .ena(1'b1), + .regout(wire_countera_regout[4:4]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_4.cin_used = "true", + countera_4.lut_mask = "6c50", + countera_4.operation_mode = "arithmetic", + countera_4.sum_lutc_input = "cin", + countera_4.synch_mode = "on", + countera_4.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_5 + ( + .aclr(aclr), + .cin(wire_countera_4cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_5cout[0:0]), + .dataa(power_modified_counter_values[4]), + .datab(power_modified_counter_values[5]), + .ena(1'b1), + .regout(wire_countera_regout[5:5]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_5.cin_used = "true", + countera_5.lut_mask = "6c50", + countera_5.operation_mode = "arithmetic", + countera_5.sum_lutc_input = "cin", + countera_5.synch_mode = "on", + countera_5.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_6 + ( + .aclr(aclr), + .cin(wire_countera_5cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_6cout[0:0]), + .dataa(power_modified_counter_values[5]), + .datab(power_modified_counter_values[6]), + .ena(1'b1), + .regout(wire_countera_regout[6:6]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_6.cin_used = "true", + countera_6.lut_mask = "6c50", + countera_6.operation_mode = "arithmetic", + countera_6.sum_lutc_input = "cin", + countera_6.synch_mode = "on", + countera_6.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_7 + ( + .aclr(aclr), + .cin(wire_countera_6cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_7cout[0:0]), + .dataa(power_modified_counter_values[6]), + .datab(power_modified_counter_values[7]), + .ena(1'b1), + .regout(wire_countera_regout[7:7]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_7.cin_used = "true", + countera_7.lut_mask = "6c50", + countera_7.operation_mode = "arithmetic", + countera_7.sum_lutc_input = "cin", + countera_7.synch_mode = "on", + countera_7.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_8 + ( + .aclr(aclr), + .cin(wire_countera_7cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_8cout[0:0]), + .dataa(power_modified_counter_values[7]), + .datab(power_modified_counter_values[8]), + .ena(1'b1), + .regout(wire_countera_regout[8:8]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_8.cin_used = "true", + countera_8.lut_mask = "6c50", + countera_8.operation_mode = "arithmetic", + countera_8.sum_lutc_input = "cin", + countera_8.synch_mode = "on", + countera_8.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_9 + ( + .aclr(aclr), + .cin(wire_countera_8cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_9cout[0:0]), + .dataa(power_modified_counter_values[8]), + .datab(power_modified_counter_values[9]), + .ena(1'b1), + .regout(wire_countera_regout[9:9]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_9.cin_used = "true", + countera_9.lut_mask = "6c50", + countera_9.operation_mode = "arithmetic", + countera_9.sum_lutc_input = "cin", + countera_9.synch_mode = "on", + countera_9.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_10 + ( + .aclr(aclr), + .cin(wire_countera_9cout[0:0]), + .clk(clock), + .combout(), + .cout(), + .dataa(power_modified_counter_values[10]), + .ena(1'b1), + .regout(wire_countera_regout[10:10]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datab(1'b1), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_10.cin_used = "true", + countera_10.lut_mask = "5a5a", + countera_10.operation_mode = "normal", + countera_10.sum_lutc_input = "cin", + countera_10.synch_mode = "on", + countera_10.lpm_type = "cyclone_lcell"; + cyclone_lcell parity + ( + .aclr(aclr), + .cin(updown), + .clk(clock), + .combout(), + .cout(wire_parity_cout), + .dataa(cnt_en), + .datab(wire_parity_regout), + .ena(1'b1), + .regout(wire_parity_regout), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + parity.cin_used = "true", + parity.lut_mask = "6682", + parity.operation_mode = "arithmetic", + parity.synch_mode = "on", + parity.lpm_type = "cyclone_lcell"; + assign + power_modified_counter_values = {wire_countera_regout[10:0]}, + q = power_modified_counter_values, + sclr = 1'b0, + updown = 1'b1; +endmodule //fifo_2k_a_graycounter_726 + + +//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_a_graycounter_2r6 + ( + aclr, + clock, + cnt_en, + q) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clock; + input cnt_en; + output [10:0] q; + + wire [0:0] wire_countera_0cout; + wire [0:0] wire_countera_1cout; + wire [0:0] wire_countera_2cout; + wire [0:0] wire_countera_3cout; + wire [0:0] wire_countera_4cout; + wire [0:0] wire_countera_5cout; + wire [0:0] wire_countera_6cout; + wire [0:0] wire_countera_7cout; + wire [0:0] wire_countera_8cout; + wire [0:0] wire_countera_9cout; + wire [10:0] wire_countera_regout; + wire wire_parity_cout; + wire wire_parity_regout; + wire [10:0] power_modified_counter_values; + wire sclr; + wire updown; + + cyclone_lcell countera_0 + ( + .aclr(aclr), + .cin(wire_parity_cout), + .clk(clock), + .combout(), + .cout(wire_countera_0cout[0:0]), + .dataa(cnt_en), + .datab(wire_countera_regout[0:0]), + .ena(1'b1), + .regout(wire_countera_regout[0:0]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_0.cin_used = "true", + countera_0.lut_mask = "c6a0", + countera_0.operation_mode = "arithmetic", + countera_0.sum_lutc_input = "cin", + countera_0.synch_mode = "on", + countera_0.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_1 + ( + .aclr(aclr), + .cin(wire_countera_0cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_1cout[0:0]), + .dataa(power_modified_counter_values[0]), + .datab(power_modified_counter_values[1]), + .ena(1'b1), + .regout(wire_countera_regout[1:1]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_1.cin_used = "true", + countera_1.lut_mask = "6c50", + countera_1.operation_mode = "arithmetic", + countera_1.sum_lutc_input = "cin", + countera_1.synch_mode = "on", + countera_1.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_2 + ( + .aclr(aclr), + .cin(wire_countera_1cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_2cout[0:0]), + .dataa(power_modified_counter_values[1]), + .datab(power_modified_counter_values[2]), + .ena(1'b1), + .regout(wire_countera_regout[2:2]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_2.cin_used = "true", + countera_2.lut_mask = "6c50", + countera_2.operation_mode = "arithmetic", + countera_2.sum_lutc_input = "cin", + countera_2.synch_mode = "on", + countera_2.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_3 + ( + .aclr(aclr), + .cin(wire_countera_2cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_3cout[0:0]), + .dataa(power_modified_counter_values[2]), + .datab(power_modified_counter_values[3]), + .ena(1'b1), + .regout(wire_countera_regout[3:3]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_3.cin_used = "true", + countera_3.lut_mask = "6c50", + countera_3.operation_mode = "arithmetic", + countera_3.sum_lutc_input = "cin", + countera_3.synch_mode = "on", + countera_3.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_4 + ( + .aclr(aclr), + .cin(wire_countera_3cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_4cout[0:0]), + .dataa(power_modified_counter_values[3]), + .datab(power_modified_counter_values[4]), + .ena(1'b1), + .regout(wire_countera_regout[4:4]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_4.cin_used = "true", + countera_4.lut_mask = "6c50", + countera_4.operation_mode = "arithmetic", + countera_4.sum_lutc_input = "cin", + countera_4.synch_mode = "on", + countera_4.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_5 + ( + .aclr(aclr), + .cin(wire_countera_4cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_5cout[0:0]), + .dataa(power_modified_counter_values[4]), + .datab(power_modified_counter_values[5]), + .ena(1'b1), + .regout(wire_countera_regout[5:5]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_5.cin_used = "true", + countera_5.lut_mask = "6c50", + countera_5.operation_mode = "arithmetic", + countera_5.sum_lutc_input = "cin", + countera_5.synch_mode = "on", + countera_5.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_6 + ( + .aclr(aclr), + .cin(wire_countera_5cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_6cout[0:0]), + .dataa(power_modified_counter_values[5]), + .datab(power_modified_counter_values[6]), + .ena(1'b1), + .regout(wire_countera_regout[6:6]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_6.cin_used = "true", + countera_6.lut_mask = "6c50", + countera_6.operation_mode = "arithmetic", + countera_6.sum_lutc_input = "cin", + countera_6.synch_mode = "on", + countera_6.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_7 + ( + .aclr(aclr), + .cin(wire_countera_6cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_7cout[0:0]), + .dataa(power_modified_counter_values[6]), + .datab(power_modified_counter_values[7]), + .ena(1'b1), + .regout(wire_countera_regout[7:7]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_7.cin_used = "true", + countera_7.lut_mask = "6c50", + countera_7.operation_mode = "arithmetic", + countera_7.sum_lutc_input = "cin", + countera_7.synch_mode = "on", + countera_7.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_8 + ( + .aclr(aclr), + .cin(wire_countera_7cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_8cout[0:0]), + .dataa(power_modified_counter_values[7]), + .datab(power_modified_counter_values[8]), + .ena(1'b1), + .regout(wire_countera_regout[8:8]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_8.cin_used = "true", + countera_8.lut_mask = "6c50", + countera_8.operation_mode = "arithmetic", + countera_8.sum_lutc_input = "cin", + countera_8.synch_mode = "on", + countera_8.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_9 + ( + .aclr(aclr), + .cin(wire_countera_8cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_9cout[0:0]), + .dataa(power_modified_counter_values[8]), + .datab(power_modified_counter_values[9]), + .ena(1'b1), + .regout(wire_countera_regout[9:9]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_9.cin_used = "true", + countera_9.lut_mask = "6c50", + countera_9.operation_mode = "arithmetic", + countera_9.sum_lutc_input = "cin", + countera_9.synch_mode = "on", + countera_9.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_10 + ( + .aclr(aclr), + .cin(wire_countera_9cout[0:0]), + .clk(clock), + .combout(), + .cout(), + .dataa(power_modified_counter_values[10]), + .ena(1'b1), + .regout(wire_countera_regout[10:10]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datab(1'b1), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_10.cin_used = "true", + countera_10.lut_mask = "5a5a", + countera_10.operation_mode = "normal", + countera_10.sum_lutc_input = "cin", + countera_10.synch_mode = "on", + countera_10.lpm_type = "cyclone_lcell"; + cyclone_lcell parity + ( + .aclr(aclr), + .cin(updown), + .clk(clock), + .combout(), + .cout(wire_parity_cout), + .dataa(cnt_en), + .datab((~ wire_parity_regout)), + .ena(1'b1), + .regout(wire_parity_regout), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + parity.cin_used = "true", + parity.lut_mask = "9982", + parity.operation_mode = "arithmetic", + parity.synch_mode = "on", + parity.lpm_type = "cyclone_lcell"; + assign + power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])}, + q = power_modified_counter_values, + sclr = 1'b0, + updown = 1'b1; +endmodule //fifo_2k_a_graycounter_2r6 + + +//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a +//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = M4K 8 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_altsyncram_6pl + ( + address_a, + address_b, + clock0, + clock1, + clocken1, + data_a, + q_b, + wren_a) /* synthesis synthesis_clearbox=1 */; + input [10:0] address_a; + input [10:0] address_b; + input clock0; + input clock1; + input clocken1; + input [15:0] data_a; + output [15:0] q_b; + input wren_a; + + wire [0:0] wire_ram_block3a_0portbdataout; + wire [0:0] wire_ram_block3a_1portbdataout; + wire [0:0] wire_ram_block3a_2portbdataout; + wire [0:0] wire_ram_block3a_3portbdataout; + wire [0:0] wire_ram_block3a_4portbdataout; + wire [0:0] wire_ram_block3a_5portbdataout; + wire [0:0] wire_ram_block3a_6portbdataout; + wire [0:0] wire_ram_block3a_7portbdataout; + wire [0:0] wire_ram_block3a_8portbdataout; + wire [0:0] wire_ram_block3a_9portbdataout; + wire [0:0] wire_ram_block3a_10portbdataout; + wire [0:0] wire_ram_block3a_11portbdataout; + wire [0:0] wire_ram_block3a_12portbdataout; + wire [0:0] wire_ram_block3a_13portbdataout; + wire [0:0] wire_ram_block3a_14portbdataout; + wire [0:0] wire_ram_block3a_15portbdataout; + wire [10:0] address_a_wire; + wire [10:0] address_b_wire; + + cyclone_ram_block ram_block3a_0 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[0]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_0portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_0.connectivity_checking = "OFF", + ram_block3a_0.logical_ram_name = "ALTSYNCRAM", + ram_block3a_0.mixed_port_feed_through_mode = "dont_care", + ram_block3a_0.operation_mode = "dual_port", + ram_block3a_0.port_a_address_width = 11, + ram_block3a_0.port_a_data_width = 1, + ram_block3a_0.port_a_first_address = 0, + ram_block3a_0.port_a_first_bit_number = 0, + ram_block3a_0.port_a_last_address = 2047, + ram_block3a_0.port_a_logical_ram_depth = 2048, + ram_block3a_0.port_a_logical_ram_width = 16, + ram_block3a_0.port_b_address_clear = "none", + ram_block3a_0.port_b_address_clock = "clock1", + ram_block3a_0.port_b_address_width = 11, + ram_block3a_0.port_b_data_out_clear = "none", + ram_block3a_0.port_b_data_out_clock = "none", + ram_block3a_0.port_b_data_width = 1, + ram_block3a_0.port_b_first_address = 0, + ram_block3a_0.port_b_first_bit_number = 0, + ram_block3a_0.port_b_last_address = 2047, + ram_block3a_0.port_b_logical_ram_depth = 2048, + ram_block3a_0.port_b_logical_ram_width = 16, + ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_0.ram_block_type = "auto", + ram_block3a_0.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_1 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[1]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_1portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_1.connectivity_checking = "OFF", + ram_block3a_1.logical_ram_name = "ALTSYNCRAM", + ram_block3a_1.mixed_port_feed_through_mode = "dont_care", + ram_block3a_1.operation_mode = "dual_port", + ram_block3a_1.port_a_address_width = 11, + ram_block3a_1.port_a_data_width = 1, + ram_block3a_1.port_a_first_address = 0, + ram_block3a_1.port_a_first_bit_number = 1, + ram_block3a_1.port_a_last_address = 2047, + ram_block3a_1.port_a_logical_ram_depth = 2048, + ram_block3a_1.port_a_logical_ram_width = 16, + ram_block3a_1.port_b_address_clear = "none", + ram_block3a_1.port_b_address_clock = "clock1", + ram_block3a_1.port_b_address_width = 11, + ram_block3a_1.port_b_data_out_clear = "none", + ram_block3a_1.port_b_data_out_clock = "none", + ram_block3a_1.port_b_data_width = 1, + ram_block3a_1.port_b_first_address = 0, + ram_block3a_1.port_b_first_bit_number = 1, + ram_block3a_1.port_b_last_address = 2047, + ram_block3a_1.port_b_logical_ram_depth = 2048, + ram_block3a_1.port_b_logical_ram_width = 16, + ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_1.ram_block_type = "auto", + ram_block3a_1.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_2 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[2]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_2portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_2.connectivity_checking = "OFF", + ram_block3a_2.logical_ram_name = "ALTSYNCRAM", + ram_block3a_2.mixed_port_feed_through_mode = "dont_care", + ram_block3a_2.operation_mode = "dual_port", + ram_block3a_2.port_a_address_width = 11, + ram_block3a_2.port_a_data_width = 1, + ram_block3a_2.port_a_first_address = 0, + ram_block3a_2.port_a_first_bit_number = 2, + ram_block3a_2.port_a_last_address = 2047, + ram_block3a_2.port_a_logical_ram_depth = 2048, + ram_block3a_2.port_a_logical_ram_width = 16, + ram_block3a_2.port_b_address_clear = "none", + ram_block3a_2.port_b_address_clock = "clock1", + ram_block3a_2.port_b_address_width = 11, + ram_block3a_2.port_b_data_out_clear = "none", + ram_block3a_2.port_b_data_out_clock = "none", + ram_block3a_2.port_b_data_width = 1, + ram_block3a_2.port_b_first_address = 0, + ram_block3a_2.port_b_first_bit_number = 2, + ram_block3a_2.port_b_last_address = 2047, + ram_block3a_2.port_b_logical_ram_depth = 2048, + ram_block3a_2.port_b_logical_ram_width = 16, + ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_2.ram_block_type = "auto", + ram_block3a_2.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_3 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[3]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_3portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_3.connectivity_checking = "OFF", + ram_block3a_3.logical_ram_name = "ALTSYNCRAM", + ram_block3a_3.mixed_port_feed_through_mode = "dont_care", + ram_block3a_3.operation_mode = "dual_port", + ram_block3a_3.port_a_address_width = 11, + ram_block3a_3.port_a_data_width = 1, + ram_block3a_3.port_a_first_address = 0, + ram_block3a_3.port_a_first_bit_number = 3, + ram_block3a_3.port_a_last_address = 2047, + ram_block3a_3.port_a_logical_ram_depth = 2048, + ram_block3a_3.port_a_logical_ram_width = 16, + ram_block3a_3.port_b_address_clear = "none", + ram_block3a_3.port_b_address_clock = "clock1", + ram_block3a_3.port_b_address_width = 11, + ram_block3a_3.port_b_data_out_clear = "none", + ram_block3a_3.port_b_data_out_clock = "none", + ram_block3a_3.port_b_data_width = 1, + ram_block3a_3.port_b_first_address = 0, + ram_block3a_3.port_b_first_bit_number = 3, + ram_block3a_3.port_b_last_address = 2047, + ram_block3a_3.port_b_logical_ram_depth = 2048, + ram_block3a_3.port_b_logical_ram_width = 16, + ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_3.ram_block_type = "auto", + ram_block3a_3.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_4 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[4]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_4portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_4.connectivity_checking = "OFF", + ram_block3a_4.logical_ram_name = "ALTSYNCRAM", + ram_block3a_4.mixed_port_feed_through_mode = "dont_care", + ram_block3a_4.operation_mode = "dual_port", + ram_block3a_4.port_a_address_width = 11, + ram_block3a_4.port_a_data_width = 1, + ram_block3a_4.port_a_first_address = 0, + ram_block3a_4.port_a_first_bit_number = 4, + ram_block3a_4.port_a_last_address = 2047, + ram_block3a_4.port_a_logical_ram_depth = 2048, + ram_block3a_4.port_a_logical_ram_width = 16, + ram_block3a_4.port_b_address_clear = "none", + ram_block3a_4.port_b_address_clock = "clock1", + ram_block3a_4.port_b_address_width = 11, + ram_block3a_4.port_b_data_out_clear = "none", + ram_block3a_4.port_b_data_out_clock = "none", + ram_block3a_4.port_b_data_width = 1, + ram_block3a_4.port_b_first_address = 0, + ram_block3a_4.port_b_first_bit_number = 4, + ram_block3a_4.port_b_last_address = 2047, + ram_block3a_4.port_b_logical_ram_depth = 2048, + ram_block3a_4.port_b_logical_ram_width = 16, + ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_4.ram_block_type = "auto", + ram_block3a_4.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_5 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[5]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_5portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_5.connectivity_checking = "OFF", + ram_block3a_5.logical_ram_name = "ALTSYNCRAM", + ram_block3a_5.mixed_port_feed_through_mode = "dont_care", + ram_block3a_5.operation_mode = "dual_port", + ram_block3a_5.port_a_address_width = 11, + ram_block3a_5.port_a_data_width = 1, + ram_block3a_5.port_a_first_address = 0, + ram_block3a_5.port_a_first_bit_number = 5, + ram_block3a_5.port_a_last_address = 2047, + ram_block3a_5.port_a_logical_ram_depth = 2048, + ram_block3a_5.port_a_logical_ram_width = 16, + ram_block3a_5.port_b_address_clear = "none", + ram_block3a_5.port_b_address_clock = "clock1", + ram_block3a_5.port_b_address_width = 11, + ram_block3a_5.port_b_data_out_clear = "none", + ram_block3a_5.port_b_data_out_clock = "none", + ram_block3a_5.port_b_data_width = 1, + ram_block3a_5.port_b_first_address = 0, + ram_block3a_5.port_b_first_bit_number = 5, + ram_block3a_5.port_b_last_address = 2047, + ram_block3a_5.port_b_logical_ram_depth = 2048, + ram_block3a_5.port_b_logical_ram_width = 16, + ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_5.ram_block_type = "auto", + ram_block3a_5.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_6 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[6]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_6portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_6.connectivity_checking = "OFF", + ram_block3a_6.logical_ram_name = "ALTSYNCRAM", + ram_block3a_6.mixed_port_feed_through_mode = "dont_care", + ram_block3a_6.operation_mode = "dual_port", + ram_block3a_6.port_a_address_width = 11, + ram_block3a_6.port_a_data_width = 1, + ram_block3a_6.port_a_first_address = 0, + ram_block3a_6.port_a_first_bit_number = 6, + ram_block3a_6.port_a_last_address = 2047, + ram_block3a_6.port_a_logical_ram_depth = 2048, + ram_block3a_6.port_a_logical_ram_width = 16, + ram_block3a_6.port_b_address_clear = "none", + ram_block3a_6.port_b_address_clock = "clock1", + ram_block3a_6.port_b_address_width = 11, + ram_block3a_6.port_b_data_out_clear = "none", + ram_block3a_6.port_b_data_out_clock = "none", + ram_block3a_6.port_b_data_width = 1, + ram_block3a_6.port_b_first_address = 0, + ram_block3a_6.port_b_first_bit_number = 6, + ram_block3a_6.port_b_last_address = 2047, + ram_block3a_6.port_b_logical_ram_depth = 2048, + ram_block3a_6.port_b_logical_ram_width = 16, + ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_6.ram_block_type = "auto", + ram_block3a_6.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_7 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[7]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_7portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_7.connectivity_checking = "OFF", + ram_block3a_7.logical_ram_name = "ALTSYNCRAM", + ram_block3a_7.mixed_port_feed_through_mode = "dont_care", + ram_block3a_7.operation_mode = "dual_port", + ram_block3a_7.port_a_address_width = 11, + ram_block3a_7.port_a_data_width = 1, + ram_block3a_7.port_a_first_address = 0, + ram_block3a_7.port_a_first_bit_number = 7, + ram_block3a_7.port_a_last_address = 2047, + ram_block3a_7.port_a_logical_ram_depth = 2048, + ram_block3a_7.port_a_logical_ram_width = 16, + ram_block3a_7.port_b_address_clear = "none", + ram_block3a_7.port_b_address_clock = "clock1", + ram_block3a_7.port_b_address_width = 11, + ram_block3a_7.port_b_data_out_clear = "none", + ram_block3a_7.port_b_data_out_clock = "none", + ram_block3a_7.port_b_data_width = 1, + ram_block3a_7.port_b_first_address = 0, + ram_block3a_7.port_b_first_bit_number = 7, + ram_block3a_7.port_b_last_address = 2047, + ram_block3a_7.port_b_logical_ram_depth = 2048, + ram_block3a_7.port_b_logical_ram_width = 16, + ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_7.ram_block_type = "auto", + ram_block3a_7.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_8 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[8]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_8portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_8.connectivity_checking = "OFF", + ram_block3a_8.logical_ram_name = "ALTSYNCRAM", + ram_block3a_8.mixed_port_feed_through_mode = "dont_care", + ram_block3a_8.operation_mode = "dual_port", + ram_block3a_8.port_a_address_width = 11, + ram_block3a_8.port_a_data_width = 1, + ram_block3a_8.port_a_first_address = 0, + ram_block3a_8.port_a_first_bit_number = 8, + ram_block3a_8.port_a_last_address = 2047, + ram_block3a_8.port_a_logical_ram_depth = 2048, + ram_block3a_8.port_a_logical_ram_width = 16, + ram_block3a_8.port_b_address_clear = "none", + ram_block3a_8.port_b_address_clock = "clock1", + ram_block3a_8.port_b_address_width = 11, + ram_block3a_8.port_b_data_out_clear = "none", + ram_block3a_8.port_b_data_out_clock = "none", + ram_block3a_8.port_b_data_width = 1, + ram_block3a_8.port_b_first_address = 0, + ram_block3a_8.port_b_first_bit_number = 8, + ram_block3a_8.port_b_last_address = 2047, + ram_block3a_8.port_b_logical_ram_depth = 2048, + ram_block3a_8.port_b_logical_ram_width = 16, + ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_8.ram_block_type = "auto", + ram_block3a_8.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_9 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[9]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_9portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_9.connectivity_checking = "OFF", + ram_block3a_9.logical_ram_name = "ALTSYNCRAM", + ram_block3a_9.mixed_port_feed_through_mode = "dont_care", + ram_block3a_9.operation_mode = "dual_port", + ram_block3a_9.port_a_address_width = 11, + ram_block3a_9.port_a_data_width = 1, + ram_block3a_9.port_a_first_address = 0, + ram_block3a_9.port_a_first_bit_number = 9, + ram_block3a_9.port_a_last_address = 2047, + ram_block3a_9.port_a_logical_ram_depth = 2048, + ram_block3a_9.port_a_logical_ram_width = 16, + ram_block3a_9.port_b_address_clear = "none", + ram_block3a_9.port_b_address_clock = "clock1", + ram_block3a_9.port_b_address_width = 11, + ram_block3a_9.port_b_data_out_clear = "none", + ram_block3a_9.port_b_data_out_clock = "none", + ram_block3a_9.port_b_data_width = 1, + ram_block3a_9.port_b_first_address = 0, + ram_block3a_9.port_b_first_bit_number = 9, + ram_block3a_9.port_b_last_address = 2047, + ram_block3a_9.port_b_logical_ram_depth = 2048, + ram_block3a_9.port_b_logical_ram_width = 16, + ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_9.ram_block_type = "auto", + ram_block3a_9.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_10 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[10]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_10portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_10.connectivity_checking = "OFF", + ram_block3a_10.logical_ram_name = "ALTSYNCRAM", + ram_block3a_10.mixed_port_feed_through_mode = "dont_care", + ram_block3a_10.operation_mode = "dual_port", + ram_block3a_10.port_a_address_width = 11, + ram_block3a_10.port_a_data_width = 1, + ram_block3a_10.port_a_first_address = 0, + ram_block3a_10.port_a_first_bit_number = 10, + ram_block3a_10.port_a_last_address = 2047, + ram_block3a_10.port_a_logical_ram_depth = 2048, + ram_block3a_10.port_a_logical_ram_width = 16, + ram_block3a_10.port_b_address_clear = "none", + ram_block3a_10.port_b_address_clock = "clock1", + ram_block3a_10.port_b_address_width = 11, + ram_block3a_10.port_b_data_out_clear = "none", + ram_block3a_10.port_b_data_out_clock = "none", + ram_block3a_10.port_b_data_width = 1, + ram_block3a_10.port_b_first_address = 0, + ram_block3a_10.port_b_first_bit_number = 10, + ram_block3a_10.port_b_last_address = 2047, + ram_block3a_10.port_b_logical_ram_depth = 2048, + ram_block3a_10.port_b_logical_ram_width = 16, + ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_10.ram_block_type = "auto", + ram_block3a_10.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_11 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[11]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_11portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_11.connectivity_checking = "OFF", + ram_block3a_11.logical_ram_name = "ALTSYNCRAM", + ram_block3a_11.mixed_port_feed_through_mode = "dont_care", + ram_block3a_11.operation_mode = "dual_port", + ram_block3a_11.port_a_address_width = 11, + ram_block3a_11.port_a_data_width = 1, + ram_block3a_11.port_a_first_address = 0, + ram_block3a_11.port_a_first_bit_number = 11, + ram_block3a_11.port_a_last_address = 2047, + ram_block3a_11.port_a_logical_ram_depth = 2048, + ram_block3a_11.port_a_logical_ram_width = 16, + ram_block3a_11.port_b_address_clear = "none", + ram_block3a_11.port_b_address_clock = "clock1", + ram_block3a_11.port_b_address_width = 11, + ram_block3a_11.port_b_data_out_clear = "none", + ram_block3a_11.port_b_data_out_clock = "none", + ram_block3a_11.port_b_data_width = 1, + ram_block3a_11.port_b_first_address = 0, + ram_block3a_11.port_b_first_bit_number = 11, + ram_block3a_11.port_b_last_address = 2047, + ram_block3a_11.port_b_logical_ram_depth = 2048, + ram_block3a_11.port_b_logical_ram_width = 16, + ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_11.ram_block_type = "auto", + ram_block3a_11.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_12 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[12]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_12portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_12.connectivity_checking = "OFF", + ram_block3a_12.logical_ram_name = "ALTSYNCRAM", + ram_block3a_12.mixed_port_feed_through_mode = "dont_care", + ram_block3a_12.operation_mode = "dual_port", + ram_block3a_12.port_a_address_width = 11, + ram_block3a_12.port_a_data_width = 1, + ram_block3a_12.port_a_first_address = 0, + ram_block3a_12.port_a_first_bit_number = 12, + ram_block3a_12.port_a_last_address = 2047, + ram_block3a_12.port_a_logical_ram_depth = 2048, + ram_block3a_12.port_a_logical_ram_width = 16, + ram_block3a_12.port_b_address_clear = "none", + ram_block3a_12.port_b_address_clock = "clock1", + ram_block3a_12.port_b_address_width = 11, + ram_block3a_12.port_b_data_out_clear = "none", + ram_block3a_12.port_b_data_out_clock = "none", + ram_block3a_12.port_b_data_width = 1, + ram_block3a_12.port_b_first_address = 0, + ram_block3a_12.port_b_first_bit_number = 12, + ram_block3a_12.port_b_last_address = 2047, + ram_block3a_12.port_b_logical_ram_depth = 2048, + ram_block3a_12.port_b_logical_ram_width = 16, + ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_12.ram_block_type = "auto", + ram_block3a_12.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_13 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[13]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_13portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_13.connectivity_checking = "OFF", + ram_block3a_13.logical_ram_name = "ALTSYNCRAM", + ram_block3a_13.mixed_port_feed_through_mode = "dont_care", + ram_block3a_13.operation_mode = "dual_port", + ram_block3a_13.port_a_address_width = 11, + ram_block3a_13.port_a_data_width = 1, + ram_block3a_13.port_a_first_address = 0, + ram_block3a_13.port_a_first_bit_number = 13, + ram_block3a_13.port_a_last_address = 2047, + ram_block3a_13.port_a_logical_ram_depth = 2048, + ram_block3a_13.port_a_logical_ram_width = 16, + ram_block3a_13.port_b_address_clear = "none", + ram_block3a_13.port_b_address_clock = "clock1", + ram_block3a_13.port_b_address_width = 11, + ram_block3a_13.port_b_data_out_clear = "none", + ram_block3a_13.port_b_data_out_clock = "none", + ram_block3a_13.port_b_data_width = 1, + ram_block3a_13.port_b_first_address = 0, + ram_block3a_13.port_b_first_bit_number = 13, + ram_block3a_13.port_b_last_address = 2047, + ram_block3a_13.port_b_logical_ram_depth = 2048, + ram_block3a_13.port_b_logical_ram_width = 16, + ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_13.ram_block_type = "auto", + ram_block3a_13.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_14 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[14]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_14portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_14.connectivity_checking = "OFF", + ram_block3a_14.logical_ram_name = "ALTSYNCRAM", + ram_block3a_14.mixed_port_feed_through_mode = "dont_care", + ram_block3a_14.operation_mode = "dual_port", + ram_block3a_14.port_a_address_width = 11, + ram_block3a_14.port_a_data_width = 1, + ram_block3a_14.port_a_first_address = 0, + ram_block3a_14.port_a_first_bit_number = 14, + ram_block3a_14.port_a_last_address = 2047, + ram_block3a_14.port_a_logical_ram_depth = 2048, + ram_block3a_14.port_a_logical_ram_width = 16, + ram_block3a_14.port_b_address_clear = "none", + ram_block3a_14.port_b_address_clock = "clock1", + ram_block3a_14.port_b_address_width = 11, + ram_block3a_14.port_b_data_out_clear = "none", + ram_block3a_14.port_b_data_out_clock = "none", + ram_block3a_14.port_b_data_width = 1, + ram_block3a_14.port_b_first_address = 0, + ram_block3a_14.port_b_first_bit_number = 14, + ram_block3a_14.port_b_last_address = 2047, + ram_block3a_14.port_b_logical_ram_depth = 2048, + ram_block3a_14.port_b_logical_ram_width = 16, + ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_14.ram_block_type = "auto", + ram_block3a_14.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_15 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[15]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_15portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_15.connectivity_checking = "OFF", + ram_block3a_15.logical_ram_name = "ALTSYNCRAM", + ram_block3a_15.mixed_port_feed_through_mode = "dont_care", + ram_block3a_15.operation_mode = "dual_port", + ram_block3a_15.port_a_address_width = 11, + ram_block3a_15.port_a_data_width = 1, + ram_block3a_15.port_a_first_address = 0, + ram_block3a_15.port_a_first_bit_number = 15, + ram_block3a_15.port_a_last_address = 2047, + ram_block3a_15.port_a_logical_ram_depth = 2048, + ram_block3a_15.port_a_logical_ram_width = 16, + ram_block3a_15.port_b_address_clear = "none", + ram_block3a_15.port_b_address_clock = "clock1", + ram_block3a_15.port_b_address_width = 11, + ram_block3a_15.port_b_data_out_clear = "none", + ram_block3a_15.port_b_data_out_clock = "none", + ram_block3a_15.port_b_data_width = 1, + ram_block3a_15.port_b_first_address = 0, + ram_block3a_15.port_b_first_bit_number = 15, + ram_block3a_15.port_b_last_address = 2047, + ram_block3a_15.port_b_logical_ram_depth = 2048, + ram_block3a_15.port_b_logical_ram_width = 16, + ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_15.ram_block_type = "auto", + ram_block3a_15.lpm_type = "cyclone_ram_block"; + assign + address_a_wire = address_a, + address_b_wire = address_b, + q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; +endmodule //fifo_2k_altsyncram_6pl + + +//dffpipe DELAY=1 WIDTH=11 clock clrn d q +//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = lut 11 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_dffpipe_ab3 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; + input clock; + input clrn; + input [10:0] d; + output [10:0] q; + + wire [10:0] wire_dffe4a_D; + reg [10:0] dffe4a; + wire ena; + wire prn; + wire sclr; + + // synopsys translate_off + initial + dffe4a[0:0] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[0:0] <= 1'b1; + else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; + else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; + // synopsys translate_off + initial + dffe4a[1:1] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[1:1] <= 1'b1; + else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; + else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; + // synopsys translate_off + initial + dffe4a[2:2] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[2:2] <= 1'b1; + else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; + else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; + // synopsys translate_off + initial + dffe4a[3:3] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[3:3] <= 1'b1; + else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; + else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; + // synopsys translate_off + initial + dffe4a[4:4] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[4:4] <= 1'b1; + else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; + else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; + // synopsys translate_off + initial + dffe4a[5:5] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[5:5] <= 1'b1; + else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; + else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; + // synopsys translate_off + initial + dffe4a[6:6] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[6:6] <= 1'b1; + else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; + else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; + // synopsys translate_off + initial + dffe4a[7:7] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[7:7] <= 1'b1; + else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; + else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; + // synopsys translate_off + initial + dffe4a[8:8] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[8:8] <= 1'b1; + else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; + else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; + // synopsys translate_off + initial + dffe4a[9:9] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[9:9] <= 1'b1; + else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; + else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; + // synopsys translate_off + initial + dffe4a[10:10] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[10:10] <= 1'b1; + else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; + else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; + assign + wire_dffe4a_D = (d & {11{(~ sclr)}}); + assign + ena = 1'b1, + prn = 1'b1, + q = dffe4a, + sclr = 1'b0; +endmodule //fifo_2k_dffpipe_ab3 + + +//dffpipe WIDTH=11 clock clrn d q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + + +//dffpipe WIDTH=11 clock clrn d q +//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = lut 11 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_dffpipe_dm2 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; + input clock; + input clrn; + input [10:0] d; + output [10:0] q; + + wire [10:0] wire_dffe6a_D; + reg [10:0] dffe6a; + wire ena; + wire prn; + wire sclr; + + // synopsys translate_off + initial + dffe6a[0:0] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[0:0] <= 1'b1; + else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; + else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; + // synopsys translate_off + initial + dffe6a[1:1] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[1:1] <= 1'b1; + else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; + else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; + // synopsys translate_off + initial + dffe6a[2:2] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[2:2] <= 1'b1; + else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; + else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; + // synopsys translate_off + initial + dffe6a[3:3] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[3:3] <= 1'b1; + else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; + else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; + // synopsys translate_off + initial + dffe6a[4:4] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[4:4] <= 1'b1; + else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; + else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; + // synopsys translate_off + initial + dffe6a[5:5] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[5:5] <= 1'b1; + else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; + else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; + // synopsys translate_off + initial + dffe6a[6:6] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[6:6] <= 1'b1; + else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; + else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; + // synopsys translate_off + initial + dffe6a[7:7] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[7:7] <= 1'b1; + else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; + else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; + // synopsys translate_off + initial + dffe6a[8:8] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[8:8] <= 1'b1; + else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; + else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; + // synopsys translate_off + initial + dffe6a[9:9] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[9:9] <= 1'b1; + else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; + else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; + // synopsys translate_off + initial + dffe6a[10:10] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[10:10] <= 1'b1; + else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; + else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; + assign + wire_dffe6a_D = (d & {11{(~ sclr)}}); + assign + ena = 1'b1, + prn = 1'b1, + q = dffe6a, + sclr = 1'b0; +endmodule //fifo_2k_dffpipe_dm2 + +//synthesis_resources = lut 11 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_alt_synch_pipe_dm2 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; + input clock; + input clrn; + input [10:0] d; + output [10:0] q; + + wire [10:0] wire_dffpipe5_q; + + fifo_2k_dffpipe_dm2 dffpipe5 + ( + .clock(clock), + .clrn(clrn), + .d(d), + .q(wire_dffpipe5_q)); + assign + q = wire_dffpipe5_q; +endmodule //fifo_2k_alt_synch_pipe_dm2 + + +//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 11 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_add_sub_a18 + ( + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input [10:0] dataa; + input [10:0] datab; + output [10:0] result; + + wire [10:0] wire_add_sub_cella_combout; + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [0:0] wire_add_sub_cella_7cout; + wire [0:0] wire_add_sub_cella_8cout; + wire [0:0] wire_add_sub_cella_9cout; + wire [10:0] wire_add_sub_cella_dataa; + wire [10:0] wire_add_sub_cella_datab; + + cyclone_lcell add_sub_cella_0 + ( + .cin(1'b1), + .combout(wire_add_sub_cella_combout[0:0]), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "69b2", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_1 + ( + .cin(wire_add_sub_cella_0cout[0:0]), + .combout(wire_add_sub_cella_combout[1:1]), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "69b2", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_2 + ( + .cin(wire_add_sub_cella_1cout[0:0]), + .combout(wire_add_sub_cella_combout[2:2]), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "69b2", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_3 + ( + .cin(wire_add_sub_cella_2cout[0:0]), + .combout(wire_add_sub_cella_combout[3:3]), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "69b2", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_4 + ( + .cin(wire_add_sub_cella_3cout[0:0]), + .combout(wire_add_sub_cella_combout[4:4]), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "69b2", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_5 + ( + .cin(wire_add_sub_cella_4cout[0:0]), + .combout(wire_add_sub_cella_combout[5:5]), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "69b2", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_6 + ( + .cin(wire_add_sub_cella_5cout[0:0]), + .combout(wire_add_sub_cella_combout[6:6]), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "69b2", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_7 + ( + .cin(wire_add_sub_cella_6cout[0:0]), + .combout(wire_add_sub_cella_combout[7:7]), + .cout(wire_add_sub_cella_7cout[0:0]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "69b2", + add_sub_cella_7.operation_mode = "arithmetic", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_8 + ( + .cin(wire_add_sub_cella_7cout[0:0]), + .combout(wire_add_sub_cella_combout[8:8]), + .cout(wire_add_sub_cella_8cout[0:0]), + .dataa(wire_add_sub_cella_dataa[8:8]), + .datab(wire_add_sub_cella_datab[8:8]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_8.cin_used = "true", + add_sub_cella_8.lut_mask = "69b2", + add_sub_cella_8.operation_mode = "arithmetic", + add_sub_cella_8.sum_lutc_input = "cin", + add_sub_cella_8.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_9 + ( + .cin(wire_add_sub_cella_8cout[0:0]), + .combout(wire_add_sub_cella_combout[9:9]), + .cout(wire_add_sub_cella_9cout[0:0]), + .dataa(wire_add_sub_cella_dataa[9:9]), + .datab(wire_add_sub_cella_datab[9:9]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_9.cin_used = "true", + add_sub_cella_9.lut_mask = "69b2", + add_sub_cella_9.operation_mode = "arithmetic", + add_sub_cella_9.sum_lutc_input = "cin", + add_sub_cella_9.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_10 + ( + .cin(wire_add_sub_cella_9cout[0:0]), + .combout(wire_add_sub_cella_combout[10:10]), + .cout(), + .dataa(wire_add_sub_cella_dataa[10:10]), + .datab(wire_add_sub_cella_datab[10:10]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_10.cin_used = "true", + add_sub_cella_10.lut_mask = "6969", + add_sub_cella_10.operation_mode = "normal", + add_sub_cella_10.sum_lutc_input = "cin", + add_sub_cella_10.lpm_type = "cyclone_lcell"; + assign + wire_add_sub_cella_dataa = dataa, + wire_add_sub_cella_datab = datab; + assign + result = wire_add_sub_cella_combout; +endmodule //fifo_2k_add_sub_a18 + + +//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + + +//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 97 M4K 8 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_dcfifo_0cq + ( + aclr, + data, + q, + rdclk, + rdempty, + rdreq, + rdusedw, + wrclk, + wrfull, + wrreq, + wrusedw) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; + input aclr; + input [15:0] data; + output [15:0] q; + input rdclk; + output rdempty; + input rdreq; + output [10:0] rdusedw; + input wrclk; + output wrfull; + input wrreq; + output [10:0] wrusedw; + + wire [10:0] wire_rdptr_g_gray2bin_bin; + wire [10:0] wire_rs_dgwp_gray2bin_bin; + wire [10:0] wire_wrptr_g_gray2bin_bin; + wire [10:0] wire_ws_dgrp_gray2bin_bin; + wire [10:0] wire_rdptr_g_q; + wire [10:0] wire_rdptr_g1p_q; + wire [10:0] wire_wrptr_g1p_q; + wire [15:0] wire_fifo_ram_q_b; + reg [10:0] delayed_wrptr_g; + reg [10:0] wrptr_g; + wire [10:0] wire_rs_brp_q; + wire [10:0] wire_rs_bwp_q; + wire [10:0] wire_rs_dgwp_q; + wire [10:0] wire_ws_brp_q; + wire [10:0] wire_ws_bwp_q; + wire [10:0] wire_ws_dgrp_q; + wire [10:0] wire_rdusedw_sub_result; + wire [10:0] wire_wrusedw_sub_result; + reg wire_rdempty_eq_comp_aeb_int; + wire wire_rdempty_eq_comp_aeb; + wire [10:0] wire_rdempty_eq_comp_dataa; + wire [10:0] wire_rdempty_eq_comp_datab; + reg wire_wrfull_eq_comp_aeb_int; + wire wire_wrfull_eq_comp_aeb; + wire [10:0] wire_wrfull_eq_comp_dataa; + wire [10:0] wire_wrfull_eq_comp_datab; + wire int_rdempty; + wire int_wrfull; + wire valid_rdreq; + wire valid_wrreq; + + fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin + ( + .bin(wire_rdptr_g_gray2bin_bin), + .gray(wire_rdptr_g_q)); + fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin + ( + .bin(wire_rs_dgwp_gray2bin_bin), + .gray(wire_rs_dgwp_q)); + fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin + ( + .bin(wire_wrptr_g_gray2bin_bin), + .gray(wrptr_g)); + fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin + ( + .bin(wire_ws_dgrp_gray2bin_bin), + .gray(wire_ws_dgrp_q)); + fifo_2k_a_graycounter_726 rdptr_g + ( + .aclr(aclr), + .clock(rdclk), + .cnt_en(valid_rdreq), + .q(wire_rdptr_g_q)); + fifo_2k_a_graycounter_2r6 rdptr_g1p + ( + .aclr(aclr), + .clock(rdclk), + .cnt_en(valid_rdreq), + .q(wire_rdptr_g1p_q)); + fifo_2k_a_graycounter_2r6 wrptr_g1p + ( + .aclr(aclr), + .clock(wrclk), + .cnt_en(valid_wrreq), + .q(wire_wrptr_g1p_q)); + fifo_2k_altsyncram_6pl fifo_ram + ( + .address_a(wrptr_g), + .address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))), + .clock0(wrclk), + .clock1(rdclk), + .clocken1((valid_rdreq | int_rdempty)), + .data_a(data), + .q_b(wire_fifo_ram_q_b), + .wren_a(valid_wrreq)); + // synopsys translate_off + initial + delayed_wrptr_g = 0; + // synopsys translate_on + always @ ( posedge wrclk or posedge aclr) + if (aclr == 1'b1) delayed_wrptr_g <= 11'b0; + else delayed_wrptr_g <= wrptr_g; + // synopsys translate_off + initial + wrptr_g = 0; + // synopsys translate_on + always @ ( posedge wrclk or posedge aclr) + if (aclr == 1'b1) wrptr_g <= 11'b0; + else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; + fifo_2k_dffpipe_ab3 rs_brp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(wire_rdptr_g_gray2bin_bin), + .q(wire_rs_brp_q)); + fifo_2k_dffpipe_ab3 rs_bwp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(wire_rs_dgwp_gray2bin_bin), + .q(wire_rs_bwp_q)); + fifo_2k_alt_synch_pipe_dm2 rs_dgwp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(delayed_wrptr_g), + .q(wire_rs_dgwp_q)); + fifo_2k_dffpipe_ab3 ws_brp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_ws_dgrp_gray2bin_bin), + .q(wire_ws_brp_q)); + fifo_2k_dffpipe_ab3 ws_bwp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_wrptr_g_gray2bin_bin), + .q(wire_ws_bwp_q)); + fifo_2k_alt_synch_pipe_dm2 ws_dgrp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_rdptr_g_q), + .q(wire_ws_dgrp_q)); + fifo_2k_add_sub_a18 rdusedw_sub + ( + .dataa(wire_rs_bwp_q), + .datab(wire_rs_brp_q), + .result(wire_rdusedw_sub_result)); + fifo_2k_add_sub_a18 wrusedw_sub + ( + .dataa(wire_ws_bwp_q), + .datab(wire_ws_brp_q), + .result(wire_wrusedw_sub_result)); + always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) + if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) + begin + wire_rdempty_eq_comp_aeb_int = 1'b1; + end + else + begin + wire_rdempty_eq_comp_aeb_int = 1'b0; + end + assign + wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; + assign + wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, + wire_rdempty_eq_comp_datab = wire_rdptr_g_q; + always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) + if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) + begin + wire_wrfull_eq_comp_aeb_int = 1'b1; + end + else + begin + wire_wrfull_eq_comp_aeb_int = 1'b0; + end + assign + wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; + assign + wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, + wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; + assign + int_rdempty = wire_rdempty_eq_comp_aeb, + int_wrfull = wire_wrfull_eq_comp_aeb, + q = wire_fifo_ram_q_b, + rdempty = int_rdempty, + rdusedw = wire_rdusedw_sub_result, + valid_rdreq = rdreq, + valid_wrreq = wrreq, + wrfull = int_wrfull, + wrusedw = wire_wrusedw_sub_result; +endmodule //fifo_2k_dcfifo_0cq +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_2k ( + data, + wrreq, + rdreq, + rdclk, + wrclk, + aclr, + q, + rdempty, + rdusedw, + wrfull, + wrusedw)/* synthesis synthesis_clearbox = 1 */; + + input [15:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [15:0] q; + output rdempty; + output [10:0] rdusedw; + output wrfull; + output [10:0] wrusedw; + + wire sub_wire0; + wire [10:0] sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire [10:0] sub_wire4; + wire rdempty = sub_wire0; + wire [10:0] wrusedw = sub_wire1[10:0]; + wire wrfull = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire [10:0] rdusedw = sub_wire4[10:0]; + + fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: Depth NUMERIC "2048" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0] +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0] +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE diff --git a/megacells/fifo_2k_bb.v b/megacells/fifo_2k_bb.v new file mode 100644 index 000000000..3fcc2a496 --- /dev/null +++ b/megacells/fifo_2k_bb.v @@ -0,0 +1,131 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_2k.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_2k ( + data, + wrreq, + rdreq, + rdclk, + wrclk, + aclr, + q, + rdempty, + rdusedw, + wrfull, + wrusedw)/* synthesis synthesis_clearbox = 1 */; + + input [15:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [15:0] q; + output rdempty; + output [10:0] rdusedw; + output wrfull; + output [10:0] wrusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: Depth NUMERIC "2048" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0] +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0] +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE diff --git a/megacells/fifo_4k.v b/megacells/fifo_4k.v new file mode 100644 index 000000000..a5ab46677 --- /dev/null +++ b/megacells/fifo_4k.v @@ -0,0 +1,3495 @@ +// megafunction wizard: %FIFO%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4k.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + + +//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END + +//synthesis_resources = +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_a_gray2bin_9m4 + ( + bin, + gray) /* synthesis synthesis_clearbox=1 */; + output [11:0] bin; + input [11:0] gray; + + wire xor0; + wire xor1; + wire xor10; + wire xor2; + wire xor3; + wire xor4; + wire xor5; + wire xor6; + wire xor7; + wire xor8; + wire xor9; + + assign + bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, + xor0 = (gray[0] ^ xor1), + xor1 = (gray[1] ^ xor2), + xor10 = (gray[11] ^ gray[10]), + xor2 = (gray[2] ^ xor3), + xor3 = (gray[3] ^ xor4), + xor4 = (gray[4] ^ xor5), + xor5 = (gray[5] ^ xor6), + xor6 = (gray[6] ^ xor7), + xor7 = (gray[7] ^ xor8), + xor8 = (gray[8] ^ xor9), + xor9 = (gray[9] ^ xor10); +endmodule //fifo_4k_a_gray2bin_9m4 + + +//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 13 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_a_graycounter_826 + ( + aclr, + clock, + cnt_en, + q) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clock; + input cnt_en; + output [11:0] q; + + wire [0:0] wire_countera_0cout; + wire [0:0] wire_countera_1cout; + wire [0:0] wire_countera_2cout; + wire [0:0] wire_countera_3cout; + wire [0:0] wire_countera_4cout; + wire [0:0] wire_countera_5cout; + wire [0:0] wire_countera_6cout; + wire [0:0] wire_countera_7cout; + wire [0:0] wire_countera_8cout; + wire [0:0] wire_countera_9cout; + wire [0:0] wire_countera_10cout; + wire [11:0] wire_countera_regout; + wire wire_parity_cout; + wire wire_parity_regout; + wire [11:0] power_modified_counter_values; + wire sclr; + wire updown; + + cyclone_lcell countera_0 + ( + .aclr(aclr), + .cin(wire_parity_cout), + .clk(clock), + .combout(), + .cout(wire_countera_0cout[0:0]), + .dataa(cnt_en), + .datab(wire_countera_regout[0:0]), + .ena(1'b1), + .regout(wire_countera_regout[0:0]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_0.cin_used = "true", + countera_0.lut_mask = "c6a0", + countera_0.operation_mode = "arithmetic", + countera_0.sum_lutc_input = "cin", + countera_0.synch_mode = "on", + countera_0.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_1 + ( + .aclr(aclr), + .cin(wire_countera_0cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_1cout[0:0]), + .dataa(power_modified_counter_values[0]), + .datab(power_modified_counter_values[1]), + .ena(1'b1), + .regout(wire_countera_regout[1:1]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_1.cin_used = "true", + countera_1.lut_mask = "6c50", + countera_1.operation_mode = "arithmetic", + countera_1.sum_lutc_input = "cin", + countera_1.synch_mode = "on", + countera_1.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_2 + ( + .aclr(aclr), + .cin(wire_countera_1cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_2cout[0:0]), + .dataa(power_modified_counter_values[1]), + .datab(power_modified_counter_values[2]), + .ena(1'b1), + .regout(wire_countera_regout[2:2]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_2.cin_used = "true", + countera_2.lut_mask = "6c50", + countera_2.operation_mode = "arithmetic", + countera_2.sum_lutc_input = "cin", + countera_2.synch_mode = "on", + countera_2.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_3 + ( + .aclr(aclr), + .cin(wire_countera_2cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_3cout[0:0]), + .dataa(power_modified_counter_values[2]), + .datab(power_modified_counter_values[3]), + .ena(1'b1), + .regout(wire_countera_regout[3:3]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_3.cin_used = "true", + countera_3.lut_mask = "6c50", + countera_3.operation_mode = "arithmetic", + countera_3.sum_lutc_input = "cin", + countera_3.synch_mode = "on", + countera_3.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_4 + ( + .aclr(aclr), + .cin(wire_countera_3cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_4cout[0:0]), + .dataa(power_modified_counter_values[3]), + .datab(power_modified_counter_values[4]), + .ena(1'b1), + .regout(wire_countera_regout[4:4]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_4.cin_used = "true", + countera_4.lut_mask = "6c50", + countera_4.operation_mode = "arithmetic", + countera_4.sum_lutc_input = "cin", + countera_4.synch_mode = "on", + countera_4.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_5 + ( + .aclr(aclr), + .cin(wire_countera_4cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_5cout[0:0]), + .dataa(power_modified_counter_values[4]), + .datab(power_modified_counter_values[5]), + .ena(1'b1), + .regout(wire_countera_regout[5:5]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_5.cin_used = "true", + countera_5.lut_mask = "6c50", + countera_5.operation_mode = "arithmetic", + countera_5.sum_lutc_input = "cin", + countera_5.synch_mode = "on", + countera_5.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_6 + ( + .aclr(aclr), + .cin(wire_countera_5cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_6cout[0:0]), + .dataa(power_modified_counter_values[5]), + .datab(power_modified_counter_values[6]), + .ena(1'b1), + .regout(wire_countera_regout[6:6]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_6.cin_used = "true", + countera_6.lut_mask = "6c50", + countera_6.operation_mode = "arithmetic", + countera_6.sum_lutc_input = "cin", + countera_6.synch_mode = "on", + countera_6.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_7 + ( + .aclr(aclr), + .cin(wire_countera_6cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_7cout[0:0]), + .dataa(power_modified_counter_values[6]), + .datab(power_modified_counter_values[7]), + .ena(1'b1), + .regout(wire_countera_regout[7:7]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_7.cin_used = "true", + countera_7.lut_mask = "6c50", + countera_7.operation_mode = "arithmetic", + countera_7.sum_lutc_input = "cin", + countera_7.synch_mode = "on", + countera_7.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_8 + ( + .aclr(aclr), + .cin(wire_countera_7cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_8cout[0:0]), + .dataa(power_modified_counter_values[7]), + .datab(power_modified_counter_values[8]), + .ena(1'b1), + .regout(wire_countera_regout[8:8]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_8.cin_used = "true", + countera_8.lut_mask = "6c50", + countera_8.operation_mode = "arithmetic", + countera_8.sum_lutc_input = "cin", + countera_8.synch_mode = "on", + countera_8.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_9 + ( + .aclr(aclr), + .cin(wire_countera_8cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_9cout[0:0]), + .dataa(power_modified_counter_values[8]), + .datab(power_modified_counter_values[9]), + .ena(1'b1), + .regout(wire_countera_regout[9:9]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_9.cin_used = "true", + countera_9.lut_mask = "6c50", + countera_9.operation_mode = "arithmetic", + countera_9.sum_lutc_input = "cin", + countera_9.synch_mode = "on", + countera_9.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_10 + ( + .aclr(aclr), + .cin(wire_countera_9cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_10cout[0:0]), + .dataa(power_modified_counter_values[9]), + .datab(power_modified_counter_values[10]), + .ena(1'b1), + .regout(wire_countera_regout[10:10]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_10.cin_used = "true", + countera_10.lut_mask = "6c50", + countera_10.operation_mode = "arithmetic", + countera_10.sum_lutc_input = "cin", + countera_10.synch_mode = "on", + countera_10.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_11 + ( + .aclr(aclr), + .cin(wire_countera_10cout[0:0]), + .clk(clock), + .combout(), + .cout(), + .dataa(power_modified_counter_values[11]), + .ena(1'b1), + .regout(wire_countera_regout[11:11]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datab(1'b1), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_11.cin_used = "true", + countera_11.lut_mask = "5a5a", + countera_11.operation_mode = "normal", + countera_11.sum_lutc_input = "cin", + countera_11.synch_mode = "on", + countera_11.lpm_type = "cyclone_lcell"; + cyclone_lcell parity + ( + .aclr(aclr), + .cin(updown), + .clk(clock), + .combout(), + .cout(wire_parity_cout), + .dataa(cnt_en), + .datab(wire_parity_regout), + .ena(1'b1), + .regout(wire_parity_regout), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + parity.cin_used = "true", + parity.lut_mask = "6682", + parity.operation_mode = "arithmetic", + parity.synch_mode = "on", + parity.lpm_type = "cyclone_lcell"; + assign + power_modified_counter_values = {wire_countera_regout[11:0]}, + q = power_modified_counter_values, + sclr = 1'b0, + updown = 1'b1; +endmodule //fifo_4k_a_graycounter_826 + + +//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 13 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_a_graycounter_3r6 + ( + aclr, + clock, + cnt_en, + q) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clock; + input cnt_en; + output [11:0] q; + + wire [0:0] wire_countera_0cout; + wire [0:0] wire_countera_1cout; + wire [0:0] wire_countera_2cout; + wire [0:0] wire_countera_3cout; + wire [0:0] wire_countera_4cout; + wire [0:0] wire_countera_5cout; + wire [0:0] wire_countera_6cout; + wire [0:0] wire_countera_7cout; + wire [0:0] wire_countera_8cout; + wire [0:0] wire_countera_9cout; + wire [0:0] wire_countera_10cout; + wire [11:0] wire_countera_regout; + wire wire_parity_cout; + wire wire_parity_regout; + wire [11:0] power_modified_counter_values; + wire sclr; + wire updown; + + cyclone_lcell countera_0 + ( + .aclr(aclr), + .cin(wire_parity_cout), + .clk(clock), + .combout(), + .cout(wire_countera_0cout[0:0]), + .dataa(cnt_en), + .datab(wire_countera_regout[0:0]), + .ena(1'b1), + .regout(wire_countera_regout[0:0]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_0.cin_used = "true", + countera_0.lut_mask = "c6a0", + countera_0.operation_mode = "arithmetic", + countera_0.sum_lutc_input = "cin", + countera_0.synch_mode = "on", + countera_0.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_1 + ( + .aclr(aclr), + .cin(wire_countera_0cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_1cout[0:0]), + .dataa(power_modified_counter_values[0]), + .datab(power_modified_counter_values[1]), + .ena(1'b1), + .regout(wire_countera_regout[1:1]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_1.cin_used = "true", + countera_1.lut_mask = "6c50", + countera_1.operation_mode = "arithmetic", + countera_1.sum_lutc_input = "cin", + countera_1.synch_mode = "on", + countera_1.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_2 + ( + .aclr(aclr), + .cin(wire_countera_1cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_2cout[0:0]), + .dataa(power_modified_counter_values[1]), + .datab(power_modified_counter_values[2]), + .ena(1'b1), + .regout(wire_countera_regout[2:2]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_2.cin_used = "true", + countera_2.lut_mask = "6c50", + countera_2.operation_mode = "arithmetic", + countera_2.sum_lutc_input = "cin", + countera_2.synch_mode = "on", + countera_2.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_3 + ( + .aclr(aclr), + .cin(wire_countera_2cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_3cout[0:0]), + .dataa(power_modified_counter_values[2]), + .datab(power_modified_counter_values[3]), + .ena(1'b1), + .regout(wire_countera_regout[3:3]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_3.cin_used = "true", + countera_3.lut_mask = "6c50", + countera_3.operation_mode = "arithmetic", + countera_3.sum_lutc_input = "cin", + countera_3.synch_mode = "on", + countera_3.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_4 + ( + .aclr(aclr), + .cin(wire_countera_3cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_4cout[0:0]), + .dataa(power_modified_counter_values[3]), + .datab(power_modified_counter_values[4]), + .ena(1'b1), + .regout(wire_countera_regout[4:4]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_4.cin_used = "true", + countera_4.lut_mask = "6c50", + countera_4.operation_mode = "arithmetic", + countera_4.sum_lutc_input = "cin", + countera_4.synch_mode = "on", + countera_4.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_5 + ( + .aclr(aclr), + .cin(wire_countera_4cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_5cout[0:0]), + .dataa(power_modified_counter_values[4]), + .datab(power_modified_counter_values[5]), + .ena(1'b1), + .regout(wire_countera_regout[5:5]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_5.cin_used = "true", + countera_5.lut_mask = "6c50", + countera_5.operation_mode = "arithmetic", + countera_5.sum_lutc_input = "cin", + countera_5.synch_mode = "on", + countera_5.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_6 + ( + .aclr(aclr), + .cin(wire_countera_5cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_6cout[0:0]), + .dataa(power_modified_counter_values[5]), + .datab(power_modified_counter_values[6]), + .ena(1'b1), + .regout(wire_countera_regout[6:6]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_6.cin_used = "true", + countera_6.lut_mask = "6c50", + countera_6.operation_mode = "arithmetic", + countera_6.sum_lutc_input = "cin", + countera_6.synch_mode = "on", + countera_6.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_7 + ( + .aclr(aclr), + .cin(wire_countera_6cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_7cout[0:0]), + .dataa(power_modified_counter_values[6]), + .datab(power_modified_counter_values[7]), + .ena(1'b1), + .regout(wire_countera_regout[7:7]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_7.cin_used = "true", + countera_7.lut_mask = "6c50", + countera_7.operation_mode = "arithmetic", + countera_7.sum_lutc_input = "cin", + countera_7.synch_mode = "on", + countera_7.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_8 + ( + .aclr(aclr), + .cin(wire_countera_7cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_8cout[0:0]), + .dataa(power_modified_counter_values[7]), + .datab(power_modified_counter_values[8]), + .ena(1'b1), + .regout(wire_countera_regout[8:8]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_8.cin_used = "true", + countera_8.lut_mask = "6c50", + countera_8.operation_mode = "arithmetic", + countera_8.sum_lutc_input = "cin", + countera_8.synch_mode = "on", + countera_8.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_9 + ( + .aclr(aclr), + .cin(wire_countera_8cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_9cout[0:0]), + .dataa(power_modified_counter_values[8]), + .datab(power_modified_counter_values[9]), + .ena(1'b1), + .regout(wire_countera_regout[9:9]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_9.cin_used = "true", + countera_9.lut_mask = "6c50", + countera_9.operation_mode = "arithmetic", + countera_9.sum_lutc_input = "cin", + countera_9.synch_mode = "on", + countera_9.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_10 + ( + .aclr(aclr), + .cin(wire_countera_9cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_10cout[0:0]), + .dataa(power_modified_counter_values[9]), + .datab(power_modified_counter_values[10]), + .ena(1'b1), + .regout(wire_countera_regout[10:10]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_10.cin_used = "true", + countera_10.lut_mask = "6c50", + countera_10.operation_mode = "arithmetic", + countera_10.sum_lutc_input = "cin", + countera_10.synch_mode = "on", + countera_10.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_11 + ( + .aclr(aclr), + .cin(wire_countera_10cout[0:0]), + .clk(clock), + .combout(), + .cout(), + .dataa(power_modified_counter_values[11]), + .ena(1'b1), + .regout(wire_countera_regout[11:11]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datab(1'b1), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_11.cin_used = "true", + countera_11.lut_mask = "5a5a", + countera_11.operation_mode = "normal", + countera_11.sum_lutc_input = "cin", + countera_11.synch_mode = "on", + countera_11.lpm_type = "cyclone_lcell"; + cyclone_lcell parity + ( + .aclr(aclr), + .cin(updown), + .clk(clock), + .combout(), + .cout(wire_parity_cout), + .dataa(cnt_en), + .datab((~ wire_parity_regout)), + .ena(1'b1), + .regout(wire_parity_regout), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + parity.cin_used = "true", + parity.lut_mask = "9982", + parity.operation_mode = "arithmetic", + parity.synch_mode = "on", + parity.lpm_type = "cyclone_lcell"; + assign + power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])}, + q = power_modified_counter_values, + sclr = 1'b0, + updown = 1'b1; +endmodule //fifo_4k_a_graycounter_3r6 + + +//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a +//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = M4K 16 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_altsyncram_8pl + ( + address_a, + address_b, + clock0, + clock1, + clocken1, + data_a, + q_b, + wren_a) /* synthesis synthesis_clearbox=1 */; + input [11:0] address_a; + input [11:0] address_b; + input clock0; + input clock1; + input clocken1; + input [15:0] data_a; + output [15:0] q_b; + input wren_a; + + wire [0:0] wire_ram_block3a_0portbdataout; + wire [0:0] wire_ram_block3a_1portbdataout; + wire [0:0] wire_ram_block3a_2portbdataout; + wire [0:0] wire_ram_block3a_3portbdataout; + wire [0:0] wire_ram_block3a_4portbdataout; + wire [0:0] wire_ram_block3a_5portbdataout; + wire [0:0] wire_ram_block3a_6portbdataout; + wire [0:0] wire_ram_block3a_7portbdataout; + wire [0:0] wire_ram_block3a_8portbdataout; + wire [0:0] wire_ram_block3a_9portbdataout; + wire [0:0] wire_ram_block3a_10portbdataout; + wire [0:0] wire_ram_block3a_11portbdataout; + wire [0:0] wire_ram_block3a_12portbdataout; + wire [0:0] wire_ram_block3a_13portbdataout; + wire [0:0] wire_ram_block3a_14portbdataout; + wire [0:0] wire_ram_block3a_15portbdataout; + wire [11:0] address_a_wire; + wire [11:0] address_b_wire; + + cyclone_ram_block ram_block3a_0 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[0]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_0portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_0.connectivity_checking = "OFF", + ram_block3a_0.logical_ram_name = "ALTSYNCRAM", + ram_block3a_0.mixed_port_feed_through_mode = "dont_care", + ram_block3a_0.operation_mode = "dual_port", + ram_block3a_0.port_a_address_width = 12, + ram_block3a_0.port_a_data_width = 1, + ram_block3a_0.port_a_first_address = 0, + ram_block3a_0.port_a_first_bit_number = 0, + ram_block3a_0.port_a_last_address = 4095, + ram_block3a_0.port_a_logical_ram_depth = 4096, + ram_block3a_0.port_a_logical_ram_width = 16, + ram_block3a_0.port_b_address_clear = "none", + ram_block3a_0.port_b_address_clock = "clock1", + ram_block3a_0.port_b_address_width = 12, + ram_block3a_0.port_b_data_out_clear = "none", + ram_block3a_0.port_b_data_out_clock = "none", + ram_block3a_0.port_b_data_width = 1, + ram_block3a_0.port_b_first_address = 0, + ram_block3a_0.port_b_first_bit_number = 0, + ram_block3a_0.port_b_last_address = 4095, + ram_block3a_0.port_b_logical_ram_depth = 4096, + ram_block3a_0.port_b_logical_ram_width = 16, + ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_0.ram_block_type = "auto", + ram_block3a_0.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_1 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[1]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_1portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_1.connectivity_checking = "OFF", + ram_block3a_1.logical_ram_name = "ALTSYNCRAM", + ram_block3a_1.mixed_port_feed_through_mode = "dont_care", + ram_block3a_1.operation_mode = "dual_port", + ram_block3a_1.port_a_address_width = 12, + ram_block3a_1.port_a_data_width = 1, + ram_block3a_1.port_a_first_address = 0, + ram_block3a_1.port_a_first_bit_number = 1, + ram_block3a_1.port_a_last_address = 4095, + ram_block3a_1.port_a_logical_ram_depth = 4096, + ram_block3a_1.port_a_logical_ram_width = 16, + ram_block3a_1.port_b_address_clear = "none", + ram_block3a_1.port_b_address_clock = "clock1", + ram_block3a_1.port_b_address_width = 12, + ram_block3a_1.port_b_data_out_clear = "none", + ram_block3a_1.port_b_data_out_clock = "none", + ram_block3a_1.port_b_data_width = 1, + ram_block3a_1.port_b_first_address = 0, + ram_block3a_1.port_b_first_bit_number = 1, + ram_block3a_1.port_b_last_address = 4095, + ram_block3a_1.port_b_logical_ram_depth = 4096, + ram_block3a_1.port_b_logical_ram_width = 16, + ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_1.ram_block_type = "auto", + ram_block3a_1.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_2 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[2]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_2portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_2.connectivity_checking = "OFF", + ram_block3a_2.logical_ram_name = "ALTSYNCRAM", + ram_block3a_2.mixed_port_feed_through_mode = "dont_care", + ram_block3a_2.operation_mode = "dual_port", + ram_block3a_2.port_a_address_width = 12, + ram_block3a_2.port_a_data_width = 1, + ram_block3a_2.port_a_first_address = 0, + ram_block3a_2.port_a_first_bit_number = 2, + ram_block3a_2.port_a_last_address = 4095, + ram_block3a_2.port_a_logical_ram_depth = 4096, + ram_block3a_2.port_a_logical_ram_width = 16, + ram_block3a_2.port_b_address_clear = "none", + ram_block3a_2.port_b_address_clock = "clock1", + ram_block3a_2.port_b_address_width = 12, + ram_block3a_2.port_b_data_out_clear = "none", + ram_block3a_2.port_b_data_out_clock = "none", + ram_block3a_2.port_b_data_width = 1, + ram_block3a_2.port_b_first_address = 0, + ram_block3a_2.port_b_first_bit_number = 2, + ram_block3a_2.port_b_last_address = 4095, + ram_block3a_2.port_b_logical_ram_depth = 4096, + ram_block3a_2.port_b_logical_ram_width = 16, + ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_2.ram_block_type = "auto", + ram_block3a_2.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_3 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[3]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_3portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_3.connectivity_checking = "OFF", + ram_block3a_3.logical_ram_name = "ALTSYNCRAM", + ram_block3a_3.mixed_port_feed_through_mode = "dont_care", + ram_block3a_3.operation_mode = "dual_port", + ram_block3a_3.port_a_address_width = 12, + ram_block3a_3.port_a_data_width = 1, + ram_block3a_3.port_a_first_address = 0, + ram_block3a_3.port_a_first_bit_number = 3, + ram_block3a_3.port_a_last_address = 4095, + ram_block3a_3.port_a_logical_ram_depth = 4096, + ram_block3a_3.port_a_logical_ram_width = 16, + ram_block3a_3.port_b_address_clear = "none", + ram_block3a_3.port_b_address_clock = "clock1", + ram_block3a_3.port_b_address_width = 12, + ram_block3a_3.port_b_data_out_clear = "none", + ram_block3a_3.port_b_data_out_clock = "none", + ram_block3a_3.port_b_data_width = 1, + ram_block3a_3.port_b_first_address = 0, + ram_block3a_3.port_b_first_bit_number = 3, + ram_block3a_3.port_b_last_address = 4095, + ram_block3a_3.port_b_logical_ram_depth = 4096, + ram_block3a_3.port_b_logical_ram_width = 16, + ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_3.ram_block_type = "auto", + ram_block3a_3.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_4 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[4]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_4portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_4.connectivity_checking = "OFF", + ram_block3a_4.logical_ram_name = "ALTSYNCRAM", + ram_block3a_4.mixed_port_feed_through_mode = "dont_care", + ram_block3a_4.operation_mode = "dual_port", + ram_block3a_4.port_a_address_width = 12, + ram_block3a_4.port_a_data_width = 1, + ram_block3a_4.port_a_first_address = 0, + ram_block3a_4.port_a_first_bit_number = 4, + ram_block3a_4.port_a_last_address = 4095, + ram_block3a_4.port_a_logical_ram_depth = 4096, + ram_block3a_4.port_a_logical_ram_width = 16, + ram_block3a_4.port_b_address_clear = "none", + ram_block3a_4.port_b_address_clock = "clock1", + ram_block3a_4.port_b_address_width = 12, + ram_block3a_4.port_b_data_out_clear = "none", + ram_block3a_4.port_b_data_out_clock = "none", + ram_block3a_4.port_b_data_width = 1, + ram_block3a_4.port_b_first_address = 0, + ram_block3a_4.port_b_first_bit_number = 4, + ram_block3a_4.port_b_last_address = 4095, + ram_block3a_4.port_b_logical_ram_depth = 4096, + ram_block3a_4.port_b_logical_ram_width = 16, + ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_4.ram_block_type = "auto", + ram_block3a_4.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_5 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[5]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_5portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_5.connectivity_checking = "OFF", + ram_block3a_5.logical_ram_name = "ALTSYNCRAM", + ram_block3a_5.mixed_port_feed_through_mode = "dont_care", + ram_block3a_5.operation_mode = "dual_port", + ram_block3a_5.port_a_address_width = 12, + ram_block3a_5.port_a_data_width = 1, + ram_block3a_5.port_a_first_address = 0, + ram_block3a_5.port_a_first_bit_number = 5, + ram_block3a_5.port_a_last_address = 4095, + ram_block3a_5.port_a_logical_ram_depth = 4096, + ram_block3a_5.port_a_logical_ram_width = 16, + ram_block3a_5.port_b_address_clear = "none", + ram_block3a_5.port_b_address_clock = "clock1", + ram_block3a_5.port_b_address_width = 12, + ram_block3a_5.port_b_data_out_clear = "none", + ram_block3a_5.port_b_data_out_clock = "none", + ram_block3a_5.port_b_data_width = 1, + ram_block3a_5.port_b_first_address = 0, + ram_block3a_5.port_b_first_bit_number = 5, + ram_block3a_5.port_b_last_address = 4095, + ram_block3a_5.port_b_logical_ram_depth = 4096, + ram_block3a_5.port_b_logical_ram_width = 16, + ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_5.ram_block_type = "auto", + ram_block3a_5.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_6 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[6]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_6portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_6.connectivity_checking = "OFF", + ram_block3a_6.logical_ram_name = "ALTSYNCRAM", + ram_block3a_6.mixed_port_feed_through_mode = "dont_care", + ram_block3a_6.operation_mode = "dual_port", + ram_block3a_6.port_a_address_width = 12, + ram_block3a_6.port_a_data_width = 1, + ram_block3a_6.port_a_first_address = 0, + ram_block3a_6.port_a_first_bit_number = 6, + ram_block3a_6.port_a_last_address = 4095, + ram_block3a_6.port_a_logical_ram_depth = 4096, + ram_block3a_6.port_a_logical_ram_width = 16, + ram_block3a_6.port_b_address_clear = "none", + ram_block3a_6.port_b_address_clock = "clock1", + ram_block3a_6.port_b_address_width = 12, + ram_block3a_6.port_b_data_out_clear = "none", + ram_block3a_6.port_b_data_out_clock = "none", + ram_block3a_6.port_b_data_width = 1, + ram_block3a_6.port_b_first_address = 0, + ram_block3a_6.port_b_first_bit_number = 6, + ram_block3a_6.port_b_last_address = 4095, + ram_block3a_6.port_b_logical_ram_depth = 4096, + ram_block3a_6.port_b_logical_ram_width = 16, + ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_6.ram_block_type = "auto", + ram_block3a_6.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_7 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[7]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_7portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_7.connectivity_checking = "OFF", + ram_block3a_7.logical_ram_name = "ALTSYNCRAM", + ram_block3a_7.mixed_port_feed_through_mode = "dont_care", + ram_block3a_7.operation_mode = "dual_port", + ram_block3a_7.port_a_address_width = 12, + ram_block3a_7.port_a_data_width = 1, + ram_block3a_7.port_a_first_address = 0, + ram_block3a_7.port_a_first_bit_number = 7, + ram_block3a_7.port_a_last_address = 4095, + ram_block3a_7.port_a_logical_ram_depth = 4096, + ram_block3a_7.port_a_logical_ram_width = 16, + ram_block3a_7.port_b_address_clear = "none", + ram_block3a_7.port_b_address_clock = "clock1", + ram_block3a_7.port_b_address_width = 12, + ram_block3a_7.port_b_data_out_clear = "none", + ram_block3a_7.port_b_data_out_clock = "none", + ram_block3a_7.port_b_data_width = 1, + ram_block3a_7.port_b_first_address = 0, + ram_block3a_7.port_b_first_bit_number = 7, + ram_block3a_7.port_b_last_address = 4095, + ram_block3a_7.port_b_logical_ram_depth = 4096, + ram_block3a_7.port_b_logical_ram_width = 16, + ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_7.ram_block_type = "auto", + ram_block3a_7.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_8 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[8]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_8portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_8.connectivity_checking = "OFF", + ram_block3a_8.logical_ram_name = "ALTSYNCRAM", + ram_block3a_8.mixed_port_feed_through_mode = "dont_care", + ram_block3a_8.operation_mode = "dual_port", + ram_block3a_8.port_a_address_width = 12, + ram_block3a_8.port_a_data_width = 1, + ram_block3a_8.port_a_first_address = 0, + ram_block3a_8.port_a_first_bit_number = 8, + ram_block3a_8.port_a_last_address = 4095, + ram_block3a_8.port_a_logical_ram_depth = 4096, + ram_block3a_8.port_a_logical_ram_width = 16, + ram_block3a_8.port_b_address_clear = "none", + ram_block3a_8.port_b_address_clock = "clock1", + ram_block3a_8.port_b_address_width = 12, + ram_block3a_8.port_b_data_out_clear = "none", + ram_block3a_8.port_b_data_out_clock = "none", + ram_block3a_8.port_b_data_width = 1, + ram_block3a_8.port_b_first_address = 0, + ram_block3a_8.port_b_first_bit_number = 8, + ram_block3a_8.port_b_last_address = 4095, + ram_block3a_8.port_b_logical_ram_depth = 4096, + ram_block3a_8.port_b_logical_ram_width = 16, + ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_8.ram_block_type = "auto", + ram_block3a_8.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_9 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[9]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_9portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_9.connectivity_checking = "OFF", + ram_block3a_9.logical_ram_name = "ALTSYNCRAM", + ram_block3a_9.mixed_port_feed_through_mode = "dont_care", + ram_block3a_9.operation_mode = "dual_port", + ram_block3a_9.port_a_address_width = 12, + ram_block3a_9.port_a_data_width = 1, + ram_block3a_9.port_a_first_address = 0, + ram_block3a_9.port_a_first_bit_number = 9, + ram_block3a_9.port_a_last_address = 4095, + ram_block3a_9.port_a_logical_ram_depth = 4096, + ram_block3a_9.port_a_logical_ram_width = 16, + ram_block3a_9.port_b_address_clear = "none", + ram_block3a_9.port_b_address_clock = "clock1", + ram_block3a_9.port_b_address_width = 12, + ram_block3a_9.port_b_data_out_clear = "none", + ram_block3a_9.port_b_data_out_clock = "none", + ram_block3a_9.port_b_data_width = 1, + ram_block3a_9.port_b_first_address = 0, + ram_block3a_9.port_b_first_bit_number = 9, + ram_block3a_9.port_b_last_address = 4095, + ram_block3a_9.port_b_logical_ram_depth = 4096, + ram_block3a_9.port_b_logical_ram_width = 16, + ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_9.ram_block_type = "auto", + ram_block3a_9.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_10 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[10]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_10portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_10.connectivity_checking = "OFF", + ram_block3a_10.logical_ram_name = "ALTSYNCRAM", + ram_block3a_10.mixed_port_feed_through_mode = "dont_care", + ram_block3a_10.operation_mode = "dual_port", + ram_block3a_10.port_a_address_width = 12, + ram_block3a_10.port_a_data_width = 1, + ram_block3a_10.port_a_first_address = 0, + ram_block3a_10.port_a_first_bit_number = 10, + ram_block3a_10.port_a_last_address = 4095, + ram_block3a_10.port_a_logical_ram_depth = 4096, + ram_block3a_10.port_a_logical_ram_width = 16, + ram_block3a_10.port_b_address_clear = "none", + ram_block3a_10.port_b_address_clock = "clock1", + ram_block3a_10.port_b_address_width = 12, + ram_block3a_10.port_b_data_out_clear = "none", + ram_block3a_10.port_b_data_out_clock = "none", + ram_block3a_10.port_b_data_width = 1, + ram_block3a_10.port_b_first_address = 0, + ram_block3a_10.port_b_first_bit_number = 10, + ram_block3a_10.port_b_last_address = 4095, + ram_block3a_10.port_b_logical_ram_depth = 4096, + ram_block3a_10.port_b_logical_ram_width = 16, + ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_10.ram_block_type = "auto", + ram_block3a_10.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_11 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[11]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_11portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_11.connectivity_checking = "OFF", + ram_block3a_11.logical_ram_name = "ALTSYNCRAM", + ram_block3a_11.mixed_port_feed_through_mode = "dont_care", + ram_block3a_11.operation_mode = "dual_port", + ram_block3a_11.port_a_address_width = 12, + ram_block3a_11.port_a_data_width = 1, + ram_block3a_11.port_a_first_address = 0, + ram_block3a_11.port_a_first_bit_number = 11, + ram_block3a_11.port_a_last_address = 4095, + ram_block3a_11.port_a_logical_ram_depth = 4096, + ram_block3a_11.port_a_logical_ram_width = 16, + ram_block3a_11.port_b_address_clear = "none", + ram_block3a_11.port_b_address_clock = "clock1", + ram_block3a_11.port_b_address_width = 12, + ram_block3a_11.port_b_data_out_clear = "none", + ram_block3a_11.port_b_data_out_clock = "none", + ram_block3a_11.port_b_data_width = 1, + ram_block3a_11.port_b_first_address = 0, + ram_block3a_11.port_b_first_bit_number = 11, + ram_block3a_11.port_b_last_address = 4095, + ram_block3a_11.port_b_logical_ram_depth = 4096, + ram_block3a_11.port_b_logical_ram_width = 16, + ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_11.ram_block_type = "auto", + ram_block3a_11.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_12 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[12]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_12portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_12.connectivity_checking = "OFF", + ram_block3a_12.logical_ram_name = "ALTSYNCRAM", + ram_block3a_12.mixed_port_feed_through_mode = "dont_care", + ram_block3a_12.operation_mode = "dual_port", + ram_block3a_12.port_a_address_width = 12, + ram_block3a_12.port_a_data_width = 1, + ram_block3a_12.port_a_first_address = 0, + ram_block3a_12.port_a_first_bit_number = 12, + ram_block3a_12.port_a_last_address = 4095, + ram_block3a_12.port_a_logical_ram_depth = 4096, + ram_block3a_12.port_a_logical_ram_width = 16, + ram_block3a_12.port_b_address_clear = "none", + ram_block3a_12.port_b_address_clock = "clock1", + ram_block3a_12.port_b_address_width = 12, + ram_block3a_12.port_b_data_out_clear = "none", + ram_block3a_12.port_b_data_out_clock = "none", + ram_block3a_12.port_b_data_width = 1, + ram_block3a_12.port_b_first_address = 0, + ram_block3a_12.port_b_first_bit_number = 12, + ram_block3a_12.port_b_last_address = 4095, + ram_block3a_12.port_b_logical_ram_depth = 4096, + ram_block3a_12.port_b_logical_ram_width = 16, + ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_12.ram_block_type = "auto", + ram_block3a_12.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_13 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[13]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_13portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_13.connectivity_checking = "OFF", + ram_block3a_13.logical_ram_name = "ALTSYNCRAM", + ram_block3a_13.mixed_port_feed_through_mode = "dont_care", + ram_block3a_13.operation_mode = "dual_port", + ram_block3a_13.port_a_address_width = 12, + ram_block3a_13.port_a_data_width = 1, + ram_block3a_13.port_a_first_address = 0, + ram_block3a_13.port_a_first_bit_number = 13, + ram_block3a_13.port_a_last_address = 4095, + ram_block3a_13.port_a_logical_ram_depth = 4096, + ram_block3a_13.port_a_logical_ram_width = 16, + ram_block3a_13.port_b_address_clear = "none", + ram_block3a_13.port_b_address_clock = "clock1", + ram_block3a_13.port_b_address_width = 12, + ram_block3a_13.port_b_data_out_clear = "none", + ram_block3a_13.port_b_data_out_clock = "none", + ram_block3a_13.port_b_data_width = 1, + ram_block3a_13.port_b_first_address = 0, + ram_block3a_13.port_b_first_bit_number = 13, + ram_block3a_13.port_b_last_address = 4095, + ram_block3a_13.port_b_logical_ram_depth = 4096, + ram_block3a_13.port_b_logical_ram_width = 16, + ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_13.ram_block_type = "auto", + ram_block3a_13.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_14 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[14]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_14portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_14.connectivity_checking = "OFF", + ram_block3a_14.logical_ram_name = "ALTSYNCRAM", + ram_block3a_14.mixed_port_feed_through_mode = "dont_care", + ram_block3a_14.operation_mode = "dual_port", + ram_block3a_14.port_a_address_width = 12, + ram_block3a_14.port_a_data_width = 1, + ram_block3a_14.port_a_first_address = 0, + ram_block3a_14.port_a_first_bit_number = 14, + ram_block3a_14.port_a_last_address = 4095, + ram_block3a_14.port_a_logical_ram_depth = 4096, + ram_block3a_14.port_a_logical_ram_width = 16, + ram_block3a_14.port_b_address_clear = "none", + ram_block3a_14.port_b_address_clock = "clock1", + ram_block3a_14.port_b_address_width = 12, + ram_block3a_14.port_b_data_out_clear = "none", + ram_block3a_14.port_b_data_out_clock = "none", + ram_block3a_14.port_b_data_width = 1, + ram_block3a_14.port_b_first_address = 0, + ram_block3a_14.port_b_first_bit_number = 14, + ram_block3a_14.port_b_last_address = 4095, + ram_block3a_14.port_b_logical_ram_depth = 4096, + ram_block3a_14.port_b_logical_ram_width = 16, + ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_14.ram_block_type = "auto", + ram_block3a_14.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_15 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[15]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_15portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_15.connectivity_checking = "OFF", + ram_block3a_15.logical_ram_name = "ALTSYNCRAM", + ram_block3a_15.mixed_port_feed_through_mode = "dont_care", + ram_block3a_15.operation_mode = "dual_port", + ram_block3a_15.port_a_address_width = 12, + ram_block3a_15.port_a_data_width = 1, + ram_block3a_15.port_a_first_address = 0, + ram_block3a_15.port_a_first_bit_number = 15, + ram_block3a_15.port_a_last_address = 4095, + ram_block3a_15.port_a_logical_ram_depth = 4096, + ram_block3a_15.port_a_logical_ram_width = 16, + ram_block3a_15.port_b_address_clear = "none", + ram_block3a_15.port_b_address_clock = "clock1", + ram_block3a_15.port_b_address_width = 12, + ram_block3a_15.port_b_data_out_clear = "none", + ram_block3a_15.port_b_data_out_clock = "none", + ram_block3a_15.port_b_data_width = 1, + ram_block3a_15.port_b_first_address = 0, + ram_block3a_15.port_b_first_bit_number = 15, + ram_block3a_15.port_b_last_address = 4095, + ram_block3a_15.port_b_logical_ram_depth = 4096, + ram_block3a_15.port_b_logical_ram_width = 16, + ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_15.ram_block_type = "auto", + ram_block3a_15.lpm_type = "cyclone_ram_block"; + assign + address_a_wire = address_a, + address_b_wire = address_b, + q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; +endmodule //fifo_4k_altsyncram_8pl + + +//dffpipe DELAY=1 WIDTH=12 clock clrn d q +//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_dffpipe_bb3 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; + input clock; + input clrn; + input [11:0] d; + output [11:0] q; + + wire [11:0] wire_dffe4a_D; + reg [11:0] dffe4a; + wire ena; + wire prn; + wire sclr; + + // synopsys translate_off + initial + dffe4a[0:0] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[0:0] <= 1'b1; + else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; + else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; + // synopsys translate_off + initial + dffe4a[1:1] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[1:1] <= 1'b1; + else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; + else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; + // synopsys translate_off + initial + dffe4a[2:2] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[2:2] <= 1'b1; + else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; + else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; + // synopsys translate_off + initial + dffe4a[3:3] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[3:3] <= 1'b1; + else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; + else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; + // synopsys translate_off + initial + dffe4a[4:4] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[4:4] <= 1'b1; + else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; + else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; + // synopsys translate_off + initial + dffe4a[5:5] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[5:5] <= 1'b1; + else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; + else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; + // synopsys translate_off + initial + dffe4a[6:6] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[6:6] <= 1'b1; + else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; + else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; + // synopsys translate_off + initial + dffe4a[7:7] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[7:7] <= 1'b1; + else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; + else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; + // synopsys translate_off + initial + dffe4a[8:8] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[8:8] <= 1'b1; + else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; + else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; + // synopsys translate_off + initial + dffe4a[9:9] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[9:9] <= 1'b1; + else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; + else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; + // synopsys translate_off + initial + dffe4a[10:10] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[10:10] <= 1'b1; + else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; + else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; + // synopsys translate_off + initial + dffe4a[11:11] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[11:11] <= 1'b1; + else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0; + else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11]; + assign + wire_dffe4a_D = (d & {12{(~ sclr)}}); + assign + ena = 1'b1, + prn = 1'b1, + q = dffe4a, + sclr = 1'b0; +endmodule //fifo_4k_dffpipe_bb3 + + +//dffpipe WIDTH=12 clock clrn d q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + + +//dffpipe WIDTH=12 clock clrn d q +//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_dffpipe_em2 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; + input clock; + input clrn; + input [11:0] d; + output [11:0] q; + + wire [11:0] wire_dffe6a_D; + reg [11:0] dffe6a; + wire ena; + wire prn; + wire sclr; + + // synopsys translate_off + initial + dffe6a[0:0] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[0:0] <= 1'b1; + else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; + else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; + // synopsys translate_off + initial + dffe6a[1:1] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[1:1] <= 1'b1; + else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; + else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; + // synopsys translate_off + initial + dffe6a[2:2] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[2:2] <= 1'b1; + else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; + else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; + // synopsys translate_off + initial + dffe6a[3:3] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[3:3] <= 1'b1; + else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; + else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; + // synopsys translate_off + initial + dffe6a[4:4] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[4:4] <= 1'b1; + else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; + else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; + // synopsys translate_off + initial + dffe6a[5:5] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[5:5] <= 1'b1; + else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; + else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; + // synopsys translate_off + initial + dffe6a[6:6] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[6:6] <= 1'b1; + else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; + else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; + // synopsys translate_off + initial + dffe6a[7:7] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[7:7] <= 1'b1; + else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; + else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; + // synopsys translate_off + initial + dffe6a[8:8] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[8:8] <= 1'b1; + else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; + else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; + // synopsys translate_off + initial + dffe6a[9:9] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[9:9] <= 1'b1; + else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; + else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; + // synopsys translate_off + initial + dffe6a[10:10] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[10:10] <= 1'b1; + else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; + else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; + // synopsys translate_off + initial + dffe6a[11:11] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[11:11] <= 1'b1; + else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0; + else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11]; + assign + wire_dffe6a_D = (d & {12{(~ sclr)}}); + assign + ena = 1'b1, + prn = 1'b1, + q = dffe6a, + sclr = 1'b0; +endmodule //fifo_4k_dffpipe_em2 + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_alt_synch_pipe_em2 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; + input clock; + input clrn; + input [11:0] d; + output [11:0] q; + + wire [11:0] wire_dffpipe5_q; + + fifo_4k_dffpipe_em2 dffpipe5 + ( + .clock(clock), + .clrn(clrn), + .d(d), + .q(wire_dffpipe5_q)); + assign + q = wire_dffpipe5_q; +endmodule //fifo_4k_alt_synch_pipe_em2 + + +//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_add_sub_b18 + ( + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input [11:0] dataa; + input [11:0] datab; + output [11:0] result; + + wire [11:0] wire_add_sub_cella_combout; + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [0:0] wire_add_sub_cella_7cout; + wire [0:0] wire_add_sub_cella_8cout; + wire [0:0] wire_add_sub_cella_9cout; + wire [0:0] wire_add_sub_cella_10cout; + wire [11:0] wire_add_sub_cella_dataa; + wire [11:0] wire_add_sub_cella_datab; + + cyclone_lcell add_sub_cella_0 + ( + .cin(1'b1), + .combout(wire_add_sub_cella_combout[0:0]), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "69b2", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_1 + ( + .cin(wire_add_sub_cella_0cout[0:0]), + .combout(wire_add_sub_cella_combout[1:1]), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "69b2", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_2 + ( + .cin(wire_add_sub_cella_1cout[0:0]), + .combout(wire_add_sub_cella_combout[2:2]), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "69b2", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_3 + ( + .cin(wire_add_sub_cella_2cout[0:0]), + .combout(wire_add_sub_cella_combout[3:3]), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "69b2", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_4 + ( + .cin(wire_add_sub_cella_3cout[0:0]), + .combout(wire_add_sub_cella_combout[4:4]), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "69b2", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_5 + ( + .cin(wire_add_sub_cella_4cout[0:0]), + .combout(wire_add_sub_cella_combout[5:5]), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "69b2", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_6 + ( + .cin(wire_add_sub_cella_5cout[0:0]), + .combout(wire_add_sub_cella_combout[6:6]), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "69b2", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_7 + ( + .cin(wire_add_sub_cella_6cout[0:0]), + .combout(wire_add_sub_cella_combout[7:7]), + .cout(wire_add_sub_cella_7cout[0:0]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "69b2", + add_sub_cella_7.operation_mode = "arithmetic", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_8 + ( + .cin(wire_add_sub_cella_7cout[0:0]), + .combout(wire_add_sub_cella_combout[8:8]), + .cout(wire_add_sub_cella_8cout[0:0]), + .dataa(wire_add_sub_cella_dataa[8:8]), + .datab(wire_add_sub_cella_datab[8:8]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_8.cin_used = "true", + add_sub_cella_8.lut_mask = "69b2", + add_sub_cella_8.operation_mode = "arithmetic", + add_sub_cella_8.sum_lutc_input = "cin", + add_sub_cella_8.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_9 + ( + .cin(wire_add_sub_cella_8cout[0:0]), + .combout(wire_add_sub_cella_combout[9:9]), + .cout(wire_add_sub_cella_9cout[0:0]), + .dataa(wire_add_sub_cella_dataa[9:9]), + .datab(wire_add_sub_cella_datab[9:9]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_9.cin_used = "true", + add_sub_cella_9.lut_mask = "69b2", + add_sub_cella_9.operation_mode = "arithmetic", + add_sub_cella_9.sum_lutc_input = "cin", + add_sub_cella_9.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_10 + ( + .cin(wire_add_sub_cella_9cout[0:0]), + .combout(wire_add_sub_cella_combout[10:10]), + .cout(wire_add_sub_cella_10cout[0:0]), + .dataa(wire_add_sub_cella_dataa[10:10]), + .datab(wire_add_sub_cella_datab[10:10]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_10.cin_used = "true", + add_sub_cella_10.lut_mask = "69b2", + add_sub_cella_10.operation_mode = "arithmetic", + add_sub_cella_10.sum_lutc_input = "cin", + add_sub_cella_10.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_11 + ( + .cin(wire_add_sub_cella_10cout[0:0]), + .combout(wire_add_sub_cella_combout[11:11]), + .cout(), + .dataa(wire_add_sub_cella_dataa[11:11]), + .datab(wire_add_sub_cella_datab[11:11]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_11.cin_used = "true", + add_sub_cella_11.lut_mask = "6969", + add_sub_cella_11.operation_mode = "normal", + add_sub_cella_11.sum_lutc_input = "cin", + add_sub_cella_11.lpm_type = "cyclone_lcell"; + assign + wire_add_sub_cella_dataa = dataa, + wire_add_sub_cella_datab = datab; + assign + result = wire_add_sub_cella_combout; +endmodule //fifo_4k_add_sub_b18 + + +//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + + +//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 104 M4K 16 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_dcfifo_6cq + ( + aclr, + data, + q, + rdclk, + rdempty, + rdreq, + rdusedw, + wrclk, + wrfull, + wrreq, + wrusedw) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; + input aclr; + input [15:0] data; + output [15:0] q; + input rdclk; + output rdempty; + input rdreq; + output [11:0] rdusedw; + input wrclk; + output wrfull; + input wrreq; + output [11:0] wrusedw; + + wire [11:0] wire_rdptr_g_gray2bin_bin; + wire [11:0] wire_rs_dgwp_gray2bin_bin; + wire [11:0] wire_wrptr_g_gray2bin_bin; + wire [11:0] wire_ws_dgrp_gray2bin_bin; + wire [11:0] wire_rdptr_g_q; + wire [11:0] wire_rdptr_g1p_q; + wire [11:0] wire_wrptr_g1p_q; + wire [15:0] wire_fifo_ram_q_b; + reg [11:0] delayed_wrptr_g; + reg [11:0] wrptr_g; + wire [11:0] wire_rs_brp_q; + wire [11:0] wire_rs_bwp_q; + wire [11:0] wire_rs_dgwp_q; + wire [11:0] wire_ws_brp_q; + wire [11:0] wire_ws_bwp_q; + wire [11:0] wire_ws_dgrp_q; + wire [11:0] wire_rdusedw_sub_result; + wire [11:0] wire_wrusedw_sub_result; + reg wire_rdempty_eq_comp_aeb_int; + wire wire_rdempty_eq_comp_aeb; + wire [11:0] wire_rdempty_eq_comp_dataa; + wire [11:0] wire_rdempty_eq_comp_datab; + reg wire_wrfull_eq_comp_aeb_int; + wire wire_wrfull_eq_comp_aeb; + wire [11:0] wire_wrfull_eq_comp_dataa; + wire [11:0] wire_wrfull_eq_comp_datab; + wire int_rdempty; + wire int_wrfull; + wire valid_rdreq; + wire valid_wrreq; + + fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin + ( + .bin(wire_rdptr_g_gray2bin_bin), + .gray(wire_rdptr_g_q)); + fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin + ( + .bin(wire_rs_dgwp_gray2bin_bin), + .gray(wire_rs_dgwp_q)); + fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin + ( + .bin(wire_wrptr_g_gray2bin_bin), + .gray(wrptr_g)); + fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin + ( + .bin(wire_ws_dgrp_gray2bin_bin), + .gray(wire_ws_dgrp_q)); + fifo_4k_a_graycounter_826 rdptr_g + ( + .aclr(aclr), + .clock(rdclk), + .cnt_en(valid_rdreq), + .q(wire_rdptr_g_q)); + fifo_4k_a_graycounter_3r6 rdptr_g1p + ( + .aclr(aclr), + .clock(rdclk), + .cnt_en(valid_rdreq), + .q(wire_rdptr_g1p_q)); + fifo_4k_a_graycounter_3r6 wrptr_g1p + ( + .aclr(aclr), + .clock(wrclk), + .cnt_en(valid_wrreq), + .q(wire_wrptr_g1p_q)); + fifo_4k_altsyncram_8pl fifo_ram + ( + .address_a(wrptr_g), + .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))), + .clock0(wrclk), + .clock1(rdclk), + .clocken1((valid_rdreq | int_rdempty)), + .data_a(data), + .q_b(wire_fifo_ram_q_b), + .wren_a(valid_wrreq)); + // synopsys translate_off + initial + delayed_wrptr_g = 0; + // synopsys translate_on + always @ ( posedge wrclk or posedge aclr) + if (aclr == 1'b1) delayed_wrptr_g <= 12'b0; + else delayed_wrptr_g <= wrptr_g; + // synopsys translate_off + initial + wrptr_g = 0; + // synopsys translate_on + always @ ( posedge wrclk or posedge aclr) + if (aclr == 1'b1) wrptr_g <= 12'b0; + else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; + fifo_4k_dffpipe_bb3 rs_brp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(wire_rdptr_g_gray2bin_bin), + .q(wire_rs_brp_q)); + fifo_4k_dffpipe_bb3 rs_bwp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(wire_rs_dgwp_gray2bin_bin), + .q(wire_rs_bwp_q)); + fifo_4k_alt_synch_pipe_em2 rs_dgwp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(delayed_wrptr_g), + .q(wire_rs_dgwp_q)); + fifo_4k_dffpipe_bb3 ws_brp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_ws_dgrp_gray2bin_bin), + .q(wire_ws_brp_q)); + fifo_4k_dffpipe_bb3 ws_bwp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_wrptr_g_gray2bin_bin), + .q(wire_ws_bwp_q)); + fifo_4k_alt_synch_pipe_em2 ws_dgrp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_rdptr_g_q), + .q(wire_ws_dgrp_q)); + fifo_4k_add_sub_b18 rdusedw_sub + ( + .dataa(wire_rs_bwp_q), + .datab(wire_rs_brp_q), + .result(wire_rdusedw_sub_result)); + fifo_4k_add_sub_b18 wrusedw_sub + ( + .dataa(wire_ws_bwp_q), + .datab(wire_ws_brp_q), + .result(wire_wrusedw_sub_result)); + always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) + if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) + begin + wire_rdempty_eq_comp_aeb_int = 1'b1; + end + else + begin + wire_rdempty_eq_comp_aeb_int = 1'b0; + end + assign + wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; + assign + wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, + wire_rdempty_eq_comp_datab = wire_rdptr_g_q; + always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) + if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) + begin + wire_wrfull_eq_comp_aeb_int = 1'b1; + end + else + begin + wire_wrfull_eq_comp_aeb_int = 1'b0; + end + assign + wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; + assign + wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, + wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; + assign + int_rdempty = wire_rdempty_eq_comp_aeb, + int_wrfull = wire_wrfull_eq_comp_aeb, + q = wire_fifo_ram_q_b, + rdempty = int_rdempty, + rdusedw = wire_rdusedw_sub_result, + valid_rdreq = rdreq, + valid_wrreq = wrreq, + wrfull = int_wrfull, + wrusedw = wire_wrusedw_sub_result; +endmodule //fifo_4k_dcfifo_6cq +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_4k ( + data, + wrreq, + rdreq, + rdclk, + wrclk, + aclr, + q, + rdempty, + rdusedw, + wrfull, + wrusedw)/* synthesis synthesis_clearbox = 1 */; + + input [15:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + + wire sub_wire0; + wire [11:0] sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire [11:0] sub_wire4; + wire rdempty = sub_wire0; + wire [11:0] wrusedw = sub_wire1[11:0]; + wire wrfull = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire [11:0] rdusedw = sub_wire4[11:0]; + + fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE diff --git a/megacells/fifo_4k_bb.v b/megacells/fifo_4k_bb.v new file mode 100644 index 000000000..fc4ca9797 --- /dev/null +++ b/megacells/fifo_4k_bb.v @@ -0,0 +1,131 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4k.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_4k ( + data, + wrreq, + rdreq, + rdclk, + wrclk, + aclr, + q, + rdempty, + rdusedw, + wrfull, + wrusedw)/* synthesis synthesis_clearbox = 1 */; + + input [15:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE diff --git a/megacells/mylpm_addsub.bsf b/megacells/mylpm_addsub.bsf new file mode 100755 index 000000000..e5c1ded7f --- /dev/null +++ b/megacells/mylpm_addsub.bsf @@ -0,0 +1,80 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 112) + (text "mylpm_addsub" (rect 26 2 145 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 93 30 108)(font "Arial" )) + (port + (pt 0 56) + (input) + (text "dataa[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) + (text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "datab[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) + (text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 64 88)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "clock" (rect 0 0 34 16)(font "Arial" (font_size 8))) + (text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 1)) + ) + (port + (pt 0 32) + (input) + (text "add_sub" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 80 32)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "result[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) + (text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 96 72)(line_width 3)) + ) + (drawing + (text "A" (rect 66 48 75 64)(font "Arial" (font_size 8))) + (text "B" (rect 66 80 75 96)(font "Arial" (font_size 8))) + (text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8))) + (line (pt 64 48)(pt 96 56)(line_width 1)) + (line (pt 96 56)(pt 96 88)(line_width 1)) + (line (pt 96 88)(pt 64 96)(line_width 1)) + (line (pt 64 96)(pt 64 48)(line_width 1)) + (line (pt 80 32)(pt 80 52)(line_width 1)) + (line (pt 106 40)(pt 125 40)(line_width 1)) + (line (pt 64 66)(pt 70 72)(line_width 1)) + (line (pt 70 72)(pt 64 78)(line_width 1)) + ) +) diff --git a/megacells/mylpm_addsub.cmp b/megacells/mylpm_addsub.cmp new file mode 100755 index 000000000..311c54a5b --- /dev/null +++ b/megacells/mylpm_addsub.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component mylpm_addsub + PORT + ( + add_sub : IN STD_LOGIC ; + dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + clock : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/megacells/mylpm_addsub.inc b/megacells/mylpm_addsub.inc new file mode 100755 index 000000000..d8b283f49 --- /dev/null +++ b/megacells/mylpm_addsub.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION mylpm_addsub +( + add_sub, + dataa[15..0], + datab[15..0], + clock +) + +RETURNS ( + result[15..0] +); diff --git a/megacells/mylpm_addsub.v b/megacells/mylpm_addsub.v new file mode 100755 index 000000000..0566f7e57 --- /dev/null +++ b/megacells/mylpm_addsub.v @@ -0,0 +1,102 @@ +// megafunction wizard: %LPM_ADD_SUB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_add_sub + +// ============================================================ +// File Name: mylpm_addsub.v +// Megafunction Name(s): +// lpm_add_sub +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +module mylpm_addsub ( + add_sub, + dataa, + datab, + clock, + result); + + input add_sub; + input [15:0] dataa; + input [15:0] datab; + input clock; + output [15:0] result; + + wire [15:0] sub_wire0; + wire [15:0] result = sub_wire0[15:0]; + + lpm_add_sub lpm_add_sub_component ( + .dataa (dataa), + .add_sub (add_sub), + .datab (datab), + .clock (clock), + .result (sub_wire0)); + defparam + lpm_add_sub_component.lpm_width = 16, + lpm_add_sub_component.lpm_direction = "UNUSED", + lpm_add_sub_component.lpm_type = "LPM_ADD_SUB", + lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO", + lpm_add_sub_component.lpm_pipeline = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "16" +// Retrieval info: PRIVATE: Function NUMERIC "2" +// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantA NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Overflow NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "1" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub +// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] +// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0] +// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0] +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0 +// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 +// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0 +// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/mylpm_addsub_bb.v b/megacells/mylpm_addsub_bb.v new file mode 100755 index 000000000..598d3da52 --- /dev/null +++ b/megacells/mylpm_addsub_bb.v @@ -0,0 +1,35 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module mylpm_addsub ( + add_sub, + dataa, + datab, + clock, + result); + + input add_sub; + input [15:0] dataa; + input [15:0] datab; + input clock; + output [15:0] result; + +endmodule + diff --git a/megacells/mylpm_addsub_inst.v b/megacells/mylpm_addsub_inst.v new file mode 100755 index 000000000..dd732bd6d --- /dev/null +++ b/megacells/mylpm_addsub_inst.v @@ -0,0 +1,7 @@ +mylpm_addsub mylpm_addsub_inst ( + .add_sub ( add_sub_sig ), + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .clock ( clock_sig ), + .result ( result_sig ) + ); diff --git a/megacells/pll.v b/megacells/pll.v new file mode 100644 index 000000000..dacd11f23 --- /dev/null +++ b/megacells/pll.v @@ -0,0 +1,207 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [5:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0) + // synopsys translate_off +, + .fbin (), + .pllena (), + .clkswitch (), + .areset (), + .pfdena (), + .clkena (), + .extclkena (), + .scanclk (), + .scanaclr (), + .scandata (), + .scanread (), + .scanwrite (), + .extclk (), + .clkbad (), + .activeclock (), + .locked (), + .clkloss (), + .scandataout (), + .scandone (), + .sclkout1 (), + .sclkout0 (), + .enable0 (), + .enable1 () + // synopsys translate_on + +); + defparam + altpll_component.clk0_duty_cycle = 50, + altpll_component.lpm_type = "altpll", + altpll_component.clk0_multiply_by = 1, + altpll_component.inclk0_input_frequency = 20833, + altpll_component.clk0_divide_by = 1, + altpll_component.pll_type = "AUTO", + altpll_component.clk0_time_delay = "0", + altpll_component.intended_device_family = "Cyclone", + altpll_component.operation_mode = "NORMAL", + altpll_component.compensate_clock = "CLK0", + altpll_component.clk0_phase_shift = "-3000"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE diff --git a/megacells/pll_bb.v b/megacells/pll_bb.v new file mode 100644 index 000000000..debadaa25 --- /dev/null +++ b/megacells/pll_bb.v @@ -0,0 +1,29 @@ +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module pll ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + diff --git a/megacells/pll_inst.v b/megacells/pll_inst.v new file mode 100644 index 000000000..97db58ba0 --- /dev/null +++ b/megacells/pll_inst.v @@ -0,0 +1,4 @@ +pll pll_inst ( + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ) + ); diff --git a/megacells/sub32.bsf b/megacells/sub32.bsf new file mode 100755 index 000000000..753fdc738 --- /dev/null +++ b/megacells/sub32.bsf @@ -0,0 +1,87 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 128) + (text "sub32" (rect 58 2 109 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 109 31 124)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "dataa[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "dataa[31..0]" (rect 4 24 73 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 64 40)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "datab[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "datab[31..0]" (rect 4 56 73 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 4 40 35 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clken" (rect 4 80 35 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 74 96)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) + (text "aclr" (rect 4 96 25 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 85 112)(line_width 1)) + ) + (port + (pt 160 56) + (output) + (text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "result[31..0]" (rect 88 40 157 56)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 96 56)(line_width 3)) + ) + (drawing + (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8))) + (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8))) + (text "A-B" (rect 72 48 94 64)(font "Arial" (font_size 8))) + (line (pt 64 32)(pt 96 40)(line_width 1)) + (line (pt 96 40)(pt 96 72)(line_width 1)) + (line (pt 96 72)(pt 64 80)(line_width 1)) + (line (pt 64 80)(pt 64 32)(line_width 1)) + (line (pt 74 96)(pt 74 77)(line_width 1)) + (line (pt 85 112)(pt 85 74)(line_width 1)) + (line (pt 64 50)(pt 70 56)(line_width 1)) + (line (pt 70 56)(pt 64 62)(line_width 1)) + ) +) diff --git a/megacells/sub32.cmp b/megacells/sub32.cmp new file mode 100755 index 000000000..0d5b62ef9 --- /dev/null +++ b/megacells/sub32.cmp @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component sub32 + PORT + ( + dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + clock : IN STD_LOGIC ; + aclr : IN STD_LOGIC ; + clken : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/megacells/sub32.inc b/megacells/sub32.inc new file mode 100755 index 000000000..3c64e21c5 --- /dev/null +++ b/megacells/sub32.inc @@ -0,0 +1,33 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION sub32 +( + dataa[31..0], + datab[31..0], + clock, + aclr, + clken +) + +RETURNS ( + result[31..0] +); diff --git a/megacells/sub32.v b/megacells/sub32.v new file mode 100755 index 000000000..dd825d91a --- /dev/null +++ b/megacells/sub32.v @@ -0,0 +1,675 @@ +// megafunction wizard: %LPM_ADD_SUB%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_add_sub + +// ============================================================ +// File Name: sub32.v +// Megafunction Name(s): +// lpm_add_sub +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result +//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END + +//synthesis_resources = lut 32 +module sub32_add_sub_cqa + ( + aclr, + clken, + clock, + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clken; + input clock; + input [31:0] dataa; + input [31:0] datab; + output [31:0] result; + + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [0:0] wire_add_sub_cella_7cout; + wire [0:0] wire_add_sub_cella_8cout; + wire [0:0] wire_add_sub_cella_9cout; + wire [0:0] wire_add_sub_cella_10cout; + wire [0:0] wire_add_sub_cella_11cout; + wire [0:0] wire_add_sub_cella_12cout; + wire [0:0] wire_add_sub_cella_13cout; + wire [0:0] wire_add_sub_cella_14cout; + wire [0:0] wire_add_sub_cella_15cout; + wire [0:0] wire_add_sub_cella_16cout; + wire [0:0] wire_add_sub_cella_17cout; + wire [0:0] wire_add_sub_cella_18cout; + wire [0:0] wire_add_sub_cella_19cout; + wire [0:0] wire_add_sub_cella_20cout; + wire [0:0] wire_add_sub_cella_21cout; + wire [0:0] wire_add_sub_cella_22cout; + wire [0:0] wire_add_sub_cella_23cout; + wire [0:0] wire_add_sub_cella_24cout; + wire [0:0] wire_add_sub_cella_25cout; + wire [0:0] wire_add_sub_cella_26cout; + wire [0:0] wire_add_sub_cella_27cout; + wire [0:0] wire_add_sub_cella_28cout; + wire [0:0] wire_add_sub_cella_29cout; + wire [0:0] wire_add_sub_cella_30cout; + wire [31:0] wire_add_sub_cella_dataa; + wire [31:0] wire_add_sub_cella_datab; + wire [31:0] wire_add_sub_cella_regout; + + stratix_lcell add_sub_cella_0 + ( + .aclr(aclr), + .cin(1'b1), + .clk(clock), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0]), + .ena(clken), + .regout(wire_add_sub_cella_regout[0:0])); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "69b2", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_1 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_0cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1]), + .ena(clken), + .regout(wire_add_sub_cella_regout[1:1])); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "69b2", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_2 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_1cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2]), + .ena(clken), + .regout(wire_add_sub_cella_regout[2:2])); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "69b2", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_3 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_2cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3]), + .ena(clken), + .regout(wire_add_sub_cella_regout[3:3])); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "69b2", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_4 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_3cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4]), + .ena(clken), + .regout(wire_add_sub_cella_regout[4:4])); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "69b2", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_5 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_4cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5]), + .ena(clken), + .regout(wire_add_sub_cella_regout[5:5])); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "69b2", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_6 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_5cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6]), + .ena(clken), + .regout(wire_add_sub_cella_regout[6:6])); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "69b2", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_7 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_6cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_7cout[0:0]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7]), + .ena(clken), + .regout(wire_add_sub_cella_regout[7:7])); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "69b2", + add_sub_cella_7.operation_mode = "arithmetic", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_8 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_7cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_8cout[0:0]), + .dataa(wire_add_sub_cella_dataa[8:8]), + .datab(wire_add_sub_cella_datab[8:8]), + .ena(clken), + .regout(wire_add_sub_cella_regout[8:8])); + defparam + add_sub_cella_8.cin_used = "true", + add_sub_cella_8.lut_mask = "69b2", + add_sub_cella_8.operation_mode = "arithmetic", + add_sub_cella_8.sum_lutc_input = "cin", + add_sub_cella_8.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_9 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_8cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_9cout[0:0]), + .dataa(wire_add_sub_cella_dataa[9:9]), + .datab(wire_add_sub_cella_datab[9:9]), + .ena(clken), + .regout(wire_add_sub_cella_regout[9:9])); + defparam + add_sub_cella_9.cin_used = "true", + add_sub_cella_9.lut_mask = "69b2", + add_sub_cella_9.operation_mode = "arithmetic", + add_sub_cella_9.sum_lutc_input = "cin", + add_sub_cella_9.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_10 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_9cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_10cout[0:0]), + .dataa(wire_add_sub_cella_dataa[10:10]), + .datab(wire_add_sub_cella_datab[10:10]), + .ena(clken), + .regout(wire_add_sub_cella_regout[10:10])); + defparam + add_sub_cella_10.cin_used = "true", + add_sub_cella_10.lut_mask = "69b2", + add_sub_cella_10.operation_mode = "arithmetic", + add_sub_cella_10.sum_lutc_input = "cin", + add_sub_cella_10.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_11 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_10cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_11cout[0:0]), + .dataa(wire_add_sub_cella_dataa[11:11]), + .datab(wire_add_sub_cella_datab[11:11]), + .ena(clken), + .regout(wire_add_sub_cella_regout[11:11])); + defparam + add_sub_cella_11.cin_used = "true", + add_sub_cella_11.lut_mask = "69b2", + add_sub_cella_11.operation_mode = "arithmetic", + add_sub_cella_11.sum_lutc_input = "cin", + add_sub_cella_11.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_12 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_11cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_12cout[0:0]), + .dataa(wire_add_sub_cella_dataa[12:12]), + .datab(wire_add_sub_cella_datab[12:12]), + .ena(clken), + .regout(wire_add_sub_cella_regout[12:12])); + defparam + add_sub_cella_12.cin_used = "true", + add_sub_cella_12.lut_mask = "69b2", + add_sub_cella_12.operation_mode = "arithmetic", + add_sub_cella_12.sum_lutc_input = "cin", + add_sub_cella_12.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_13 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_12cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_13cout[0:0]), + .dataa(wire_add_sub_cella_dataa[13:13]), + .datab(wire_add_sub_cella_datab[13:13]), + .ena(clken), + .regout(wire_add_sub_cella_regout[13:13])); + defparam + add_sub_cella_13.cin_used = "true", + add_sub_cella_13.lut_mask = "69b2", + add_sub_cella_13.operation_mode = "arithmetic", + add_sub_cella_13.sum_lutc_input = "cin", + add_sub_cella_13.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_14 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_13cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_14cout[0:0]), + .dataa(wire_add_sub_cella_dataa[14:14]), + .datab(wire_add_sub_cella_datab[14:14]), + .ena(clken), + .regout(wire_add_sub_cella_regout[14:14])); + defparam + add_sub_cella_14.cin_used = "true", + add_sub_cella_14.lut_mask = "69b2", + add_sub_cella_14.operation_mode = "arithmetic", + add_sub_cella_14.sum_lutc_input = "cin", + add_sub_cella_14.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_15 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_14cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_15cout[0:0]), + .dataa(wire_add_sub_cella_dataa[15:15]), + .datab(wire_add_sub_cella_datab[15:15]), + .ena(clken), + .regout(wire_add_sub_cella_regout[15:15])); + defparam + add_sub_cella_15.cin_used = "true", + add_sub_cella_15.lut_mask = "69b2", + add_sub_cella_15.operation_mode = "arithmetic", + add_sub_cella_15.sum_lutc_input = "cin", + add_sub_cella_15.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_16 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_15cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_16cout[0:0]), + .dataa(wire_add_sub_cella_dataa[16:16]), + .datab(wire_add_sub_cella_datab[16:16]), + .ena(clken), + .regout(wire_add_sub_cella_regout[16:16])); + defparam + add_sub_cella_16.cin_used = "true", + add_sub_cella_16.lut_mask = "69b2", + add_sub_cella_16.operation_mode = "arithmetic", + add_sub_cella_16.sum_lutc_input = "cin", + add_sub_cella_16.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_17 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_16cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_17cout[0:0]), + .dataa(wire_add_sub_cella_dataa[17:17]), + .datab(wire_add_sub_cella_datab[17:17]), + .ena(clken), + .regout(wire_add_sub_cella_regout[17:17])); + defparam + add_sub_cella_17.cin_used = "true", + add_sub_cella_17.lut_mask = "69b2", + add_sub_cella_17.operation_mode = "arithmetic", + add_sub_cella_17.sum_lutc_input = "cin", + add_sub_cella_17.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_18 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_17cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_18cout[0:0]), + .dataa(wire_add_sub_cella_dataa[18:18]), + .datab(wire_add_sub_cella_datab[18:18]), + .ena(clken), + .regout(wire_add_sub_cella_regout[18:18])); + defparam + add_sub_cella_18.cin_used = "true", + add_sub_cella_18.lut_mask = "69b2", + add_sub_cella_18.operation_mode = "arithmetic", + add_sub_cella_18.sum_lutc_input = "cin", + add_sub_cella_18.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_19 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_18cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_19cout[0:0]), + .dataa(wire_add_sub_cella_dataa[19:19]), + .datab(wire_add_sub_cella_datab[19:19]), + .ena(clken), + .regout(wire_add_sub_cella_regout[19:19])); + defparam + add_sub_cella_19.cin_used = "true", + add_sub_cella_19.lut_mask = "69b2", + add_sub_cella_19.operation_mode = "arithmetic", + add_sub_cella_19.sum_lutc_input = "cin", + add_sub_cella_19.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_20 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_19cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_20cout[0:0]), + .dataa(wire_add_sub_cella_dataa[20:20]), + .datab(wire_add_sub_cella_datab[20:20]), + .ena(clken), + .regout(wire_add_sub_cella_regout[20:20])); + defparam + add_sub_cella_20.cin_used = "true", + add_sub_cella_20.lut_mask = "69b2", + add_sub_cella_20.operation_mode = "arithmetic", + add_sub_cella_20.sum_lutc_input = "cin", + add_sub_cella_20.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_21 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_20cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_21cout[0:0]), + .dataa(wire_add_sub_cella_dataa[21:21]), + .datab(wire_add_sub_cella_datab[21:21]), + .ena(clken), + .regout(wire_add_sub_cella_regout[21:21])); + defparam + add_sub_cella_21.cin_used = "true", + add_sub_cella_21.lut_mask = "69b2", + add_sub_cella_21.operation_mode = "arithmetic", + add_sub_cella_21.sum_lutc_input = "cin", + add_sub_cella_21.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_22 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_21cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_22cout[0:0]), + .dataa(wire_add_sub_cella_dataa[22:22]), + .datab(wire_add_sub_cella_datab[22:22]), + .ena(clken), + .regout(wire_add_sub_cella_regout[22:22])); + defparam + add_sub_cella_22.cin_used = "true", + add_sub_cella_22.lut_mask = "69b2", + add_sub_cella_22.operation_mode = "arithmetic", + add_sub_cella_22.sum_lutc_input = "cin", + add_sub_cella_22.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_23 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_22cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_23cout[0:0]), + .dataa(wire_add_sub_cella_dataa[23:23]), + .datab(wire_add_sub_cella_datab[23:23]), + .ena(clken), + .regout(wire_add_sub_cella_regout[23:23])); + defparam + add_sub_cella_23.cin_used = "true", + add_sub_cella_23.lut_mask = "69b2", + add_sub_cella_23.operation_mode = "arithmetic", + add_sub_cella_23.sum_lutc_input = "cin", + add_sub_cella_23.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_24 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_23cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_24cout[0:0]), + .dataa(wire_add_sub_cella_dataa[24:24]), + .datab(wire_add_sub_cella_datab[24:24]), + .ena(clken), + .regout(wire_add_sub_cella_regout[24:24])); + defparam + add_sub_cella_24.cin_used = "true", + add_sub_cella_24.lut_mask = "69b2", + add_sub_cella_24.operation_mode = "arithmetic", + add_sub_cella_24.sum_lutc_input = "cin", + add_sub_cella_24.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_25 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_24cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_25cout[0:0]), + .dataa(wire_add_sub_cella_dataa[25:25]), + .datab(wire_add_sub_cella_datab[25:25]), + .ena(clken), + .regout(wire_add_sub_cella_regout[25:25])); + defparam + add_sub_cella_25.cin_used = "true", + add_sub_cella_25.lut_mask = "69b2", + add_sub_cella_25.operation_mode = "arithmetic", + add_sub_cella_25.sum_lutc_input = "cin", + add_sub_cella_25.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_26 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_25cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_26cout[0:0]), + .dataa(wire_add_sub_cella_dataa[26:26]), + .datab(wire_add_sub_cella_datab[26:26]), + .ena(clken), + .regout(wire_add_sub_cella_regout[26:26])); + defparam + add_sub_cella_26.cin_used = "true", + add_sub_cella_26.lut_mask = "69b2", + add_sub_cella_26.operation_mode = "arithmetic", + add_sub_cella_26.sum_lutc_input = "cin", + add_sub_cella_26.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_27 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_26cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_27cout[0:0]), + .dataa(wire_add_sub_cella_dataa[27:27]), + .datab(wire_add_sub_cella_datab[27:27]), + .ena(clken), + .regout(wire_add_sub_cella_regout[27:27])); + defparam + add_sub_cella_27.cin_used = "true", + add_sub_cella_27.lut_mask = "69b2", + add_sub_cella_27.operation_mode = "arithmetic", + add_sub_cella_27.sum_lutc_input = "cin", + add_sub_cella_27.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_28 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_27cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_28cout[0:0]), + .dataa(wire_add_sub_cella_dataa[28:28]), + .datab(wire_add_sub_cella_datab[28:28]), + .ena(clken), + .regout(wire_add_sub_cella_regout[28:28])); + defparam + add_sub_cella_28.cin_used = "true", + add_sub_cella_28.lut_mask = "69b2", + add_sub_cella_28.operation_mode = "arithmetic", + add_sub_cella_28.sum_lutc_input = "cin", + add_sub_cella_28.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_29 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_28cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_29cout[0:0]), + .dataa(wire_add_sub_cella_dataa[29:29]), + .datab(wire_add_sub_cella_datab[29:29]), + .ena(clken), + .regout(wire_add_sub_cella_regout[29:29])); + defparam + add_sub_cella_29.cin_used = "true", + add_sub_cella_29.lut_mask = "69b2", + add_sub_cella_29.operation_mode = "arithmetic", + add_sub_cella_29.sum_lutc_input = "cin", + add_sub_cella_29.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_30 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_29cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_30cout[0:0]), + .dataa(wire_add_sub_cella_dataa[30:30]), + .datab(wire_add_sub_cella_datab[30:30]), + .ena(clken), + .regout(wire_add_sub_cella_regout[30:30])); + defparam + add_sub_cella_30.cin_used = "true", + add_sub_cella_30.lut_mask = "69b2", + add_sub_cella_30.operation_mode = "arithmetic", + add_sub_cella_30.sum_lutc_input = "cin", + add_sub_cella_30.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_31 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_30cout[0:0]), + .clk(clock), + .dataa(wire_add_sub_cella_dataa[31:31]), + .datab(wire_add_sub_cella_datab[31:31]), + .ena(clken), + .regout(wire_add_sub_cella_regout[31:31])); + defparam + add_sub_cella_31.cin_used = "true", + add_sub_cella_31.lut_mask = "6969", + add_sub_cella_31.operation_mode = "normal", + add_sub_cella_31.sum_lutc_input = "cin", + add_sub_cella_31.lpm_type = "stratix_lcell"; + assign + wire_add_sub_cella_dataa = dataa, + wire_add_sub_cella_datab = datab; + assign + result = wire_add_sub_cella_regout; +endmodule //sub32_add_sub_cqa +//VALID FILE + + +module sub32 ( + dataa, + datab, + clock, + aclr, + clken, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] dataa; + input [31:0] datab; + input clock; + input aclr; + input clken; + output [31:0] result; + + wire [31:0] sub_wire0; + wire [31:0] result = sub_wire0[31:0]; + + sub32_add_sub_cqa sub32_add_sub_cqa_component ( + .dataa (dataa), + .datab (datab), + .clken (clken), + .aclr (aclr), + .clock (clock), + .result (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "32" +// Retrieval info: PRIVATE: Function NUMERIC "1" +// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantA NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Overflow NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "1" +// Retrieval info: PRIVATE: aclr NUMERIC "1" +// Retrieval info: PRIVATE: clken NUMERIC "1" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] +// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0] +// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0] +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken +// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 +// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0 +// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/sub32_bb.v b/megacells/sub32_bb.v new file mode 100755 index 000000000..488ab51cf --- /dev/null +++ b/megacells/sub32_bb.v @@ -0,0 +1,37 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module sub32 ( + dataa, + datab, + clock, + aclr, + clken, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] dataa; + input [31:0] datab; + input clock; + input aclr; + input clken; + output [31:0] result; + +endmodule + diff --git a/megacells/sub32_inst.v b/megacells/sub32_inst.v new file mode 100755 index 000000000..1916fc524 --- /dev/null +++ b/megacells/sub32_inst.v @@ -0,0 +1,8 @@ +sub32 sub32_inst ( + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .clock ( clock_sig ), + .aclr ( aclr_sig ), + .clken ( clken_sig ), + .result ( result_sig ) + ); diff --git a/models/bustri.v b/models/bustri.v new file mode 100644 index 000000000..6e5a0f74c --- /dev/null +++ b/models/bustri.v @@ -0,0 +1,17 @@ + +// Model for tristate bus on altera +// FIXME do we really need to use a megacell for this? + +module bustri (data, + enabledt, + tridata); + + input [15:0] data; + input enabledt; + inout [15:0] tridata; + + assign tridata = enabledt ? data :16'bz; + +endmodule // bustri + + diff --git a/models/fifo.v b/models/fifo.v new file mode 100644 index 000000000..a04e7da6c --- /dev/null +++ b/models/fifo.v @@ -0,0 +1,81 @@ +// Model of FIFO in Altera + +module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q, + rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); + + parameter width = 16; + parameter depth = 1024; + parameter addr_bits = 10; + + //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req + + input [width-1:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [width-1:0] q; + output rdfull; + output rdempty; + output reg [addr_bits-1:0] rdusedw; + output wrfull; + output wrempty; + output reg [addr_bits-1:0] wrusedw; + + reg [width-1:0] mem [0:depth-1]; + reg [addr_bits-1:0] rdptr; + reg [addr_bits-1:0] wrptr; + +`ifdef rd_req + reg [width-1:0] q; +`else + wire [width-1:0] q; +`endif + + integer i; + + always @( aclr) + begin + wrptr <= #1 0; + rdptr <= #1 0; + for(i=0;i DAC) + always @(posedge usbclk, posedge reset) + begin + if(reset) + begin + fifo_in <= #1 0; + write_count <= #1 0; + end + else + if(WR & ~write_count[8]) + begin + case(write_count[0]) + 1'b0 : fifo_in[31:16] <= #1 usbdata_in; // I + 1'b1 : fifo_in[15:0] <= #1 usbdata_in; // Q + endcase + write_count <= #1 write_count + 9'd1; + end + else + write_count <= #1 WR ? write_count : 9'b0; + end + + always @(posedge usbclk) + if(reset) + commit <= #1 1'b0; + else + if(write_count[0] && ~write_count[8] && WR) + commit <= #1 1'b1; + else + commit <= #1 1'b0; + + assign rdreq = txstrobe & !tx_empty; + assign txdata = tx_empty ? 32'b0 : txd; + + always @(posedge txclk) + if(reset) + tx_underrun <= 1'b0; + else if(txstrobe & tx_empty) + tx_underrun <= 1'b1; + else if(clear_status) + tx_underrun <= 1'b0; + + fifo_1c_2k txfifo (.data ( fifo_in ), + .wrreq ( commit ), + .wrclk ( usbclk ), + + .q ( txd ), + .rdreq ( rdreq), + .rdclk ( txclk ), + + .aclr ( reset ), + + .rdempty ( tx_empty ), + .rdusedw ( ), + .wrfull ( tx_full ), + .wrusedw ( txfifolevel ) + ); + + assign have_space = (txfifolevel <= (2048-128)); + + ////////////////////////////// + // Receive FIFO (ADC --> USB) + + always @(posedge rxclk) + if(reset) + rx_overrun <= 1'b0; + else if(rxstrobe & rx_full) + rx_overrun <= 1'b1; + else if(clear_status) + rx_overrun <= 1'b0; + + always @(select_out, fifo_out) + case(select_out) + 0 : usbdata_out = fifo_out[31:16]; // I + 1 : usbdata_out = fifo_out[15:0]; // Q + endcase + +/* + always @(posedge usbclk, posedge reset) + if(reset) + usbdata_out <= #1 16'b0; + else + if(select_out) + usbdata_out = fifo_out[31:16]; + else + usbdata_out = fifo_out[15:0]; + */ + + always @(negedge usbclk, posedge reset) + if(reset) + select_out <= #1 1'b0; + else if(~RD) + select_out <= #1 1'b0; + else + select_out <= #1 ~select_out; + + fifo_1c_2k rxfifo (.data ( rxdata ), // counter ), + .wrreq (rxstrobe & ~rx_full ), + .wrclk ( rxclk ), + + .q ( fifo_out ), + .rdreq ( select_out ),// & RD ), // FIXME + .rdclk ( usbclk ), + + .aclr ( reset ), + + .rdempty ( rx_empty ), + .rdusedw ( rxfifolevel ), + .wrfull ( rx_full ), + .wrusedw ( ) + ); + + assign have_pkt_rdy = (rxfifolevel >= 128); + + // Debugging Aids + assign debugbus[0] = tx_underrun; + assign debugbus[1] = rx_overrun; + assign debugbus[2] = tx_empty; + assign debugbus[3] = tx_full; + assign debugbus[4] = rx_empty; + assign debugbus[5] = rx_full; + assign debugbus[6] = txstrobe; + assign debugbus[7] = rxstrobe; + assign debugbus[8] = select_out; + assign debugbus[9] = rxstrobe & ~rx_full; + assign debugbus[10] = have_space; + assign debugbus[11] = have_pkt_rdy; + +endmodule // bus_interface + diff --git a/sdr_lib/cic_decim.v b/sdr_lib/cic_decim.v new file mode 100755 index 000000000..45b863f16 --- /dev/null +++ b/sdr_lib/cic_decim.v @@ -0,0 +1,106 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + +module cic_decim + ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out); + parameter bw = 16; + parameter N = 4; + parameter log2_of_max_rate = 8; + parameter maxbitgain = N * log2_of_max_rate; + + input clock; + input reset; + input enable; + input [7:0] rate; + input strobe_in,strobe_out; + input [bw-1:0] signal_in; + output [bw-1:0] signal_out; + reg [bw-1:0] signal_out; + + wire [bw+maxbitgain-1:0] signal_in_ext; + reg [bw+maxbitgain-1:0] integrator [0:N-1]; + reg [bw+maxbitgain-1:0] differentiator [0:N-1]; + reg [bw+maxbitgain-1:0] pipeline [0:N-1]; + reg [bw+maxbitgain-1:0] sampler; + + integer i; + + sign_extend #(bw,bw+maxbitgain) + ext_input (.in(signal_in),.out(signal_in_ext)); + + always @(posedge clock) + if(reset) + for(i=0;i=0;i=i-1) + bin_val[i] = bin_val[i+1] ^ gray_val[i]; + end +endmodule // gray2bin diff --git a/sdr_lib/gen_cordic_consts.py b/sdr_lib/gen_cordic_consts.py new file mode 100755 index 000000000..ab66cfe01 --- /dev/null +++ b/sdr_lib/gen_cordic_consts.py @@ -0,0 +1,10 @@ +#!/usr/bin/env python + +import math + +zwidth = 16 + +for i in range(17): + c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth) + print "`define c%02d %d'd%d" % (i, zwidth, round (c)) + diff --git a/sdr_lib/gen_sync.v b/sdr_lib/gen_sync.v new file mode 100644 index 000000000..d72b39d56 --- /dev/null +++ b/sdr_lib/gen_sync.v @@ -0,0 +1,43 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +module gen_sync + ( input clock, + input reset, + input enable, + input [7:0] rate, + output wire sync ); + +// parameter width = 8; + + reg [7:0] counter; + assign sync = |(((rate+1)>>1)& counter); + + always @(posedge clock) + if(reset || ~enable) + counter <= #1 0; + else if(counter == rate) + counter <= #1 0; + else + counter <= #1 counter + 8'd1; + +endmodule // gen_sync + diff --git a/sdr_lib/hb/acc.v b/sdr_lib/hb/acc.v new file mode 100644 index 000000000..195d5ea94 --- /dev/null +++ b/sdr_lib/hb/acc.v @@ -0,0 +1,22 @@ + + +module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, + input signed [30:0] addend, output reg signed [33:0] sum ); + + always @(posedge clock) + if(reset) + sum <= #1 34'd0; + //else if(clear & enable_in) + // sum <= #1 addend; + //else if(clear) + // sum <= #1 34'd0; + else if(clear) + sum <= #1 addend; + else if(enable_in) + sum <= #1 sum + addend; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // acc + diff --git a/sdr_lib/hb/coeff_ram.v b/sdr_lib/hb/coeff_ram.v new file mode 100644 index 000000000..65460822f --- /dev/null +++ b/sdr_lib/hb/coeff_ram.v @@ -0,0 +1,26 @@ + + +module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data); + + always @(posedge clock) + case (rd_addr) + 4'd0 : rd_data <= #1 -16'd16; + 4'd1 : rd_data <= #1 16'd74; + 4'd2 : rd_data <= #1 -16'd254; + 4'd3 : rd_data <= #1 16'd669; + 4'd4 : rd_data <= #1 -16'd1468; + 4'd5 : rd_data <= #1 16'd2950; + 4'd6 : rd_data <= #1 -16'd6158; + 4'd7 : rd_data <= #1 16'd20585; + 4'd8 : rd_data <= #1 16'd20585; + 4'd9 : rd_data <= #1 -16'd6158; + 4'd10 : rd_data <= #1 16'd2950; + 4'd11 : rd_data <= #1 -16'd1468; + 4'd12 : rd_data <= #1 16'd669; + 4'd13 : rd_data <= #1 -16'd254; + 4'd14 : rd_data <= #1 16'd74; + 4'd15 : rd_data <= #1 -16'd16; + default : rd_data <= #1 16'd0; + endcase // case(rd_addr) + +endmodule // ram diff --git a/sdr_lib/hb/coeff_rom.v b/sdr_lib/hb/coeff_rom.v new file mode 100644 index 000000000..c287eaaad --- /dev/null +++ b/sdr_lib/hb/coeff_rom.v @@ -0,0 +1,19 @@ + + +module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); + + always @(posedge clock) + case (addr) + 3'd0 : data <= #1 -16'd16; + 3'd1 : data <= #1 16'd74; + 3'd2 : data <= #1 -16'd254; + 3'd3 : data <= #1 16'd669; + 3'd4 : data <= #1 -16'd1468; + 3'd5 : data <= #1 16'd2950; + 3'd6 : data <= #1 -16'd6158; + 3'd7 : data <= #1 16'd20585; + endcase // case(addr) + +endmodule // coeff_rom + + diff --git a/sdr_lib/hb/halfband_decim.v b/sdr_lib/hb/halfband_decim.v new file mode 100644 index 000000000..2a05ce52c --- /dev/null +++ b/sdr_lib/hb/halfband_decim.v @@ -0,0 +1,163 @@ +/* -*- verilog -*- + * + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2005 Matt Ettus + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * This implements a 31-tap halfband filter that decimates by two. + * The coefficients are symmetric, and with the exception of the middle tap, + * every other coefficient is zero. The middle section of taps looks like this: + * + * ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ... + * | + * middle tap -------+ + * + * See coeff_rom.v for the full set. The taps are scaled relative to 32768, + * thus the middle tap equals 1.0. Not counting the middle tap, there are 8 + * non-zero taps on each side, and they are symmetric. A naive implementation + * requires a mulitply for each non-zero tap. Because of symmetry, we can + * replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output + * sample, we need to perform 8 multiplications. Since the middle tap is 1.0, + * we just add the corresponding delay line value. + * + * About timing: We implement this with a single multiplier, so it takes + * 8 cycles to compute a single output. However, since we're decimating by two + * we can accept a new input value every 4 cycles. strobe_in is asserted when + * there's a new input sample available. Depending on the overall decimation + * rate, strobe_in may be asserted less frequently than once every 4 clocks. + * On the output side, we assert strobe_out when output contains a new sample. + * + * Implementation: Every time strobe_in is asserted we store the new data into + * the delay line. We split the delay line into two components, one for the + * even samples, and one for the odd samples. ram16_odd is the delay line for + * the odd samples. This ram is written on each odd assertion of strobe_in, and + * is read on each clock when we're computing the dot product. ram16_even is + * similar, although because it holds the even samples we must be able to read + * two samples from different addresses at the same time, while writing the incoming + * even samples. Thus it's "triple-ported". + */ + +module halfband_decim + (input clock, input reset, input enable, input strobe_in, output wire strobe_out, + input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl); + + reg [3:0] rd_addr1; + reg [3:0] rd_addr2; + reg [3:0] phase; + reg [3:0] base_addr; + + wire signed [15:0] mac_out,middle_data, sum, coeff; + wire signed [30:0] product; + wire signed [33:0] sum_even; + wire clear; + reg store_odd; + + always @(posedge clock) + if(reset) + store_odd <= #1 1'b0; + else + if(strobe_in) + store_odd <= #1 ~store_odd; + + wire start = strobe_in & store_odd; + always @(posedge clock) + if(reset) + base_addr <= #1 4'd0; + else if(start) + base_addr <= #1 base_addr + 4'd1; + + always @(posedge clock) + if(reset) + phase <= #1 4'd8; + else if (start) + phase <= #1 4'd0; + else if(phase != 4'd8) + phase <= #1 phase + 4'd1; + + reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD; + always @(posedge clock) + begin + start_d1 <= #1 start; + start_d2 <= #1 start_d1; + start_d3 <= #1 start_d2; + start_d4 <= #1 start_d3; + start_d5 <= #1 start_d4; + start_d6 <= #1 start_d5; + start_d7 <= #1 start_d6; + start_d8 <= #1 start_d7; + start_d9 <= #1 start_d8; + start_dA <= #1 start_d9; + start_dB <= #1 start_dA; + start_dC <= #1 start_dB; + start_dD <= #1 start_dC; + end // always @ (posedge clock) + + reg mult_en, mult_en_pre; + always @(posedge clock) + begin + mult_en_pre <= #1 phase!=8; + mult_en <= #1 mult_en_pre; + end + + assign clear = start_d4; // was dC + wire latch_result = start_d4; // was dC + assign strobe_out = start_d5; // was dD + wire acc_en; + + always @* + case(phase[2:0]) + 3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end + 3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end + 3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end + 3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end + 3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end + 3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end + 3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end + 3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end + default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end + endcase // case(phase) + + coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff)); + + ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), + .wr_addr(base_addr),.wr_data(data_in), + .rd_addr1(rd_addr1),.rd_addr2(rd_addr2), + .sum(sum)); + + ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items + .wr_addr(base_addr),.wr_data(data_in), + //.rd_addr(base_addr+4'd7),.rd_data(middle_data)); + .rd_addr(base_addr+4'd6),.rd_data(middle_data)); + + mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en)); + + acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(), + .clear(clear),.addend(product),.sum(sum_even)); + + wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!! + + always @(posedge clock) + if(reset) + data_out <= #1 16'd0; + else if(latch_result) + data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]); + + assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase}; + +endmodule // halfband_decim diff --git a/sdr_lib/hb/halfband_interp.v b/sdr_lib/hb/halfband_interp.v new file mode 100644 index 000000000..cdb11c1f6 --- /dev/null +++ b/sdr_lib/hb/halfband_interp.v @@ -0,0 +1,121 @@ + + +module halfband_interp + (input clock, input reset, input enable, + input strobe_in, input strobe_out, + input [15:0] signal_in_i, input [15:0] signal_in_q, + output reg [15:0] signal_out_i, output reg [15:0] signal_out_q, + output wire [12:0] debug); + + wire [15:0] coeff_ram_out; + wire [15:0] data_ram_out_i; + wire [15:0] data_ram_out_q; + + wire [3:0] data_rd_addr; + reg [3:0] data_wr_addr; + reg [2:0] coeff_rd_addr; + + wire filt_done; + + wire [15:0] mac_out_i; + wire [15:0] mac_out_q; + reg [15:0] delayed_middle_i, delayed_middle_q; + wire [7:0] shift = 8'd9; + + reg stb_out_happened; + + wire [15:0] data_ram_out_i_b; + + always @(posedge clock) + if(strobe_in) + stb_out_happened <= #1 1'b0; + else if(strobe_out) + stb_out_happened <= #1 1'b1; + +assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr}; + + wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i; + wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q; + +/* always @(posedge clock) + if(reset) + begin + signal_out_i <= #1 16'd0; + signal_out_q <= #1 16'd0; + end + else if(strobe_in) + begin + signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff + signal_out_q <= #1 delayed_middle_q; + end + //else if(filt_done&stb_out_happened) + else if(stb_out_happened) + begin + signal_out_i <= #1 mac_out_i; + signal_out_q <= #1 mac_out_q; + end +*/ + + always @(posedge clock) + if(reset) + coeff_rd_addr <= #1 3'd0; + else if(coeff_rd_addr != 3'd0) + coeff_rd_addr <= #1 coeff_rd_addr + 3'd1; + else if(strobe_in) + coeff_rd_addr <= #1 3'd1; + + reg filt_done_d1; + always@(posedge clock) + filt_done_d1 <= #1 filt_done; + + always @(posedge clock) + if(reset) + data_wr_addr <= #1 4'd0; + //else if(strobe_in) + else if(filt_done & ~filt_done_d1) + data_wr_addr <= #1 data_wr_addr + 4'd1; + + always @(posedge clock) + if(coeff_rd_addr == 3'd7) + begin + delayed_middle_i <= #1 data_ram_out_i_b; + // delayed_middle_q <= #1 data_ram_out_q_b; + end + +// always @(posedge clock) +// if(reset) +// data_rd_addr <= #1 4'd0; +// else if(strobe_in) +// data_rd_addr <= #1 data_wr_addr + 4'd1; +// else if(!filt_done) +// data_rd_addr <= #1 data_rd_addr + 4'd1; +// else +// data_rd_addr <= #1 data_wr_addr; + + wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr}; + wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr}; +// always @(posedge clock) +// if(reset) +// filt_done <= #1 1'b1; +// else if(strobe_in) + // filt_done <= #1 1'b0; +// else if(coeff_rd_addr == 4'd0) +// filt_done <= #1 1'b1; + + assign filt_done = (coeff_rd_addr == 3'd0); + + coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) ); + + ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i), + .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i)); + + ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q), + .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q)); + + mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), + .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) ); + + mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), + .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) ); + +endmodule // halfband_interp diff --git a/sdr_lib/hb/hbd_tb/HBD b/sdr_lib/hb/hbd_tb/HBD new file mode 100644 index 000000000..574fbba91 --- /dev/null +++ b/sdr_lib/hb/hbd_tb/HBD @@ -0,0 +1,80 @@ +*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +test_hbd.clock +test_hbd.reset +@420 +test_hbd.halfband_decim.middle_data[15:0] +@22 +test_hbd.halfband_decim.sum_even[33:0] +test_hbd.halfband_decim.base_addr[3:0] +@420 +test_hbd.i_in[15:0] +@24 +test_hbd.halfband_decim.phase[3:0] +test_hbd.halfband_decim.ram16_even.rd_addr1[3:0] +test_hbd.halfband_decim.ram16_even.rd_addr2[3:0] +test_hbd.halfband_decim.ram16_even.wr_addr[3:0] +test_hbd.halfband_decim.ram16_even.wr_data[15:0] +@28 +test_hbd.halfband_decim.ram16_even.write +@420 +test_hbd.halfband_decim.sum[15:0] +test_hbd.halfband_decim.product[30:0] +test_hbd.halfband_decim.dout[33:0] +test_hbd.halfband_decim.sum_even[33:0] +@22 +test_hbd.halfband_decim.acc.addend[30:0] +@28 +test_hbd.halfband_decim.acc.reset +@420 +test_hbd.halfband_decim.acc.sum[33:0] +test_hbd.halfband_decim.mult.x[15:0] +test_hbd.halfband_decim.mult.y[15:0] +@28 +test_hbd.halfband_decim.acc.clear +test_hbd.strobe_in +test_hbd.strobe_out +test_hbd.halfband_decim.acc_en +@420 +test_hbd.i_out[15:0] +@28 +test_hbd.halfband_decim.mult_en +test_hbd.halfband_decim.latch_result +@420 +test_hbd.halfband_decim.sum[15:0] +test_hbd.halfband_decim.sum_even[33:0] +test_hbd.halfband_decim.dout[33:0] +test_hbd.halfband_decim.data_out[15:0] +@22 +test_hbd.halfband_decim.data_out[15:0] +@28 +test_hbd.halfband_decim.dout[33:0] +@29 +test_hbd.halfband_decim.acc_en +@22 +test_hbd.halfband_decim.base_addr[3:0] +@28 +test_hbd.halfband_decim.clear +test_hbd.halfband_decim.latch_result +test_hbd.halfband_decim.mult_en +test_hbd.halfband_decim.mult_en_pre +@22 +test_hbd.halfband_decim.phase[3:0] +@28 +test_hbd.halfband_decim.start +test_hbd.halfband_decim.start_d1 +test_hbd.halfband_decim.start_d2 +test_hbd.halfband_decim.start_d3 +test_hbd.halfband_decim.start_d4 +test_hbd.halfband_decim.start_d5 +test_hbd.halfband_decim.start_d6 +test_hbd.halfband_decim.start_d7 +test_hbd.halfband_decim.start_d8 +test_hbd.halfband_decim.start_d9 +test_hbd.halfband_decim.start_dA +test_hbd.halfband_decim.start_dB +test_hbd.halfband_decim.start_dC +test_hbd.halfband_decim.start_dD +test_hbd.halfband_decim.store_odd +test_hbd.halfband_decim.strobe_in +test_hbd.halfband_decim.strobe_out diff --git a/sdr_lib/hb/hbd_tb/really_golden b/sdr_lib/hb/hbd_tb/really_golden new file mode 100644 index 000000000..2d24a9e14 --- /dev/null +++ b/sdr_lib/hb/hbd_tb/really_golden @@ -0,0 +1,142 @@ +VCD info: dumpfile test_hbd.vcd opened for output. + x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8192 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 +- 4 + 18 +- 63 + 167 +- 367 + 737 +- 1539 + 5146 + 5146 +- 1539 + 737 +- 367 + 167 +- 63 + 18 +- 4 + 0 + 0 + 0 + 0 + 0 +- 4 + 14 +- 49 + 118 +- 249 + 488 + 7141 +12287 +17433 +15894 +16631 +16264 +16432 +16368 +16387 +16383 +16383 +16383 +16383 +16383 +16387 +16368 +16432 +16264 +16631 +15894 + 9241 + 4095 +- 1051 + 488 +- 249 + 118 +- 49 + 14 +- 4 + 0 + 0 + 0 + 0 + 0 +- 4 + 14 +- 49 + 118 +- 249 + 488 +- 1051 +12287 +17433 +15894 +16631 +16264 +16432 +16368 +16387 +16383 +16383 +16383 +16383 +16383 +16387 +16368 +16432 +16264 +16631 +15894 +17433 + 4095 +- 1051 + 488 +- 249 + 118 +- 49 + 14 +- 4 + 0 + 0 + 0 + 0 diff --git a/sdr_lib/hb/hbd_tb/regression b/sdr_lib/hb/hbd_tb/regression new file mode 100644 index 000000000..fc279c2f2 --- /dev/null +++ b/sdr_lib/hb/hbd_tb/regression @@ -0,0 +1,95 @@ +echo "Baseline 1000" +iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden +diff golden really_golden + +echo +echo "Test 100" +iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 50" +iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 40" +iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 30" +iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 25" +iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 20" +iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 19" +iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 18" +iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 17" +iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 16" +iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 15" +iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 14" +iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 13" +iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 12" +iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 11" +iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 10" +iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 9" +iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 8" +iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 7" +iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 6" +iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 5" +iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 4" +iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 3" +iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden diff --git a/sdr_lib/hb/hbd_tb/run_hbd b/sdr_lib/hb/hbd_tb/run_hbd new file mode 100755 index 000000000..b8aec7574 --- /dev/null +++ b/sdr_lib/hb/hbd_tb/run_hbd @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog -y .. -o test_hbd test_hbd.v +./test_hbd diff --git a/sdr_lib/hb/hbd_tb/test_hbd.v b/sdr_lib/hb/hbd_tb/test_hbd.v new file mode 100644 index 000000000..01ab5e7e0 --- /dev/null +++ b/sdr_lib/hb/hbd_tb/test_hbd.v @@ -0,0 +1,75 @@ + + +module test_hbd(); + + reg clock; + initial clock = 1'b0; + always #5 clock <= ~clock; + + reg reset; + initial reset = 1'b1; + initial #1000 reset = 1'b0; + + initial $dumpfile("test_hbd.vcd"); + initial $dumpvars(0,test_hbd); + + reg [15:0] i_in, q_in; + wire [15:0] i_out, q_out; + + reg strobe_in; + wire strobe_out; + reg coeff_write; + reg [15:0] coeff_data; + reg [4:0] coeff_addr; + + halfband_decim halfband_decim + ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), + .data_in(i_in),.data_out(i_out) ); + + always @(posedge strobe_out) + if(i_out[15]) + $display("-%d",65536-i_out); + else + $display("%d",i_out); + + initial + begin + strobe_in = 1'b0; + @(negedge reset); + @(posedge clock); + while(1) + begin + strobe_in <= #1 1'b1; + @(posedge clock); + strobe_in <= #1 1'b0; + repeat (`RATE) + @(posedge clock); + end + end + + initial #10000000 $finish; // Just in case... + + initial + begin + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (41) @(posedge strobe_in); + i_in <= #1 16'd16384; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + repeat (7) @(posedge clock); + $finish; + end // initial begin +endmodule // test_hb diff --git a/sdr_lib/hb/mac.v b/sdr_lib/hb/mac.v new file mode 100644 index 000000000..5a270bc73 --- /dev/null +++ b/sdr_lib/hb/mac.v @@ -0,0 +1,58 @@ + + +module mac (input clock, input reset, input enable, input clear, + input signed [15:0] x, input signed [15:0] y, + input [7:0] shift, output [15:0] z ); + + reg signed [30:0] product; + reg signed [39:0] z_int; + reg signed [15:0] z_shift; + + reg enable_d1; + always @(posedge clock) + enable_d1 <= #1 enable; + + always @(posedge clock) + if(reset | clear) + z_int <= #1 40'd0; + else if(enable_d1) + z_int <= #1 z_int + {{9{product[30]}},product}; + + always @(posedge clock) + product <= #1 x*y; + + always @* // FIXME full case? parallel case? + case(shift) + //8'd0 : z_shift <= z_int[39:24]; + //8'd1 : z_shift <= z_int[38:23]; + //8'd2 : z_shift <= z_int[37:22]; + //8'd3 : z_shift <= z_int[36:21]; + //8'd4 : z_shift <= z_int[35:20]; + //8'd5 : z_shift <= z_int[34:19]; + 8'd6 : z_shift <= z_int[33:18]; + 8'd7 : z_shift <= z_int[32:17]; + 8'd8 : z_shift <= z_int[31:16]; + 8'd9 : z_shift <= z_int[30:15]; + 8'd10 : z_shift <= z_int[29:14]; + 8'd11 : z_shift <= z_int[28:13]; + //8'd12 : z_shift <= z_int[27:12]; + //8'd13 : z_shift <= z_int[26:11]; + //8'd14 : z_shift <= z_int[25:10]; + //8'd15 : z_shift <= z_int[24:9]; + //8'd16 : z_shift <= z_int[23:8]; + //8'd17 : z_shift <= z_int[22:7]; + //8'd18 : z_shift <= z_int[21:6]; + //8'd19 : z_shift <= z_int[20:5]; + //8'd20 : z_shift <= z_int[19:4]; + //8'd21 : z_shift <= z_int[18:3]; + //8'd22 : z_shift <= z_int[17:2]; + //8'd23 : z_shift <= z_int[16:1]; + //8'd24 : z_shift <= z_int[15:0]; + default : z_shift <= z_int[15:0]; + endcase // case(shift) + + // FIXME do we need to saturate? + //assign z = z_shift; + assign z = z_int[15:0]; + +endmodule // mac diff --git a/sdr_lib/hb/mult.v b/sdr_lib/hb/mult.v new file mode 100644 index 000000000..a8d4cb1b7 --- /dev/null +++ b/sdr_lib/hb/mult.v @@ -0,0 +1,16 @@ + + +module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, + input enable_in, output reg enable_out ); + + always @(posedge clock) + if(enable_in) + product <= #1 x*y; + else + product <= #1 31'd0; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // mult + diff --git a/sdr_lib/hb/ram16_2port.v b/sdr_lib/hb/ram16_2port.v new file mode 100644 index 000000000..e1761a926 --- /dev/null +++ b/sdr_lib/hb/ram16_2port.v @@ -0,0 +1,22 @@ + + +module ram16_2port (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr1, output reg [15:0] rd_data1, + input [3:0] rd_addr2, output reg [15:0] rd_data2); + + reg [15:0] ram_array [0:31]; + + always @(posedge clock) + rd_data1 <= #1 ram_array[rd_addr1]; + + always @(posedge clock) + rd_data2 <= #1 ram_array[rd_addr2]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram16_2port + + diff --git a/sdr_lib/hb/ram16_2sum.v b/sdr_lib/hb/ram16_2sum.v new file mode 100644 index 000000000..559b06fd5 --- /dev/null +++ b/sdr_lib/hb/ram16_2sum.v @@ -0,0 +1,27 @@ + + +module ram16_2sum (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr1, input [3:0] rd_addr2, + output reg [15:0] sum); + + reg signed [15:0] ram_array [0:15]; + reg signed [15:0] a,b; + wire signed [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + always @(posedge clock) + begin + a <= #1 ram_array[rd_addr1]; + b <= #1 ram_array[rd_addr2]; + end + + assign sum_int = {a[15],a} + {b[15],b}; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + +endmodule // ram16_2sum diff --git a/sdr_lib/hb/ram32_2sum.v b/sdr_lib/hb/ram32_2sum.v new file mode 100644 index 000000000..d1f55b7d0 --- /dev/null +++ b/sdr_lib/hb/ram32_2sum.v @@ -0,0 +1,22 @@ + + +module ram32_2sum (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr1, input [4:0] rd_addr2, + output reg [15:0] sum); + + reg [15:0] ram_array [0:31]; + wire [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + + +endmodule // ram32_2sum + diff --git a/sdr_lib/io_pins.v b/sdr_lib/io_pins.v new file mode 100644 index 000000000..da20b3b03 --- /dev/null +++ b/sdr_lib/io_pins.v @@ -0,0 +1,52 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2005,2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +`include "../../firmware/include/fpga_regs_common.v" +`include "../../firmware/include/fpga_regs_standard.v" + +module io_pins + ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3, + input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3, + input clock, input rx_reset, input tx_reset, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe); + + reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe; + + bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0)); + bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1)); + bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe),.reg_val(reg_2)); + bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe),.reg_val(reg_3)); + + // Upper 16 bits are mask for lower 16 + always @(posedge clock) + if(serial_strobe) + case(serial_addr) + `FR_OE_0 : io_0_oe + <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_1 : io_1_oe + <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_2 : io_2_oe + <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_3 : io_3_oe + <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + endcase // case(serial_addr) + +endmodule // io_pins diff --git a/sdr_lib/master_control.v b/sdr_lib/master_control.v new file mode 100644 index 000000000..d42817c72 --- /dev/null +++ b/sdr_lib/master_control.v @@ -0,0 +1,155 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2005 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// Clock, enable, and reset controls for whole system + +module master_control + ( input master_clk, input usbclk, + input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe, + output tx_bus_reset, output rx_bus_reset, + output wire tx_dsp_reset, output wire rx_dsp_reset, + output wire enable_tx, output wire enable_rx, + output wire [7:0] interp_rate, output wire [7:0] decim_rate, + output tx_sample_strobe, output strobe_interp, + output rx_sample_strobe, output strobe_decim, + input tx_empty, + input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3, + output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3 + ); + + // FIXME need a separate reset for all control settings + // Master Controls assignments + wire [7:0] master_controls; + setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls)); + assign enable_tx = master_controls[0]; + assign enable_rx = master_controls[1]; + assign tx_dsp_reset = master_controls[2]; + assign rx_dsp_reset = master_controls[3]; + // Unused - 4-7 + + // Strobe Generators + setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate)); + setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate)); + + strobe_gen da_strobe_gen + ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx), + .rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) ); + + strobe_gen tx_strobe_gen + ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx), + .rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) ); + + assign rx_sample_strobe = 1'b1; + + strobe_gen decim_strobe_gen + ( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx), + .rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) ); + + // Reset syncs for bus (usbclk) side + // The RX bus side reset isn't used, the TX bus side one may not be needed + reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2; + + always @(posedge usbclk) + begin + tx_reset_bus_sync1 <= #1 tx_dsp_reset; + rx_reset_bus_sync1 <= #1 rx_dsp_reset; + tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1; + rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1; + end + + assign tx_bus_reset = tx_reset_bus_sync2; + assign rx_bus_reset = rx_reset_bus_sync2; + + wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk; + wire txaclk,txbclk,rxaclk,rxbclk; + wire [3:0] debug_en, txcvr_ctrl; + + wire [31:0] txcvr_rxlines, txcvr_txlines; + + setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk)); + setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk)); + setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk)); + setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk)); + + setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en)); + + clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0])); + clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0])); + clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0])); + clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0])); + + reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg; + // Upper 16 bits are mask for lower 16 + always @(posedge master_clk) + if(serial_strobe) + case(serial_addr) + `FR_IO_0 : io_0_reg + <= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_IO_1 : io_1_reg + <= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_IO_2 : io_2_reg + <= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_IO_3 : io_3_reg + <= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + endcase // case(serial_addr) + + wire transmit_now = !tx_empty & enable_tx; + wire atr_ctl; + wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3; + + setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0)); + setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0)); + setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0)); + + setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1)); + setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1)); + setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1)); + + setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2)); + setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2)); + setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2)); + + setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3)); + setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3)); + setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3)); + + //setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl)); + assign atr_ctl = 1'b1; + + wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0; + wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg); + + wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1; + wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg); + + wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2; + wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg); + + wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3; + wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg); + + assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0; + assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1; + assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2; + assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3; + + +endmodule // master_control diff --git a/sdr_lib/master_control_multi.v b/sdr_lib/master_control_multi.v new file mode 100644 index 000000000..af1e0b1f1 --- /dev/null +++ b/sdr_lib/master_control_multi.v @@ -0,0 +1,73 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// +`include "usrp_multi.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" +// Clock, enable, and reset controls for whole system +// Modified version to enable multi_usrp synchronisation + +module master_control_multi + ( input master_clk, input usbclk, + input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe, + input wire rx_slave_sync, + output tx_bus_reset, output rx_bus_reset, + output wire tx_dsp_reset, output wire rx_dsp_reset, + output wire enable_tx, output wire enable_rx, + output wire sync_rx, + output wire [7:0] interp_rate, output wire [7:0] decim_rate, + output tx_sample_strobe, output strobe_interp, + output rx_sample_strobe, output strobe_decim, + input tx_empty, + input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3, + output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3 + ); + + wire [15:0] reg_1_std; + + master_control master_control_standard + ( .master_clk(master_clk),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + .debug_0(debug_0),.debug_1(debug_1), + .debug_2(debug_2),.debug_3(debug_3), + .reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) ); + + // FIXME need a separate reset for all control settings + // Master/slave Controls assignments + wire [7:0] rx_master_slave_controls; + setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls)); + + assign sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync); + //sync if we are told by master_control or if we get a hardware slave sync + //TODO There can be a one sample difference between master and slave sync. + // Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger + // Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind) + //TODO make output pin not hardwired +assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]}; + + +endmodule // master_control diff --git a/sdr_lib/phase_acc.v b/sdr_lib/phase_acc.v new file mode 100755 index 000000000..d00716fd0 --- /dev/null +++ b/sdr_lib/phase_acc.v @@ -0,0 +1,52 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + + +// Basic Phase accumulator for DDS + + +module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase); + parameter FREQADDR = 0; + parameter PHASEADDR = 0; + parameter resolution = 32; + + input clk, reset, enable, strobe; + input [6:0] serial_addr; + input [31:0] serial_data; + input serial_strobe; + + output reg [resolution-1:0] phase; + wire [resolution-1:0] freq; + + setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq)); + + always @(posedge clk) + if(reset) + phase <= #1 32'b0; + else if(serial_strobe & (serial_addr == PHASEADDR)) + phase <= #1 serial_data; + else if(enable & strobe) + phase <= #1 phase + freq; + +endmodule // phase_acc + + diff --git a/sdr_lib/ram.v b/sdr_lib/ram.v new file mode 100644 index 000000000..fb64cdeae --- /dev/null +++ b/sdr_lib/ram.v @@ -0,0 +1,16 @@ + + +module ram (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:31]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram diff --git a/sdr_lib/ram16.v b/sdr_lib/ram16.v new file mode 100644 index 000000000..0c93da2be --- /dev/null +++ b/sdr_lib/ram16.v @@ -0,0 +1,17 @@ + + +module ram16 (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:15]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram16 + diff --git a/sdr_lib/ram32.v b/sdr_lib/ram32.v new file mode 100644 index 000000000..064e2735a --- /dev/null +++ b/sdr_lib/ram32.v @@ -0,0 +1,17 @@ + + +module ram32 (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:31]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram32 + diff --git a/sdr_lib/ram64.v b/sdr_lib/ram64.v new file mode 100644 index 000000000..084545808 --- /dev/null +++ b/sdr_lib/ram64.v @@ -0,0 +1,16 @@ + + +module ram64 (input clock, input write, + input [5:0] wr_addr, input [15:0] wr_data, + input [5:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:63]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram64 diff --git a/sdr_lib/rssi.v b/sdr_lib/rssi.v new file mode 100644 index 000000000..e45e2148c --- /dev/null +++ b/sdr_lib/rssi.v @@ -0,0 +1,30 @@ + + +module rssi (input clock, input reset, input enable, + input [11:0] adc, output [15:0] rssi, output [15:0] over_count); + + wire over_hi = (adc == 12'h7FF); + wire over_lo = (adc == 12'h800); + wire over = over_hi | over_lo; + + reg [25:0] over_count_int; + always @(posedge clock) + if(reset | ~enable) + over_count_int <= #1 26'd0; + else + over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10]; + + assign over_count = over_count_int[25:10]; + + wire [11:0] abs_adc = adc[11] ? ~adc : adc; + + reg [25:0] rssi_int; + always @(posedge clock) + if(reset | ~enable) + rssi_int <= #1 26'd0; + else + rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10]; + + assign rssi = rssi_int[25:10]; + +endmodule // rssi diff --git a/sdr_lib/rx_buffer.v b/sdr_lib/rx_buffer.v new file mode 100644 index 000000000..70c800e3d --- /dev/null +++ b/sdr_lib/rx_buffer.v @@ -0,0 +1,182 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// Interface to Cypress FX2 bus +// A packet is 512 Bytes. Each fifo line is 2 bytes +// Fifo has 1024 or 2048 lines + +`include "../../firmware/include/fpga_regs_common.v" +`include "../../firmware/include/fpga_regs_standard.v" + +module rx_buffer + ( input usbclk, + input bus_reset, // Not used in RX + input reset, // DSP side reset (used here), do not reset registers + input reset_regs, //Only reset registers + output [15:0] usbdata, + input RD, + output wire have_pkt_rdy, + output reg rx_overrun, + input wire [3:0] channels, + input wire [15:0] ch_0, + input wire [15:0] ch_1, + input wire [15:0] ch_2, + input wire [15:0] ch_3, + input wire [15:0] ch_4, + input wire [15:0] ch_5, + input wire [15:0] ch_6, + input wire [15:0] ch_7, + input rxclk, + input rxstrobe, + input clear_status, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, + output [15:0] debugbus + ); + + wire [15:0] fifodata, fifodata_8; + reg [15:0] fifodata_16; + + wire [11:0] rxfifolevel; + wire rx_empty, rx_full; + + wire bypass_hb, want_q; + wire [4:0] bitwidth; + wire [3:0] bitshift; + + setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({bypass_hb,want_q,bitwidth,bitshift})); + + // Receive FIFO (ADC --> USB) + + // 257 Bug Fix + reg [8:0] read_count; + always @(negedge usbclk) + if(bus_reset) + read_count <= #1 9'd0; + else if(RD & ~read_count[8]) + read_count <= #1 read_count + 9'd1; + else + read_count <= #1 RD ? read_count : 9'b0; + + // Detect overrun + always @(posedge rxclk) + if(reset) + rx_overrun <= 1'b0; + else if(rxstrobe & (store_next != 0)) + rx_overrun <= 1'b1; + else if(clear_status) + rx_overrun <= 1'b0; + + reg [3:0] store_next; + always @(posedge rxclk) + if(reset) + store_next <= #1 4'd0; + else if(rxstrobe & (store_next == 0)) + store_next <= #1 4'd1; + else if(~rx_full & (store_next == channels)) + store_next <= #1 4'd0; + else if(~rx_full & (bitwidth == 5'd8) & (store_next == (channels>>1))) + store_next <= #1 4'd0; + else if(~rx_full & (store_next != 0)) + store_next <= #1 store_next + 4'd1; + + assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16; + + assign fifodata_8 = {round_8(top),round_8(bottom)}; + reg [15:0] top,bottom; + + function [7:0] round_8; + input [15:0] in_val; + + round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]); + endfunction // round_8 + + always @* + case(store_next) + 4'd1 : begin + bottom = ch_0; + top = ch_1; + end + 4'd2 : begin + bottom = ch_2; + top = ch_3; + end + 4'd3 : begin + bottom = ch_4; + top = ch_5; + end + 4'd4 : begin + bottom = ch_6; + top = ch_7; + end + default : begin + top = 16'hFFFF; + bottom = 16'hFFFF; + end + endcase // case(store_next) + + always @* + case(store_next) + 4'd1 : fifodata_16 = ch_0; + 4'd2 : fifodata_16 = ch_1; + 4'd3 : fifodata_16 = ch_2; + 4'd4 : fifodata_16 = ch_3; + 4'd5 : fifodata_16 = ch_4; + 4'd6 : fifodata_16 = ch_5; + 4'd7 : fifodata_16 = ch_6; + 4'd8 : fifodata_16 = ch_7; + default : fifodata_16 = 16'hFFFF; + endcase // case(store_next) + + fifo_4k rxfifo + ( .data ( fifodata ), + .wrreq (~rx_full & (store_next != 0)), + .wrclk ( rxclk ), + + .q ( usbdata ), + .rdreq ( RD & ~read_count[8] ), + .rdclk ( ~usbclk ), + + .aclr ( reset ), // This one is asynchronous, so we can use either reset + + .rdempty ( rx_empty ), + .rdusedw ( rxfifolevel ), + .wrfull ( rx_full ), + .wrusedw ( ) + ); + + assign have_pkt_rdy = (rxfifolevel >= 256); + + // Debugging Aids + assign debugbus[0] = RD; + assign debugbus[1] = rx_overrun; + assign debugbus[2] = read_count[8]; + assign debugbus[3] = rx_full; + assign debugbus[4] = rxstrobe; + assign debugbus[5] = usbclk; + assign debugbus[6] = have_pkt_rdy; + assign debugbus[10:7] = store_next; + //assign debugbus[15:11] = rxfifolevel[4:0]; + assign debugbus[15:11] = bitwidth; + +endmodule // rx_buffer + diff --git a/sdr_lib/rx_chain.v b/sdr_lib/rx_chain.v new file mode 100644 index 000000000..4031e6bfb --- /dev/null +++ b/sdr_lib/rx_chain.v @@ -0,0 +1,105 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// Following defines conditionally include RX path circuitry + +`include "usrp_std.vh" +module rx_chain + (input clock, + input reset, + input enable, + input wire [7:0] decim_rate, + input sample_strobe, + input decimator_strobe, + output wire hb_strobe, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out, + output wire [15:0] q_out, + output wire [15:0] debugdata,output wire [15:0] debugctrl + ); + + parameter FREQADDR = 0; + parameter PHASEADDR = 0; + + wire [31:0] phase; + wire [15:0] bb_i, bb_q; + wire [15:0] hb_in_i, hb_in_q; + + assign debugdata = hb_in_i; + +`ifdef RX_NCO_ON + phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc + (.clk(clock),.reset(reset),.enable(enable), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .strobe(sample_strobe),.phase(phase) ); + + cordic rx_cordic + ( .clock(clock),.reset(reset),.enable(enable), + .xi(i_in),.yi(q_in),.zi(phase[31:16]), + .xo(bb_i),.yo(bb_q),.zo() ); +`else + assign bb_i = i_in; + assign bb_q = q_in; + assign sample_strobe = 1; +`endif // !`ifdef RX_NCO_ON + +`ifdef RX_CIC_ON + cic_decim cic_decim_i_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_i),.signal_out(hb_in_i) ); +`else + assign hb_in_i = bb_i; + assign decimator_strobe = sample_strobe; +`endif + +`ifdef RX_HB_ON + halfband_decim hbd_i_0 + ( .clock(clock),.reset(reset),.enable(enable), + .strobe_in(decimator_strobe),.strobe_out(hb_strobe), + .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) ); +`else + assign i_out = hb_in_i; + assign hb_strobe = decimator_strobe; +`endif + +`ifdef RX_CIC_ON + cic_decim cic_decim_q_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_q),.signal_out(hb_in_q) ); +`else + assign hb_in_q = bb_q; +`endif + +`ifdef RX_HB_ON + halfband_decim hbd_q_0 + ( .clock(clock),.reset(reset),.enable(enable), + .strobe_in(decimator_strobe),.strobe_out(), + .data_in(hb_in_q),.data_out(q_out) ); +`else + assign q_out = hb_in_q; +`endif + + +endmodule // rx_chain diff --git a/sdr_lib/rx_chain_dual.v b/sdr_lib/rx_chain_dual.v new file mode 100644 index 000000000..698859468 --- /dev/null +++ b/sdr_lib/rx_chain_dual.v @@ -0,0 +1,103 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +module rx_chain_dual + (input clock, + input clock_2x, + input reset, + input enable, + input wire [7:0] decim_rate, + input sample_strobe, + input decimator_strobe, + input wire [31:0] freq0, + input wire [15:0] i_in0, + input wire [15:0] q_in0, + output wire [15:0] i_out0, + output wire [15:0] q_out0, + input wire [31:0] freq1, + input wire [15:0] i_in1, + input wire [15:0] q_in1, + output wire [15:0] i_out1, + output wire [15:0] q_out1 + ); + + wire [15:0] phase; + wire [15:0] bb_i, bb_q; + wire [15:0] i_in, q_in; + + wire [31:0] phase0; + wire [31:0] phase1; + reg [15:0] bb_i0, bb_q0; + reg [15:0] bb_i1, bb_q1; + + // We want to time-share the CORDIC by double-clocking it + + phase_acc rx_phase_acc_0 + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq0),.phase(phase0) ); + + phase_acc rx_phase_acc_1 + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq1),.phase(phase1) ); + + assign phase = clock ? phase0[31:16] : phase1[31:16]; + assign i_in = clock ? i_in0 : i_in1; + assign q_in = clock ? q_in0 : q_in1; + +// This appears reversed because of the number of CORDIC stages + always @(posedge clock_2x) + if(clock) + begin + bb_i1 <= #1 bb_i; + bb_q1 <= #1 bb_q; + end + else + begin + bb_i0 <= #1 bb_i; + bb_q0 <= #1 bb_q; + end + + cordic rx_cordic + ( .clock(clock_2x),.reset(reset),.enable(enable), + .xi(i_in),.yi(q_in),.zi(phase), + .xo(bb_i),.yo(bb_q),.zo() ); + + cic_decim cic_decim_i_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_i0),.signal_out(i_out0) ); + + cic_decim cic_decim_q_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_q0),.signal_out(q_out0) ); + + cic_decim cic_decim_i_1 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_i1),.signal_out(i_out1) ); + + cic_decim cic_decim_q_1 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_q1),.signal_out(q_out1) ); + +endmodule // rx_chain diff --git a/sdr_lib/rx_dcoffset.v b/sdr_lib/rx_dcoffset.v new file mode 100644 index 000000000..3be475ed6 --- /dev/null +++ b/sdr_lib/rx_dcoffset.v @@ -0,0 +1,22 @@ + + +module rx_dcoffset (input clock, input enable, input reset, + input signed [15:0] adc_in, output signed [15:0] adc_out, + input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe); + parameter MYADDR = 0; + + reg signed [31:0] integrator; + wire signed [15:0] scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]); + assign adc_out = adc_in - scaled_integrator; + + // FIXME do we need signed? + //FIXME What do we do when clipping? + always @(posedge clock) + if(reset) + integrator <= #1 32'd0; + else if(serial_strobe & (MYADDR == serial_addr)) + integrator <= #1 {serial_data[15:0],16'd0}; + else if(enable) + integrator <= #1 integrator + adc_out; + +endmodule // rx_dcoffset diff --git a/sdr_lib/serial_io.v b/sdr_lib/serial_io.v new file mode 100644 index 000000000..1fe43c959 --- /dev/null +++ b/sdr_lib/serial_io.v @@ -0,0 +1,118 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2004 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + + +// Serial Control Bus from Cypress chip + +module serial_io + ( input master_clk, + input serial_clock, + input serial_data_in, + input enable, + input reset, + inout wire serial_data_out, + output reg [6:0] serial_addr, + output reg [31:0] serial_data, + output wire serial_strobe, + input wire [31:0] readback_0, + input wire [31:0] readback_1, + input wire [31:0] readback_2, + input wire [31:0] readback_3, + input wire [31:0] readback_4, + input wire [31:0] readback_5, + input wire [31:0] readback_6, + input wire [31:0] readback_7 + ); + + reg is_read; + reg [7:0] ser_ctr; + reg write_done; + + assign serial_data_out = is_read ? serial_data[31] : 1'bz; + + always @(posedge serial_clock, posedge reset, negedge enable) + if(reset) + ser_ctr <= #1 8'd0; + else if(~enable) + ser_ctr <= #1 8'd0; + else if(ser_ctr == 39) + ser_ctr <= #1 8'd0; + else + ser_ctr <= #1 ser_ctr + 8'd1; + + always @(posedge serial_clock, posedge reset, negedge enable) + if(reset) + is_read <= #1 1'b0; + else if(~enable) + is_read <= #1 1'b0; + else if((ser_ctr == 7)&&(serial_addr[6]==1)) + is_read <= #1 1'b1; + + always @(posedge serial_clock, posedge reset) + if(reset) + begin + serial_addr <= #1 7'b0; + serial_data <= #1 32'b0; + write_done <= #1 1'b0; + end + else if(~enable) + begin + //serial_addr <= #1 7'b0; + //serial_data <= #1 32'b0; + write_done <= #1 1'b0; + end + else + begin + if(~is_read && (ser_ctr == 39)) + write_done <= #1 1'b1; + else + write_done <= #1 1'b0; + if(is_read & (ser_ctr==8)) + case (serial_addr) + 7'd1: serial_data <= #1 readback_0; + 7'd2: serial_data <= #1 readback_1; + 7'd3: serial_data <= #1 readback_2; + 7'd4: serial_data <= #1 readback_3; + 7'd5: serial_data <= #1 readback_4; + 7'd6: serial_data <= #1 readback_5; + 7'd7: serial_data <= #1 readback_6; + 7'd8: serial_data <= #1 readback_7; + default: serial_data <= #1 32'd0; + endcase // case(serial_addr) + else if(ser_ctr >= 8) + serial_data <= #1 {serial_data[30:0],serial_data_in}; + else if(ser_ctr < 8) + serial_addr <= #1 {serial_addr[5:0],serial_data_in}; + end // else: !if(~enable) + + reg enable_d1, enable_d2; + always @(posedge master_clk) + begin + enable_d1 <= #1 enable; + enable_d2 <= #1 enable_d1; + end + + assign serial_strobe = enable_d2 & ~enable_d1; + +endmodule // serial_io + + diff --git a/sdr_lib/setting_reg.v b/sdr_lib/setting_reg.v new file mode 100644 index 000000000..3d31a9efb --- /dev/null +++ b/sdr_lib/setting_reg.v @@ -0,0 +1,23 @@ + + +module setting_reg + ( input clock, input reset, input strobe, input wire [6:0] addr, + input wire [31:0] in, output reg [31:0] out, output reg changed); + parameter my_addr = 0; + + always @(posedge clock) + if(reset) + begin + out <= #1 32'd0; + changed <= #1 1'b0; + end + else + if(strobe & (my_addr==addr)) + begin + out <= #1 in; + changed <= #1 1'b1; + end + else + changed <= #1 1'b0; + +endmodule // setting_reg diff --git a/sdr_lib/setting_reg_masked.v b/sdr_lib/setting_reg_masked.v new file mode 100644 index 000000000..72f7e21eb --- /dev/null +++ b/sdr_lib/setting_reg_masked.v @@ -0,0 +1,26 @@ + + +module setting_reg_masked + ( input clock, input reset, input strobe, input wire [6:0] addr, + input wire [31:0] in, output reg [31:0] out, output reg changed); +/* upper 16 bits are mask, lower 16 bits are value + * Note that you get a 16 bit register, not a 32 bit one */ + + parameter my_addr = 0; + + always @(posedge clock) + if(reset) + begin + out <= #1 32'd0; + changed <= #1 1'b0; + end + else + if(strobe & (my_addr==addr)) + begin + out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] ); + changed <= #1 1'b1; + end + else + changed <= #1 1'b0; + +endmodule // setting_reg_masked diff --git a/sdr_lib/sign_extend.v b/sdr_lib/sign_extend.v new file mode 100644 index 000000000..2417909bd --- /dev/null +++ b/sdr_lib/sign_extend.v @@ -0,0 +1,35 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + +// Sign extension "macro" +// bits_out should be greater than bits_in + +module sign_extend (in,out); + parameter bits_in=0; // FIXME Quartus insists on a default + parameter bits_out=0; + + input [bits_in-1:0] in; + output [bits_out-1:0] out; + + assign out = {{(bits_out-bits_in){in[bits_in-1]}},in}; + +endmodule diff --git a/sdr_lib/strobe_gen.v b/sdr_lib/strobe_gen.v new file mode 100644 index 000000000..0511b6a1d --- /dev/null +++ b/sdr_lib/strobe_gen.v @@ -0,0 +1,44 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +module strobe_gen + ( input clock, + input reset, + input enable, + input [7:0] rate, + input strobe_in, + output wire strobe ); + +// parameter width = 8; + + reg [7:0] counter; + assign strobe = ~|counter && enable && strobe_in; + + always @(posedge clock) + if(reset | ~enable) + counter <= #1 8'd0; + else if(strobe_in) + if(counter == 0) + counter <= #1 rate; + else + counter <= #1 counter - 8'd1; + +endmodule // strobe_gen diff --git a/sdr_lib/tx_buffer.v b/sdr_lib/tx_buffer.v new file mode 100644 index 000000000..cae6607b3 --- /dev/null +++ b/sdr_lib/tx_buffer.v @@ -0,0 +1,138 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// Interface to Cypress FX2 bus +// A packet is 512 Bytes. Each fifo line is 2 bytes +// Fifo has 1024 or 2048 lines + +module tx_buffer + ( input usbclk, + input bus_reset, // Used here for the 257-Hack to fix the FX2 bug + input reset, // standard DSP-side reset + input [15:0] usbdata, + input wire WR, + output wire have_space, + output reg tx_underrun, + input wire [3:0] channels, + output reg [15:0] tx_i_0, + output reg [15:0] tx_q_0, + output reg [15:0] tx_i_1, + output reg [15:0] tx_q_1, + output reg [15:0] tx_i_2, + output reg [15:0] tx_q_2, + output reg [15:0] tx_i_3, + output reg [15:0] tx_q_3, + input txclk, + input txstrobe, + input clear_status, + output wire tx_empty, + output [11:0] debugbus + ); + + wire [11:0] txfifolevel; + reg [8:0] write_count; + wire tx_full; + wire [15:0] fifodata; + wire rdreq; + + reg [3:0] load_next; + + // DAC Side of FIFO + assign rdreq = ((load_next != channels) & !tx_empty); + + always @(posedge txclk) + if(reset) + begin + {tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3} + <= #1 128'h0; + load_next <= #1 4'd0; + end + else + if((load_next != channels) & !tx_empty) + begin + load_next <= #1 load_next + 4'd1; + case(load_next) + 4'd0 : tx_i_0 <= #1 fifodata; + 4'd1 : tx_q_0 <= #1 fifodata; + 4'd2 : tx_i_1 <= #1 fifodata; + 4'd3 : tx_q_1 <= #1 fifodata; + 4'd4 : tx_i_2 <= #1 fifodata; + 4'd5 : tx_q_2 <= #1 fifodata; + 4'd6 : tx_i_3 <= #1 fifodata; + 4'd7 : tx_q_3 <= #1 fifodata; + endcase // case(load_next) + end // if ((load_next != channels) & !tx_empty) + else if(txstrobe & (load_next == channels)) + begin + load_next <= #1 4'd0; + end + + // USB Side of FIFO + assign have_space = (txfifolevel <= (4095-256)); + + always @(posedge usbclk) + if(bus_reset) // Use bus reset because this is on usbclk + write_count <= #1 0; + else if(WR & ~write_count[8]) + write_count <= #1 write_count + 9'd1; + else + write_count <= #1 WR ? write_count : 9'b0; + + // Detect Underruns + always @(posedge txclk) + if(reset) + tx_underrun <= 1'b0; + else if(txstrobe & (load_next != channels)) + tx_underrun <= 1'b1; + else if(clear_status) + tx_underrun <= 1'b0; + + // FIFO + fifo_4k txfifo + ( .data ( usbdata ), + .wrreq ( WR & ~write_count[8] ), + .wrclk ( usbclk ), + + .q ( fifodata ), + .rdreq ( rdreq ), + .rdclk ( txclk ), + + .aclr ( reset ), // asynch, so we can use either + + .rdempty ( tx_empty ), + .rdusedw ( ), + .wrfull ( tx_full ), + .wrusedw ( txfifolevel ) + ); + + // Debugging Aids + assign debugbus[0] = WR; + assign debugbus[1] = have_space; + assign debugbus[2] = tx_empty; + assign debugbus[3] = tx_full; + assign debugbus[4] = tx_underrun; + assign debugbus[5] = write_count[8]; + assign debugbus[6] = txstrobe; + assign debugbus[7] = rdreq; + assign debugbus[11:8] = load_next; + +endmodule // tx_buffer + diff --git a/sdr_lib/tx_chain.v b/sdr_lib/tx_chain.v new file mode 100644 index 000000000..8f0a17a52 --- /dev/null +++ b/sdr_lib/tx_chain.v @@ -0,0 +1,65 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +module tx_chain + (input clock, + input reset, + input enable, + input wire [7:0] interp_rate, + input sample_strobe, + input interpolator_strobe, + input wire [31:0] freq, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out, + output wire [15:0] q_out + ); + + wire [15:0] bb_i, bb_q; + + cic_interp cic_interp_i + ( .clock(clock),.reset(reset),.enable(enable), + .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe), + .signal_in(i_in),.signal_out(bb_i) ); + + cic_interp cic_interp_q + ( .clock(clock),.reset(reset),.enable(enable), + .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe), + .signal_in(q_in),.signal_out(bb_q) ); + +`define NOCORDIC_TX +`ifdef NOCORDIC_TX + assign i_out = bb_i; + assign q_out = bb_q; +`else + wire [31:0] phase; + + phase_acc phase_acc_tx + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq),.phase(phase) ); + + cordic tx_cordic_0 + ( .clock(clock),.reset(reset),.enable(sample_strobe), + .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), + .xo(i_out),.yo(q_out),.zo() ); +`endif + +endmodule // tx_chain diff --git a/sdr_lib/tx_chain_hb.v b/sdr_lib/tx_chain_hb.v new file mode 100644 index 000000000..6cbe29c00 --- /dev/null +++ b/sdr_lib/tx_chain_hb.v @@ -0,0 +1,76 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +module tx_chain_hb + (input clock, + input reset, + input enable, + input wire [7:0] interp_rate, + input sample_strobe, + input interpolator_strobe, + input hb_strobe, + input wire [31:0] freq, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out, + output wire [15:0] q_out, +output wire [15:0] debug, output [15:0] hb_i_out + ); +assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe}; + + wire [15:0] bb_i, bb_q; + wire [15:0] hb_i_out, hb_q_out; + + halfband_interp hb + (.clock(clock),.reset(reset),.enable(enable), + .strobe_in(interpolator_strobe),.strobe_out(hb_strobe), + .signal_in_i(i_in),.signal_in_q(q_in), + .signal_out_i(hb_i_out),.signal_out_q(hb_q_out), + .debug(debug[12:0])); + + cic_interp cic_interp_i + ( .clock(clock),.reset(reset),.enable(enable), + .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), + .signal_in(hb_i_out),.signal_out(bb_i) ); + + cic_interp cic_interp_q + ( .clock(clock),.reset(reset),.enable(enable), + .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), + .signal_in(hb_q_out),.signal_out(bb_q) ); + +`define NOCORDIC_TX +`ifdef NOCORDIC_TX + assign i_out = bb_i; + assign q_out = bb_q; +`else + wire [31:0] phase; + + phase_acc phase_acc_tx + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq),.phase(phase) ); + + cordic tx_cordic_0 + ( .clock(clock),.reset(reset),.enable(sample_strobe), + .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), + .xo(i_out),.yo(q_out),.zo() ); +`endif + +endmodule // tx_chain diff --git a/tb/cbus_tb.v b/tb/cbus_tb.v new file mode 100644 index 000000000..53cc1272b --- /dev/null +++ b/tb/cbus_tb.v @@ -0,0 +1,71 @@ +module cbus_tb; + +`define ch1in_freq 0 +`define ch2in_freq 1 +`define ch3in_freq 2 +`define ch4in_freq 3 +`define ch1out_freq 4 +`define ch2out_freq 5 +`define ch3out_freq 6 +`define ch4out_freq 7 +`define rates 8 +`define misc 9 + + task send_config_word; + input [7:0] addr; + input [31:0] data; + integer i; + + begin + #10 serenable = 1; + for(i=7;i>=0;i=i-1) + begin + #10 serdata = addr[i]; + #10 serclk = 0; + #10 serclk = 1; + #10 serclk = 0; + end + for(i=31;i>=0;i=i-1) + begin + #10 serdata = data[i]; + #10 serclk = 0; + #10 serclk = 1; + #10 serclk = 0; + end + #10 serenable = 0; + // #10 serclk = 1; + // #10 serclk = 0; + end + endtask // send_config_word + + initial $dumpfile("cbus_tb.vcd"); + initial $dumpvars(0,cbus_tb); + + initial reset = 1; + initial #500 reset = 0; + + reg serclk, serdata, serenable, reset; + wire SDO; + + control_bus control_bus + ( .serial_clock(serclk), + .serial_data_in(serdata), + .enable(serenable), + .reset(reset), + .serial_data_out(SDO) ); + + + initial + begin + #1000 send_config_word(8'd1,32'hDEAD_BEEF); + #1000 send_config_word(8'd3,32'hDDEE_FF01); + #1000 send_config_word(8'd19,32'hFFFF_FFFF); + #1000 send_config_word(8'd23,32'h1234_FEDC); + #1000 send_config_word(8'h80,32'h0); + #1000 send_config_word(8'h81,32'h0); + #1000 send_config_word(8'h82,32'h0); + #1000 reset = 1; + #1 $finish; + end + +endmodule // cbus_tb diff --git a/tb/cordic_tb.v b/tb/cordic_tb.v new file mode 100644 index 000000000..ed85b37b1 --- /dev/null +++ b/tb/cordic_tb.v @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + + +module cordic_tb(); + + cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo ); + + reg reset; + reg clk; + reg enable; + reg [15:0] xi, yi, zi; + + initial reset = 1'b1; + initial #1000 reset = 1'b0; + + initial clk = 1'b0; + always #50 clk <= ~clk; + + initial enable = 1'b1; + + initial zi = 16'b0; + + always @(posedge clk) + zi <= #1 zi + 16'd0; + + wire [15:0] xo,yo,zo; + + initial $dumpfile("cordic.vcd"); + initial $dumpvars(0,cordic_tb); + initial + begin +`include "sine.txt" + end + + wire [15:0] xiu = {~xi[15],xi[14:0]}; + wire [15:0] yiu = {~yi[15],yi[14:0]}; + wire [15:0] xou = {~xo[15],xo[14:0]}; + wire [15:0] you = {~yo[15],yo[14:0]}; + initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you); + +endmodule // cordic_tb diff --git a/tb/decim_tb.v b/tb/decim_tb.v new file mode 100644 index 000000000..ecf20cf4a --- /dev/null +++ b/tb/decim_tb.v @@ -0,0 +1,108 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + +// testbench for fullchip + +module decim_tb(); + +`include "usrp_tasks.v" + + reg clk_120mhz; + reg usbclk; + reg reset; + + reg [11:0] adc1_data, adc2_data; + wire [13:0] dac1_data, dac2_data; + + wire [5:0] usbctl; + wire [5:0] usbrdy; + + wire [15:0] usbdata; + + reg WE, RD, OE; + + assign usbctl[0] = WE; + assign usbctl[1] = RD; + assign usbctl[2] = OE; + assign usbctl[5:3] = 0; + + reg tb_oe; + assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; + reg serload, serenable, serclk, serdata; + reg enable_tx, enable_rx; + reg [15:0] usbdatareg; + +/////////////////////////////////////////////// +// Simulation Control +initial +begin + $dumpfile("decim_tb.vcd"); + $dumpvars(0, fc_tb); +end + +initial #100000 $finish; + +/////////////////////////////////////////////// +// Monitors + +reg [7:0] counter_decim; +wire [7:0] decim_rate; +assign decim_rate = 32; +initial $monitor(dac1_data); + + always @(posedge clk_120mhz) + begin + if(reset | ~enable_tx) + counter_decim <= #1 0; + else if(counter_decim == 0) + counter_decim <= #1 decim_rate - 8'b1; + else + counter_decim <= #1 counter_decim - 8'b1; + end + +/////////////////////////////////////////////// +// Clock and reset + +initial clk_120mhz = 0; +initial usbclk = 0; +always #48 clk_120mhz = ~clk_120mhz; +always #120 usbclk = ~usbclk; + +initial reset = 1'b1; +initial #500 reset = 1'b0; + + +initial enable_tx = 1'b1; + + wire [31:0] decim_out, q_decim_out; + wire [31:0] decim_out; + wire [31:0] phase; + + cic_decim #(.bitwidth(32),.stages(4)) + decim_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), + .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); + + cic_decim #(.bitwidth(32),.stages(4)) + decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), + .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); + +endmodule diff --git a/tb/fullchip_tb.v b/tb/fullchip_tb.v new file mode 100755 index 000000000..c446ff0e1 --- /dev/null +++ b/tb/fullchip_tb.v @@ -0,0 +1,174 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + +// testbench for fullchip + +`timescale 1ns/1ns + +module fullchip_tb(); + +`include "usrp_tasks.v" + +fullchip fullchip + ( + .clk_120mhz(clk_120mhz), + .reset(reset), + .enable_rx(enable_rx), + .enable_tx(enable_tx), + .SLD(serload), + .SEN(serenable), + .clear_status(), + .SDI(serdata), + .SCLK(serclk), + + .adc1_data(adc1_data), + .adc2_data(adc2_data), + .adc3_data(adc1_data), + .adc4_data(adc2_data), + + .dac1_data(dac1_data), + .dac2_data(dac2_data), + .dac3_data(),.dac4_data(), + + .adclk0(adclk),.adclk1(), + + .adc_oeb(),.adc_otr(4'b0), + + .clk_out(clk_out), + + .misc_pins(), + + // USB interface + .usbclk(usbclk),.usbctl(usbctl), + .usbrdy(usbrdy),.usbdata(usbdata) + ); + + reg clk_120mhz; + reg usbclk; + reg reset; + + reg [11:0] adc1_data, adc2_data; + wire [13:0] dac1_data, dac2_data; + + wire [5:0] usbctl; + wire [5:0] usbrdy; + + wire [15:0] usbdata; + + reg WE, RD, OE; + + assign usbctl[0] = WE; + assign usbctl[1] = RD; + assign usbctl[2] = OE; + assign usbctl[5:3] = 0; + + wire have_packet_rdy = usbrdy[1]; + + reg tb_oe; + initial tb_oe=1'b1; + + assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; + reg serload, serenable, serclk, serdata; + reg enable_tx, enable_rx; + reg [15:0] usbdatareg; + +/////////////////////////////////////////////// +// Simulation Control +initial +begin + $dumpfile("fullchip_tb.vcd"); + $dumpvars(0, fullchip_tb); +end + +//initial #1000000 $finish; + +/////////////////////////////////////////////// +// Monitors + +//initial $monitor(dac1_data); + +/////////////////////////////////////////////// +// Clock and reset + +initial clk_120mhz = 0; +initial usbclk = 0; +always #24 clk_120mhz = ~clk_120mhz; +always #60 usbclk = ~usbclk; + +initial reset = 1'b1; +initial #500 reset = 1'b0; + +///////////////////////////////////////////////// +// Run AD input + +always @(posedge adclk) adc1_data <= #1 12'd1234; +always @(posedge adclk) adc2_data <= #1 12'd1234; + +///////////////////////////////////////////////// +// USB interface + + initial + begin + initialize_usb; + #30000 @(posedge usbclk); + burst_usb_write(257); + + #30000 burst_usb_read(256); + #10000 $finish; + +// repeat(30) +// begin +// write_from_usb; +// read_from_usb; +// end +end + +///////////////////////////////////////////////// +// TX and RX enable + +initial enable_tx = 1'b0; +initial #40000 enable_tx = 1'b1; +initial enable_rx = 1'b0; +initial #40000 enable_rx = 1'b1; + +////////////////////////////////////////////////// +// Set up control bus + +initial +begin + #1000 send_config_word(`ch1in_freq,32'h0); // 1 MHz on 60 MHz clock + send_config_word(`ch2in_freq,32'h0); + send_config_word(`ch3in_freq,32'h0); + send_config_word(`ch4in_freq,32'h0); + send_config_word(`ch1out_freq,32'h01234567); + send_config_word(`ch2out_freq,32'h0); + send_config_word(`ch3out_freq,32'h0); + send_config_word(`ch4out_freq,32'h0); + send_config_word(`misc,32'h0); + send_config_word(`rates,{8'd2,8'd12,8'h0f,8'h07}); + // adc, ext, interp, decim +end + +///////////////////////////////////////////////////////// + +endmodule + diff --git a/tb/interp_tb.v b/tb/interp_tb.v new file mode 100755 index 000000000..8a8e89ff9 --- /dev/null +++ b/tb/interp_tb.v @@ -0,0 +1,108 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + +// testbench for fullchip + +module interp_tb(); + +`include "usrp_tasks.v" + + reg clk_120mhz; + reg usbclk; + reg reset; + + reg [11:0] adc1_data, adc2_data; + wire [13:0] dac1_data, dac2_data; + + wire [5:0] usbctl; + wire [5:0] usbrdy; + + wire [15:0] usbdata; + + reg WE, RD, OE; + + assign usbctl[0] = WE; + assign usbctl[1] = RD; + assign usbctl[2] = OE; + assign usbctl[5:3] = 0; + + reg tb_oe; + assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; + reg serload, serenable, serclk, serdata; + reg enable_tx, enable_rx; + reg [15:0] usbdatareg; + +/////////////////////////////////////////////// +// Simulation Control +initial +begin + $dumpfile("interp_tb.vcd"); + $dumpvars(0, fc_tb); +end + +initial #100000 $finish; + +/////////////////////////////////////////////// +// Monitors + +reg [7:0] counter_interp; +wire [7:0] interp_rate; +assign interp_rate = 32; +initial $monitor(dac1_data); + + always @(posedge clk_120mhz) + begin + if(reset | ~enable_tx) + counter_interp <= #1 0; + else if(counter_interp == 0) + counter_interp <= #1 interp_rate - 8'b1; + else + counter_interp <= #1 counter_interp - 8'b1; + end + +/////////////////////////////////////////////// +// Clock and reset + +initial clk_120mhz = 0; +initial usbclk = 0; +always #48 clk_120mhz = ~clk_120mhz; +always #120 usbclk = ~usbclk; + +initial reset = 1'b1; +initial #500 reset = 1'b0; + + +initial enable_tx = 1'b1; + + wire [31:0] interp_out, q_interp_out; + wire [31:0] decim_out; + wire [31:0] phase; + + cic_interp #(.bitwidth(32),.stages(4)) + interp_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), + .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(interp_out)); + + cic_decim #(.bitwidth(32),.stages(4)) + decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), + .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); + +endmodule diff --git a/tb/justinterp_tb.v b/tb/justinterp_tb.v new file mode 100644 index 000000000..ffbd0f178 --- /dev/null +++ b/tb/justinterp_tb.v @@ -0,0 +1,73 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + +module cic_decim_tb; + +cic_decim #(.bitwidth(16),.stages(4)) + decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out); + + reg clock; + reg reset; + reg enable; + wire strobe; + reg [15:0] signal_in; + wire [15:0] signal_out; + + assign strobe_in = 1'b1; + reg strobe_out; + + always @(posedge clock) + while(1) + begin + @(posedge clock); + @(posedge clock); + @(posedge clock); + @(posedge clock); + strobe_out <= 1'b1; + @(posedge clock); + @(posedge clock); + @(posedge clock); + @(posedge clock); + strobe_out <= 1'b0; + end + + initial clock = 0; + always #50 clock = ~clock; + + initial reset = 1; + initial #1000 reset = 0; + + initial enable = 0; + initial #2000 enable = 1; + + initial signal_in = 16'h1; + initial #500000 signal_in = 16'h7fff; + initial #1000000 signal_in = 16'h8000; + initial #1500000 signal_in = 16'hffff; + + + initial $dumpfile("decim.vcd"); + initial $dumpvars(0,cic_decim_tb); + + initial #10000000 $finish; + +endmodule // cic_decim_tb diff --git a/tb/makesine.pl b/tb/makesine.pl new file mode 100755 index 000000000..9aebd6947 --- /dev/null +++ b/tb/makesine.pl @@ -0,0 +1,14 @@ +#!/usr/bin/perl + +$angle = 0; +$angle_inc = 2*3.14159/87.2; +$amp = 1; +$amp_rate = 1.0035; +for($i=0;$i<3500;$i++) + { + printf("@(posedge clk);xi<= #1 16'h%x;yi<= #1 16'h%x;\n",65535&int($amp*cos($angle)),65535&int($amp*sin($angle))); + $angle += $angle_inc; + $amp *= $amp_rate; + } + +printf("\$finish;\n"); diff --git a/tb/run_cordic b/tb/run_cordic new file mode 100755 index 000000000..68144fc83 --- /dev/null +++ b/tb/run_cordic @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog -y ../sdr_lib -o cordic_tb cordic_tb.v + diff --git a/tb/run_fullchip b/tb/run_fullchip new file mode 100755 index 000000000..eb81d7ff7 --- /dev/null +++ b/tb/run_fullchip @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog -y ../toplevel/fullchip -y ../sdr_lib -y ../models -y . -o fullchip_tb fullchip_tb.v + diff --git a/tb/usrp_tasks.v b/tb/usrp_tasks.v new file mode 100755 index 000000000..00f82b9e1 --- /dev/null +++ b/tb/usrp_tasks.v @@ -0,0 +1,145 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// Tasks + +///////////////////////////////////////////////// +// USB interface + +task initialize_usb; +begin + OE = 0;WE = 0;RD = 0; + usbdatareg <= 16'h0; +end +endtask + +task write_from_usb; +begin + tb_oe <= 1'b1; + @(posedge usbclk); + usbdatareg <= #1 $random % 65536; + WE <= #1 1'b1; + @(posedge usbclk) + WE <= #1 1'b0; + tb_oe <= #1 1'b0; +end +endtask + +task burst_usb_write; + input [31:0] repeat_count; + + begin + tb_oe <= 1'b1; + repeat(repeat_count) + begin + @(posedge usbclk) + usbdatareg <= #1 usbdatareg + 1; //$random % 65536; + WE <= #1 1'b1; + end + @(posedge usbclk) + WE <= #1 1'b0; + tb_oe <= 1'b0; + end +endtask // burst_usb_write + + +task read_from_usb; +begin + @(posedge usbclk); + RD <= #1 1'b1; + @(posedge usbclk); + RD <= #1 1'b0; + OE <= #1 1'b1; + @(posedge usbclk); + OE <= #1 1'b0; +end +endtask + +task burst_usb_read; + input [31:0] repeat_count; + begin + while (~have_packet_rdy) begin + @(posedge usbclk); + end + + @(posedge usbclk) + RD <= #1 1'b1; + repeat(repeat_count) + begin + @(posedge usbclk) + OE <= #1 1'b1; + end + RD <= #1 1'b0; + @(posedge usbclk); + OE <= #1 1'b0; + end +endtask // burst_usb_read + +///////////////////////////////////////////////// +// TX and RX enable + +////////////////////////////////////////////////// +// Set up control bus + +`define ch1in_freq 0 +`define ch2in_freq 1 +`define ch3in_freq 2 +`define ch4in_freq 3 +`define ch1out_freq 4 +`define ch2out_freq 5 +`define ch3out_freq 6 +`define ch4out_freq 7 +`define rates 8 +`define misc 9 + + task send_config_word; + input [7:0] addr; + input [31:0] data; + integer i; + + begin + #10 serenable = 1; + for(i=7;i>=0;i=i-1) + begin + #10 serdata = addr[i]; + #10 serclk = 0; + #10 serclk = 1; + #10 serclk = 0; + end + for(i=31;i>=0;i=i-1) + begin + #10 serdata = data[i]; + #10 serclk = 0; + #10 serclk = 1; + #10 serclk = 0; + end + #10 serenable = 0; + // #10 serload = 0; + // #10 serload = 1; + #10 serclk = 1; + #10 serclk = 0; + //#10 serload = 0; + end + endtask // send_config_word + + +///////////////////////////////////////////////////////// + diff --git a/toplevel/mrfm/biquad_2stage.v b/toplevel/mrfm/biquad_2stage.v new file mode 100644 index 000000000..9b769014d --- /dev/null +++ b/toplevel/mrfm/biquad_2stage.v @@ -0,0 +1,131 @@ +`include "mrfm.vh" + +module biquad_2stage (input clock, input reset, input strobe_in, + input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, + input wire [15:0] sample_in, output reg [15:0] sample_out, output wire [63:0] debugbus); + + wire [3:0] coeff_addr, coeff_wr_addr; + wire [3:0] data_addr, data_wr_addr; + reg [3:0] cur_offset, data_addr_int, data_wr_addr_int; + + wire [15:0] coeff, coeff_wr_data, data, data_wr_data; + wire coeff_wr; + reg data_wr; + + wire [30:0] product; + wire [33:0] accum; + wire [15:0] scaled_accum; + + wire [7:0] shift; + reg [3:0] phase; + wire enable_mult, enable_acc, latch_out, select_input; + reg done, clear_acc; + + setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr)); + + setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(shift),.changed()); + + ram16 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data), + .rd_addr(coeff_addr),.rd_data(coeff)); + + ram16 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data), + .rd_addr(data_addr),.rd_data(data)); + + mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() ); + + acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), + .addend(product),.sum(accum) ); + + shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); + + assign data_wr_data = select_input ? sample_in : scaled_accum; + assign enable_mult = 1'b1; + + always @(posedge clock) + if(reset) + cur_offset <= #1 4'd0; + else if(latch_out) + cur_offset <= #1 cur_offset + 4'd1; + + assign data_addr = data_addr_int + cur_offset; + assign data_wr_addr = data_wr_addr_int + cur_offset; + + always @(posedge clock) + if(reset) + done <= #1 1'b0; + else if(latch_out) + done <= #1 1'b1; + else if(strobe_in) + done <= #1 1'b0; + + always @(posedge clock) + if(reset) + phase <= #1 4'd0; + else if(strobe_in) + phase <= #1 4'd0; + else if(!done) + phase <= #1 phase + 4'd1; + + assign coeff_addr = phase; + + always @(phase) + case(phase) + 4'd01 : data_addr_int = 4'd00; 4'd02 : data_addr_int = 4'd01; 4'd03 : data_addr_int = 4'd02; + 4'd04 : data_addr_int = 4'd03; 4'd05 : data_addr_int = 4'd04; + + 4'd07 : data_addr_int = 4'd03; 4'd08 : data_addr_int = 4'd04; 4'd09 : data_addr_int = 4'd05; + 4'd10 : data_addr_int = 4'd06; 4'd11 : data_addr_int = 4'd07; + default : data_addr_int = 4'd00; + endcase // case(phase) + + always @(phase) + case(phase) + 4'd0 : data_wr_addr_int = 4'd2; + 4'd8 : data_wr_addr_int = 4'd5; + 4'd14 : data_wr_addr_int = 4'd8; + default : data_wr_addr_int = 4'd0; + endcase // case(phase) + + always @(phase) + case(phase) + 4'd0, 4'd8, 4'd14 : data_wr = 1'b1; + default : data_wr = 1'b0; + endcase // case(phase) + + assign select_input = (phase == 4'd0); + + always @(phase) + case(phase) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd9, 4'd15 : clear_acc = 1'd1; + default : clear_acc = 1'b0; + endcase // case(phase) + + assign enable_acc = ~clear_acc; + assign latch_out = (phase == 4'd14); + + always @(posedge clock) + if(reset) + sample_out <= #1 16'd0; + else if(latch_out) + sample_out <= #1 scaled_accum; + + //////////////////////////////////////////////////////// + // Debug + + wire [3:0] debugmux; + + setting_reg #(`FR_MRFM_DEBUG) sr_debugmux(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(debugmux),.changed()); + + assign debugbus[15:0] = debugmux[0] ? {coeff_addr,data_addr,data_wr_addr,cur_offset} : {phase,data_addr_int,data_wr_addr_int,cur_offset}; + assign debugbus[31:16] = debugmux[1] ? scaled_accum : {clock, strobe_in, data_wr, enable_mult, enable_acc, clear_acc, latch_out,select_input,done, data_addr_int}; + assign debugbus[47:32] = debugmux[2] ? sample_out : coeff; + assign debugbus[63:48] = debugmux[3] ? sample_in : data; + +endmodule // biquad_2stage + diff --git a/toplevel/mrfm/biquad_6stage.v b/toplevel/mrfm/biquad_6stage.v new file mode 100644 index 000000000..2b0c511ce --- /dev/null +++ b/toplevel/mrfm/biquad_6stage.v @@ -0,0 +1,137 @@ +`include "mrfm.vh" + +module mrfm_iir (input clock, input reset, input strobe_in, + input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, + input wire [15:0] sample_in, output reg [15:0] sample_out); + + wire [5:0] coeff_addr, coeff_wr_addr; + wire [4:0] data_addr, data_wr_addr; + reg [4:0] cur_offset, data_addr_int, data_wr_addr_int; + + wire [15:0] coeff, coeff_wr_data, data, data_wr_data; + wire coeff_wr; + reg data_wr; + + wire [30:0] product; + wire [33:0] accum; + wire [15:0] scaled_accum; + + wire [7:0] shift; + reg [5:0] phase; + wire enable_mult, enable_acc, latch_out, select_input; + reg done, clear_acc; + + setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr)); + + setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(shift),.changed()); + + ram64 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data), + .rd_addr(coeff_addr),.rd_data(coeff)); + + ram32 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data), + .rd_addr(data_addr),.rd_data(data)); + + mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() ); + + acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), + .addend(product),.sum(accum) ); + + shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); + + assign data_wr_data = select_input ? sample_in : scaled_accum; + assign enable_mult = 1'b1; + + always @(posedge clock) + if(reset) + cur_offset <= #1 5'd0; + else if(latch_out) + cur_offset <= #1 cur_offset + 5'd1; + + assign data_addr = data_addr_int + cur_offset; + assign data_wr_addr = data_wr_addr_int + cur_offset; + + always @(posedge clock) + if(reset) + done <= #1 1'b0; + else if(latch_out) + done <= #1 1'b1; + else if(strobe_in) + done <= #1 1'b0; + + always @(posedge clock) + if(reset) + phase <= #1 6'd0; + else if(strobe_in) + phase <= #1 6'd0; + else if(!done) + phase <= #1 phase + 6'd1; + + always @(phase) + case(phase) + 6'd0 : data_addr_int = 5'd0; + default : data_addr_int = 5'd0; + endcase // case(phase) + + assign coeff_addr = phase; + + always @(phase) + case(phase) + 6'd01 : data_addr_int = 5'd00; 6'd02 : data_addr_int = 5'd01; 6'd03 : data_addr_int = 5'd02; + 6'd04 : data_addr_int = 5'd03; 6'd05 : data_addr_int = 5'd04; + + 6'd07 : data_addr_int = 5'd03; 6'd08 : data_addr_int = 5'd04; 6'd09 : data_addr_int = 5'd05; + 6'd10 : data_addr_int = 5'd06; 6'd11 : data_addr_int = 5'd07; + + 6'd13 : data_addr_int = 5'd06; 6'd14 : data_addr_int = 5'd07; 6'd15 : data_addr_int = 5'd08; + 6'd16 : data_addr_int = 5'd09; 6'd17 : data_addr_int = 5'd10; + + 6'd19 : data_addr_int = 5'd09; 6'd20 : data_addr_int = 5'd10; 6'd21 : data_addr_int = 5'd11; + 6'd22 : data_addr_int = 5'd12; 6'd23 : data_addr_int = 5'd13; + + 6'd25 : data_addr_int = 5'd12; 6'd26 : data_addr_int = 5'd13; 6'd27 : data_addr_int = 5'd14; + 6'd28 : data_addr_int = 5'd15; 6'd29 : data_addr_int = 5'd16; + + 6'd31 : data_addr_int = 5'd15; 6'd32 : data_addr_int = 5'd16; 6'd33 : data_addr_int = 5'd17; + 6'd34 : data_addr_int = 5'd18; 6'd35 : data_addr_int = 5'd19; + + default : data_addr_int = 5'd00; + endcase // case(phase) + + always @(phase) + case(phase) + 6'd0 : data_wr_addr_int = 5'd2; + 6'd8 : data_wr_addr_int = 5'd5; + 6'd14 : data_wr_addr_int = 5'd8; + 6'd20 : data_wr_addr_int = 5'd11; + 6'd26 : data_wr_addr_int = 5'd14; + 6'd32 : data_wr_addr_int = 5'd17; + 6'd38 : data_wr_addr_int = 5'd20; + default : data_wr_addr_int = 5'd0; + endcase // case(phase) + + always @(phase) + case(phase) + 6'd0, 6'd8, 6'd14, 6'd20, 6'd26, 6'd32, 6'd38: data_wr = 1'b1; + default : data_wr = 1'b0; + endcase // case(phase) + + always @(phase) + case(phase) + 6'd0, 6'd1, 6'd2, 6'd3, 6'd9, 6'd15, 6'd21, 6'd27, 6'd33 : clear_acc = 1'd1; + default : clear_acc = 1'b0; + endcase // case(phase) + + assign enable_acc = ~clear_acc; + assign latch_out = (phase == 6'd38); + + always @(posedge clock) + if(reset) + sample_out <= #1 16'd0; + else if(latch_out) + sample_out <= #1 scaled_accum; + +endmodule // mrfm_iir diff --git a/toplevel/mrfm/mrfm.csf b/toplevel/mrfm/mrfm.csf new file mode 100644 index 000000000..2c30b996b --- /dev/null +++ b/toplevel/mrfm/mrfm.csf @@ -0,0 +1,444 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; + OPTIMIZE_TIMING = "NORMAL COMPILATION"; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = OFF; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |mrfm; + ROUTING_BACK_ANNOTATION_MODE = OFF; + INC_PLC_MODE = OFF; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} +CHIP(mrfm) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; + AUTO_RESTART_CONFIGURATION = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + USER_START_UP_CLOCK = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_JTAG_BST_SUPPORT = OFF; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + USE_CONFIGURATION_DEVICE = OFF; + APEX20K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + STRATIX_UPDATE_MODE = STANDARD; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + COMPRESSION_MODE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + GENERATE_TTF_FILE = OFF; + GENERATE_RBF_FILE = ON; + GENERATE_HEX_FILE = OFF; + SECURITY_BIT = OFF; + ENABLE_VREFA_PIN = OFF; + ENABLE_VREFB_PIN = OFF; + GENERATE_SVF_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_JBC_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_HEXOUT_FILE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; + BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; + HEXOUT_FILE_START_ADDRESS = 0; + HEXOUT_FILE_COUNT_DIRECTION = UP; + RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; + STRATIX_DEVICE_IO_STANDARD = LVTTL; + CLOCK_SOURCE = INTERNAL; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CONFIGURATION_CLOCK_DIVISOR = 1; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + SCLK : LOCATION = Pin_101; + SDI : LOCATION = Pin_100; + SEN : LOCATION = Pin_98; + SLD : LOCATION = Pin_95; + adc1_data[0] : LOCATION = Pin_5; + adc1_data[10] : LOCATION = Pin_235; + adc1_data[11] : LOCATION = Pin_234; + adc1_data[1] : LOCATION = Pin_4; + adc1_data[2] : LOCATION = Pin_3; + adc1_data[3] : LOCATION = Pin_2; + adc1_data[4] : LOCATION = Pin_1; + adc1_data[4] : IO_STANDARD = LVTTL; + adc1_data[5] : LOCATION = Pin_240; + adc1_data[6] : LOCATION = Pin_239; + adc1_data[7] : LOCATION = Pin_238; + adc1_data[8] : LOCATION = Pin_237; + adc1_data[9] : LOCATION = Pin_236; + adc2_data[0] : LOCATION = Pin_20; + adc2_data[10] : LOCATION = Pin_8; + adc2_data[11] : LOCATION = Pin_7; + adc2_data[1] : LOCATION = Pin_19; + adc2_data[2] : LOCATION = Pin_18; + adc2_data[3] : LOCATION = Pin_17; + adc2_data[4] : LOCATION = Pin_16; + adc2_data[5] : LOCATION = Pin_15; + adc2_data[6] : LOCATION = Pin_14; + adc2_data[7] : LOCATION = Pin_13; + adc2_data[8] : LOCATION = Pin_12; + adc2_data[9] : LOCATION = Pin_11; + adc3_data[0] : LOCATION = Pin_200; + adc3_data[10] : LOCATION = Pin_184; + adc3_data[11] : LOCATION = Pin_183; + adc3_data[1] : LOCATION = Pin_197; + adc3_data[2] : LOCATION = Pin_196; + adc3_data[3] : LOCATION = Pin_195; + adc3_data[4] : LOCATION = Pin_194; + adc3_data[5] : LOCATION = Pin_193; + adc3_data[6] : LOCATION = Pin_188; + adc3_data[7] : LOCATION = Pin_187; + adc3_data[8] : LOCATION = Pin_186; + adc3_data[9] : LOCATION = Pin_185; + adc4_data[0] : LOCATION = Pin_222; + adc4_data[10] : LOCATION = Pin_203; + adc4_data[11] : LOCATION = Pin_202; + adc4_data[1] : LOCATION = Pin_219; + adc4_data[2] : LOCATION = Pin_217; + adc4_data[3] : LOCATION = Pin_216; + adc4_data[4] : LOCATION = Pin_215; + adc4_data[5] : LOCATION = Pin_214; + adc4_data[6] : LOCATION = Pin_213; + adc4_data[7] : LOCATION = Pin_208; + adc4_data[8] : LOCATION = Pin_207; + adc4_data[9] : LOCATION = Pin_206; + adc_oeb[0] : LOCATION = Pin_228; + adc_oeb[1] : LOCATION = Pin_21; + adc_oeb[2] : LOCATION = Pin_181; + adc_oeb[3] : LOCATION = Pin_218; + adc_otr[0] : LOCATION = Pin_233; + adc_otr[1] : LOCATION = Pin_6; + adc_otr[2] : LOCATION = Pin_182; + adc_otr[3] : LOCATION = Pin_201; + adclk0 : LOCATION = Pin_224; + adclk1 : LOCATION = Pin_226; + clk0 : LOCATION = Pin_28; + clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk0 : IO_STANDARD = LVTTL; + clk1 : LOCATION = Pin_29; + clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk1 : IO_STANDARD = LVTTL; + clk3 : LOCATION = Pin_152; + clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk3 : IO_STANDARD = LVTTL; + clk_120mhz : LOCATION = Pin_153; + clk_120mhz : IO_STANDARD = LVTTL; + clk_out : LOCATION = Pin_63; + clk_out : IO_STANDARD = LVTTL; + dac1_data[0] : LOCATION = Pin_165; + dac1_data[10] : LOCATION = Pin_177; + dac1_data[11] : LOCATION = Pin_178; + dac1_data[12] : LOCATION = Pin_179; + dac1_data[13] : LOCATION = Pin_180; + dac1_data[1] : LOCATION = Pin_166; + dac1_data[2] : LOCATION = Pin_167; + dac1_data[3] : LOCATION = Pin_168; + dac1_data[4] : LOCATION = Pin_169; + dac1_data[5] : LOCATION = Pin_170; + dac1_data[6] : LOCATION = Pin_173; + dac1_data[7] : LOCATION = Pin_174; + dac1_data[8] : LOCATION = Pin_175; + dac1_data[9] : LOCATION = Pin_176; + dac2_data[0] : LOCATION = Pin_159; + dac2_data[10] : LOCATION = Pin_163; + dac2_data[11] : LOCATION = Pin_139; + dac2_data[12] : LOCATION = Pin_164; + dac2_data[13] : LOCATION = Pin_138; + dac2_data[1] : LOCATION = Pin_158; + dac2_data[2] : LOCATION = Pin_160; + dac2_data[3] : LOCATION = Pin_156; + dac2_data[4] : LOCATION = Pin_161; + dac2_data[5] : LOCATION = Pin_144; + dac2_data[6] : LOCATION = Pin_162; + dac2_data[7] : LOCATION = Pin_141; + dac2_data[8] : LOCATION = Pin_143; + dac2_data[9] : LOCATION = Pin_140; + dac3_data[0] : LOCATION = Pin_122; + dac3_data[10] : LOCATION = Pin_134; + dac3_data[11] : LOCATION = Pin_135; + dac3_data[12] : LOCATION = Pin_136; + dac3_data[13] : LOCATION = Pin_137; + dac3_data[1] : LOCATION = Pin_123; + dac3_data[2] : LOCATION = Pin_124; + dac3_data[3] : LOCATION = Pin_125; + dac3_data[4] : LOCATION = Pin_126; + dac3_data[5] : LOCATION = Pin_127; + dac3_data[6] : LOCATION = Pin_128; + dac3_data[7] : LOCATION = Pin_131; + dac3_data[8] : LOCATION = Pin_132; + dac3_data[9] : LOCATION = Pin_133; + dac4_data[0] : LOCATION = Pin_104; + dac4_data[10] : LOCATION = Pin_118; + dac4_data[11] : LOCATION = Pin_119; + dac4_data[12] : LOCATION = Pin_120; + dac4_data[13] : LOCATION = Pin_121; + dac4_data[1] : LOCATION = Pin_105; + dac4_data[2] : LOCATION = Pin_106; + dac4_data[3] : LOCATION = Pin_107; + dac4_data[4] : LOCATION = Pin_108; + dac4_data[5] : LOCATION = Pin_113; + dac4_data[6] : LOCATION = Pin_114; + dac4_data[7] : LOCATION = Pin_115; + dac4_data[8] : LOCATION = Pin_116; + dac4_data[9] : LOCATION = Pin_117; + enable_rx : LOCATION = Pin_88; + enable_tx : LOCATION = Pin_93; + gndbus[0] : LOCATION = Pin_223; + gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[0] : IO_STANDARD = LVTTL; + gndbus[1] : LOCATION = Pin_225; + gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[1] : IO_STANDARD = LVTTL; + gndbus[2] : LOCATION = Pin_227; + gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[2] : IO_STANDARD = LVTTL; + gndbus[3] : LOCATION = Pin_62; + gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[3] : IO_STANDARD = LVTTL; + gndbus[4] : LOCATION = Pin_64; + gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[4] : IO_STANDARD = LVTTL; + misc_pins[0] : LOCATION = Pin_87; + misc_pins[0] : IO_STANDARD = LVTTL; + misc_pins[10] : LOCATION = Pin_76; + misc_pins[10] : IO_STANDARD = LVTTL; + misc_pins[11] : LOCATION = Pin_74; + misc_pins[11] : IO_STANDARD = LVTTL; + misc_pins[1] : LOCATION = Pin_86; + misc_pins[1] : IO_STANDARD = LVTTL; + misc_pins[2] : LOCATION = Pin_85; + misc_pins[2] : IO_STANDARD = LVTTL; + misc_pins[3] : LOCATION = Pin_84; + misc_pins[3] : IO_STANDARD = LVTTL; + misc_pins[4] : LOCATION = Pin_83; + misc_pins[4] : IO_STANDARD = LVTTL; + misc_pins[5] : LOCATION = Pin_82; + misc_pins[5] : IO_STANDARD = LVTTL; + misc_pins[6] : LOCATION = Pin_79; + misc_pins[6] : IO_STANDARD = LVTTL; + misc_pins[7] : LOCATION = Pin_78; + misc_pins[7] : IO_STANDARD = LVTTL; + misc_pins[8] : LOCATION = Pin_77; + misc_pins[8] : IO_STANDARD = LVTTL; + misc_pins[9] : LOCATION = Pin_75; + misc_pins[9] : IO_STANDARD = LVTTL; + reset : LOCATION = Pin_94; + usbclk : LOCATION = Pin_55; + usbctl[0] : LOCATION = Pin_56; + usbctl[1] : LOCATION = Pin_54; + usbctl[2] : LOCATION = Pin_53; + usbctl[3] : LOCATION = Pin_58; + usbctl[4] : LOCATION = Pin_57; + usbctl[5] : LOCATION = Pin_44; + usbdata[0] : LOCATION = Pin_73; + usbdata[10] : LOCATION = Pin_41; + usbdata[11] : LOCATION = Pin_39; + usbdata[12] : LOCATION = Pin_38; + usbdata[12] : IO_STANDARD = LVTTL; + usbdata[13] : LOCATION = Pin_37; + usbdata[14] : LOCATION = Pin_24; + usbdata[15] : LOCATION = Pin_23; + usbdata[1] : LOCATION = Pin_68; + usbdata[2] : LOCATION = Pin_67; + usbdata[3] : LOCATION = Pin_66; + usbdata[4] : LOCATION = Pin_65; + usbdata[5] : LOCATION = Pin_61; + usbdata[6] : LOCATION = Pin_60; + usbdata[7] : LOCATION = Pin_59; + usbdata[8] : LOCATION = Pin_43; + usbdata[9] : LOCATION = Pin_42; + usbrdy[0] : LOCATION = Pin_45; + usbrdy[1] : LOCATION = Pin_46; + usbrdy[2] : LOCATION = Pin_47; + usbrdy[3] : LOCATION = Pin_48; + usbrdy[4] : LOCATION = Pin_49; + usbrdy[5] : LOCATION = Pin_50; + clear_status : LOCATION = Pin_99; +} diff --git a/toplevel/mrfm/mrfm.esf b/toplevel/mrfm/mrfm.esf new file mode 100644 index 000000000..72b84e39e --- /dev/null +++ b/toplevel/mrfm/mrfm.esf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = mrfm; +} diff --git a/toplevel/mrfm/mrfm.psf b/toplevel/mrfm/mrfm.psf new file mode 100644 index 000000000..678a7faa2 --- /dev/null +++ b/toplevel/mrfm/mrfm.psf @@ -0,0 +1,312 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_DSP_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_TURBO_BIT = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_PARALLEL_EXPANDERS = ON; + AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; + AUTO_FAST_OUTPUT_REGISTERS = OFF; + AUTO_FAST_INPUT_REGISTERS = OFF; + AUTO_CASCADE_CHAINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; + PARALLEL_EXPANDER_CHAIN_LENGTH = 16; + CASCADE_CHAIN_LENGTH = 2; + STRATIX_CARRY_CHAIN_LENGTH = 70; + MERCURY_CARRY_CHAIN_LENGTH = 48; + FLEX10K_CARRY_CHAIN_LENGTH = 32; + FLEX6K_CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN_LENGTH = 48; + CARRY_OUT_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + AUTO_LCELL_INSERTION = ON; + ALLOW_XOR_GATE_USAGE = ON; + AUTO_PACKED_REGISTERS_STRATIX = NORMAL; + AUTO_PACKED_REGISTERS = OFF; + AUTO_PACKED_REG_CYCLONE = NORMAL; + FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; + FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; + MERCURY_OPTIMIZATION_TECHNIQUE = AREA; + APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; + MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; + STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; + CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; + FLEX10K_TECHNOLOGY_MAPPER = LUT; + FLEX6K_TECHNOLOGY_MAPPER = LUT; + MERCURY_TECHNOLOGY_MAPPER = LUT; + APEX20K_TECHNOLOGY_MAPPER = LUT; + MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; + STRATIX_TECHNOLOGY_MAPPER = LUT; + AUTO_IMPLEMENT_IN_ROM = OFF; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_CLOCK = ON; + USE_LPM_FOR_AHDL_OPERATORS = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + TURBO_BIT = ON; + MAX7000_IGNORE_SOFT_BUFFERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MAX7000_IGNORE_LCELL_BUFFERS = AUTO; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + DSP_BLOCK_BALANCING = AUTO; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(mrfm) +{ + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; + USER_LIBRARIES = "e:\usrp\fpga\megacells"; +} +THIRD_PARTY_EDA_TOOLS(mrfm) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} +CLOCK(clk_120mhz) +{ + FMAX_REQUIREMENT = "120.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(usbclk) +{ + FMAX_REQUIREMENT = "48.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(SCLK) +{ + FMAX_REQUIREMENT = "1.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk0) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk1) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} diff --git a/toplevel/mrfm/mrfm.py b/toplevel/mrfm/mrfm.py new file mode 100644 index 000000000..0ce46012d --- /dev/null +++ b/toplevel/mrfm/mrfm.py @@ -0,0 +1,129 @@ +#!/usr/bin/env python +# +# This is mrfm_fft_sos.py +# Modification of Matt's mrfm_fft.py that reads filter coefs from file +# +# Copyright 2004,2005 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# + +from gnuradio import gr, gru +from gnuradio import usrp + +class source_c(usrp.source_c): + def __init__(self,fpga_filename): + usrp.source_c.__init__(self,which=0, decim_rate=64, nchan=2, mux=0x32103210, mode=0, + fpga_filename=fpga_filename) + + self._write_9862(0,2,0x80) # Bypass ADC buffer, minimum gain + self._write_9862(0,3,0x80) # Bypass ADC buffer, minimum gain + + self._write_9862(0,8,0) # TX PWR Down + self._write_9862(0,10,0) # DAC offset + self._write_9862(0,11,0) # DAC offset + self._write_9862(0,14,0x80) # gain + self._write_9862(0,16,0xff) # pga + self._write_9862(0,18,0x0c) # TX IF + self._write_9862(0,19,0x01) # TX Digital + self._write_9862(0,20,0x00) # TX Mod + + # max/min values are +/-2, so scale is set to make 2 = 32767 + + self._write_fpga_reg(69,0x0e) # debug mux + self._write_fpga_reg(5,-1) + self._write_fpga_reg(7,-1) + self._write_oe(0,0xffff, 0xffff) + self._write_oe(1,0xffff, 0xffff) + self._write_fpga_reg(14,0xf) + + self.decim = None + + def set_coeffs(self,frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11): + def make_val(address,value): + return (address << 16) | (value & 0xffff) + + # gain, scale already included in a's and b's from file + + self._write_fpga_reg(67,make_val(1,b20)) + self._write_fpga_reg(67,make_val(2,b10)) + self._write_fpga_reg(67,make_val(3,b00)) + self._write_fpga_reg(67,make_val(4,a20)) + self._write_fpga_reg(67,make_val(5,a10)) + + self._write_fpga_reg(67,make_val(7,b21)) + self._write_fpga_reg(67,make_val(8,b11)) + self._write_fpga_reg(67,make_val(9,b01)) + self._write_fpga_reg(67,make_val(10,a21)) + self._write_fpga_reg(67,make_val(11,a11)) + + self._write_fpga_reg(68,frac_bits) # Shift + + print "Biquad 0 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b20,b10,b00,a20,a10) + print "Biquad 1 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b21,b11,b01,a21,a11) + + def set_decim_rate(self,rate=None): + i=2 + turn=1 + a=1 + b=1 + while (rate>1) and (i<257): + if (rate/i) * i == rate: + if turn == 1: + if a*i<257: + a = a * i + turn = 0 + elif b*i<257: + b = b * i + turn = 0 + else: + print "Failed to set DECIMATOR" + return self.decim + elif b*i<257: + b = b * i + turn = 1 + elif a*i<257: + a = a * i + turn = 1 + else: + print "Failed to set DECIMATOR" + return self.decim + rate=rate/i + continue + i = i + 1 + if rate > 1: + print "Failed to set DECIMATOR" + return self.decim + else: + self.decim = a*b + print "a = %d b = %d" % (a,b) + self._write_fpga_reg(64,(a-1)*256+(b-1)) # Set actual decimation + + def decim_rate(self): + return self.decim + + def set_center_freq(self,freq): + self._write_fpga_reg(65,int(-freq/64e6*65536*65536)) # set center freq + + def set_compensator(self,a11,a12,a21,a22,shift): + self._write_fpga_reg(70,a11) + self._write_fpga_reg(71,a12) + self._write_fpga_reg(72,a21) + self._write_fpga_reg(73,a22) + self._write_fpga_reg(74,shift) # comp shift + diff --git a/toplevel/mrfm/mrfm.qpf b/toplevel/mrfm/mrfm.qpf new file mode 100644 index 000000000..959140875 --- /dev/null +++ b/toplevel/mrfm/mrfm.qpf @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2004 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.0" +DATE = "17:10:11 December 20, 2004" + + +# Active Revisions + +PROJECT_REVISION = "mrfm" diff --git a/toplevel/mrfm/mrfm.qsf b/toplevel/mrfm/mrfm.qsf new file mode 100644 index 000000000..ba1ae0223 --- /dev/null +++ b/toplevel/mrfm/mrfm.qsf @@ -0,0 +1,411 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# mrfm_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" +set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2" + +# Pin & Location Assignments +# ========================== +set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" +set_location_assignment PIN_29 -to SCLK +set_location_assignment PIN_117 -to SDI +set_location_assignment PIN_28 -to usbclk +set_location_assignment PIN_107 -to usbctl[0] +set_location_assignment PIN_106 -to usbctl[1] +set_location_assignment PIN_105 -to usbctl[2] +set_location_assignment PIN_100 -to usbdata[0] +set_location_assignment PIN_84 -to usbdata[10] +set_location_assignment PIN_83 -to usbdata[11] +set_location_assignment PIN_82 -to usbdata[12] +set_location_assignment PIN_79 -to usbdata[13] +set_location_assignment PIN_78 -to usbdata[14] +set_location_assignment PIN_77 -to usbdata[15] +set_location_assignment PIN_99 -to usbdata[1] +set_location_assignment PIN_98 -to usbdata[2] +set_location_assignment PIN_95 -to usbdata[3] +set_location_assignment PIN_94 -to usbdata[4] +set_location_assignment PIN_93 -to usbdata[5] +set_location_assignment PIN_88 -to usbdata[6] +set_location_assignment PIN_87 -to usbdata[7] +set_location_assignment PIN_86 -to usbdata[8] +set_location_assignment PIN_85 -to usbdata[9] +set_location_assignment PIN_104 -to usbrdy[0] +set_location_assignment PIN_101 -to usbrdy[1] +set_location_assignment PIN_76 -to FX2_1 +set_location_assignment PIN_75 -to FX2_2 +set_location_assignment PIN_74 -to FX2_3 +set_location_assignment PIN_116 -to io_rx_a[0] +set_location_assignment PIN_115 -to io_rx_a[1] +set_location_assignment PIN_114 -to io_rx_a[2] +set_location_assignment PIN_113 -to io_rx_a[3] +set_location_assignment PIN_108 -to io_rx_a[4] +set_location_assignment PIN_195 -to io_rx_a[5] +set_location_assignment PIN_196 -to io_rx_a[6] +set_location_assignment PIN_197 -to io_rx_a[7] +set_location_assignment PIN_200 -to io_rx_a[8] +set_location_assignment PIN_201 -to io_rx_a[9] +set_location_assignment PIN_202 -to io_rx_a[10] +set_location_assignment PIN_203 -to io_rx_a[11] +set_location_assignment PIN_206 -to io_rx_a[12] +set_location_assignment PIN_207 -to io_rx_a[13] +set_location_assignment PIN_208 -to io_rx_a[14] +set_location_assignment PIN_214 -to io_rx_b[0] +set_location_assignment PIN_215 -to io_rx_b[1] +set_location_assignment PIN_216 -to io_rx_b[2] +set_location_assignment PIN_217 -to io_rx_b[3] +set_location_assignment PIN_218 -to io_rx_b[4] +set_location_assignment PIN_219 -to io_rx_b[5] +set_location_assignment PIN_222 -to io_rx_b[6] +set_location_assignment PIN_223 -to io_rx_b[7] +set_location_assignment PIN_224 -to io_rx_b[8] +set_location_assignment PIN_225 -to io_rx_b[9] +set_location_assignment PIN_226 -to io_rx_b[10] +set_location_assignment PIN_227 -to io_rx_b[11] +set_location_assignment PIN_228 -to io_rx_b[12] +set_location_assignment PIN_233 -to io_rx_b[13] +set_location_assignment PIN_234 -to io_rx_b[14] +set_location_assignment PIN_175 -to io_tx_a[0] +set_location_assignment PIN_176 -to io_tx_a[1] +set_location_assignment PIN_177 -to io_tx_a[2] +set_location_assignment PIN_178 -to io_tx_a[3] +set_location_assignment PIN_179 -to io_tx_a[4] +set_location_assignment PIN_180 -to io_tx_a[5] +set_location_assignment PIN_181 -to io_tx_a[6] +set_location_assignment PIN_182 -to io_tx_a[7] +set_location_assignment PIN_183 -to io_tx_a[8] +set_location_assignment PIN_184 -to io_tx_a[9] +set_location_assignment PIN_185 -to io_tx_a[10] +set_location_assignment PIN_186 -to io_tx_a[11] +set_location_assignment PIN_187 -to io_tx_a[12] +set_location_assignment PIN_188 -to io_tx_a[13] +set_location_assignment PIN_193 -to io_tx_a[14] +set_location_assignment PIN_73 -to io_tx_b[0] +set_location_assignment PIN_68 -to io_tx_b[1] +set_location_assignment PIN_67 -to io_tx_b[2] +set_location_assignment PIN_66 -to io_tx_b[3] +set_location_assignment PIN_65 -to io_tx_b[4] +set_location_assignment PIN_64 -to io_tx_b[5] +set_location_assignment PIN_63 -to io_tx_b[6] +set_location_assignment PIN_62 -to io_tx_b[7] +set_location_assignment PIN_61 -to io_tx_b[8] +set_location_assignment PIN_60 -to io_tx_b[9] +set_location_assignment PIN_59 -to io_tx_b[10] +set_location_assignment PIN_58 -to io_tx_b[11] +set_location_assignment PIN_57 -to io_tx_b[12] +set_location_assignment PIN_56 -to io_tx_b[13] +set_location_assignment PIN_55 -to io_tx_b[14] +set_location_assignment PIN_152 -to master_clk +set_location_assignment PIN_144 -to rx_a_a[0] +set_location_assignment PIN_143 -to rx_a_a[1] +set_location_assignment PIN_141 -to rx_a_a[2] +set_location_assignment PIN_140 -to rx_a_a[3] +set_location_assignment PIN_139 -to rx_a_a[4] +set_location_assignment PIN_138 -to rx_a_a[5] +set_location_assignment PIN_137 -to rx_a_a[6] +set_location_assignment PIN_136 -to rx_a_a[7] +set_location_assignment PIN_135 -to rx_a_a[8] +set_location_assignment PIN_134 -to rx_a_a[9] +set_location_assignment PIN_133 -to rx_a_a[10] +set_location_assignment PIN_132 -to rx_a_a[11] +set_location_assignment PIN_23 -to rx_a_b[0] +set_location_assignment PIN_21 -to rx_a_b[1] +set_location_assignment PIN_20 -to rx_a_b[2] +set_location_assignment PIN_19 -to rx_a_b[3] +set_location_assignment PIN_18 -to rx_a_b[4] +set_location_assignment PIN_17 -to rx_a_b[5] +set_location_assignment PIN_16 -to rx_a_b[6] +set_location_assignment PIN_15 -to rx_a_b[7] +set_location_assignment PIN_14 -to rx_a_b[8] +set_location_assignment PIN_13 -to rx_a_b[9] +set_location_assignment PIN_12 -to rx_a_b[10] +set_location_assignment PIN_11 -to rx_a_b[11] +set_location_assignment PIN_131 -to rx_b_a[0] +set_location_assignment PIN_128 -to rx_b_a[1] +set_location_assignment PIN_127 -to rx_b_a[2] +set_location_assignment PIN_126 -to rx_b_a[3] +set_location_assignment PIN_125 -to rx_b_a[4] +set_location_assignment PIN_124 -to rx_b_a[5] +set_location_assignment PIN_123 -to rx_b_a[6] +set_location_assignment PIN_122 -to rx_b_a[7] +set_location_assignment PIN_121 -to rx_b_a[8] +set_location_assignment PIN_120 -to rx_b_a[9] +set_location_assignment PIN_119 -to rx_b_a[10] +set_location_assignment PIN_118 -to rx_b_a[11] +set_location_assignment PIN_8 -to rx_b_b[0] +set_location_assignment PIN_7 -to rx_b_b[1] +set_location_assignment PIN_6 -to rx_b_b[2] +set_location_assignment PIN_5 -to rx_b_b[3] +set_location_assignment PIN_4 -to rx_b_b[4] +set_location_assignment PIN_3 -to rx_b_b[5] +set_location_assignment PIN_2 -to rx_b_b[6] +set_location_assignment PIN_240 -to rx_b_b[7] +set_location_assignment PIN_239 -to rx_b_b[8] +set_location_assignment PIN_238 -to rx_b_b[9] +set_location_assignment PIN_237 -to rx_b_b[10] +set_location_assignment PIN_236 -to rx_b_b[11] +set_location_assignment PIN_156 -to SDO +set_location_assignment PIN_153 -to SEN_FPGA +set_location_assignment PIN_159 -to tx_a[0] +set_location_assignment PIN_160 -to tx_a[1] +set_location_assignment PIN_161 -to tx_a[2] +set_location_assignment PIN_162 -to tx_a[3] +set_location_assignment PIN_163 -to tx_a[4] +set_location_assignment PIN_164 -to tx_a[5] +set_location_assignment PIN_165 -to tx_a[6] +set_location_assignment PIN_166 -to tx_a[7] +set_location_assignment PIN_167 -to tx_a[8] +set_location_assignment PIN_168 -to tx_a[9] +set_location_assignment PIN_169 -to tx_a[10] +set_location_assignment PIN_170 -to tx_a[11] +set_location_assignment PIN_173 -to tx_a[12] +set_location_assignment PIN_174 -to tx_a[13] +set_location_assignment PIN_38 -to tx_b[0] +set_location_assignment PIN_39 -to tx_b[1] +set_location_assignment PIN_41 -to tx_b[2] +set_location_assignment PIN_42 -to tx_b[3] +set_location_assignment PIN_43 -to tx_b[4] +set_location_assignment PIN_44 -to tx_b[5] +set_location_assignment PIN_45 -to tx_b[6] +set_location_assignment PIN_46 -to tx_b[7] +set_location_assignment PIN_47 -to tx_b[8] +set_location_assignment PIN_48 -to tx_b[9] +set_location_assignment PIN_49 -to tx_b[10] +set_location_assignment PIN_50 -to tx_b[11] +set_location_assignment PIN_53 -to tx_b[12] +set_location_assignment PIN_54 -to tx_b[13] +set_location_assignment PIN_158 -to TXSYNC_A +set_location_assignment PIN_37 -to TXSYNC_B +set_location_assignment PIN_235 -to io_rx_b[15] +set_location_assignment PIN_24 -to io_tx_b[15] +set_location_assignment PIN_213 -to io_rx_a[15] +set_location_assignment PIN_194 -to io_tx_a[15] +set_location_assignment PIN_1 -to MYSTERY_SIGNAL + +# Timing Assignments +# ================== +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name TOP_LEVEL_ENTITY mrfm +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name INC_PLC_MODE OFF +set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF +set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# Timing Analysis Assignments +# =========================== +set_global_assignment -name MAX_SCC_SIZE 50 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF + +# Simulator Assignments +# ===================== +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "1 ns" + +# Design Assistant Assignments +# ============================ +set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF +set_global_assignment -name ASSG_CAT OFF +set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF +set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF +set_global_assignment -name CLK_CAT OFF +set_global_assignment -name CLK_RULE_COMB_CLOCK OFF +set_global_assignment -name CLK_RULE_INV_CLOCK OFF +set_global_assignment -name CLK_RULE_GATING_SCHEME OFF +set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF +set_global_assignment -name CLK_RULE_MIX_EDGES OFF +set_global_assignment -name RESET_CAT OFF +set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name TIMING_CAT OFF +set_global_assignment -name TIMING_RULE_SHIFT_REG OFF +set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF +set_global_assignment -name NONSYNCHSTRUCT_CAT OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF +set_global_assignment -name SIGNALRACE_CAT OFF +set_global_assignment -name ACLK_CAT OFF +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF +set_global_assignment -name HCPY_CAT OFF +set_global_assignment -name HCPY_VREF_PINS OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name HUB_ENTITY_NAME SLD_HUB +set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST +set_global_assignment -name ENABLE_SIGNALTAP OFF + +# LogicLock Region Assignments +# ============================ +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF + +# ----------------- +# start CLOCK(SCLK) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK +set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK + +# end CLOCK(SCLK) +# --------------- + +# ----------------------- +# start CLOCK(master_clk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk +set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk + +# end CLOCK(master_clk) +# --------------------- + +# ------------------- +# start CLOCK(usbclk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk +set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk + +# end CLOCK(usbclk) +# ----------------- + +# ---------------------- +# start ENTITY(mrfm) + + # Timing Assignments + # ================== +set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK +set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk +set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk + +# end ENTITY(mrfm) +# -------------------- + + +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name VERILOG_FILE mrfm.vh +set_global_assignment -name VERILOG_FILE biquad_2stage.v +set_global_assignment -name VERILOG_FILE mrfm_compensator.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v +set_global_assignment -name VERILOG_FILE mrfm_proc.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v +set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v +set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v +set_global_assignment -name VERILOG_FILE mrfm.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" \ No newline at end of file diff --git a/toplevel/mrfm/mrfm.v b/toplevel/mrfm/mrfm.v new file mode 100644 index 000000000..cf9d1119a --- /dev/null +++ b/toplevel/mrfm/mrfm.v @@ -0,0 +1,199 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// Top level module for a full setup with DUCs and DDCs + +// Uncomment the following to include optional circuitry + +`include "mrfm.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module mrfm +(output MYSTERY_SIGNAL, + input master_clk, + input SCLK, + input SDI, + inout SDO, + input SEN_FPGA, + + input FX2_1, + output FX2_2, + output FX2_3, + + input wire [11:0] rx_a_a, + input wire [11:0] rx_b_a, + input wire [11:0] rx_a_b, + input wire [11:0] rx_b_b, + + output wire [13:0] tx_a, + output wire [13:0] tx_b, + + output wire TXSYNC_A, + output wire TXSYNC_B, + + // USB interface + input usbclk, + input wire [2:0] usbctl, + output wire [1:0] usbrdy, + inout [15:0] usbdata, // NB Careful, inout + + // These are the general purpose i/o's that go to the daughterboard slots + inout wire [15:0] io_tx_a, + inout wire [15:0] io_tx_b, + inout wire [15:0] io_rx_a, + inout wire [15:0] io_rx_b + ); + wire [15:0] debugdata,debugctrl; + assign MYSTERY_SIGNAL = 1'b0; + + wire clk64; + + wire WR = usbctl[0]; + wire RD = usbctl[1]; + wire OE = usbctl[2]; + + wire have_space, have_pkt_rdy; + assign usbrdy[0] = have_space; + assign usbrdy[1] = have_pkt_rdy; + + wire tx_underrun, rx_overrun; + wire clear_status = FX2_1; + assign FX2_2 = rx_overrun; + assign FX2_3 = tx_underrun; + + wire [15:0] usbdata_out; + + wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; + + wire tx_realsignals; + wire [3:0] rx_numchan; + + wire [15:0] tx_debugbus, rx_debugbus; + + wire enable_tx, enable_rx; + wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; + wire [7:0] settings; + + // Tri-state bus macro + bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); + + assign clk64 = master_clk; + + wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; + wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; + + wire serial_strobe; + wire [6:0] serial_addr; + wire [31:0] serial_data; + + ///////////////////////////////////////////////////////////////////////////////////////////////////// + + setting_reg #(`FR_TX_MUX) + sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + ////////////////////////////////////////////////////////////////////////////////////////////////////// + // Signal Processing Chain + + reg [15:0] adc0; + wire [15:0] dac0; + wire [15:0] i,q,ip,qp; + wire strobe_out; + wire sync_out; + + always @(posedge clk64) + adc0 <= #1 {rx_a_a[11],rx_a_a[11:0],3'b0}; + + wire [15:0] adc0_corr; + rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0_corr), + .serial_addr(7'd0),.serial_data(32'd0),.serial_strobe(1'b0)); + + //wire [63:0] filt_debug = 64'd0; + + mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .signal_in(adc0_corr),.signal_out(dac0),.sync_out(sync_out), + .i(i),.q(q),.ip(ip),.qp(qp),.strobe_out(strobe_out), + .debugbus( /* filt_debug */ )); + + wire txsync = 1'b0; + assign TXSYNC_A = txsync; + assign TXSYNC_B = txsync; + + assign tx_a = dac0[15:2]; + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Data Collection on RX Buffer + + assign rx_numchan[0] = 1'b0; + setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr), + .in(serial_data),.out(rx_numchan[3:1])); + + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(i),.ch_1(q), + .ch_2(ip),.ch_3(qp), + .ch_4(16'd0),.ch_5(16'd0), + .ch_6(16'd0),.ch_7(16'd0), + .rxclk(clk64),.rxstrobe(strobe_out), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .debugbus(rx_debugbus) ); + + ////////////////////////////////////////////////////////////////////////////// + // Control Functions + + wire [31:0] capabilities = 32'd2; + + serial_io serial_io + ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), + .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) ); + + wire [15:0] reg_0,reg_1,reg_2,reg_3; + master_control master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + .debug_0({15'd0,sync_out}), //filt_debug[63:48]), + .debug_1({15'd0,sync_out}), //filt_debug[47:32]), + .debug_2({15'd0,sync_out}), //filt_debug[31:16]), + .debug_3({15'd0,sync_out}), //filt_debug[15:0]), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + + io_pins io_pins + (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + +endmodule // mrfm + diff --git a/toplevel/mrfm/mrfm.vh b/toplevel/mrfm/mrfm.vh new file mode 100644 index 000000000..808342d8d --- /dev/null +++ b/toplevel/mrfm/mrfm.vh @@ -0,0 +1,21 @@ + + +// MRFM Register defines + +`define FR_MRFM_DECIM 7'd64 +`define FR_MRFM_FREQ 7'd65 +`define FR_MRFM_PHASE 7'd66 +`define FR_MRFM_IIR_COEFF 7'd67 +`define FR_MRFM_IIR_SHIFT 7'd68 +`define FR_MRFM_DEBUG 7'd69 +`define FR_MRFM_COMP_A11 7'd70 +`define FR_MRFM_COMP_A12 7'd71 +`define FR_MRFM_COMP_A21 7'd72 +`define FR_MRFM_COMP_A22 7'd73 +`define FR_MRFM_COMP_SHIFT 7'd74 +`define FR_USER_11 7'd75 +`define FR_USER_12 7'd76 +`define FR_USER_13 7'd77 +`define FR_USER_14 7'd78 +`define FR_USER_15 7'd79 + diff --git a/toplevel/mrfm/mrfm_compensator.v b/toplevel/mrfm/mrfm_compensator.v new file mode 100644 index 000000000..f44b73b2f --- /dev/null +++ b/toplevel/mrfm/mrfm_compensator.v @@ -0,0 +1,80 @@ + + +module mrfm_compensator (input clock, input reset, input strobe_in, + input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, + input [15:0] i_in, input [15:0] q_in, output reg [15:0] i_out, output reg [15:0] q_out); + + wire [15:0] a11,a12,a21,a22; + reg [15:0] i_in_reg, q_in_reg; + wire [30:0] product; + reg [3:0] phase; + wire [15:0] data,coeff; + wire [7:0] shift; + wire [33:0] accum; + wire [15:0] scaled_accum; + wire enable_acc; + + setting_reg #(`FR_MRFM_COMP_A11) sr_a11(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(a11),.changed()); + setting_reg #(`FR_MRFM_COMP_A12) sr_a12(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(a12),.changed()); + setting_reg #(`FR_MRFM_COMP_A21) sr_a21(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(a21),.changed()); + setting_reg #(`FR_MRFM_COMP_A22) sr_a22(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(a22),.changed()); + setting_reg #(`FR_MRFM_COMP_SHIFT) sr_cshift(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(shift),.changed()); + + mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(1'b1),.enable_out() ); + acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), + .addend(product),.sum(accum) ); + shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); + + always @(posedge clock) + if(reset) + begin + i_in_reg <= #1 16'd0; + q_in_reg <= #1 16'd0; + end + else if(strobe_in) + begin + i_in_reg <= #1 i_in; + q_in_reg <= #1 q_in; + end + + always @(posedge clock) + if(reset) + phase <= #1 4'd0; + else if(strobe_in) + phase <= #1 4'd1; + else if(strobe_in != 4'd8) + phase <= #1 phase + 4'd1; + + assign data = ((phase == 4'd1)||(phase === 4'd4)) ? i_in_reg : + ((phase == 4'd2)||(phase == 4'd5)) ? q_in_reg : 16'd0; + + assign coeff = (phase == 4'd1) ? a11 : (phase == 4'd2) ? a12 : + (phase == 4'd4) ? a21 : (phase == 4'd5) ? a22 : 16'd0; + + assign clear_acc = (phase == 4'd0) || (phase == 4'd1) || (phase == 4'd4) || (phase==4'd8); + assign enable_acc = ~clear_acc; + + always @(posedge clock) + if(reset) + i_out <= #1 16'd0; + else if(phase == 4'd4) + i_out <= #1 scaled_accum; + + always @(posedge clock) + if(reset) + q_out <= #1 16'd0; + else if(phase == 4'd7) + q_out <= #1 scaled_accum; + + +endmodule // mrfm_compensator diff --git a/toplevel/mrfm/mrfm_fft.py b/toplevel/mrfm/mrfm_fft.py new file mode 100755 index 000000000..343ab0197 --- /dev/null +++ b/toplevel/mrfm/mrfm_fft.py @@ -0,0 +1,319 @@ +#!/usr/bin/env python +# +# This is mrfm_fft_sos.py +# Modification of Matt's mrfm_fft.py that reads filter coefs from file +# +# Copyright 2004,2005 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# + +from gnuradio import gr, gru +from gnuradio import usrp +from gnuradio import eng_notation +from gnuradio.eng_option import eng_option +from gnuradio.wxgui import stdgui, fftsink, waterfallsink, scopesink, form, slider +from optparse import OptionParser +import wx +import sys +import mrfm + + +def pick_subdevice(u): + """ + The user didn't specify a subdevice on the command line. + If there's a daughterboard on A, select A. + If there's a daughterboard on B, select B. + Otherwise, select A. + """ + if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a problem + return (0, 0) + if u.db[1][0].dbid() >= 0: + return (1, 0) + return (0, 0) + +def read_ints(filename): + try: + f = open(filename) + ints = [ int(i) for i in f.read().split() ] + f.close() + return ints + except: + return [] + +class app_flow_graph(stdgui.gui_flow_graph): + def __init__(self, frame, panel, vbox, argv): + stdgui.gui_flow_graph.__init__(self) + + self.frame = frame + self.panel = panel + + parser = OptionParser(option_class=eng_option) + parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, + help="select USRP Rx side A or B (default=first one with a daughterboard)") + parser.add_option("-d", "--decim", type="int", default=16, + help="set fgpa decimation rate to DECIM [default=%default]") + parser.add_option("-f", "--freq", type="eng_float", default=None, + help="set frequency to FREQ", metavar="FREQ") + parser.add_option("-g", "--gain", type="eng_float", default=None, + help="set gain in dB (default is midpoint)") + parser.add_option("-W", "--waterfall", action="store_true", default=False, + help="Enable waterfall display") + parser.add_option("-8", "--width-8", action="store_true", default=False, + help="Enable 8-bit samples across USB") + parser.add_option("-S", "--oscilloscope", action="store_true", default=False, + help="Enable oscilloscope display") + parser.add_option("-F", "--filename", default=None, + help="Name of file with filter coefficients") + parser.add_option("-C", "--cfilename", default=None, + help="Name of file with compensator coefficients") + parser.add_option("-B", "--bitstream", default="mrfm.rbf", + help="Name of FPGA Bitstream file (.rbf)") + parser.add_option("-n", "--frame-decim", type="int", default=20, + help="set oscope frame decimation factor to n [default=12]") + (options, args) = parser.parse_args() + if len(args) != 0: + parser.print_help() + sys.exit(1) + + self.show_debug_info = True + + # default filter coefs + b00 = b01 = 16384 + b10 = b20 = a10 = a20 = b11 = b21 = a11 = a21 = 0 + + ba = read_ints(options.filename) + if len(ba) >= 6: + b00 = ba[0]; b10 = ba[1]; b20 = ba[2]; a10 = ba[4]; a20 = ba[5] + if len(ba) >= 12: + b01 = ba[6]; b11 = ba[7]; b21 = ba[8]; a11 = ba[10]; a21=ba[11] + print b00, b10, b20, a10, a20, b01, b11, b21, a11, a21 + + # default compensator coefficients + c11 = c22 = 1 + c12 = c21 = cscale = 0 + + cs = read_ints(options.cfilename) + if len(cs) >= 5: + c11 = cs[0]; c12 = cs[1]; c21 = cs[2]; c22 = cs[3]; cscale = cs[4] + print c11, c12, c21, c22, cscale + + # build the graph + self.u = mrfm.source_c(options.bitstream) + + self.u.set_decim_rate(options.decim) + self.u.set_center_freq(options.freq) + + frac_bits = 14 + self.u.set_coeffs(frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11) + + self.u.set_compensator(c11,c12,c21,c22,cscale) + + if options.rx_subdev_spec is None: + options.rx_subdev_spec = pick_subdevice(self.u) + self.u.set_mux(usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec)) + + if options.width_8: + width = 8 + shift = 8 + format = self.u.make_format(width, shift) + print "format =", hex(format) + r = self.u.set_format(format) + print "set_format =", r + + # determine the daughterboard subdevice we're using + self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec) + + #input_rate = self.u.adc_freq() / self.u.decim_rate() + input_rate = self.u.adc_freq() / options.decim + + # fft_rate = 15 + fft_rate = 5 + + self.deint = gr.deinterleave(gr.sizeof_gr_complex) + self.connect(self.u,self.deint) + + if options.waterfall: + self.scope1=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, + fft_rate=fft_rate) + self.scope2=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, + fft_rate=fft_rate) + + elif options.oscilloscope: + self.scope1 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) # added option JPJ 4/21/2006 + self.scope2 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) + + else: + self.scope1 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, + fft_rate=fft_rate) + self.scope2 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, + fft_rate=fft_rate) + + # Show I, I' on top scope panel, Q, Q' on bottom + #self.fin = gr.complex_to_float() + #self.fout = gr.complex_to_float() + + #self.connect((self.deint,0), self.fin) + #self.connect((self.deint,1), self.fout) + + #self.ii = gr.float_to_complex() + #self.qq = gr.float_to_complex() + + #self.connect((self.fin,0), (self.ii,0)) + #self.connect((self.fout,0), (self.ii,1)) + #self.connect((self.fin,1), (self.qq,0)) + #self.connect((self.fout,1), (self.qq,1)) + + #self.connect(self.ii, self.scope1) + #self.connect(self.qq, self.scope2) + + self.connect ((self.deint,0),self.scope1) + self.connect ((self.deint,1),self.scope2) + + self._build_gui(vbox) + + # set initial values + + if options.gain is None: + # if no gain was specified, use the mid-point in dB + g = self.subdev.gain_range() + options.gain = float(g[0]+g[1])/2 + + if options.freq is None: + # if no freq was specified, use the mid-point + r = self.subdev.freq_range() + options.freq = float(r[0]+r[1])/2 + + self.set_gain(options.gain) + + if not(self.set_freq(options.freq)): + self._set_status_msg("Failed to set initial frequency") + + if self.show_debug_info: + self.myform['decim'].set_value(self.u.decim_rate()) + self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) + self.myform['dbname'].set_value(self.subdev.name()) + + + def _set_status_msg(self, msg): + self.frame.GetStatusBar().SetStatusText(msg, 0) + + def _build_gui(self, vbox): + + def _form_set_freq(kv): + return self.set_freq(kv['freq']) + + vbox.Add(self.scope1.win, 10, wx.EXPAND) + vbox.Add(self.scope2.win, 10, wx.EXPAND) + + # add control area at the bottom + self.myform = myform = form.form() + hbox = wx.BoxSizer(wx.HORIZONTAL) + hbox.Add((5,0), 0, 0) + myform['freq'] = form.float_field( + parent=self.panel, sizer=hbox, label="Center freq", weight=1, + callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) + + hbox.Add((5,0), 0, 0) + g = self.subdev.gain_range() + myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain", + weight=3, + min=int(g[0]), max=int(g[1]), + callback=self.set_gain) + + hbox.Add((5,0), 0, 0) + vbox.Add(hbox, 0, wx.EXPAND) + + self._build_subpanel(vbox) + + def _build_subpanel(self, vbox_arg): + # build a secondary information panel (sometimes hidden) + + # FIXME figure out how to have this be a subpanel that is always + # created, but has its visibility controlled by foo.Show(True/False) + + if not(self.show_debug_info): + return + + panel = self.panel + vbox = vbox_arg + myform = self.myform + + #panel = wx.Panel(self.panel, -1) + #vbox = wx.BoxSizer(wx.VERTICAL) + + hbox = wx.BoxSizer(wx.HORIZONTAL) + hbox.Add((5,0), 0) + myform['decim'] = form.static_float_field( + parent=panel, sizer=hbox, label="Decim") + + hbox.Add((5,0), 1) + myform['fs@usb'] = form.static_float_field( + parent=panel, sizer=hbox, label="Fs@USB") + + hbox.Add((5,0), 1) + myform['dbname'] = form.static_text_field( + parent=panel, sizer=hbox) + + hbox.Add((5,0), 1) + myform['baseband'] = form.static_float_field( + parent=panel, sizer=hbox, label="Analog BB") + + hbox.Add((5,0), 1) + myform['ddc'] = form.static_float_field( + parent=panel, sizer=hbox, label="DDC") + + hbox.Add((5,0), 0) + vbox.Add(hbox, 0, wx.EXPAND) + + + + def set_freq(self, target_freq): + """ + Set the center frequency we're interested in. + + @param target_freq: frequency in Hz + @rypte: bool + + Tuning is a two step process. First we ask the front-end to + tune as close to the desired frequency as it can. Then we use + the result of that operation and our target_frequency to + determine the value for the digital down converter. + """ + r = self.u.tune(0, self.subdev, target_freq) + + if r: + self.myform['freq'].set_value(target_freq) # update displayed value + if self.show_debug_info: + self.myform['baseband'].set_value(r.baseband_freq) + self.myform['ddc'].set_value(r.dxc_freq) + return True + + return False + + def set_gain(self, gain): + self.myform['gain'].set_value(gain) # update displayed value + self.subdev.set_gain(gain) + + +def main (): + app = stdgui.stdapp(app_flow_graph, "USRP FFT", nstatus=1) + app.MainLoop() + +if __name__ == '__main__': + main () diff --git a/toplevel/mrfm/mrfm_proc.v b/toplevel/mrfm/mrfm_proc.v new file mode 100644 index 000000000..80de9fc90 --- /dev/null +++ b/toplevel/mrfm/mrfm_proc.v @@ -0,0 +1,96 @@ + +`include "mrfm.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module mrfm_proc (input clock, input reset, input enable, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, + input [15:0] signal_in, output wire [15:0] signal_out, output wire sync_out, + output wire [15:0] i, output wire [15:0] q, + output wire [15:0] ip, output wire [15:0] qp, + output wire strobe_out, output wire [63:0] debugbus); + + // Strobes + wire sample_strobe, strobe_0, strobe_1, strobe_2; + assign sample_strobe = 1'b1; + wire [7:0] rate_0, rate_1, rate_2; + + setting_reg #(`FR_MRFM_DECIM) sr_decim(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out({rate_2,rate_1,rate_0})); + + strobe_gen strobe_gen_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(sample_strobe),.strobe(strobe_0) ); + strobe_gen strobe_gen_1 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_0),.strobe(strobe_1) ); + + wire [31:0] phase; + + assign sync_out = phase[31]; + wire [15:0] i_decim_0, i_decim_1, i_decim_2; + wire [15:0] q_decim_0, q_decim_1, q_decim_2; + + wire [15:0] i_interp_0, i_interp_1, i_interp_2; + wire [15:0] q_interp_0, q_interp_1, q_interp_2; + + wire [15:0] i_filt, q_filt, i_comp, q_comp; + + assign ip=i_comp; + assign qp=q_comp; + + phase_acc #(`FR_MRFM_FREQ,`FR_MRFM_PHASE,32) rx_phase_acc + (.clk(clock),.reset(reset),.enable(enable), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .strobe(sample_strobe),.phase(phase) ); + + cordic rx_cordic (.clock(clock),.reset(reset),.enable(enable), + .xi(signal_in),.yi(16'd0),.zi(phase[31:16]), + .xo(i_decim_0),.yo(q_decim_0),.zo() ); + + cic_decim cic_decim_i_0 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), + .signal_in(i_decim_0),.signal_out(i_decim_1)); + cic_decim cic_decim_i_1 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), + .signal_in(i_decim_1),.signal_out(i)); + + cic_decim cic_decim_q_0 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), + .signal_in(q_decim_0),.signal_out(q_decim_1)); + cic_decim cic_decim_q_1 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), + .signal_in(q_decim_1),.signal_out(q)); + + assign strobe_out = strobe_1; + + biquad_2stage iir_i (.clock(clock),.reset(reset),.strobe_in(strobe_1), + .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), + .sample_in(i),.sample_out(i_filt),.debugbus(debugbus)); + + biquad_2stage iir_q (.clock(clock),.reset(reset),.strobe_in(strobe_1), + .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), + .sample_in(q),.sample_out(q_filt),.debugbus()); + + mrfm_compensator compensator (.clock(clock),.reset(reset),.strobe_in(strobe_1), + .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), + .i_in(i_filt),.q_in(q_filt),.i_out(i_comp),.q_out(q_comp)); + + cic_interp cic_interp_i_0 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), + .signal_in(i_comp),.signal_out(i_interp_0)); + cic_interp cic_interp_i_1 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), + .signal_in(i_interp_0),.signal_out(i_interp_1)); + + cic_interp cic_interp_q_0 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), + .signal_in(q_comp),.signal_out(q_interp_0)); + cic_interp cic_interp_q_1 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), + .signal_in(q_interp_0),.signal_out(q_interp_1)); + + cordic tx_cordic (.clock(clock),.reset(reset),.enable(enable), + .xi(i_interp_1),.yi(q_interp_1),.zi(-phase[31:16]), + .xo(signal_out),.yo(),.zo() ); + +endmodule // mrfm_proc diff --git a/toplevel/mrfm/shifter.v b/toplevel/mrfm/shifter.v new file mode 100644 index 000000000..08d49db6e --- /dev/null +++ b/toplevel/mrfm/shifter.v @@ -0,0 +1,106 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2005,2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +module shifter(input wire [33:0] in, output wire [15:0] out, input wire [7:0] shift); + // Wish we could do assign out = in[15+shift:shift]; + + reg [15:0] quotient, remainder; + wire [15:0] out_unclipped; + reg [18:0] msbs; + wire in_range; + + always @* + case(shift) + 0 : quotient = in[15:0]; + 1 : quotient = in[16:1]; + 2 : quotient = in[17:2]; + 3 : quotient = in[18:3]; + 4 : quotient = in[19:4]; + 5 : quotient = in[20:5]; + 6 : quotient = in[21:6]; + 7 : quotient = in[22:7]; + 8 : quotient = in[23:8]; + 9 : quotient = in[24:9]; + 10 : quotient = in[25:10]; + 11 : quotient = in[26:11]; + 12 : quotient = in[27:12]; + 13 : quotient = in[28:13]; + 14 : quotient = in[29:14]; + 15 : quotient = in[30:15]; + 16 : quotient = in[31:16]; + 17 : quotient = in[32:17]; + 18 : quotient = in[33:18]; + default : quotient = in[15:0]; + endcase // case(shift) + + always @* + case(shift) + 0 : remainder = 16'b0; + 1 : remainder = {in[0],15'b0}; + 2 : remainder = {in[1:0],14'b0}; + 3 : remainder = {in[2:0],13'b0}; + 4 : remainder = {in[3:0],12'b0}; + 5 : remainder = {in[4:0],11'b0}; + 6 : remainder = {in[5:0],10'b0}; + 7 : remainder = {in[6:0],9'b0}; + 8 : remainder = {in[7:0],8'b0}; + 9 : remainder = {in[8:0],7'b0}; + 10 : remainder = {in[9:0],6'b0}; + 11 : remainder = {in[10:0],5'b0}; + 12 : remainder = {in[11:0],4'b0}; + 13 : remainder = {in[12:0],3'b0}; + 14 : remainder = {in[13:0],2'b0}; + 15 : remainder = {in[14:0],1'b0}; + 16 : remainder = in[15:0]; + 17 : remainder = in[16:1]; + 18 : remainder = in[17:2]; + default : remainder = 16'b0; + endcase // case(shift) + + always @* + case(shift) + 0 : msbs = in[33:15]; + 1 : msbs = {in[33],in[33:16]}; + 2 : msbs = {{2{in[33]}},in[33:17]}; + 3 : msbs = {{3{in[33]}},in[33:18]}; + 4 : msbs = {{4{in[33]}},in[33:19]}; + 5 : msbs = {{5{in[33]}},in[33:20]}; + 6 : msbs = {{6{in[33]}},in[33:21]}; + 7 : msbs = {{7{in[33]}},in[33:22]}; + 8 : msbs = {{8{in[33]}},in[33:23]}; + 9 : msbs = {{9{in[33]}},in[33:24]}; + 10 : msbs = {{10{in[33]}},in[33:25]}; + 11 : msbs = {{11{in[33]}},in[33:26]}; + 12 : msbs = {{12{in[33]}},in[33:27]}; + 13 : msbs = {{13{in[33]}},in[33:28]}; + 14 : msbs = {{14{in[33]}},in[33:29]}; + 15 : msbs = {{15{in[33]}},in[33:30]}; + 16 : msbs = {{16{in[33]}},in[33:31]}; + 17 : msbs = {{17{in[33]}},in[33:32]}; + 18 : msbs = {{18{in[33]}},in[33]}; + default : msbs = in[33:15]; + endcase // case(shift) + + assign in_range = &msbs | ~(|msbs); + assign out_unclipped = quotient + (in[33] & |remainder); + assign out = in_range ? out_unclipped : {in[33],{15{~in[33]}}}; + +endmodule // shifter diff --git a/toplevel/sizetest/sizetest.csf b/toplevel/sizetest/sizetest.csf new file mode 100644 index 000000000..4b724e7f5 --- /dev/null +++ b/toplevel/sizetest/sizetest.csf @@ -0,0 +1,160 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = OFF; + OPTIMIZE_TIMING = OFF; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = ON; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |sizetest; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +CHIP(sizetest) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} diff --git a/toplevel/sizetest/sizetest.psf b/toplevel/sizetest/sizetest.psf new file mode 100644 index 000000000..e4fc6aa27 --- /dev/null +++ b/toplevel/sizetest/sizetest.psf @@ -0,0 +1,228 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + STRATIX_CARRY_CHAIN_LENGTH = 70; + AUTO_PACKED_REG_CYCLONE = "MINIMIZE AREA WITH CHAINS"; + CYCLONE_OPTIMIZATION_TECHNIQUE = SPEED; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_CLOCK = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + IGNORE_SOFT_BUFFERS = ON; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(sizetest) +{ + USER_LIBRARIES = "e:\fpga\megacells\"; + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "22:00:25 SEPTEMBER 28, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; +} +THIRD_PARTY_EDA_TOOLS(sizetest) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} diff --git a/toplevel/sizetest/sizetest.quartus b/toplevel/sizetest/sizetest.quartus new file mode 100644 index 000000000..d1eaf227a --- /dev/null +++ b/toplevel/sizetest/sizetest.quartus @@ -0,0 +1,19 @@ +COMPILER_SETTINGS_LIST +{ + COMPILER_SETTINGS = sizetest; +} +SIMULATOR_SETTINGS_LIST +{ + SIMULATOR_SETTINGS = sizetest; +} +SOFTWARE_SETTINGS_LIST +{ + SOFTWARE_SETTINGS = Debug; + SOFTWARE_SETTINGS = Release; +} +FILES +{ + VERILOG_FILE = ..\..\sdr_lib\cordic_stage.v; + VERILOG_FILE = ..\..\sdr_lib\cordic.v; + VERILOG_FILE = sizetest.v; +} diff --git a/toplevel/sizetest/sizetest.ssf b/toplevel/sizetest/sizetest.ssf new file mode 100644 index 000000000..1aceab1f1 --- /dev/null +++ b/toplevel/sizetest/sizetest.ssf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = sizetest; +} diff --git a/toplevel/sizetest/sizetest.v b/toplevel/sizetest/sizetest.v new file mode 100644 index 000000000..cdbd0861a --- /dev/null +++ b/toplevel/sizetest/sizetest.v @@ -0,0 +1,39 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + + +module sizetest(input clock, + input reset, + input enable, + input [15:0]xi, + input [15:0] yi, + input [15:0] zi, + output [15:0] xo, + output [15:0] yo, + output [15:0] zo +// input [15:0] constant + ); + +wire [16:0] zo; + +cordic_stage cordic_stage(clock, reset, enable, xi, yi, zi, 16'd16383, xo, yo, zo ); + +endmodule diff --git a/toplevel/usrp_multi/usrp_multi.csf b/toplevel/usrp_multi/usrp_multi.csf new file mode 100644 index 000000000..2f5df2bca --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi.csf @@ -0,0 +1,444 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; + OPTIMIZE_TIMING = "NORMAL COMPILATION"; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = OFF; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |usrp_multi; + ROUTING_BACK_ANNOTATION_MODE = OFF; + INC_PLC_MODE = OFF; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} +CHIP(usrp_multi) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; + AUTO_RESTART_CONFIGURATION = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + USER_START_UP_CLOCK = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_JTAG_BST_SUPPORT = OFF; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + USE_CONFIGURATION_DEVICE = OFF; + APEX20K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + STRATIX_UPDATE_MODE = STANDARD; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + COMPRESSION_MODE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + GENERATE_TTF_FILE = OFF; + GENERATE_RBF_FILE = ON; + GENERATE_HEX_FILE = OFF; + SECURITY_BIT = OFF; + ENABLE_VREFA_PIN = OFF; + ENABLE_VREFB_PIN = OFF; + GENERATE_SVF_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_JBC_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_HEXOUT_FILE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; + BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; + HEXOUT_FILE_START_ADDRESS = 0; + HEXOUT_FILE_COUNT_DIRECTION = UP; + RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; + STRATIX_DEVICE_IO_STANDARD = LVTTL; + CLOCK_SOURCE = INTERNAL; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CONFIGURATION_CLOCK_DIVISOR = 1; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + SCLK : LOCATION = Pin_101; + SDI : LOCATION = Pin_100; + SEN : LOCATION = Pin_98; + SLD : LOCATION = Pin_95; + adc1_data[0] : LOCATION = Pin_5; + adc1_data[10] : LOCATION = Pin_235; + adc1_data[11] : LOCATION = Pin_234; + adc1_data[1] : LOCATION = Pin_4; + adc1_data[2] : LOCATION = Pin_3; + adc1_data[3] : LOCATION = Pin_2; + adc1_data[4] : LOCATION = Pin_1; + adc1_data[4] : IO_STANDARD = LVTTL; + adc1_data[5] : LOCATION = Pin_240; + adc1_data[6] : LOCATION = Pin_239; + adc1_data[7] : LOCATION = Pin_238; + adc1_data[8] : LOCATION = Pin_237; + adc1_data[9] : LOCATION = Pin_236; + adc2_data[0] : LOCATION = Pin_20; + adc2_data[10] : LOCATION = Pin_8; + adc2_data[11] : LOCATION = Pin_7; + adc2_data[1] : LOCATION = Pin_19; + adc2_data[2] : LOCATION = Pin_18; + adc2_data[3] : LOCATION = Pin_17; + adc2_data[4] : LOCATION = Pin_16; + adc2_data[5] : LOCATION = Pin_15; + adc2_data[6] : LOCATION = Pin_14; + adc2_data[7] : LOCATION = Pin_13; + adc2_data[8] : LOCATION = Pin_12; + adc2_data[9] : LOCATION = Pin_11; + adc3_data[0] : LOCATION = Pin_200; + adc3_data[10] : LOCATION = Pin_184; + adc3_data[11] : LOCATION = Pin_183; + adc3_data[1] : LOCATION = Pin_197; + adc3_data[2] : LOCATION = Pin_196; + adc3_data[3] : LOCATION = Pin_195; + adc3_data[4] : LOCATION = Pin_194; + adc3_data[5] : LOCATION = Pin_193; + adc3_data[6] : LOCATION = Pin_188; + adc3_data[7] : LOCATION = Pin_187; + adc3_data[8] : LOCATION = Pin_186; + adc3_data[9] : LOCATION = Pin_185; + adc4_data[0] : LOCATION = Pin_222; + adc4_data[10] : LOCATION = Pin_203; + adc4_data[11] : LOCATION = Pin_202; + adc4_data[1] : LOCATION = Pin_219; + adc4_data[2] : LOCATION = Pin_217; + adc4_data[3] : LOCATION = Pin_216; + adc4_data[4] : LOCATION = Pin_215; + adc4_data[5] : LOCATION = Pin_214; + adc4_data[6] : LOCATION = Pin_213; + adc4_data[7] : LOCATION = Pin_208; + adc4_data[8] : LOCATION = Pin_207; + adc4_data[9] : LOCATION = Pin_206; + adc_oeb[0] : LOCATION = Pin_228; + adc_oeb[1] : LOCATION = Pin_21; + adc_oeb[2] : LOCATION = Pin_181; + adc_oeb[3] : LOCATION = Pin_218; + adc_otr[0] : LOCATION = Pin_233; + adc_otr[1] : LOCATION = Pin_6; + adc_otr[2] : LOCATION = Pin_182; + adc_otr[3] : LOCATION = Pin_201; + adclk0 : LOCATION = Pin_224; + adclk1 : LOCATION = Pin_226; + clk0 : LOCATION = Pin_28; + clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk0 : IO_STANDARD = LVTTL; + clk1 : LOCATION = Pin_29; + clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk1 : IO_STANDARD = LVTTL; + clk3 : LOCATION = Pin_152; + clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk3 : IO_STANDARD = LVTTL; + clk_120mhz : LOCATION = Pin_153; + clk_120mhz : IO_STANDARD = LVTTL; + clk_out : LOCATION = Pin_63; + clk_out : IO_STANDARD = LVTTL; + dac1_data[0] : LOCATION = Pin_165; + dac1_data[10] : LOCATION = Pin_177; + dac1_data[11] : LOCATION = Pin_178; + dac1_data[12] : LOCATION = Pin_179; + dac1_data[13] : LOCATION = Pin_180; + dac1_data[1] : LOCATION = Pin_166; + dac1_data[2] : LOCATION = Pin_167; + dac1_data[3] : LOCATION = Pin_168; + dac1_data[4] : LOCATION = Pin_169; + dac1_data[5] : LOCATION = Pin_170; + dac1_data[6] : LOCATION = Pin_173; + dac1_data[7] : LOCATION = Pin_174; + dac1_data[8] : LOCATION = Pin_175; + dac1_data[9] : LOCATION = Pin_176; + dac2_data[0] : LOCATION = Pin_159; + dac2_data[10] : LOCATION = Pin_163; + dac2_data[11] : LOCATION = Pin_139; + dac2_data[12] : LOCATION = Pin_164; + dac2_data[13] : LOCATION = Pin_138; + dac2_data[1] : LOCATION = Pin_158; + dac2_data[2] : LOCATION = Pin_160; + dac2_data[3] : LOCATION = Pin_156; + dac2_data[4] : LOCATION = Pin_161; + dac2_data[5] : LOCATION = Pin_144; + dac2_data[6] : LOCATION = Pin_162; + dac2_data[7] : LOCATION = Pin_141; + dac2_data[8] : LOCATION = Pin_143; + dac2_data[9] : LOCATION = Pin_140; + dac3_data[0] : LOCATION = Pin_122; + dac3_data[10] : LOCATION = Pin_134; + dac3_data[11] : LOCATION = Pin_135; + dac3_data[12] : LOCATION = Pin_136; + dac3_data[13] : LOCATION = Pin_137; + dac3_data[1] : LOCATION = Pin_123; + dac3_data[2] : LOCATION = Pin_124; + dac3_data[3] : LOCATION = Pin_125; + dac3_data[4] : LOCATION = Pin_126; + dac3_data[5] : LOCATION = Pin_127; + dac3_data[6] : LOCATION = Pin_128; + dac3_data[7] : LOCATION = Pin_131; + dac3_data[8] : LOCATION = Pin_132; + dac3_data[9] : LOCATION = Pin_133; + dac4_data[0] : LOCATION = Pin_104; + dac4_data[10] : LOCATION = Pin_118; + dac4_data[11] : LOCATION = Pin_119; + dac4_data[12] : LOCATION = Pin_120; + dac4_data[13] : LOCATION = Pin_121; + dac4_data[1] : LOCATION = Pin_105; + dac4_data[2] : LOCATION = Pin_106; + dac4_data[3] : LOCATION = Pin_107; + dac4_data[4] : LOCATION = Pin_108; + dac4_data[5] : LOCATION = Pin_113; + dac4_data[6] : LOCATION = Pin_114; + dac4_data[7] : LOCATION = Pin_115; + dac4_data[8] : LOCATION = Pin_116; + dac4_data[9] : LOCATION = Pin_117; + enable_rx : LOCATION = Pin_88; + enable_tx : LOCATION = Pin_93; + gndbus[0] : LOCATION = Pin_223; + gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[0] : IO_STANDARD = LVTTL; + gndbus[1] : LOCATION = Pin_225; + gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[1] : IO_STANDARD = LVTTL; + gndbus[2] : LOCATION = Pin_227; + gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[2] : IO_STANDARD = LVTTL; + gndbus[3] : LOCATION = Pin_62; + gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[3] : IO_STANDARD = LVTTL; + gndbus[4] : LOCATION = Pin_64; + gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[4] : IO_STANDARD = LVTTL; + misc_pins[0] : LOCATION = Pin_87; + misc_pins[0] : IO_STANDARD = LVTTL; + misc_pins[10] : LOCATION = Pin_76; + misc_pins[10] : IO_STANDARD = LVTTL; + misc_pins[11] : LOCATION = Pin_74; + misc_pins[11] : IO_STANDARD = LVTTL; + misc_pins[1] : LOCATION = Pin_86; + misc_pins[1] : IO_STANDARD = LVTTL; + misc_pins[2] : LOCATION = Pin_85; + misc_pins[2] : IO_STANDARD = LVTTL; + misc_pins[3] : LOCATION = Pin_84; + misc_pins[3] : IO_STANDARD = LVTTL; + misc_pins[4] : LOCATION = Pin_83; + misc_pins[4] : IO_STANDARD = LVTTL; + misc_pins[5] : LOCATION = Pin_82; + misc_pins[5] : IO_STANDARD = LVTTL; + misc_pins[6] : LOCATION = Pin_79; + misc_pins[6] : IO_STANDARD = LVTTL; + misc_pins[7] : LOCATION = Pin_78; + misc_pins[7] : IO_STANDARD = LVTTL; + misc_pins[8] : LOCATION = Pin_77; + misc_pins[8] : IO_STANDARD = LVTTL; + misc_pins[9] : LOCATION = Pin_75; + misc_pins[9] : IO_STANDARD = LVTTL; + reset : LOCATION = Pin_94; + usbclk : LOCATION = Pin_55; + usbctl[0] : LOCATION = Pin_56; + usbctl[1] : LOCATION = Pin_54; + usbctl[2] : LOCATION = Pin_53; + usbctl[3] : LOCATION = Pin_58; + usbctl[4] : LOCATION = Pin_57; + usbctl[5] : LOCATION = Pin_44; + usbdata[0] : LOCATION = Pin_73; + usbdata[10] : LOCATION = Pin_41; + usbdata[11] : LOCATION = Pin_39; + usbdata[12] : LOCATION = Pin_38; + usbdata[12] : IO_STANDARD = LVTTL; + usbdata[13] : LOCATION = Pin_37; + usbdata[14] : LOCATION = Pin_24; + usbdata[15] : LOCATION = Pin_23; + usbdata[1] : LOCATION = Pin_68; + usbdata[2] : LOCATION = Pin_67; + usbdata[3] : LOCATION = Pin_66; + usbdata[4] : LOCATION = Pin_65; + usbdata[5] : LOCATION = Pin_61; + usbdata[6] : LOCATION = Pin_60; + usbdata[7] : LOCATION = Pin_59; + usbdata[8] : LOCATION = Pin_43; + usbdata[9] : LOCATION = Pin_42; + usbrdy[0] : LOCATION = Pin_45; + usbrdy[1] : LOCATION = Pin_46; + usbrdy[2] : LOCATION = Pin_47; + usbrdy[3] : LOCATION = Pin_48; + usbrdy[4] : LOCATION = Pin_49; + usbrdy[5] : LOCATION = Pin_50; + clear_status : LOCATION = Pin_99; +} diff --git a/toplevel/usrp_multi/usrp_multi.esf b/toplevel/usrp_multi/usrp_multi.esf new file mode 100644 index 000000000..df45f676b --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi.esf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = usrp_multi; +} diff --git a/toplevel/usrp_multi/usrp_multi.psf b/toplevel/usrp_multi/usrp_multi.psf new file mode 100644 index 000000000..68c2d12f9 --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi.psf @@ -0,0 +1,312 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_DSP_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_TURBO_BIT = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_PARALLEL_EXPANDERS = ON; + AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; + AUTO_FAST_OUTPUT_REGISTERS = OFF; + AUTO_FAST_INPUT_REGISTERS = OFF; + AUTO_CASCADE_CHAINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; + PARALLEL_EXPANDER_CHAIN_LENGTH = 16; + CASCADE_CHAIN_LENGTH = 2; + STRATIX_CARRY_CHAIN_LENGTH = 70; + MERCURY_CARRY_CHAIN_LENGTH = 48; + FLEX10K_CARRY_CHAIN_LENGTH = 32; + FLEX6K_CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN_LENGTH = 48; + CARRY_OUT_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + AUTO_LCELL_INSERTION = ON; + ALLOW_XOR_GATE_USAGE = ON; + AUTO_PACKED_REGISTERS_STRATIX = NORMAL; + AUTO_PACKED_REGISTERS = OFF; + AUTO_PACKED_REG_CYCLONE = NORMAL; + FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; + FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; + MERCURY_OPTIMIZATION_TECHNIQUE = AREA; + APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; + MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; + STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; + CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; + FLEX10K_TECHNOLOGY_MAPPER = LUT; + FLEX6K_TECHNOLOGY_MAPPER = LUT; + MERCURY_TECHNOLOGY_MAPPER = LUT; + APEX20K_TECHNOLOGY_MAPPER = LUT; + MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; + STRATIX_TECHNOLOGY_MAPPER = LUT; + AUTO_IMPLEMENT_IN_ROM = OFF; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_CLOCK = ON; + USE_LPM_FOR_AHDL_OPERATORS = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + TURBO_BIT = ON; + MAX7000_IGNORE_SOFT_BUFFERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MAX7000_IGNORE_LCELL_BUFFERS = AUTO; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + DSP_BLOCK_BALANCING = AUTO; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(usrp_multi) +{ + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; + USER_LIBRARIES = "e:\usrp\fpga\megacells"; +} +THIRD_PARTY_EDA_TOOLS(usrp_multi) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} +CLOCK(clk_120mhz) +{ + FMAX_REQUIREMENT = "120.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(usbclk) +{ + FMAX_REQUIREMENT = "48.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(SCLK) +{ + FMAX_REQUIREMENT = "1.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk0) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk1) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} diff --git a/toplevel/usrp_multi/usrp_multi.qpf b/toplevel/usrp_multi/usrp_multi.qpf new file mode 100644 index 000000000..1524de1bb --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi.qpf @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2004 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.0" +DATE = "17:10:11 December 20, 2004" + + +# Active Revisions + +PROJECT_REVISION = "usrp_multi" diff --git a/toplevel/usrp_multi/usrp_multi.qsf b/toplevel/usrp_multi/usrp_multi.qsf new file mode 100644 index 000000000..e45c683af --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi.qsf @@ -0,0 +1,408 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# usrp_multi_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" +set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1" + +# Pin & Location Assignments +# ========================== +set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" +set_location_assignment PIN_29 -to SCLK +set_location_assignment PIN_117 -to SDI +set_location_assignment PIN_28 -to usbclk +set_location_assignment PIN_107 -to usbctl[0] +set_location_assignment PIN_106 -to usbctl[1] +set_location_assignment PIN_105 -to usbctl[2] +set_location_assignment PIN_100 -to usbdata[0] +set_location_assignment PIN_84 -to usbdata[10] +set_location_assignment PIN_83 -to usbdata[11] +set_location_assignment PIN_82 -to usbdata[12] +set_location_assignment PIN_79 -to usbdata[13] +set_location_assignment PIN_78 -to usbdata[14] +set_location_assignment PIN_77 -to usbdata[15] +set_location_assignment PIN_99 -to usbdata[1] +set_location_assignment PIN_98 -to usbdata[2] +set_location_assignment PIN_95 -to usbdata[3] +set_location_assignment PIN_94 -to usbdata[4] +set_location_assignment PIN_93 -to usbdata[5] +set_location_assignment PIN_88 -to usbdata[6] +set_location_assignment PIN_87 -to usbdata[7] +set_location_assignment PIN_86 -to usbdata[8] +set_location_assignment PIN_85 -to usbdata[9] +set_location_assignment PIN_104 -to usbrdy[0] +set_location_assignment PIN_101 -to usbrdy[1] +set_location_assignment PIN_76 -to FX2_1 +set_location_assignment PIN_75 -to FX2_2 +set_location_assignment PIN_74 -to FX2_3 +set_location_assignment PIN_116 -to io_rx_a[0] +set_location_assignment PIN_115 -to io_rx_a[1] +set_location_assignment PIN_114 -to io_rx_a[2] +set_location_assignment PIN_113 -to io_rx_a[3] +set_location_assignment PIN_108 -to io_rx_a[4] +set_location_assignment PIN_195 -to io_rx_a[5] +set_location_assignment PIN_196 -to io_rx_a[6] +set_location_assignment PIN_197 -to io_rx_a[7] +set_location_assignment PIN_200 -to io_rx_a[8] +set_location_assignment PIN_201 -to io_rx_a[9] +set_location_assignment PIN_202 -to io_rx_a[10] +set_location_assignment PIN_203 -to io_rx_a[11] +set_location_assignment PIN_206 -to io_rx_a[12] +set_location_assignment PIN_207 -to io_rx_a[13] +set_location_assignment PIN_208 -to io_rx_a[14] +set_location_assignment PIN_214 -to io_rx_b[0] +set_location_assignment PIN_215 -to io_rx_b[1] +set_location_assignment PIN_216 -to io_rx_b[2] +set_location_assignment PIN_217 -to io_rx_b[3] +set_location_assignment PIN_218 -to io_rx_b[4] +set_location_assignment PIN_219 -to io_rx_b[5] +set_location_assignment PIN_222 -to io_rx_b[6] +set_location_assignment PIN_223 -to io_rx_b[7] +set_location_assignment PIN_224 -to io_rx_b[8] +set_location_assignment PIN_225 -to io_rx_b[9] +set_location_assignment PIN_226 -to io_rx_b[10] +set_location_assignment PIN_227 -to io_rx_b[11] +set_location_assignment PIN_228 -to io_rx_b[12] +set_location_assignment PIN_233 -to io_rx_b[13] +set_location_assignment PIN_234 -to io_rx_b[14] +set_location_assignment PIN_175 -to io_tx_a[0] +set_location_assignment PIN_176 -to io_tx_a[1] +set_location_assignment PIN_177 -to io_tx_a[2] +set_location_assignment PIN_178 -to io_tx_a[3] +set_location_assignment PIN_179 -to io_tx_a[4] +set_location_assignment PIN_180 -to io_tx_a[5] +set_location_assignment PIN_181 -to io_tx_a[6] +set_location_assignment PIN_182 -to io_tx_a[7] +set_location_assignment PIN_183 -to io_tx_a[8] +set_location_assignment PIN_184 -to io_tx_a[9] +set_location_assignment PIN_185 -to io_tx_a[10] +set_location_assignment PIN_186 -to io_tx_a[11] +set_location_assignment PIN_187 -to io_tx_a[12] +set_location_assignment PIN_188 -to io_tx_a[13] +set_location_assignment PIN_193 -to io_tx_a[14] +set_location_assignment PIN_73 -to io_tx_b[0] +set_location_assignment PIN_68 -to io_tx_b[1] +set_location_assignment PIN_67 -to io_tx_b[2] +set_location_assignment PIN_66 -to io_tx_b[3] +set_location_assignment PIN_65 -to io_tx_b[4] +set_location_assignment PIN_64 -to io_tx_b[5] +set_location_assignment PIN_63 -to io_tx_b[6] +set_location_assignment PIN_62 -to io_tx_b[7] +set_location_assignment PIN_61 -to io_tx_b[8] +set_location_assignment PIN_60 -to io_tx_b[9] +set_location_assignment PIN_59 -to io_tx_b[10] +set_location_assignment PIN_58 -to io_tx_b[11] +set_location_assignment PIN_57 -to io_tx_b[12] +set_location_assignment PIN_56 -to io_tx_b[13] +set_location_assignment PIN_55 -to io_tx_b[14] +set_location_assignment PIN_152 -to master_clk +set_location_assignment PIN_144 -to rx_a_a[0] +set_location_assignment PIN_143 -to rx_a_a[1] +set_location_assignment PIN_141 -to rx_a_a[2] +set_location_assignment PIN_140 -to rx_a_a[3] +set_location_assignment PIN_139 -to rx_a_a[4] +set_location_assignment PIN_138 -to rx_a_a[5] +set_location_assignment PIN_137 -to rx_a_a[6] +set_location_assignment PIN_136 -to rx_a_a[7] +set_location_assignment PIN_135 -to rx_a_a[8] +set_location_assignment PIN_134 -to rx_a_a[9] +set_location_assignment PIN_133 -to rx_a_a[10] +set_location_assignment PIN_132 -to rx_a_a[11] +set_location_assignment PIN_23 -to rx_a_b[0] +set_location_assignment PIN_21 -to rx_a_b[1] +set_location_assignment PIN_20 -to rx_a_b[2] +set_location_assignment PIN_19 -to rx_a_b[3] +set_location_assignment PIN_18 -to rx_a_b[4] +set_location_assignment PIN_17 -to rx_a_b[5] +set_location_assignment PIN_16 -to rx_a_b[6] +set_location_assignment PIN_15 -to rx_a_b[7] +set_location_assignment PIN_14 -to rx_a_b[8] +set_location_assignment PIN_13 -to rx_a_b[9] +set_location_assignment PIN_12 -to rx_a_b[10] +set_location_assignment PIN_11 -to rx_a_b[11] +set_location_assignment PIN_131 -to rx_b_a[0] +set_location_assignment PIN_128 -to rx_b_a[1] +set_location_assignment PIN_127 -to rx_b_a[2] +set_location_assignment PIN_126 -to rx_b_a[3] +set_location_assignment PIN_125 -to rx_b_a[4] +set_location_assignment PIN_124 -to rx_b_a[5] +set_location_assignment PIN_123 -to rx_b_a[6] +set_location_assignment PIN_122 -to rx_b_a[7] +set_location_assignment PIN_121 -to rx_b_a[8] +set_location_assignment PIN_120 -to rx_b_a[9] +set_location_assignment PIN_119 -to rx_b_a[10] +set_location_assignment PIN_118 -to rx_b_a[11] +set_location_assignment PIN_8 -to rx_b_b[0] +set_location_assignment PIN_7 -to rx_b_b[1] +set_location_assignment PIN_6 -to rx_b_b[2] +set_location_assignment PIN_5 -to rx_b_b[3] +set_location_assignment PIN_4 -to rx_b_b[4] +set_location_assignment PIN_3 -to rx_b_b[5] +set_location_assignment PIN_2 -to rx_b_b[6] +set_location_assignment PIN_240 -to rx_b_b[7] +set_location_assignment PIN_239 -to rx_b_b[8] +set_location_assignment PIN_238 -to rx_b_b[9] +set_location_assignment PIN_237 -to rx_b_b[10] +set_location_assignment PIN_236 -to rx_b_b[11] +set_location_assignment PIN_156 -to SDO +set_location_assignment PIN_153 -to SEN_FPGA +set_location_assignment PIN_159 -to tx_a[0] +set_location_assignment PIN_160 -to tx_a[1] +set_location_assignment PIN_161 -to tx_a[2] +set_location_assignment PIN_162 -to tx_a[3] +set_location_assignment PIN_163 -to tx_a[4] +set_location_assignment PIN_164 -to tx_a[5] +set_location_assignment PIN_165 -to tx_a[6] +set_location_assignment PIN_166 -to tx_a[7] +set_location_assignment PIN_167 -to tx_a[8] +set_location_assignment PIN_168 -to tx_a[9] +set_location_assignment PIN_169 -to tx_a[10] +set_location_assignment PIN_170 -to tx_a[11] +set_location_assignment PIN_173 -to tx_a[12] +set_location_assignment PIN_174 -to tx_a[13] +set_location_assignment PIN_38 -to tx_b[0] +set_location_assignment PIN_39 -to tx_b[1] +set_location_assignment PIN_41 -to tx_b[2] +set_location_assignment PIN_42 -to tx_b[3] +set_location_assignment PIN_43 -to tx_b[4] +set_location_assignment PIN_44 -to tx_b[5] +set_location_assignment PIN_45 -to tx_b[6] +set_location_assignment PIN_46 -to tx_b[7] +set_location_assignment PIN_47 -to tx_b[8] +set_location_assignment PIN_48 -to tx_b[9] +set_location_assignment PIN_49 -to tx_b[10] +set_location_assignment PIN_50 -to tx_b[11] +set_location_assignment PIN_53 -to tx_b[12] +set_location_assignment PIN_54 -to tx_b[13] +set_location_assignment PIN_158 -to TXSYNC_A +set_location_assignment PIN_37 -to TXSYNC_B +set_location_assignment PIN_235 -to io_rx_b[15] +set_location_assignment PIN_24 -to io_tx_b[15] +set_location_assignment PIN_213 -to io_rx_a[15] +set_location_assignment PIN_194 -to io_tx_a[15] +set_location_assignment PIN_1 -to MYSTERY_SIGNAL + +# Timing Assignments +# ================== +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name TOP_LEVEL_ENTITY usrp_multi +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name USER_LIBRARIES "H:\\usrp-for2.7\\fpga\\megacells" +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name INC_PLC_MODE OFF +set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF +set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# Timing Analysis Assignments +# =========================== +set_global_assignment -name MAX_SCC_SIZE 50 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF + +# Simulator Assignments +# ===================== +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "1 ns" + +# Design Assistant Assignments +# ============================ +set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF +set_global_assignment -name ASSG_CAT OFF +set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF +set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF +set_global_assignment -name CLK_CAT OFF +set_global_assignment -name CLK_RULE_COMB_CLOCK OFF +set_global_assignment -name CLK_RULE_INV_CLOCK OFF +set_global_assignment -name CLK_RULE_GATING_SCHEME OFF +set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF +set_global_assignment -name CLK_RULE_MIX_EDGES OFF +set_global_assignment -name RESET_CAT OFF +set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name TIMING_CAT OFF +set_global_assignment -name TIMING_RULE_SHIFT_REG OFF +set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF +set_global_assignment -name NONSYNCHSTRUCT_CAT OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF +set_global_assignment -name SIGNALRACE_CAT OFF +set_global_assignment -name ACLK_CAT OFF +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF +set_global_assignment -name HCPY_CAT OFF +set_global_assignment -name HCPY_VREF_PINS OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name HUB_ENTITY_NAME SLD_HUB +set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST +set_global_assignment -name ENABLE_SIGNALTAP Off + +# LogicLock Region Assignments +# ============================ +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF + +# ----------------- +# start CLOCK(SCLK) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK + set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK + set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK + +# end CLOCK(SCLK) +# --------------- + +# ----------------------- +# start CLOCK(master_clk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk + set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk + set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk + +# end CLOCK(master_clk) +# --------------------- + +# ------------------- +# start CLOCK(usbclk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk + set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk + set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk + +# end CLOCK(usbclk) +# ----------------- + +# ---------------------- +# start ENTITY(usrp_multi) + + # Timing Assignments + # ================== + set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK + set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk + set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk + +# end ENTITY(usrp_multi) +# -------------------- + + +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg_masked.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control_multi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v +set_global_assignment -name VERILOG_FILE usrp_multi.vh +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v +set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v +set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v +set_global_assignment -name VERILOG_FILE usrp_multi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file diff --git a/toplevel/usrp_multi/usrp_multi.v b/toplevel/usrp_multi/usrp_multi.v new file mode 100644 index 000000000..b27d3d3a6 --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi.v @@ -0,0 +1,379 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2004,2005,2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// Top level module for a full setup with DUCs and DDCs + +// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins +// for debugging info. NB, This can kill the m'board and/or d'board if you +// have anything except basic d'boards installed. + +// Uncomment the following to include optional circuitry + +`include "usrp_multi.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module usrp_multi +(output MYSTERY_SIGNAL, + input master_clk, + input SCLK, + input SDI, + inout SDO, + input SEN_FPGA, + + input FX2_1, + output FX2_2, + output FX2_3, + + input wire [11:0] rx_a_a, + input wire [11:0] rx_b_a, + input wire [11:0] rx_a_b, + input wire [11:0] rx_b_b, + + output wire [13:0] tx_a, + output wire [13:0] tx_b, + + output wire TXSYNC_A, + output wire TXSYNC_B, + + // USB interface + input usbclk, + input wire [2:0] usbctl, + output wire [1:0] usbrdy, + inout [15:0] usbdata, // NB Careful, inout + + // These are the general purpose i/o's that go to the daughterboard slots + inout wire [15:0] io_tx_a, + inout wire [15:0] io_tx_b, + inout wire [15:0] io_rx_a, + inout wire [15:0] io_rx_b + ); + wire [15:0] debugdata,debugctrl; + assign MYSTERY_SIGNAL = 1'b0; + + wire clk64,clk128; + + wire WR = usbctl[0]; + wire RD = usbctl[1]; + wire OE = usbctl[2]; + + wire have_space, have_pkt_rdy; + assign usbrdy[0] = have_space; + assign usbrdy[1] = have_pkt_rdy; + + wire tx_underrun, rx_overrun; + wire clear_status = FX2_1; + assign FX2_2 = rx_overrun; + assign FX2_3 = tx_underrun; + + wire [15:0] usbdata_out; + + wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; + + wire tx_realsignals; + wire [3:0] rx_numchan; + wire [2:0] tx_numchan; + + wire [7:0] interp_rate, decim_rate; + wire [15:0] tx_debugbus, rx_debugbus; + + wire enable_tx, enable_rx; + wire reset_data; +`ifdef MULTI_ON + wire sync_rx; + assign reset_data = sync_rx; +`else + assign reset_data = 1'b0; +`endif // `ifdef MULTI_ON + + wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; + wire [7:0] settings; + + // Tri-state bus macro + bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); + + assign clk64 = master_clk; + + wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; + wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; + + // TX + wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; + wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; + + wire strobe_interp, tx_sample_strobe; + wire tx_empty; + + wire serial_strobe; + wire [6:0] serial_addr; + wire [31:0] serial_data; + + reg [15:0] debug_counter; +`ifdef COUNTER_32BIT_ON + reg [31:0] sample_counter_32bit; +`endif // `ifdef COUNTER_32BIT_ON + reg [15:0] loopback_i_0,loopback_q_0; + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Transmit Side +`ifdef TX_ON + assign bb_tx_i0 = ch0tx; + assign bb_tx_q0 = ch1tx; + assign bb_tx_i1 = ch2tx; + assign bb_tx_q1 = ch3tx; + + tx_buffer tx_buffer + ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), + .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), + .channels({tx_numchan,1'b0}), + .tx_i_0(ch0tx),.tx_q_0(ch1tx), + .tx_i_1(ch2tx),.tx_q_1(ch3tx), + .tx_i_2(),.tx_q_2(), + .tx_i_3(),.tx_q_3(), + .txclk(clk64),.txstrobe(strobe_interp), + .clear_status(clear_status), + .tx_empty(tx_empty), + .debugbus(tx_debugbus) ); + + tx_chain tx_chain_0 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); + + tx_chain tx_chain_1 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); + + setting_reg #(`FR_TX_MUX) + sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; + + wire txsync = tx_sample_strobe; + assign TXSYNC_A = txsync; + assign TXSYNC_B = txsync; + + assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; + assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; +`endif // `ifdef TX_ON + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Receive Side +`ifdef RX_ON + wire rx_sample_strobe,strobe_decim,hb_strobe; + wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, + bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; + + wire loopback = settings[0]; + wire counter = settings[1]; +`ifdef COUNTER_32BIT_ON + wire counter_32bit = settings[2]; + + always @(posedge clk64) + if(rx_dsp_reset) + sample_counter_32bit <= #1 32'd0; + else if(~enable_rx | reset_data) + sample_counter_32bit <=#1 32'd0; + else if(hb_strobe) + sample_counter_32bit <=#1 sample_counter_32bit + 32'd1; +`endif // `ifdef COUNTER_32BIT_ON + + always @(posedge clk64) + if(rx_dsp_reset) + debug_counter <= #1 16'd0; + else if(~enable_rx) + debug_counter <= #1 16'd0; + else if(hb_strobe) + debug_counter <=#1 debug_counter + 16'd2; + + always @(posedge clk64) + if(strobe_interp) + begin + loopback_i_0 <= #1 ch0tx; + loopback_q_0 <= #1 ch1tx; + end + +`ifdef COUNTER_32BIT_ON + assign ch0rx = counter_32bit?sample_counter_32bit[31:16]:counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; + assign ch1rx = counter_32bit?sample_counter_32bit[15:0]:counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; + assign ch2rx = bb_rx_i1; + assign ch3rx = bb_rx_q1; + assign ch4rx = counter_32bit?bb_rx_i0:bb_rx_i2; + assign ch5rx = counter_32bit?bb_rx_q0:bb_rx_q2;// If using counter replicate channels here to be able to get rx_i0 when using counter + //This means if you use 4 channels that channel 3 will be replaced by channel 0 + // and channel 0 will output the 32 bit counter. + assign ch6rx = bb_rx_i3; + assign ch7rx = bb_rx_q3; +`else + assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; + assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; + assign ch2rx = bb_rx_i1; + assign ch3rx = bb_rx_q1; + assign ch4rx = bb_rx_i2; + assign ch5rx = bb_rx_q2; + assign ch6rx = bb_rx_i3; + assign ch7rx = bb_rx_q3; +`endif // `ifdef COUNTER_32BIT_ON + + + wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; + adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), + .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), + .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), + .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), + .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); + + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset | reset_data), + .reset_regs(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(ch0rx),.ch_1(ch1rx), + .ch_2(ch2rx),.ch_3(ch3rx), + .ch_4(ch4rx),.ch_5(ch5rx), + .ch_6(ch6rx),.ch_7(ch7rx), + .rxclk(clk64),.rxstrobe(hb_strobe), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .debugbus(rx_debugbus) ); + + `ifdef RX_EN_0 + rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 + ( .clock(clk64),.reset(reset_data),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); + `else + assign bb_rx_i0=16'd0; + assign bb_rx_q0=16'd0; + `endif + + `ifdef RX_EN_1 + rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 + ( .clock(clk64),.reset(reset_data),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); + `else + assign bb_rx_i1=16'd0; + assign bb_rx_q1=16'd0; + `endif + + `ifdef RX_EN_2 + rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 + ( .clock(clk64),.reset(reset_data),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); + `else + assign bb_rx_i2=16'd0; + assign bb_rx_q2=16'd0; + `endif + + `ifdef RX_EN_3 + rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 + ( .clock(clk64),.reset(reset_data),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); + assign bb_rx_i3=16'd0; + assign bb_rx_q3=16'd0; + `endif + +`endif // `ifdef RX_ON + + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Control Functions + + wire [31:0] capabilities; + assign capabilities[7] = `TX_CAP_HB; + assign capabilities[6:4] = `TX_CAP_NCHAN; + assign capabilities[3] = `RX_CAP_HB; + assign capabilities[2:0] = `RX_CAP_NCHAN; + + + serial_io serial_io + ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), + .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) ); + + wire [15:0] reg_0,reg_1,reg_2,reg_3; + +`ifdef MULTI_ON + + master_control_multi master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .rx_slave_sync(io_rx_a[`bitnoFR_RX_SYNC_INPUT_IOPIN]), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .sync_rx(sync_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + //.debug_0(rx_a_a),.debug_1(ddc0_in_i), + .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + +`else //`ifdef MULTI_ON + + master_control master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + //.debug_0(rx_a_a),.debug_1(ddc0_in_i), + .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + +`endif //`ifdef MULTI_ON + + io_pins io_pins + (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Misc Settings + setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); + +endmodule // usrp_multi diff --git a/toplevel/usrp_multi/usrp_multi.vh b/toplevel/usrp_multi/usrp_multi.vh new file mode 100644 index 000000000..2904a9352 --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi.vh @@ -0,0 +1,141 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// ==================================================================== +// User control over what parts get included +// +// >>>> EDIT ONLY THIS SECTION <<<< +// Uncomment only ONE configuration +// ==================================================================== + +// ==== Multi usrp configurations ==== +// Uncomment this for multi with 2 rx channels (w/ halfband) & 2 transmit channels +`include "usrp_multi_config_2rxhb_2tx.vh" + +// Uncomment this for multi with 4 rx channels (w/o halfband) & 0 transmit channels +//`include "usrp_multi_config_4rx_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels +//`include "usrp_multi_config_2rxhb_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels +//`include "usrp_multi_config_2rx_0tx.vh" + +// ==== Standard configurations (no multi support) ==== +// Uncomment this for standard with 2 rx channels (w/ halfband) & 2 transmit channels +// `include "../usrp_std/usrp_std_config_2rxhb_2tx.vh" + +// Uncomment this for standard with 4 rx channels (w/o halfband) & 0 transmit channels +//`include "../usrp_std/usrp_std_config_4rx_0tx.vh" + +// Add other "known to fit" configurations here... + +// ==================================================================== +// +// >>>> DO NOT EDIT BELOW HERE <<<< +// +// [The stuff from here down is derived from the stuff included above] +// +// N.B., *all* the remainder of the code should be conditionalized +// only in terms of: +// +// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB, +// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB, +// RX_NCO_ON, RX_CIC_ON +// ==================================================================== +`ifdef MULTI_ON + `define COUNTER_32BIT_ON +`endif + +`ifdef TX_ON + + `ifdef TX_SINGLE + `define TX_EN_0 + `define TX_CAP_NCHAN 3'd1 + `endif + + `ifdef TX_DUAL + `define TX_EN_0 + `define TX_EN_1 + `define TX_CAP_NCHAN 3'd2 + `endif + + `ifdef TX_QUAD + `define TX_EN_0 + `define TX_EN_1 + `define TX_EN_2 + `define TX_EN_3 + `define TX_CAP_NCHAN 3'd4 + `endif + + `ifdef TX_HB_ON + `define TX_CAP_HB 1 + `else + `define TX_CAP_HB 0 + `endif + +`else // !ifdef TX_ON + + `define TX_CAP_NCHAN 3'd0 + `define TX_CAP_HB 0 + +`endif // !ifdef TX_ON + +// -------------------------------------------------------------------- + +`ifdef RX_ON + + `ifdef RX_SINGLE + `define RX_EN_0 + `define RX_CAP_NCHAN 3'd1 + `endif + + `ifdef RX_DUAL + `define RX_EN_0 + `define RX_EN_1 + `ifdef MULTI_ON + `define RX_CAP_NCHAN 3'd4 + `else + `define RX_CAP_NCHAN 3'd2 + `endif + `endif + + `ifdef RX_QUAD + `define RX_EN_0 + `define RX_EN_1 + `define RX_EN_2 + `define RX_EN_3 + `define RX_CAP_NCHAN 3'd4 + `endif + + `ifdef RX_HB_ON + `define RX_CAP_HB 1 + `else + `define RX_CAP_HB 0 + `endif + +`else // !ifdef RX_ON + + `define RX_CAP_NCHAN 3'd0 + `define RX_CAP_HB 0 + +`endif // !ifdef RX_ON diff --git a/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh new file mode 100644 index 000000000..26a41e4d0 --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh @@ -0,0 +1,62 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// +`define MULTI_ON +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_DUAL is currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE +`define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter +//`define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh new file mode 100644 index 000000000..0673d9600 --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh @@ -0,0 +1,62 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// +`define MULTI_ON +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_DUAL is currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE + `define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh new file mode 100644 index 000000000..80c7fbdcb --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh @@ -0,0 +1,62 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// +`define MULTI_ON +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built + `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_DUAL is currently valid] +//`define TX_SINGLE + `define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE + `define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh new file mode 100644 index 000000000..36176be4a --- /dev/null +++ b/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh @@ -0,0 +1,62 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// +`define MULTI_ON +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_DUAL is currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE +//`define RX_DUAL + `define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter +//`define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/usrp_multi/usrp_std.vh b/toplevel/usrp_multi/usrp_std.vh new file mode 100644 index 000000000..189cf14b8 --- /dev/null +++ b/toplevel/usrp_multi/usrp_std.vh @@ -0,0 +1,29 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// ==================================================================== +// Do not remove or edit this file. +// This is a redirect to usrp_multi.vh +// This is needed because some common source files have a +// hardcoded `include "usrp_std.vh" +// ==================================================================== + +`include "usrp_multi.vh" diff --git a/toplevel/usrp_std/usrp_std.csf b/toplevel/usrp_std/usrp_std.csf new file mode 100644 index 000000000..627197caf --- /dev/null +++ b/toplevel/usrp_std/usrp_std.csf @@ -0,0 +1,444 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; + OPTIMIZE_TIMING = "NORMAL COMPILATION"; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = OFF; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |usrp_std; + ROUTING_BACK_ANNOTATION_MODE = OFF; + INC_PLC_MODE = OFF; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} +CHIP(usrp_std) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; + AUTO_RESTART_CONFIGURATION = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + USER_START_UP_CLOCK = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_JTAG_BST_SUPPORT = OFF; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + USE_CONFIGURATION_DEVICE = OFF; + APEX20K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + STRATIX_UPDATE_MODE = STANDARD; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + COMPRESSION_MODE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + GENERATE_TTF_FILE = OFF; + GENERATE_RBF_FILE = ON; + GENERATE_HEX_FILE = OFF; + SECURITY_BIT = OFF; + ENABLE_VREFA_PIN = OFF; + ENABLE_VREFB_PIN = OFF; + GENERATE_SVF_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_JBC_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_HEXOUT_FILE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; + BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; + HEXOUT_FILE_START_ADDRESS = 0; + HEXOUT_FILE_COUNT_DIRECTION = UP; + RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; + STRATIX_DEVICE_IO_STANDARD = LVTTL; + CLOCK_SOURCE = INTERNAL; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CONFIGURATION_CLOCK_DIVISOR = 1; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + SCLK : LOCATION = Pin_101; + SDI : LOCATION = Pin_100; + SEN : LOCATION = Pin_98; + SLD : LOCATION = Pin_95; + adc1_data[0] : LOCATION = Pin_5; + adc1_data[10] : LOCATION = Pin_235; + adc1_data[11] : LOCATION = Pin_234; + adc1_data[1] : LOCATION = Pin_4; + adc1_data[2] : LOCATION = Pin_3; + adc1_data[3] : LOCATION = Pin_2; + adc1_data[4] : LOCATION = Pin_1; + adc1_data[4] : IO_STANDARD = LVTTL; + adc1_data[5] : LOCATION = Pin_240; + adc1_data[6] : LOCATION = Pin_239; + adc1_data[7] : LOCATION = Pin_238; + adc1_data[8] : LOCATION = Pin_237; + adc1_data[9] : LOCATION = Pin_236; + adc2_data[0] : LOCATION = Pin_20; + adc2_data[10] : LOCATION = Pin_8; + adc2_data[11] : LOCATION = Pin_7; + adc2_data[1] : LOCATION = Pin_19; + adc2_data[2] : LOCATION = Pin_18; + adc2_data[3] : LOCATION = Pin_17; + adc2_data[4] : LOCATION = Pin_16; + adc2_data[5] : LOCATION = Pin_15; + adc2_data[6] : LOCATION = Pin_14; + adc2_data[7] : LOCATION = Pin_13; + adc2_data[8] : LOCATION = Pin_12; + adc2_data[9] : LOCATION = Pin_11; + adc3_data[0] : LOCATION = Pin_200; + adc3_data[10] : LOCATION = Pin_184; + adc3_data[11] : LOCATION = Pin_183; + adc3_data[1] : LOCATION = Pin_197; + adc3_data[2] : LOCATION = Pin_196; + adc3_data[3] : LOCATION = Pin_195; + adc3_data[4] : LOCATION = Pin_194; + adc3_data[5] : LOCATION = Pin_193; + adc3_data[6] : LOCATION = Pin_188; + adc3_data[7] : LOCATION = Pin_187; + adc3_data[8] : LOCATION = Pin_186; + adc3_data[9] : LOCATION = Pin_185; + adc4_data[0] : LOCATION = Pin_222; + adc4_data[10] : LOCATION = Pin_203; + adc4_data[11] : LOCATION = Pin_202; + adc4_data[1] : LOCATION = Pin_219; + adc4_data[2] : LOCATION = Pin_217; + adc4_data[3] : LOCATION = Pin_216; + adc4_data[4] : LOCATION = Pin_215; + adc4_data[5] : LOCATION = Pin_214; + adc4_data[6] : LOCATION = Pin_213; + adc4_data[7] : LOCATION = Pin_208; + adc4_data[8] : LOCATION = Pin_207; + adc4_data[9] : LOCATION = Pin_206; + adc_oeb[0] : LOCATION = Pin_228; + adc_oeb[1] : LOCATION = Pin_21; + adc_oeb[2] : LOCATION = Pin_181; + adc_oeb[3] : LOCATION = Pin_218; + adc_otr[0] : LOCATION = Pin_233; + adc_otr[1] : LOCATION = Pin_6; + adc_otr[2] : LOCATION = Pin_182; + adc_otr[3] : LOCATION = Pin_201; + adclk0 : LOCATION = Pin_224; + adclk1 : LOCATION = Pin_226; + clk0 : LOCATION = Pin_28; + clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk0 : IO_STANDARD = LVTTL; + clk1 : LOCATION = Pin_29; + clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk1 : IO_STANDARD = LVTTL; + clk3 : LOCATION = Pin_152; + clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk3 : IO_STANDARD = LVTTL; + clk_120mhz : LOCATION = Pin_153; + clk_120mhz : IO_STANDARD = LVTTL; + clk_out : LOCATION = Pin_63; + clk_out : IO_STANDARD = LVTTL; + dac1_data[0] : LOCATION = Pin_165; + dac1_data[10] : LOCATION = Pin_177; + dac1_data[11] : LOCATION = Pin_178; + dac1_data[12] : LOCATION = Pin_179; + dac1_data[13] : LOCATION = Pin_180; + dac1_data[1] : LOCATION = Pin_166; + dac1_data[2] : LOCATION = Pin_167; + dac1_data[3] : LOCATION = Pin_168; + dac1_data[4] : LOCATION = Pin_169; + dac1_data[5] : LOCATION = Pin_170; + dac1_data[6] : LOCATION = Pin_173; + dac1_data[7] : LOCATION = Pin_174; + dac1_data[8] : LOCATION = Pin_175; + dac1_data[9] : LOCATION = Pin_176; + dac2_data[0] : LOCATION = Pin_159; + dac2_data[10] : LOCATION = Pin_163; + dac2_data[11] : LOCATION = Pin_139; + dac2_data[12] : LOCATION = Pin_164; + dac2_data[13] : LOCATION = Pin_138; + dac2_data[1] : LOCATION = Pin_158; + dac2_data[2] : LOCATION = Pin_160; + dac2_data[3] : LOCATION = Pin_156; + dac2_data[4] : LOCATION = Pin_161; + dac2_data[5] : LOCATION = Pin_144; + dac2_data[6] : LOCATION = Pin_162; + dac2_data[7] : LOCATION = Pin_141; + dac2_data[8] : LOCATION = Pin_143; + dac2_data[9] : LOCATION = Pin_140; + dac3_data[0] : LOCATION = Pin_122; + dac3_data[10] : LOCATION = Pin_134; + dac3_data[11] : LOCATION = Pin_135; + dac3_data[12] : LOCATION = Pin_136; + dac3_data[13] : LOCATION = Pin_137; + dac3_data[1] : LOCATION = Pin_123; + dac3_data[2] : LOCATION = Pin_124; + dac3_data[3] : LOCATION = Pin_125; + dac3_data[4] : LOCATION = Pin_126; + dac3_data[5] : LOCATION = Pin_127; + dac3_data[6] : LOCATION = Pin_128; + dac3_data[7] : LOCATION = Pin_131; + dac3_data[8] : LOCATION = Pin_132; + dac3_data[9] : LOCATION = Pin_133; + dac4_data[0] : LOCATION = Pin_104; + dac4_data[10] : LOCATION = Pin_118; + dac4_data[11] : LOCATION = Pin_119; + dac4_data[12] : LOCATION = Pin_120; + dac4_data[13] : LOCATION = Pin_121; + dac4_data[1] : LOCATION = Pin_105; + dac4_data[2] : LOCATION = Pin_106; + dac4_data[3] : LOCATION = Pin_107; + dac4_data[4] : LOCATION = Pin_108; + dac4_data[5] : LOCATION = Pin_113; + dac4_data[6] : LOCATION = Pin_114; + dac4_data[7] : LOCATION = Pin_115; + dac4_data[8] : LOCATION = Pin_116; + dac4_data[9] : LOCATION = Pin_117; + enable_rx : LOCATION = Pin_88; + enable_tx : LOCATION = Pin_93; + gndbus[0] : LOCATION = Pin_223; + gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[0] : IO_STANDARD = LVTTL; + gndbus[1] : LOCATION = Pin_225; + gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[1] : IO_STANDARD = LVTTL; + gndbus[2] : LOCATION = Pin_227; + gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[2] : IO_STANDARD = LVTTL; + gndbus[3] : LOCATION = Pin_62; + gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[3] : IO_STANDARD = LVTTL; + gndbus[4] : LOCATION = Pin_64; + gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[4] : IO_STANDARD = LVTTL; + misc_pins[0] : LOCATION = Pin_87; + misc_pins[0] : IO_STANDARD = LVTTL; + misc_pins[10] : LOCATION = Pin_76; + misc_pins[10] : IO_STANDARD = LVTTL; + misc_pins[11] : LOCATION = Pin_74; + misc_pins[11] : IO_STANDARD = LVTTL; + misc_pins[1] : LOCATION = Pin_86; + misc_pins[1] : IO_STANDARD = LVTTL; + misc_pins[2] : LOCATION = Pin_85; + misc_pins[2] : IO_STANDARD = LVTTL; + misc_pins[3] : LOCATION = Pin_84; + misc_pins[3] : IO_STANDARD = LVTTL; + misc_pins[4] : LOCATION = Pin_83; + misc_pins[4] : IO_STANDARD = LVTTL; + misc_pins[5] : LOCATION = Pin_82; + misc_pins[5] : IO_STANDARD = LVTTL; + misc_pins[6] : LOCATION = Pin_79; + misc_pins[6] : IO_STANDARD = LVTTL; + misc_pins[7] : LOCATION = Pin_78; + misc_pins[7] : IO_STANDARD = LVTTL; + misc_pins[8] : LOCATION = Pin_77; + misc_pins[8] : IO_STANDARD = LVTTL; + misc_pins[9] : LOCATION = Pin_75; + misc_pins[9] : IO_STANDARD = LVTTL; + reset : LOCATION = Pin_94; + usbclk : LOCATION = Pin_55; + usbctl[0] : LOCATION = Pin_56; + usbctl[1] : LOCATION = Pin_54; + usbctl[2] : LOCATION = Pin_53; + usbctl[3] : LOCATION = Pin_58; + usbctl[4] : LOCATION = Pin_57; + usbctl[5] : LOCATION = Pin_44; + usbdata[0] : LOCATION = Pin_73; + usbdata[10] : LOCATION = Pin_41; + usbdata[11] : LOCATION = Pin_39; + usbdata[12] : LOCATION = Pin_38; + usbdata[12] : IO_STANDARD = LVTTL; + usbdata[13] : LOCATION = Pin_37; + usbdata[14] : LOCATION = Pin_24; + usbdata[15] : LOCATION = Pin_23; + usbdata[1] : LOCATION = Pin_68; + usbdata[2] : LOCATION = Pin_67; + usbdata[3] : LOCATION = Pin_66; + usbdata[4] : LOCATION = Pin_65; + usbdata[5] : LOCATION = Pin_61; + usbdata[6] : LOCATION = Pin_60; + usbdata[7] : LOCATION = Pin_59; + usbdata[8] : LOCATION = Pin_43; + usbdata[9] : LOCATION = Pin_42; + usbrdy[0] : LOCATION = Pin_45; + usbrdy[1] : LOCATION = Pin_46; + usbrdy[2] : LOCATION = Pin_47; + usbrdy[3] : LOCATION = Pin_48; + usbrdy[4] : LOCATION = Pin_49; + usbrdy[5] : LOCATION = Pin_50; + clear_status : LOCATION = Pin_99; +} diff --git a/toplevel/usrp_std/usrp_std.esf b/toplevel/usrp_std/usrp_std.esf new file mode 100644 index 000000000..b88c15994 --- /dev/null +++ b/toplevel/usrp_std/usrp_std.esf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = usrp_std; +} diff --git a/toplevel/usrp_std/usrp_std.psf b/toplevel/usrp_std/usrp_std.psf new file mode 100644 index 000000000..506c81b6a --- /dev/null +++ b/toplevel/usrp_std/usrp_std.psf @@ -0,0 +1,312 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_DSP_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_TURBO_BIT = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_PARALLEL_EXPANDERS = ON; + AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; + AUTO_FAST_OUTPUT_REGISTERS = OFF; + AUTO_FAST_INPUT_REGISTERS = OFF; + AUTO_CASCADE_CHAINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; + PARALLEL_EXPANDER_CHAIN_LENGTH = 16; + CASCADE_CHAIN_LENGTH = 2; + STRATIX_CARRY_CHAIN_LENGTH = 70; + MERCURY_CARRY_CHAIN_LENGTH = 48; + FLEX10K_CARRY_CHAIN_LENGTH = 32; + FLEX6K_CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN_LENGTH = 48; + CARRY_OUT_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + AUTO_LCELL_INSERTION = ON; + ALLOW_XOR_GATE_USAGE = ON; + AUTO_PACKED_REGISTERS_STRATIX = NORMAL; + AUTO_PACKED_REGISTERS = OFF; + AUTO_PACKED_REG_CYCLONE = NORMAL; + FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; + FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; + MERCURY_OPTIMIZATION_TECHNIQUE = AREA; + APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; + MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; + STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; + CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; + FLEX10K_TECHNOLOGY_MAPPER = LUT; + FLEX6K_TECHNOLOGY_MAPPER = LUT; + MERCURY_TECHNOLOGY_MAPPER = LUT; + APEX20K_TECHNOLOGY_MAPPER = LUT; + MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; + STRATIX_TECHNOLOGY_MAPPER = LUT; + AUTO_IMPLEMENT_IN_ROM = OFF; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_CLOCK = ON; + USE_LPM_FOR_AHDL_OPERATORS = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + TURBO_BIT = ON; + MAX7000_IGNORE_SOFT_BUFFERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MAX7000_IGNORE_LCELL_BUFFERS = AUTO; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + DSP_BLOCK_BALANCING = AUTO; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(usrp_std) +{ + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; + USER_LIBRARIES = "e:\usrp\fpga\megacells"; +} +THIRD_PARTY_EDA_TOOLS(usrp_std) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} +CLOCK(clk_120mhz) +{ + FMAX_REQUIREMENT = "120.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(usbclk) +{ + FMAX_REQUIREMENT = "48.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(SCLK) +{ + FMAX_REQUIREMENT = "1.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk0) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk1) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} diff --git a/toplevel/usrp_std/usrp_std.qpf b/toplevel/usrp_std/usrp_std.qpf new file mode 100644 index 000000000..e8b27505c --- /dev/null +++ b/toplevel/usrp_std/usrp_std.qpf @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2004 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.0" +DATE = "17:10:11 December 20, 2004" + + +# Active Revisions + +PROJECT_REVISION = "usrp_std" diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf new file mode 100644 index 000000000..51d7e1ea2 --- /dev/null +++ b/toplevel/usrp_std/usrp_std.qsf @@ -0,0 +1,406 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# usrp_std_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" +set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2" + +# Pin & Location Assignments +# ========================== +set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" +set_location_assignment PIN_29 -to SCLK +set_location_assignment PIN_117 -to SDI +set_location_assignment PIN_28 -to usbclk +set_location_assignment PIN_107 -to usbctl[0] +set_location_assignment PIN_106 -to usbctl[1] +set_location_assignment PIN_105 -to usbctl[2] +set_location_assignment PIN_100 -to usbdata[0] +set_location_assignment PIN_84 -to usbdata[10] +set_location_assignment PIN_83 -to usbdata[11] +set_location_assignment PIN_82 -to usbdata[12] +set_location_assignment PIN_79 -to usbdata[13] +set_location_assignment PIN_78 -to usbdata[14] +set_location_assignment PIN_77 -to usbdata[15] +set_location_assignment PIN_99 -to usbdata[1] +set_location_assignment PIN_98 -to usbdata[2] +set_location_assignment PIN_95 -to usbdata[3] +set_location_assignment PIN_94 -to usbdata[4] +set_location_assignment PIN_93 -to usbdata[5] +set_location_assignment PIN_88 -to usbdata[6] +set_location_assignment PIN_87 -to usbdata[7] +set_location_assignment PIN_86 -to usbdata[8] +set_location_assignment PIN_85 -to usbdata[9] +set_location_assignment PIN_104 -to usbrdy[0] +set_location_assignment PIN_101 -to usbrdy[1] +set_location_assignment PIN_76 -to FX2_1 +set_location_assignment PIN_75 -to FX2_2 +set_location_assignment PIN_74 -to FX2_3 +set_location_assignment PIN_116 -to io_rx_a[0] +set_location_assignment PIN_115 -to io_rx_a[1] +set_location_assignment PIN_114 -to io_rx_a[2] +set_location_assignment PIN_113 -to io_rx_a[3] +set_location_assignment PIN_108 -to io_rx_a[4] +set_location_assignment PIN_195 -to io_rx_a[5] +set_location_assignment PIN_196 -to io_rx_a[6] +set_location_assignment PIN_197 -to io_rx_a[7] +set_location_assignment PIN_200 -to io_rx_a[8] +set_location_assignment PIN_201 -to io_rx_a[9] +set_location_assignment PIN_202 -to io_rx_a[10] +set_location_assignment PIN_203 -to io_rx_a[11] +set_location_assignment PIN_206 -to io_rx_a[12] +set_location_assignment PIN_207 -to io_rx_a[13] +set_location_assignment PIN_208 -to io_rx_a[14] +set_location_assignment PIN_214 -to io_rx_b[0] +set_location_assignment PIN_215 -to io_rx_b[1] +set_location_assignment PIN_216 -to io_rx_b[2] +set_location_assignment PIN_217 -to io_rx_b[3] +set_location_assignment PIN_218 -to io_rx_b[4] +set_location_assignment PIN_219 -to io_rx_b[5] +set_location_assignment PIN_222 -to io_rx_b[6] +set_location_assignment PIN_223 -to io_rx_b[7] +set_location_assignment PIN_224 -to io_rx_b[8] +set_location_assignment PIN_225 -to io_rx_b[9] +set_location_assignment PIN_226 -to io_rx_b[10] +set_location_assignment PIN_227 -to io_rx_b[11] +set_location_assignment PIN_228 -to io_rx_b[12] +set_location_assignment PIN_233 -to io_rx_b[13] +set_location_assignment PIN_234 -to io_rx_b[14] +set_location_assignment PIN_175 -to io_tx_a[0] +set_location_assignment PIN_176 -to io_tx_a[1] +set_location_assignment PIN_177 -to io_tx_a[2] +set_location_assignment PIN_178 -to io_tx_a[3] +set_location_assignment PIN_179 -to io_tx_a[4] +set_location_assignment PIN_180 -to io_tx_a[5] +set_location_assignment PIN_181 -to io_tx_a[6] +set_location_assignment PIN_182 -to io_tx_a[7] +set_location_assignment PIN_183 -to io_tx_a[8] +set_location_assignment PIN_184 -to io_tx_a[9] +set_location_assignment PIN_185 -to io_tx_a[10] +set_location_assignment PIN_186 -to io_tx_a[11] +set_location_assignment PIN_187 -to io_tx_a[12] +set_location_assignment PIN_188 -to io_tx_a[13] +set_location_assignment PIN_193 -to io_tx_a[14] +set_location_assignment PIN_73 -to io_tx_b[0] +set_location_assignment PIN_68 -to io_tx_b[1] +set_location_assignment PIN_67 -to io_tx_b[2] +set_location_assignment PIN_66 -to io_tx_b[3] +set_location_assignment PIN_65 -to io_tx_b[4] +set_location_assignment PIN_64 -to io_tx_b[5] +set_location_assignment PIN_63 -to io_tx_b[6] +set_location_assignment PIN_62 -to io_tx_b[7] +set_location_assignment PIN_61 -to io_tx_b[8] +set_location_assignment PIN_60 -to io_tx_b[9] +set_location_assignment PIN_59 -to io_tx_b[10] +set_location_assignment PIN_58 -to io_tx_b[11] +set_location_assignment PIN_57 -to io_tx_b[12] +set_location_assignment PIN_56 -to io_tx_b[13] +set_location_assignment PIN_55 -to io_tx_b[14] +set_location_assignment PIN_152 -to master_clk +set_location_assignment PIN_144 -to rx_a_a[0] +set_location_assignment PIN_143 -to rx_a_a[1] +set_location_assignment PIN_141 -to rx_a_a[2] +set_location_assignment PIN_140 -to rx_a_a[3] +set_location_assignment PIN_139 -to rx_a_a[4] +set_location_assignment PIN_138 -to rx_a_a[5] +set_location_assignment PIN_137 -to rx_a_a[6] +set_location_assignment PIN_136 -to rx_a_a[7] +set_location_assignment PIN_135 -to rx_a_a[8] +set_location_assignment PIN_134 -to rx_a_a[9] +set_location_assignment PIN_133 -to rx_a_a[10] +set_location_assignment PIN_132 -to rx_a_a[11] +set_location_assignment PIN_23 -to rx_a_b[0] +set_location_assignment PIN_21 -to rx_a_b[1] +set_location_assignment PIN_20 -to rx_a_b[2] +set_location_assignment PIN_19 -to rx_a_b[3] +set_location_assignment PIN_18 -to rx_a_b[4] +set_location_assignment PIN_17 -to rx_a_b[5] +set_location_assignment PIN_16 -to rx_a_b[6] +set_location_assignment PIN_15 -to rx_a_b[7] +set_location_assignment PIN_14 -to rx_a_b[8] +set_location_assignment PIN_13 -to rx_a_b[9] +set_location_assignment PIN_12 -to rx_a_b[10] +set_location_assignment PIN_11 -to rx_a_b[11] +set_location_assignment PIN_131 -to rx_b_a[0] +set_location_assignment PIN_128 -to rx_b_a[1] +set_location_assignment PIN_127 -to rx_b_a[2] +set_location_assignment PIN_126 -to rx_b_a[3] +set_location_assignment PIN_125 -to rx_b_a[4] +set_location_assignment PIN_124 -to rx_b_a[5] +set_location_assignment PIN_123 -to rx_b_a[6] +set_location_assignment PIN_122 -to rx_b_a[7] +set_location_assignment PIN_121 -to rx_b_a[8] +set_location_assignment PIN_120 -to rx_b_a[9] +set_location_assignment PIN_119 -to rx_b_a[10] +set_location_assignment PIN_118 -to rx_b_a[11] +set_location_assignment PIN_8 -to rx_b_b[0] +set_location_assignment PIN_7 -to rx_b_b[1] +set_location_assignment PIN_6 -to rx_b_b[2] +set_location_assignment PIN_5 -to rx_b_b[3] +set_location_assignment PIN_4 -to rx_b_b[4] +set_location_assignment PIN_3 -to rx_b_b[5] +set_location_assignment PIN_2 -to rx_b_b[6] +set_location_assignment PIN_240 -to rx_b_b[7] +set_location_assignment PIN_239 -to rx_b_b[8] +set_location_assignment PIN_238 -to rx_b_b[9] +set_location_assignment PIN_237 -to rx_b_b[10] +set_location_assignment PIN_236 -to rx_b_b[11] +set_location_assignment PIN_156 -to SDO +set_location_assignment PIN_153 -to SEN_FPGA +set_location_assignment PIN_159 -to tx_a[0] +set_location_assignment PIN_160 -to tx_a[1] +set_location_assignment PIN_161 -to tx_a[2] +set_location_assignment PIN_162 -to tx_a[3] +set_location_assignment PIN_163 -to tx_a[4] +set_location_assignment PIN_164 -to tx_a[5] +set_location_assignment PIN_165 -to tx_a[6] +set_location_assignment PIN_166 -to tx_a[7] +set_location_assignment PIN_167 -to tx_a[8] +set_location_assignment PIN_168 -to tx_a[9] +set_location_assignment PIN_169 -to tx_a[10] +set_location_assignment PIN_170 -to tx_a[11] +set_location_assignment PIN_173 -to tx_a[12] +set_location_assignment PIN_174 -to tx_a[13] +set_location_assignment PIN_38 -to tx_b[0] +set_location_assignment PIN_39 -to tx_b[1] +set_location_assignment PIN_41 -to tx_b[2] +set_location_assignment PIN_42 -to tx_b[3] +set_location_assignment PIN_43 -to tx_b[4] +set_location_assignment PIN_44 -to tx_b[5] +set_location_assignment PIN_45 -to tx_b[6] +set_location_assignment PIN_46 -to tx_b[7] +set_location_assignment PIN_47 -to tx_b[8] +set_location_assignment PIN_48 -to tx_b[9] +set_location_assignment PIN_49 -to tx_b[10] +set_location_assignment PIN_50 -to tx_b[11] +set_location_assignment PIN_53 -to tx_b[12] +set_location_assignment PIN_54 -to tx_b[13] +set_location_assignment PIN_158 -to TXSYNC_A +set_location_assignment PIN_37 -to TXSYNC_B +set_location_assignment PIN_235 -to io_rx_b[15] +set_location_assignment PIN_24 -to io_tx_b[15] +set_location_assignment PIN_213 -to io_rx_a[15] +set_location_assignment PIN_194 -to io_tx_a[15] +set_location_assignment PIN_1 -to MYSTERY_SIGNAL + +# Timing Assignments +# ================== +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name TOP_LEVEL_ENTITY usrp_std +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name INC_PLC_MODE OFF +set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF +set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# Timing Analysis Assignments +# =========================== +set_global_assignment -name MAX_SCC_SIZE 50 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF + +# Simulator Assignments +# ===================== +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "1 ns" + +# Design Assistant Assignments +# ============================ +set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF +set_global_assignment -name ASSG_CAT OFF +set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF +set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF +set_global_assignment -name CLK_CAT OFF +set_global_assignment -name CLK_RULE_COMB_CLOCK OFF +set_global_assignment -name CLK_RULE_INV_CLOCK OFF +set_global_assignment -name CLK_RULE_GATING_SCHEME OFF +set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF +set_global_assignment -name CLK_RULE_MIX_EDGES OFF +set_global_assignment -name RESET_CAT OFF +set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name TIMING_CAT OFF +set_global_assignment -name TIMING_RULE_SHIFT_REG OFF +set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF +set_global_assignment -name NONSYNCHSTRUCT_CAT OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF +set_global_assignment -name SIGNALRACE_CAT OFF +set_global_assignment -name ACLK_CAT OFF +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF +set_global_assignment -name HCPY_CAT OFF +set_global_assignment -name HCPY_VREF_PINS OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name HUB_ENTITY_NAME SLD_HUB +set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST +set_global_assignment -name ENABLE_SIGNALTAP Off + +# LogicLock Region Assignments +# ============================ +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF + +# ----------------- +# start CLOCK(SCLK) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK + set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK + set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK + +# end CLOCK(SCLK) +# --------------- + +# ----------------------- +# start CLOCK(master_clk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk + set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk + set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk + +# end CLOCK(master_clk) +# --------------------- + +# ------------------- +# start CLOCK(usbclk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk + set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk + set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk + +# end CLOCK(usbclk) +# ----------------- + +# ---------------------- +# start ENTITY(usrp_std) + + # Timing Assignments + # ================== + set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK + set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk + set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk + +# end ENTITY(usrp_std) +# -------------------- + +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v +set_global_assignment -name VERILOG_FILE usrp_std.vh +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v +set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v +set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v +set_global_assignment -name VERILOG_FILE usrp_std.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v new file mode 100644 index 000000000..9ba8c7c65 --- /dev/null +++ b/toplevel/usrp_std/usrp_std.v @@ -0,0 +1,324 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2004 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// Top level module for a full setup with DUCs and DDCs + +// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins +// for debugging info. NB, This can kill the m'board and/or d'board if you +// have anything except basic d'boards installed. + +// Uncomment the following to include optional circuitry + +`include "usrp_std.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module usrp_std +(output MYSTERY_SIGNAL, + input master_clk, + input SCLK, + input SDI, + inout SDO, + input SEN_FPGA, + + input FX2_1, + output FX2_2, + output FX2_3, + + input wire [11:0] rx_a_a, + input wire [11:0] rx_b_a, + input wire [11:0] rx_a_b, + input wire [11:0] rx_b_b, + + output wire [13:0] tx_a, + output wire [13:0] tx_b, + + output wire TXSYNC_A, + output wire TXSYNC_B, + + // USB interface + input usbclk, + input wire [2:0] usbctl, + output wire [1:0] usbrdy, + inout [15:0] usbdata, // NB Careful, inout + + // These are the general purpose i/o's that go to the daughterboard slots + inout wire [15:0] io_tx_a, + inout wire [15:0] io_tx_b, + inout wire [15:0] io_rx_a, + inout wire [15:0] io_rx_b + ); + wire [15:0] debugdata,debugctrl; + assign MYSTERY_SIGNAL = 1'b0; + + wire clk64,clk128; + + wire WR = usbctl[0]; + wire RD = usbctl[1]; + wire OE = usbctl[2]; + + wire have_space, have_pkt_rdy; + assign usbrdy[0] = have_space; + assign usbrdy[1] = have_pkt_rdy; + + wire tx_underrun, rx_overrun; + wire clear_status = FX2_1; + assign FX2_2 = rx_overrun; + assign FX2_3 = tx_underrun; + + wire [15:0] usbdata_out; + + wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; + + wire tx_realsignals; + wire [3:0] rx_numchan; + wire [2:0] tx_numchan; + + wire [7:0] interp_rate, decim_rate; + wire [15:0] tx_debugbus, rx_debugbus; + + wire enable_tx, enable_rx; + wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; + wire [7:0] settings; + + // Tri-state bus macro + bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); + + assign clk64 = master_clk; + + wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; + wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; + + // TX + wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; + wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; + + wire strobe_interp, tx_sample_strobe; + wire tx_empty; + + wire serial_strobe; + wire [6:0] serial_addr; + wire [31:0] serial_data; + + reg [15:0] debug_counter; + reg [15:0] loopback_i_0,loopback_q_0; + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Transmit Side +`ifdef TX_ON + assign bb_tx_i0 = ch0tx; + assign bb_tx_q0 = ch1tx; + assign bb_tx_i1 = ch2tx; + assign bb_tx_q1 = ch3tx; + + tx_buffer tx_buffer + ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), + .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), + .channels({tx_numchan,1'b0}), + .tx_i_0(ch0tx),.tx_q_0(ch1tx), + .tx_i_1(ch2tx),.tx_q_1(ch3tx), + .tx_i_2(),.tx_q_2(), + .tx_i_3(),.tx_q_3(), + .txclk(clk64),.txstrobe(strobe_interp), + .clear_status(clear_status), + .tx_empty(tx_empty), + .debugbus(tx_debugbus) ); + + tx_chain tx_chain_0 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); + + tx_chain tx_chain_1 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); + + setting_reg #(`FR_TX_MUX) + sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; + + wire txsync = tx_sample_strobe; + assign TXSYNC_A = txsync; + assign TXSYNC_B = txsync; + + assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; + assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; +`endif // `ifdef TX_ON + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Receive Side +`ifdef RX_ON + wire rx_sample_strobe,strobe_decim,hb_strobe; + wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, + bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; + + wire loopback = settings[0]; + wire counter = settings[1]; + + always @(posedge clk64) + if(rx_dsp_reset) + debug_counter <= #1 16'd0; + else if(~enable_rx) + debug_counter <= #1 16'd0; + else if(hb_strobe) + debug_counter <=#1 debug_counter + 16'd2; + + always @(posedge clk64) + if(strobe_interp) + begin + loopback_i_0 <= #1 ch0tx; + loopback_q_0 <= #1 ch1tx; + end + + assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; + assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; + assign ch2rx = bb_rx_i1; + assign ch3rx = bb_rx_q1; + assign ch4rx = bb_rx_i2; + assign ch5rx = bb_rx_q2; + assign ch6rx = bb_rx_i3; + assign ch7rx = bb_rx_q3; + + wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; + wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; + + adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), + .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3), + .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), + .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), + .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), + .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); + + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), + .reset_regs(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(ch0rx),.ch_1(ch1rx), + .ch_2(ch2rx),.ch_3(ch3rx), + .ch_4(ch4rx),.ch_5(ch5rx), + .ch_6(ch6rx),.ch_7(ch7rx), + .rxclk(clk64),.rxstrobe(hb_strobe), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .debugbus(rx_debugbus) ); + + `ifdef RX_EN_0 + rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); + `else + assign bb_rx_i0=16'd0; + assign bb_rx_q0=16'd0; + `endif + + `ifdef RX_EN_1 + rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); + `else + assign bb_rx_i1=16'd0; + assign bb_rx_q1=16'd0; + `endif + + `ifdef RX_EN_2 + rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); + `else + assign bb_rx_i2=16'd0; + assign bb_rx_q2=16'd0; + `endif + + `ifdef RX_EN_3 + rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); + `else + assign bb_rx_i3=16'd0; + assign bb_rx_q3=16'd0; + `endif + +`endif // `ifdef RX_ON + + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Control Functions + + wire [31:0] capabilities; + assign capabilities[7] = `TX_CAP_HB; + assign capabilities[6:4] = `TX_CAP_NCHAN; + assign capabilities[3] = `RX_CAP_HB; + assign capabilities[2:0] = `RX_CAP_NCHAN; + + + serial_io serial_io + ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), + .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), + .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) + ); + + wire [15:0] reg_0,reg_1,reg_2,reg_3; + master_control master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + //.debug_0(rx_a_a),.debug_1(ddc0_in_i), + .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + + io_pins io_pins + (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Misc Settings + setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); + +endmodule // usrp_std diff --git a/toplevel/usrp_std/usrp_std.vh b/toplevel/usrp_std/usrp_std.vh new file mode 100644 index 000000000..65aed9b43 --- /dev/null +++ b/toplevel/usrp_std/usrp_std.vh @@ -0,0 +1,119 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// ==================================================================== +// User control over what parts get included +// +// >>>> EDIT ONLY THIS SECTION <<<< +// +// ==================================================================== + +// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels + `include "usrp_std_config_2rxhb_2tx.vh" + +// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels +//`include "usrp_std_config_4rx_0tx.vh" + +// Add other "known to fit" configurations here... + +// ==================================================================== +// +// >>>> DO NOT EDIT BELOW HERE <<<< +// +// [The stuff from here down is derived from the stuff included above] +// +// N.B., *all* the remainder of the code should be conditionalized +// only in terms of: +// +// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB, +// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB, +// RX_NCO_ON, RX_CIC_ON +// ==================================================================== + +`ifdef TX_ON + + `ifdef TX_SINGLE + `define TX_EN_0 + `define TX_CAP_NCHAN 3'd1 + `endif + + `ifdef TX_DUAL + `define TX_EN_0 + `define TX_EN_1 + `define TX_CAP_NCHAN 3'd2 + `endif + + `ifdef TX_QUAD + `define TX_EN_0 + `define TX_EN_1 + `define TX_EN_2 + `define TX_EN_3 + `define TX_CAP_NCHAN 3'd4 + `endif + + `ifdef TX_HB_ON + `define TX_CAP_HB 1 + `else + `define TX_CAP_HB 0 + `endif + +`else // !ifdef TX_ON + + `define TX_CAP_NCHAN 3'd0 + `define TX_CAP_HB 0 + +`endif // !ifdef TX_ON + +// -------------------------------------------------------------------- + +`ifdef RX_ON + + `ifdef RX_SINGLE + `define RX_EN_0 + `define RX_CAP_NCHAN 3'd1 + `endif + + `ifdef RX_DUAL + `define RX_EN_0 + `define RX_EN_1 + `define RX_CAP_NCHAN 3'd2 + `endif + + `ifdef RX_QUAD + `define RX_EN_0 + `define RX_EN_1 + `define RX_EN_2 + `define RX_EN_3 + `define RX_CAP_NCHAN 3'd4 + `endif + + `ifdef RX_HB_ON + `define RX_CAP_HB 1 + `else + `define RX_CAP_HB 0 + `endif + +`else // !ifdef RX_ON + + `define RX_CAP_NCHAN 3'd0 + `define RX_CAP_HB 0 + +`endif // !ifdef RX_ON diff --git a/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh new file mode 100644 index 000000000..74f1bfd1c --- /dev/null +++ b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built + `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_DUAL is currently valid] +//`define TX_SINGLE + `define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE + `define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh new file mode 100644 index 000000000..0bd188778 --- /dev/null +++ b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_DUAL is currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE +//`define RX_DUAL + `define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter +//`define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON -- cgit v1.2.3 From 6f725de982a80f1a024072ef1e4f31cf2ff5b01d Mon Sep 17 00:00:00 2001 From: eb Date: Wed, 13 Sep 2006 21:30:04 +0000 Subject: Updated FSF address in all files. Fixes ticket:51 git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3534 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.am | 4 ++-- gen_makefile_extra.py | 4 ++-- models/pll.v | 2 +- rbf/Makefile.am | 4 ++-- sdr_lib/bus_interface.v | 2 +- sdr_lib/cic_decim.v | 2 +- sdr_lib/cic_int_shifter.v | 2 +- sdr_lib/cic_interp.v | 2 +- sdr_lib/clk_divider.v | 2 +- sdr_lib/cordic.v | 2 +- sdr_lib/cordic_stage.v | 2 +- sdr_lib/ddc.v | 2 +- sdr_lib/dpram.v | 2 +- sdr_lib/duc.v | 2 +- sdr_lib/ext_fifo.v | 2 +- sdr_lib/gen_sync.v | 2 +- sdr_lib/hb/halfband_decim.v | 2 +- sdr_lib/io_pins.v | 2 +- sdr_lib/master_control.v | 2 +- sdr_lib/master_control_multi.v | 2 +- sdr_lib/phase_acc.v | 2 +- sdr_lib/rx_buffer.v | 2 +- sdr_lib/rx_chain.v | 2 +- sdr_lib/rx_chain_dual.v | 2 +- sdr_lib/serial_io.v | 2 +- sdr_lib/sign_extend.v | 2 +- sdr_lib/strobe_gen.v | 2 +- sdr_lib/tx_buffer.v | 2 +- sdr_lib/tx_chain.v | 2 +- sdr_lib/tx_chain_hb.v | 2 +- tb/cordic_tb.v | 2 +- tb/decim_tb.v | 2 +- tb/fullchip_tb.v | 2 +- tb/interp_tb.v | 2 +- tb/justinterp_tb.v | 2 +- tb/usrp_tasks.v | 2 +- toplevel/mrfm/mrfm.py | 4 ++-- toplevel/mrfm/mrfm.v | 2 +- toplevel/mrfm/mrfm_fft.py | 4 ++-- toplevel/mrfm/shifter.v | 2 +- toplevel/sizetest/sizetest.v | 2 +- toplevel/usrp_multi/usrp_multi.v | 2 +- toplevel/usrp_multi/usrp_multi.vh | 2 +- toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh | 2 +- toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh | 2 +- toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh | 2 +- toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh | 2 +- toplevel/usrp_multi/usrp_std.vh | 2 +- toplevel/usrp_std/usrp_std.v | 2 +- toplevel/usrp_std/usrp_std.vh | 2 +- toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh | 2 +- toplevel/usrp_std/usrp_std_config_4rx_0tx.vh | 2 +- 52 files changed, 57 insertions(+), 57 deletions(-) diff --git a/Makefile.am b/Makefile.am index 61227f056..02f971da3 100644 --- a/Makefile.am +++ b/Makefile.am @@ -15,8 +15,8 @@ # # You should have received a copy of the GNU General Public License # along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, -# Boston, MA 02111-1307, USA. +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. # SUBDIRS = rbf diff --git a/gen_makefile_extra.py b/gen_makefile_extra.py index 165a84940..e20a852af 100755 --- a/gen_makefile_extra.py +++ b/gen_makefile_extra.py @@ -16,8 +16,8 @@ # # You should have received a copy of the GNU General Public License # along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, -# Boston, MA 02111-1307, USA. +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. # """ diff --git a/models/pll.v b/models/pll.v index d87964844..1d0cc7966 100644 --- a/models/pll.v +++ b/models/pll.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Very simple model for the PLL in the RX buffer diff --git a/rbf/Makefile.am b/rbf/Makefile.am index dbc2875fc..ae2cbab81 100644 --- a/rbf/Makefile.am +++ b/rbf/Makefile.am @@ -15,8 +15,8 @@ # # You should have received a copy of the GNU General Public License # along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, -# Boston, MA 02111-1307, USA. +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. # include $(top_srcdir)/Makefile.common diff --git a/sdr_lib/bus_interface.v b/sdr_lib/bus_interface.v index 3f5f748d5..b326889c0 100755 --- a/sdr_lib/bus_interface.v +++ b/sdr_lib/bus_interface.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Interface to Cypress FX2 bus diff --git a/sdr_lib/cic_decim.v b/sdr_lib/cic_decim.v index 45b863f16..d7e5310b8 100755 --- a/sdr_lib/cic_decim.v +++ b/sdr_lib/cic_decim.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/cic_int_shifter.v b/sdr_lib/cic_int_shifter.v index 112d8712b..fd928373b 100644 --- a/sdr_lib/cic_int_shifter.v +++ b/sdr_lib/cic_int_shifter.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/cic_interp.v b/sdr_lib/cic_interp.v index 43ab17d3b..0dd621623 100755 --- a/sdr_lib/cic_interp.v +++ b/sdr_lib/cic_interp.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/clk_divider.v b/sdr_lib/clk_divider.v index a687297b4..fdef234d2 100755 --- a/sdr_lib/clk_divider.v +++ b/sdr_lib/clk_divider.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/cordic.v b/sdr_lib/cordic.v index 8c8c0ab0d..fee241f62 100755 --- a/sdr_lib/cordic.v +++ b/sdr_lib/cordic.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo ); diff --git a/sdr_lib/cordic_stage.v b/sdr_lib/cordic_stage.v index c9c0ef9a3..0106da5cb 100755 --- a/sdr_lib/cordic_stage.v +++ b/sdr_lib/cordic_stage.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo); diff --git a/sdr_lib/ddc.v b/sdr_lib/ddc.v index 48bca9a79..0d4da9bbc 100755 --- a/sdr_lib/ddc.v +++ b/sdr_lib/ddc.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/dpram.v b/sdr_lib/dpram.v index 5c38decce..28af90163 100644 --- a/sdr_lib/dpram.v +++ b/sdr_lib/dpram.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/duc.v b/sdr_lib/duc.v index 780fc9f23..6dac95b49 100755 --- a/sdr_lib/duc.v +++ b/sdr_lib/duc.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // DUC block diff --git a/sdr_lib/ext_fifo.v b/sdr_lib/ext_fifo.v index dfe1f2fe7..41e30de71 100644 --- a/sdr_lib/ext_fifo.v +++ b/sdr_lib/ext_fifo.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/gen_sync.v b/sdr_lib/gen_sync.v index d72b39d56..d6efdba98 100644 --- a/sdr_lib/gen_sync.v +++ b/sdr_lib/gen_sync.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module gen_sync diff --git a/sdr_lib/hb/halfband_decim.v b/sdr_lib/hb/halfband_decim.v index 2a05ce52c..dff4d902c 100644 --- a/sdr_lib/hb/halfband_decim.v +++ b/sdr_lib/hb/halfband_decim.v @@ -16,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA */ /* diff --git a/sdr_lib/io_pins.v b/sdr_lib/io_pins.v index da20b3b03..ad1b7b4a8 100644 --- a/sdr_lib/io_pins.v +++ b/sdr_lib/io_pins.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // `include "../../firmware/include/fpga_regs_common.v" diff --git a/sdr_lib/master_control.v b/sdr_lib/master_control.v index d42817c72..863d44a82 100644 --- a/sdr_lib/master_control.v +++ b/sdr_lib/master_control.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Clock, enable, and reset controls for whole system diff --git a/sdr_lib/master_control_multi.v b/sdr_lib/master_control_multi.v index af1e0b1f1..95c4ec17e 100644 --- a/sdr_lib/master_control_multi.v +++ b/sdr_lib/master_control_multi.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // `include "usrp_multi.vh" `include "../../../firmware/include/fpga_regs_common.v" diff --git a/sdr_lib/phase_acc.v b/sdr_lib/phase_acc.v index d00716fd0..f44853d36 100755 --- a/sdr_lib/phase_acc.v +++ b/sdr_lib/phase_acc.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/rx_buffer.v b/sdr_lib/rx_buffer.v index 70c800e3d..ec5b8eefe 100644 --- a/sdr_lib/rx_buffer.v +++ b/sdr_lib/rx_buffer.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Interface to Cypress FX2 bus diff --git a/sdr_lib/rx_chain.v b/sdr_lib/rx_chain.v index 4031e6bfb..73c0c26ea 100644 --- a/sdr_lib/rx_chain.v +++ b/sdr_lib/rx_chain.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Following defines conditionally include RX path circuitry diff --git a/sdr_lib/rx_chain_dual.v b/sdr_lib/rx_chain_dual.v index 698859468..d9d98f3fc 100644 --- a/sdr_lib/rx_chain_dual.v +++ b/sdr_lib/rx_chain_dual.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module rx_chain_dual diff --git a/sdr_lib/serial_io.v b/sdr_lib/serial_io.v index 1fe43c959..62f92bed2 100644 --- a/sdr_lib/serial_io.v +++ b/sdr_lib/serial_io.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/sign_extend.v b/sdr_lib/sign_extend.v index 2417909bd..eae67faf2 100644 --- a/sdr_lib/sign_extend.v +++ b/sdr_lib/sign_extend.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/sdr_lib/strobe_gen.v b/sdr_lib/strobe_gen.v index 0511b6a1d..a27dda8d3 100644 --- a/sdr_lib/strobe_gen.v +++ b/sdr_lib/strobe_gen.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module strobe_gen diff --git a/sdr_lib/tx_buffer.v b/sdr_lib/tx_buffer.v index cae6607b3..ff8fd839d 100644 --- a/sdr_lib/tx_buffer.v +++ b/sdr_lib/tx_buffer.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Interface to Cypress FX2 bus diff --git a/sdr_lib/tx_chain.v b/sdr_lib/tx_chain.v index 8f0a17a52..60f868475 100644 --- a/sdr_lib/tx_chain.v +++ b/sdr_lib/tx_chain.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module tx_chain diff --git a/sdr_lib/tx_chain_hb.v b/sdr_lib/tx_chain_hb.v index 6cbe29c00..5594348b4 100644 --- a/sdr_lib/tx_chain_hb.v +++ b/sdr_lib/tx_chain_hb.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module tx_chain_hb diff --git a/tb/cordic_tb.v b/tb/cordic_tb.v index ed85b37b1..946fc776c 100644 --- a/tb/cordic_tb.v +++ b/tb/cordic_tb.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/tb/decim_tb.v b/tb/decim_tb.v index ecf20cf4a..d9a926125 100644 --- a/tb/decim_tb.v +++ b/tb/decim_tb.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/tb/fullchip_tb.v b/tb/fullchip_tb.v index c446ff0e1..2406fa777 100755 --- a/tb/fullchip_tb.v +++ b/tb/fullchip_tb.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/tb/interp_tb.v b/tb/interp_tb.v index 8a8e89ff9..830fceb31 100755 --- a/tb/interp_tb.v +++ b/tb/interp_tb.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/tb/justinterp_tb.v b/tb/justinterp_tb.v index ffbd0f178..f97696488 100644 --- a/tb/justinterp_tb.v +++ b/tb/justinterp_tb.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/tb/usrp_tasks.v b/tb/usrp_tasks.v index 00f82b9e1..93395f96a 100755 --- a/tb/usrp_tasks.v +++ b/tb/usrp_tasks.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Tasks diff --git a/toplevel/mrfm/mrfm.py b/toplevel/mrfm/mrfm.py index 0ce46012d..414f5817e 100644 --- a/toplevel/mrfm/mrfm.py +++ b/toplevel/mrfm/mrfm.py @@ -19,8 +19,8 @@ # # You should have received a copy of the GNU General Public License # along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, -# Boston, MA 02111-1307, USA. +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. # from gnuradio import gr, gru diff --git a/toplevel/mrfm/mrfm.v b/toplevel/mrfm/mrfm.v index cf9d1119a..7a0e38059 100644 --- a/toplevel/mrfm/mrfm.v +++ b/toplevel/mrfm/mrfm.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Top level module for a full setup with DUCs and DDCs diff --git a/toplevel/mrfm/mrfm_fft.py b/toplevel/mrfm/mrfm_fft.py index 343ab0197..9ca867082 100755 --- a/toplevel/mrfm/mrfm_fft.py +++ b/toplevel/mrfm/mrfm_fft.py @@ -19,8 +19,8 @@ # # You should have received a copy of the GNU General Public License # along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 59 Temple Place - Suite 330, -# Boston, MA 02111-1307, USA. +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. # from gnuradio import gr, gru diff --git a/toplevel/mrfm/shifter.v b/toplevel/mrfm/shifter.v index 08d49db6e..dd4d4b527 100644 --- a/toplevel/mrfm/shifter.v +++ b/toplevel/mrfm/shifter.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module shifter(input wire [33:0] in, output wire [15:0] out, input wire [7:0] shift); diff --git a/toplevel/sizetest/sizetest.v b/toplevel/sizetest/sizetest.v index cdbd0861a..5a847b961 100644 --- a/toplevel/sizetest/sizetest.v +++ b/toplevel/sizetest/sizetest.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/toplevel/usrp_multi/usrp_multi.v b/toplevel/usrp_multi/usrp_multi.v index b27d3d3a6..e3706d71b 100644 --- a/toplevel/usrp_multi/usrp_multi.v +++ b/toplevel/usrp_multi/usrp_multi.v @@ -17,7 +17,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Top level module for a full setup with DUCs and DDCs diff --git a/toplevel/usrp_multi/usrp_multi.vh b/toplevel/usrp_multi/usrp_multi.vh index 2904a9352..fb5dc8d1f 100644 --- a/toplevel/usrp_multi/usrp_multi.vh +++ b/toplevel/usrp_multi/usrp_multi.vh @@ -17,7 +17,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // ==================================================================== diff --git a/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh index 26a41e4d0..3c471463f 100644 --- a/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh +++ b/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh @@ -17,7 +17,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // `define MULTI_ON // ------------------------------------------------------------ diff --git a/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh index 0673d9600..43ed8e638 100644 --- a/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh +++ b/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh @@ -17,7 +17,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // `define MULTI_ON // ------------------------------------------------------------ diff --git a/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh index 80c7fbdcb..9ec92a4ec 100644 --- a/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh +++ b/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh @@ -17,7 +17,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // `define MULTI_ON // ------------------------------------------------------------ diff --git a/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh index 36176be4a..42549befd 100644 --- a/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh +++ b/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh @@ -17,7 +17,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // `define MULTI_ON // ------------------------------------------------------------ diff --git a/toplevel/usrp_multi/usrp_std.vh b/toplevel/usrp_multi/usrp_std.vh index 189cf14b8..2732a1992 100644 --- a/toplevel/usrp_multi/usrp_std.vh +++ b/toplevel/usrp_multi/usrp_std.vh @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // ==================================================================== diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v index 9ba8c7c65..ea556d70f 100644 --- a/toplevel/usrp_std/usrp_std.v +++ b/toplevel/usrp_std/usrp_std.v @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Top level module for a full setup with DUCs and DDCs diff --git a/toplevel/usrp_std/usrp_std.vh b/toplevel/usrp_std/usrp_std.vh index 65aed9b43..5c239f75e 100644 --- a/toplevel/usrp_std/usrp_std.vh +++ b/toplevel/usrp_std/usrp_std.vh @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // ==================================================================== diff --git a/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh index 74f1bfd1c..fc30a5417 100644 --- a/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh +++ b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // ------------------------------------------------------------ diff --git a/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh index 0bd188778..e6a662a43 100644 --- a/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh +++ b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh @@ -16,7 +16,7 @@ // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // ------------------------------------------------------------ -- cgit v1.2.3 From 001b83a02dfe7757ac5c8bf67ff73aaa8330ef92 Mon Sep 17 00:00:00 2001 From: eb Date: Wed, 27 Sep 2006 06:29:48 +0000 Subject: New rbfs. These were compiled using Quartus 6.0 sp1 and include the post-ADC / pre-DDC digital rssi measurement code. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3667 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 175896 -> 176948 bytes rbf/rev2/std_4rx_0tx.rbf | Bin 171213 -> 173865 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 175896 -> 176948 bytes rbf/rev4/std_4rx_0tx.rbf | Bin 171213 -> 173865 bytes 4 files changed, 0 insertions(+), 0 deletions(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 80f336c9d..44fd06f77 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev2/std_4rx_0tx.rbf b/rbf/rev2/std_4rx_0tx.rbf index 7dc16e24a..e8a8b6ee9 100755 Binary files a/rbf/rev2/std_4rx_0tx.rbf and b/rbf/rev2/std_4rx_0tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 80f336c9d..44fd06f77 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_4rx_0tx.rbf b/rbf/rev4/std_4rx_0tx.rbf index 7dc16e24a..e8a8b6ee9 100755 Binary files a/rbf/rev4/std_4rx_0tx.rbf and b/rbf/rev4/std_4rx_0tx.rbf differ -- cgit v1.2.3 From 22c092f08b0ea96cb973b0556b81c46a9b94ace9 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Wed, 4 Oct 2006 19:08:50 +0000 Subject: Partial fix for ticket:81 git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3709 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.extra | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile.extra b/Makefile.extra index c3ccaa043..921781190 100644 --- a/Makefile.extra +++ b/Makefile.extra @@ -91,6 +91,7 @@ EXTRA_DIST = \ sdr_lib/ram16.v \ sdr_lib/ram32.v \ sdr_lib/ram64.v \ + sdr_lib/rssi.v \ sdr_lib/rx_buffer.v \ sdr_lib/rx_chain.v \ sdr_lib/rx_chain_dual.v \ -- cgit v1.2.3 From a4c4926c39831e6eb6d405e3630b1a0b0455310c Mon Sep 17 00:00:00 2001 From: matt Date: Wed, 1 Nov 2006 23:36:51 +0000 Subject: optimized halfband coefficients, courtesy of Larry Doolittle git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3917 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/hb/coeff_rom.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/sdr_lib/hb/coeff_rom.v b/sdr_lib/hb/coeff_rom.v index c287eaaad..7f8886b4e 100644 --- a/sdr_lib/hb/coeff_rom.v +++ b/sdr_lib/hb/coeff_rom.v @@ -4,14 +4,14 @@ module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); always @(posedge clock) case (addr) - 3'd0 : data <= #1 -16'd16; - 3'd1 : data <= #1 16'd74; - 3'd2 : data <= #1 -16'd254; - 3'd3 : data <= #1 16'd669; - 3'd4 : data <= #1 -16'd1468; - 3'd5 : data <= #1 16'd2950; - 3'd6 : data <= #1 -16'd6158; - 3'd7 : data <= #1 16'd20585; + 3'd0 : data <= #1 -16'd49; + 3'd1 : data <= #1 16'd165; + 3'd2 : data <= #1 -16'd412; + 3'd3 : data <= #1 16'd873; + 3'd4 : data <= #1 -16'd1681; + 3'd5 : data <= #1 16'd3135; + 3'd6 : data <= #1 -16'd6282; + 3'd7 : data <= #1 16'd20628; endcase // case(addr) endmodule // coeff_rom -- cgit v1.2.3 From 5d3a381e708900d69059bbded94993a5c52a454f Mon Sep 17 00:00:00 2001 From: matt Date: Mon, 20 Nov 2006 02:41:19 +0000 Subject: latest version of quartus git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4004 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std.qsf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index 51d7e1ea2..1503c8cc6 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2" +set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1" # Pin & Location Assignments # ========================== -- cgit v1.2.3 From 0e54e0523398c4b607a853bb502fc9073fdaf7b4 Mon Sep 17 00:00:00 2001 From: eb Date: Sun, 14 Jan 2007 21:03:40 +0000 Subject: removed unused/out-of-date bus_interface.v git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4277 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.extra | 1 - sdr_lib/bus_interface.v | 213 ------------------------------------------------ 2 files changed, 214 deletions(-) delete mode 100755 sdr_lib/bus_interface.v diff --git a/Makefile.extra b/Makefile.extra index 921781190..0a9949629 100644 --- a/Makefile.extra +++ b/Makefile.extra @@ -59,7 +59,6 @@ EXTRA_DIST = \ models/ssram.v \ sdr_lib/adc_interface.v \ sdr_lib/bidir_reg.v \ - sdr_lib/bus_interface.v \ sdr_lib/cic_decim.v \ sdr_lib/cic_int_shifter.v \ sdr_lib/cic_interp.v \ diff --git a/sdr_lib/bus_interface.v b/sdr_lib/bus_interface.v deleted file mode 100755 index b326889c0..000000000 --- a/sdr_lib/bus_interface.v +++ /dev/null @@ -1,213 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Interface to Cypress FX2 bus -// A packet is 512 Bytes. Each fifo line is 4 bytes -// Fifo has 1024 or 2048 lines - -module bus_interface - ( input usbclk, - input reset, - inout [15:0] usbdata, // TRISTATE - input wire [5:0] usbctl, - output wire [5:0] usbrdy, - output [31:0] txdata, - input [31:0] rxdata, - input txclk, - input txstrobe, - input rxclk, - input rxstrobe, - output [11:0] debugbus, - input clear_status - ); - - parameter IN_CHANNELS = 1; - parameter OUT_CHANNELS = 1; - parameter bitmask = (IN_CHANNELS*2)-1; - - wire have_space, have_pkt_rdy; - wire WR, RD, OE; - reg tx_underrun, rx_overrun; - - assign WR = usbctl[0]; - assign RD = usbctl[1]; - assign OE = usbctl[2]; - - assign usbrdy[0] = have_space; - assign usbrdy[1] = have_pkt_rdy; - assign usbrdy[2] = tx_underrun; - assign usbrdy[3] = rx_overrun; - - reg [IN_CHANNELS*2*16-1:0] fifo_in; - wire [OUT_CHANNELS*2*16-1:0] fifo_out; - - wire [15:0] usbdata_in = usbdata; - - reg select_out; - reg select_in; - - reg commit; - reg rd_next; - reg [15:0] usbdata_out; - wire [10:0] txfifolevel,rxfifolevel; - reg [8:0] write_count; - wire tx_empty; - wire tx_full; - wire rx_empty; - wire rx_full; - wire [31:0] txd; - wire rdreq; - - // Tri-state bus macro - bustri bustri(.data(usbdata_out), - .enabledt(OE), - .tridata(usbdata) ); - - ////////////////////////////////////////////// - // TX Side (USB --> DAC) - always @(posedge usbclk, posedge reset) - begin - if(reset) - begin - fifo_in <= #1 0; - write_count <= #1 0; - end - else - if(WR & ~write_count[8]) - begin - case(write_count[0]) - 1'b0 : fifo_in[31:16] <= #1 usbdata_in; // I - 1'b1 : fifo_in[15:0] <= #1 usbdata_in; // Q - endcase - write_count <= #1 write_count + 9'd1; - end - else - write_count <= #1 WR ? write_count : 9'b0; - end - - always @(posedge usbclk) - if(reset) - commit <= #1 1'b0; - else - if(write_count[0] && ~write_count[8] && WR) - commit <= #1 1'b1; - else - commit <= #1 1'b0; - - assign rdreq = txstrobe & !tx_empty; - assign txdata = tx_empty ? 32'b0 : txd; - - always @(posedge txclk) - if(reset) - tx_underrun <= 1'b0; - else if(txstrobe & tx_empty) - tx_underrun <= 1'b1; - else if(clear_status) - tx_underrun <= 1'b0; - - fifo_1c_2k txfifo (.data ( fifo_in ), - .wrreq ( commit ), - .wrclk ( usbclk ), - - .q ( txd ), - .rdreq ( rdreq), - .rdclk ( txclk ), - - .aclr ( reset ), - - .rdempty ( tx_empty ), - .rdusedw ( ), - .wrfull ( tx_full ), - .wrusedw ( txfifolevel ) - ); - - assign have_space = (txfifolevel <= (2048-128)); - - ////////////////////////////// - // Receive FIFO (ADC --> USB) - - always @(posedge rxclk) - if(reset) - rx_overrun <= 1'b0; - else if(rxstrobe & rx_full) - rx_overrun <= 1'b1; - else if(clear_status) - rx_overrun <= 1'b0; - - always @(select_out, fifo_out) - case(select_out) - 0 : usbdata_out = fifo_out[31:16]; // I - 1 : usbdata_out = fifo_out[15:0]; // Q - endcase - -/* - always @(posedge usbclk, posedge reset) - if(reset) - usbdata_out <= #1 16'b0; - else - if(select_out) - usbdata_out = fifo_out[31:16]; - else - usbdata_out = fifo_out[15:0]; - */ - - always @(negedge usbclk, posedge reset) - if(reset) - select_out <= #1 1'b0; - else if(~RD) - select_out <= #1 1'b0; - else - select_out <= #1 ~select_out; - - fifo_1c_2k rxfifo (.data ( rxdata ), // counter ), - .wrreq (rxstrobe & ~rx_full ), - .wrclk ( rxclk ), - - .q ( fifo_out ), - .rdreq ( select_out ),// & RD ), // FIXME - .rdclk ( usbclk ), - - .aclr ( reset ), - - .rdempty ( rx_empty ), - .rdusedw ( rxfifolevel ), - .wrfull ( rx_full ), - .wrusedw ( ) - ); - - assign have_pkt_rdy = (rxfifolevel >= 128); - - // Debugging Aids - assign debugbus[0] = tx_underrun; - assign debugbus[1] = rx_overrun; - assign debugbus[2] = tx_empty; - assign debugbus[3] = tx_full; - assign debugbus[4] = rx_empty; - assign debugbus[5] = rx_full; - assign debugbus[6] = txstrobe; - assign debugbus[7] = rxstrobe; - assign debugbus[8] = select_out; - assign debugbus[9] = rxstrobe & ~rx_full; - assign debugbus[10] = have_space; - assign debugbus[11] = have_pkt_rdy; - -endmodule // bus_interface - -- cgit v1.2.3 From 706545cb6c084d8595e9ffe53fd623b8dfc49c12 Mon Sep 17 00:00:00 2001 From: eb Date: Wed, 17 Jan 2007 22:44:13 +0000 Subject: Applied patch from Brett Trotter that stuffs zeros into the head of the tx signal processing pipeline when the Tx FIFO is empty. This results in the DACs outputing zeros when there's no data, unless the tx pipeline is disabled on the host. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4287 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 176948 -> 177079 bytes rbf/rev2/std_4rx_0tx.rbf | Bin 173865 -> 174171 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 176948 -> 177079 bytes rbf/rev4/std_4rx_0tx.rbf | Bin 173865 -> 174171 bytes sdr_lib/tx_buffer.v | 20 ++++++++++---------- toplevel/usrp_std/usrp_std.qsf | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 44fd06f77..966bae865 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev2/std_4rx_0tx.rbf b/rbf/rev2/std_4rx_0tx.rbf index e8a8b6ee9..a5a5cf99d 100755 Binary files a/rbf/rev2/std_4rx_0tx.rbf and b/rbf/rev2/std_4rx_0tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 44fd06f77..966bae865 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_4rx_0tx.rbf b/rbf/rev4/std_4rx_0tx.rbf index e8a8b6ee9..a5a5cf99d 100755 Binary files a/rbf/rev4/std_4rx_0tx.rbf and b/rbf/rev4/std_4rx_0tx.rbf differ diff --git a/sdr_lib/tx_buffer.v b/sdr_lib/tx_buffer.v index ff8fd839d..63202c9df 100644 --- a/sdr_lib/tx_buffer.v +++ b/sdr_lib/tx_buffer.v @@ -66,20 +66,20 @@ module tx_buffer load_next <= #1 4'd0; end else - if((load_next != channels) & !tx_empty) + if(load_next != channels) begin load_next <= #1 load_next + 4'd1; case(load_next) - 4'd0 : tx_i_0 <= #1 fifodata; - 4'd1 : tx_q_0 <= #1 fifodata; - 4'd2 : tx_i_1 <= #1 fifodata; - 4'd3 : tx_q_1 <= #1 fifodata; - 4'd4 : tx_i_2 <= #1 fifodata; - 4'd5 : tx_q_2 <= #1 fifodata; - 4'd6 : tx_i_3 <= #1 fifodata; - 4'd7 : tx_q_3 <= #1 fifodata; + 4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata; + 4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata; + 4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata; + 4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata; + 4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata; + 4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata; + 4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata; + 4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata; endcase // case(load_next) - end // if ((load_next != channels) & !tx_empty) + end // if (load_next != channels) else if(txstrobe & (load_next == channels)) begin load_next <= #1 4'd0; diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index 1503c8cc6..8297f0f7b 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1" +set_global_assignment -name LAST_QUARTUS_VERSION 6.1 # Pin & Location Assignments # ========================== -- cgit v1.2.3 From 77c59427041d9b3e3796178aa92ac29433c8a537 Mon Sep 17 00:00:00 2001 From: eb Date: Mon, 26 Feb 2007 23:56:39 +0000 Subject: fixed comment git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4655 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh index fc30a5417..4d51a2049 100644 --- a/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh +++ b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh @@ -37,7 +37,7 @@ //`define TX_HB_ON // ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* transmit circuitry built +// IF RX_ON is not defined, there is *no* receive circuitry built `define RX_ON // ------------------------------------------------------------ -- cgit v1.2.3 From a344417b9510e111f9b37b09c83545f08b0123c1 Mon Sep 17 00:00:00 2001 From: eb Date: Mon, 26 Feb 2007 23:57:36 +0000 Subject: fixed comment git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4656 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std_config_4rx_0tx.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh index e6a662a43..2bc713822 100644 --- a/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh +++ b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh @@ -37,7 +37,7 @@ //`define TX_HB_ON // ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* transmit circuitry built +// IF RX_ON is not defined, there is *no* receive circuitry built `define RX_ON // ------------------------------------------------------------ -- cgit v1.2.3 From 78ba89f589ac3a1e53e2767edd8811d231e13946 Mon Sep 17 00:00:00 2001 From: eb Date: Sat, 3 Mar 2007 03:49:04 +0000 Subject: updated qsf file to Quartus 6.1. No semantic changes git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4694 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std.qsf | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index 8297f0f7b..fe6773f67 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -223,7 +223,7 @@ set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name TOP_LEVEL_ENTITY usrp_std set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON # Fitter Assignments # ================== @@ -314,7 +314,7 @@ set_global_assignment -name HCPY_VREF_PINS OFF # ======================== set_global_assignment -name HUB_ENTITY_NAME SLD_HUB set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP Off +set_global_assignment -name ENABLE_SIGNALTAP OFF # LogicLock Region Assignments # ============================ @@ -326,8 +326,8 @@ set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF # Timing Assignments # ================== set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK - set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK - set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK +set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK # end CLOCK(SCLK) # --------------- @@ -338,8 +338,8 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK # Timing Assignments # ================== set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk - set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk - set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk +set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk # end CLOCK(master_clk) # --------------------- @@ -350,8 +350,8 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk # Timing Assignments # ================== set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk - set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk - set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk +set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk # end CLOCK(usbclk) # ----------------- @@ -361,9 +361,9 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk # Timing Assignments # ================== - set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK - set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk - set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk +set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK +set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk +set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk # end ENTITY(usrp_std) # -------------------- -- cgit v1.2.3 From 2a732b0122279fc795203e176c430d6f9974c66d Mon Sep 17 00:00:00 2001 From: eb Date: Sat, 3 Mar 2007 03:50:06 +0000 Subject: Add new standard configuration for 1 RX w/ half-band, 1 TX git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4695 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std.v | 12 ++++- toplevel/usrp_std/usrp_std.vh | 3 ++ toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh | 61 ++++++++++++++++++++++++++ 3 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v index ea556d70f..ad882ce16 100644 --- a/toplevel/usrp_std/usrp_std.v +++ b/toplevel/usrp_std/usrp_std.v @@ -124,7 +124,7 @@ module usrp_std //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Transmit Side `ifdef TX_ON - assign bb_tx_i0 = ch0tx; + assign bb_tx_i0 = ch0tx; assign bb_tx_q0 = ch1tx; assign bb_tx_i1 = ch2tx; assign bb_tx_q1 = ch3tx; @@ -142,17 +142,27 @@ module usrp_std .tx_empty(tx_empty), .debugbus(tx_debugbus) ); + `ifdef TX_EN_0 tx_chain tx_chain_0 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), .interpolator_strobe(strobe_interp),.freq(), .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); + `else + assign i_out_0=16'd0; + assign q_out_0=16'd0; + `endif + `ifdef TX_EN_1 tx_chain tx_chain_1 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), .interpolator_strobe(strobe_interp),.freq(), .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); + `else + assign i_out_1=16'd0; + assign q_out_1=16'd0; + `endif setting_reg #(`FR_TX_MUX) sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), diff --git a/toplevel/usrp_std/usrp_std.vh b/toplevel/usrp_std/usrp_std.vh index 5c239f75e..7b7433cd4 100644 --- a/toplevel/usrp_std/usrp_std.vh +++ b/toplevel/usrp_std/usrp_std.vh @@ -26,6 +26,9 @@ // // ==================================================================== +// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel +//`include "usrp_std_config_1rxhb_1tx.vh" + // Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels `include "usrp_std_config_2rxhb_2tx.vh" diff --git a/toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh b/toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh new file mode 100644 index 000000000..e0291924b --- /dev/null +++ b/toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built + `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_DUAL is currently valid] + `define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + + `define RX_SINGLE +//`define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON \ No newline at end of file -- cgit v1.2.3 From a67127dcd59dd7f7d58323f05ed8504faafe8c63 Mon Sep 17 00:00:00 2001 From: eb Date: Mon, 5 Mar 2007 05:00:02 +0000 Subject: Refactored FPGA *.vh files. Moved common pieces to toplevel/include. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4713 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.extra | 11 +- sdr_lib/master_control_multi.v | 2 +- sdr_lib/rx_chain.v | 3 +- toplevel/include/common_config_1rxhb_1tx.vh | 61 +++++++++ toplevel/include/common_config_2rx_0tx.vh | 61 +++++++++ toplevel/include/common_config_2rxhb_0tx.vh | 61 +++++++++ toplevel/include/common_config_2rxhb_2tx.vh | 61 +++++++++ toplevel/include/common_config_4rx_0tx.vh | 61 +++++++++ toplevel/include/common_config_bottom.vh | 104 +++++++++++++++ toplevel/usrp_multi/config.vh | 62 +++++++++ toplevel/usrp_multi/usrp_multi.qsf | 26 ++-- toplevel/usrp_multi/usrp_multi.v | 2 +- toplevel/usrp_multi/usrp_multi.vh | 141 --------------------- toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh | 62 --------- toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh | 62 --------- toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh | 62 --------- toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh | 62 --------- toplevel/usrp_multi/usrp_std.vh | 29 ----- toplevel/usrp_std/config.vh | 53 ++++++++ toplevel/usrp_std/usrp_std.qsf | 1 - toplevel/usrp_std/usrp_std.v | 2 +- toplevel/usrp_std/usrp_std.vh | 122 ------------------ toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh | 61 --------- toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh | 61 --------- toplevel/usrp_std/usrp_std_config_4rx_0tx.vh | 61 --------- 25 files changed, 544 insertions(+), 750 deletions(-) create mode 100644 toplevel/include/common_config_1rxhb_1tx.vh create mode 100644 toplevel/include/common_config_2rx_0tx.vh create mode 100644 toplevel/include/common_config_2rxhb_0tx.vh create mode 100644 toplevel/include/common_config_2rxhb_2tx.vh create mode 100644 toplevel/include/common_config_4rx_0tx.vh create mode 100644 toplevel/include/common_config_bottom.vh create mode 100644 toplevel/usrp_multi/config.vh delete mode 100644 toplevel/usrp_multi/usrp_multi.vh delete mode 100644 toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh delete mode 100644 toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh delete mode 100644 toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh delete mode 100644 toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh delete mode 100644 toplevel/usrp_multi/usrp_std.vh create mode 100644 toplevel/usrp_std/config.vh delete mode 100644 toplevel/usrp_std/usrp_std.vh delete mode 100644 toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh delete mode 100644 toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh delete mode 100644 toplevel/usrp_std/usrp_std_config_4rx_0tx.vh diff --git a/Makefile.extra b/Makefile.extra index 0a9949629..7055447a9 100644 --- a/Makefile.extra +++ b/Makefile.extra @@ -133,18 +133,11 @@ EXTRA_DIST = \ toplevel/usrp_multi/usrp_multi.qpf \ toplevel/usrp_multi/usrp_multi.qsf \ toplevel/usrp_multi/usrp_multi.v \ - toplevel/usrp_multi/usrp_multi.vh \ - toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh \ - toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh \ - toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh \ - toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh \ - toplevel/usrp_multi/usrp_std.vh \ + toplevel/usrp_multi/config.vh \ toplevel/usrp_std/usrp_std.csf \ toplevel/usrp_std/usrp_std.esf \ toplevel/usrp_std/usrp_std.psf \ toplevel/usrp_std/usrp_std.qpf \ toplevel/usrp_std/usrp_std.qsf \ toplevel/usrp_std/usrp_std.v \ - toplevel/usrp_std/usrp_std.vh \ - toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh \ - toplevel/usrp_std/usrp_std_config_4rx_0tx.vh + toplevel/usrp_std/config.vh diff --git a/sdr_lib/master_control_multi.v b/sdr_lib/master_control_multi.v index 95c4ec17e..cab96a79f 100644 --- a/sdr_lib/master_control_multi.v +++ b/sdr_lib/master_control_multi.v @@ -18,7 +18,7 @@ // along with this program; if not, write to the Free Software // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // -`include "usrp_multi.vh" +`include "config.vh" `include "../../../firmware/include/fpga_regs_common.v" `include "../../../firmware/include/fpga_regs_standard.v" // Clock, enable, and reset controls for whole system diff --git a/sdr_lib/rx_chain.v b/sdr_lib/rx_chain.v index 73c0c26ea..bc4336e41 100644 --- a/sdr_lib/rx_chain.v +++ b/sdr_lib/rx_chain.v @@ -21,7 +21,8 @@ // Following defines conditionally include RX path circuitry -`include "usrp_std.vh" +`include "config.vh" // resolved relative to project root + module rx_chain (input clock, input reset, diff --git a/toplevel/include/common_config_1rxhb_1tx.vh b/toplevel/include/common_config_1rxhb_1tx.vh new file mode 100644 index 000000000..fb2e915b1 --- /dev/null +++ b/toplevel/include/common_config_1rxhb_1tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built + `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] + `define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* receive circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + + `define RX_SINGLE +//`define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/include/common_config_2rx_0tx.vh b/toplevel/include/common_config_2rx_0tx.vh new file mode 100644 index 000000000..c97c5a32b --- /dev/null +++ b/toplevel/include/common_config_2rx_0tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* receive circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE +`define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter +//`define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/include/common_config_2rxhb_0tx.vh b/toplevel/include/common_config_2rxhb_0tx.vh new file mode 100644 index 000000000..459268b6a --- /dev/null +++ b/toplevel/include/common_config_2rxhb_0tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE + `define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/include/common_config_2rxhb_2tx.vh b/toplevel/include/common_config_2rxhb_2tx.vh new file mode 100644 index 000000000..ecf0fa03e --- /dev/null +++ b/toplevel/include/common_config_2rxhb_2tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built + `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] +//`define TX_SINGLE + `define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* receive circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE + `define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/include/common_config_4rx_0tx.vh b/toplevel/include/common_config_4rx_0tx.vh new file mode 100644 index 000000000..498419570 --- /dev/null +++ b/toplevel/include/common_config_4rx_0tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* receive circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE +//`define RX_DUAL + `define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter +//`define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/toplevel/include/common_config_bottom.vh b/toplevel/include/common_config_bottom.vh new file mode 100644 index 000000000..3129798a1 --- /dev/null +++ b/toplevel/include/common_config_bottom.vh @@ -0,0 +1,104 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006,2007 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ==================================================================== +// This is the common tail for standard configuation +// ==================================================================== +// +// >>>> DO NOT EDIT BELOW HERE <<<< +// +// N.B., *all* the remainder of the code should be conditionalized +// only in terms of: +// +// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB, +// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB, +// RX_NCO_ON, RX_CIC_ON +// ==================================================================== + +`ifdef TX_ON + + `ifdef TX_SINGLE + `define TX_EN_0 + `define TX_CAP_NCHAN 3'd1 + `endif + + `ifdef TX_DUAL + `define TX_EN_0 + `define TX_EN_1 + `define TX_CAP_NCHAN 3'd2 + `endif + + `ifdef TX_QUAD + `define TX_EN_0 + `define TX_EN_1 + `define TX_EN_2 + `define TX_EN_3 + `define TX_CAP_NCHAN 3'd4 + `endif + + `ifdef TX_HB_ON + `define TX_CAP_HB 1 + `else + `define TX_CAP_HB 0 + `endif + +`else // !ifdef TX_ON + + `define TX_CAP_NCHAN 3'd0 + `define TX_CAP_HB 0 + +`endif // !ifdef TX_ON + +// -------------------------------------------------------------------- + +`ifdef RX_ON + + `ifdef RX_SINGLE + `define RX_EN_0 + `define RX_CAP_NCHAN 3'd1 + `endif + + `ifdef RX_DUAL + `define RX_EN_0 + `define RX_EN_1 + `define RX_CAP_NCHAN 3'd2 + `endif + + `ifdef RX_QUAD + `define RX_EN_0 + `define RX_EN_1 + `define RX_EN_2 + `define RX_EN_3 + `define RX_CAP_NCHAN 3'd4 + `endif + + `ifdef RX_HB_ON + `define RX_CAP_HB 1 + `else + `define RX_CAP_HB 0 + `endif + +`else // !ifdef RX_ON + + `define RX_CAP_NCHAN 3'd0 + `define RX_CAP_HB 0 + +`endif // !ifdef RX_ON diff --git a/toplevel/usrp_multi/config.vh b/toplevel/usrp_multi/config.vh new file mode 100644 index 000000000..07011bd48 --- /dev/null +++ b/toplevel/usrp_multi/config.vh @@ -0,0 +1,62 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006,2007 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ==================================================================== +// User control over what parts get included +// +// >>>> EDIT ONLY THIS SECTION <<<< +// Uncomment only ONE configuration +// ==================================================================== + +// ==================================================================== +// FIXME drive configuration selection from the command line and/or gui +// ==================================================================== + +`define MULTI_ON // enable multi usrp configuration + +// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel +//`include "../include/common_config_1rxhb_1tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 2 transmit channels +`include "../include/common_config_2rxhb_2tx.vh" + +// Uncomment this for multi with 4 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_4rx_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels +//`include "../include/common_config_2rxhb_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_2rx_0tx.vh" + + +// Add other "known to fit" configurations here... + +// ==================================================================== +// Now include the common footer +// ==================================================================== + +`ifdef MULTI_ON + `define COUNTER_32BIT_ON +`endif + +`include "../include/common_config_bottom.vh" diff --git a/toplevel/usrp_multi/usrp_multi.qsf b/toplevel/usrp_multi/usrp_multi.qsf index e45c683af..9f0efbd83 100644 --- a/toplevel/usrp_multi/usrp_multi.qsf +++ b/toplevel/usrp_multi/usrp_multi.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1" +set_global_assignment -name LAST_QUARTUS_VERSION 6.1 # Pin & Location Assignments # ========================== @@ -223,7 +223,7 @@ set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name TOP_LEVEL_ENTITY usrp_multi set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name USER_LIBRARIES "H:\\usrp-for2.7\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON # Fitter Assignments # ================== @@ -314,7 +314,7 @@ set_global_assignment -name HCPY_VREF_PINS OFF # ======================== set_global_assignment -name HUB_ENTITY_NAME SLD_HUB set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP Off +set_global_assignment -name ENABLE_SIGNALTAP OFF # LogicLock Region Assignments # ============================ @@ -326,8 +326,8 @@ set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF # Timing Assignments # ================== set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK - set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK - set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK +set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK # end CLOCK(SCLK) # --------------- @@ -338,8 +338,8 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK # Timing Assignments # ================== set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk - set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk - set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk +set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk # end CLOCK(master_clk) # --------------------- @@ -350,8 +350,8 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk # Timing Assignments # ================== set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk - set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk - set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk +set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk # end CLOCK(usbclk) # ----------------- @@ -361,18 +361,18 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk # Timing Assignments # ================== - set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK - set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk - set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk +set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK +set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk +set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk # end ENTITY(usrp_multi) # -------------------- +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg_masked.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control_multi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE usrp_multi.vh set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v diff --git a/toplevel/usrp_multi/usrp_multi.v b/toplevel/usrp_multi/usrp_multi.v index e3706d71b..ce484fc1c 100644 --- a/toplevel/usrp_multi/usrp_multi.v +++ b/toplevel/usrp_multi/usrp_multi.v @@ -28,7 +28,7 @@ // Uncomment the following to include optional circuitry -`include "usrp_multi.vh" +`include "config.vh" `include "../../../firmware/include/fpga_regs_common.v" `include "../../../firmware/include/fpga_regs_standard.v" diff --git a/toplevel/usrp_multi/usrp_multi.vh b/toplevel/usrp_multi/usrp_multi.vh deleted file mode 100644 index fb5dc8d1f..000000000 --- a/toplevel/usrp_multi/usrp_multi.vh +++ /dev/null @@ -1,141 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// User control over what parts get included -// -// >>>> EDIT ONLY THIS SECTION <<<< -// Uncomment only ONE configuration -// ==================================================================== - -// ==== Multi usrp configurations ==== -// Uncomment this for multi with 2 rx channels (w/ halfband) & 2 transmit channels -`include "usrp_multi_config_2rxhb_2tx.vh" - -// Uncomment this for multi with 4 rx channels (w/o halfband) & 0 transmit channels -//`include "usrp_multi_config_4rx_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels -//`include "usrp_multi_config_2rxhb_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels -//`include "usrp_multi_config_2rx_0tx.vh" - -// ==== Standard configurations (no multi support) ==== -// Uncomment this for standard with 2 rx channels (w/ halfband) & 2 transmit channels -// `include "../usrp_std/usrp_std_config_2rxhb_2tx.vh" - -// Uncomment this for standard with 4 rx channels (w/o halfband) & 0 transmit channels -//`include "../usrp_std/usrp_std_config_4rx_0tx.vh" - -// Add other "known to fit" configurations here... - -// ==================================================================== -// -// >>>> DO NOT EDIT BELOW HERE <<<< -// -// [The stuff from here down is derived from the stuff included above] -// -// N.B., *all* the remainder of the code should be conditionalized -// only in terms of: -// -// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB, -// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB, -// RX_NCO_ON, RX_CIC_ON -// ==================================================================== -`ifdef MULTI_ON - `define COUNTER_32BIT_ON -`endif - -`ifdef TX_ON - - `ifdef TX_SINGLE - `define TX_EN_0 - `define TX_CAP_NCHAN 3'd1 - `endif - - `ifdef TX_DUAL - `define TX_EN_0 - `define TX_EN_1 - `define TX_CAP_NCHAN 3'd2 - `endif - - `ifdef TX_QUAD - `define TX_EN_0 - `define TX_EN_1 - `define TX_EN_2 - `define TX_EN_3 - `define TX_CAP_NCHAN 3'd4 - `endif - - `ifdef TX_HB_ON - `define TX_CAP_HB 1 - `else - `define TX_CAP_HB 0 - `endif - -`else // !ifdef TX_ON - - `define TX_CAP_NCHAN 3'd0 - `define TX_CAP_HB 0 - -`endif // !ifdef TX_ON - -// -------------------------------------------------------------------- - -`ifdef RX_ON - - `ifdef RX_SINGLE - `define RX_EN_0 - `define RX_CAP_NCHAN 3'd1 - `endif - - `ifdef RX_DUAL - `define RX_EN_0 - `define RX_EN_1 - `ifdef MULTI_ON - `define RX_CAP_NCHAN 3'd4 - `else - `define RX_CAP_NCHAN 3'd2 - `endif - `endif - - `ifdef RX_QUAD - `define RX_EN_0 - `define RX_EN_1 - `define RX_EN_2 - `define RX_EN_3 - `define RX_CAP_NCHAN 3'd4 - `endif - - `ifdef RX_HB_ON - `define RX_CAP_HB 1 - `else - `define RX_CAP_HB 0 - `endif - -`else // !ifdef RX_ON - - `define RX_CAP_NCHAN 3'd0 - `define RX_CAP_HB 0 - -`endif // !ifdef RX_ON diff --git a/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh deleted file mode 100644 index 3c471463f..000000000 --- a/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh +++ /dev/null @@ -1,62 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -`define MULTI_ON -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built -// `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_DUAL is currently valid] -//`define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* transmit circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE -`define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter -//`define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh deleted file mode 100644 index 43ed8e638..000000000 --- a/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh +++ /dev/null @@ -1,62 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -`define MULTI_ON -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built -// `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_DUAL is currently valid] -//`define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* transmit circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE - `define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter - `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh deleted file mode 100644 index 9ec92a4ec..000000000 --- a/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh +++ /dev/null @@ -1,62 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -`define MULTI_ON -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built - `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_DUAL is currently valid] -//`define TX_SINGLE - `define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* transmit circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE - `define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter - `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh deleted file mode 100644 index 42549befd..000000000 --- a/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh +++ /dev/null @@ -1,62 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -`define MULTI_ON -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built -// `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_DUAL is currently valid] -//`define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* transmit circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE -//`define RX_DUAL - `define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter -//`define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/usrp_multi/usrp_std.vh b/toplevel/usrp_multi/usrp_std.vh deleted file mode 100644 index 2732a1992..000000000 --- a/toplevel/usrp_multi/usrp_std.vh +++ /dev/null @@ -1,29 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// Do not remove or edit this file. -// This is a redirect to usrp_multi.vh -// This is needed because some common source files have a -// hardcoded `include "usrp_std.vh" -// ==================================================================== - -`include "usrp_multi.vh" diff --git a/toplevel/usrp_std/config.vh b/toplevel/usrp_std/config.vh new file mode 100644 index 000000000..f1f8ec40e --- /dev/null +++ b/toplevel/usrp_std/config.vh @@ -0,0 +1,53 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006,2007 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ==================================================================== +// User control over what parts get included +// +// >>>> EDIT ONLY THIS SECTION <<<< +// Uncomment only ONE configuration +// ==================================================================== + +// ==================================================================== +// FIXME drive configuration selection from the command line and/or gui +// ==================================================================== + +// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel +//`include "../include/common_config_1rxhb_1tx.vh" + +// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels + `include "../include/common_config_2rxhb_2tx.vh" + +// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_4rx_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels +//`include "../include/common_config_2rxhb_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_2rx_0tx.vh" + +// Add other "known to fit" configurations here... + +// ==================================================================== +// Now include the common footer +// ==================================================================== + `include "../include/common_config_bottom.vh" diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index fe6773f67..e43d39ba3 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -370,7 +370,6 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE usrp_std.vh set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v index ad882ce16..870f43769 100644 --- a/toplevel/usrp_std/usrp_std.v +++ b/toplevel/usrp_std/usrp_std.v @@ -27,7 +27,7 @@ // Uncomment the following to include optional circuitry -`include "usrp_std.vh" +`include "config.vh" `include "../../../firmware/include/fpga_regs_common.v" `include "../../../firmware/include/fpga_regs_standard.v" diff --git a/toplevel/usrp_std/usrp_std.vh b/toplevel/usrp_std/usrp_std.vh deleted file mode 100644 index 7b7433cd4..000000000 --- a/toplevel/usrp_std/usrp_std.vh +++ /dev/null @@ -1,122 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// User control over what parts get included -// -// >>>> EDIT ONLY THIS SECTION <<<< -// -// ==================================================================== - -// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel -//`include "usrp_std_config_1rxhb_1tx.vh" - -// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels - `include "usrp_std_config_2rxhb_2tx.vh" - -// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels -//`include "usrp_std_config_4rx_0tx.vh" - -// Add other "known to fit" configurations here... - -// ==================================================================== -// -// >>>> DO NOT EDIT BELOW HERE <<<< -// -// [The stuff from here down is derived from the stuff included above] -// -// N.B., *all* the remainder of the code should be conditionalized -// only in terms of: -// -// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB, -// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB, -// RX_NCO_ON, RX_CIC_ON -// ==================================================================== - -`ifdef TX_ON - - `ifdef TX_SINGLE - `define TX_EN_0 - `define TX_CAP_NCHAN 3'd1 - `endif - - `ifdef TX_DUAL - `define TX_EN_0 - `define TX_EN_1 - `define TX_CAP_NCHAN 3'd2 - `endif - - `ifdef TX_QUAD - `define TX_EN_0 - `define TX_EN_1 - `define TX_EN_2 - `define TX_EN_3 - `define TX_CAP_NCHAN 3'd4 - `endif - - `ifdef TX_HB_ON - `define TX_CAP_HB 1 - `else - `define TX_CAP_HB 0 - `endif - -`else // !ifdef TX_ON - - `define TX_CAP_NCHAN 3'd0 - `define TX_CAP_HB 0 - -`endif // !ifdef TX_ON - -// -------------------------------------------------------------------- - -`ifdef RX_ON - - `ifdef RX_SINGLE - `define RX_EN_0 - `define RX_CAP_NCHAN 3'd1 - `endif - - `ifdef RX_DUAL - `define RX_EN_0 - `define RX_EN_1 - `define RX_CAP_NCHAN 3'd2 - `endif - - `ifdef RX_QUAD - `define RX_EN_0 - `define RX_EN_1 - `define RX_EN_2 - `define RX_EN_3 - `define RX_CAP_NCHAN 3'd4 - `endif - - `ifdef RX_HB_ON - `define RX_CAP_HB 1 - `else - `define RX_CAP_HB 0 - `endif - -`else // !ifdef RX_ON - - `define RX_CAP_NCHAN 3'd0 - `define RX_CAP_HB 0 - -`endif // !ifdef RX_ON diff --git a/toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh b/toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh deleted file mode 100644 index e0291924b..000000000 --- a/toplevel/usrp_std/usrp_std_config_1rxhb_1tx.vh +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built - `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_DUAL is currently valid] - `define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* transmit circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - - `define RX_SINGLE -//`define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter - `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON \ No newline at end of file diff --git a/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh deleted file mode 100644 index 4d51a2049..000000000 --- a/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built - `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_DUAL is currently valid] -//`define TX_SINGLE - `define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* receive circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE - `define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter - `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh deleted file mode 100644 index 2bc713822..000000000 --- a/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built -// `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_DUAL is currently valid] -//`define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* receive circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE -//`define RX_DUAL - `define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter -//`define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON -- cgit v1.2.3 From 403a009a8d78ea8d6d03b6abbaf640ff082d1edc Mon Sep 17 00:00:00 2001 From: matt Date: Tue, 20 Mar 2007 01:02:25 +0000 Subject: added comments, removed dead code git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4779 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/cic_int_shifter.v | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/sdr_lib/cic_int_shifter.v b/sdr_lib/cic_int_shifter.v index fd928373b..fd148c979 100644 --- a/sdr_lib/cic_int_shifter.v +++ b/sdr_lib/cic_int_shifter.v @@ -20,25 +20,21 @@ // +// NOTE This only works for N=4, max interp rate of 128 +// NOTE signal "rate" is ONE LESS THAN the actual rate + module cic_int_shifter(rate,signal_in,signal_out); parameter bw = 16; - parameter N = 4; - parameter log2_of_max_rate = 7; - parameter maxbitgain = (N-1)*log2_of_max_rate; + parameter maxbitgain = 21; input [7:0] rate; input wire [bw+maxbitgain-1:0] signal_in; output reg [bw-1:0] signal_out; - function [2:0] log_ceil; - input [7:0] val; - log_ceil = val[6] ? 3'd7 : val[5] ? 3'd6 : val[4] ? 3'd5 : - val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; - endfunction // log_ceil - function [4:0] bitgain; input [7:0] rate; case(rate) + // Exact Cases 8'd4 : bitgain = 2*(N-1); 8'd8 : bitgain = 3*(N-1); 8'd16 : bitgain = 4*(N-1); @@ -46,6 +42,7 @@ module cic_int_shifter(rate,signal_in,signal_out); 8'd64 : bitgain = 6*(N-1); 8'd128 : bitgain = 7*(N-1); + // Nearest without overflow 8'd5 : bitgain = 7; 8'd6 : bitgain = 8; 8'd7 : bitgain = 9; @@ -90,7 +87,6 @@ module cic_int_shifter(rate,signal_in,signal_out); 5'd19 : signal_out = signal_in[19+bw-1:19]; 5'd20 : signal_out = signal_in[20+bw-1:20]; - default : signal_out = signal_in[21+bw-1:21]; endcase // case(shift) -- cgit v1.2.3 From 178228ec495c7169890c61bfd92b3ef5de1f33bd Mon Sep 17 00:00:00 2001 From: matt Date: Tue, 20 Mar 2007 01:02:46 +0000 Subject: added comment git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4780 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/strobe_gen.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sdr_lib/strobe_gen.v b/sdr_lib/strobe_gen.v index a27dda8d3..ba1a8ab28 100644 --- a/sdr_lib/strobe_gen.v +++ b/sdr_lib/strobe_gen.v @@ -19,11 +19,13 @@ // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // + + module strobe_gen ( input clock, input reset, input enable, - input [7:0] rate, + input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio input strobe_in, output wire strobe ); -- cgit v1.2.3 From 9242153cbf59db9d225f52a125746fe202485147 Mon Sep 17 00:00:00 2001 From: matt Date: Tue, 20 Mar 2007 01:03:10 +0000 Subject: allow for varying the bitwidth git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4781 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/cic_interp.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sdr_lib/cic_interp.v b/sdr_lib/cic_interp.v index 0dd621623..732f82ce0 100755 --- a/sdr_lib/cic_interp.v +++ b/sdr_lib/cic_interp.v @@ -82,7 +82,8 @@ module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_ wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1]; - cic_int_shifter cic_int_shifter(rate,signal_out_unnorm,signal_out); + cic_int_shifter #(bw) + cic_int_shifter(rate,signal_out_unnorm,signal_out); endmodule // cic_interp -- cgit v1.2.3 From c9748d38085587d037e9cd56f958c7b416b2539a Mon Sep 17 00:00:00 2001 From: matt Date: Tue, 20 Mar 2007 01:05:29 +0000 Subject: removed a parameter git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4782 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/cic_int_shifter.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/sdr_lib/cic_int_shifter.v b/sdr_lib/cic_int_shifter.v index fd148c979..33086787b 100644 --- a/sdr_lib/cic_int_shifter.v +++ b/sdr_lib/cic_int_shifter.v @@ -35,12 +35,12 @@ module cic_int_shifter(rate,signal_in,signal_out); input [7:0] rate; case(rate) // Exact Cases - 8'd4 : bitgain = 2*(N-1); - 8'd8 : bitgain = 3*(N-1); - 8'd16 : bitgain = 4*(N-1); - 8'd32 : bitgain = 5*(N-1); - 8'd64 : bitgain = 6*(N-1); - 8'd128 : bitgain = 7*(N-1); + 8'd4 : bitgain = 6; + 8'd8 : bitgain = 9; + 8'd16 : bitgain = 12; + 8'd32 : bitgain = 15; + 8'd64 : bitgain = 18; + 8'd128 : bitgain = 21; // Nearest without overflow 8'd5 : bitgain = 7; -- cgit v1.2.3 From 25d5b9c9f72f34c0bf9205c74847660ac90d3349 Mon Sep 17 00:00:00 2001 From: matt Date: Tue, 20 Mar 2007 01:23:26 +0000 Subject: if you ever tried to interpolate by 44 it didn't work. now it does. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4783 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/cic_int_shifter.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sdr_lib/cic_int_shifter.v b/sdr_lib/cic_int_shifter.v index 33086787b..a8a3276f1 100644 --- a/sdr_lib/cic_int_shifter.v +++ b/sdr_lib/cic_int_shifter.v @@ -47,7 +47,7 @@ module cic_int_shifter(rate,signal_in,signal_out); 8'd6 : bitgain = 8; 8'd7 : bitgain = 9; 8'd9,8'd10 : bitgain = 10; - 8'd12 : bitgain = 11; + 8'd11,8'd12 : bitgain = 11; 8'd13,8'd14,8'd15 : bitgain = 12; 8'd17,8'd18,8'd19,8'd20 : bitgain = 13; 8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14; -- cgit v1.2.3 From 2d3721456fb3a428136ec6054d3bf09c0645bbb5 Mon Sep 17 00:00:00 2001 From: matt Date: Tue, 20 Mar 2007 02:13:06 +0000 Subject: proper shifting for the cic decim now keeps signals roughly leveled git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4784 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/cic_dec_shifter.v | 100 +++++++++++++++++++++++++++++++++++++++++ sdr_lib/cic_decim.v | 23 ++-------- toplevel/usrp_std/usrp_std.qsf | 1 + 3 files changed, 104 insertions(+), 20 deletions(-) create mode 100644 sdr_lib/cic_dec_shifter.v diff --git a/sdr_lib/cic_dec_shifter.v b/sdr_lib/cic_dec_shifter.v new file mode 100644 index 000000000..a213303c8 --- /dev/null +++ b/sdr_lib/cic_dec_shifter.v @@ -0,0 +1,100 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// NOTE This only works for N=4, max decim rate of 128 +// NOTE signal "rate" is ONE LESS THAN the actual rate + +module cic_dec_shifter(rate,signal_in,signal_out); + parameter bw = 16; + parameter maxbitgain = 28; + + input [7:0] rate; + input wire [bw+maxbitgain-1:0] signal_in; + output reg [bw-1:0] signal_out; + + function [4:0] bitgain; + input [7:0] rate; + case(rate) + // Exact Cases -- N*log2(rate) + 8'd4 : bitgain = 8; + 8'd8 : bitgain = 12; + 8'd16 : bitgain = 16; + 8'd32 : bitgain = 20; + 8'd64 : bitgain = 24; + 8'd128 : bitgain = 28; + + // Nearest without overflow -- ceil(N*log2(rate)) + 8'd5 : bitgain = 10; + 8'd6 : bitgain = 11; + 8'd7 : bitgain = 12; + 8'd9 : bitgain = 13; + 8'd10,8'd11 : bitgain = 14; + 8'd12,8'd13 : bitgain = 15; + 8'd14,8'd15 : bitgain = 16; + 8'd17,8'd18,8'd19 : bitgain = 17; + 8'd20,8'd21,8'd22 : bitgain = 18; + 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; + 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; + 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; + 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; + 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; + 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; + 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; + 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; + 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; + default : bitgain = 28; + endcase // case(rate) + endfunction // bitgain + + wire [4:0] shift = bitgain(rate+1); + + // We should be able to do this, but can't .... + // assign signal_out = signal_in[shift+bw-1:shift]; + + always @* + case(shift) + 5'd8 : signal_out = signal_in[8+bw-1:8]; + 5'd10 : signal_out = signal_in[10+bw-1:10]; + 5'd11 : signal_out = signal_in[11+bw-1:11]; + 5'd12 : signal_out = signal_in[12+bw-1:12]; + 5'd13 : signal_out = signal_in[13+bw-1:13]; + 5'd14 : signal_out = signal_in[14+bw-1:14]; + 5'd15 : signal_out = signal_in[15+bw-1:15]; + 5'd16 : signal_out = signal_in[16+bw-1:16]; + 5'd17 : signal_out = signal_in[17+bw-1:17]; + 5'd18 : signal_out = signal_in[18+bw-1:18]; + 5'd19 : signal_out = signal_in[19+bw-1:19]; + 5'd20 : signal_out = signal_in[20+bw-1:20]; + 5'd21 : signal_out = signal_in[21+bw-1:21]; + 5'd22 : signal_out = signal_in[22+bw-1:22]; + 5'd23 : signal_out = signal_in[23+bw-1:23]; + 5'd24 : signal_out = signal_in[24+bw-1:24]; + 5'd25 : signal_out = signal_in[25+bw-1:25]; + 5'd26 : signal_out = signal_in[26+bw-1:26]; + 5'd27 : signal_out = signal_in[27+bw-1:27]; + 5'd28 : signal_out = signal_in[28+bw-1:28]; + + default : signal_out = signal_in[28+bw-1:28]; + endcase // case(shift) + +endmodule // cic_dec_shifter + diff --git a/sdr_lib/cic_decim.v b/sdr_lib/cic_decim.v index d7e5310b8..6c20416f1 100755 --- a/sdr_lib/cic_decim.v +++ b/sdr_lib/cic_decim.v @@ -24,7 +24,7 @@ module cic_decim ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out); parameter bw = 16; parameter N = 4; - parameter log2_of_max_rate = 8; + parameter log2_of_max_rate = 7; parameter maxbitgain = N * log2_of_max_rate; input clock; @@ -82,25 +82,8 @@ module cic_decim wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1]; - // Output Scaling to same width as input - function [2:0] log_ceil; - input [7:0] val; - log_ceil = val[6] ? 3'd7 : val[5] ? 3'd6 : val[4] ? 3'd5 : - val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; - endfunction // log_ceil - - wire [2:0] shift = log_ceil(rate); - - always @* - case(shift) - 3'd2 : signal_out = signal_out_unnorm[2*N+bw-1:2*N]; // Decim by 4 - 3'd3 : signal_out = signal_out_unnorm[3*N+bw-1:3*N]; - 3'd4 : signal_out = signal_out_unnorm[4*N+bw-1:4*N]; - 3'd5 : signal_out = signal_out_unnorm[5*N+bw-1:5*N]; - 3'd6 : signal_out = signal_out_unnorm[6*N+bw-1:6*N]; - 3'd7 : signal_out = signal_out_unnorm[7*N+bw-1:7*N]; - default : signal_out = signal_out_unnorm[7*N+bw-1:7*N]; - endcase // case(shift) + cic_dec_shifter #(bw) + cic_dec_shifter(rate,signal_out_unnorm,signal_out); endmodule // cic_decim diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index e43d39ba3..ad98b1165 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -368,6 +368,7 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk # end ENTITY(usrp_std) # -------------------- +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v -- cgit v1.2.3 From 9cc7ba54f445f6cdb812132b772f6c96088dedbb Mon Sep 17 00:00:00 2001 From: eb Date: Wed, 28 Mar 2007 19:00:55 +0000 Subject: copied usrp_inband_usb from -r4809 features/inband-usb into trunk git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4810 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_inband_usb/config.vh | 53 ++++ toplevel/usrp_inband_usb/usrp_inband_usb.csf | 444 +++++++++++++++++++++++++++ toplevel/usrp_inband_usb/usrp_inband_usb.esf | 14 + toplevel/usrp_inband_usb/usrp_inband_usb.psf | 312 +++++++++++++++++++ toplevel/usrp_inband_usb/usrp_inband_usb.qpf | 29 ++ toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 409 ++++++++++++++++++++++++ toplevel/usrp_inband_usb/usrp_inband_usb.v | 327 ++++++++++++++++++++ 7 files changed, 1588 insertions(+) create mode 100644 toplevel/usrp_inband_usb/config.vh create mode 100644 toplevel/usrp_inband_usb/usrp_inband_usb.csf create mode 100644 toplevel/usrp_inband_usb/usrp_inband_usb.esf create mode 100644 toplevel/usrp_inband_usb/usrp_inband_usb.psf create mode 100644 toplevel/usrp_inband_usb/usrp_inband_usb.qpf create mode 100644 toplevel/usrp_inband_usb/usrp_inband_usb.qsf create mode 100644 toplevel/usrp_inband_usb/usrp_inband_usb.v diff --git a/toplevel/usrp_inband_usb/config.vh b/toplevel/usrp_inband_usb/config.vh new file mode 100644 index 000000000..2d1929439 --- /dev/null +++ b/toplevel/usrp_inband_usb/config.vh @@ -0,0 +1,53 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006,2007 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ==================================================================== +// User control over what parts get included +// +// >>>> EDIT ONLY THIS SECTION <<<< +// Uncomment only ONE configuration +// ==================================================================== + +// ==================================================================== +// FIXME drive configuration selection from the command line and/or gui +// ==================================================================== + +// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel + `include "../include/common_config_1rxhb_1tx.vh" + +// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels +//`include "../include/common_config_2rxhb_2tx.vh" + +// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_4rx_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels +//`include "../include/common_config_2rxhb_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_2rx_0tx.vh" + +// Add other "known to fit" configurations here... + +// ==================================================================== +// Now include the common footer +// ==================================================================== + `include "../include/common_config_bottom.vh" diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.csf b/toplevel/usrp_inband_usb/usrp_inband_usb.csf new file mode 100644 index 000000000..c10cff92c --- /dev/null +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.csf @@ -0,0 +1,444 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; + OPTIMIZE_TIMING = "NORMAL COMPILATION"; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = OFF; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |usrp_inband_usb; + ROUTING_BACK_ANNOTATION_MODE = OFF; + INC_PLC_MODE = OFF; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} +CHIP(usrp_inband_usb) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; + AUTO_RESTART_CONFIGURATION = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + USER_START_UP_CLOCK = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_JTAG_BST_SUPPORT = OFF; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + USE_CONFIGURATION_DEVICE = OFF; + APEX20K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + STRATIX_UPDATE_MODE = STANDARD; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + COMPRESSION_MODE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + GENERATE_TTF_FILE = OFF; + GENERATE_RBF_FILE = ON; + GENERATE_HEX_FILE = OFF; + SECURITY_BIT = OFF; + ENABLE_VREFA_PIN = OFF; + ENABLE_VREFB_PIN = OFF; + GENERATE_SVF_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_JBC_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_HEXOUT_FILE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; + BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; + HEXOUT_FILE_START_ADDRESS = 0; + HEXOUT_FILE_COUNT_DIRECTION = UP; + RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; + STRATIX_DEVICE_IO_STANDARD = LVTTL; + CLOCK_SOURCE = INTERNAL; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CONFIGURATION_CLOCK_DIVISOR = 1; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + SCLK : LOCATION = Pin_101; + SDI : LOCATION = Pin_100; + SEN : LOCATION = Pin_98; + SLD : LOCATION = Pin_95; + adc1_data[0] : LOCATION = Pin_5; + adc1_data[10] : LOCATION = Pin_235; + adc1_data[11] : LOCATION = Pin_234; + adc1_data[1] : LOCATION = Pin_4; + adc1_data[2] : LOCATION = Pin_3; + adc1_data[3] : LOCATION = Pin_2; + adc1_data[4] : LOCATION = Pin_1; + adc1_data[4] : IO_STANDARD = LVTTL; + adc1_data[5] : LOCATION = Pin_240; + adc1_data[6] : LOCATION = Pin_239; + adc1_data[7] : LOCATION = Pin_238; + adc1_data[8] : LOCATION = Pin_237; + adc1_data[9] : LOCATION = Pin_236; + adc2_data[0] : LOCATION = Pin_20; + adc2_data[10] : LOCATION = Pin_8; + adc2_data[11] : LOCATION = Pin_7; + adc2_data[1] : LOCATION = Pin_19; + adc2_data[2] : LOCATION = Pin_18; + adc2_data[3] : LOCATION = Pin_17; + adc2_data[4] : LOCATION = Pin_16; + adc2_data[5] : LOCATION = Pin_15; + adc2_data[6] : LOCATION = Pin_14; + adc2_data[7] : LOCATION = Pin_13; + adc2_data[8] : LOCATION = Pin_12; + adc2_data[9] : LOCATION = Pin_11; + adc3_data[0] : LOCATION = Pin_200; + adc3_data[10] : LOCATION = Pin_184; + adc3_data[11] : LOCATION = Pin_183; + adc3_data[1] : LOCATION = Pin_197; + adc3_data[2] : LOCATION = Pin_196; + adc3_data[3] : LOCATION = Pin_195; + adc3_data[4] : LOCATION = Pin_194; + adc3_data[5] : LOCATION = Pin_193; + adc3_data[6] : LOCATION = Pin_188; + adc3_data[7] : LOCATION = Pin_187; + adc3_data[8] : LOCATION = Pin_186; + adc3_data[9] : LOCATION = Pin_185; + adc4_data[0] : LOCATION = Pin_222; + adc4_data[10] : LOCATION = Pin_203; + adc4_data[11] : LOCATION = Pin_202; + adc4_data[1] : LOCATION = Pin_219; + adc4_data[2] : LOCATION = Pin_217; + adc4_data[3] : LOCATION = Pin_216; + adc4_data[4] : LOCATION = Pin_215; + adc4_data[5] : LOCATION = Pin_214; + adc4_data[6] : LOCATION = Pin_213; + adc4_data[7] : LOCATION = Pin_208; + adc4_data[8] : LOCATION = Pin_207; + adc4_data[9] : LOCATION = Pin_206; + adc_oeb[0] : LOCATION = Pin_228; + adc_oeb[1] : LOCATION = Pin_21; + adc_oeb[2] : LOCATION = Pin_181; + adc_oeb[3] : LOCATION = Pin_218; + adc_otr[0] : LOCATION = Pin_233; + adc_otr[1] : LOCATION = Pin_6; + adc_otr[2] : LOCATION = Pin_182; + adc_otr[3] : LOCATION = Pin_201; + adclk0 : LOCATION = Pin_224; + adclk1 : LOCATION = Pin_226; + clk0 : LOCATION = Pin_28; + clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk0 : IO_STANDARD = LVTTL; + clk1 : LOCATION = Pin_29; + clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk1 : IO_STANDARD = LVTTL; + clk3 : LOCATION = Pin_152; + clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk3 : IO_STANDARD = LVTTL; + clk_120mhz : LOCATION = Pin_153; + clk_120mhz : IO_STANDARD = LVTTL; + clk_out : LOCATION = Pin_63; + clk_out : IO_STANDARD = LVTTL; + dac1_data[0] : LOCATION = Pin_165; + dac1_data[10] : LOCATION = Pin_177; + dac1_data[11] : LOCATION = Pin_178; + dac1_data[12] : LOCATION = Pin_179; + dac1_data[13] : LOCATION = Pin_180; + dac1_data[1] : LOCATION = Pin_166; + dac1_data[2] : LOCATION = Pin_167; + dac1_data[3] : LOCATION = Pin_168; + dac1_data[4] : LOCATION = Pin_169; + dac1_data[5] : LOCATION = Pin_170; + dac1_data[6] : LOCATION = Pin_173; + dac1_data[7] : LOCATION = Pin_174; + dac1_data[8] : LOCATION = Pin_175; + dac1_data[9] : LOCATION = Pin_176; + dac2_data[0] : LOCATION = Pin_159; + dac2_data[10] : LOCATION = Pin_163; + dac2_data[11] : LOCATION = Pin_139; + dac2_data[12] : LOCATION = Pin_164; + dac2_data[13] : LOCATION = Pin_138; + dac2_data[1] : LOCATION = Pin_158; + dac2_data[2] : LOCATION = Pin_160; + dac2_data[3] : LOCATION = Pin_156; + dac2_data[4] : LOCATION = Pin_161; + dac2_data[5] : LOCATION = Pin_144; + dac2_data[6] : LOCATION = Pin_162; + dac2_data[7] : LOCATION = Pin_141; + dac2_data[8] : LOCATION = Pin_143; + dac2_data[9] : LOCATION = Pin_140; + dac3_data[0] : LOCATION = Pin_122; + dac3_data[10] : LOCATION = Pin_134; + dac3_data[11] : LOCATION = Pin_135; + dac3_data[12] : LOCATION = Pin_136; + dac3_data[13] : LOCATION = Pin_137; + dac3_data[1] : LOCATION = Pin_123; + dac3_data[2] : LOCATION = Pin_124; + dac3_data[3] : LOCATION = Pin_125; + dac3_data[4] : LOCATION = Pin_126; + dac3_data[5] : LOCATION = Pin_127; + dac3_data[6] : LOCATION = Pin_128; + dac3_data[7] : LOCATION = Pin_131; + dac3_data[8] : LOCATION = Pin_132; + dac3_data[9] : LOCATION = Pin_133; + dac4_data[0] : LOCATION = Pin_104; + dac4_data[10] : LOCATION = Pin_118; + dac4_data[11] : LOCATION = Pin_119; + dac4_data[12] : LOCATION = Pin_120; + dac4_data[13] : LOCATION = Pin_121; + dac4_data[1] : LOCATION = Pin_105; + dac4_data[2] : LOCATION = Pin_106; + dac4_data[3] : LOCATION = Pin_107; + dac4_data[4] : LOCATION = Pin_108; + dac4_data[5] : LOCATION = Pin_113; + dac4_data[6] : LOCATION = Pin_114; + dac4_data[7] : LOCATION = Pin_115; + dac4_data[8] : LOCATION = Pin_116; + dac4_data[9] : LOCATION = Pin_117; + enable_rx : LOCATION = Pin_88; + enable_tx : LOCATION = Pin_93; + gndbus[0] : LOCATION = Pin_223; + gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[0] : IO_STANDARD = LVTTL; + gndbus[1] : LOCATION = Pin_225; + gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[1] : IO_STANDARD = LVTTL; + gndbus[2] : LOCATION = Pin_227; + gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[2] : IO_STANDARD = LVTTL; + gndbus[3] : LOCATION = Pin_62; + gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[3] : IO_STANDARD = LVTTL; + gndbus[4] : LOCATION = Pin_64; + gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[4] : IO_STANDARD = LVTTL; + misc_pins[0] : LOCATION = Pin_87; + misc_pins[0] : IO_STANDARD = LVTTL; + misc_pins[10] : LOCATION = Pin_76; + misc_pins[10] : IO_STANDARD = LVTTL; + misc_pins[11] : LOCATION = Pin_74; + misc_pins[11] : IO_STANDARD = LVTTL; + misc_pins[1] : LOCATION = Pin_86; + misc_pins[1] : IO_STANDARD = LVTTL; + misc_pins[2] : LOCATION = Pin_85; + misc_pins[2] : IO_STANDARD = LVTTL; + misc_pins[3] : LOCATION = Pin_84; + misc_pins[3] : IO_STANDARD = LVTTL; + misc_pins[4] : LOCATION = Pin_83; + misc_pins[4] : IO_STANDARD = LVTTL; + misc_pins[5] : LOCATION = Pin_82; + misc_pins[5] : IO_STANDARD = LVTTL; + misc_pins[6] : LOCATION = Pin_79; + misc_pins[6] : IO_STANDARD = LVTTL; + misc_pins[7] : LOCATION = Pin_78; + misc_pins[7] : IO_STANDARD = LVTTL; + misc_pins[8] : LOCATION = Pin_77; + misc_pins[8] : IO_STANDARD = LVTTL; + misc_pins[9] : LOCATION = Pin_75; + misc_pins[9] : IO_STANDARD = LVTTL; + reset : LOCATION = Pin_94; + usbclk : LOCATION = Pin_55; + usbctl[0] : LOCATION = Pin_56; + usbctl[1] : LOCATION = Pin_54; + usbctl[2] : LOCATION = Pin_53; + usbctl[3] : LOCATION = Pin_58; + usbctl[4] : LOCATION = Pin_57; + usbctl[5] : LOCATION = Pin_44; + usbdata[0] : LOCATION = Pin_73; + usbdata[10] : LOCATION = Pin_41; + usbdata[11] : LOCATION = Pin_39; + usbdata[12] : LOCATION = Pin_38; + usbdata[12] : IO_STANDARD = LVTTL; + usbdata[13] : LOCATION = Pin_37; + usbdata[14] : LOCATION = Pin_24; + usbdata[15] : LOCATION = Pin_23; + usbdata[1] : LOCATION = Pin_68; + usbdata[2] : LOCATION = Pin_67; + usbdata[3] : LOCATION = Pin_66; + usbdata[4] : LOCATION = Pin_65; + usbdata[5] : LOCATION = Pin_61; + usbdata[6] : LOCATION = Pin_60; + usbdata[7] : LOCATION = Pin_59; + usbdata[8] : LOCATION = Pin_43; + usbdata[9] : LOCATION = Pin_42; + usbrdy[0] : LOCATION = Pin_45; + usbrdy[1] : LOCATION = Pin_46; + usbrdy[2] : LOCATION = Pin_47; + usbrdy[3] : LOCATION = Pin_48; + usbrdy[4] : LOCATION = Pin_49; + usbrdy[5] : LOCATION = Pin_50; + clear_status : LOCATION = Pin_99; +} diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.esf b/toplevel/usrp_inband_usb/usrp_inband_usb.esf new file mode 100644 index 000000000..6079e9795 --- /dev/null +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.esf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = usrp_inband_usb; +} diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.psf b/toplevel/usrp_inband_usb/usrp_inband_usb.psf new file mode 100644 index 000000000..85276ecc4 --- /dev/null +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.psf @@ -0,0 +1,312 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_DSP_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_TURBO_BIT = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_PARALLEL_EXPANDERS = ON; + AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; + AUTO_FAST_OUTPUT_REGISTERS = OFF; + AUTO_FAST_INPUT_REGISTERS = OFF; + AUTO_CASCADE_CHAINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; + PARALLEL_EXPANDER_CHAIN_LENGTH = 16; + CASCADE_CHAIN_LENGTH = 2; + STRATIX_CARRY_CHAIN_LENGTH = 70; + MERCURY_CARRY_CHAIN_LENGTH = 48; + FLEX10K_CARRY_CHAIN_LENGTH = 32; + FLEX6K_CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN_LENGTH = 48; + CARRY_OUT_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + AUTO_LCELL_INSERTION = ON; + ALLOW_XOR_GATE_USAGE = ON; + AUTO_PACKED_REGISTERS_STRATIX = NORMAL; + AUTO_PACKED_REGISTERS = OFF; + AUTO_PACKED_REG_CYCLONE = NORMAL; + FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; + FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; + MERCURY_OPTIMIZATION_TECHNIQUE = AREA; + APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; + MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; + STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; + CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; + FLEX10K_TECHNOLOGY_MAPPER = LUT; + FLEX6K_TECHNOLOGY_MAPPER = LUT; + MERCURY_TECHNOLOGY_MAPPER = LUT; + APEX20K_TECHNOLOGY_MAPPER = LUT; + MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; + STRATIX_TECHNOLOGY_MAPPER = LUT; + AUTO_IMPLEMENT_IN_ROM = OFF; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_CLOCK = ON; + USE_LPM_FOR_AHDL_OPERATORS = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + TURBO_BIT = ON; + MAX7000_IGNORE_SOFT_BUFFERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MAX7000_IGNORE_LCELL_BUFFERS = AUTO; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + DSP_BLOCK_BALANCING = AUTO; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(usrp_inband_usb) +{ + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; + USER_LIBRARIES = "e:\usrp\fpga\megacells"; +} +THIRD_PARTY_EDA_TOOLS(usrp_inband_usb) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} +CLOCK(clk_120mhz) +{ + FMAX_REQUIREMENT = "120.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(usbclk) +{ + FMAX_REQUIREMENT = "48.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(SCLK) +{ + FMAX_REQUIREMENT = "1.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk0) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk1) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qpf b/toplevel/usrp_inband_usb/usrp_inband_usb.qpf new file mode 100644 index 000000000..f6220e320 --- /dev/null +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.qpf @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2004 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.0" +DATE = "17:10:11 December 20, 2004" + + +# Active Revisions + +PROJECT_REVISION = "usrp_inband_usb" diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf new file mode 100644 index 000000000..2646d831f --- /dev/null +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -0,0 +1,409 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# usrp_inband_usb_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" +set_global_assignment -name LAST_QUARTUS_VERSION 6.1 + +# Pin & Location Assignments +# ========================== +set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" +set_location_assignment PIN_29 -to SCLK +set_location_assignment PIN_117 -to SDI +set_location_assignment PIN_28 -to usbclk +set_location_assignment PIN_107 -to usbctl[0] +set_location_assignment PIN_106 -to usbctl[1] +set_location_assignment PIN_105 -to usbctl[2] +set_location_assignment PIN_100 -to usbdata[0] +set_location_assignment PIN_84 -to usbdata[10] +set_location_assignment PIN_83 -to usbdata[11] +set_location_assignment PIN_82 -to usbdata[12] +set_location_assignment PIN_79 -to usbdata[13] +set_location_assignment PIN_78 -to usbdata[14] +set_location_assignment PIN_77 -to usbdata[15] +set_location_assignment PIN_99 -to usbdata[1] +set_location_assignment PIN_98 -to usbdata[2] +set_location_assignment PIN_95 -to usbdata[3] +set_location_assignment PIN_94 -to usbdata[4] +set_location_assignment PIN_93 -to usbdata[5] +set_location_assignment PIN_88 -to usbdata[6] +set_location_assignment PIN_87 -to usbdata[7] +set_location_assignment PIN_86 -to usbdata[8] +set_location_assignment PIN_85 -to usbdata[9] +set_location_assignment PIN_104 -to usbrdy[0] +set_location_assignment PIN_101 -to usbrdy[1] +set_location_assignment PIN_76 -to FX2_1 +set_location_assignment PIN_75 -to FX2_2 +set_location_assignment PIN_74 -to FX2_3 +set_location_assignment PIN_116 -to io_rx_a[0] +set_location_assignment PIN_115 -to io_rx_a[1] +set_location_assignment PIN_114 -to io_rx_a[2] +set_location_assignment PIN_113 -to io_rx_a[3] +set_location_assignment PIN_108 -to io_rx_a[4] +set_location_assignment PIN_195 -to io_rx_a[5] +set_location_assignment PIN_196 -to io_rx_a[6] +set_location_assignment PIN_197 -to io_rx_a[7] +set_location_assignment PIN_200 -to io_rx_a[8] +set_location_assignment PIN_201 -to io_rx_a[9] +set_location_assignment PIN_202 -to io_rx_a[10] +set_location_assignment PIN_203 -to io_rx_a[11] +set_location_assignment PIN_206 -to io_rx_a[12] +set_location_assignment PIN_207 -to io_rx_a[13] +set_location_assignment PIN_208 -to io_rx_a[14] +set_location_assignment PIN_214 -to io_rx_b[0] +set_location_assignment PIN_215 -to io_rx_b[1] +set_location_assignment PIN_216 -to io_rx_b[2] +set_location_assignment PIN_217 -to io_rx_b[3] +set_location_assignment PIN_218 -to io_rx_b[4] +set_location_assignment PIN_219 -to io_rx_b[5] +set_location_assignment PIN_222 -to io_rx_b[6] +set_location_assignment PIN_223 -to io_rx_b[7] +set_location_assignment PIN_224 -to io_rx_b[8] +set_location_assignment PIN_225 -to io_rx_b[9] +set_location_assignment PIN_226 -to io_rx_b[10] +set_location_assignment PIN_227 -to io_rx_b[11] +set_location_assignment PIN_228 -to io_rx_b[12] +set_location_assignment PIN_233 -to io_rx_b[13] +set_location_assignment PIN_234 -to io_rx_b[14] +set_location_assignment PIN_175 -to io_tx_a[0] +set_location_assignment PIN_176 -to io_tx_a[1] +set_location_assignment PIN_177 -to io_tx_a[2] +set_location_assignment PIN_178 -to io_tx_a[3] +set_location_assignment PIN_179 -to io_tx_a[4] +set_location_assignment PIN_180 -to io_tx_a[5] +set_location_assignment PIN_181 -to io_tx_a[6] +set_location_assignment PIN_182 -to io_tx_a[7] +set_location_assignment PIN_183 -to io_tx_a[8] +set_location_assignment PIN_184 -to io_tx_a[9] +set_location_assignment PIN_185 -to io_tx_a[10] +set_location_assignment PIN_186 -to io_tx_a[11] +set_location_assignment PIN_187 -to io_tx_a[12] +set_location_assignment PIN_188 -to io_tx_a[13] +set_location_assignment PIN_193 -to io_tx_a[14] +set_location_assignment PIN_73 -to io_tx_b[0] +set_location_assignment PIN_68 -to io_tx_b[1] +set_location_assignment PIN_67 -to io_tx_b[2] +set_location_assignment PIN_66 -to io_tx_b[3] +set_location_assignment PIN_65 -to io_tx_b[4] +set_location_assignment PIN_64 -to io_tx_b[5] +set_location_assignment PIN_63 -to io_tx_b[6] +set_location_assignment PIN_62 -to io_tx_b[7] +set_location_assignment PIN_61 -to io_tx_b[8] +set_location_assignment PIN_60 -to io_tx_b[9] +set_location_assignment PIN_59 -to io_tx_b[10] +set_location_assignment PIN_58 -to io_tx_b[11] +set_location_assignment PIN_57 -to io_tx_b[12] +set_location_assignment PIN_56 -to io_tx_b[13] +set_location_assignment PIN_55 -to io_tx_b[14] +set_location_assignment PIN_152 -to master_clk +set_location_assignment PIN_144 -to rx_a_a[0] +set_location_assignment PIN_143 -to rx_a_a[1] +set_location_assignment PIN_141 -to rx_a_a[2] +set_location_assignment PIN_140 -to rx_a_a[3] +set_location_assignment PIN_139 -to rx_a_a[4] +set_location_assignment PIN_138 -to rx_a_a[5] +set_location_assignment PIN_137 -to rx_a_a[6] +set_location_assignment PIN_136 -to rx_a_a[7] +set_location_assignment PIN_135 -to rx_a_a[8] +set_location_assignment PIN_134 -to rx_a_a[9] +set_location_assignment PIN_133 -to rx_a_a[10] +set_location_assignment PIN_132 -to rx_a_a[11] +set_location_assignment PIN_23 -to rx_a_b[0] +set_location_assignment PIN_21 -to rx_a_b[1] +set_location_assignment PIN_20 -to rx_a_b[2] +set_location_assignment PIN_19 -to rx_a_b[3] +set_location_assignment PIN_18 -to rx_a_b[4] +set_location_assignment PIN_17 -to rx_a_b[5] +set_location_assignment PIN_16 -to rx_a_b[6] +set_location_assignment PIN_15 -to rx_a_b[7] +set_location_assignment PIN_14 -to rx_a_b[8] +set_location_assignment PIN_13 -to rx_a_b[9] +set_location_assignment PIN_12 -to rx_a_b[10] +set_location_assignment PIN_11 -to rx_a_b[11] +set_location_assignment PIN_131 -to rx_b_a[0] +set_location_assignment PIN_128 -to rx_b_a[1] +set_location_assignment PIN_127 -to rx_b_a[2] +set_location_assignment PIN_126 -to rx_b_a[3] +set_location_assignment PIN_125 -to rx_b_a[4] +set_location_assignment PIN_124 -to rx_b_a[5] +set_location_assignment PIN_123 -to rx_b_a[6] +set_location_assignment PIN_122 -to rx_b_a[7] +set_location_assignment PIN_121 -to rx_b_a[8] +set_location_assignment PIN_120 -to rx_b_a[9] +set_location_assignment PIN_119 -to rx_b_a[10] +set_location_assignment PIN_118 -to rx_b_a[11] +set_location_assignment PIN_8 -to rx_b_b[0] +set_location_assignment PIN_7 -to rx_b_b[1] +set_location_assignment PIN_6 -to rx_b_b[2] +set_location_assignment PIN_5 -to rx_b_b[3] +set_location_assignment PIN_4 -to rx_b_b[4] +set_location_assignment PIN_3 -to rx_b_b[5] +set_location_assignment PIN_2 -to rx_b_b[6] +set_location_assignment PIN_240 -to rx_b_b[7] +set_location_assignment PIN_239 -to rx_b_b[8] +set_location_assignment PIN_238 -to rx_b_b[9] +set_location_assignment PIN_237 -to rx_b_b[10] +set_location_assignment PIN_236 -to rx_b_b[11] +set_location_assignment PIN_156 -to SDO +set_location_assignment PIN_153 -to SEN_FPGA +set_location_assignment PIN_159 -to tx_a[0] +set_location_assignment PIN_160 -to tx_a[1] +set_location_assignment PIN_161 -to tx_a[2] +set_location_assignment PIN_162 -to tx_a[3] +set_location_assignment PIN_163 -to tx_a[4] +set_location_assignment PIN_164 -to tx_a[5] +set_location_assignment PIN_165 -to tx_a[6] +set_location_assignment PIN_166 -to tx_a[7] +set_location_assignment PIN_167 -to tx_a[8] +set_location_assignment PIN_168 -to tx_a[9] +set_location_assignment PIN_169 -to tx_a[10] +set_location_assignment PIN_170 -to tx_a[11] +set_location_assignment PIN_173 -to tx_a[12] +set_location_assignment PIN_174 -to tx_a[13] +set_location_assignment PIN_38 -to tx_b[0] +set_location_assignment PIN_39 -to tx_b[1] +set_location_assignment PIN_41 -to tx_b[2] +set_location_assignment PIN_42 -to tx_b[3] +set_location_assignment PIN_43 -to tx_b[4] +set_location_assignment PIN_44 -to tx_b[5] +set_location_assignment PIN_45 -to tx_b[6] +set_location_assignment PIN_46 -to tx_b[7] +set_location_assignment PIN_47 -to tx_b[8] +set_location_assignment PIN_48 -to tx_b[9] +set_location_assignment PIN_49 -to tx_b[10] +set_location_assignment PIN_50 -to tx_b[11] +set_location_assignment PIN_53 -to tx_b[12] +set_location_assignment PIN_54 -to tx_b[13] +set_location_assignment PIN_158 -to TXSYNC_A +set_location_assignment PIN_37 -to TXSYNC_B +set_location_assignment PIN_235 -to io_rx_b[15] +set_location_assignment PIN_24 -to io_tx_b[15] +set_location_assignment PIN_213 -to io_rx_a[15] +set_location_assignment PIN_194 -to io_tx_a[15] +set_location_assignment PIN_1 -to MYSTERY_SIGNAL + +# Timing Assignments +# ================== +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name TOP_LEVEL_ENTITY usrp_inband_usb +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name INC_PLC_MODE OFF +set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF +set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# Timing Analysis Assignments +# =========================== +set_global_assignment -name MAX_SCC_SIZE 50 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF + +# Simulator Assignments +# ===================== +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "1 ns" + +# Design Assistant Assignments +# ============================ +set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF +set_global_assignment -name ASSG_CAT OFF +set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF +set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF +set_global_assignment -name CLK_CAT OFF +set_global_assignment -name CLK_RULE_COMB_CLOCK OFF +set_global_assignment -name CLK_RULE_INV_CLOCK OFF +set_global_assignment -name CLK_RULE_GATING_SCHEME OFF +set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF +set_global_assignment -name CLK_RULE_MIX_EDGES OFF +set_global_assignment -name RESET_CAT OFF +set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name TIMING_CAT OFF +set_global_assignment -name TIMING_RULE_SHIFT_REG OFF +set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF +set_global_assignment -name NONSYNCHSTRUCT_CAT OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF +set_global_assignment -name SIGNALRACE_CAT OFF +set_global_assignment -name ACLK_CAT OFF +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF +set_global_assignment -name HCPY_CAT OFF +set_global_assignment -name HCPY_VREF_PINS OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name HUB_ENTITY_NAME SLD_HUB +set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST +set_global_assignment -name ENABLE_SIGNALTAP OFF + +# LogicLock Region Assignments +# ============================ +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF + +# ----------------- +# start CLOCK(SCLK) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK +set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK + +# end CLOCK(SCLK) +# --------------- + +# ----------------------- +# start CLOCK(master_clk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk +set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk + +# end CLOCK(master_clk) +# --------------------- + +# ------------------- +# start CLOCK(usbclk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk +set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk + +# end CLOCK(usbclk) +# ----------------- + +# ---------------------- +# start ENTITY(usrp_inband_usb) + + # Timing Assignments + # ================== +set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK +set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk +set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk + +# end ENTITY(usrp_inband_usb) +# -------------------- + + +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v +set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v +set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v +set_global_assignment -name VERILOG_FILE usrp_inband_usb.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" \ No newline at end of file diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.v b/toplevel/usrp_inband_usb/usrp_inband_usb.v new file mode 100644 index 000000000..55701b897 --- /dev/null +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.v @@ -0,0 +1,327 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2004 Matt Ettus +// Copyright 2007 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +`include "config.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module usrp_inband_usb +(output MYSTERY_SIGNAL, + input master_clk, + input SCLK, + input SDI, + inout SDO, + input SEN_FPGA, + + input FX2_1, + output FX2_2, + output FX2_3, + + input wire [11:0] rx_a_a, + input wire [11:0] rx_b_a, + input wire [11:0] rx_a_b, + input wire [11:0] rx_b_b, + + output wire [13:0] tx_a, + output wire [13:0] tx_b, + + output wire TXSYNC_A, + output wire TXSYNC_B, + + // USB interface + input usbclk, + input wire [2:0] usbctl, + output wire [1:0] usbrdy, + inout [15:0] usbdata, // NB Careful, inout + + // These are the general purpose i/o's that go to the daughterboard slots + inout wire [15:0] io_tx_a, + inout wire [15:0] io_tx_b, + inout wire [15:0] io_rx_a, + inout wire [15:0] io_rx_b + ); + wire [15:0] debugdata,debugctrl; + assign MYSTERY_SIGNAL = 1'b0; + + wire clk64,clk128; + + wire WR = usbctl[0]; + wire RD = usbctl[1]; + wire OE = usbctl[2]; + + wire have_space, have_pkt_rdy; + assign usbrdy[0] = have_space; + assign usbrdy[1] = have_pkt_rdy; + + wire tx_underrun, rx_overrun; + wire clear_status = FX2_1; + assign FX2_2 = rx_overrun; + assign FX2_3 = tx_underrun; + + wire [15:0] usbdata_out; + + wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; + + wire tx_realsignals; + wire [3:0] rx_numchan; + wire [2:0] tx_numchan; + + wire [7:0] interp_rate, decim_rate; + wire [15:0] tx_debugbus, rx_debugbus; + + wire enable_tx, enable_rx; + wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; + wire [7:0] settings; + + // Tri-state bus macro + bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); + + assign clk64 = master_clk; + + wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; + wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; + + // TX + wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; + wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; + + wire strobe_interp, tx_sample_strobe; + wire tx_empty; + + wire serial_strobe; + wire [6:0] serial_addr; + wire [31:0] serial_data; + + reg [15:0] debug_counter; + reg [15:0] loopback_i_0,loopback_q_0; + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Transmit Side +`ifdef TX_ON + assign bb_tx_i0 = ch0tx; + assign bb_tx_q0 = ch1tx; + assign bb_tx_i1 = ch2tx; + assign bb_tx_q1 = ch3tx; + + tx_buffer tx_buffer + ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), + .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), + .channels({tx_numchan,1'b0}), + .tx_i_0(ch0tx),.tx_q_0(ch1tx), + .tx_i_1(ch2tx),.tx_q_1(ch3tx), + .tx_i_2(),.tx_q_2(), + .tx_i_3(),.tx_q_3(), + .txclk(clk64),.txstrobe(strobe_interp), + .clear_status(clear_status), + .tx_empty(tx_empty), + .debugbus(tx_debugbus) ); + + `ifdef TX_EN_0 + tx_chain tx_chain_0 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); + `else + assign i_out_0=16'd0; + assign q_out_0=16'd0; + `endif + + `ifdef TX_EN_1 + tx_chain tx_chain_1 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); + `else + assign i_out_1=16'd0; + assign q_out_1=16'd0; + `endif + + setting_reg #(`FR_TX_MUX) + sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; + + wire txsync = tx_sample_strobe; + assign TXSYNC_A = txsync; + assign TXSYNC_B = txsync; + + assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; + assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; +`endif // `ifdef TX_ON + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Receive Side +`ifdef RX_ON + wire rx_sample_strobe,strobe_decim,hb_strobe; + wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, + bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; + + wire loopback = settings[0]; + wire counter = settings[1]; + + always @(posedge clk64) + if(rx_dsp_reset) + debug_counter <= #1 16'd0; + else if(~enable_rx) + debug_counter <= #1 16'd0; + else if(hb_strobe) + debug_counter <=#1 debug_counter + 16'd2; + + always @(posedge clk64) + if(strobe_interp) + begin + loopback_i_0 <= #1 ch0tx; + loopback_q_0 <= #1 ch1tx; + end + + assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; + assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; + assign ch2rx = bb_rx_i1; + assign ch3rx = bb_rx_q1; + assign ch4rx = bb_rx_i2; + assign ch5rx = bb_rx_q2; + assign ch6rx = bb_rx_i3; + assign ch7rx = bb_rx_q3; + + wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; + wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; + + adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), + .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3), + .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), + .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), + .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), + .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); + + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), + .reset_regs(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(ch0rx),.ch_1(ch1rx), + .ch_2(ch2rx),.ch_3(ch3rx), + .ch_4(ch4rx),.ch_5(ch5rx), + .ch_6(ch6rx),.ch_7(ch7rx), + .rxclk(clk64),.rxstrobe(hb_strobe), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .debugbus(rx_debugbus) ); + + `ifdef RX_EN_0 + rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); + `else + assign bb_rx_i0=16'd0; + assign bb_rx_q0=16'd0; + `endif + + `ifdef RX_EN_1 + rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); + `else + assign bb_rx_i1=16'd0; + assign bb_rx_q1=16'd0; + `endif + + `ifdef RX_EN_2 + rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); + `else + assign bb_rx_i2=16'd0; + assign bb_rx_q2=16'd0; + `endif + + `ifdef RX_EN_3 + rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); + `else + assign bb_rx_i3=16'd0; + assign bb_rx_q3=16'd0; + `endif + +`endif // `ifdef RX_ON + + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Control Functions + + wire [31:0] capabilities; + assign capabilities[7] = `TX_CAP_HB; + assign capabilities[6:4] = `TX_CAP_NCHAN; + assign capabilities[3] = `RX_CAP_HB; + assign capabilities[2:0] = `RX_CAP_NCHAN; + + + serial_io serial_io + ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), + .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), + .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) + ); + + wire [15:0] reg_0,reg_1,reg_2,reg_3; + master_control master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + //.debug_0(rx_a_a),.debug_1(ddc0_in_i), + .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + + io_pins io_pins + (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Misc Settings + setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); + +endmodule // usrp_inband_usb -- cgit v1.2.3 From b505867e3e5430eeeadb87ce1ccfd5ee4241da0e Mon Sep 17 00:00:00 2001 From: matt Date: Fri, 30 Mar 2007 21:52:52 +0000 Subject: registered to meet timing git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4826 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/cic_decim.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/sdr_lib/cic_decim.v b/sdr_lib/cic_decim.v index 6c20416f1..8c44f006d 100755 --- a/sdr_lib/cic_decim.v +++ b/sdr_lib/cic_decim.v @@ -35,7 +35,8 @@ module cic_decim input [bw-1:0] signal_in; output [bw-1:0] signal_out; reg [bw-1:0] signal_out; - + wire [bw-1:0] signal_out_unreg; + wire [bw+maxbitgain-1:0] signal_in_ext; reg [bw+maxbitgain-1:0] integrator [0:N-1]; reg [bw+maxbitgain-1:0] differentiator [0:N-1]; @@ -83,7 +84,10 @@ module cic_decim wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1]; cic_dec_shifter #(bw) - cic_dec_shifter(rate,signal_out_unnorm,signal_out); + cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg); + + always @(posedge clock) + signal_out <= #1 signal_out_unreg; endmodule // cic_decim -- cgit v1.2.3 From 886cbb6ba4bcecd88701310b744076b5921a7f15 Mon Sep 17 00:00:00 2001 From: eb Date: Mon, 2 Apr 2007 23:39:16 +0000 Subject: New FPGA binaries (.rbfs). These include fixes for the scaling in the CIC decimator so that signals are now roughly leveled, independent of the decimation rate. Decimating by 44 now works too ;) git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4848 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 177079 -> 179750 bytes rbf/rev2/std_4rx_0tx.rbf | Bin 174171 -> 182928 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 177079 -> 179750 bytes rbf/rev4/std_4rx_0tx.rbf | Bin 174171 -> 182928 bytes 4 files changed, 0 insertions(+), 0 deletions(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 966bae865..dbcd84e2d 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev2/std_4rx_0tx.rbf b/rbf/rev2/std_4rx_0tx.rbf index a5a5cf99d..5404e608b 100755 Binary files a/rbf/rev2/std_4rx_0tx.rbf and b/rbf/rev2/std_4rx_0tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 966bae865..dbcd84e2d 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_4rx_0tx.rbf b/rbf/rev4/std_4rx_0tx.rbf index a5a5cf99d..5404e608b 100755 Binary files a/rbf/rev4/std_4rx_0tx.rbf and b/rbf/rev4/std_4rx_0tx.rbf differ -- cgit v1.2.3 From 5a17f48e7374466b10787ef2721166b1bb862cf1 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Mon, 16 Apr 2007 21:30:13 +0000 Subject: Adds capability to independently delay the Auto T/R switching signal by a configurable number of clock ticks, to allow users to precisely align their T/R output with the pipeline delays in the transmitter. There are two new registers: FR_ATR_TX_DELAY (7'd2) FR_ATR_RX_DELAY (7'd3) ...and the corresponding db_base.py methods to set them: db_base.set_atr_tx_delay(clock_ticks) db_base.set_atr_rx_delay(clock_ticks) These methods are inherited by all the daughterboard objects so you can call them from your scripts as: subdev.set_atr_tx_delay(...) ...where 'subdev' represents the daughtercard object you're working with. The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%, with no additional synthesis messages or impact on timing. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 179750 -> 180404 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 179750 -> 180404 bytes sdr_lib/atr_delay.v | 83 +++++++++++++++++++++++++++++++++++++++++ sdr_lib/master_control.v | 10 ++++- toplevel/usrp_std/usrp_std.qsf | 5 ++- 5 files changed, 96 insertions(+), 2 deletions(-) create mode 100644 sdr_lib/atr_delay.v diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index dbcd84e2d..2b97f9d4e 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index dbcd84e2d..2b97f9d4e 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/sdr_lib/atr_delay.v b/sdr_lib/atr_delay.v new file mode 100644 index 000000000..a832421a1 --- /dev/null +++ b/sdr_lib/atr_delay.v @@ -0,0 +1,83 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o); + input clk_i; + input rst_i; + input ena_i; + input tx_empty_i; + input [31:0] tx_delay_i; + input [31:0] rx_delay_i; + output atr_tx_o; + + reg [3:0] state; + reg [31:0] count; + + `define ST_RX_DELAY 4'b0001 + `define ST_RX 4'b0010 + `define ST_TX_DELAY 4'b0100 + `define ST_TX 4'b1000 + + always @(posedge clk_i) + if (rst_i | ~ena_i) + begin + state <= `ST_RX; + count <= 0; + end + else + case (state) + `ST_RX: + if (!tx_empty_i) + begin + state <= `ST_TX_DELAY; + count <= tx_delay_i; + end + + `ST_TX_DELAY: + if (count == 0) + state <= `ST_TX; + else + count <= count - 1; + + `ST_TX: + if (tx_empty_i) + begin + state <= `ST_RX_DELAY; + count <= rx_delay_i; + end + + `ST_RX_DELAY: + if (count == 0) + state <= `ST_RX; + else + count <= count - 1; + + default: // Error + begin + state <= `ST_RX; + count <= 0; + end + endcase + + assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY); + +endmodule // atr_delay + diff --git a/sdr_lib/master_control.v b/sdr_lib/master_control.v index 863d44a82..6befc4dfd 100644 --- a/sdr_lib/master_control.v +++ b/sdr_lib/master_control.v @@ -3,6 +3,7 @@ // USRP - Universal Software Radio Peripheral // // Copyright (C) 2003,2005 Matt Ettus +// Copyright (C) 2007 Corgan Enterprises LLC // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -111,8 +112,9 @@ module master_control <= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); endcase // case(serial_addr) - wire transmit_now = !tx_empty & enable_tx; + wire transmit_now; wire atr_ctl; + wire [31:0] atr_tx_delay, atr_rx_delay; wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3; setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0)); @@ -132,8 +134,14 @@ module master_control setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3)); //setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl)); + setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay)); + setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay)); + assign atr_ctl = 1'b1; + atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl & enable_tx),.tx_empty_i(tx_empty), + .tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now)); + wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0; wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg); diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index ad98b1165..14dbd30c2 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION 6.1 +set_global_assignment -name LAST_QUARTUS_VERSION 7.0 # Pin & Location Assignments # ========================== @@ -368,6 +368,9 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk # end ENTITY(usrp_std) # -------------------- +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -- cgit v1.2.3 From b535098017d3df071b031bd15452a7bba53aab14 Mon Sep 17 00:00:00 2001 From: eb Date: Wed, 2 May 2007 04:08:47 +0000 Subject: Merged features/inband -r4812:5218 into trunk. This group of changes includes: * working stand-alone mblock code * work-in-progress on usrp inband signaling usrp now depends on mblock, and guile is a dependency. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5221 221aa14e-8319-0410-a670-987f0aec2ac5 --- inband_lib/chan_fifo_reader.v | 197 +++++++++++++++++++++++++++ inband_lib/data_packet_fifo.v | 128 +++++++++++++++++ inband_lib/tx_buffer_inband.v | 183 +++++++++++++++++++++++++ inband_lib/usb_fifo_reader.v | 135 ++++++++++++++++++ inband_lib/usb_packet_fifo.v | 112 +++++++++++++++ inband_lib/usb_packet_fifo2.v | 119 ++++++++++++++++ megacells/fifo_512.bsf | 116 ++++++++++++++++ megacells/fifo_512.cmp | 31 +++++ megacells/fifo_512.inc | 32 +++++ megacells/fifo_512.v | 180 ++++++++++++++++++++++++ megacells/fifo_512_bb.v | 131 ++++++++++++++++++ toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 12 +- toplevel/usrp_inband_usb/usrp_inband_usb.v | 16 +++ 13 files changed, 1389 insertions(+), 3 deletions(-) create mode 100755 inband_lib/chan_fifo_reader.v create mode 100755 inband_lib/data_packet_fifo.v create mode 100755 inband_lib/tx_buffer_inband.v create mode 100755 inband_lib/usb_fifo_reader.v create mode 100755 inband_lib/usb_packet_fifo.v create mode 100755 inband_lib/usb_packet_fifo2.v create mode 100755 megacells/fifo_512.bsf create mode 100755 megacells/fifo_512.cmp create mode 100755 megacells/fifo_512.inc create mode 100755 megacells/fifo_512.v create mode 100755 megacells/fifo_512_bb.v diff --git a/inband_lib/chan_fifo_reader.v b/inband_lib/chan_fifo_reader.v new file mode 100755 index 000000000..2b3178da7 --- /dev/null +++ b/inband_lib/chan_fifo_reader.v @@ -0,0 +1,197 @@ +module chan_fifo_reader + ( input reset, + input tx_clock, + input tx_strobe, + input [31:0]adc_clock, + input [3:0] samples_format, + input [15:0] fifodata, + input pkt_waiting, + output reg rdreq, + output reg skip, + output reg [15:0]tx_q, + output reg [15:0]tx_i, + output reg overrun, + output reg underrun) ; + + // Should not be needed if adc clock rate < tx clock rate + `define JITTER 5 + + //Samples format + // 16 bits interleaved complex samples + `define QI16 4'b0 + + // States + `define IDLE 4'd0 + `define READ 4'd1 + `define HEADER1 4'd2 + `define HEADER2 4'd3 + `define TIMESTAMP1 4'd4 + `define TIMESTAMP2 4'd5 + `define WAIT 4'd6 + `define WAITSTROBE 4'd7 + `define SENDWAIT 4'd8 + `define SEND 4'd9 + `define FEED 4'd10 + `define DISCARD 4'd11 + + // State registers + reg[3:0] reader_state; + reg[3:0] reader_next_state; + + //Variables + reg[8:0] payload_len; + reg[8:0] read_len; + reg[31:0] timestamp; + reg burst; + reg qsample; + always @(posedge tx_clock) + begin + if (reset) + begin + reader_state <= `IDLE; + reader_next_state <= `IDLE; + rdreq <= 0; + skip <= 0; + overrun <= 0; + underrun <= 0; + burst <= 0; + qsample <= 1; + end + else + begin + reader_state = reader_next_state; + case (reader_state) + `IDLE: + begin + if (pkt_waiting == 1) + begin + reader_next_state <= `READ; + rdreq <= 1; + underrun <= 0; + end + else if (burst == 1) + underrun <= 1; + end + + // Just wait for the fifo data to arrive + `READ: + begin + reader_next_state <= `HEADER1; + end + + // First part of the header + `HEADER1: + begin + reader_next_state <= `HEADER2; + + //Check Start burst flag + if (fifodata[3] == 1) + burst <= 1; + + if (fifodata[4] == 1) + burst <= 0; + end + + // Read payload length + `HEADER2: + begin + payload_len <= (fifodata & 16'h1FF); + read_len <= 9'd0; + reader_next_state <= `TIMESTAMP1; + end + + `TIMESTAMP1: + begin + timestamp <= {fifodata, 16'b0}; + rdreq <= 0; + reader_next_state <= `TIMESTAMP2; + end + + `TIMESTAMP2: + begin + timestamp <= timestamp + fifodata; + reader_next_state <= `WAIT; + end + + // Decide if we wait, send or discard samples + `WAIT: + begin + // Wait a little bit more + if (timestamp > adc_clock + `JITTER) + reader_next_state <= `WAIT; + // Let's send it + else if ((timestamp < adc_clock + `JITTER + && timestamp > adc_clock) + || timestamp == 32'hFFFFFFFF) + begin + reader_next_state <= `WAITSTROBE; + end + // Outdated + else if (timestamp < adc_clock) + begin + reader_next_state <= `DISCARD; + skip <= 1; + end + end + + // Wait for the transmit chain to be ready + `WAITSTROBE: + begin + // If end of payload... + if (read_len == payload_len) + begin + reader_next_state <= `DISCARD; + skip <= (payload_len < 508); + end + + if (tx_strobe == 1) + reader_next_state <= `SENDWAIT; + end + + `SENDWAIT: + begin + rdreq <= 1; + reader_next_state <= `SEND; + end + + // Send the samples to the tx_chain + `SEND: + begin + reader_next_state <= `WAITSTROBE; + rdreq <= 0; + read_len <= read_len + 2; + case(samples_format) + `QI16: + begin + tx_q <= qsample ? fifodata : 16'bZ; + tx_i <= ~qsample ? fifodata : 16'bZ; + qsample <= ~ qsample; + end + default: + begin + // Assume 16 bits complex samples by default + $display ("Error unknown samples format"); + tx_q <= qsample ? fifodata : 16'bZ; + tx_i <= ~qsample ? fifodata : 16'bZ; + qsample <= ~ qsample; + end + endcase + end + + `DISCARD: + begin + skip <= 0; + reader_next_state <= `IDLE; + end + + default: + begin + $display ("Error unknown state"); + reader_state <= `IDLE; + reader_next_state <= `IDLE; + end + endcase + end + end + +endmodule \ No newline at end of file diff --git a/inband_lib/data_packet_fifo.v b/inband_lib/data_packet_fifo.v new file mode 100755 index 000000000..5b37b14ea --- /dev/null +++ b/inband_lib/data_packet_fifo.v @@ -0,0 +1,128 @@ +module data_packet_fifo + ( input reset, + input clock, + input [15:0]ram_data_in, + input write_enable, + output reg have_space, + output reg [15:0]ram_data_out, + output reg pkt_waiting, + input read_enable, + input pkt_complete, + input skip_packet) ; + + /* Some parameters for usage later on */ + parameter DATA_WIDTH = 16 ; + parameter NUM_PACKETS = 4 ; + + /* Create the RAM here */ + reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ; + + /* Create the address signals */ + reg [7:0] usb_ram_offset_out ; + reg [1:0] usb_ram_packet_out ; + reg [7:0] usb_ram_offset_in ; + reg [1:0] usb_ram_packet_in ; + + wire [7-2+NUM_PACKETS:0] usb_ram_aout ; + wire [7-2+NUM_PACKETS:0] usb_ram_ain ; + reg isfull; + + assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ; + assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ; + + // Check if there is one full packet to process + always @(usb_ram_ain, usb_ram_aout) + begin + if (reset) + pkt_waiting <= 0; + else if (usb_ram_ain >= usb_ram_aout) + pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256; + else + pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256; + end + + // Check if there is room + always @(usb_ram_ain, usb_ram_aout) + begin + if (reset) + have_space <= 1; + else if (usb_ram_ain == usb_ram_aout) + have_space <= ~isfull; + else if (usb_ram_ain > usb_ram_aout) + have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1); + else + have_space <= (usb_ram_aout - usb_ram_ain) >= 256; + end + + /* RAM Write Address process */ + always @(posedge clock) + begin + if( reset ) + begin + usb_ram_offset_in <= 0 ; + usb_ram_packet_in <= 0 ; + end + else + if( pkt_complete ) + begin + usb_ram_packet_in <= usb_ram_packet_in + 1; + usb_ram_offset_in <= 0; + end + else if( write_enable ) + begin + if (usb_ram_offset_in == 8'b11111111) + begin + usb_ram_offset_in <= 0; + usb_ram_packet_in <= usb_ram_packet_in + 1; + end + else + usb_ram_offset_in <= usb_ram_offset_in + 1 ; + if (usb_ram_ain + 1 == usb_ram_aout) + isfull <= 1; + end + end + + /* RAM Writing process */ + always @(posedge clock) + begin + if( write_enable ) + begin + usb_ram[usb_ram_ain] <= ram_data_in ; + end + end + + /* RAM Read Address process */ + always @(posedge clock) + begin + if( reset ) + begin + usb_ram_packet_out <= 0 ; + usb_ram_offset_out <= 0 ; + isfull <= 0; + end + else + if( skip_packet ) + begin + usb_ram_packet_out <= usb_ram_packet_out + 1 ; + usb_ram_offset_out <= 0 ; + end + else if(read_enable) begin + if( usb_ram_offset_out == 8'b11111111 ) + begin + usb_ram_offset_out <= 0 ; + usb_ram_packet_out <= usb_ram_packet_out + 1 ; + end + else + usb_ram_offset_out <= usb_ram_offset_out + 1 ; + end + if (usb_ram_ain == usb_ram_aout) + isfull <= 0; + end + + /* RAM Reading Process */ + always @(posedge clock) + begin + ram_data_out <= usb_ram[usb_ram_aout] ; + end + +endmodule diff --git a/inband_lib/tx_buffer_inband.v b/inband_lib/tx_buffer_inband.v new file mode 100755 index 000000000..56c07807a --- /dev/null +++ b/inband_lib/tx_buffer_inband.v @@ -0,0 +1,183 @@ +module tx_buffer_inband + ( input usbclk, + input bus_reset, // Used here for the 257-Hack to fix the FX2 bug + input reset, // standard DSP-side reset + input [15:0] usbdata, + input wire WR, + output wire have_space, + output reg tx_underrun, + input wire [3:0] channels, + output [15:0] tx_i_0, + output [15:0] tx_q_0, + output [15:0] tx_i_1, + output [15:0] tx_q_1, + //NOT USED + output reg [15:0] tx_i_2, + output reg [15:0] tx_q_2, + output reg [15:0] tx_i_3, + output reg [15:0] tx_q_3, + input txclk, + input txstrobe, + input clear_status, + output wire tx_empty, + output [11:0] debugbus + ); + + wire [15:0] tx_data_bus; + + wire WR_chan_0; + wire chan_0_done; + wire OR0; + wire UR0; + + wire WR_chan_1; + wire chan_1_done; + wire OR1; + wire UR1; + + // NOT USED yet + wire WR_cmd; + wire cmd_done; + + //EXTERNAL REGISTER + //TODO: increment it + reg [31:0] time_counter; + reg [7:0] txstrobe_rate_0; + reg [7:0] txstrobe_rate_1; + + + //Usb block + wire [15:0] tupf_fifodata; + wire tupf_pkt_waiting; + wire tupf_rdreq; + wire tupf_skip; + wire tupf_have_space; + + usb_packet_fifo2 tx_usb_packet_fifo + ( .reset (reset), + .usb_clock (usbclk), + .fpga_clock (txclk), + .write_data (usbdata), + .write_enable (WR), + .read_data (tupf_fifodata), + .pkt_waiting (tupf_pkt_waiting), + .read_enable (tupf_rdreq), + .skip_packet (tupf_skip), + .have_space (tupf_have_space), + .tx_empty (tx_empty) + ); + + usb_fifo_reader tx_usb_packet_reader ( + .reset(reset), + .tx_clock(txclk), + .tx_data_bus(tx_data_bus), + .WR_chan_0(WR_chan_0), + .WR_chan_1(WR_chan_1), + .WR_cmd(WR_cmd), + .chan_0_done(chan_0_done), + .chan_1_done(chan_1_done), + .cmd_done(cmd_done), + .rdreq(tupf_rdreq), + .skip(tupf_skip), + .pkt_waiting(tupf_pkt_waiting), + .fifodata(tupf_fifodata) + ); + + + //Channel 0 block + wire [15:0] tdpf_fifodata_0; + wire tdpf_pkt_waiting_0; + wire tdpf_rdreq_0; + wire tdpf_skip_0; + wire tdpf_have_space_0; + wire txstrobe_chan_0; + + data_packet_fifo tx_data_packet_fifo_0 + ( .reset(reset), + .clock(txclk), + .ram_data_in(tx_data_bus), + .write_enable(WR_chan_0), + .ram_data_out(tdpf_fifodata_0), + .pkt_waiting(tdpf_pkt_waiting_0), + .read_enable(tdpf_rdreq_0), + .pkt_complete(chan_0_done), + .skip_packet(tdpf_skip_0), + .have_space(tdpf_have_space_0) + ); + + strobe_gen strobe_gen_0 + ( .clock(txclk), + .reset(reset), + .enable(1'b1), + .rate(txstrobe_rate_0), + .strobe_in(txstrobe), + .strobe(txstrobe_chan_0) + ); + + chan_fifo_reader tx_chan_0_reader ( + .reset(reset), + .tx_clock(txclk), + .tx_strobe(txstrobe), + //.tx_strobe(txstrobe_chan_0), + .adc_clock(time_counter), + .samples_format(4'b0), + .tx_q(tx_q_0), + .tx_i(tx_i_0), + .overrun(OR0), + .underrun(UR0), + .skip(tdpf_skip_0), + .rdreq(tdpf_rdreq_0), + .fifodata(tdpf_fifodata_0), + .pkt_waiting(tdpf_pkt_waiting_0) + ); + + + //Channel 1 block + wire [15:0] tdpf_fifodata_1; + wire tdpf_pkt_waiting_1; + wire tdpf_rdreq_1; + wire tdpf_skip_1; + wire tdpf_have_space_1; + wire txstrobe_chan_1; + + data_packet_fifo tx_data_packet_fifo_1 + ( .reset(reset), + .clock(txclk), + .ram_data_in(tx_data_bus), + .write_enable(WR_chan_1), + .ram_data_out(tdpf_fifodata_1), + .pkt_waiting(tdpf_pkt_waiting_1), + .read_enable(tdpf_rdreq_1), + .pkt_complete(chan_1_done), + .skip_packet(tdpf_skip_1), + .have_space(tdpf_have_space_1) + ); + + strobe_gen strobe_gen_1 + ( .clock(txclk), + .reset(reset), + .enable(1'b1), + .rate(txstrobe_rate_1), + .strobe_in(txstrobe), + .strobe(txstrobe_chan_1) + ); + + chan_fifo_reader tx_chan_1_reader ( + .reset(reset), + .tx_clock(txclk), + .tx_strobe(txstrobe), + //.tx_strobe(txstrobe_chan_1), + .adc_clock(time_counter), + .samples_format(4'b0), + .tx_q(tx_q_1), + .tx_i(tx_i_1), + .overrun(OR1), + .underrun(UR1), + .skip(tdpf_skip_1), + .rdreq(tdpf_rdreq_1), + .fifodata(tdpf_fifodata_1), + .pkt_waiting(tdpf_pkt_waiting_1) + ); + +endmodule // tx_buffer + diff --git a/inband_lib/usb_fifo_reader.v b/inband_lib/usb_fifo_reader.v new file mode 100755 index 000000000..170c70fd4 --- /dev/null +++ b/inband_lib/usb_fifo_reader.v @@ -0,0 +1,135 @@ +module usb_fifo_reader (tx_clock, fifodata, pkt_waiting, reset, + rdreq, skip, done_chan, WR_chan, tx_data_bus); + + /* Module parameters */ + parameter NUM_CHAN = 2 ; + parameter WIDTH = 32 ; + + input wire tx_clock ; + input wire reset ; + input wire [WIDTH-1:0] fifodata ; + input wire pkt_waiting ; + output reg rdreq ; + output reg skip ; + output reg [NUM_CHAN:0] done_chan ; + output reg [NUM_CHAN:0] WR_chan ; + output reg [WIDTH-1:0] tx_data_bus ; + + + + /* States definition */ + `define IDLE 3'd0 + `define WAIT 3'd1 + `define READ_HEADER 3'd2 + `define FORWARD_DATA 3'd3 + `define SKIP_REST 3'd4 + + /* Channel Ids */ + `define TXCHAN0 5'h0 + `define TXCHAN1 5'h1 + `define TXCMD 5'h1F + + /* Local registers */ + reg [2:0] reader_state ; + reg [2:0] reader_next_state ; + reg [4:0] channel ; + reg [8:0] pkt_length ; + reg [8:0] read_length ; + + /* State Machine */ + always @(posedge tx_clock) + begin + if (reset) + begin + reader_state <= `IDLE ; + reader_next_state <= `IDLE ; + rdreq <= 0 ; + skip <= 0 ; + WR_chan <= {NUM_CHAN+1{1'b0}} ; + done_chan <= {NUM_CHAN+1{1'b0}} ; + end + else + begin + reader_state = reader_next_state ; + + case(reader_state) + `IDLE: + begin + reader_next_state <= pkt_waiting ? `WAIT : `IDLE ; + rdreq <= pkt_waiting ; + end + + /* Wait for the fifo's data to show up */ + `WAIT: + begin + reader_next_state <= `READ_HEADER ; + end + + `READ_HEADER: + begin + reader_next_state <= `FORWARD_DATA ; + + /* Read header fields */ + channel <= (fifodata & 32'h1F0000) ; + pkt_length <= (fifodata & 16'h1FF) + 4 ; + read_length <= 9'd0 ; + + /* Forward data */ + case (channel) + `TXCHAN0: WR_chan[0] <= 1 ; + `TXCHAN1: WR_chan[1] <= 1 ; + `TXCMD: WR_chan[2] <= 1 ; + default: WR_chan <= 1 ; + endcase + tx_data_bus <= fifodata ; + end + + `FORWARD_DATA: + begin + read_length <= read_length + 4 ; + + // If end of payload... + if (read_length == pkt_length) + begin + reader_next_state <= `SKIP_REST ; + /* If the packet is 512 bytes, don't skip */ + skip <= pkt_length < 506 ; + + /* Data pushing done */ + WR_chan <= {NUM_CHAN+1{1'b0}} ; + + /* Notify next block */ + case (channel) + `TXCHAN0: done_chan[0] <= 1 ; + `TXCHAN1: done_chan[1] <= 1 ; + `TXCMD: done_chan[2] <= 1 ; + default: done_chan[0] <= 1 ; + endcase + end + else if (read_length == pkt_length - 4) + rdreq <= 0 ; + + /* Forward data */ + tx_data_bus <= fifodata ; + end + + `SKIP_REST: + begin + reader_next_state <= pkt_waiting ? `READ_HEADER : `IDLE ; + done_chan <= {NUM_CHAN+1{1'b0}} ; + rdreq <= pkt_waiting ; + skip <= 0 ; + end + + default: + begin + reader_state <= `IDLE; + reader_next_state <= `IDLE; + end + endcase + end + end +endmodule + + + \ No newline at end of file diff --git a/inband_lib/usb_packet_fifo.v b/inband_lib/usb_packet_fifo.v new file mode 100755 index 000000000..c416e2bdb --- /dev/null +++ b/inband_lib/usb_packet_fifo.v @@ -0,0 +1,112 @@ +module usb_packet_fifo + ( input reset, + input clock_in, + input clock_out, + input [15:0]ram_data_in, + input write_enable, + output reg [15:0]ram_data_out, + output reg pkt_waiting, + output reg have_space, + input read_enable, + input skip_packet ) ; + + /* Some parameters for usage later on */ + parameter DATA_WIDTH = 16 ; + parameter NUM_PACKETS = 4 ; + + /* Create the RAM here */ + reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ; + + /* Create the address signals */ + reg [7-2+NUM_PACKETS:0] usb_ram_ain ; + reg [7:0] usb_ram_offset ; + reg [1:0] usb_ram_packet ; + + wire [7-2+NUM_PACKETS:0] usb_ram_aout ; + reg isfull; + + assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ; + + // Check if there is one full packet to process + always @(usb_ram_ain, usb_ram_aout) + begin + if (reset) + pkt_waiting <= 0; + else if (usb_ram_ain == usb_ram_aout) + pkt_waiting <= isfull; + else if (usb_ram_ain > usb_ram_aout) + pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256; + else + pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256; + end + + // Check if there is room + always @(usb_ram_ain, usb_ram_aout) + begin + if (reset) + have_space <= 1; + else if (usb_ram_ain == usb_ram_aout) + have_space <= ~isfull; + else if (usb_ram_ain > usb_ram_aout) + have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1); + else + have_space <= (usb_ram_aout - usb_ram_ain) >= 256; + end + + /* RAM Write Address process */ + always @(posedge clock_in) + begin + if( reset ) + usb_ram_ain <= 0 ; + else + if( write_enable ) + begin + usb_ram_ain <= usb_ram_ain + 1 ; + if (usb_ram_ain + 1 == usb_ram_aout) + isfull <= 1; + end + end + + /* RAM Writing process */ + always @(posedge clock_in) + begin + if( write_enable ) + begin + usb_ram[usb_ram_ain] <= ram_data_in ; + end + end + + /* RAM Read Address process */ + always @(posedge clock_out) + begin + if( reset ) + begin + usb_ram_packet <= 0 ; + usb_ram_offset <= 0 ; + isfull <= 0; + end + else + if( skip_packet ) + begin + usb_ram_packet <= usb_ram_packet + 1 ; + usb_ram_offset <= 0 ; + end + else if(read_enable) + if( usb_ram_offset == 8'b11111111 ) + begin + usb_ram_offset <= 0 ; + usb_ram_packet <= usb_ram_packet + 1 ; + end + else + usb_ram_offset <= usb_ram_offset + 1 ; + if (usb_ram_ain == usb_ram_aout) + isfull <= 0; + end + + /* RAM Reading Process */ + always @(posedge clock_out) + begin + ram_data_out <= usb_ram[usb_ram_aout] ; + end + +endmodule \ No newline at end of file diff --git a/inband_lib/usb_packet_fifo2.v b/inband_lib/usb_packet_fifo2.v new file mode 100755 index 000000000..d815e4e37 --- /dev/null +++ b/inband_lib/usb_packet_fifo2.v @@ -0,0 +1,119 @@ +`default_nettype none + +module usb_packet_fifo2(reset, usb_clock, fpga_clock, write_enable, write_data, + read_enable, skip_packet, read_data, have_space, pkt_waiting, tx_empty) ; + + /* Module parameters */ + parameter LOG2_N = 2 ; + parameter BUS_WIDTH = 16 ; + parameter FIFO_WIDTH = 32 ; + + input wire reset; + input wire usb_clock ; + input wire fpga_clock ; + input wire write_enable ; + input wire [BUS_WIDTH-1:0] write_data ; + input wire read_enable ; + input wire skip_packet ; + output wire [FIFO_WIDTH-1:0] read_data ; + output wire have_space ; + output wire pkt_waiting ; + output wire tx_empty; + + + /* Variable for generate statement */ + genvar i ; + + /* Local wires for FIFO connections */ + wire [2**LOG2_N-1:0] fifo_resets ; + reg [2**LOG2_N-1:0] fifo_we ; + wire [2**LOG2_N-1:0] fifo_re ; + reg [FIFO_WIDTH-1:0] fifo_wdata[2**LOG2_N-1:0] ; + wire [FIFO_WIDTH-1:0] fifo_rdata[2**LOG2_N-1:0] ; + wire [2**LOG2_N-1:0] fifo_rempty ; + wire [2**LOG2_N-1:0] fifo_rfull ; + wire [2**LOG2_N-1:0] fifo_wempty ; + wire [2**LOG2_N-1:0] fifo_wfull ; + + /* FIFO Select for read and write ports */ + reg [LOG2_N-1:0] fifo_rselect ; + reg [LOG2_N-1:0] fifo_wselect ; + + /* Used to convert 16 bits usbdata to the 32 bits wide fifo */ + reg word_complete ; + reg [BUS_WIDTH-1:0] write_data_delayed ; + + /* Assign have_space to empty flag of currently selected write FIFO */ + assign have_space = fifo_wempty[fifo_wselect] ; + + /* Assign pkt_waiting to full flag of currently selected read FIFO */ + assign pkt_waiting = fifo_rfull[fifo_rselect] ; + + /* Assign the read_data to the output of the currently selected FIFO */ + assign read_data = fifo_rdata[fifo_rselect] ; + + /* Figure out if we're all empty */ + assign tx_empty = !(~fifo_rempty) ; + + /* Increment fifo_rselect here */ + always @(posedge fpga_clock) + begin + if (reset) + fifo_rselect <= {2**LOG2_N{1'b0}} ; + + if (fifo_rempty[fifo_rselect]) + fifo_rselect <= fifo_rselect + 1 ; + + if (skip_packet) + fifo_rselect <= fifo_rselect + 1 ; + end + + /* Increment fifo_wselect and pack data into 32 bits block */ + always @(posedge usb_clock, reset) + begin + if (reset) + begin + fifo_wselect <= {2**LOG2_N{1'b0}} ; + word_complete <= 0; + end + + if (fifo_wfull[fifo_wselect]) + fifo_wselect <= fifo_wselect + 1 ; + + if (write_enable) + begin + word_complete <= ~word_complete ; + + if (word_complete) + fifo_wdata[fifo_wselect] <= {write_data_delayed, write_data} ; + else + write_data_delayed <= write_data ; + + /* Avoid to continue to write in the previous fifo when we have + just swichted to the next one */ + fifo_we[fifo_wselect-1] <= 0 ; + + fifo_we[fifo_wselect] <= write_enable & word_complete ; + end + end + + /* Generate all the single packet FIFOs */ + generate + for( i = 0 ; i < 2**LOG2_N ; i = i + 1 ) + begin : generate_single_packet_fifos + assign fifo_re[i] = (fifo_rselect == i) ? read_enable : 1'b0 ; + assign fifo_resets[i] = (fifo_rselect == i) ? skip_packet : 1'b0 ; + fifo_512 single_packet_fifo(.wrclk ( usb_clock ), + .rdclk ( fpga_clock ), + .aclr ( fifo_resets[i] ), + .wrreq ( fifo_we[i] ), + .data ( fifo_wdata[i] ), + .rdreq ( fifo_re[i] ), + .q ( fifo_rdata[i] ), + .rdfull ( fifo_rfull[i] ), + .rdempty( fifo_rempty[i] ), + .wrfull ( fifo_wfull[i] ), + .wrempty( fifo_wempty[i] ) ) ; + end + endgenerate +endmodule \ No newline at end of file diff --git a/megacells/fifo_512.bsf b/megacells/fifo_512.bsf new file mode 100755 index 000000000..a955b5655 --- /dev/null +++ b/megacells/fifo_512.bsf @@ -0,0 +1,116 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 184) + (text "fifo_512" (rect 58 1 109 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 168 25 180)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 16 160)(line_width 1)) + ) + (port + (pt 160 40) + (output) + (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8))) + (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8))) + (line (pt 160 40)(pt 144 40)(line_width 1)) + ) + (port + (pt 160 56) + (output) + (text "wrempty" (rect 0 0 50 14)(font "Arial" (font_size 8))) + (text "wrempty" (rect 98 50 137 63)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 144 56)(line_width 1)) + ) + (port + (pt 160 96) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (port + (pt 160 120) + (output) + (text "rdfull" (rect 0 0 28 14)(font "Arial" (font_size 8))) + (text "rdfull" (rect 117 114 141 127)(font "Arial" (font_size 8))) + (line (pt 160 120)(pt 144 120)(line_width 1)) + ) + (port + (pt 160 136) + (output) + (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) + (text "rdempty" (rect 102 130 140 143)(font "Arial" (font_size 8))) + (line (pt 160 136)(pt 144 136)(line_width 1)) + ) + (drawing + (text "32 bits x 128 words" (rect 63 156 144 168)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 168)(line_width 1)) + (line (pt 144 168)(pt 16 168)(line_width 1)) + (line (pt 16 168)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 148)(pt 144 148)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/megacells/fifo_512.cmp b/megacells/fifo_512.cmp new file mode 100755 index 000000000..86fc07846 --- /dev/null +++ b/megacells/fifo_512.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_512 + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + rdfull : OUT STD_LOGIC ; + wrempty : OUT STD_LOGIC ; + wrfull : OUT STD_LOGIC + ); +end component; diff --git a/megacells/fifo_512.inc b/megacells/fifo_512.inc new file mode 100755 index 000000000..9ae1e3af4 --- /dev/null +++ b/megacells/fifo_512.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_512 +( + aclr, + data[31..0], + rdclk, + rdreq, + wrclk, + wrreq +) + +RETURNS ( + q[31..0], + rdempty, + rdfull, + wrempty, + wrfull +); diff --git a/megacells/fifo_512.v b/megacells/fifo_512.v new file mode 100755 index 000000000..b034b4ddc --- /dev/null +++ b/megacells/fifo_512.v @@ -0,0 +1,180 @@ +// megafunction wizard: %LPM_FIFO+% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_512.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_512 ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdfull, + wrempty, + wrfull); + + input aclr; + input [31:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [31:0] q; + output rdempty; + output rdfull; + output wrempty; + output wrfull; + + wire sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire sub_wire3; + wire [31:0] sub_wire4; + wire rdfull = sub_wire0; + wire rdempty = sub_wire1; + wire wrfull = sub_wire2; + wire wrempty = sub_wire3; + wire [31:0] q = sub_wire4[31:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdfull (sub_wire0), + .rdempty (sub_wire1), + .wrfull (sub_wire2), + .wrempty (sub_wire3), + .q (sub_wire4) + // synopsys translate_off + , + .rdusedw (), + .wrusedw () + // synopsys translate_on + ); + defparam + dcfifo_component.add_ram_output_register = "OFF", + dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone", + dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", + dcfifo_component.lpm_numwords = 128, + dcfifo_component.lpm_showahead = "OFF", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 32, + dcfifo_component.lpm_widthu = 7, + dcfifo_component.overflow_checking = "ON", + dcfifo_component.underflow_checking = "ON", + dcfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "128" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "32" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_wave*.jpg FALSE diff --git a/megacells/fifo_512_bb.v b/megacells/fifo_512_bb.v new file mode 100755 index 000000000..b11803159 --- /dev/null +++ b/megacells/fifo_512_bb.v @@ -0,0 +1,131 @@ +// megafunction wizard: %LPM_FIFO+%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_512.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_512 ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdfull, + wrempty, + wrfull); + + input aclr; + input [31:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [31:0] q; + output rdempty; + output rdfull; + output wrempty; + output wrfull; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "128" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "32" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_wave*.jpg FALSE diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf index 2646d831f..8296a453e 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION 6.1 +set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1" # Pin & Location Assignments # ========================== @@ -371,6 +371,13 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" +set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_fifo.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v @@ -405,5 +412,4 @@ set_global_assignment -name VERILOG_FILE usrp_inband_usb.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" \ No newline at end of file +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.v b/toplevel/usrp_inband_usb/usrp_inband_usb.v index 55701b897..cc7490c5a 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.v +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.v @@ -19,6 +19,7 @@ // along with this program; if not, write to the Free Software // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // +`define IN_BAND `include "config.vh" `include "../../../firmware/include/fpga_regs_common.v" @@ -122,6 +123,20 @@ module usrp_inband_usb assign bb_tx_i1 = ch2tx; assign bb_tx_q1 = ch3tx; +`ifdef IN_BAND + tx_buffer_inband tx_buffer + ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), + .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), + .channels({tx_numchan,1'b0}), + .tx_i_0(ch0tx),.tx_q_0(ch1tx), + .tx_i_1(ch2tx),.tx_q_1(ch3tx), + .tx_i_2(),.tx_q_2(), + .tx_i_3(),.tx_q_3(), + .txclk(clk64),.txstrobe(strobe_interp), + .clear_status(clear_status), + .tx_empty(tx_empty), + .debugbus(tx_debugbus) ); +`else tx_buffer tx_buffer ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), @@ -134,6 +149,7 @@ module usrp_inband_usb .clear_status(clear_status), .tx_empty(tx_empty), .debugbus(tx_debugbus) ); +`endif `ifdef TX_EN_0 tx_chain tx_chain_0 -- cgit v1.2.3 From 9c3a39287e7ae106c9ed91cb4d8fac5f176b2888 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Wed, 2 May 2007 15:50:56 +0000 Subject: Merged r5203:5204 from developer branch jcorgan/atr. Fixed ATR delay enable and reduced delay width to 12 bits. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5228 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 180404 -> 180080 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 180404 -> 180080 bytes sdr_lib/atr_delay.v | 8 ++++---- sdr_lib/master_control.v | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 2b97f9d4e..340a68346 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 2b97f9d4e..340a68346 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/sdr_lib/atr_delay.v b/sdr_lib/atr_delay.v index a832421a1..bbba9e291 100644 --- a/sdr_lib/atr_delay.v +++ b/sdr_lib/atr_delay.v @@ -24,12 +24,12 @@ module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o); input rst_i; input ena_i; input tx_empty_i; - input [31:0] tx_delay_i; - input [31:0] rx_delay_i; + input [11:0] tx_delay_i; + input [11:0] rx_delay_i; output atr_tx_o; reg [3:0] state; - reg [31:0] count; + reg [11:0] count; `define ST_RX_DELAY 4'b0001 `define ST_RX 4'b0010 @@ -40,7 +40,7 @@ module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o); if (rst_i | ~ena_i) begin state <= `ST_RX; - count <= 0; + count <= 12'b0; end else case (state) diff --git a/sdr_lib/master_control.v b/sdr_lib/master_control.v index 6befc4dfd..3bce55f23 100644 --- a/sdr_lib/master_control.v +++ b/sdr_lib/master_control.v @@ -114,7 +114,7 @@ module master_control wire transmit_now; wire atr_ctl; - wire [31:0] atr_tx_delay, atr_rx_delay; + wire [11:0] atr_tx_delay, atr_rx_delay; wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3; setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0)); @@ -139,7 +139,7 @@ module master_control assign atr_ctl = 1'b1; - atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl & enable_tx),.tx_empty_i(tx_empty), + atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty), .tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now)); wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0; -- cgit v1.2.3 From 31d04440b2d986e9f28c6f22c386045e8f6c9d92 Mon Sep 17 00:00:00 2001 From: matt Date: Wed, 30 May 2007 23:27:58 +0000 Subject: not used git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5578 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/hb/coeff_ram.v | 26 -------------------------- 1 file changed, 26 deletions(-) delete mode 100644 sdr_lib/hb/coeff_ram.v diff --git a/sdr_lib/hb/coeff_ram.v b/sdr_lib/hb/coeff_ram.v deleted file mode 100644 index 65460822f..000000000 --- a/sdr_lib/hb/coeff_ram.v +++ /dev/null @@ -1,26 +0,0 @@ - - -module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data); - - always @(posedge clock) - case (rd_addr) - 4'd0 : rd_data <= #1 -16'd16; - 4'd1 : rd_data <= #1 16'd74; - 4'd2 : rd_data <= #1 -16'd254; - 4'd3 : rd_data <= #1 16'd669; - 4'd4 : rd_data <= #1 -16'd1468; - 4'd5 : rd_data <= #1 16'd2950; - 4'd6 : rd_data <= #1 -16'd6158; - 4'd7 : rd_data <= #1 16'd20585; - 4'd8 : rd_data <= #1 16'd20585; - 4'd9 : rd_data <= #1 -16'd6158; - 4'd10 : rd_data <= #1 16'd2950; - 4'd11 : rd_data <= #1 -16'd1468; - 4'd12 : rd_data <= #1 16'd669; - 4'd13 : rd_data <= #1 -16'd254; - 4'd14 : rd_data <= #1 16'd74; - 4'd15 : rd_data <= #1 -16'd16; - default : rd_data <= #1 16'd0; - endcase // case(rd_addr) - -endmodule // ram -- cgit v1.2.3 From 8c62b0535cc1a839c076719b6e0c899e63e6624c Mon Sep 17 00:00:00 2001 From: trondeau Date: Mon, 4 Jun 2007 16:08:44 +0000 Subject: merge ordm/receiver branch -r5574:5659. Reworks OFDM receiver with refactored OFDM blocks. A few bug fixes for other blocks have also been slipped in. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5661 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.extra | 1 - 1 file changed, 1 deletion(-) diff --git a/Makefile.extra b/Makefile.extra index 7055447a9..dc26413cc 100644 --- a/Makefile.extra +++ b/Makefile.extra @@ -72,7 +72,6 @@ EXTRA_DIST = \ sdr_lib/gen_cordic_consts.py \ sdr_lib/gen_sync.v \ sdr_lib/hb/acc.v \ - sdr_lib/hb/coeff_ram.v \ sdr_lib/hb/coeff_rom.v \ sdr_lib/hb/halfband_decim.v \ sdr_lib/hb/halfband_interp.v \ -- cgit v1.2.3 From b827fdb70e17c64691a0e07e0739706c58b70b8c Mon Sep 17 00:00:00 2001 From: jcorgan Date: Thu, 12 Jul 2007 00:54:37 +0000 Subject: Merged r5732:5941 from jcorgan/sar into trunk. Adds start of gr-radar-mono component. Trunk passes distcheck. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5942 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 180080 -> 180657 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 180080 -> 180657 bytes sdr_lib/cordic.v | 2 +- sdr_lib/cordic_stage.v | 2 +- 4 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 340a68346..71c301333 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 340a68346..71c301333 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/sdr_lib/cordic.v b/sdr_lib/cordic.v index fee241f62..ea4119426 100755 --- a/sdr_lib/cordic.v +++ b/sdr_lib/cordic.v @@ -66,7 +66,7 @@ module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo ); begin x0 <= #1 0; y0 <= #1 0; z0 <= #1 0; end - else// if(enable) + else if(enable) begin z0 <= #1 zi[zwidth-2:0]; case (zi[zwidth-1:zwidth-2]) diff --git a/sdr_lib/cordic_stage.v b/sdr_lib/cordic_stage.v index 0106da5cb..d44998b0d 100755 --- a/sdr_lib/cordic_stage.v +++ b/sdr_lib/cordic_stage.v @@ -45,7 +45,7 @@ module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo); yo <= #1 0; zo <= #1 0; end - else //if(enable) + else if(enable) begin xo <= #1 z_is_pos ? xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} : -- cgit v1.2.3 From 632d8e2dd3c961326f985add8d5d97db5ffcf314 Mon Sep 17 00:00:00 2001 From: eb Date: Sat, 21 Jul 2007 03:44:38 +0000 Subject: Updated license from GPL version 2 or later to GPL version 3 or later. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6044 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.am | 2 +- gen_makefile_extra.py | 2 +- rbf/Makefile.am | 2 +- toplevel/mrfm/mrfm.py | 2 +- toplevel/mrfm/mrfm_fft.py | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Makefile.am b/Makefile.am index 02f971da3..8721af4a7 100644 --- a/Makefile.am +++ b/Makefile.am @@ -5,7 +5,7 @@ # # GNU Radio is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) +# the Free Software Foundation; either version 3, or (at your option) # any later version. # # GNU Radio is distributed in the hope that it will be useful, diff --git a/gen_makefile_extra.py b/gen_makefile_extra.py index e20a852af..9f48802a2 100755 --- a/gen_makefile_extra.py +++ b/gen_makefile_extra.py @@ -6,7 +6,7 @@ # # GNU Radio is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) +# the Free Software Foundation; either version 3, or (at your option) # any later version. # # GNU Radio is distributed in the hope that it will be useful, diff --git a/rbf/Makefile.am b/rbf/Makefile.am index ae2cbab81..49d2f2592 100644 --- a/rbf/Makefile.am +++ b/rbf/Makefile.am @@ -5,7 +5,7 @@ # # GNU Radio is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) +# the Free Software Foundation; either version 3, or (at your option) # any later version. # # GNU Radio is distributed in the hope that it will be useful, diff --git a/toplevel/mrfm/mrfm.py b/toplevel/mrfm/mrfm.py index 414f5817e..100db69eb 100644 --- a/toplevel/mrfm/mrfm.py +++ b/toplevel/mrfm/mrfm.py @@ -9,7 +9,7 @@ # # GNU Radio is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) +# the Free Software Foundation; either version 3, or (at your option) # any later version. # # GNU Radio is distributed in the hope that it will be useful, diff --git a/toplevel/mrfm/mrfm_fft.py b/toplevel/mrfm/mrfm_fft.py index 9ca867082..a4db0a53d 100755 --- a/toplevel/mrfm/mrfm_fft.py +++ b/toplevel/mrfm/mrfm_fft.py @@ -9,7 +9,7 @@ # # GNU Radio is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) +# the Free Software Foundation; either version 3, or (at your option) # any later version. # # GNU Radio is distributed in the hope that it will be useful, -- cgit v1.2.3 From 3872941ae16eab596f48429057b3490b256bce6d Mon Sep 17 00:00:00 2001 From: eb Date: Wed, 5 Sep 2007 01:43:43 +0000 Subject: Merged features/inband-usb r5224:6306 into trunk. This is work-in-progress on inband signaling for the USRP1. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6307 221aa14e-8319-0410-a670-987f0aec2ac5 --- inband_lib/chan_fifo_reader.v | 356 ++++++++++++------------ inband_lib/channel_demux.v | 78 ++++++ inband_lib/channel_ram.v | 114 ++++++++ inband_lib/cmd_reader.v | 292 ++++++++++++++++++++ inband_lib/data_packet_fifo.v | 118 ++++---- inband_lib/packet_builder.v | 132 +++++++++ inband_lib/register_io.v | 60 +++++ inband_lib/rx_buffer_inband.v | 175 ++++++++++++ inband_lib/tx_buffer_inband.v | 386 +++++++++++++++------------ inband_lib/tx_packer.v | 119 +++++++++ inband_lib/usb_fifo_reader.v | 146 ++-------- inband_lib/usb_fifo_writer.v | 183 +++++++++++++ inband_lib/usb_packet_fifo2.v | 119 --------- megacells/fifo_2k_1clk.v | 167 ++++++++++++ megacells/fifo_2kx16.bsf | 99 +++++++ megacells/fifo_2kx16.cmp | 29 ++ megacells/fifo_2kx16.inc | 30 +++ megacells/fifo_2kx16.v | 167 ++++++++++++ megacells/fifo_2kx16_bb.v | 122 +++++++++ megacells/fifo_2kx16_inst.v | 11 + megacells/fifo_4kx16.bsf | 99 +++++++ megacells/fifo_4kx16.cmp | 29 ++ megacells/fifo_4kx16.inc | 30 +++ megacells/fifo_4kx16.v | 167 ++++++++++++ megacells/fifo_4kx16_bb.v | 122 +++++++++ megacells/fifo_4kx16_inst.v | 11 + megacells/fifo_512.bsf | 116 -------- megacells/fifo_512.cmp | 31 --- megacells/fifo_512.inc | 32 --- megacells/fifo_512.v | 180 ------------- megacells/fifo_512_bb.v | 131 --------- toplevel/usrp_inband_usb/config.vh | 2 +- toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 15 +- toplevel/usrp_inband_usb/usrp_inband_usb.v | 68 ++++- 34 files changed, 2780 insertions(+), 1156 deletions(-) create mode 100644 inband_lib/channel_demux.v create mode 100755 inband_lib/channel_ram.v create mode 100755 inband_lib/cmd_reader.v create mode 100755 inband_lib/packet_builder.v create mode 100755 inband_lib/register_io.v create mode 100755 inband_lib/rx_buffer_inband.v create mode 100644 inband_lib/tx_packer.v create mode 100755 inband_lib/usb_fifo_writer.v delete mode 100755 inband_lib/usb_packet_fifo2.v create mode 100755 megacells/fifo_2k_1clk.v create mode 100755 megacells/fifo_2kx16.bsf create mode 100755 megacells/fifo_2kx16.cmp create mode 100755 megacells/fifo_2kx16.inc create mode 100755 megacells/fifo_2kx16.v create mode 100755 megacells/fifo_2kx16_bb.v create mode 100755 megacells/fifo_2kx16_inst.v create mode 100755 megacells/fifo_4kx16.bsf create mode 100755 megacells/fifo_4kx16.cmp create mode 100755 megacells/fifo_4kx16.inc create mode 100755 megacells/fifo_4kx16.v create mode 100755 megacells/fifo_4kx16_bb.v create mode 100755 megacells/fifo_4kx16_inst.v delete mode 100755 megacells/fifo_512.bsf delete mode 100755 megacells/fifo_512.cmp delete mode 100755 megacells/fifo_512.inc delete mode 100755 megacells/fifo_512.v delete mode 100755 megacells/fifo_512_bb.v diff --git a/inband_lib/chan_fifo_reader.v b/inband_lib/chan_fifo_reader.v index 2b3178da7..9392bf151 100755 --- a/inband_lib/chan_fifo_reader.v +++ b/inband_lib/chan_fifo_reader.v @@ -1,197 +1,219 @@ module chan_fifo_reader - ( input reset, - input tx_clock, - input tx_strobe, - input [31:0]adc_clock, - input [3:0] samples_format, - input [15:0] fifodata, - input pkt_waiting, - output reg rdreq, - output reg skip, - output reg [15:0]tx_q, - output reg [15:0]tx_i, - output reg overrun, - output reg underrun) ; - + ( reset, tx_clock, tx_strobe, adc_time, samples_format, + fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i, + underrun, tx_empty, debug, rssi, threshhold) ; + + input wire reset ; + input wire tx_clock ; + input wire tx_strobe ; //signal to output tx_i and tx_q + input wire [31:0] adc_time ; //current time + input wire [3:0] samples_format ;// not useful at this point + input wire [31:0] fifodata ; //the data input + input wire pkt_waiting ; //signal the next packet is ready + output reg rdreq ; //actually an ack to the current fifodata + output reg skip ; //finish reading current packet + output reg [15:0] tx_q ; //top 16 bit output of fifodata + output reg [15:0] tx_i ; //bottom 16 bit output of fifodata + output reg underrun ; + output reg tx_empty ; //cause 0 to be the output + input wire [31:0] rssi; + input wire [31:0] threshhold; + + output wire [14:0] debug; + assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]}; // Should not be needed if adc clock rate < tx clock rate - `define JITTER 5 + // Used only to debug + `define JITTER 5 //Samples format // 16 bits interleaved complex samples - `define QI16 4'b0 + `define QI16 4'b0 // States - `define IDLE 4'd0 - `define READ 4'd1 - `define HEADER1 4'd2 - `define HEADER2 4'd3 - `define TIMESTAMP1 4'd4 - `define TIMESTAMP2 4'd5 - `define WAIT 4'd6 - `define WAITSTROBE 4'd7 - `define SENDWAIT 4'd8 - `define SEND 4'd9 - `define FEED 4'd10 - `define DISCARD 4'd11 + parameter IDLE = 3'd0; + parameter HEADER = 3'd1; + parameter TIMESTAMP = 3'd2; + parameter WAIT = 3'd3; + parameter WAITSTROBE = 3'd4; + parameter SEND = 3'd5; - // State registers - reg[3:0] reader_state; - reg[3:0] reader_next_state; + // Header format + `define PAYLOAD 8:2 + `define ENDOFBURST 27 + `define STARTOFBURST 28 + `define RSSI_FLAG 15 + + + /* State registers */ + reg [2:0] reader_state; + + reg [6:0] payload_len; + reg [6:0] read_len; + reg [31:0] timestamp; + reg burst; + reg trash; + reg rssi_flag; - //Variables - reg[8:0] payload_len; - reg[8:0] read_len; - reg[31:0] timestamp; - reg burst; - reg qsample; - always @(posedge tx_clock) - begin - if (reset) + always @(posedge tx_clock) + begin + if (reset) begin - reader_state <= `IDLE; - reader_next_state <= `IDLE; - rdreq <= 0; - skip <= 0; - overrun <= 0; - underrun <= 0; - burst <= 0; - qsample <= 1; - end + reader_state <= IDLE; + rdreq <= 0; + skip <= 0; + underrun <= 0; + burst <= 0; + tx_empty <= 1; + tx_q <= 0; + tx_i <= 0; + trash <= 0; + rssi_flag <= 0; + end else - begin - reader_state = reader_next_state; + begin case (reader_state) - `IDLE: - begin - if (pkt_waiting == 1) - begin - reader_next_state <= `READ; - rdreq <= 1; - underrun <= 0; - end - else if (burst == 1) + IDLE: + begin + /* + * reset all the variables and wait for a tx_strobe + * it is assumed that the ram connected to this fifo_reader + * is a short hand fifo meaning that the header to the next packet + * is already available to this fifo_reader when pkt_waiting is on + */ + skip <=0; + if (pkt_waiting == 1) + begin + reader_state <= HEADER; + rdreq <= 1; + underrun <= 0; + end + else if (burst == 1) underrun <= 1; - end - - // Just wait for the fifo data to arrive - `READ: - begin - reader_next_state <= `HEADER1; - end - - // First part of the header - `HEADER1: - begin - reader_next_state <= `HEADER2; - - //Check Start burst flag - if (fifodata[3] == 1) - burst <= 1; - if (fifodata[4] == 1) - burst <= 0; - end + if (tx_strobe == 1) + tx_empty <= 1 ; + end - // Read payload length - `HEADER2: - begin - payload_len <= (fifodata & 16'h1FF); - read_len <= 9'd0; - reader_next_state <= `TIMESTAMP1; - end + /* Process header */ + HEADER: + begin + if (tx_strobe == 1) + tx_empty <= 1 ; + + rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST]; + //Check Start/End burst flag + if (fifodata[`STARTOFBURST] == 1 + && fifodata[`ENDOFBURST] == 1) + burst <= 0; + else if (fifodata[`STARTOFBURST] == 1) + burst <= 1; + else if (fifodata[`ENDOFBURST] == 1) + burst <= 0; - `TIMESTAMP1: - begin - timestamp <= {fifodata, 16'b0}; - rdreq <= 0; - reader_next_state <= `TIMESTAMP2; - end - - `TIMESTAMP2: - begin - timestamp <= timestamp + fifodata; - reader_next_state <= `WAIT; - end + if (trash == 1 && fifodata[`STARTOFBURST] == 0) + begin + skip <= 1; + reader_state <= IDLE; + rdreq <= 0; + end + else + begin + payload_len <= fifodata[`PAYLOAD] ; + read_len <= 0; + rdreq <= 1; + reader_state <= TIMESTAMP; + end + end + + TIMESTAMP: + begin + timestamp <= fifodata; + reader_state <= WAIT; + if (tx_strobe == 1) + tx_empty <= 1 ; + rdreq <= 0; + end - // Decide if we wait, send or discard samples - `WAIT: - begin - // Wait a little bit more - if (timestamp > adc_clock + `JITTER) - reader_next_state <= `WAIT; + // Decide if we wait, send or discard samples + WAIT: + begin + if (tx_strobe == 1) + tx_empty <= 1 ; + // Let's send it - else if ((timestamp < adc_clock + `JITTER - && timestamp > adc_clock) - || timestamp == 32'hFFFFFFFF) - begin - reader_next_state <= `WAITSTROBE; - end + if ((timestamp <= adc_time + `JITTER + && timestamp > adc_time) + || timestamp == 32'hFFFFFFFF) + begin + if (rssi <= threshhold || rssi_flag == 0) + begin + trash <= 0; + reader_state <= WAITSTROBE; + end + else + reader_state <= WAIT; + end + // Wait a little bit more + else if (timestamp > adc_time + `JITTER) + reader_state <= WAIT; // Outdated - else if (timestamp < adc_clock) - begin - reader_next_state <= `DISCARD; - skip <= 1; + else if (timestamp < adc_time) + begin + trash <= 1; + reader_state <= IDLE; + skip <= 1; end - end + end - // Wait for the transmit chain to be ready - `WAITSTROBE: - begin - // If end of payload... - if (read_len == payload_len) + // Wait for the transmit chain to be ready + WAITSTROBE: + begin + // If end of payload... + if (read_len == payload_len) + begin + reader_state <= IDLE; + skip <= 1; + if (tx_strobe == 1) + tx_empty <= 1 ; + end + else if (tx_strobe == 1) + begin + reader_state <= SEND; + rdreq <= 1; + end + end + + // Send the samples to the tx_chain + SEND: + begin + reader_state <= WAITSTROBE; + read_len <= read_len + 7'd1; + tx_empty <= 0; + rdreq <= 0; + + case(samples_format) + `QI16: begin - reader_next_state <= `DISCARD; - skip <= (payload_len < 508); + tx_i <= fifodata[15:0]; + tx_q <= fifodata[31:16]; end - - if (tx_strobe == 1) - reader_next_state <= `SENDWAIT; - end - - `SENDWAIT: - begin - rdreq <= 1; - reader_next_state <= `SEND; - end - - // Send the samples to the tx_chain - `SEND: - begin - reader_next_state <= `WAITSTROBE; - rdreq <= 0; - read_len <= read_len + 2; - case(samples_format) - `QI16: - begin - tx_q <= qsample ? fifodata : 16'bZ; - tx_i <= ~qsample ? fifodata : 16'bZ; - qsample <= ~ qsample; - end + + // Assume 16 bits complex samples by default default: - begin - // Assume 16 bits complex samples by default - $display ("Error unknown samples format"); - tx_q <= qsample ? fifodata : 16'bZ; - tx_i <= ~qsample ? fifodata : 16'bZ; - qsample <= ~ qsample; - end - endcase - end - - `DISCARD: - begin - skip <= 0; - reader_next_state <= `IDLE; - end + begin + tx_i <= fifodata[15:0]; + tx_q <= fifodata[31:16]; + end + endcase + end default: - begin - $display ("Error unknown state"); - reader_state <= `IDLE; - reader_next_state <= `IDLE; - end + begin + //error handling + reader_state <= IDLE; + end endcase end end -endmodule \ No newline at end of file +endmodule diff --git a/inband_lib/channel_demux.v b/inband_lib/channel_demux.v new file mode 100644 index 000000000..d46be9397 --- /dev/null +++ b/inband_lib/channel_demux.v @@ -0,0 +1,78 @@ +module channel_demux + #(parameter NUM_CHAN = 2, parameter CHAN_WIDTH = 2) ( //usb Side + input [31:0]usbdata_final, + input WR_final, + + // TX Side + input reset, + input txclk, + output reg [CHAN_WIDTH:0] WR_channel, + output reg [31:0] ram_data, + output reg [CHAN_WIDTH:0] WR_done_channel ); +/* Parse header and forward to ram */ + reg [2:0]reader_state; + reg [4:0]channel ; + reg [6:0]read_length ; + + // States + parameter IDLE = 3'd0; + parameter HEADER = 3'd1; + parameter WAIT = 3'd2; + parameter FORWARD = 3'd3; + + `define CHANNEL 20:16 + `define PKT_SIZE 127 + wire [4:0] true_channel; + assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ? + NUM_CHAN : (usbdata_final[`CHANNEL]); + + always @(posedge txclk) + begin + if (reset) + begin + reader_state <= IDLE; + WR_channel <= 0; + WR_done_channel <= 0; + end + else + case (reader_state) + IDLE: begin + if (WR_final) + reader_state <= HEADER; + end + + // Store channel and forware header + HEADER: begin + channel <= true_channel; + WR_channel[true_channel] <= 1; + ram_data <= usbdata_final; + read_length <= 7'd0 ; + + reader_state <= WAIT; + end + + WAIT: begin + WR_channel[channel] <= 0; + + if (read_length == `PKT_SIZE) + reader_state <= IDLE; + else if (WR_final) + reader_state <= FORWARD; + end + + FORWARD: begin + WR_channel[channel] <= 1; + ram_data <= usbdata_final; + read_length <= read_length + 7'd1; + + reader_state <= WAIT; + end + + default: + begin + //error handling + reader_state <= IDLE; + end + endcase + end +endmodule diff --git a/inband_lib/channel_ram.v b/inband_lib/channel_ram.v new file mode 100755 index 000000000..40e0efc01 --- /dev/null +++ b/inband_lib/channel_ram.v @@ -0,0 +1,114 @@ +module channel_ram + ( // System + input txclk, + input reset, + + // USB side + input [31:0] datain, + input WR, + input WR_done, + output have_space, + + // Reader side + output [31:0] dataout, + input RD, + input RD_done, + output packet_waiting); + + reg [6:0] wr_addr, rd_addr; + reg [1:0] which_ram_wr, which_ram_rd; + reg [2:0] nb_packets; + + reg [31:0] ram0 [0:127]; + reg [31:0] ram1 [0:127]; + reg [31:0] ram2 [0:127]; + reg [31:0] ram3 [0:127]; + + reg [31:0] dataout0; + reg [31:0] dataout1; + reg [31:0] dataout2; + reg [31:0] dataout3; + + wire wr_done_int; + wire rd_done_int; + wire [6:0] rd_addr_final; + wire [1:0] which_ram_rd_final; + + // USB side + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain; + + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain; + + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain; + + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain; + + assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done); + + always @(posedge txclk) + if(reset) + wr_addr <= 0; + else if (WR_done) + wr_addr <= 0; + else if (WR) + wr_addr <= wr_addr + 7'd1; + + always @(posedge txclk) + if(reset) + which_ram_wr <= 0; + else if (wr_done_int) + which_ram_wr <= which_ram_wr + 2'd1; + + assign have_space = (nb_packets < 3'd3); + + // Reader side + // short hand fifo + // rd_addr_final is what rd_addr is going to be next clock cycle + // which_ram_rd_final is what which_ram_rd is going to be next clock cycle + always @(posedge txclk) dataout0 <= ram0[rd_addr_final]; + always @(posedge txclk) dataout1 <= ram1[rd_addr_final]; + always @(posedge txclk) dataout2 <= ram2[rd_addr_final]; + always @(posedge txclk) dataout3 <= ram3[rd_addr_final]; + + assign dataout = (which_ram_rd_final[1]) ? + (which_ram_rd_final[0] ? dataout3 : dataout2) : + (which_ram_rd_final[0] ? dataout1 : dataout0); + + //RD_done is the only way to signal the end of one packet + assign rd_done_int = RD_done; + + always @(posedge txclk) + if (reset) + rd_addr <= 0; + else if (RD_done) + rd_addr <= 0; + else if (RD) rd_addr <= rd_addr + 7'd1; + + assign rd_addr_final = (reset|RD_done) ? (6'd0) : + ((RD)?(rd_addr+7'd1):rd_addr); + always @(posedge txclk) + if (reset) + which_ram_rd <= 0; + else if (rd_done_int) + which_ram_rd <= which_ram_rd + 2'd1; + + assign which_ram_rd_final = (reset) ? (2'd0): + ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd); + + //packet_waiting is set to zero if rd_done_int is high + //because there is no guarantee that nb_packets will be pos. + assign packet_waiting = (nb_packets != 0) & (~rd_done_int); + + always @(posedge txclk) + if (reset) + nb_packets <= 0; + else if (wr_done_int & ~rd_done_int) + nb_packets <= nb_packets + 3'd1; + else if (rd_done_int & ~wr_done_int) + nb_packets <= nb_packets - 3'd1; + +endmodule \ No newline at end of file diff --git a/inband_lib/cmd_reader.v b/inband_lib/cmd_reader.v new file mode 100755 index 000000000..7604321e4 --- /dev/null +++ b/inband_lib/cmd_reader.v @@ -0,0 +1,292 @@ +module cmd_reader( + //System + input reset, + input txclk, + input [31:0] adc_time, + //FX2 Side + output reg skip, + output reg rdreq, + input [31:0] fifodata, + input pkt_waiting, + //Rx side + input rx_WR_enabled, + output reg [15:0] rx_databus, + output reg rx_WR, + output reg rx_WR_done, + //register io + input wire [31:0] reg_data_out, + output reg [31:0] reg_data_in, + output reg [6:0] reg_addr, + output reg [1:0] reg_io_enable, + output wire [14:0] debug + ); + + // States + parameter IDLE = 4'd0; + parameter HEADER = 4'd1; + parameter TIMESTAMP = 4'd2; + parameter WAIT = 4'd3; + parameter TEST = 4'd4; + parameter SEND = 4'd5; + parameter PING = 4'd6; + parameter WRITE_REG = 4'd7; + parameter WRITE_REG_MASKED = 4'd8; + parameter READ_REG = 4'd9; + parameter DELAY = 4'd14; + + `define OP_PING_FIXED 8'd0 + `define OP_PING_FIXED_REPLY 8'd1 + `define OP_WRITE_REG 8'd2 + `define OP_WRITE_REG_MASKED 8'd3 + `define OP_READ_REG 8'd4 + `define OP_READ_REG_REPLY 8'd5 + `define OP_DELAY 8'd12 + + reg [6:0] payload; + reg [6:0] payload_read; + reg [3:0] state; + reg [15:0] high; + reg [15:0] low; + reg pending; + reg [31:0] value0; + reg [31:0] value1; + reg [31:0] value2; + reg [1:0] lines_in; + reg [1:0] lines_out; + reg [1:0] lines_out_total; + + `define JITTER 5 + `define OP_CODE 31:24 + `define PAYLOAD 8:2 + + wire [7:0] ops; + assign ops = value0[`OP_CODE]; + assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]}; + + always @(posedge txclk) + if (reset) + begin + pending <= 0; + state <= IDLE; + skip <= 0; + rdreq <= 0; + rx_WR <= 0; + reg_io_enable <= 0; + reg_data_in <= 0; + reg_addr <= 0; + end + else case (state) + IDLE : begin + payload_read <= 0; + skip <= 0; + lines_in <= 0; + if (pkt_waiting) + begin + state <= HEADER; + rdreq <= 1; + end + end + + HEADER : begin + payload <= fifodata[`PAYLOAD]; + state <= TIMESTAMP; + end + + TIMESTAMP : begin + value0 <= fifodata; + state <= WAIT; + rdreq <= 0; + end + + WAIT : begin + // Let's send it + if ((value0 <= adc_time + `JITTER + && value0 > adc_time) + || value0 == 32'hFFFFFFFF) + state <= TEST; + // Wait a little bit more + else if (value0 > adc_time + `JITTER) + state <= WAIT; + // Outdated + else if (value0 < adc_time) + begin + state <= IDLE; + skip <= 1; + end + end + + TEST : begin + reg_io_enable <= 0; + rx_WR <= 0; + rx_WR_done <= 1; + if (payload_read == payload) + begin + skip <= 1; + state <= IDLE; + rdreq <= 0; + end + else + begin + value0 <= fifodata; + lines_in <= 2'd1; + rdreq <= 1; + payload_read <= payload_read + 7'd1; + lines_out <= 0; + case (fifodata[`OP_CODE]) + `OP_PING_FIXED: begin + state <= PING; + end + `OP_WRITE_REG: begin + state <= WRITE_REG; + pending <= 1; + end + `OP_WRITE_REG_MASKED: begin + state <= WRITE_REG_MASKED; + pending <= 1; + end + `OP_READ_REG: begin + state <= READ_REG; + end + `OP_DELAY: begin + state <= DELAY; + end + default: begin + //error, skip this packet + skip <= 1; + state <= IDLE; + end + endcase + end + end + + SEND: begin + rdreq <= 0; + rx_WR_done <= 0; + if (pending) + begin + rx_WR <= 1; + rx_databus <= high; + pending <= 0; + if (lines_out == lines_out_total) + state <= TEST; + else case (ops) + `OP_READ_REG: begin + state <= READ_REG; + end + default: begin + state <= TEST; + end + endcase + end + else + begin + if (rx_WR_enabled) + begin + rx_WR <= 1; + rx_databus <= low; + pending <= 1; + lines_out <= lines_out + 2'd1; + end + else + rx_WR <= 0; + end + end + + PING: begin + rx_WR <= 0; + rdreq <= 0; + rx_WR_done <= 0; + lines_out_total <= 2'd1; + pending <= 0; + state <= SEND; + high <= {`OP_PING_FIXED_REPLY, 8'd2}; + low <= value0[15:0]; + end + + READ_REG: begin + rx_WR <= 0; + rx_WR_done <= 0; + rdreq <= 0; + lines_out_total <= 2'd2; + pending <= 0; + state <= SEND; + if (lines_out == 0) + begin + high <= {`OP_READ_REG_REPLY, 8'd6}; + low <= value0[15:0]; + reg_io_enable <= 2'd3; + reg_addr <= value0[6:0]; + end + else + begin + high <= reg_data_out[31:16]; + low <= reg_data_out[15:0]; + end + end + + WRITE_REG: begin + rx_WR <= 0; + if (pending) + pending <= 0; + else + begin + if (lines_in == 2'd1) + begin + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value1 <= fifodata; + rdreq <= 0; + end + else + begin + reg_io_enable <= 2'd2; + reg_data_in <= value1; + reg_addr <= value0[6:0]; + state <= TEST; + end + end + end + + WRITE_REG_MASKED: begin + rx_WR <= 0; + if (pending) + pending <= 0; + else + begin + if (lines_in == 2'd1) + begin + rdreq <= 1; + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value1 <= fifodata; + end + else if (lines_in == 2'd2) + begin + rdreq <= 0; + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value2 <= fifodata; + end + else + begin + reg_io_enable <= 2'd2; + reg_data_in <= (value1 & value2); + reg_addr <= value0[6:0]; + state <= TEST; + end + end + end + + DELAY : begin + rdreq <= 0; + value1 <= value1 + 32'd1; + if (value0[15:0] == value1[15:0]) + state <= TEST; + end + + default : begin + //error state handling + state <= IDLE; + end + endcase +endmodule \ No newline at end of file diff --git a/inband_lib/data_packet_fifo.v b/inband_lib/data_packet_fifo.v index 5b37b14ea..a9bcbdae7 100755 --- a/inband_lib/data_packet_fifo.v +++ b/inband_lib/data_packet_fifo.v @@ -1,128 +1,118 @@ module data_packet_fifo ( input reset, input clock, - input [15:0]ram_data_in, + input [31:0]ram_data_in, input write_enable, output reg have_space, - output reg [15:0]ram_data_out, + output reg [31:0]ram_data_out, output reg pkt_waiting, + output reg isfull, + output reg [1:0]usb_ram_packet_out, + output reg [1:0]usb_ram_packet_in, input read_enable, input pkt_complete, input skip_packet) ; /* Some parameters for usage later on */ - parameter DATA_WIDTH = 16 ; + parameter DATA_WIDTH = 32 ; + parameter PKT_DEPTH = 128 ; parameter NUM_PACKETS = 4 ; /* Create the RAM here */ - reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ; + reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ; /* Create the address signals */ - reg [7:0] usb_ram_offset_out ; - reg [1:0] usb_ram_packet_out ; - reg [7:0] usb_ram_offset_in ; - reg [1:0] usb_ram_packet_in ; + reg [6:0] usb_ram_offset_out ; + //reg [1:0] usb_ram_packet_out ; + reg [6:0] usb_ram_offset_in ; + //reg [1:0] usb_ram_packet_in ; - wire [7-2+NUM_PACKETS:0] usb_ram_aout ; - wire [7-2+NUM_PACKETS:0] usb_ram_ain ; - reg isfull; + wire [6-2+NUM_PACKETS:0] usb_ram_aout ; + wire [6-2+NUM_PACKETS:0] usb_ram_ain ; + //reg isfull; assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ; assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ; // Check if there is one full packet to process - always @(usb_ram_ain, usb_ram_aout) + always @(usb_ram_ain, usb_ram_aout, isfull) begin - if (reset) - pkt_waiting <= 0; - else if (usb_ram_ain >= usb_ram_aout) - pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256; + if (usb_ram_ain == usb_ram_aout) + pkt_waiting <= isfull ; + else if (usb_ram_ain > usb_ram_aout) + pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= PKT_DEPTH; else - pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256; + pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >= PKT_DEPTH; end - + // Check if there is room - always @(usb_ram_ain, usb_ram_aout) + always @(usb_ram_ain, usb_ram_aout, isfull) begin - if (reset) - have_space <= 1; - else if (usb_ram_ain == usb_ram_aout) + if (usb_ram_ain == usb_ram_aout) have_space <= ~isfull; else if (usb_ram_ain > usb_ram_aout) - have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1); + have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH * (NUM_PACKETS - 1))? 1'b1 : 1'b0; else - have_space <= (usb_ram_aout - usb_ram_ain) >= 256; + have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH; end - /* RAM Write Address process */ - always @(posedge clock) - begin - if( reset ) - begin - usb_ram_offset_in <= 0 ; - usb_ram_packet_in <= 0 ; - end - else - if( pkt_complete ) - begin - usb_ram_packet_in <= usb_ram_packet_in + 1; - usb_ram_offset_in <= 0; - end - else if( write_enable ) - begin - if (usb_ram_offset_in == 8'b11111111) - begin - usb_ram_offset_in <= 0; - usb_ram_packet_in <= usb_ram_packet_in + 1; - end - else - usb_ram_offset_in <= usb_ram_offset_in + 1 ; - if (usb_ram_ain + 1 == usb_ram_aout) - isfull <= 1; - end - end - /* RAM Writing process */ + + /* RAM Writing/Reading process */ always @(posedge clock) begin if( write_enable ) begin usb_ram[usb_ram_ain] <= ram_data_in ; end + ram_data_out <= usb_ram[usb_ram_aout] ; end - /* RAM Read Address process */ + /* RAM Write/Read Address process */ always @(posedge clock) begin if( reset ) begin usb_ram_packet_out <= 0 ; usb_ram_offset_out <= 0 ; + usb_ram_offset_in <= 0 ; + usb_ram_packet_in <= 0 ; isfull <= 0; end else + begin if( skip_packet ) begin usb_ram_packet_out <= usb_ram_packet_out + 1 ; usb_ram_offset_out <= 0 ; + isfull <= 0; end - else if(read_enable) begin - if( usb_ram_offset_out == 8'b11111111 ) + else if(read_enable) + begin + if( usb_ram_offset_out == 7'b1111111 ) begin + isfull <= 0 ; usb_ram_offset_out <= 0 ; usb_ram_packet_out <= usb_ram_packet_out + 1 ; end else usb_ram_offset_out <= usb_ram_offset_out + 1 ; - end - if (usb_ram_ain == usb_ram_aout) - isfull <= 0; - end - - /* RAM Reading Process */ - always @(posedge clock) - begin - ram_data_out <= usb_ram[usb_ram_aout] ; + end + if( pkt_complete ) + begin + usb_ram_packet_in <= usb_ram_packet_in + 1 ; + usb_ram_offset_in <= 0 ; + if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out) + isfull <= 1 ; + end + else if( write_enable ) + begin + if (usb_ram_offset_in == 7'b1111111) + usb_ram_offset_in <= 7'b1111111 ; + else + usb_ram_offset_in <= usb_ram_offset_in + 1 ; + end + end end endmodule diff --git a/inband_lib/packet_builder.v b/inband_lib/packet_builder.v new file mode 100755 index 000000000..205293479 --- /dev/null +++ b/inband_lib/packet_builder.v @@ -0,0 +1,132 @@ +module packet_builder #(parameter NUM_CHAN = 1)( + // System + input rxclk, + input reset, + input [31:0] adctime, + input [3:0] channels, + // ADC side + input [15:0]chan_fifodata, + input [NUM_CHAN:0]chan_empty, + input [9:0]chan_usedw, + output reg [3:0]rd_select, + output reg chan_rdreq, + // FX2 side + output reg WR, + output reg [15:0]fifodata, + input have_space, + input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2, + input wire [31:0]rssi_3, output wire [7:0] debugbus); + + + // States + `define IDLE 3'd0 + `define HEADER1 3'd1 + `define HEADER2 3'd2 + `define TIMESTAMP 3'd3 + `define FORWARD 3'd4 + + `define MAXPAYLOAD 504 + + `define PAYLOAD_LEN 8:0 + `define TAG 12:9 + `define MBZ 15:13 + + `define CHAN 4:0 + `define RSSI 10:5 + `define BURST 12:11 + `define DROPPED 13 + `define UNDERRUN 14 + `define OVERRUN 15 + + reg [2:0] state; + reg [8:0] read_length; + reg [8:0] payload_len; + reg tstamp_complete; + reg [3:0] check_next; + wire [8:0] chan_used; + wire [31:0] true_rssi; + + assign debugbus = {state, chan_empty[0], chan_empty[1], check_next[0], + have_space, rd_select[0]}; + assign chan_used = chan_usedw[8:0]; + assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) : + ((rd_select[0]) ? rssi_1:rssi_0); + always @(posedge rxclk) + begin + if (reset) + begin + WR <= 0; + rd_select <= 0; + chan_rdreq <= 0; + tstamp_complete <= 0; + check_next <= 0; + state <= `IDLE; + end + else case (state) + `IDLE: begin + if (have_space) + begin + if(~chan_empty[check_next]) + begin + state <= #1 `HEADER1; + rd_select <= #1 check_next; + end + check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1); + end + end + + `HEADER1: begin + fifodata[`PAYLOAD_LEN] <= #1 (chan_used > 9'd252 + ? 9'd252 : chan_used << 1); + payload_len <= #1 (chan_used > 9'd252 + ? 9'd252 : chan_used << 1); + fifodata[`TAG] <= #1 0; + fifodata[`MBZ] <= #1 0; + WR <= #1 1; + + state <= #1 `HEADER2; + read_length <= #1 0; + end + + `HEADER2: begin + fifodata[`CHAN] <= #1 (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); + fifodata[`RSSI] <= #1 true_rssi[5:0]; + fifodata[`BURST] <= #1 0; + fifodata[`DROPPED] <= #1 0; + fifodata[`UNDERRUN] <= #1 0; + fifodata[`OVERRUN] <= #1 0; + + state <= #1 `TIMESTAMP; + end + + `TIMESTAMP: begin + fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]); + tstamp_complete <= #1 ~tstamp_complete; + + if (~tstamp_complete) + chan_rdreq <= #1 1; + + state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP); + end + + `FORWARD: begin + read_length <= #1 read_length + 9'd2; + fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata); + + if (read_length >= `MAXPAYLOAD) + begin + WR <= #1 0; + state <= #1 `IDLE; + end + else if (read_length == payload_len - 4) + chan_rdreq <= #1 0; + end + + default: begin + //handling error state + state <= `IDLE; + end + endcase + end +endmodule + diff --git a/inband_lib/register_io.v b/inband_lib/register_io.v new file mode 100755 index 000000000..63a26549c --- /dev/null +++ b/inband_lib/register_io.v @@ -0,0 +1,60 @@ +module register_io + (input clk, input reset, input wire [1:0] enable, input wire [6:0] addr, + input wire [31:0] datain, output reg [31:0] dataout, output wire [15:0] debugbus, + input wire [31:0] rssi_0, input wire [31:0] rssi_1, + input wire [31:0] rssi_2, input wire [31:0] rssi_3, output wire [31:0] threshhold); + + reg strobe; + wire [31:0] out[7:0]; + assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]}; + assign threshhold = out[1]; + + always @(*) + if (reset | ~enable[1]) + begin + strobe <= 0; + dataout <= 0; + end + else + begin + if (enable[0]) + begin + //read + if (addr == 7'd9) + dataout <= rssi_0; + else if (addr == 7'd10) + dataout <= rssi_1; + else if (addr == 7'd11) + dataout <= rssi_2; + else if (addr == 7'd12) + dataout <= rssi_3; + else + dataout <= out[addr[2:0]]; + strobe <= 0; + end + else + begin + //write + dataout <= dataout; + strobe <= 1; + end + end + + //register declarations + setting_reg #(0) setting_reg0(.clock(clk),.reset(reset), + .strobe(strobe),.addr(addr),.in(datain),.out(out[0])); + setting_reg #(1) setting_reg1(.clock(clk),.reset(reset), + .strobe(strobe),.addr(addr),.in(datain),.out(out[1])); + setting_reg #(2) setting_reg2(.clock(clk),.reset(reset), + .strobe(strobe),.addr(addr),.in(datain),.out(out[2])); + setting_reg #(3) setting_reg3(.clock(clk),.reset(reset), + .strobe(strobe),.addr(addr),.in(datain),.out(out[3])); + setting_reg #(4) setting_reg4(.clock(clk),.reset(reset), + .strobe(strobe),.addr(addr),.in(datain),.out(out[4])); + setting_reg #(5) setting_reg5(.clock(clk),.reset(reset), + .strobe(strobe),.addr(addr),.in(datain),.out(out[5])); + setting_reg #(6) setting_reg6(.clock(clk),.reset(reset), + .strobe(strobe),.addr(addr),.in(datain),.out(out[6])); + setting_reg #(7) setting_reg7(.clock(clk),.reset(reset), + .strobe(strobe),.addr(addr),.in(datain),.out(out[7])); +endmodule \ No newline at end of file diff --git a/inband_lib/rx_buffer_inband.v b/inband_lib/rx_buffer_inband.v new file mode 100755 index 000000000..c23ce09b7 --- /dev/null +++ b/inband_lib/rx_buffer_inband.v @@ -0,0 +1,175 @@ +//`include "../../firmware/include/fpga_regs_common.v" +//`include "../../firmware/include/fpga_regs_standard.v" +module rx_buffer_inband + ( input usbclk, + input bus_reset, + input reset, // DSP side reset (used here), do not reset registers + input reset_regs, //Only reset registers + output [15:0] usbdata, + input RD, + output wire have_pkt_rdy, + output reg rx_overrun, + input wire [3:0] channels, + input wire [15:0] ch_0, + input wire [15:0] ch_1, + input wire [15:0] ch_2, + input wire [15:0] ch_3, + input wire [15:0] ch_4, + input wire [15:0] ch_5, + input wire [15:0] ch_6, + input wire [15:0] ch_7, + input rxclk, + input rxstrobe, + input clear_status, + input [6:0] serial_addr, + input [31:0] serial_data, + input serial_strobe, + output wire [15:0] debugbus, + + //Connection with tx_inband + input rx_WR, + input [15:0] rx_databus, + input rx_WR_done, + output reg rx_WR_enabled, + //signal strength + input wire [31:0] rssi_0, input wire [31:0] rssi_1, + input wire [31:0] rssi_2, input wire [31:0] rssi_3 + ); + + parameter NUM_CHAN = 1; + genvar i ; + + // FX2 Bug Fix + reg [8:0] read_count; + always @(negedge usbclk) + if(bus_reset) + read_count <= #1 9'd0; + else if(RD & ~read_count[8]) + read_count <= #1 read_count + 9'd1; + else + read_count <= #1 RD ? read_count : 9'b0; + + // Time counter + reg [31:0] adctime; + always @(posedge rxclk) + if (reset) + adctime <= 0; + else if (rxstrobe) + adctime <= adctime + 1; + + // USB side fifo + wire [11:0] rdusedw; + wire [11:0] wrusedw; + wire [15:0] fifodata; + wire WR; + wire have_space; + + fifo_4kx16_dc rx_usb_fifo ( + .aclr ( reset ), + .data ( fifodata ), + .rdclk ( ~usbclk ), + .rdreq ( RD & ~read_count[8] ), + .wrclk ( rxclk ), + .wrreq ( WR ), + .q ( usbdata ), + .rdempty ( ), + .rdusedw ( rdusedw ), + .wrfull ( ), + .wrusedw ( wrusedw ) ); + + assign have_pkt_rdy = (rdusedw >= 12'd256); + assign have_space = (wrusedw < 12'd760); + + // Rx side fifos + wire chan_rdreq; + wire [15:0] chan_fifodata; + wire [9:0] chan_usedw; + wire [NUM_CHAN:0] chan_empty; + wire [3:0] rd_select; + wire [NUM_CHAN:0] rx_full; + + packet_builder #(NUM_CHAN) rx_pkt_builer ( + .rxclk ( rxclk ), + .reset ( reset ), + .adctime ( adctime ), + .channels ( 4'd1 ), + .chan_rdreq ( chan_rdreq ), + .chan_fifodata ( chan_fifodata ), + .chan_empty ( chan_empty ), + .rd_select ( rd_select ), + .chan_usedw ( chan_usedw ), + .WR ( WR ), + .fifodata ( fifodata ), + .have_space ( have_space ), + .rssi_0(rssi_0), .rssi_1(rssi_1), + .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug)); + + // Detect overrun + always @(posedge rxclk) + if(reset) + rx_overrun <= 1'b0; + else if(rx_full[0]) + rx_overrun <= 1'b1; + else if(clear_status) + rx_overrun <= 1'b0; + + reg [6:0] test; + always @(posedge rxclk) + if (reset) + test <= 0; + else + test <= test + 7'd1; + + // TODO write this genericly + wire [15:0]ch[NUM_CHAN:0]; + assign ch[0] = ch_0; + + wire cmd_empty; + always @(posedge rxclk) + if(reset) + rx_WR_enabled <= 1; + else if(cmd_empty) + rx_WR_enabled <= 1; + else if(rx_WR_done) + rx_WR_enabled <= 0; + + wire [15:0] dataout [0:NUM_CHAN]; + wire [9:0] usedw [0:NUM_CHAN]; + + generate for (i = 0 ; i < NUM_CHAN; i = i + 1) + begin : generate_channel_fifos + wire rdreq; + + assign rdreq = (rd_select == i) & chan_rdreq; + assign chan_empty[i] = usedw[i] < 10'd126; + + fifo_2kx16 rx_chan_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( ch[i] ), + .rdreq ( rdreq ), + .wrreq ( ~rx_full[i] & rxstrobe), + .empty ( ), + .full ( rx_full[i] ), + .q ( dataout[i]), + .usedw ( usedw[i] ) + ); + end + endgenerate + wire [7:0] debug; + fifo_2kx16 rx_cmd_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( rx_databus ), + .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), + .wrreq ( rx_WR & rx_WR_enabled), + .empty ( cmd_empty), + .full ( rx_full[NUM_CHAN] ), + .q ( dataout[NUM_CHAN]), + .usedw ( usedw[NUM_CHAN] ) + ); + assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; + assign chan_fifodata = dataout[rd_select]; + assign chan_usedw = usedw[rd_select]; + assign debugbus = {wrusedw, have_space, RD, read_count[8], rxclk}; +endmodule diff --git a/inband_lib/tx_buffer_inband.v b/inband_lib/tx_buffer_inband.v index 56c07807a..af7ed394a 100755 --- a/inband_lib/tx_buffer_inband.v +++ b/inband_lib/tx_buffer_inband.v @@ -1,183 +1,227 @@ module tx_buffer_inband - ( input usbclk, - input bus_reset, // Used here for the 257-Hack to fix the FX2 bug - input reset, // standard DSP-side reset - input [15:0] usbdata, - input wire WR, - output wire have_space, - output reg tx_underrun, - input wire [3:0] channels, - output [15:0] tx_i_0, - output [15:0] tx_q_0, - output [15:0] tx_i_1, - output [15:0] tx_q_1, - //NOT USED - output reg [15:0] tx_i_2, - output reg [15:0] tx_q_2, - output reg [15:0] tx_i_3, - output reg [15:0] tx_q_3, - input txclk, - input txstrobe, - input clear_status, - output wire tx_empty, - output [11:0] debugbus - ); + ( usbclk, bus_reset, reset, usbdata, WR, have_space, + tx_underrun, channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1, + tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe, + clear_status, tx_empty, debugbus, + rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable, + reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2, + rssi_3, threshhold + ); - wire [15:0] tx_data_bus; + //CHAN_WIDTH is the width of the channel + //NUM_CHAN is the number of data channel (index from 0 to NUM_CHAN-1) + //index NUM_CHAN is reserved for command + + parameter CHAN_WIDTH = 2 ; + parameter NUM_CHAN = 2 ; + /* Debug paramters */ + parameter STROBE_RATE_0 = 8'd1 ; + parameter STROBE_RATE_1 = 8'd2 ; + + input wire usbclk ; + input wire bus_reset ; // Used here for the 257-Hack to fix the FX2 bug + input wire reset ; // standard DSP-side reset + input wire [15:0] usbdata ; + input wire WR ; + input wire txclk ; + input wire txstrobe ; + input wire rx_WR_enabled; + /* Not used yet */ + input wire [3:0] channels ; + input wire clear_status ; + /*register io*/ + input wire [31:0]reg_data_out; + // rssi + input wire [31:0]rssi_0; + input wire [31:0]rssi_1; + input wire [31:0]rssi_2; + input wire [31:0]rssi_3; + input wire [31:0]threshhold; - wire WR_chan_0; - wire chan_0_done; - wire OR0; - wire UR0; - - wire WR_chan_1; - wire chan_1_done; - wire OR1; - wire UR1; - - // NOT USED yet - wire WR_cmd; - wire cmd_done; - - //EXTERNAL REGISTER - //TODO: increment it - reg [31:0] time_counter; - reg [7:0] txstrobe_rate_0; - reg [7:0] txstrobe_rate_1; - - - //Usb block - wire [15:0] tupf_fifodata; - wire tupf_pkt_waiting; - wire tupf_rdreq; - wire tupf_skip; - wire tupf_have_space; + output wire have_space ; + output wire tx_underrun ; + output wire tx_empty ; + output wire [15:0] tx_i_0 ; + output wire [15:0] tx_q_0 ; + output wire [15:0] tx_i_1 ; + output wire [15:0] tx_q_1 ; + output wire [15:0] debugbus ; + /* Not used yet */ + output wire [15:0] tx_i_2 ; + output wire [15:0] tx_q_2 ; + output wire [15:0] tx_i_3 ; + output wire [15:0] tx_q_3 ; + + output wire [15:0] rx_databus ; + output wire rx_WR; + output wire rx_WR_done; + /* reg_io */ + output wire [31:0] reg_data_in; + output wire [6:0] reg_addr; + output wire [1:0] reg_io_enable; + + /* To generate channel readers */ + genvar i ; + + /* These will eventually be external register */ + reg [31:0] adc_time ; + wire [7:0] txstrobe_rate [CHAN_WIDTH-1:0] ; + wire [31:0] rssi [3:0]; + assign rssi[0] = rssi_0; + assign rssi[1] = rssi_1; + assign rssi[2] = rssi_2; + assign rssi[3] = rssi_3; - usb_packet_fifo2 tx_usb_packet_fifo - ( .reset (reset), - .usb_clock (usbclk), - .fpga_clock (txclk), - .write_data (usbdata), - .write_enable (WR), - .read_data (tupf_fifodata), - .pkt_waiting (tupf_pkt_waiting), - .read_enable (tupf_rdreq), - .skip_packet (tupf_skip), - .have_space (tupf_have_space), - .tx_empty (tx_empty) - ); + always @(posedge txclk) + if (reset) + adc_time <= 0; + else if (txstrobe) + adc_time <= adc_time + 1; + + + /* Connections between tx_usb_fifo_reader and + cnannel/command processing blocks */ + wire [31:0] tx_data_bus ; + wire [CHAN_WIDTH:0] chan_WR ; + wire [CHAN_WIDTH:0] chan_done ; + + /* Connections between data block and the + FX2/TX chains */ + wire [CHAN_WIDTH:0] chan_underrun ; + wire [CHAN_WIDTH:0] chan_txempty ; - usb_fifo_reader tx_usb_packet_reader ( - .reset(reset), - .tx_clock(txclk), - .tx_data_bus(tx_data_bus), - .WR_chan_0(WR_chan_0), - .WR_chan_1(WR_chan_1), - .WR_cmd(WR_cmd), - .chan_0_done(chan_0_done), - .chan_1_done(chan_1_done), - .cmd_done(cmd_done), - .rdreq(tupf_rdreq), - .skip(tupf_skip), - .pkt_waiting(tupf_pkt_waiting), - .fifodata(tupf_fifodata) + /* Conections between tx_data_packet_fifo and + its reader + strobe generator */ + wire [31:0] chan_fifodata [CHAN_WIDTH:0] ; + wire chan_pkt_waiting [CHAN_WIDTH:0] ; + wire chan_rdreq [CHAN_WIDTH:0] ; + wire chan_skip [CHAN_WIDTH:0] ; + wire [CHAN_WIDTH:0] chan_have_space ; + wire chan_txstrobe [CHAN_WIDTH-1:0] ; + + wire [14:0] debug; + + /* Outputs to transmit chains */ + wire [15:0] tx_i [CHAN_WIDTH-1:0] ; + wire [15:0] tx_q [CHAN_WIDTH-1:0] ; + + /* TODO: Figure out how to write this genericly */ + assign have_space = chan_have_space[0] & chan_have_space[1]; + assign tx_empty = chan_txempty[0] & chan_txempty[1] ; + assign tx_underrun = chan_underrun[0] | chan_underrun[1] ; + assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; + assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; + assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; + assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ; + + /* Debug statement */ + assign txstrobe_rate[0] = STROBE_RATE_0 ; + assign txstrobe_rate[1] = STROBE_RATE_1 ; + assign tx_q_2 = 16'b0 ; + assign tx_i_2 = 16'b0 ; + assign tx_q_3 = 16'b0 ; + assign tx_i_3 = 16'b0 ; + assign tx_i_3 = 16'b0 ; + + assign debugbus = {debug, txclk}; + + wire [31:0] usbdata_final; + wire WR_final; + + tx_packer tx_usb_packer + ( + .bus_reset (bus_reset), + .usbclk (usbclk), + .WR_fx2 (WR), + .usbdata (usbdata), + .reset (reset), + .txclk (txclk), + .usbdata_final (usbdata_final), + .WR_final (WR_final) + ); + + channel_demux channel_demuxer + ( + .usbdata_final (usbdata_final), + .WR_final (WR_final), + .reset (reset), + .txclk (txclk), + .WR_channel (chan_WR), + .WR_done_channel (chan_done), + .ram_data (tx_data_bus) ); + + generate for (i = 0 ; i < NUM_CHAN; i = i + 1) + begin : generate_channel_readers + channel_ram tx_data_packet_fifo + ( .reset (reset), + .txclk (txclk), + .datain (tx_data_bus), + .WR (chan_WR[i]), + .WR_done (chan_done[i]), + .have_space (chan_have_space[i]), + .dataout (chan_fifodata[i]), + .packet_waiting (chan_pkt_waiting[i]), + .RD (chan_rdreq[i]), + .RD_done (chan_skip[i]) + ); + chan_fifo_reader tx_chan_reader + ( .reset (reset), + .tx_clock (txclk), + .tx_strobe (txstrobe), + .adc_time (adc_time), + .samples_format (4'b0), + .tx_q (tx_q[i]), + .tx_i (tx_i[i]), + .underrun (chan_underrun[i]), + .skip (chan_skip[i]), + .rdreq (chan_rdreq[i]), + .fifodata (chan_fifodata[i]), + .pkt_waiting (chan_pkt_waiting[i]), + .tx_empty (chan_txempty[i]), + .rssi (rssi[i]), + .threshhold (threshhold) + ); + + end + endgenerate - //Channel 0 block - wire [15:0] tdpf_fifodata_0; - wire tdpf_pkt_waiting_0; - wire tdpf_rdreq_0; - wire tdpf_skip_0; - wire tdpf_have_space_0; - wire txstrobe_chan_0; - data_packet_fifo tx_data_packet_fifo_0 - ( .reset(reset), - .clock(txclk), - .ram_data_in(tx_data_bus), - .write_enable(WR_chan_0), - .ram_data_out(tdpf_fifodata_0), - .pkt_waiting(tdpf_pkt_waiting_0), - .read_enable(tdpf_rdreq_0), - .pkt_complete(chan_0_done), - .skip_packet(tdpf_skip_0), - .have_space(tdpf_have_space_0) - ); - - strobe_gen strobe_gen_0 - ( .clock(txclk), - .reset(reset), - .enable(1'b1), - .rate(txstrobe_rate_0), - .strobe_in(txstrobe), - .strobe(txstrobe_chan_0) - ); - - chan_fifo_reader tx_chan_0_reader ( - .reset(reset), - .tx_clock(txclk), - .tx_strobe(txstrobe), - //.tx_strobe(txstrobe_chan_0), - .adc_clock(time_counter), - .samples_format(4'b0), - .tx_q(tx_q_0), - .tx_i(tx_i_0), - .overrun(OR0), - .underrun(UR0), - .skip(tdpf_skip_0), - .rdreq(tdpf_rdreq_0), - .fifodata(tdpf_fifodata_0), - .pkt_waiting(tdpf_pkt_waiting_0) - ); - - - //Channel 1 block - wire [15:0] tdpf_fifodata_1; - wire tdpf_pkt_waiting_1; - wire tdpf_rdreq_1; - wire tdpf_skip_1; - wire tdpf_have_space_1; - wire txstrobe_chan_1; - - data_packet_fifo tx_data_packet_fifo_1 - ( .reset(reset), - .clock(txclk), - .ram_data_in(tx_data_bus), - .write_enable(WR_chan_1), - .ram_data_out(tdpf_fifodata_1), - .pkt_waiting(tdpf_pkt_waiting_1), - .read_enable(tdpf_rdreq_1), - .pkt_complete(chan_1_done), - .skip_packet(tdpf_skip_1), - .have_space(tdpf_have_space_1) - ); - - strobe_gen strobe_gen_1 - ( .clock(txclk), - .reset(reset), - .enable(1'b1), - .rate(txstrobe_rate_1), - .strobe_in(txstrobe), - .strobe(txstrobe_chan_1) - ); - - chan_fifo_reader tx_chan_1_reader ( - .reset(reset), - .tx_clock(txclk), - .tx_strobe(txstrobe), - //.tx_strobe(txstrobe_chan_1), - .adc_clock(time_counter), - .samples_format(4'b0), - .tx_q(tx_q_1), - .tx_i(tx_i_1), - .overrun(OR1), - .underrun(UR1), - .skip(tdpf_skip_1), - .rdreq(tdpf_rdreq_1), - .fifodata(tdpf_fifodata_1), - .pkt_waiting(tdpf_pkt_waiting_1) - ); + channel_ram tx_cmd_packet_fifo + ( .reset (reset), + .txclk (txclk), + .datain (tx_data_bus), + .WR (chan_WR[NUM_CHAN]), + .WR_done (chan_done[NUM_CHAN]), + .have_space (chan_have_space[NUM_CHAN]), + .dataout (chan_fifodata[NUM_CHAN]), + .packet_waiting (chan_pkt_waiting[NUM_CHAN]), + .RD (chan_rdreq[NUM_CHAN]), + .RD_done (chan_skip[NUM_CHAN]) + ); + + + cmd_reader tx_cmd_reader + ( .reset (reset), + .txclk (txclk), + .adc_time (adc_time), + .skip (chan_skip[NUM_CHAN]), + .rdreq (chan_rdreq[NUM_CHAN]), + .fifodata (chan_fifodata[NUM_CHAN]), + .pkt_waiting (chan_pkt_waiting[NUM_CHAN]), + .rx_databus (rx_databus), + .rx_WR (rx_WR), + .rx_WR_done (rx_WR_done), + .rx_WR_enabled (rx_WR_enabled), + .reg_data_in (reg_data_in), + .reg_data_out (reg_data_out), + .reg_addr (reg_addr), + .reg_io_enable (reg_io_enable), + .debug (debug) + ); + + endmodule // tx_buffer diff --git a/inband_lib/tx_packer.v b/inband_lib/tx_packer.v new file mode 100644 index 000000000..2f19b21f3 --- /dev/null +++ b/inband_lib/tx_packer.v @@ -0,0 +1,119 @@ +module tx_packer + ( //FX2 Side + input bus_reset, + input usbclk, + input WR_fx2, + input [15:0]usbdata, + + // TX Side + input reset, + input txclk, + output reg [31:0] usbdata_final, + output reg WR_final); + + reg [8:0] write_count; + + /* Fix FX2 bug */ + always @(posedge usbclk) + begin + if(bus_reset) // Use bus reset because this is on usbclk + write_count <= #1 0; + else if(WR_fx2 & ~write_count[8]) + write_count <= #1 write_count + 9'd1; + else + write_count <= #1 WR_fx2 ? write_count : 9'b0; + end + + reg WR_fx2_fixed; + reg [15:0]usbdata_fixed; + + always @(posedge usbclk) + begin + WR_fx2_fixed <= WR_fx2 & ~write_count[8]; + usbdata_fixed <= usbdata; + end + + /* Used to convert 16 bits bus_data to the 32 bits wide fifo */ + reg word_complete ; + reg [15:0] usbdata_delayed ; + reg writing ; + wire [31:0] usbdata_packed ; + wire WR_packed ; + + always @(posedge usbclk) + begin + if (bus_reset) + begin + word_complete <= 0 ; + writing <= 0 ; + end + else if (WR_fx2_fixed) + begin + writing <= 1 ; + if (word_complete) + word_complete <= 0 ; + else + begin + usbdata_delayed <= usbdata_fixed ; + word_complete <= 1 ; + end + end + else + writing <= 0 ; + end + + assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ; + assign WR_packed = word_complete & writing ; + + /* Make sure data are sync with usbclk */ + reg [31:0]usbdata_usbclk; + reg WR_usbclk; + + always @(posedge usbclk) + begin + if (WR_packed) + usbdata_usbclk <= usbdata_packed; + WR_usbclk <= WR_packed; + end + + /* Cross clock boundaries */ + reg [31:0] usbdata_tx ; + reg WR_tx; + reg WR_1; + reg WR_2; + + always @(posedge txclk) usbdata_tx <= usbdata_usbclk; + + always @(posedge txclk) + if (reset) + WR_1 <= 0; + else + WR_1 <= WR_usbclk; + + always @(posedge txclk) + if (reset) + WR_2 <= 0; + else + WR_2 <= WR_1; + + always @(posedge txclk) + begin + if (reset) + WR_tx <= 0; + else + WR_tx <= WR_1 & ~WR_2; + end + + always @(posedge txclk) + begin + if (reset) + WR_final <= 0; + else + begin + WR_final <= WR_tx; + if (WR_tx) + usbdata_final <= usbdata_tx; + end + end + +endmodule diff --git a/inband_lib/usb_fifo_reader.v b/inband_lib/usb_fifo_reader.v index 170c70fd4..d002d90ff 100755 --- a/inband_lib/usb_fifo_reader.v +++ b/inband_lib/usb_fifo_reader.v @@ -1,134 +1,24 @@ -module usb_fifo_reader (tx_clock, fifodata, pkt_waiting, reset, - rdreq, skip, done_chan, WR_chan, tx_data_bus); +module usb_fifo_reader ( + input usbclk, + input bus_reset, + input RD, + output rdreq, + ); - /* Module parameters */ - parameter NUM_CHAN = 2 ; - parameter WIDTH = 32 ; + // FX2 Bug Fix + reg [8:0] read_count; + always @(negedge usbclk) + if(bus_reset) + read_count <= #1 9'd0; + else if(RD & ~read_count[8]) + read_count <= #1 read_count + 9'd1; + else + read_count <= #1 RD ? read_count : 9'b0; + + assign rdreq = RD & ~read_count[8]; - input wire tx_clock ; - input wire reset ; - input wire [WIDTH-1:0] fifodata ; - input wire pkt_waiting ; - output reg rdreq ; - output reg skip ; - output reg [NUM_CHAN:0] done_chan ; - output reg [NUM_CHAN:0] WR_chan ; - output reg [WIDTH-1:0] tx_data_bus ; - - - - /* States definition */ - `define IDLE 3'd0 - `define WAIT 3'd1 - `define READ_HEADER 3'd2 - `define FORWARD_DATA 3'd3 - `define SKIP_REST 3'd4 - - /* Channel Ids */ - `define TXCHAN0 5'h0 - `define TXCHAN1 5'h1 - `define TXCMD 5'h1F - - /* Local registers */ - reg [2:0] reader_state ; - reg [2:0] reader_next_state ; - reg [4:0] channel ; - reg [8:0] pkt_length ; - reg [8:0] read_length ; - /* State Machine */ - always @(posedge tx_clock) - begin - if (reset) - begin - reader_state <= `IDLE ; - reader_next_state <= `IDLE ; - rdreq <= 0 ; - skip <= 0 ; - WR_chan <= {NUM_CHAN+1{1'b0}} ; - done_chan <= {NUM_CHAN+1{1'b0}} ; - end - else - begin - reader_state = reader_next_state ; - - case(reader_state) - `IDLE: - begin - reader_next_state <= pkt_waiting ? `WAIT : `IDLE ; - rdreq <= pkt_waiting ; - end - - /* Wait for the fifo's data to show up */ - `WAIT: - begin - reader_next_state <= `READ_HEADER ; - end - - `READ_HEADER: - begin - reader_next_state <= `FORWARD_DATA ; - - /* Read header fields */ - channel <= (fifodata & 32'h1F0000) ; - pkt_length <= (fifodata & 16'h1FF) + 4 ; - read_length <= 9'd0 ; - - /* Forward data */ - case (channel) - `TXCHAN0: WR_chan[0] <= 1 ; - `TXCHAN1: WR_chan[1] <= 1 ; - `TXCMD: WR_chan[2] <= 1 ; - default: WR_chan <= 1 ; - endcase - tx_data_bus <= fifodata ; - end - - `FORWARD_DATA: - begin - read_length <= read_length + 4 ; - - // If end of payload... - if (read_length == pkt_length) - begin - reader_next_state <= `SKIP_REST ; - /* If the packet is 512 bytes, don't skip */ - skip <= pkt_length < 506 ; - - /* Data pushing done */ - WR_chan <= {NUM_CHAN+1{1'b0}} ; - - /* Notify next block */ - case (channel) - `TXCHAN0: done_chan[0] <= 1 ; - `TXCHAN1: done_chan[1] <= 1 ; - `TXCMD: done_chan[2] <= 1 ; - default: done_chan[0] <= 1 ; - endcase - end - else if (read_length == pkt_length - 4) - rdreq <= 0 ; - - /* Forward data */ - tx_data_bus <= fifodata ; - end - - `SKIP_REST: - begin - reader_next_state <= pkt_waiting ? `READ_HEADER : `IDLE ; - done_chan <= {NUM_CHAN+1{1'b0}} ; - rdreq <= pkt_waiting ; - skip <= 0 ; - end - - default: - begin - reader_state <= `IDLE; - reader_next_state <= `IDLE; - end - endcase - end - end + endmodule diff --git a/inband_lib/usb_fifo_writer.v b/inband_lib/usb_fifo_writer.v new file mode 100755 index 000000000..abe1dd567 --- /dev/null +++ b/inband_lib/usb_fifo_writer.v @@ -0,0 +1,183 @@ + +module usb_fifo_writer + #(parameter BUS_WIDTH = 16, + parameter NUM_CHAN = 2, + parameter FIFO_WIDTH = 32) + ( //FX2 Side + input bus_reset, + input usbclk, + input WR_fx2, + input [15:0]usbdata, + + // TX Side + input reset, + input txclk, + output reg [NUM_CHAN:0] WR_channel, + output reg [FIFO_WIDTH-1:0] ram_data, + output reg [NUM_CHAN:0] WR_done_channel ); + + + reg [8:0] write_count; + + /* Fix FX2 bug */ + always @(posedge usbclk) + if(bus_reset) // Use bus reset because this is on usbclk + write_count <= #1 0; + else if(WR_fx2 & ~write_count[8]) + write_count <= #1 write_count + 9'd1; + else + write_count <= #1 WR_fx2 ? write_count : 9'b0; + + reg WR_fx2_fixed; + reg [15:0]usbdata_fixed; + + always @(posedge usbclk) + begin + WR_fx2_fixed <= WR_fx2 & ~write_count[8]; + usbdata_fixed <= usbdata; + end + + /* Used to convert 16 bits bus_data to the 32 bits wide fifo */ + reg word_complete ; + reg [BUS_WIDTH-1:0] usbdata_delayed ; + reg writing ; + wire [FIFO_WIDTH-1:0] usbdata_packed ; + wire WR_packed ; + + always @(posedge usbclk) + begin + if (bus_reset) + begin + word_complete <= 0 ; + writing <= 0 ; + end + else if (WR_fx2_fixed) + begin + writing <= 1 ; + if (word_complete) + word_complete <= 0 ; + else + begin + usbdata_delayed <= usbdata_fixed ; + word_complete <= 1 ; + end + end + else + writing <= 0 ; + end + + assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ; + assign WR_packed = word_complete & writing ; + + /* Make sure data are sync with usbclk */ + reg [31:0]usbdata_usbclk; + reg WR_usbclk; + + always @(posedge usbclk) + begin + if (WR_packed) + usbdata_usbclk <= usbdata_packed; + WR_usbclk <= WR_packed; + end + + /* Cross clock boundaries */ + reg [FIFO_WIDTH-1:0] usbdata_tx ; + reg WR_tx; + reg WR_1; + reg WR_2; + reg [31:0] usbdata_final; + reg WR_final; + + always @(posedge txclk) usbdata_tx <= usbdata_usbclk; + + always @(posedge txclk) + if (reset) + WR_1 <= 0; + else + WR_1 <= WR_usbclk; + + always @(posedge txclk) + if (reset) + WR_2 <= 0; + else + WR_2 <= WR_1; + + always @(posedge txclk) + begin + if (reset) + WR_tx <= 0; + else + WR_tx <= WR_1 & ~WR_2; + end + + always @(posedge txclk) + begin + if (reset) + WR_final <= 0; + else + begin + WR_final <= WR_tx; + if (WR_tx) + usbdata_final <= usbdata_tx; + end + end + + /* Parse header and forward to ram */ + reg [3:0]reader_state; + reg [4:0]channel ; + reg [9:0]read_length ; + + parameter IDLE = 4'd0; + parameter HEADER = 4'd1; + parameter WAIT = 4'd2; + parameter FORWARD = 4'd3; + + `define CHANNEL 20:16 + `define PKT_SIZE 512 + + always @(posedge txclk) + begin + if (reset) + begin + reader_state <= 0; + WR_channel <= 0; + WR_done_channel <= 0; + end + else + case (reader_state) + IDLE: begin + if (WR_final) + reader_state <= HEADER; + end + + // Store channel and forware header + HEADER: begin + channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL]) ; + WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL])] <= 1; + //channel <= usbdata_final[`CHANNEL] ; + //WR_channel[usbdata_final[`CHANNEL]] <= 1; + ram_data <= usbdata_final; + read_length <= 10'd4 ; + + reader_state <= WAIT; + end + + WAIT: begin + WR_channel[channel] <= 0; + + if (read_length == `PKT_SIZE) + reader_state <= IDLE; + else if (WR_final) + reader_state <= FORWARD; + end + + FORWARD: begin + WR_channel[channel] <= 1; + ram_data <= usbdata_final; + read_length <= read_length + 10'd4; + + reader_state <= WAIT; + end + endcase + end +endmodule \ No newline at end of file diff --git a/inband_lib/usb_packet_fifo2.v b/inband_lib/usb_packet_fifo2.v deleted file mode 100755 index d815e4e37..000000000 --- a/inband_lib/usb_packet_fifo2.v +++ /dev/null @@ -1,119 +0,0 @@ -`default_nettype none - -module usb_packet_fifo2(reset, usb_clock, fpga_clock, write_enable, write_data, - read_enable, skip_packet, read_data, have_space, pkt_waiting, tx_empty) ; - - /* Module parameters */ - parameter LOG2_N = 2 ; - parameter BUS_WIDTH = 16 ; - parameter FIFO_WIDTH = 32 ; - - input wire reset; - input wire usb_clock ; - input wire fpga_clock ; - input wire write_enable ; - input wire [BUS_WIDTH-1:0] write_data ; - input wire read_enable ; - input wire skip_packet ; - output wire [FIFO_WIDTH-1:0] read_data ; - output wire have_space ; - output wire pkt_waiting ; - output wire tx_empty; - - - /* Variable for generate statement */ - genvar i ; - - /* Local wires for FIFO connections */ - wire [2**LOG2_N-1:0] fifo_resets ; - reg [2**LOG2_N-1:0] fifo_we ; - wire [2**LOG2_N-1:0] fifo_re ; - reg [FIFO_WIDTH-1:0] fifo_wdata[2**LOG2_N-1:0] ; - wire [FIFO_WIDTH-1:0] fifo_rdata[2**LOG2_N-1:0] ; - wire [2**LOG2_N-1:0] fifo_rempty ; - wire [2**LOG2_N-1:0] fifo_rfull ; - wire [2**LOG2_N-1:0] fifo_wempty ; - wire [2**LOG2_N-1:0] fifo_wfull ; - - /* FIFO Select for read and write ports */ - reg [LOG2_N-1:0] fifo_rselect ; - reg [LOG2_N-1:0] fifo_wselect ; - - /* Used to convert 16 bits usbdata to the 32 bits wide fifo */ - reg word_complete ; - reg [BUS_WIDTH-1:0] write_data_delayed ; - - /* Assign have_space to empty flag of currently selected write FIFO */ - assign have_space = fifo_wempty[fifo_wselect] ; - - /* Assign pkt_waiting to full flag of currently selected read FIFO */ - assign pkt_waiting = fifo_rfull[fifo_rselect] ; - - /* Assign the read_data to the output of the currently selected FIFO */ - assign read_data = fifo_rdata[fifo_rselect] ; - - /* Figure out if we're all empty */ - assign tx_empty = !(~fifo_rempty) ; - - /* Increment fifo_rselect here */ - always @(posedge fpga_clock) - begin - if (reset) - fifo_rselect <= {2**LOG2_N{1'b0}} ; - - if (fifo_rempty[fifo_rselect]) - fifo_rselect <= fifo_rselect + 1 ; - - if (skip_packet) - fifo_rselect <= fifo_rselect + 1 ; - end - - /* Increment fifo_wselect and pack data into 32 bits block */ - always @(posedge usb_clock, reset) - begin - if (reset) - begin - fifo_wselect <= {2**LOG2_N{1'b0}} ; - word_complete <= 0; - end - - if (fifo_wfull[fifo_wselect]) - fifo_wselect <= fifo_wselect + 1 ; - - if (write_enable) - begin - word_complete <= ~word_complete ; - - if (word_complete) - fifo_wdata[fifo_wselect] <= {write_data_delayed, write_data} ; - else - write_data_delayed <= write_data ; - - /* Avoid to continue to write in the previous fifo when we have - just swichted to the next one */ - fifo_we[fifo_wselect-1] <= 0 ; - - fifo_we[fifo_wselect] <= write_enable & word_complete ; - end - end - - /* Generate all the single packet FIFOs */ - generate - for( i = 0 ; i < 2**LOG2_N ; i = i + 1 ) - begin : generate_single_packet_fifos - assign fifo_re[i] = (fifo_rselect == i) ? read_enable : 1'b0 ; - assign fifo_resets[i] = (fifo_rselect == i) ? skip_packet : 1'b0 ; - fifo_512 single_packet_fifo(.wrclk ( usb_clock ), - .rdclk ( fpga_clock ), - .aclr ( fifo_resets[i] ), - .wrreq ( fifo_we[i] ), - .data ( fifo_wdata[i] ), - .rdreq ( fifo_re[i] ), - .q ( fifo_rdata[i] ), - .rdfull ( fifo_rfull[i] ), - .rdempty( fifo_rempty[i] ), - .wrfull ( fifo_wfull[i] ), - .wrempty( fifo_wempty[i] ) ) ; - end - endgenerate -endmodule \ No newline at end of file diff --git a/megacells/fifo_2k_1clk.v b/megacells/fifo_2k_1clk.v new file mode 100755 index 000000000..095615bb8 --- /dev/null +++ b/megacells/fifo_2k_1clk.v @@ -0,0 +1,167 @@ +// megafunction wizard: %LPM_FIFO+% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_2k_1clk.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_2k_1clk ( + aclr, + clock, + data, + rdreq, + wrreq, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [15:0] q; + output [9:0] usedw; + + wire [9:0] sub_wire0; + wire sub_wire1; + wire [15:0] sub_wire2; + wire sub_wire3; + wire [9:0] usedw = sub_wire0[9:0]; + wire empty = sub_wire1; + wire [15:0] q = sub_wire2[15:0]; + wire full = sub_wire3; + + scfifo scfifo_component ( + .rdreq (rdreq), + .aclr (aclr), + .clock (clock), + .wrreq (wrreq), + .data (data), + .usedw (sub_wire0), + .empty (sub_wire1), + .q (sub_wire2), + .full (sub_wire3) + // synopsys translate_off + , + .almost_empty (), + .sclr (), + .almost_full () + // synopsys translate_on + ); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.intended_device_family = "Cyclone", + scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", + scfifo_component.lpm_numwords = 1024, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 16, + scfifo_component.lpm_widthu = 10, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_wave*.jpg FALSE diff --git a/megacells/fifo_2kx16.bsf b/megacells/fifo_2kx16.bsf new file mode 100755 index 000000000..1067991fb --- /dev/null +++ b/megacells/fifo_2kx16.bsf @@ -0,0 +1,99 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 144) + (text "fifo_2kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 128 25 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 114 37 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 56) + (output) + (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 144 56)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 1)) + ) + (port + (pt 160 88) + (output) + (text "usedw[10..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) + (text "usedw[10..0]" (rect 77 82 136 95)(font "Arial" (font_size 8))) + (line (pt 160 88)(pt 144 88)(line_width 3)) + ) + (drawing + (text "16 bits x 2048 words" (rect 58 116 144 128)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 128)(line_width 1)) + (line (pt 144 128)(pt 16 128)(line_width 1)) + (line (pt 16 128)(pt 16 16)(line_width 1)) + (line (pt 16 108)(pt 144 108)(line_width 1)) + (line (pt 16 90)(pt 22 96)(line_width 1)) + (line (pt 22 96)(pt 16 102)(line_width 1)) + ) +) diff --git a/megacells/fifo_2kx16.cmp b/megacells/fifo_2kx16.cmp new file mode 100755 index 000000000..96c34d8d7 --- /dev/null +++ b/megacells/fifo_2kx16.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_2kx16 + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) + ); +end component; diff --git a/megacells/fifo_2kx16.inc b/megacells/fifo_2kx16.inc new file mode 100755 index 000000000..3d72c6601 --- /dev/null +++ b/megacells/fifo_2kx16.inc @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_2kx16 +( + aclr, + clock, + data[15..0], + rdreq, + wrreq +) + +RETURNS ( + empty, + full, + q[15..0], + usedw[10..0] +); diff --git a/megacells/fifo_2kx16.v b/megacells/fifo_2kx16.v new file mode 100755 index 000000000..eb229769d --- /dev/null +++ b/megacells/fifo_2kx16.v @@ -0,0 +1,167 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_2kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_2kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [15:0] q; + output [10:0] usedw; + + wire [10:0] sub_wire0; + wire sub_wire1; + wire [15:0] sub_wire2; + wire sub_wire3; + wire [10:0] usedw = sub_wire0[10:0]; + wire empty = sub_wire1; + wire [15:0] q = sub_wire2[15:0]; + wire full = sub_wire3; + + scfifo scfifo_component ( + .rdreq (rdreq), + .aclr (aclr), + .clock (clock), + .wrreq (wrreq), + .data (data), + .usedw (sub_wire0), + .empty (sub_wire1), + .q (sub_wire2), + .full (sub_wire3) + // synopsys translate_off + , + .almost_empty (), + .sclr (), + .almost_full () + // synopsys translate_on + ); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.intended_device_family = "Cyclone", + scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", + scfifo_component.lpm_numwords = 2048, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 16, + scfifo_component.lpm_widthu = 11, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "2048" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL usedw[10..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_wave*.jpg FALSE diff --git a/megacells/fifo_2kx16_bb.v b/megacells/fifo_2kx16_bb.v new file mode 100755 index 000000000..507bac073 --- /dev/null +++ b/megacells/fifo_2kx16_bb.v @@ -0,0 +1,122 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_2kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_2kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [15:0] q; + output [10:0] usedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "2048" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL usedw[10..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_wave*.jpg FALSE diff --git a/megacells/fifo_2kx16_inst.v b/megacells/fifo_2kx16_inst.v new file mode 100755 index 000000000..6185c6fe6 --- /dev/null +++ b/megacells/fifo_2kx16_inst.v @@ -0,0 +1,11 @@ +fifo_2kx16 fifo_2kx16_inst ( + .aclr ( aclr_sig ), + .clock ( clock_sig ), + .data ( data_sig ), + .rdreq ( rdreq_sig ), + .wrreq ( wrreq_sig ), + .empty ( empty_sig ), + .full ( full_sig ), + .q ( q_sig ), + .usedw ( usedw_sig ) + ); diff --git a/megacells/fifo_4kx16.bsf b/megacells/fifo_4kx16.bsf new file mode 100755 index 000000000..4d988c5e9 --- /dev/null +++ b/megacells/fifo_4kx16.bsf @@ -0,0 +1,99 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 144) + (text "fifo_4kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 128 25 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 114 37 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 56) + (output) + (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 144 56)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 1)) + ) + (port + (pt 160 88) + (output) + (text "usedw[11..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) + (text "usedw[11..0]" (rect 77 82 136 95)(font "Arial" (font_size 8))) + (line (pt 160 88)(pt 144 88)(line_width 3)) + ) + (drawing + (text "16 bits x 4096 words" (rect 58 116 144 128)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 128)(line_width 1)) + (line (pt 144 128)(pt 16 128)(line_width 1)) + (line (pt 16 128)(pt 16 16)(line_width 1)) + (line (pt 16 108)(pt 144 108)(line_width 1)) + (line (pt 16 90)(pt 22 96)(line_width 1)) + (line (pt 22 96)(pt 16 102)(line_width 1)) + ) +) diff --git a/megacells/fifo_4kx16.cmp b/megacells/fifo_4kx16.cmp new file mode 100755 index 000000000..7bc6941d7 --- /dev/null +++ b/megacells/fifo_4kx16.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_4kx16 + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + usedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) + ); +end component; diff --git a/megacells/fifo_4kx16.inc b/megacells/fifo_4kx16.inc new file mode 100755 index 000000000..db5d4f29e --- /dev/null +++ b/megacells/fifo_4kx16.inc @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_4kx16 +( + aclr, + clock, + data[15..0], + rdreq, + wrreq +) + +RETURNS ( + empty, + full, + q[15..0], + usedw[11..0] +); diff --git a/megacells/fifo_4kx16.v b/megacells/fifo_4kx16.v new file mode 100755 index 000000000..c5ecfbae7 --- /dev/null +++ b/megacells/fifo_4kx16.v @@ -0,0 +1,167 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_4kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_4kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [15:0] q; + output [11:0] usedw; + + wire [11:0] sub_wire0; + wire sub_wire1; + wire [15:0] sub_wire2; + wire sub_wire3; + wire [11:0] usedw = sub_wire0[11:0]; + wire empty = sub_wire1; + wire [15:0] q = sub_wire2[15:0]; + wire full = sub_wire3; + + scfifo scfifo_component ( + .rdreq (rdreq), + .aclr (aclr), + .clock (clock), + .wrreq (wrreq), + .data (data), + .usedw (sub_wire0), + .empty (sub_wire1), + .q (sub_wire2), + .full (sub_wire3) + // synopsys translate_off + , + .almost_empty (), + .sclr (), + .almost_full () + // synopsys translate_on + ); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.intended_device_family = "Cyclone", + scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", + scfifo_component.lpm_numwords = 4096, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 16, + scfifo_component.lpm_widthu = 12, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 12 0 OUTPUT NODEFVAL usedw[11..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 12 0 @usedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_bb.v b/megacells/fifo_4kx16_bb.v new file mode 100755 index 000000000..d41e9f090 --- /dev/null +++ b/megacells/fifo_4kx16_bb.v @@ -0,0 +1,122 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_4kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_4kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [15:0] q; + output [11:0] usedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 12 0 OUTPUT NODEFVAL usedw[11..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 12 0 @usedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_inst.v b/megacells/fifo_4kx16_inst.v new file mode 100755 index 000000000..eb260acaa --- /dev/null +++ b/megacells/fifo_4kx16_inst.v @@ -0,0 +1,11 @@ +fifo_4kx16 fifo_4kx16_inst ( + .aclr ( aclr_sig ), + .clock ( clock_sig ), + .data ( data_sig ), + .rdreq ( rdreq_sig ), + .wrreq ( wrreq_sig ), + .empty ( empty_sig ), + .full ( full_sig ), + .q ( q_sig ), + .usedw ( usedw_sig ) + ); diff --git a/megacells/fifo_512.bsf b/megacells/fifo_512.bsf deleted file mode 100755 index a955b5655..000000000 --- a/megacells/fifo_512.bsf +++ /dev/null @@ -1,116 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2006 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 184) - (text "fifo_512" (rect 58 1 109 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 168 25 180)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 104) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 16 104)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) - (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 0 160) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8))) - (line (pt 0 160)(pt 16 160)(line_width 1)) - ) - (port - (pt 160 40) - (output) - (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8))) - (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8))) - (line (pt 160 40)(pt 144 40)(line_width 1)) - ) - (port - (pt 160 56) - (output) - (text "wrempty" (rect 0 0 50 14)(font "Arial" (font_size 8))) - (text "wrempty" (rect 98 50 137 63)(font "Arial" (font_size 8))) - (line (pt 160 56)(pt 144 56)(line_width 1)) - ) - (port - (pt 160 96) - (output) - (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) - (line (pt 160 96)(pt 144 96)(line_width 3)) - ) - (port - (pt 160 120) - (output) - (text "rdfull" (rect 0 0 28 14)(font "Arial" (font_size 8))) - (text "rdfull" (rect 117 114 141 127)(font "Arial" (font_size 8))) - (line (pt 160 120)(pt 144 120)(line_width 1)) - ) - (port - (pt 160 136) - (output) - (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) - (text "rdempty" (rect 102 130 140 143)(font "Arial" (font_size 8))) - (line (pt 160 136)(pt 144 136)(line_width 1)) - ) - (drawing - (text "32 bits x 128 words" (rect 63 156 144 168)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 168)(line_width 1)) - (line (pt 144 168)(pt 16 168)(line_width 1)) - (line (pt 16 168)(pt 16 16)(line_width 1)) - (line (pt 16 84)(pt 144 84)(line_width 1)) - (line (pt 16 148)(pt 144 148)(line_width 1)) - (line (pt 16 66)(pt 22 72)(line_width 1)) - (line (pt 22 72)(pt 16 78)(line_width 1)) - (line (pt 16 114)(pt 22 120)(line_width 1)) - (line (pt 22 120)(pt 16 126)(line_width 1)) - ) -) diff --git a/megacells/fifo_512.cmp b/megacells/fifo_512.cmp deleted file mode 100755 index 86fc07846..000000000 --- a/megacells/fifo_512.cmp +++ /dev/null @@ -1,31 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component fifo_512 - PORT - ( - aclr : IN STD_LOGIC := '0'; - data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); - rdempty : OUT STD_LOGIC ; - rdfull : OUT STD_LOGIC ; - wrempty : OUT STD_LOGIC ; - wrfull : OUT STD_LOGIC - ); -end component; diff --git a/megacells/fifo_512.inc b/megacells/fifo_512.inc deleted file mode 100755 index 9ae1e3af4..000000000 --- a/megacells/fifo_512.inc +++ /dev/null @@ -1,32 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION fifo_512 -( - aclr, - data[31..0], - rdclk, - rdreq, - wrclk, - wrreq -) - -RETURNS ( - q[31..0], - rdempty, - rdfull, - wrempty, - wrfull -); diff --git a/megacells/fifo_512.v b/megacells/fifo_512.v deleted file mode 100755 index b034b4ddc..000000000 --- a/megacells/fifo_512.v +++ /dev/null @@ -1,180 +0,0 @@ -// megafunction wizard: %LPM_FIFO+% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_512.v -// Megafunction Name(s): -// dcfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_512 ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - rdfull, - wrempty, - wrfull); - - input aclr; - input [31:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [31:0] q; - output rdempty; - output rdfull; - output wrempty; - output wrfull; - - wire sub_wire0; - wire sub_wire1; - wire sub_wire2; - wire sub_wire3; - wire [31:0] sub_wire4; - wire rdfull = sub_wire0; - wire rdempty = sub_wire1; - wire wrfull = sub_wire2; - wire wrempty = sub_wire3; - wire [31:0] q = sub_wire4[31:0]; - - dcfifo dcfifo_component ( - .wrclk (wrclk), - .rdreq (rdreq), - .aclr (aclr), - .rdclk (rdclk), - .wrreq (wrreq), - .data (data), - .rdfull (sub_wire0), - .rdempty (sub_wire1), - .wrfull (sub_wire2), - .wrempty (sub_wire3), - .q (sub_wire4) - // synopsys translate_off - , - .rdusedw (), - .wrusedw () - // synopsys translate_on - ); - defparam - dcfifo_component.add_ram_output_register = "OFF", - dcfifo_component.clocks_are_synchronized = "FALSE", - dcfifo_component.intended_device_family = "Cyclone", - dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", - dcfifo_component.lpm_numwords = 128, - dcfifo_component.lpm_showahead = "OFF", - dcfifo_component.lpm_type = "dcfifo", - dcfifo_component.lpm_width = 32, - dcfifo_component.lpm_widthu = 7, - dcfifo_component.overflow_checking = "ON", - dcfifo_component.underflow_checking = "ON", - dcfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: Depth NUMERIC "128" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "32" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "1" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] -// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 -// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_wave*.jpg FALSE diff --git a/megacells/fifo_512_bb.v b/megacells/fifo_512_bb.v deleted file mode 100755 index b11803159..000000000 --- a/megacells/fifo_512_bb.v +++ /dev/null @@ -1,131 +0,0 @@ -// megafunction wizard: %LPM_FIFO+%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_512.v -// Megafunction Name(s): -// dcfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_512 ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - rdfull, - wrempty, - wrfull); - - input aclr; - input [31:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [31:0] q; - output rdempty; - output rdfull; - output wrempty; - output wrfull; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: Depth NUMERIC "128" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "32" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "1" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] -// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 -// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_wave*.jpg FALSE diff --git a/toplevel/usrp_inband_usb/config.vh b/toplevel/usrp_inband_usb/config.vh index 2d1929439..3291dc10b 100644 --- a/toplevel/usrp_inband_usb/config.vh +++ b/toplevel/usrp_inband_usb/config.vh @@ -1,4 +1,4 @@ -// -*- verilog -*- + // -*- verilog -*- // // USRP - Universal Software Radio Peripheral // diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf index 8296a453e..6b4764078 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -372,11 +372,16 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" +set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k_1clk.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1k.v set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_fifo.v set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v @@ -412,4 +417,6 @@ set_global_assignment -name VERILOG_FILE usrp_inband_usb.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v \ No newline at end of file diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.v b/toplevel/usrp_inband_usb/usrp_inband_usb.v index cc7490c5a..3bfdda56b 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.v +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.v @@ -19,7 +19,8 @@ // along with this program; if not, write to the Free Software // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // -`define IN_BAND +`define TX_IN_BAND +`define RX_IN_BAND `include "config.vh" `include "../../../firmware/include/fpga_regs_common.v" @@ -115,6 +116,12 @@ module usrp_inband_usb reg [15:0] debug_counter; reg [15:0] loopback_i_0,loopback_q_0; + + //Connection RX inband <-> TX inband + wire rx_WR; + wire [15:0] rx_databus; + wire rx_WR_done; + wire rx_WR_enabled; //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Transmit Side `ifdef TX_ON @@ -123,7 +130,17 @@ module usrp_inband_usb assign bb_tx_i1 = ch2tx; assign bb_tx_q1 = ch3tx; -`ifdef IN_BAND +wire [6:0] reg_addr; +wire [31:0] reg_data_out; +wire [31:0] reg_data_in; +wire [1:0] reg_io_enable; +wire [31:0] rssi_threshhold; +register_io register_control +(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in), + .dataout(reg_data_out),.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), + .rssi_3(rssi_3), .threshhold(rssi_threshhold)); + +`ifdef TX_IN_BAND tx_buffer_inband tx_buffer ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), @@ -135,7 +152,17 @@ module usrp_inband_usb .txclk(clk64),.txstrobe(strobe_interp), .clear_status(clear_status), .tx_empty(tx_empty), - .debugbus(tx_debugbus) ); + .rx_WR(rx_WR), + .rx_databus(rx_databus), + .rx_WR_done(rx_WR_done), + .rx_WR_enabled(rx_WR_enabled), + .reg_addr(reg_addr), + .reg_data_out(reg_data_out), + .reg_data_in(reg_data_in), + .reg_io_enable(reg_io_enable), + .debugbus(tx_debugbus), + .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), + .rssi_3(rssi_3), .threshhold(rssi_threshhold)); `else tx_buffer tx_buffer ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), @@ -147,8 +174,7 @@ module usrp_inband_usb .tx_i_3(),.tx_q_3(), .txclk(clk64),.txstrobe(strobe_interp), .clear_status(clear_status), - .tx_empty(tx_empty), - .debugbus(tx_debugbus) ); + .tx_empty(tx_empty)); `endif `ifdef TX_EN_0 @@ -226,7 +252,6 @@ module usrp_inband_usb wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; - adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), @@ -234,9 +259,9 @@ module usrp_inband_usb .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), - .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); - - rx_buffer rx_buffer + .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan)); + `ifdef RX_IN_BAND + rx_buffer_inband rx_buffer ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), .reset_regs(rx_dsp_reset), .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), @@ -248,7 +273,27 @@ module usrp_inband_usb .rxclk(clk64),.rxstrobe(hb_strobe), .clear_status(clear_status), .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus(rx_debugbus) ); + .rx_WR(rx_WR), + .rx_databus(rx_databus), + .rx_WR_done(rx_WR_done), + .rx_WR_enabled(rx_WR_enabled), + .debugbus(rx_debugbus), + .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3)); + `else + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), + .reset_regs(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(ch0rx),.ch_1(ch1rx), + .ch_2(ch2rx),.ch_3(ch3rx), + .ch_4(ch4rx),.ch_5(ch5rx), + .ch_6(ch6rx),.ch_7(ch7rx), + .rxclk(clk64),.rxstrobe(hb_strobe), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)/*, + .debugbus(rx_debugbus)*/); + `endif `ifdef RX_EN_0 rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 @@ -305,7 +350,6 @@ module usrp_inband_usb assign capabilities[3] = `RX_CAP_HB; assign capabilities[2:0] = `RX_CAP_NCHAN; - serial_io serial_io ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), @@ -326,7 +370,7 @@ module usrp_inband_usb .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), .tx_empty(tx_empty), //.debug_0(rx_a_a),.debug_1(ddc0_in_i), - .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_0(tx_debugbus),.debug_1(tx_debugbus), .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); -- cgit v1.2.3 From c459c56ac7993b28e87e94bae21d152b4ff7799b Mon Sep 17 00:00:00 2001 From: eb Date: Thu, 13 Sep 2007 23:21:41 +0000 Subject: Merged r6329:6428 of features/inband-usb + distcheck fixes into trunk. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6429 221aa14e-8319-0410-a670-987f0aec2ac5 --- inband_lib/chan_fifo_reader.v | 42 ++-- inband_lib/channel_ram.v | 4 +- inband_lib/packet_builder.v | 18 +- inband_lib/register_io.v | 4 +- inband_lib/rx_buffer_inband.v | 354 ++++++++++++++------------- inband_lib/tx_buffer_inband.v | 45 ++-- megacells/fifo_1kx16.bsf | 107 ++++++++ megacells/fifo_1kx16.cmp | 30 +++ megacells/fifo_1kx16.inc | 31 +++ megacells/fifo_1kx16.v | 175 +++++++++++++ megacells/fifo_1kx16_bb.v | 127 ++++++++++ megacells/fifo_1kx16_inst.v | 12 + megacells/fifo_2k_1clk.v | 167 ------------- megacells/fifo_2kx16.bsf | 99 -------- megacells/fifo_2kx16.cmp | 29 --- megacells/fifo_2kx16.inc | 30 --- megacells/fifo_2kx16.v | 167 ------------- megacells/fifo_2kx16_bb.v | 122 --------- megacells/fifo_2kx16_inst.v | 11 - megacells/fifo_4kx16.bsf | 99 -------- megacells/fifo_4kx16.cmp | 29 --- megacells/fifo_4kx16.inc | 30 --- megacells/fifo_4kx16.v | 167 ------------- megacells/fifo_4kx16_bb.v | 122 --------- megacells/fifo_4kx16_dc.bsf | 117 +++++++++ megacells/fifo_4kx16_dc.cmp | 31 +++ megacells/fifo_4kx16_dc.inc | 32 +++ megacells/fifo_4kx16_dc.v | 178 ++++++++++++++ megacells/fifo_4kx16_dc_bb.v | 130 ++++++++++ megacells/fifo_4kx16_dc_inst.v | 13 + megacells/fifo_4kx16_inst.v | 11 - toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 4 +- toplevel/usrp_inband_usb/usrp_inband_usb.v | 28 ++- 33 files changed, 1242 insertions(+), 1323 deletions(-) create mode 100755 megacells/fifo_1kx16.bsf create mode 100755 megacells/fifo_1kx16.cmp create mode 100755 megacells/fifo_1kx16.inc create mode 100755 megacells/fifo_1kx16.v create mode 100755 megacells/fifo_1kx16_bb.v create mode 100755 megacells/fifo_1kx16_inst.v delete mode 100755 megacells/fifo_2k_1clk.v delete mode 100755 megacells/fifo_2kx16.bsf delete mode 100755 megacells/fifo_2kx16.cmp delete mode 100755 megacells/fifo_2kx16.inc delete mode 100755 megacells/fifo_2kx16.v delete mode 100755 megacells/fifo_2kx16_bb.v delete mode 100755 megacells/fifo_2kx16_inst.v delete mode 100755 megacells/fifo_4kx16.bsf delete mode 100755 megacells/fifo_4kx16.cmp delete mode 100755 megacells/fifo_4kx16.inc delete mode 100755 megacells/fifo_4kx16.v delete mode 100755 megacells/fifo_4kx16_bb.v create mode 100755 megacells/fifo_4kx16_dc.bsf create mode 100755 megacells/fifo_4kx16_dc.cmp create mode 100755 megacells/fifo_4kx16_dc.inc create mode 100755 megacells/fifo_4kx16_dc.v create mode 100755 megacells/fifo_4kx16_dc_bb.v create mode 100755 megacells/fifo_4kx16_dc_inst.v delete mode 100755 megacells/fifo_4kx16_inst.v diff --git a/inband_lib/chan_fifo_reader.v b/inband_lib/chan_fifo_reader.v index 9392bf151..a6edf2c60 100755 --- a/inband_lib/chan_fifo_reader.v +++ b/inband_lib/chan_fifo_reader.v @@ -1,7 +1,7 @@ module chan_fifo_reader ( reset, tx_clock, tx_strobe, adc_time, samples_format, fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i, - underrun, tx_empty, debug, rssi, threshhold) ; + underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ; input wire reset ; input wire tx_clock ; @@ -18,6 +18,7 @@ module chan_fifo_reader output reg tx_empty ; //cause 0 to be the output input wire [31:0] rssi; input wire [31:0] threshhold; + input wire [31:0] rssi_wait; output wire [14:0] debug; assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]}; @@ -41,18 +42,19 @@ module chan_fifo_reader `define PAYLOAD 8:2 `define ENDOFBURST 27 `define STARTOFBURST 28 - `define RSSI_FLAG 15 + `define RSSI_FLAG 26 /* State registers */ reg [2:0] reader_state; - + /* Local registers */ reg [6:0] payload_len; reg [6:0] read_len; reg [31:0] timestamp; reg burst; reg trash; reg rssi_flag; + reg [31:0] time_wait; always @(posedge tx_clock) begin @@ -68,6 +70,7 @@ module chan_fifo_reader tx_i <= 0; trash <= 0; rssi_flag <= 0; + time_wait <= 0; end else begin @@ -81,13 +84,14 @@ module chan_fifo_reader * is already available to this fifo_reader when pkt_waiting is on */ skip <=0; + time_wait <= 0; if (pkt_waiting == 1) begin reader_state <= HEADER; rdreq <= 1; underrun <= 0; end - else if (burst == 1) + if (burst == 1 && pkt_waiting == 0) underrun <= 1; if (tx_strobe == 1) @@ -139,9 +143,18 @@ module chan_fifo_reader begin if (tx_strobe == 1) tx_empty <= 1 ; - - // Let's send it - if ((timestamp <= adc_time + `JITTER + + time_wait <= time_wait + 32'd1; + // Outdated + if ((timestamp < adc_time) || + (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag)) + begin + trash <= 1; + reader_state <= IDLE; + skip <= 1; + end + // Let's send it + else if ((timestamp <= adc_time + `JITTER && timestamp > adc_time) || timestamp == 32'hFFFFFFFF) begin @@ -153,16 +166,11 @@ module chan_fifo_reader else reader_state <= WAIT; end + else + reader_state <= WAIT; // Wait a little bit more - else if (timestamp > adc_time + `JITTER) - reader_state <= WAIT; - // Outdated - else if (timestamp < adc_time) - begin - trash <= 1; - reader_state <= IDLE; - skip <= 1; - end + //else if (timestamp > adc_time + `JITTER) + // reader_state <= WAIT; end // Wait for the transmit chain to be ready @@ -183,7 +191,7 @@ module chan_fifo_reader end end - // Send the samples to the tx_chain + // Send the samples to the tx_chain SEND: begin reader_state <= WAITSTROBE; diff --git a/inband_lib/channel_ram.v b/inband_lib/channel_ram.v index 40e0efc01..60450f02d 100755 --- a/inband_lib/channel_ram.v +++ b/inband_lib/channel_ram.v @@ -101,8 +101,8 @@ module channel_ram //packet_waiting is set to zero if rd_done_int is high //because there is no guarantee that nb_packets will be pos. - assign packet_waiting = (nb_packets != 0) & (~rd_done_int); - + //assign packet_waiting = (nb_packets != 0) & (~rd_done_int); + assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)); always @(posedge txclk) if (reset) nb_packets <= 0; diff --git a/inband_lib/packet_builder.v b/inband_lib/packet_builder.v index 205293479..fbf0a656e 100755 --- a/inband_lib/packet_builder.v +++ b/inband_lib/packet_builder.v @@ -15,7 +15,8 @@ module packet_builder #(parameter NUM_CHAN = 1)( output reg [15:0]fifodata, input have_space, input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2, - input wire [31:0]rssi_3, output wire [7:0] debugbus); + input wire [31:0]rssi_3, output wire [7:0] debugbus, + input [NUM_CHAN:0] overrun, input [NUM_CHAN:0] underrun); // States @@ -45,12 +46,14 @@ module packet_builder #(parameter NUM_CHAN = 1)( reg [3:0] check_next; wire [8:0] chan_used; wire [31:0] true_rssi; + wire [4:0] true_channel; - assign debugbus = {state, chan_empty[0], chan_empty[1], check_next[0], + assign debugbus = {state, chan_empty[0], underrun[0], check_next[0], have_space, rd_select[0]}; assign chan_used = chan_usedw[8:0]; assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) : - ((rd_select[0]) ? rssi_1:rssi_0); + ((rd_select[0]) ? rssi_1:rssi_0); + assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); always @(posedge rxclk) begin if (reset) @@ -64,6 +67,7 @@ module packet_builder #(parameter NUM_CHAN = 1)( end else case (state) `IDLE: begin + chan_rdreq <= #1 0; if (have_space) begin if(~chan_empty[check_next]) @@ -89,13 +93,12 @@ module packet_builder #(parameter NUM_CHAN = 1)( end `HEADER2: begin - fifodata[`CHAN] <= #1 (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); + fifodata[`CHAN] <= #1 true_channel; fifodata[`RSSI] <= #1 true_rssi[5:0]; fifodata[`BURST] <= #1 0; fifodata[`DROPPED] <= #1 0; - fifodata[`UNDERRUN] <= #1 0; - fifodata[`OVERRUN] <= #1 0; - + fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel]; + fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel]; state <= #1 `TIMESTAMP; end @@ -117,6 +120,7 @@ module packet_builder #(parameter NUM_CHAN = 1)( begin WR <= #1 0; state <= #1 `IDLE; + chan_rdreq <= #1 0; end else if (read_length == payload_len - 4) chan_rdreq <= #1 0; diff --git a/inband_lib/register_io.v b/inband_lib/register_io.v index 63a26549c..b116b3ace 100755 --- a/inband_lib/register_io.v +++ b/inband_lib/register_io.v @@ -2,12 +2,14 @@ module register_io (input clk, input reset, input wire [1:0] enable, input wire [6:0] addr, input wire [31:0] datain, output reg [31:0] dataout, output wire [15:0] debugbus, input wire [31:0] rssi_0, input wire [31:0] rssi_1, - input wire [31:0] rssi_2, input wire [31:0] rssi_3, output wire [31:0] threshhold); + input wire [31:0] rssi_2, input wire [31:0] rssi_3, + output wire [31:0] threshhold, output wire [31:0] rssi_wait); reg strobe; wire [31:0] out[7:0]; assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]}; assign threshhold = out[1]; + assign rssi_wait = out[2]; always @(*) if (reset | ~enable[1]) diff --git a/inband_lib/rx_buffer_inband.v b/inband_lib/rx_buffer_inband.v index c23ce09b7..1eaecabed 100755 --- a/inband_lib/rx_buffer_inband.v +++ b/inband_lib/rx_buffer_inband.v @@ -1,175 +1,179 @@ -//`include "../../firmware/include/fpga_regs_common.v" -//`include "../../firmware/include/fpga_regs_standard.v" -module rx_buffer_inband - ( input usbclk, - input bus_reset, - input reset, // DSP side reset (used here), do not reset registers - input reset_regs, //Only reset registers - output [15:0] usbdata, - input RD, - output wire have_pkt_rdy, - output reg rx_overrun, - input wire [3:0] channels, - input wire [15:0] ch_0, - input wire [15:0] ch_1, - input wire [15:0] ch_2, - input wire [15:0] ch_3, - input wire [15:0] ch_4, - input wire [15:0] ch_5, - input wire [15:0] ch_6, - input wire [15:0] ch_7, - input rxclk, - input rxstrobe, - input clear_status, - input [6:0] serial_addr, - input [31:0] serial_data, - input serial_strobe, - output wire [15:0] debugbus, - - //Connection with tx_inband - input rx_WR, - input [15:0] rx_databus, - input rx_WR_done, - output reg rx_WR_enabled, - //signal strength - input wire [31:0] rssi_0, input wire [31:0] rssi_1, - input wire [31:0] rssi_2, input wire [31:0] rssi_3 - ); - - parameter NUM_CHAN = 1; - genvar i ; - - // FX2 Bug Fix - reg [8:0] read_count; - always @(negedge usbclk) - if(bus_reset) - read_count <= #1 9'd0; - else if(RD & ~read_count[8]) - read_count <= #1 read_count + 9'd1; - else - read_count <= #1 RD ? read_count : 9'b0; - - // Time counter - reg [31:0] adctime; - always @(posedge rxclk) - if (reset) - adctime <= 0; - else if (rxstrobe) - adctime <= adctime + 1; - - // USB side fifo - wire [11:0] rdusedw; - wire [11:0] wrusedw; - wire [15:0] fifodata; - wire WR; - wire have_space; - - fifo_4kx16_dc rx_usb_fifo ( - .aclr ( reset ), - .data ( fifodata ), - .rdclk ( ~usbclk ), - .rdreq ( RD & ~read_count[8] ), - .wrclk ( rxclk ), - .wrreq ( WR ), - .q ( usbdata ), - .rdempty ( ), - .rdusedw ( rdusedw ), - .wrfull ( ), - .wrusedw ( wrusedw ) ); - - assign have_pkt_rdy = (rdusedw >= 12'd256); - assign have_space = (wrusedw < 12'd760); - - // Rx side fifos - wire chan_rdreq; - wire [15:0] chan_fifodata; - wire [9:0] chan_usedw; - wire [NUM_CHAN:0] chan_empty; - wire [3:0] rd_select; - wire [NUM_CHAN:0] rx_full; - - packet_builder #(NUM_CHAN) rx_pkt_builer ( - .rxclk ( rxclk ), - .reset ( reset ), - .adctime ( adctime ), - .channels ( 4'd1 ), - .chan_rdreq ( chan_rdreq ), - .chan_fifodata ( chan_fifodata ), - .chan_empty ( chan_empty ), - .rd_select ( rd_select ), - .chan_usedw ( chan_usedw ), - .WR ( WR ), - .fifodata ( fifodata ), - .have_space ( have_space ), - .rssi_0(rssi_0), .rssi_1(rssi_1), - .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug)); - - // Detect overrun - always @(posedge rxclk) - if(reset) - rx_overrun <= 1'b0; - else if(rx_full[0]) - rx_overrun <= 1'b1; - else if(clear_status) - rx_overrun <= 1'b0; - - reg [6:0] test; - always @(posedge rxclk) - if (reset) - test <= 0; - else - test <= test + 7'd1; - - // TODO write this genericly - wire [15:0]ch[NUM_CHAN:0]; - assign ch[0] = ch_0; - - wire cmd_empty; - always @(posedge rxclk) - if(reset) - rx_WR_enabled <= 1; - else if(cmd_empty) - rx_WR_enabled <= 1; - else if(rx_WR_done) - rx_WR_enabled <= 0; - - wire [15:0] dataout [0:NUM_CHAN]; - wire [9:0] usedw [0:NUM_CHAN]; - - generate for (i = 0 ; i < NUM_CHAN; i = i + 1) - begin : generate_channel_fifos - wire rdreq; - - assign rdreq = (rd_select == i) & chan_rdreq; - assign chan_empty[i] = usedw[i] < 10'd126; - - fifo_2kx16 rx_chan_fifo ( - .aclr ( reset ), - .clock ( rxclk ), - .data ( ch[i] ), - .rdreq ( rdreq ), - .wrreq ( ~rx_full[i] & rxstrobe), - .empty ( ), - .full ( rx_full[i] ), - .q ( dataout[i]), - .usedw ( usedw[i] ) - ); - end - endgenerate - wire [7:0] debug; - fifo_2kx16 rx_cmd_fifo ( - .aclr ( reset ), - .clock ( rxclk ), - .data ( rx_databus ), - .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), - .wrreq ( rx_WR & rx_WR_enabled), - .empty ( cmd_empty), - .full ( rx_full[NUM_CHAN] ), - .q ( dataout[NUM_CHAN]), - .usedw ( usedw[NUM_CHAN] ) - ); - assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; - assign chan_fifodata = dataout[rd_select]; - assign chan_usedw = usedw[rd_select]; - assign debugbus = {wrusedw, have_space, RD, read_count[8], rxclk}; -endmodule +//`include "../../firmware/include/fpga_regs_common.v" +//`include "../../firmware/include/fpga_regs_standard.v" +module rx_buffer_inband + ( input usbclk, + input bus_reset, + input reset, // DSP side reset (used here), do not reset registers + input reset_regs, //Only reset registers + output [15:0] usbdata, + input RD, + output wire have_pkt_rdy, + output reg rx_overrun, + input wire [3:0] channels, + input wire [15:0] ch_0, + input wire [15:0] ch_1, + input wire [15:0] ch_2, + input wire [15:0] ch_3, + input wire [15:0] ch_4, + input wire [15:0] ch_5, + input wire [15:0] ch_6, + input wire [15:0] ch_7, + input rxclk, + input rxstrobe, + input clear_status, + input [6:0] serial_addr, + input [31:0] serial_data, + input serial_strobe, + output wire [15:0] debugbus, + + //Connection with tx_inband + input rx_WR, + input [15:0] rx_databus, + input rx_WR_done, + output reg rx_WR_enabled, + //signal strength + input wire [31:0] rssi_0, input wire [31:0] rssi_1, + input wire [31:0] rssi_2, input wire [31:0] rssi_3, + input wire [1:0] tx_overrun, input wire [1:0] tx_underrun + ); + + parameter NUM_CHAN = 1; + genvar i ; + + // FX2 Bug Fix + reg [8:0] read_count; + always @(negedge usbclk) + if(bus_reset) + read_count <= #1 9'd0; + else if(RD & ~read_count[8]) + read_count <= #1 read_count + 9'd1; + else + read_count <= #1 RD ? read_count : 9'b0; + + // Time counter + reg [31:0] adctime; + always @(posedge rxclk) + if (reset) + adctime <= 0; + else if (rxstrobe) + adctime <= adctime + 1; + + // USB side fifo + wire [11:0] rdusedw; + wire [11:0] wrusedw; + wire [15:0] fifodata; + wire WR; + wire have_space; + + fifo_4kx16_dc rx_usb_fifo ( + .aclr ( reset ), + .data ( fifodata ), + .rdclk ( ~usbclk ), + .rdreq ( RD & ~read_count[8] ), + .wrclk ( rxclk ), + .wrreq ( WR ), + .q ( usbdata ), + .rdempty ( ), + .rdusedw ( rdusedw ), + .wrfull ( ), + .wrusedw ( wrusedw ) ); + + assign have_pkt_rdy = (rdusedw >= 12'd256); + assign have_space = (wrusedw < 12'd760); + + // Rx side fifos + wire chan_rdreq; + wire [15:0] chan_fifodata; + wire [9:0] chan_usedw; + wire [NUM_CHAN:0] chan_empty; + wire [3:0] rd_select; + wire [NUM_CHAN:0] rx_full; + + packet_builder #(NUM_CHAN) rx_pkt_builer ( + .rxclk ( rxclk ), + .reset ( reset ), + .adctime ( adctime ), + .channels ( 4'd1 ), + .chan_rdreq ( chan_rdreq ), + .chan_fifodata ( chan_fifodata ), + .chan_empty ( chan_empty ), + .rd_select ( rd_select ), + .chan_usedw ( chan_usedw ), + .WR ( WR ), + .fifodata ( fifodata ), + .have_space ( have_space ), + .rssi_0(rssi_0), .rssi_1(rssi_1), + .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug), + .overrun(tx_overrun), .underrun(tx_underrun)); + + // Detect overrun + always @(posedge rxclk) + if(reset) + rx_overrun <= 1'b0; + else if(rx_full[0]) + rx_overrun <= 1'b1; + else if(clear_status) + rx_overrun <= 1'b0; + + reg [6:0] test; + always @(posedge rxclk) + if (reset) + test <= 0; + else + test <= test + 7'd1; + + // TODO write this genericly + wire [15:0]ch[NUM_CHAN:0]; + assign ch[0] = ch_0; + + wire cmd_empty; + always @(posedge rxclk) + if(reset) + rx_WR_enabled <= 1; + else if(cmd_empty) + rx_WR_enabled <= 1; + else if(rx_WR_done) + rx_WR_enabled <= 0; + + wire [15:0] dataout [0:NUM_CHAN]; + wire [9:0] usedw [0:NUM_CHAN]; + wire empty[0:NUM_CHAN]; + + generate for (i = 0 ; i < NUM_CHAN; i = i + 1) + begin : generate_channel_fifos + wire rdreq; + + assign rdreq = (rd_select == i) & chan_rdreq; + //assign chan_empty[i] = usedw[i] < 10'd126; + fifo_1kx16 rx_chan_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( ch[i] ), + .rdreq ( rdreq ), + .wrreq ( ~rx_full[i] & rxstrobe), + .empty (empty[i]), + .full (rx_full[i]), + .q ( dataout[i]), + .usedw ( usedw[i]), + .almost_empty(chan_empty[i]) + ); + end + endgenerate + wire [7:0] debug; + fifo_1kx16 rx_cmd_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( rx_databus ), + .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), + .wrreq ( rx_WR & rx_WR_enabled), + .empty ( cmd_empty), + .full ( rx_full[NUM_CHAN] ), + .q ( dataout[NUM_CHAN]), + .usedw ( usedw[NUM_CHAN] ) + ); + assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; + assign chan_fifodata = dataout[rd_select]; + assign chan_usedw = usedw[rd_select]; + assign debugbus = {rxstrobe, chan_rdreq, debug, + rx_full[0], chan_empty[0], empty[0], have_space, RD, rxclk}; +endmodule diff --git a/inband_lib/tx_buffer_inband.v b/inband_lib/tx_buffer_inband.v index af7ed394a..fec9dbe31 100755 --- a/inband_lib/tx_buffer_inband.v +++ b/inband_lib/tx_buffer_inband.v @@ -1,18 +1,13 @@ module tx_buffer_inband ( usbclk, bus_reset, reset, usbdata, WR, have_space, - tx_underrun, channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1, + channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1, tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe, clear_status, tx_empty, debugbus, rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable, reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2, - rssi_3, threshhold + rssi_3, rssi_wait, threshhold, tx_underrun ); - - //CHAN_WIDTH is the width of the channel - //NUM_CHAN is the number of data channel (index from 0 to NUM_CHAN-1) - //index NUM_CHAN is reserved for command - parameter CHAN_WIDTH = 2 ; parameter NUM_CHAN = 2 ; /* Debug paramters */ parameter STROBE_RATE_0 = 8'd1 ; @@ -37,9 +32,9 @@ module tx_buffer_inband input wire [31:0]rssi_2; input wire [31:0]rssi_3; input wire [31:0]threshhold; - + input wire [31:0]rssi_wait; + output wire have_space ; - output wire tx_underrun ; output wire tx_empty ; output wire [15:0] tx_i_0 ; output wire [15:0] tx_q_0 ; @@ -59,13 +54,14 @@ module tx_buffer_inband output wire [31:0] reg_data_in; output wire [6:0] reg_addr; output wire [1:0] reg_io_enable; + output wire [NUM_CHAN-1:0] tx_underrun; /* To generate channel readers */ genvar i ; /* These will eventually be external register */ reg [31:0] adc_time ; - wire [7:0] txstrobe_rate [CHAN_WIDTH-1:0] ; + wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ; wire [31:0] rssi [3:0]; assign rssi[0] = rssi_0; assign rssi[1] = rssi_1; @@ -82,33 +78,32 @@ module tx_buffer_inband /* Connections between tx_usb_fifo_reader and cnannel/command processing blocks */ wire [31:0] tx_data_bus ; - wire [CHAN_WIDTH:0] chan_WR ; - wire [CHAN_WIDTH:0] chan_done ; + wire [NUM_CHAN:0] chan_WR ; + wire [NUM_CHAN:0] chan_done ; /* Connections between data block and the FX2/TX chains */ - wire [CHAN_WIDTH:0] chan_underrun ; - wire [CHAN_WIDTH:0] chan_txempty ; + wire [NUM_CHAN:0] chan_underrun ; + wire [NUM_CHAN:0] chan_txempty ; /* Conections between tx_data_packet_fifo and its reader + strobe generator */ - wire [31:0] chan_fifodata [CHAN_WIDTH:0] ; - wire chan_pkt_waiting [CHAN_WIDTH:0] ; - wire chan_rdreq [CHAN_WIDTH:0] ; - wire chan_skip [CHAN_WIDTH:0] ; - wire [CHAN_WIDTH:0] chan_have_space ; - wire chan_txstrobe [CHAN_WIDTH-1:0] ; + wire [31:0] chan_fifodata [NUM_CHAN:0] ; + wire chan_pkt_waiting [NUM_CHAN:0] ; + wire chan_rdreq [NUM_CHAN:0] ; + wire chan_skip [NUM_CHAN:0] ; + wire [NUM_CHAN:0] chan_have_space ; + wire chan_txstrobe [NUM_CHAN-1:0] ; wire [14:0] debug; /* Outputs to transmit chains */ - wire [15:0] tx_i [CHAN_WIDTH-1:0] ; - wire [15:0] tx_q [CHAN_WIDTH-1:0] ; + wire [15:0] tx_i [NUM_CHAN-1:0] ; + wire [15:0] tx_q [NUM_CHAN-1:0] ; /* TODO: Figure out how to write this genericly */ assign have_space = chan_have_space[0] & chan_have_space[1]; assign tx_empty = chan_txempty[0] & chan_txempty[1] ; - assign tx_underrun = chan_underrun[0] | chan_underrun[1] ; assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; @@ -153,6 +148,7 @@ module tx_buffer_inband generate for (i = 0 ; i < NUM_CHAN; i = i + 1) begin : generate_channel_readers + assign tx_underrun[i] = chan_underrun[i]; channel_ram tx_data_packet_fifo ( .reset (reset), .txclk (txclk), @@ -181,7 +177,8 @@ module tx_buffer_inband .pkt_waiting (chan_pkt_waiting[i]), .tx_empty (chan_txempty[i]), .rssi (rssi[i]), - .threshhold (threshhold) + .threshhold (threshhold), + .rssi_wait (rssi_wait) ); end diff --git a/megacells/fifo_1kx16.bsf b/megacells/fifo_1kx16.bsf new file mode 100755 index 000000000..329be2d44 --- /dev/null +++ b/megacells/fifo_1kx16.bsf @@ -0,0 +1,107 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 160) + (text "fifo_1kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 144 25 156)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 56) + (output) + (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 144 56)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 1)) + ) + (port + (pt 160 88) + (output) + (text "almost_empty" (rect 0 0 77 14)(font "Arial" (font_size 8))) + (text "almost_empty" (rect 75 82 141 95)(font "Arial" (font_size 8))) + (line (pt 160 88)(pt 144 88)(line_width 1)) + ) + (port + (pt 160 104) + (output) + (text "usedw[9..0]" (rect 0 0 68 14)(font "Arial" (font_size 8))) + (text "usedw[9..0]" (rect 83 98 136 111)(font "Arial" (font_size 8))) + (line (pt 160 104)(pt 144 104)(line_width 3)) + ) + (drawing + (text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial" )) + (text "almost_empty < 126" (rect 58 122 144 134)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 144)(line_width 1)) + (line (pt 144 144)(pt 16 144)(line_width 1)) + (line (pt 16 144)(pt 16 16)(line_width 1)) + (line (pt 16 116)(pt 144 116)(line_width 1)) + (line (pt 16 90)(pt 22 96)(line_width 1)) + (line (pt 22 96)(pt 16 102)(line_width 1)) + ) +) diff --git a/megacells/fifo_1kx16.cmp b/megacells/fifo_1kx16.cmp new file mode 100755 index 000000000..9b2c2c0c3 --- /dev/null +++ b/megacells/fifo_1kx16.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_1kx16 + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + almost_empty : OUT STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +end component; diff --git a/megacells/fifo_1kx16.inc b/megacells/fifo_1kx16.inc new file mode 100755 index 000000000..0b70afe62 --- /dev/null +++ b/megacells/fifo_1kx16.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_1kx16 +( + aclr, + clock, + data[15..0], + rdreq, + wrreq +) + +RETURNS ( + almost_empty, + empty, + full, + q[15..0], + usedw[9..0] +); diff --git a/megacells/fifo_1kx16.v b/megacells/fifo_1kx16.v new file mode 100755 index 000000000..e22b416e5 --- /dev/null +++ b/megacells/fifo_1kx16.v @@ -0,0 +1,175 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_1kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_1kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + almost_empty, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output almost_empty; + output empty; + output full; + output [15:0] q; + output [9:0] usedw; + + wire [9:0] sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire sub_wire4; + wire [9:0] usedw = sub_wire0[9:0]; + wire empty = sub_wire1; + wire almost_empty = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire full = sub_wire4; + + scfifo scfifo_component ( + .rdreq (rdreq), + .aclr (aclr), + .clock (clock), + .wrreq (wrreq), + .data (data), + .usedw (sub_wire0), + .empty (sub_wire1), + .almost_empty (sub_wire2), + .q (sub_wire3), + .full (sub_wire4) + // synopsys translate_off + , + .sclr (), + .almost_full () + // synopsys translate_on + ); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.almost_empty_value = 126, + scfifo_component.intended_device_family = "Cyclone", + scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", + scfifo_component.lpm_numwords = 1024, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 16, + scfifo_component.lpm_widthu = 10, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE diff --git a/megacells/fifo_1kx16_bb.v b/megacells/fifo_1kx16_bb.v new file mode 100755 index 000000000..283aada81 --- /dev/null +++ b/megacells/fifo_1kx16_bb.v @@ -0,0 +1,127 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_1kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_1kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + almost_empty, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output almost_empty; + output empty; + output full; + output [15:0] q; + output [9:0] usedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE diff --git a/megacells/fifo_1kx16_inst.v b/megacells/fifo_1kx16_inst.v new file mode 100755 index 000000000..73662dea3 --- /dev/null +++ b/megacells/fifo_1kx16_inst.v @@ -0,0 +1,12 @@ +fifo_1kx16 fifo_1kx16_inst ( + .aclr ( aclr_sig ), + .clock ( clock_sig ), + .data ( data_sig ), + .rdreq ( rdreq_sig ), + .wrreq ( wrreq_sig ), + .almost_empty ( almost_empty_sig ), + .empty ( empty_sig ), + .full ( full_sig ), + .q ( q_sig ), + .usedw ( usedw_sig ) + ); diff --git a/megacells/fifo_2k_1clk.v b/megacells/fifo_2k_1clk.v deleted file mode 100755 index 095615bb8..000000000 --- a/megacells/fifo_2k_1clk.v +++ /dev/null @@ -1,167 +0,0 @@ -// megafunction wizard: %LPM_FIFO+% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_2k_1clk.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_2k_1clk ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [9:0] usedw; - - wire [9:0] sub_wire0; - wire sub_wire1; - wire [15:0] sub_wire2; - wire sub_wire3; - wire [9:0] usedw = sub_wire0[9:0]; - wire empty = sub_wire1; - wire [15:0] q = sub_wire2[15:0]; - wire full = sub_wire3; - - scfifo scfifo_component ( - .rdreq (rdreq), - .aclr (aclr), - .clock (clock), - .wrreq (wrreq), - .data (data), - .usedw (sub_wire0), - .empty (sub_wire1), - .q (sub_wire2), - .full (sub_wire3) - // synopsys translate_off - , - .almost_empty (), - .sclr (), - .almost_full () - // synopsys translate_on - ); - defparam - scfifo_component.add_ram_output_register = "OFF", - scfifo_component.intended_device_family = "Cyclone", - scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", - scfifo_component.lpm_numwords = 1024, - scfifo_component.lpm_showahead = "OFF", - scfifo_component.lpm_type = "scfifo", - scfifo_component.lpm_width = 16, - scfifo_component.lpm_widthu = 10, - scfifo_component.overflow_checking = "ON", - scfifo_component.underflow_checking = "ON", - scfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "1024" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_waveforms.html FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_wave*.jpg FALSE diff --git a/megacells/fifo_2kx16.bsf b/megacells/fifo_2kx16.bsf deleted file mode 100755 index 1067991fb..000000000 --- a/megacells/fifo_2kx16.bsf +++ /dev/null @@ -1,99 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2006 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 144) - (text "fifo_2kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 128 25 140)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 114 37 127)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 160 32) - (output) - (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) - (line (pt 160 32)(pt 144 32)(line_width 3)) - ) - (port - (pt 160 56) - (output) - (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) - (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) - (line (pt 160 56)(pt 144 56)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 144 72)(line_width 1)) - ) - (port - (pt 160 88) - (output) - (text "usedw[10..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) - (text "usedw[10..0]" (rect 77 82 136 95)(font "Arial" (font_size 8))) - (line (pt 160 88)(pt 144 88)(line_width 3)) - ) - (drawing - (text "16 bits x 2048 words" (rect 58 116 144 128)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 128)(line_width 1)) - (line (pt 144 128)(pt 16 128)(line_width 1)) - (line (pt 16 128)(pt 16 16)(line_width 1)) - (line (pt 16 108)(pt 144 108)(line_width 1)) - (line (pt 16 90)(pt 22 96)(line_width 1)) - (line (pt 22 96)(pt 16 102)(line_width 1)) - ) -) diff --git a/megacells/fifo_2kx16.cmp b/megacells/fifo_2kx16.cmp deleted file mode 100755 index 96c34d8d7..000000000 --- a/megacells/fifo_2kx16.cmp +++ /dev/null @@ -1,29 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component fifo_2kx16 - PORT - ( - aclr : IN STD_LOGIC ; - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rdreq : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - empty : OUT STD_LOGIC ; - full : OUT STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) - ); -end component; diff --git a/megacells/fifo_2kx16.inc b/megacells/fifo_2kx16.inc deleted file mode 100755 index 3d72c6601..000000000 --- a/megacells/fifo_2kx16.inc +++ /dev/null @@ -1,30 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION fifo_2kx16 -( - aclr, - clock, - data[15..0], - rdreq, - wrreq -) - -RETURNS ( - empty, - full, - q[15..0], - usedw[10..0] -); diff --git a/megacells/fifo_2kx16.v b/megacells/fifo_2kx16.v deleted file mode 100755 index eb229769d..000000000 --- a/megacells/fifo_2kx16.v +++ /dev/null @@ -1,167 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_2kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_2kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [10:0] usedw; - - wire [10:0] sub_wire0; - wire sub_wire1; - wire [15:0] sub_wire2; - wire sub_wire3; - wire [10:0] usedw = sub_wire0[10:0]; - wire empty = sub_wire1; - wire [15:0] q = sub_wire2[15:0]; - wire full = sub_wire3; - - scfifo scfifo_component ( - .rdreq (rdreq), - .aclr (aclr), - .clock (clock), - .wrreq (wrreq), - .data (data), - .usedw (sub_wire0), - .empty (sub_wire1), - .q (sub_wire2), - .full (sub_wire3) - // synopsys translate_off - , - .almost_empty (), - .sclr (), - .almost_full () - // synopsys translate_on - ); - defparam - scfifo_component.add_ram_output_register = "OFF", - scfifo_component.intended_device_family = "Cyclone", - scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", - scfifo_component.lpm_numwords = 2048, - scfifo_component.lpm_showahead = "OFF", - scfifo_component.lpm_type = "scfifo", - scfifo_component.lpm_width = 16, - scfifo_component.lpm_widthu = 11, - scfifo_component.overflow_checking = "ON", - scfifo_component.underflow_checking = "ON", - scfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "2048" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL usedw[10..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_wave*.jpg FALSE diff --git a/megacells/fifo_2kx16_bb.v b/megacells/fifo_2kx16_bb.v deleted file mode 100755 index 507bac073..000000000 --- a/megacells/fifo_2kx16_bb.v +++ /dev/null @@ -1,122 +0,0 @@ -// megafunction wizard: %FIFO%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_2kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_2kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [10:0] usedw; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "2048" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL usedw[10..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_wave*.jpg FALSE diff --git a/megacells/fifo_2kx16_inst.v b/megacells/fifo_2kx16_inst.v deleted file mode 100755 index 6185c6fe6..000000000 --- a/megacells/fifo_2kx16_inst.v +++ /dev/null @@ -1,11 +0,0 @@ -fifo_2kx16 fifo_2kx16_inst ( - .aclr ( aclr_sig ), - .clock ( clock_sig ), - .data ( data_sig ), - .rdreq ( rdreq_sig ), - .wrreq ( wrreq_sig ), - .empty ( empty_sig ), - .full ( full_sig ), - .q ( q_sig ), - .usedw ( usedw_sig ) - ); diff --git a/megacells/fifo_4kx16.bsf b/megacells/fifo_4kx16.bsf deleted file mode 100755 index 4d988c5e9..000000000 --- a/megacells/fifo_4kx16.bsf +++ /dev/null @@ -1,99 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2006 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 144) - (text "fifo_4kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 128 25 140)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 114 37 127)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 160 32) - (output) - (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) - (line (pt 160 32)(pt 144 32)(line_width 3)) - ) - (port - (pt 160 56) - (output) - (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) - (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) - (line (pt 160 56)(pt 144 56)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 144 72)(line_width 1)) - ) - (port - (pt 160 88) - (output) - (text "usedw[11..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) - (text "usedw[11..0]" (rect 77 82 136 95)(font "Arial" (font_size 8))) - (line (pt 160 88)(pt 144 88)(line_width 3)) - ) - (drawing - (text "16 bits x 4096 words" (rect 58 116 144 128)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 128)(line_width 1)) - (line (pt 144 128)(pt 16 128)(line_width 1)) - (line (pt 16 128)(pt 16 16)(line_width 1)) - (line (pt 16 108)(pt 144 108)(line_width 1)) - (line (pt 16 90)(pt 22 96)(line_width 1)) - (line (pt 22 96)(pt 16 102)(line_width 1)) - ) -) diff --git a/megacells/fifo_4kx16.cmp b/megacells/fifo_4kx16.cmp deleted file mode 100755 index 7bc6941d7..000000000 --- a/megacells/fifo_4kx16.cmp +++ /dev/null @@ -1,29 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component fifo_4kx16 - PORT - ( - aclr : IN STD_LOGIC ; - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rdreq : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - empty : OUT STD_LOGIC ; - full : OUT STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - usedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) - ); -end component; diff --git a/megacells/fifo_4kx16.inc b/megacells/fifo_4kx16.inc deleted file mode 100755 index db5d4f29e..000000000 --- a/megacells/fifo_4kx16.inc +++ /dev/null @@ -1,30 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION fifo_4kx16 -( - aclr, - clock, - data[15..0], - rdreq, - wrreq -) - -RETURNS ( - empty, - full, - q[15..0], - usedw[11..0] -); diff --git a/megacells/fifo_4kx16.v b/megacells/fifo_4kx16.v deleted file mode 100755 index c5ecfbae7..000000000 --- a/megacells/fifo_4kx16.v +++ /dev/null @@ -1,167 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_4kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_4kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [11:0] usedw; - - wire [11:0] sub_wire0; - wire sub_wire1; - wire [15:0] sub_wire2; - wire sub_wire3; - wire [11:0] usedw = sub_wire0[11:0]; - wire empty = sub_wire1; - wire [15:0] q = sub_wire2[15:0]; - wire full = sub_wire3; - - scfifo scfifo_component ( - .rdreq (rdreq), - .aclr (aclr), - .clock (clock), - .wrreq (wrreq), - .data (data), - .usedw (sub_wire0), - .empty (sub_wire1), - .q (sub_wire2), - .full (sub_wire3) - // synopsys translate_off - , - .almost_empty (), - .sclr (), - .almost_full () - // synopsys translate_on - ); - defparam - scfifo_component.add_ram_output_register = "OFF", - scfifo_component.intended_device_family = "Cyclone", - scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", - scfifo_component.lpm_numwords = 4096, - scfifo_component.lpm_showahead = "OFF", - scfifo_component.lpm_type = "scfifo", - scfifo_component.lpm_width = 16, - scfifo_component.lpm_widthu = 12, - scfifo_component.overflow_checking = "ON", - scfifo_component.underflow_checking = "ON", - scfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 12 0 OUTPUT NODEFVAL usedw[11..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 12 0 @usedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_bb.v b/megacells/fifo_4kx16_bb.v deleted file mode 100755 index d41e9f090..000000000 --- a/megacells/fifo_4kx16_bb.v +++ /dev/null @@ -1,122 +0,0 @@ -// megafunction wizard: %FIFO%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_4kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_4kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [11:0] usedw; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 12 0 OUTPUT NODEFVAL usedw[11..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 12 0 @usedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_dc.bsf b/megacells/fifo_4kx16_dc.bsf new file mode 100755 index 000000000..b80add8de --- /dev/null +++ b/megacells/fifo_4kx16_dc.bsf @@ -0,0 +1,117 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 184) + (text "fifo_4kx16_dc" (rect 41 1 134 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 168 25 180)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 16 160)(line_width 1)) + ) + (port + (pt 160 40) + (output) + (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8))) + (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8))) + (line (pt 160 40)(pt 144 40)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "wrusedw[11..0]" (rect 0 0 92 14)(font "Arial" (font_size 8))) + (text "wrusedw[11..0]" (rect 63 66 132 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 3)) + ) + (port + (pt 160 96) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (port + (pt 160 120) + (output) + (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) + (text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8))) + (line (pt 160 120)(pt 144 120)(line_width 1)) + ) + (port + (pt 160 136) + (output) + (text "rdusedw[11..0]" (rect 0 0 87 14)(font "Arial" (font_size 8))) + (text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8))) + (line (pt 160 136)(pt 144 136)(line_width 3)) + ) + (drawing + (text "(ack)" (rect 51 99 72 111)(font "Arial" )) + (text "16 bits x 4096 words" (rect 58 156 144 168)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 168)(line_width 1)) + (line (pt 144 168)(pt 16 168)(line_width 1)) + (line (pt 16 168)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 148)(pt 144 148)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/megacells/fifo_4kx16_dc.cmp b/megacells/fifo_4kx16_dc.cmp new file mode 100755 index 000000000..356de4d62 --- /dev/null +++ b/megacells/fifo_4kx16_dc.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_4kx16_dc + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + wrfull : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) + ); +end component; diff --git a/megacells/fifo_4kx16_dc.inc b/megacells/fifo_4kx16_dc.inc new file mode 100755 index 000000000..c14c01836 --- /dev/null +++ b/megacells/fifo_4kx16_dc.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_4kx16_dc +( + aclr, + data[15..0], + rdclk, + rdreq, + wrclk, + wrreq +) + +RETURNS ( + q[15..0], + rdempty, + rdusedw[11..0], + wrfull, + wrusedw[11..0] +); diff --git a/megacells/fifo_4kx16_dc.v b/megacells/fifo_4kx16_dc.v new file mode 100755 index 000000000..1f09000e3 --- /dev/null +++ b/megacells/fifo_4kx16_dc.v @@ -0,0 +1,178 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4kx16_dc.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_4kx16_dc ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdusedw, + wrfull, + wrusedw); + + input aclr; + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + + wire sub_wire0; + wire [11:0] sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire [11:0] sub_wire4; + wire rdempty = sub_wire0; + wire [11:0] wrusedw = sub_wire1[11:0]; + wire wrfull = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire [11:0] rdusedw = sub_wire4[11:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4) + // synopsys translate_off + , + .wrempty (), + .rdfull () + // synopsys translate_on + ); + defparam + dcfifo_component.add_ram_output_register = "OFF", + dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone", + dcfifo_component.lpm_numwords = 4096, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 16, + dcfifo_component.lpm_widthu = 12, + dcfifo_component.overflow_checking = "OFF", + dcfifo_component.underflow_checking = "OFF", + dcfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_dc_bb.v b/megacells/fifo_4kx16_dc_bb.v new file mode 100755 index 000000000..91c3c322f --- /dev/null +++ b/megacells/fifo_4kx16_dc_bb.v @@ -0,0 +1,130 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4kx16_dc.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_4kx16_dc ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdusedw, + wrfull, + wrusedw); + + input aclr; + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_dc_inst.v b/megacells/fifo_4kx16_dc_inst.v new file mode 100755 index 000000000..566f27a17 --- /dev/null +++ b/megacells/fifo_4kx16_dc_inst.v @@ -0,0 +1,13 @@ +fifo_4kx16_dc fifo_4kx16_dc_inst ( + .aclr ( aclr_sig ), + .data ( data_sig ), + .rdclk ( rdclk_sig ), + .rdreq ( rdreq_sig ), + .wrclk ( wrclk_sig ), + .wrreq ( wrreq_sig ), + .q ( q_sig ), + .rdempty ( rdempty_sig ), + .rdusedw ( rdusedw_sig ), + .wrfull ( wrfull_sig ), + .wrusedw ( wrusedw_sig ) + ); diff --git a/megacells/fifo_4kx16_inst.v b/megacells/fifo_4kx16_inst.v deleted file mode 100755 index eb260acaa..000000000 --- a/megacells/fifo_4kx16_inst.v +++ /dev/null @@ -1,11 +0,0 @@ -fifo_4kx16 fifo_4kx16_inst ( - .aclr ( aclr_sig ), - .clock ( clock_sig ), - .data ( data_sig ), - .rdreq ( rdreq_sig ), - .wrreq ( wrreq_sig ), - .empty ( empty_sig ), - .full ( full_sig ), - .q ( q_sig ), - .usedw ( usedw_sig ) - ); diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf index 6b4764078..c9eebc1ad 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -372,14 +372,14 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4kx16_dc.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16.v set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k_1clk.v set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1k.v set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.v b/toplevel/usrp_inband_usb/usrp_inband_usb.v index 3bfdda56b..cc625b0e7 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.v +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.v @@ -74,10 +74,10 @@ module usrp_inband_usb assign usbrdy[0] = have_space; assign usbrdy[1] = have_pkt_rdy; - wire tx_underrun, rx_overrun; + wire rx_overrun; wire clear_status = FX2_1; assign FX2_2 = rx_overrun; - assign FX2_3 = tx_underrun; + assign FX2_3 = (tx_underrun == 0); wire [15:0] usbdata_out; @@ -135,16 +135,20 @@ wire [31:0] reg_data_out; wire [31:0] reg_data_in; wire [1:0] reg_io_enable; wire [31:0] rssi_threshhold; +wire [31:0] rssi_wait; + register_io register_control (.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in), .dataout(reg_data_out),.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), - .rssi_3(rssi_3), .threshhold(rssi_threshhold)); + .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait)); +wire [1:0] tx_overrun; +wire [1:0] tx_underrun; `ifdef TX_IN_BAND tx_buffer_inband tx_buffer ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), - .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), - .channels({tx_numchan,1'b0}), + .usbdata(usbdata),.WR(WR),.have_space(have_space), + .tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}), .tx_i_0(ch0tx),.tx_q_0(ch1tx), .tx_i_1(ch2tx),.tx_q_1(ch3tx), .tx_i_2(),.tx_q_2(), @@ -160,9 +164,9 @@ register_io register_control .reg_data_out(reg_data_out), .reg_data_in(reg_data_in), .reg_io_enable(reg_io_enable), - .debugbus(tx_debugbus), + .debugbus(), .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), - .rssi_3(rssi_3), .threshhold(rssi_threshhold)); + .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait)); `else tx_buffer tx_buffer ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), @@ -277,8 +281,9 @@ register_io register_control .rx_databus(rx_databus), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled), - .debugbus(rx_debugbus), - .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3)); + .debugbus(tx_debugbus), + .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3), + .tx_overrun(tx_overrun), .tx_underrun(tx_underrun)); `else rx_buffer rx_buffer ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), @@ -291,8 +296,7 @@ register_io register_control .ch_6(ch6rx),.ch_7(ch7rx), .rxclk(clk64),.rxstrobe(hb_strobe), .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)/*, - .debugbus(rx_debugbus)*/); + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); `endif `ifdef RX_EN_0 @@ -371,7 +375,7 @@ register_io register_control .tx_empty(tx_empty), //.debug_0(rx_a_a),.debug_1(ddc0_in_i), .debug_0(tx_debugbus),.debug_1(tx_debugbus), - .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,(tx_underrun == 0),rx_overrun,decim_rate}), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); io_pins io_pins -- cgit v1.2.3 From 83fcac4c30bdeaba5e67f4ab778df2fb839ade01 Mon Sep 17 00:00:00 2001 From: eb Date: Tue, 9 Oct 2007 20:09:04 +0000 Subject: New rbfs built from r6602 using Quartus II Web Edition version 7.1 SP1 git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6603 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 180657 -> 181070 bytes rbf/rev2/std_4rx_0tx.rbf | Bin 182928 -> 185032 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 180657 -> 181070 bytes rbf/rev4/std_4rx_0tx.rbf | Bin 182928 -> 185032 bytes 4 files changed, 0 insertions(+), 0 deletions(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 71c301333..06d1a33fc 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev2/std_4rx_0tx.rbf b/rbf/rev2/std_4rx_0tx.rbf index 5404e608b..88573ebe6 100755 Binary files a/rbf/rev2/std_4rx_0tx.rbf and b/rbf/rev2/std_4rx_0tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 71c301333..06d1a33fc 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_4rx_0tx.rbf b/rbf/rev4/std_4rx_0tx.rbf index 5404e608b..88573ebe6 100755 Binary files a/rbf/rev4/std_4rx_0tx.rbf and b/rbf/rev4/std_4rx_0tx.rbf differ -- cgit v1.2.3 From 0b06bc618313444a547e45a2226f1f3b4630af21 Mon Sep 17 00:00:00 2001 From: eb Date: Tue, 9 Oct 2007 20:10:04 +0000 Subject: tool version changed git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6604 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std.qsf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index 14dbd30c2..269d3c8f8 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION 7.0 +set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1" # Pin & Location Assignments # ========================== -- cgit v1.2.3 From 346dedc208a9f39d16e9ec916770f21f766454ae Mon Sep 17 00:00:00 2001 From: jcorgan Date: Thu, 1 Nov 2007 03:29:36 +0000 Subject: Merged r6749:6763 from jcorgan/t179. Fixes ticket:179. New RBFs synthesized with 7.1SP1. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6764 221aa14e-8319-0410-a670-987f0aec2ac5 --- megacells/fifo_4k_18.v | 186 ++++++++++++++++++++++++++++++++++++++ models/fifo.v | 3 +- models/fifo_4k_18.v | 26 ++++++ rbf/rev2/std_2rxhb_2tx.rbf | Bin 181070 -> 181358 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 181070 -> 181358 bytes sdr_lib/tx_buffer.v | 198 ++++++++++++++++++++++++----------------- toplevel/usrp_std/usrp_std.qsf | 2 +- toplevel/usrp_std/usrp_std.v | 18 ++-- 8 files changed, 339 insertions(+), 94 deletions(-) create mode 100755 megacells/fifo_4k_18.v create mode 100644 models/fifo_4k_18.v diff --git a/megacells/fifo_4k_18.v b/megacells/fifo_4k_18.v new file mode 100755 index 000000000..ad76121bb --- /dev/null +++ b/megacells/fifo_4k_18.v @@ -0,0 +1,186 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4k_18.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2007 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_4k_18 ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdusedw, + wrfull, + wrusedw); + + input aclr; + input [17:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [17:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + + wire sub_wire0; + wire [11:0] sub_wire1; + wire sub_wire2; + wire [17:0] sub_wire3; + wire [11:0] sub_wire4; + wire rdempty = sub_wire0; + wire [11:0] wrusedw = sub_wire1[11:0]; + wire wrfull = sub_wire2; + wire [17:0] q = sub_wire3[17:0]; + wire [11:0] rdusedw = sub_wire4[11:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4) + // synopsys translate_off + , + .rdfull (), + .wrempty () + // synopsys translate_on + ); + defparam + dcfifo_component.add_ram_output_register = "OFF", + dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone", + dcfifo_component.lpm_numwords = 4096, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 18, + dcfifo_component.lpm_widthu = 12, + dcfifo_component.overflow_checking = "OFF", + dcfifo_component.underflow_checking = "OFF", + dcfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "18" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "18" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0] +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/models/fifo.v b/models/fifo.v index a04e7da6c..0ade49e9c 100644 --- a/models/fifo.v +++ b/models/fifo.v @@ -77,5 +77,6 @@ module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q, assign rdempty = (rdusedw == 0); assign rdfull = (rdusedw == depth-1); -endmodule // fifo_1c_1k +endmodule // fifo + diff --git a/models/fifo_4k_18.v b/models/fifo_4k_18.v new file mode 100644 index 000000000..3efbf74f0 --- /dev/null +++ b/models/fifo_4k_18.v @@ -0,0 +1,26 @@ + + +module fifo_4k_18 + (input [17:0] data, + input wrreq, + input wrclk, + output wrfull, + output wrempty, + output [11:0] wrusedw, + + output [17:0] q, + input rdreq, + input rdclk, + output rdfull, + output rdempty, + output [11:0] rdusedw, + + input aclr ); + +fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k + ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, + rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); + +endmodule // fifo_4k_18 + + diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 06d1a33fc..32c931b52 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 06d1a33fc..32c931b52 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/sdr_lib/tx_buffer.v b/sdr_lib/tx_buffer.v index 63202c9df..58642229d 100644 --- a/sdr_lib/tx_buffer.v +++ b/sdr_lib/tx_buffer.v @@ -24,115 +24,147 @@ // Fifo has 1024 or 2048 lines module tx_buffer - ( input usbclk, + ( // USB Side + input usbclk, input bus_reset, // Used here for the 257-Hack to fix the FX2 bug - input reset, // standard DSP-side reset input [15:0] usbdata, input wire WR, - output wire have_space, + output reg have_space, output reg tx_underrun, + input clear_status, + + // DSP Side + input txclk, + input reset, // standard DSP-side reset input wire [3:0] channels, output reg [15:0] tx_i_0, output reg [15:0] tx_q_0, output reg [15:0] tx_i_1, output reg [15:0] tx_q_1, - output reg [15:0] tx_i_2, - output reg [15:0] tx_q_2, - output reg [15:0] tx_i_3, - output reg [15:0] tx_q_3, - input txclk, input txstrobe, - input clear_status, output wire tx_empty, - output [11:0] debugbus + output [31:0] debugbus ); - wire [11:0] txfifolevel; - reg [8:0] write_count; - wire tx_full; - wire [15:0] fifodata; - wire rdreq; - - reg [3:0] load_next; - - // DAC Side of FIFO - assign rdreq = ((load_next != channels) & !tx_empty); + wire [11:0] txfifolevel; + wire [15:0] fifodata; + wire rdreq; + reg [3:0] phase; + wire sop_f, iq_f; + reg sop; + + // USB Side of FIFO + reg [15:0] usbdata_reg; + reg wr_reg; + reg [8:0] write_count; + always @(posedge usbclk) + have_space <= (txfifolevel < (4092-256)); // be extra conservative + + always @(posedge usbclk) + begin + wr_reg <= WR; + usbdata_reg <= usbdata; + end + + always @(posedge usbclk) + if(bus_reset) + write_count <= 0; + else if(wr_reg) + write_count <= write_count + 1; + else + write_count <= 0; + + always @(posedge usbclk) + sop <= WR & ~wr_reg; // Edge detect + + // FIFO + fifo_4k_18 txfifo + ( // USB Write Side + .data ( {sop,write_count[0],usbdata_reg} ), + .wrreq ( wr_reg & ~write_count[8] ), + .wrclk ( usbclk ), + .wrfull ( ), + .wrempty ( ), + .wrusedw ( txfifolevel ), + // DSP Read Side + .q ( {sop_f, iq_f, fifodata} ), + .rdreq ( rdreq ), + .rdclk ( txclk ), + .rdfull ( ), + .rdempty ( tx_empty ), + .rdusedw ( ), + // Async, shared + .aclr ( reset ) ); + + // DAC Side of FIFO always @(posedge txclk) if(reset) begin - {tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3} - <= #1 128'h0; - load_next <= #1 4'd0; + {tx_i_0,tx_q_0,tx_i_1,tx_q_1} <= 64'h0; + phase <= 4'd0; + end + else if(phase == channels) + begin + if(txstrobe) + phase <= 4'd0; end else - if(load_next != channels) - begin - load_next <= #1 load_next + 4'd1; - case(load_next) - 4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata; - 4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata; - 4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata; - 4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata; - 4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata; - 4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata; - 4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata; - 4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata; - endcase // case(load_next) - end // if (load_next != channels) - else if(txstrobe & (load_next == channels)) + if(~tx_empty) begin - load_next <= #1 4'd0; + case(phase) + 4'd0 : tx_i_0 <= fifodata; + 4'd1 : tx_q_0 <= fifodata; + 4'd2 : tx_i_1 <= fifodata; + 4'd3 : tx_q_1 <= fifodata; + endcase // case(phase) + phase <= phase + 4'd1; end - - // USB Side of FIFO - assign have_space = (txfifolevel <= (4095-256)); + + assign rdreq = ((phase != channels) & ~tx_empty); + + // Detect Underruns, cross clock domains + reg clear_status_dsp, tx_underrun_dsp; + always @(posedge txclk) + clear_status_dsp <= clear_status; always @(posedge usbclk) - if(bus_reset) // Use bus reset because this is on usbclk - write_count <= #1 0; - else if(WR & ~write_count[8]) - write_count <= #1 write_count + 9'd1; - else - write_count <= #1 WR ? write_count : 9'b0; - - // Detect Underruns + tx_underrun <= tx_underrun_dsp; + always @(posedge txclk) if(reset) - tx_underrun <= 1'b0; - else if(txstrobe & (load_next != channels)) - tx_underrun <= 1'b1; - else if(clear_status) - tx_underrun <= 1'b0; + tx_underrun_dsp <= 1'b0; + else if(txstrobe & (phase != channels)) + tx_underrun_dsp <= 1'b1; + else if(clear_status_dsp) + tx_underrun_dsp <= 1'b0; - // FIFO - fifo_4k txfifo - ( .data ( usbdata ), - .wrreq ( WR & ~write_count[8] ), - .wrclk ( usbclk ), - - .q ( fifodata ), - .rdreq ( rdreq ), - .rdclk ( txclk ), - - .aclr ( reset ), // asynch, so we can use either - - .rdempty ( tx_empty ), - .rdusedw ( ), - .wrfull ( tx_full ), - .wrusedw ( txfifolevel ) - ); - - // Debugging Aids - assign debugbus[0] = WR; - assign debugbus[1] = have_space; - assign debugbus[2] = tx_empty; - assign debugbus[3] = tx_full; - assign debugbus[4] = tx_underrun; - assign debugbus[5] = write_count[8]; - assign debugbus[6] = txstrobe; - assign debugbus[7] = rdreq; - assign debugbus[11:8] = load_next; + // TX debug bus + // + // 15:0 txclk domain => TXA [15:0] + // 31:16 usbclk domain => RXA [15:0] + assign debugbus[0] = reset; + assign debugbus[1] = txstrobe; + assign debugbus[2] = rdreq; + assign debugbus[6:3] = phase; + assign debugbus[7] = tx_empty; + assign debugbus[8] = tx_underrun_dsp; + assign debugbus[9] = iq_f; + assign debugbus[10] = sop_f; + assign debugbus[14:11] = 0; + assign debugbus[15] = txclk; + + assign debugbus[16] = bus_reset; + assign debugbus[17] = WR; + assign debugbus[18] = wr_reg; + assign debugbus[19] = have_space; + assign debugbus[20] = write_count[8]; + assign debugbus[21] = write_count[0]; + assign debugbus[22] = sop; + assign debugbus[23] = tx_underrun; + assign debugbus[30:24] = 0; + assign debugbus[31] = usbclk; + endmodule // tx_buffer diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index 269d3c8f8..e0bac4893 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -370,6 +370,7 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v @@ -381,7 +382,6 @@ set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v index 870f43769..4b92cfb16 100644 --- a/toplevel/usrp_std/usrp_std.v +++ b/toplevel/usrp_std/usrp_std.v @@ -93,7 +93,8 @@ module usrp_std wire [2:0] tx_numchan; wire [7:0] interp_rate, decim_rate; - wire [15:0] tx_debugbus, rx_debugbus; + wire [15:0] rx_debugbus; + wire [31:0] tx_debugbus; wire enable_tx, enable_rx; wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; @@ -130,18 +131,17 @@ module usrp_std assign bb_tx_q1 = ch3tx; tx_buffer tx_buffer - ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), - .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), + ( .usbclk(usbclk), .bus_reset(tx_bus_reset), + .usbdata(usbdata),.WR(WR), .have_space(have_space), + .tx_underrun(tx_underrun), .clear_status(clear_status), + .txclk(clk64), .reset(tx_dsp_reset), .channels({tx_numchan,1'b0}), .tx_i_0(ch0tx),.tx_q_0(ch1tx), .tx_i_1(ch2tx),.tx_q_1(ch3tx), - .tx_i_2(),.tx_q_2(), - .tx_i_3(),.tx_q_3(), - .txclk(clk64),.txstrobe(strobe_interp), - .clear_status(clear_status), + .txstrobe(strobe_interp), .tx_empty(tx_empty), .debugbus(tx_debugbus) ); - + `ifdef TX_EN_0 tx_chain tx_chain_0 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), @@ -317,7 +317,7 @@ module usrp_std .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), .tx_empty(tx_empty), //.debug_0(rx_a_a),.debug_1(ddc0_in_i), - .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]), .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); -- cgit v1.2.3 From fe861a8b2281686ced4fa93f3742cd4983f3eb24 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Thu, 1 Nov 2007 23:56:59 +0000 Subject: Merged r6766:6775 from jcorgan/t195. Fixes ticket:195. NOTE: this removes 8 bit sample width support on receive. Synthesized with 7.1SP1. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6776 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 181358 -> 180944 bytes rbf/rev2/std_4rx_0tx.rbf | Bin 185032 -> 181726 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 181358 -> 180944 bytes rbf/rev4/std_4rx_0tx.rbf | Bin 185032 -> 181726 bytes sdr_lib/rx_buffer.v | 243 ++++++++++++++++++++++++++----------------- toplevel/usrp_std/usrp_std.v | 5 +- 6 files changed, 151 insertions(+), 97 deletions(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 32c931b52..072bd8dde 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev2/std_4rx_0tx.rbf b/rbf/rev2/std_4rx_0tx.rbf index 88573ebe6..43f901d31 100755 Binary files a/rbf/rev2/std_4rx_0tx.rbf and b/rbf/rev2/std_4rx_0tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 32c931b52..072bd8dde 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_4rx_0tx.rbf b/rbf/rev4/std_4rx_0tx.rbf index 88573ebe6..43f901d31 100755 Binary files a/rbf/rev4/std_4rx_0tx.rbf and b/rbf/rev4/std_4rx_0tx.rbf differ diff --git a/sdr_lib/rx_buffer.v b/sdr_lib/rx_buffer.v index ec5b8eefe..7c52925c9 100644 --- a/sdr_lib/rx_buffer.v +++ b/sdr_lib/rx_buffer.v @@ -20,21 +20,24 @@ // // Interface to Cypress FX2 bus -// A packet is 512 Bytes. Each fifo line is 2 bytes -// Fifo has 1024 or 2048 lines +// A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each `include "../../firmware/include/fpga_regs_common.v" `include "../../firmware/include/fpga_regs_standard.v" module rx_buffer - ( input usbclk, - input bus_reset, // Not used in RX - input reset, // DSP side reset (used here), do not reset registers - input reset_regs, //Only reset registers + ( // Read/USB side + input usbclk, + input bus_reset, output [15:0] usbdata, input RD, - output wire have_pkt_rdy, + output reg have_pkt_rdy, output reg rx_overrun, + input clear_status, + // Write/DSP side + input rxclk, + input reset, // DSP side reset (used here), do not reset registers + input rxstrobe, input wire [3:0] channels, input wire [15:0] ch_0, input wire [15:0] ch_1, @@ -44,139 +47,191 @@ module rx_buffer input wire [15:0] ch_5, input wire [15:0] ch_6, input wire [15:0] ch_7, - input rxclk, - input rxstrobe, - input clear_status, + // Settings, on rxclk also input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, - output [15:0] debugbus + input reset_regs, //Only reset registers + output [31:0] debugbus ); - - wire [15:0] fifodata, fifodata_8; - reg [15:0] fifodata_16; - wire [11:0] rxfifolevel; - wire rx_empty, rx_full; - - wire bypass_hb, want_q; - wire [4:0] bitwidth; - wire [3:0] bitshift; + wire [15:0] fifodata, fifodata_8; + reg [15:0] fifodata_16; + + wire [11:0] rxfifolevel; + wire rx_full; + + wire bypass_hb, want_q; + wire [4:0] bitwidth; + wire [3:0] bitshift; setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs), .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), .out({bypass_hb,want_q,bitwidth,bitshift})); - // Receive FIFO (ADC --> USB) + // USB Read Side of FIFO + always @(negedge usbclk) + have_pkt_rdy <= (rxfifolevel >= 256); // 257 Bug Fix - reg [8:0] read_count; + reg [8:0] read_count; always @(negedge usbclk) if(bus_reset) - read_count <= #1 9'd0; - else if(RD & ~read_count[8]) - read_count <= #1 read_count + 9'd1; + read_count <= 0; + else if(RD) + read_count <= read_count + 1; else - read_count <= #1 RD ? read_count : 9'b0; + read_count <= 0; - // Detect overrun + // FIFO + wire ch0_in, ch0_out, iq_out; + assign ch0_in = (phase == 1); + + fifo_4k_18 rxfifo + ( // DSP Write Side + .data ( {ch0_in, phase[0], fifodata} ), + .wrreq (~rx_full & (phase != 0)), + .wrclk ( rxclk ), + .wrfull ( rx_full ), + .wrempty ( ), + .wrusedw ( ), + // USB Read Side + .q ( {ch0_out,iq_out,usbdata} ), + .rdreq ( RD & ~read_count[8] ), + .rdclk ( ~usbclk ), + .rdfull ( ), + .rdempty ( ), + .rdusedw ( rxfifolevel ), + // Async, shared + .aclr ( reset ) ); + + // DSP Write Side of FIFO + reg [15:0] ch_0_reg; + reg [15:0] ch_1_reg; + reg [15:0] ch_2_reg; + reg [15:0] ch_3_reg; + reg [15:0] ch_4_reg; + reg [15:0] ch_5_reg; + reg [15:0] ch_6_reg; + reg [15:0] ch_7_reg; + always @(posedge rxclk) - if(reset) - rx_overrun <= 1'b0; - else if(rxstrobe & (store_next != 0)) - rx_overrun <= 1'b1; - else if(clear_status) - rx_overrun <= 1'b0; + if (rxstrobe) + begin + ch_0_reg <= ch_0; + ch_1_reg <= ch_1; + ch_2_reg <= ch_2; + ch_3_reg <= ch_3; + ch_4_reg <= ch_4; + ch_5_reg <= ch_5; + ch_6_reg <= ch_6; + ch_7_reg <= ch_7; + end - reg [3:0] store_next; + reg [3:0] phase; always @(posedge rxclk) if(reset) - store_next <= #1 4'd0; - else if(rxstrobe & (store_next == 0)) - store_next <= #1 4'd1; - else if(~rx_full & (store_next == channels)) - store_next <= #1 4'd0; - else if(~rx_full & (bitwidth == 5'd8) & (store_next == (channels>>1))) - store_next <= #1 4'd0; - else if(~rx_full & (store_next != 0)) - store_next <= #1 store_next + 4'd1; - + phase <= 4'd0; + else if(phase == 0) + begin + if(rxstrobe) + phase <= 4'd1; + end + else if(~rx_full) + if(phase == channels) + phase <= 4'd0; + else + phase <= phase + 4'd1; + assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16; - + assign fifodata_8 = {round_8(top),round_8(bottom)}; reg [15:0] top,bottom; - + function [7:0] round_8; input [15:0] in_val; - + round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]); endfunction // round_8 always @* - case(store_next) + case(phase) 4'd1 : begin - bottom = ch_0; - top = ch_1; + bottom = ch_0_reg; + top = ch_1_reg; end 4'd2 : begin - bottom = ch_2; - top = ch_3; + bottom = ch_2_reg; + top = ch_3_reg; end 4'd3 : begin - bottom = ch_4; - top = ch_5; + bottom = ch_4_reg; + top = ch_5_reg; end 4'd4 : begin - bottom = ch_6; - top = ch_7; + bottom = ch_6_reg; + top = ch_7_reg; end default : begin top = 16'hFFFF; bottom = 16'hFFFF; end - endcase // case(store_next) + endcase // case(phase) always @* - case(store_next) - 4'd1 : fifodata_16 = ch_0; - 4'd2 : fifodata_16 = ch_1; - 4'd3 : fifodata_16 = ch_2; - 4'd4 : fifodata_16 = ch_3; - 4'd5 : fifodata_16 = ch_4; - 4'd6 : fifodata_16 = ch_5; - 4'd7 : fifodata_16 = ch_6; - 4'd8 : fifodata_16 = ch_7; + case(phase) + 4'd1 : fifodata_16 = ch_0_reg; + 4'd2 : fifodata_16 = ch_1_reg; + 4'd3 : fifodata_16 = ch_2_reg; + 4'd4 : fifodata_16 = ch_3_reg; + 4'd5 : fifodata_16 = ch_4_reg; + 4'd6 : fifodata_16 = ch_5_reg; + 4'd7 : fifodata_16 = ch_6_reg; + 4'd8 : fifodata_16 = ch_7_reg; default : fifodata_16 = 16'hFFFF; - endcase // case(store_next) + endcase // case(phase) - fifo_4k rxfifo - ( .data ( fifodata ), - .wrreq (~rx_full & (store_next != 0)), - .wrclk ( rxclk ), + // Detect overrun + reg clear_status_dsp, rx_overrun_dsp; + always @(posedge rxclk) + clear_status_dsp <= clear_status; - .q ( usbdata ), - .rdreq ( RD & ~read_count[8] ), - .rdclk ( ~usbclk ), - - .aclr ( reset ), // This one is asynchronous, so we can use either reset - - .rdempty ( rx_empty ), - .rdusedw ( rxfifolevel ), - .wrfull ( rx_full ), - .wrusedw ( ) - ); + always @(negedge usbclk) + rx_overrun <= rx_overrun_dsp; + + always @(posedge rxclk) + if(reset) + rx_overrun_dsp <= 1'b0; + else if(rxstrobe & (phase != 0)) + rx_overrun_dsp <= 1'b1; + else if(clear_status_dsp) + rx_overrun_dsp <= 1'b0; + + // Debug bus + // + // 15:0 rxclk domain => TXA 15:0 + // 31:16 usbclk domain => RXA 15:0 - assign have_pkt_rdy = (rxfifolevel >= 256); + assign debugbus[0] = reset; + assign debugbus[1] = reset_regs; + assign debugbus[2] = rxstrobe; + assign debugbus[6:3] = channels; + assign debugbus[7] = rx_full; + assign debugbus[11:8] = phase; + assign debugbus[12] = ch0_in; + assign debugbus[13] = clear_status_dsp; + assign debugbus[14] = rx_overrun_dsp; + assign debugbus[15] = rxclk; - // Debugging Aids - assign debugbus[0] = RD; - assign debugbus[1] = rx_overrun; - assign debugbus[2] = read_count[8]; - assign debugbus[3] = rx_full; - assign debugbus[4] = rxstrobe; - assign debugbus[5] = usbclk; - assign debugbus[6] = have_pkt_rdy; - assign debugbus[10:7] = store_next; - //assign debugbus[15:11] = rxfifolevel[4:0]; - assign debugbus[15:11] = bitwidth; + assign debugbus[16] = bus_reset; + assign debugbus[17] = RD; + assign debugbus[18] = have_pkt_rdy; + assign debugbus[19] = rx_overrun; + assign debugbus[20] = read_count[0]; + assign debugbus[21] = read_count[8]; + assign debugbus[22] = ch0_out; + assign debugbus[23] = iq_out; + assign debugbus[24] = clear_status; + assign debugbus[30:25] = 0; + assign debugbus[31] = usbclk; endmodule // rx_buffer diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v index 4b92cfb16..8b29a9c21 100644 --- a/toplevel/usrp_std/usrp_std.v +++ b/toplevel/usrp_std/usrp_std.v @@ -93,8 +93,7 @@ module usrp_std wire [2:0] tx_numchan; wire [7:0] interp_rate, decim_rate; - wire [15:0] rx_debugbus; - wire [31:0] tx_debugbus; + wire [31:0] tx_debugbus, rx_debugbus; wire enable_tx, enable_rx; wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; @@ -318,7 +317,7 @@ module usrp_std .tx_empty(tx_empty), //.debug_0(rx_a_a),.debug_1(ddc0_in_i), .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]), - .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); io_pins io_pins -- cgit v1.2.3 From 881199a5cc09fc98ce34219426ff2dd76a3f25c7 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Thu, 1 Nov 2007 23:57:49 +0000 Subject: Regenerated USRP Makefile.extra git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6777 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.extra | 326 ++++++++++++++++++++++++++++++++------------------------- 1 file changed, 184 insertions(+), 142 deletions(-) diff --git a/Makefile.extra b/Makefile.extra index dc26413cc..8154e2eb0 100644 --- a/Makefile.extra +++ b/Makefile.extra @@ -1,142 +1,184 @@ -EXTRA_DIST = \ - gen_makefile_extra.py \ - megacells/accum32.bsf \ - megacells/accum32.cmp \ - megacells/accum32.inc \ - megacells/accum32.v \ - megacells/accum32_bb.v \ - megacells/accum32_inst.v \ - megacells/add32.bsf \ - megacells/add32.cmp \ - megacells/add32.inc \ - megacells/add32.v \ - megacells/add32_bb.v \ - megacells/add32_inst.v \ - megacells/addsub16.bsf \ - megacells/addsub16.cmp \ - megacells/addsub16.inc \ - megacells/addsub16.v \ - megacells/addsub16_bb.v \ - megacells/addsub16_inst.v \ - megacells/bustri.bsf \ - megacells/bustri.cmp \ - megacells/bustri.inc \ - megacells/bustri.v \ - megacells/bustri_bb.v \ - megacells/bustri_inst.v \ - megacells/clk_doubler.v \ - megacells/clk_doubler_bb.v \ - megacells/dspclkpll.v \ - megacells/dspclkpll_bb.v \ - megacells/fifo_2k.v \ - megacells/fifo_2k_bb.v \ - megacells/fifo_4k.v \ - megacells/fifo_4k_bb.v \ - megacells/mylpm_addsub.bsf \ - megacells/mylpm_addsub.cmp \ - megacells/mylpm_addsub.inc \ - megacells/mylpm_addsub.v \ - megacells/mylpm_addsub_bb.v \ - megacells/mylpm_addsub_inst.v \ - megacells/pll.v \ - megacells/pll_bb.v \ - megacells/pll_inst.v \ - megacells/sub32.bsf \ - megacells/sub32.cmp \ - megacells/sub32.inc \ - megacells/sub32.v \ - megacells/sub32_bb.v \ - megacells/sub32_inst.v \ - models/bustri.v \ - models/fifo.v \ - models/fifo_1c_1k.v \ - models/fifo_1c_2k.v \ - models/fifo_1c_4k.v \ - models/fifo_1k.v \ - models/fifo_2k.v \ - models/fifo_4k.v \ - models/pll.v \ - models/ssram.v \ - sdr_lib/adc_interface.v \ - sdr_lib/bidir_reg.v \ - sdr_lib/cic_decim.v \ - sdr_lib/cic_int_shifter.v \ - sdr_lib/cic_interp.v \ - sdr_lib/clk_divider.v \ - sdr_lib/cordic.v \ - sdr_lib/cordic_stage.v \ - sdr_lib/ddc.v \ - sdr_lib/dpram.v \ - sdr_lib/duc.v \ - sdr_lib/ext_fifo.v \ - sdr_lib/gen_cordic_consts.py \ - sdr_lib/gen_sync.v \ - sdr_lib/hb/acc.v \ - sdr_lib/hb/coeff_rom.v \ - sdr_lib/hb/halfband_decim.v \ - sdr_lib/hb/halfband_interp.v \ - sdr_lib/hb/hbd_tb/test_hbd.v \ - sdr_lib/hb/mac.v \ - sdr_lib/hb/mult.v \ - sdr_lib/hb/ram16_2port.v \ - sdr_lib/hb/ram16_2sum.v \ - sdr_lib/hb/ram32_2sum.v \ - sdr_lib/io_pins.v \ - sdr_lib/master_control.v \ - sdr_lib/master_control_multi.v \ - sdr_lib/phase_acc.v \ - sdr_lib/ram.v \ - sdr_lib/ram16.v \ - sdr_lib/ram32.v \ - sdr_lib/ram64.v \ - sdr_lib/rssi.v \ - sdr_lib/rx_buffer.v \ - sdr_lib/rx_chain.v \ - sdr_lib/rx_chain_dual.v \ - sdr_lib/rx_dcoffset.v \ - sdr_lib/serial_io.v \ - sdr_lib/setting_reg.v \ - sdr_lib/setting_reg_masked.v \ - sdr_lib/sign_extend.v \ - sdr_lib/strobe_gen.v \ - sdr_lib/tx_buffer.v \ - sdr_lib/tx_chain.v \ - sdr_lib/tx_chain_hb.v \ - tb/cbus_tb.v \ - tb/cordic_tb.v \ - tb/decim_tb.v \ - tb/fullchip_tb.v \ - tb/interp_tb.v \ - tb/justinterp_tb.v \ - tb/usrp_tasks.v \ - toplevel/mrfm/biquad_2stage.v \ - toplevel/mrfm/biquad_6stage.v \ - toplevel/mrfm/mrfm.csf \ - toplevel/mrfm/mrfm.esf \ - toplevel/mrfm/mrfm.psf \ - toplevel/mrfm/mrfm.py \ - toplevel/mrfm/mrfm.qpf \ - toplevel/mrfm/mrfm.qsf \ - toplevel/mrfm/mrfm.v \ - toplevel/mrfm/mrfm.vh \ - toplevel/mrfm/mrfm_compensator.v \ - toplevel/mrfm/mrfm_fft.py \ - toplevel/mrfm/mrfm_proc.v \ - toplevel/mrfm/shifter.v \ - toplevel/sizetest/sizetest.csf \ - toplevel/sizetest/sizetest.psf \ - toplevel/sizetest/sizetest.v \ - toplevel/usrp_multi/usrp_multi.csf \ - toplevel/usrp_multi/usrp_multi.esf \ - toplevel/usrp_multi/usrp_multi.psf \ - toplevel/usrp_multi/usrp_multi.qpf \ - toplevel/usrp_multi/usrp_multi.qsf \ - toplevel/usrp_multi/usrp_multi.v \ - toplevel/usrp_multi/config.vh \ - toplevel/usrp_std/usrp_std.csf \ - toplevel/usrp_std/usrp_std.esf \ - toplevel/usrp_std/usrp_std.psf \ - toplevel/usrp_std/usrp_std.qpf \ - toplevel/usrp_std/usrp_std.qsf \ - toplevel/usrp_std/usrp_std.v \ - toplevel/usrp_std/config.vh +EXTRA_DIST = \ + gen_makefile_extra.py \ + inband_lib/chan_fifo_reader.v \ + inband_lib/channel_demux.v \ + inband_lib/channel_ram.v \ + inband_lib/cmd_reader.v \ + inband_lib/data_packet_fifo.v \ + inband_lib/packet_builder.v \ + inband_lib/register_io.v \ + inband_lib/rx_buffer_inband.v \ + inband_lib/tx_buffer_inband.v \ + inband_lib/tx_packer.v \ + inband_lib/usb_fifo_reader.v \ + inband_lib/usb_fifo_writer.v \ + inband_lib/usb_packet_fifo.v \ + megacells/accum32.bsf \ + megacells/accum32.cmp \ + megacells/accum32.inc \ + megacells/accum32.v \ + megacells/accum32_bb.v \ + megacells/accum32_inst.v \ + megacells/add32.bsf \ + megacells/add32.cmp \ + megacells/add32.inc \ + megacells/add32.v \ + megacells/add32_bb.v \ + megacells/add32_inst.v \ + megacells/addsub16.bsf \ + megacells/addsub16.cmp \ + megacells/addsub16.inc \ + megacells/addsub16.v \ + megacells/addsub16_bb.v \ + megacells/addsub16_inst.v \ + megacells/bustri.bsf \ + megacells/bustri.cmp \ + megacells/bustri.inc \ + megacells/bustri.v \ + megacells/bustri_bb.v \ + megacells/bustri_inst.v \ + megacells/clk_doubler.v \ + megacells/clk_doubler_bb.v \ + megacells/dspclkpll.v \ + megacells/dspclkpll_bb.v \ + megacells/fifo_1kx16.bsf \ + megacells/fifo_1kx16.cmp \ + megacells/fifo_1kx16.inc \ + megacells/fifo_1kx16.v \ + megacells/fifo_1kx16_bb.v \ + megacells/fifo_1kx16_inst.v \ + megacells/fifo_2k.v \ + megacells/fifo_2k_bb.v \ + megacells/fifo_4k.v \ + megacells/fifo_4k_18.v \ + megacells/fifo_4k_bb.v \ + megacells/fifo_4kx16_dc.bsf \ + megacells/fifo_4kx16_dc.cmp \ + megacells/fifo_4kx16_dc.inc \ + megacells/fifo_4kx16_dc.v \ + megacells/fifo_4kx16_dc_bb.v \ + megacells/fifo_4kx16_dc_inst.v \ + megacells/mylpm_addsub.bsf \ + megacells/mylpm_addsub.cmp \ + megacells/mylpm_addsub.inc \ + megacells/mylpm_addsub.v \ + megacells/mylpm_addsub_bb.v \ + megacells/mylpm_addsub_inst.v \ + megacells/pll.v \ + megacells/pll_bb.v \ + megacells/pll_inst.v \ + megacells/sub32.bsf \ + megacells/sub32.cmp \ + megacells/sub32.inc \ + megacells/sub32.v \ + megacells/sub32_bb.v \ + megacells/sub32_inst.v \ + models/bustri.v \ + models/fifo.v \ + models/fifo_1c_1k.v \ + models/fifo_1c_2k.v \ + models/fifo_1c_4k.v \ + models/fifo_1k.v \ + models/fifo_2k.v \ + models/fifo_4k.v \ + models/fifo_4k_18.v \ + models/pll.v \ + models/ssram.v \ + sdr_lib/adc_interface.v \ + sdr_lib/atr_delay.v \ + sdr_lib/bidir_reg.v \ + sdr_lib/cic_dec_shifter.v \ + sdr_lib/cic_decim.v \ + sdr_lib/cic_int_shifter.v \ + sdr_lib/cic_interp.v \ + sdr_lib/clk_divider.v \ + sdr_lib/cordic.v \ + sdr_lib/cordic_stage.v \ + sdr_lib/ddc.v \ + sdr_lib/dpram.v \ + sdr_lib/duc.v \ + sdr_lib/ext_fifo.v \ + sdr_lib/gen_cordic_consts.py \ + sdr_lib/gen_sync.v \ + sdr_lib/hb/acc.v \ + sdr_lib/hb/coeff_rom.v \ + sdr_lib/hb/halfband_decim.v \ + sdr_lib/hb/halfband_interp.v \ + sdr_lib/hb/hbd_tb/test_hbd.v \ + sdr_lib/hb/mac.v \ + sdr_lib/hb/mult.v \ + sdr_lib/hb/ram16_2port.v \ + sdr_lib/hb/ram16_2sum.v \ + sdr_lib/hb/ram32_2sum.v \ + sdr_lib/io_pins.v \ + sdr_lib/master_control.v \ + sdr_lib/master_control_multi.v \ + sdr_lib/phase_acc.v \ + sdr_lib/ram.v \ + sdr_lib/ram16.v \ + sdr_lib/ram32.v \ + sdr_lib/ram64.v \ + sdr_lib/rssi.v \ + sdr_lib/rx_buffer.v \ + sdr_lib/rx_chain.v \ + sdr_lib/rx_chain_dual.v \ + sdr_lib/rx_dcoffset.v \ + sdr_lib/serial_io.v \ + sdr_lib/setting_reg.v \ + sdr_lib/setting_reg_masked.v \ + sdr_lib/sign_extend.v \ + sdr_lib/strobe_gen.v \ + sdr_lib/tx_buffer.v \ + sdr_lib/tx_chain.v \ + sdr_lib/tx_chain_hb.v \ + tb/cbus_tb.v \ + tb/cordic_tb.v \ + tb/decim_tb.v \ + tb/fullchip_tb.v \ + tb/interp_tb.v \ + tb/justinterp_tb.v \ + tb/usrp_tasks.v \ + toplevel/include/common_config_1rxhb_1tx.vh \ + toplevel/include/common_config_2rx_0tx.vh \ + toplevel/include/common_config_2rxhb_0tx.vh \ + toplevel/include/common_config_2rxhb_2tx.vh \ + toplevel/include/common_config_4rx_0tx.vh \ + toplevel/include/common_config_bottom.vh \ + toplevel/mrfm/biquad_2stage.v \ + toplevel/mrfm/biquad_6stage.v \ + toplevel/mrfm/mrfm.csf \ + toplevel/mrfm/mrfm.esf \ + toplevel/mrfm/mrfm.psf \ + toplevel/mrfm/mrfm.py \ + toplevel/mrfm/mrfm.qpf \ + toplevel/mrfm/mrfm.qsf \ + toplevel/mrfm/mrfm.v \ + toplevel/mrfm/mrfm.vh \ + toplevel/mrfm/mrfm_compensator.v \ + toplevel/mrfm/mrfm_fft.py \ + toplevel/mrfm/mrfm_proc.v \ + toplevel/mrfm/shifter.v \ + toplevel/sizetest/sizetest.csf \ + toplevel/sizetest/sizetest.psf \ + toplevel/sizetest/sizetest.v \ + toplevel/usrp_inband_usb/config.vh \ + toplevel/usrp_inband_usb/usrp_inband_usb.csf \ + toplevel/usrp_inband_usb/usrp_inband_usb.esf \ + toplevel/usrp_inband_usb/usrp_inband_usb.psf \ + toplevel/usrp_inband_usb/usrp_inband_usb.qpf \ + toplevel/usrp_inband_usb/usrp_inband_usb.qsf \ + toplevel/usrp_inband_usb/usrp_inband_usb.v \ + toplevel/usrp_multi/config.vh \ + toplevel/usrp_multi/usrp_multi.csf \ + toplevel/usrp_multi/usrp_multi.esf \ + toplevel/usrp_multi/usrp_multi.psf \ + toplevel/usrp_multi/usrp_multi.qpf \ + toplevel/usrp_multi/usrp_multi.qsf \ + toplevel/usrp_multi/usrp_multi.v \ + toplevel/usrp_std/config.vh \ + toplevel/usrp_std/usrp_std.csf \ + toplevel/usrp_std/usrp_std.esf \ + toplevel/usrp_std/usrp_std.psf \ + toplevel/usrp_std/usrp_std.qpf \ + toplevel/usrp_std/usrp_std.qsf \ + toplevel/usrp_std/usrp_std.v -- cgit v1.2.3 From 78452721f53679ce8f1c70defc9a4b93ccf69b92 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Sat, 10 Nov 2007 19:23:57 +0000 Subject: Restores 8-bit sample format support to FPGA code. Synthesized with 7.1SP1. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6858 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 180944 -> 181148 bytes rbf/rev2/std_4rx_0tx.rbf | Bin 181726 -> 183046 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 180944 -> 181148 bytes rbf/rev4/std_4rx_0tx.rbf | Bin 181726 -> 183046 bytes sdr_lib/rx_buffer.v | 2 +- 5 files changed, 1 insertion(+), 1 deletion(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index 072bd8dde..f09848704 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev2/std_4rx_0tx.rbf b/rbf/rev2/std_4rx_0tx.rbf index 43f901d31..1deca9517 100755 Binary files a/rbf/rev2/std_4rx_0tx.rbf and b/rbf/rev2/std_4rx_0tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index 072bd8dde..f09848704 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_4rx_0tx.rbf b/rbf/rev4/std_4rx_0tx.rbf index 43f901d31..1deca9517 100755 Binary files a/rbf/rev4/std_4rx_0tx.rbf and b/rbf/rev4/std_4rx_0tx.rbf differ diff --git a/sdr_lib/rx_buffer.v b/sdr_lib/rx_buffer.v index 7c52925c9..d17294b98 100644 --- a/sdr_lib/rx_buffer.v +++ b/sdr_lib/rx_buffer.v @@ -136,7 +136,7 @@ module rx_buffer phase <= 4'd1; end else if(~rx_full) - if(phase == channels) + if(phase == ((bitwidth == 5'd8) ? (channels>>1) : channels)) phase <= 4'd0; else phase <= phase + 4'd1; -- cgit v1.2.3 From 4a2d8bec69cef42bedece7c0f2ada64829c8eab2 Mon Sep 17 00:00:00 2001 From: eb Date: Wed, 30 Apr 2008 03:52:31 +0000 Subject: Merged features/inband-usb -r6431:8293 into trunk. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@8295 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.extra | 3 - inband_lib/chan_fifo_reader.v | 262 ++++++------- inband_lib/channel_demux.v | 38 +- inband_lib/channel_ram.v | 175 ++++----- inband_lib/cmd_reader.v | 565 ++++++++++++++------------- inband_lib/data_packet_fifo.v | 118 ------ inband_lib/packet_builder.v | 84 ++-- inband_lib/register_io.v | 94 +++-- inband_lib/rx_buffer_inband.v | 388 +++++++++--------- inband_lib/tx_buffer_inband.v | 305 ++++++--------- inband_lib/usb_fifo_reader.v | 25 -- inband_lib/usb_fifo_writer.v | 183 --------- megacells/fifo_1kx16.bsf | 2 +- megacells/fifo_1kx16.v | 6 +- megacells/fifo_1kx16_bb.v | 4 +- rbf/Makefile.am | 4 + rbf/rev2/inband_1rxhb_1tx.rbf | Bin 0 -> 161180 bytes rbf/rev2/inband_2rxhb_2tx.rbf | Bin 0 -> 191849 bytes rbf/rev4/inband_1rxhb_1tx.rbf | Bin 0 -> 161180 bytes rbf/rev4/inband_2rxhb_2tx.rbf | Bin 0 -> 191849 bytes toplevel/usrp_inband_usb/config.vh | 2 +- toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 7 +- toplevel/usrp_inband_usb/usrp_inband_usb.v | 81 ++-- 23 files changed, 1021 insertions(+), 1325 deletions(-) delete mode 100755 inband_lib/data_packet_fifo.v delete mode 100755 inband_lib/usb_fifo_reader.v delete mode 100755 inband_lib/usb_fifo_writer.v create mode 100755 rbf/rev2/inband_1rxhb_1tx.rbf create mode 100755 rbf/rev2/inband_2rxhb_2tx.rbf create mode 100755 rbf/rev4/inband_1rxhb_1tx.rbf create mode 100755 rbf/rev4/inband_2rxhb_2tx.rbf diff --git a/Makefile.extra b/Makefile.extra index 8154e2eb0..56df23c98 100644 --- a/Makefile.extra +++ b/Makefile.extra @@ -4,14 +4,11 @@ EXTRA_DIST = \ inband_lib/channel_demux.v \ inband_lib/channel_ram.v \ inband_lib/cmd_reader.v \ - inband_lib/data_packet_fifo.v \ inband_lib/packet_builder.v \ inband_lib/register_io.v \ inband_lib/rx_buffer_inband.v \ inband_lib/tx_buffer_inband.v \ inband_lib/tx_packer.v \ - inband_lib/usb_fifo_reader.v \ - inband_lib/usb_fifo_writer.v \ inband_lib/usb_packet_fifo.v \ megacells/accum32.bsf \ megacells/accum32.cmp \ diff --git a/inband_lib/chan_fifo_reader.v b/inband_lib/chan_fifo_reader.v index a6edf2c60..69da9ec5a 100755 --- a/inband_lib/chan_fifo_reader.v +++ b/inband_lib/chan_fifo_reader.v @@ -1,106 +1,102 @@ module chan_fifo_reader - ( reset, tx_clock, tx_strobe, adc_time, samples_format, + (reset, tx_clock, tx_strobe, timestamp_clock, samples_format, fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i, underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ; - input wire reset ; - input wire tx_clock ; - input wire tx_strobe ; //signal to output tx_i and tx_q - input wire [31:0] adc_time ; //current time - input wire [3:0] samples_format ;// not useful at this point - input wire [31:0] fifodata ; //the data input - input wire pkt_waiting ; //signal the next packet is ready - output reg rdreq ; //actually an ack to the current fifodata - output reg skip ; //finish reading current packet - output reg [15:0] tx_q ; //top 16 bit output of fifodata - output reg [15:0] tx_i ; //bottom 16 bit output of fifodata - output reg underrun ; - output reg tx_empty ; //cause 0 to be the output - input wire [31:0] rssi; - input wire [31:0] threshhold; - input wire [31:0] rssi_wait; + input wire reset ; + input wire tx_clock ; + input wire tx_strobe ; //signal to output tx_i and tx_q + input wire [31:0] timestamp_clock ; //current time + input wire [3:0] samples_format ;// not useful at this point + input wire [31:0] fifodata ; //the data input + input wire pkt_waiting ; //signal the next packet is ready + output reg rdreq ; //actually an ack to the current fifodata + output reg skip ; //finish reading current packet + output reg [15:0] tx_q ; //top 16 bit output of fifodata + output reg [15:0] tx_i ; //bottom 16 bit output of fifodata + output reg underrun ; + output reg tx_empty ; //cause 0 to be the output + input wire [31:0] rssi; + input wire [31:0] threshhold; + input wire [31:0] rssi_wait; - output wire [14:0] debug; - assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]}; - // Should not be needed if adc clock rate < tx clock rate - // Used only to debug - `define JITTER 5 - - //Samples format - // 16 bits interleaved complex samples - `define QI16 4'b0 + output wire [14:0] debug; + assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock}; + + //Samples format + // 16 bits interleaved complex samples + `define QI16 4'b0 - // States - parameter IDLE = 3'd0; - parameter HEADER = 3'd1; - parameter TIMESTAMP = 3'd2; - parameter WAIT = 3'd3; - parameter WAITSTROBE = 3'd4; - parameter SEND = 3'd5; + // States + parameter IDLE = 3'd0; + parameter HEADER = 3'd1; + parameter TIMESTAMP = 3'd2; + parameter WAIT = 3'd3; + parameter WAITSTROBE = 3'd4; + parameter SEND = 3'd5; - // Header format - `define PAYLOAD 8:2 - `define ENDOFBURST 27 - `define STARTOFBURST 28 - `define RSSI_FLAG 26 + // Header format + `define PAYLOAD 8:2 + `define ENDOFBURST 27 + `define STARTOFBURST 28 + `define RSSI_FLAG 26 - /* State registers */ - reg [2:0] reader_state; - /* Local registers */ - reg [6:0] payload_len; - reg [6:0] read_len; - reg [31:0] timestamp; - reg burst; - reg trash; - reg rssi_flag; - reg [31:0] time_wait; + /* State registers */ + reg [2:0] reader_state; + /* Local registers */ + reg [6:0] payload_len; + reg [6:0] read_len; + reg [31:0] timestamp; + reg burst; + reg trash; + reg rssi_flag; + reg [31:0] time_wait; - always @(posedge tx_clock) - begin - if (reset) - begin - reader_state <= IDLE; - rdreq <= 0; - skip <= 0; - underrun <= 0; - burst <= 0; - tx_empty <= 1; - tx_q <= 0; - tx_i <= 0; - trash <= 0; - rssi_flag <= 0; - time_wait <= 0; + always @(posedge tx_clock) + begin + if (reset) + begin + reader_state <= IDLE; + rdreq <= 0; + skip <= 0; + underrun <= 0; + burst <= 0; + tx_empty <= 1; + tx_q <= 0; + tx_i <= 0; + trash <= 0; + rssi_flag <= 0; + time_wait <= 0; end else - begin + begin case (reader_state) - IDLE: + IDLE: begin - /* - * reset all the variables and wait for a tx_strobe - * it is assumed that the ram connected to this fifo_reader - * is a short hand fifo meaning that the header to the next packet - * is already available to this fifo_reader when pkt_waiting is on - */ - skip <=0; - time_wait <= 0; - if (pkt_waiting == 1) - begin - reader_state <= HEADER; - rdreq <= 1; - underrun <= 0; - end - if (burst == 1 && pkt_waiting == 0) - underrun <= 1; - - if (tx_strobe == 1) - tx_empty <= 1 ; + /* + * reset all the variables and wait for a tx_strobe + * it is assumed that the ram connected to this fifo_reader + * is a short hand fifo meaning that the header to the next packet + * is already available to this fifo_reader when pkt_waiting is on + */ + skip <=0; + time_wait <= 0; + if (pkt_waiting == 1) + begin + reader_state <= HEADER; + rdreq <= 1; + underrun <= 0; + end + if (burst == 1 && pkt_waiting == 0) + underrun <= 1; + if (tx_strobe == 1) + tx_empty <= 1 ; end - /* Process header */ + /* Process header */ HEADER: - begin + begin if (tx_strobe == 1) tx_empty <= 1 ; @@ -114,68 +110,64 @@ module chan_fifo_reader else if (fifodata[`ENDOFBURST] == 1) burst <= 0; - if (trash == 1 && fifodata[`STARTOFBURST] == 0) - begin - skip <= 1; - reader_state <= IDLE; - rdreq <= 0; - end - else - begin - payload_len <= fifodata[`PAYLOAD] ; - read_len <= 0; - rdreq <= 1; - reader_state <= TIMESTAMP; - end - end + if (trash == 1 && fifodata[`STARTOFBURST] == 0) + begin + skip <= 1; + reader_state <= IDLE; + rdreq <= 0; + end + else + begin + payload_len <= fifodata[`PAYLOAD] ; + read_len <= 0; + rdreq <= 1; + reader_state <= TIMESTAMP; + end + end TIMESTAMP: - begin + begin timestamp <= fifodata; reader_state <= WAIT; if (tx_strobe == 1) tx_empty <= 1 ; rdreq <= 0; - end + end - // Decide if we wait, send or discard samples + // Decide if we wait, send or discard samples WAIT: - begin + begin if (tx_strobe == 1) tx_empty <= 1 ; time_wait <= time_wait + 32'd1; - // Outdated - if ((timestamp < adc_time) || - (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag)) + // Outdated + if ((timestamp < timestamp_clock) || + (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag)) begin - trash <= 1; - reader_state <= IDLE; - skip <= 1; + trash <= 1; + reader_state <= IDLE; + skip <= 1; end // Let's send it - else if ((timestamp <= adc_time + `JITTER - && timestamp > adc_time) + else if (timestamp == timestamp_clock || timestamp == 32'hFFFFFFFF) - begin - if (rssi <= threshhold || rssi_flag == 0) - begin - trash <= 0; - reader_state <= WAITSTROBE; - end - else - reader_state <= WAIT; - end - else - reader_state <= WAIT; - // Wait a little bit more - //else if (timestamp > adc_time + `JITTER) - // reader_state <= WAIT; - end + begin + if (rssi <= threshhold || rssi_flag == 0) + begin + trash <= 0; + reader_state <= WAITSTROBE; + end + else + reader_state <= WAIT; + end + else + reader_state <= WAIT; + end // Wait for the transmit chain to be ready WAITSTROBE: - begin + begin // If end of payload... if (read_len == payload_len) begin @@ -189,11 +181,11 @@ module chan_fifo_reader reader_state <= SEND; rdreq <= 1; end - end + end - // Send the samples to the tx_chain + // Send the samples to the tx_chain SEND: - begin + begin reader_state <= WAITSTROBE; read_len <= read_len + 7'd1; tx_empty <= 0; @@ -213,13 +205,13 @@ module chan_fifo_reader tx_q <= fifodata[31:16]; end endcase - end + end default: - begin - //error handling + begin + //error handling reader_state <= IDLE; - end + end endcase end end diff --git a/inband_lib/channel_demux.v b/inband_lib/channel_demux.v index d46be9397..cca5cdb65 100644 --- a/inband_lib/channel_demux.v +++ b/inband_lib/channel_demux.v @@ -1,24 +1,24 @@ module channel_demux - #(parameter NUM_CHAN = 2, parameter CHAN_WIDTH = 2) ( //usb Side - input [31:0]usbdata_final, - input WR_final, - - // TX Side - input reset, - input txclk, - output reg [CHAN_WIDTH:0] WR_channel, - output reg [31:0] ram_data, - output reg [CHAN_WIDTH:0] WR_done_channel ); -/* Parse header and forward to ram */ - reg [2:0]reader_state; - reg [4:0]channel ; - reg [6:0]read_length ; + #(parameter NUM_CHAN = 2) ( //usb Side + input [31:0]usbdata_final, + input WR_final, + // TX Side + input reset, + input txclk, + output reg [NUM_CHAN:0] WR_channel, + output reg [31:0] ram_data, + output reg [NUM_CHAN:0] WR_done_channel ); + /* Parse header and forward to ram */ + + reg [2:0]reader_state; + reg [4:0]channel ; + reg [6:0]read_length ; // States - parameter IDLE = 3'd0; - parameter HEADER = 3'd1; - parameter WAIT = 3'd2; - parameter FORWARD = 3'd3; + parameter IDLE = 3'd0; + parameter HEADER = 3'd1; + parameter WAIT = 3'd2; + parameter FORWARD = 3'd3; `define CHANNEL 20:16 `define PKT_SIZE 127 @@ -27,7 +27,7 @@ module channel_demux NUM_CHAN : (usbdata_final[`CHANNEL]); always @(posedge txclk) - begin + begin if (reset) begin reader_state <= IDLE; diff --git a/inband_lib/channel_ram.v b/inband_lib/channel_ram.v index 60450f02d..9621246c5 100755 --- a/inband_lib/channel_ram.v +++ b/inband_lib/channel_ram.v @@ -1,114 +1,107 @@ module channel_ram - ( // System - input txclk, - input reset, + ( // System + input txclk, input reset, + // USB side + input [31:0] datain, input WR, input WR_done, output have_space, + // Reader side + output [31:0] dataout, input RD, input RD_done, output packet_waiting); - // USB side - input [31:0] datain, - input WR, - input WR_done, - output have_space, - - // Reader side - output [31:0] dataout, - input RD, - input RD_done, - output packet_waiting); - - reg [6:0] wr_addr, rd_addr; - reg [1:0] which_ram_wr, which_ram_rd; - reg [2:0] nb_packets; + reg [6:0] wr_addr, rd_addr; + reg [1:0] which_ram_wr, which_ram_rd; + reg [2:0] nb_packets; - reg [31:0] ram0 [0:127]; - reg [31:0] ram1 [0:127]; - reg [31:0] ram2 [0:127]; - reg [31:0] ram3 [0:127]; + reg [31:0] ram0 [0:127]; + reg [31:0] ram1 [0:127]; + reg [31:0] ram2 [0:127]; + reg [31:0] ram3 [0:127]; - reg [31:0] dataout0; - reg [31:0] dataout1; - reg [31:0] dataout2; - reg [31:0] dataout3; + reg [31:0] dataout0; + reg [31:0] dataout1; + reg [31:0] dataout2; + reg [31:0] dataout3; - wire wr_done_int; - wire rd_done_int; - wire [6:0] rd_addr_final; - wire [1:0] which_ram_rd_final; + wire wr_done_int; + wire rd_done_int; + wire [6:0] rd_addr_final; + wire [1:0] which_ram_rd_final; - // USB side - always @(posedge txclk) - if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain; + // USB side + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain; - always @(posedge txclk) - if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain; + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain; - always @(posedge txclk) - if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain; + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain; - always @(posedge txclk) - if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain; + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain; assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done); - always @(posedge txclk) - if(reset) - wr_addr <= 0; - else if (WR_done) - wr_addr <= 0; - else if (WR) - wr_addr <= wr_addr + 7'd1; + always @(posedge txclk) + if(reset) + wr_addr <= 0; + else if (WR_done) + wr_addr <= 0; + else if (WR) + wr_addr <= wr_addr + 7'd1; - always @(posedge txclk) - if(reset) - which_ram_wr <= 0; - else if (wr_done_int) - which_ram_wr <= which_ram_wr + 2'd1; + always @(posedge txclk) + if(reset) + which_ram_wr <= 0; + else if (wr_done_int) + which_ram_wr <= which_ram_wr + 2'd1; - assign have_space = (nb_packets < 3'd3); + assign have_space = (nb_packets < 3'd3); - // Reader side - // short hand fifo - // rd_addr_final is what rd_addr is going to be next clock cycle - // which_ram_rd_final is what which_ram_rd is going to be next clock cycle - always @(posedge txclk) dataout0 <= ram0[rd_addr_final]; - always @(posedge txclk) dataout1 <= ram1[rd_addr_final]; - always @(posedge txclk) dataout2 <= ram2[rd_addr_final]; - always @(posedge txclk) dataout3 <= ram3[rd_addr_final]; + // Reader side + // short hand fifo + // rd_addr_final is what rd_addr is going to be next clock cycle + // which_ram_rd_final is what which_ram_rd is going to be next clock cycle + always @(posedge txclk) dataout0 <= ram0[rd_addr_final]; + always @(posedge txclk) dataout1 <= ram1[rd_addr_final]; + always @(posedge txclk) dataout2 <= ram2[rd_addr_final]; + always @(posedge txclk) dataout3 <= ram3[rd_addr_final]; - assign dataout = (which_ram_rd_final[1]) ? - (which_ram_rd_final[0] ? dataout3 : dataout2) : - (which_ram_rd_final[0] ? dataout1 : dataout0); + assign dataout = (which_ram_rd_final[1]) ? + (which_ram_rd_final[0] ? dataout3 : dataout2) : + (which_ram_rd_final[0] ? dataout1 : dataout0); - //RD_done is the only way to signal the end of one packet - assign rd_done_int = RD_done; + //RD_done is the only way to signal the end of one packet + assign rd_done_int = RD_done; - always @(posedge txclk) - if (reset) - rd_addr <= 0; - else if (RD_done) - rd_addr <= 0; - else if (RD) rd_addr <= rd_addr + 7'd1; + always @(posedge txclk) + if (reset) + rd_addr <= 0; + else if (RD_done) + rd_addr <= 0; + else if (RD) + rd_addr <= rd_addr + 7'd1; - assign rd_addr_final = (reset|RD_done) ? (6'd0) : - ((RD)?(rd_addr+7'd1):rd_addr); - always @(posedge txclk) - if (reset) - which_ram_rd <= 0; - else if (rd_done_int) - which_ram_rd <= which_ram_rd + 2'd1; + assign rd_addr_final = (reset|RD_done) ? (6'd0) : + ((RD)?(rd_addr+7'd1):rd_addr); + + always @(posedge txclk) + if (reset) + which_ram_rd <= 0; + else if (rd_done_int) + which_ram_rd <= which_ram_rd + 2'd1; - assign which_ram_rd_final = (reset) ? (2'd0): + assign which_ram_rd_final = (reset) ? (2'd0): ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd); - //packet_waiting is set to zero if rd_done_int is high - //because there is no guarantee that nb_packets will be pos. - //assign packet_waiting = (nb_packets != 0) & (~rd_done_int); - assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)); - always @(posedge txclk) - if (reset) - nb_packets <= 0; - else if (wr_done_int & ~rd_done_int) - nb_packets <= nb_packets + 3'd1; - else if (rd_done_int & ~wr_done_int) - nb_packets <= nb_packets - 3'd1; + //packet_waiting is set to zero if rd_done_int is high + //because there is no guarantee that nb_packets will be pos. + + assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)); + always @(posedge txclk) + if (reset) + nb_packets <= 0; + else if (wr_done_int & ~rd_done_int) + nb_packets <= nb_packets + 3'd1; + else if (rd_done_int & ~wr_done_int) + nb_packets <= nb_packets - 3'd1; -endmodule \ No newline at end of file +endmodule diff --git a/inband_lib/cmd_reader.v b/inband_lib/cmd_reader.v index 7604321e4..b69ea02b7 100755 --- a/inband_lib/cmd_reader.v +++ b/inband_lib/cmd_reader.v @@ -1,292 +1,305 @@ -module cmd_reader( - //System - input reset, - input txclk, - input [31:0] adc_time, - //FX2 Side - output reg skip, - output reg rdreq, - input [31:0] fifodata, - input pkt_waiting, - //Rx side - input rx_WR_enabled, - output reg [15:0] rx_databus, - output reg rx_WR, - output reg rx_WR_done, - //register io - input wire [31:0] reg_data_out, - output reg [31:0] reg_data_in, - output reg [6:0] reg_addr, - output reg [1:0] reg_io_enable, - output wire [14:0] debug - ); +module cmd_reader + (//System + input reset, input txclk, input [31:0] timestamp_clock, + //FX2 Side + output reg skip, output reg rdreq, + input [31:0] fifodata, input pkt_waiting, + //Rx side + input rx_WR_enabled, output reg [15:0] rx_databus, + output reg rx_WR, output reg rx_WR_done, + //register io + input wire [31:0] reg_data_out, output reg [31:0] reg_data_in, + output reg [6:0] reg_addr, output reg [1:0] reg_io_enable, + output wire [14:0] debug, output reg stop, output reg [15:0] stop_time); - // States - parameter IDLE = 4'd0; - parameter HEADER = 4'd1; - parameter TIMESTAMP = 4'd2; - parameter WAIT = 4'd3; - parameter TEST = 4'd4; - parameter SEND = 4'd5; - parameter PING = 4'd6; - parameter WRITE_REG = 4'd7; - parameter WRITE_REG_MASKED = 4'd8; - parameter READ_REG = 4'd9; - parameter DELAY = 4'd14; + // States + parameter IDLE = 4'd0; + parameter HEADER = 4'd1; + parameter TIMESTAMP = 4'd2; + parameter WAIT = 4'd3; + parameter TEST = 4'd4; + parameter SEND = 4'd5; + parameter PING = 4'd6; + parameter WRITE_REG = 4'd7; + parameter WRITE_REG_MASKED = 4'd8; + parameter READ_REG = 4'd9; + parameter DELAY = 4'd14; - `define OP_PING_FIXED 8'd0 - `define OP_PING_FIXED_REPLY 8'd1 - `define OP_WRITE_REG 8'd2 - `define OP_WRITE_REG_MASKED 8'd3 - `define OP_READ_REG 8'd4 - `define OP_READ_REG_REPLY 8'd5 - `define OP_DELAY 8'd12 + `define OP_PING_FIXED 8'd0 + `define OP_PING_FIXED_REPLY 8'd1 + `define OP_WRITE_REG 8'd2 + `define OP_WRITE_REG_MASKED 8'd3 + `define OP_READ_REG 8'd4 + `define OP_READ_REG_REPLY 8'd5 + `define OP_DELAY 8'd12 - reg [6:0] payload; - reg [6:0] payload_read; - reg [3:0] state; - reg [15:0] high; - reg [15:0] low; - reg pending; - reg [31:0] value0; - reg [31:0] value1; - reg [31:0] value2; - reg [1:0] lines_in; - reg [1:0] lines_out; - reg [1:0] lines_out_total; + reg [6:0] payload; + reg [6:0] payload_read; + reg [3:0] state; + reg [15:0] high; + reg [15:0] low; + reg pending; + reg [31:0] value0; + reg [31:0] value1; + reg [31:0] value2; + reg [1:0] lines_in; + reg [1:0] lines_out; + reg [1:0] lines_out_total; - `define JITTER 5 - `define OP_CODE 31:24 - `define PAYLOAD 8:2 + `define JITTER 5 + `define OP_CODE 31:24 + `define PAYLOAD 8:2 - wire [7:0] ops; - assign ops = value0[`OP_CODE]; - assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]}; + wire [7:0] ops; + assign ops = value0[`OP_CODE]; + assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]}; - always @(posedge txclk) - if (reset) - begin - pending <= 0; - state <= IDLE; - skip <= 0; - rdreq <= 0; - rx_WR <= 0; - reg_io_enable <= 0; - reg_data_in <= 0; - reg_addr <= 0; - end - else case (state) - IDLE : begin - payload_read <= 0; - skip <= 0; - lines_in <= 0; - if (pkt_waiting) - begin - state <= HEADER; - rdreq <= 1; - end - end + always @(posedge txclk) + if (reset) + begin + pending <= 0; + state <= IDLE; + skip <= 0; + rdreq <= 0; + rx_WR <= 0; + reg_io_enable <= 0; + reg_data_in <= 0; + reg_addr <= 0; + stop <= 0; + end + else case (state) + IDLE : + begin + payload_read <= 0; + skip <= 0; + lines_in <= 0; + if(pkt_waiting) + begin + state <= HEADER; + rdreq <= 1; + end + end + + HEADER : + begin + payload <= fifodata[`PAYLOAD]; + state <= TIMESTAMP; + end + + TIMESTAMP : + begin + value0 <= fifodata; + state <= WAIT; + rdreq <= 0; + end - HEADER : begin - payload <= fifodata[`PAYLOAD]; - state <= TIMESTAMP; - end + WAIT : + begin + // Let's send it + if ((value0 <= timestamp_clock + `JITTER + && value0 > timestamp_clock) + || value0 == 32'hFFFFFFFF) + state <= TEST; + // Wait a little bit more + else if (value0 > timestamp_clock + `JITTER) + state <= WAIT; + // Outdated + else if (value0 < timestamp_clock) + begin + state <= IDLE; + skip <= 1; + end + end - TIMESTAMP : begin - value0 <= fifodata; - state <= WAIT; - rdreq <= 0; - end - - WAIT : begin - // Let's send it - if ((value0 <= adc_time + `JITTER - && value0 > adc_time) - || value0 == 32'hFFFFFFFF) - state <= TEST; - // Wait a little bit more - else if (value0 > adc_time + `JITTER) - state <= WAIT; - // Outdated - else if (value0 < adc_time) - begin - state <= IDLE; + TEST : + begin + reg_io_enable <= 0; + rx_WR <= 0; + rx_WR_done <= 1; + stop <= 0; + if (payload_read == payload) + begin + skip <= 1; + state <= IDLE; + rdreq <= 0; + end + else + begin + value0 <= fifodata; + lines_in <= 2'd1; + rdreq <= 1; + payload_read <= payload_read + 7'd1; + lines_out <= 0; + case (fifodata[`OP_CODE]) + `OP_PING_FIXED: + begin + state <= PING; + end + `OP_WRITE_REG: + begin + state <= WRITE_REG; + pending <= 1; + end + `OP_WRITE_REG_MASKED: + begin + state <= WRITE_REG_MASKED; + pending <= 1; + end + `OP_READ_REG: + begin + state <= READ_REG; + end + `OP_DELAY: + begin + state <= DELAY; + end + default: + begin + //error, skip this packet skip <= 1; - end - end - - TEST : begin - reg_io_enable <= 0; - rx_WR <= 0; - rx_WR_done <= 1; - if (payload_read == payload) - begin - skip <= 1; - state <= IDLE; - rdreq <= 0; - end - else - begin - value0 <= fifodata; - lines_in <= 2'd1; - rdreq <= 1; - payload_read <= payload_read + 7'd1; - lines_out <= 0; - case (fifodata[`OP_CODE]) - `OP_PING_FIXED: begin - state <= PING; - end - `OP_WRITE_REG: begin - state <= WRITE_REG; - pending <= 1; - end - `OP_WRITE_REG_MASKED: begin - state <= WRITE_REG_MASKED; - pending <= 1; - end - `OP_READ_REG: begin - state <= READ_REG; - end - `OP_DELAY: begin - state <= DELAY; - end - default: begin - //error, skip this packet - skip <= 1; - state <= IDLE; - end - endcase - end - end + state <= IDLE; + end + endcase + end + end - SEND: begin - rdreq <= 0; - rx_WR_done <= 0; - if (pending) - begin - rx_WR <= 1; - rx_databus <= high; - pending <= 0; - if (lines_out == lines_out_total) - state <= TEST; - else case (ops) - `OP_READ_REG: begin - state <= READ_REG; - end - default: begin - state <= TEST; - end - endcase - end - else - begin - if (rx_WR_enabled) - begin - rx_WR <= 1; - rx_databus <= low; - pending <= 1; - lines_out <= lines_out + 2'd1; - end - else - rx_WR <= 0; - end - end + SEND: + begin + rdreq <= 0; + rx_WR_done <= 0; + if (pending) + begin + rx_WR <= 1; + rx_databus <= high; + pending <= 0; + if (lines_out == lines_out_total) + state <= TEST; + else case (ops) + `OP_READ_REG: + begin + state <= READ_REG; + end + default: + begin + state <= TEST; + end + endcase + end + else + begin + if (rx_WR_enabled) + begin + rx_WR <= 1; + rx_databus <= low; + pending <= 1; + lines_out <= lines_out + 2'd1; + end + else + rx_WR <= 0; + end + end - PING: begin - rx_WR <= 0; - rdreq <= 0; - rx_WR_done <= 0; - lines_out_total <= 2'd1; - pending <= 0; - state <= SEND; - high <= {`OP_PING_FIXED_REPLY, 8'd2}; - low <= value0[15:0]; - end + PING: + begin + rx_WR <= 0; + rdreq <= 0; + rx_WR_done <= 0; + lines_out_total <= 2'd1; + pending <= 0; + state <= SEND; + high <= {`OP_PING_FIXED_REPLY, 8'd2}; + low <= value0[15:0]; + end - READ_REG: begin - rx_WR <= 0; - rx_WR_done <= 0; - rdreq <= 0; - lines_out_total <= 2'd2; - pending <= 0; - state <= SEND; - if (lines_out == 0) - begin - high <= {`OP_READ_REG_REPLY, 8'd6}; - low <= value0[15:0]; - reg_io_enable <= 2'd3; - reg_addr <= value0[6:0]; - end - else - begin - high <= reg_data_out[31:16]; - low <= reg_data_out[15:0]; - end - end + READ_REG: + begin + rx_WR <= 0; + rx_WR_done <= 0; + rdreq <= 0; + lines_out_total <= 2'd2; + pending <= 0; + state <= SEND; + if (lines_out == 0) + begin + high <= {`OP_READ_REG_REPLY, 8'd6}; + low <= value0[15:0]; + reg_io_enable <= 2'd3; + reg_addr <= value0[6:0]; + end + else + begin + high <= reg_data_out[31:16]; + low <= reg_data_out[15:0]; + end + end - WRITE_REG: begin - rx_WR <= 0; - if (pending) - pending <= 0; - else - begin - if (lines_in == 2'd1) - begin - payload_read <= payload_read + 7'd1; - lines_in <= lines_in + 2'd1; - value1 <= fifodata; - rdreq <= 0; - end - else - begin - reg_io_enable <= 2'd2; - reg_data_in <= value1; - reg_addr <= value0[6:0]; - state <= TEST; - end - end - end + WRITE_REG: + begin + rx_WR <= 0; + if (pending) + pending <= 0; + else + begin + if (lines_in == 2'd1) + begin + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value1 <= fifodata; + rdreq <= 0; + end + else + begin + reg_io_enable <= 2'd2; + reg_data_in <= value1; + reg_addr <= value0[6:0]; + state <= TEST; + end + end + end - WRITE_REG_MASKED: begin - rx_WR <= 0; - if (pending) - pending <= 0; - else - begin - if (lines_in == 2'd1) - begin - rdreq <= 1; - payload_read <= payload_read + 7'd1; - lines_in <= lines_in + 2'd1; - value1 <= fifodata; - end - else if (lines_in == 2'd2) - begin - rdreq <= 0; - payload_read <= payload_read + 7'd1; - lines_in <= lines_in + 2'd1; - value2 <= fifodata; - end - else - begin - reg_io_enable <= 2'd2; - reg_data_in <= (value1 & value2); - reg_addr <= value0[6:0]; - state <= TEST; - end - end - end + WRITE_REG_MASKED: + begin + rx_WR <= 0; + if (pending) + pending <= 0; + else + begin + if (lines_in == 2'd1) + begin + rdreq <= 1; + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value1 <= fifodata; + end + else if (lines_in == 2'd2) + begin + rdreq <= 0; + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value2 <= fifodata; + end + else + begin + reg_io_enable <= 2'd2; + reg_data_in <= (value1 & value2); + reg_addr <= value0[6:0]; + state <= TEST; + end + end + end - DELAY : begin - rdreq <= 0; - value1 <= value1 + 32'd1; - if (value0[15:0] == value1[15:0]) - state <= TEST; - end + DELAY : + begin + rdreq <= 0; + stop <= 1; + stop_time <= value0[15:0]; + state <= TEST; + end - default : begin - //error state handling - state <= IDLE; - end - endcase -endmodule \ No newline at end of file + default : + begin + //error state handling + state <= IDLE; + end + endcase +endmodule diff --git a/inband_lib/data_packet_fifo.v b/inband_lib/data_packet_fifo.v deleted file mode 100755 index a9bcbdae7..000000000 --- a/inband_lib/data_packet_fifo.v +++ /dev/null @@ -1,118 +0,0 @@ -module data_packet_fifo - ( input reset, - input clock, - input [31:0]ram_data_in, - input write_enable, - output reg have_space, - output reg [31:0]ram_data_out, - output reg pkt_waiting, - output reg isfull, - output reg [1:0]usb_ram_packet_out, - output reg [1:0]usb_ram_packet_in, - input read_enable, - input pkt_complete, - input skip_packet) ; - - /* Some parameters for usage later on */ - parameter DATA_WIDTH = 32 ; - parameter PKT_DEPTH = 128 ; - parameter NUM_PACKETS = 4 ; - - /* Create the RAM here */ - reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ; - - /* Create the address signals */ - reg [6:0] usb_ram_offset_out ; - //reg [1:0] usb_ram_packet_out ; - reg [6:0] usb_ram_offset_in ; - //reg [1:0] usb_ram_packet_in ; - - wire [6-2+NUM_PACKETS:0] usb_ram_aout ; - wire [6-2+NUM_PACKETS:0] usb_ram_ain ; - //reg isfull; - - assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ; - assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ; - - // Check if there is one full packet to process - always @(usb_ram_ain, usb_ram_aout, isfull) - begin - if (usb_ram_ain == usb_ram_aout) - pkt_waiting <= isfull ; - else if (usb_ram_ain > usb_ram_aout) - pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= PKT_DEPTH; - else - pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >= PKT_DEPTH; - end - - // Check if there is room - always @(usb_ram_ain, usb_ram_aout, isfull) - begin - if (usb_ram_ain == usb_ram_aout) - have_space <= ~isfull; - else if (usb_ram_ain > usb_ram_aout) - have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH * (NUM_PACKETS - 1))? 1'b1 : 1'b0; - else - have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH; - end - - - - /* RAM Writing/Reading process */ - always @(posedge clock) - begin - if( write_enable ) - begin - usb_ram[usb_ram_ain] <= ram_data_in ; - end - ram_data_out <= usb_ram[usb_ram_aout] ; - end - - /* RAM Write/Read Address process */ - always @(posedge clock) - begin - if( reset ) - begin - usb_ram_packet_out <= 0 ; - usb_ram_offset_out <= 0 ; - usb_ram_offset_in <= 0 ; - usb_ram_packet_in <= 0 ; - isfull <= 0; - end - else - begin - if( skip_packet ) - begin - usb_ram_packet_out <= usb_ram_packet_out + 1 ; - usb_ram_offset_out <= 0 ; - isfull <= 0; - end - else if(read_enable) - begin - if( usb_ram_offset_out == 7'b1111111 ) - begin - isfull <= 0 ; - usb_ram_offset_out <= 0 ; - usb_ram_packet_out <= usb_ram_packet_out + 1 ; - end - else - usb_ram_offset_out <= usb_ram_offset_out + 1 ; - end - if( pkt_complete ) - begin - usb_ram_packet_in <= usb_ram_packet_in + 1 ; - usb_ram_offset_in <= 0 ; - if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out) - isfull <= 1 ; - end - else if( write_enable ) - begin - if (usb_ram_offset_in == 7'b1111111) - usb_ram_offset_in <= 7'b1111111 ; - else - usb_ram_offset_in <= usb_ram_offset_in + 1 ; - end - end - end - -endmodule diff --git a/inband_lib/packet_builder.v b/inband_lib/packet_builder.v index fbf0a656e..2c9122394 100755 --- a/inband_lib/packet_builder.v +++ b/inband_lib/packet_builder.v @@ -1,8 +1,8 @@ -module packet_builder #(parameter NUM_CHAN = 1)( +module packet_builder #(parameter NUM_CHAN = 2)( // System input rxclk, input reset, - input [31:0] adctime, + input [31:0] timestamp_clock, input [3:0] channels, // ADC side input [15:0]chan_fifodata, @@ -14,17 +14,17 @@ module packet_builder #(parameter NUM_CHAN = 1)( output reg WR, output reg [15:0]fifodata, input have_space, - input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2, - input wire [31:0]rssi_3, output wire [7:0] debugbus, - input [NUM_CHAN:0] overrun, input [NUM_CHAN:0] underrun); + input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2, + input wire [31:0]rssi_3, output wire [7:0] debugbus, + input [NUM_CHAN:0] underrun); // States `define IDLE 3'd0 `define HEADER1 3'd1 - `define HEADER2 3'd2 + `define HEADER2 3'd2 `define TIMESTAMP 3'd3 - `define FORWARD 3'd4 + `define FORWARD 3'd4 `define MAXPAYLOAD 504 @@ -39,51 +39,67 @@ module packet_builder #(parameter NUM_CHAN = 1)( `define UNDERRUN 14 `define OVERRUN 15 + reg [NUM_CHAN:0] overrun; reg [2:0] state; reg [8:0] read_length; reg [8:0] payload_len; - reg tstamp_complete; + reg timestamp_complete; reg [3:0] check_next; - wire [8:0] chan_used; + wire [31:0] true_rssi; - wire [4:0] true_channel; + wire [4:0] true_channel; + wire ready_to_send; + + assign debugbus = {chan_empty[0], rd_select[0], have_space, + (chan_usedw >= 10'd504), (chan_usedw ==0), + ready_to_send, state[1:0]}; - assign debugbus = {state, chan_empty[0], underrun[0], check_next[0], - have_space, rd_select[0]}; - assign chan_used = chan_usedw[8:0]; - assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) : + assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) : ((rd_select[0]) ? rssi_1:rssi_0); - assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); + assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); + assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) || + ((rd_select == NUM_CHAN)&&(chan_usedw > 0)); + always @(posedge rxclk) begin if (reset) begin + overrun <= 0; WR <= 0; rd_select <= 0; chan_rdreq <= 0; - tstamp_complete <= 0; + timestamp_complete <= 0; check_next <= 0; state <= `IDLE; end else case (state) `IDLE: begin - chan_rdreq <= #1 0; - if (have_space) - begin - if(~chan_empty[check_next]) - begin - state <= #1 `HEADER1; - rd_select <= #1 check_next; - end - check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1); - end + chan_rdreq <= #1 0; + //check if the channel is full + if(~chan_empty[check_next]) + begin + if (have_space) + begin + //transmit if the usb buffer have space + //check if we should send + if (ready_to_send) + state <= #1 `HEADER1; + + overrun[check_next] <= 0; + end + else + begin + state <= #1 `IDLE; + overrun[check_next] <= 1; + end + rd_select <= #1 check_next; + end + check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1); end `HEADER1: begin - fifodata[`PAYLOAD_LEN] <= #1 (chan_used > 9'd252 - ? 9'd252 : chan_used << 1); - payload_len <= #1 (chan_used > 9'd252 - ? 9'd252 : chan_used << 1); + fifodata[`PAYLOAD_LEN] <= #1 9'd504; + payload_len <= #1 9'd504; fifodata[`TAG] <= #1 0; fifodata[`MBZ] <= #1 0; WR <= #1 1; @@ -103,13 +119,13 @@ module packet_builder #(parameter NUM_CHAN = 1)( end `TIMESTAMP: begin - fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]); - tstamp_complete <= #1 ~tstamp_complete; + fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]); + timestamp_complete <= #1 ~timestamp_complete; - if (~tstamp_complete) + if (~timestamp_complete) chan_rdreq <= #1 1; - state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP); + state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP); end `FORWARD: begin diff --git a/inband_lib/register_io.v b/inband_lib/register_io.v index b116b3ace..2b0cd1732 100755 --- a/inband_lib/register_io.v +++ b/inband_lib/register_io.v @@ -1,15 +1,38 @@ module register_io - (input clk, input reset, input wire [1:0] enable, input wire [6:0] addr, - input wire [31:0] datain, output reg [31:0] dataout, output wire [15:0] debugbus, - input wire [31:0] rssi_0, input wire [31:0] rssi_1, - input wire [31:0] rssi_2, input wire [31:0] rssi_3, - output wire [31:0] threshhold, output wire [31:0] rssi_wait); - + (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr, + rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3, + debug_en, misc, txmux); + + input clk; + input reset; + input wire [1:0] enable; + input wire [6:0] addr; + input wire [31:0] datain; + output reg [31:0] dataout; + output wire [15:0] debugbus; + output reg [6:0] addr_wr; + output reg [31:0] data_wr; + output wire strobe_wr; + input wire [31:0] rssi_0; + input wire [31:0] rssi_1; + input wire [31:0] rssi_2; + input wire [31:0] rssi_3; + output wire [31:0] threshhold; + output wire [31:0] rssi_wait; + input wire [15:0] reg_0; + input wire [15:0] reg_1; + input wire [15:0] reg_2; + input wire [15:0] reg_3; + input wire [3:0] debug_en; + input wire [7:0] misc; + input wire [31:0] txmux; + reg strobe; - wire [31:0] out[7:0]; + wire [31:0] out[2:1]; assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]}; assign threshhold = out[1]; assign rssi_wait = out[2]; + assign strobe_wr = strobe; always @(*) if (reset | ~enable[1]) @@ -22,41 +45,38 @@ module register_io if (enable[0]) begin //read - if (addr == 7'd9) - dataout <= rssi_0; - else if (addr == 7'd10) - dataout <= rssi_1; - else if (addr == 7'd11) - dataout <= rssi_2; - else if (addr == 7'd12) - dataout <= rssi_3; - else - dataout <= out[addr[2:0]]; - strobe <= 0; - end + if (addr <= 7'd52 && addr > 7'd50) + dataout <= out[addr-7'd50]; + else + dataout <= 32'hFFFFFFFF; + strobe <= 0; + end else begin //write dataout <= dataout; strobe <= 1; + data_wr <= datain; + addr_wr <= addr; end end - //register declarations - setting_reg #(0) setting_reg0(.clock(clk),.reset(reset), - .strobe(strobe),.addr(addr),.in(datain),.out(out[0])); - setting_reg #(1) setting_reg1(.clock(clk),.reset(reset), - .strobe(strobe),.addr(addr),.in(datain),.out(out[1])); - setting_reg #(2) setting_reg2(.clock(clk),.reset(reset), - .strobe(strobe),.addr(addr),.in(datain),.out(out[2])); - setting_reg #(3) setting_reg3(.clock(clk),.reset(reset), - .strobe(strobe),.addr(addr),.in(datain),.out(out[3])); - setting_reg #(4) setting_reg4(.clock(clk),.reset(reset), - .strobe(strobe),.addr(addr),.in(datain),.out(out[4])); - setting_reg #(5) setting_reg5(.clock(clk),.reset(reset), - .strobe(strobe),.addr(addr),.in(datain),.out(out[5])); - setting_reg #(6) setting_reg6(.clock(clk),.reset(reset), - .strobe(strobe),.addr(addr),.in(datain),.out(out[6])); - setting_reg #(7) setting_reg7(.clock(clk),.reset(reset), - .strobe(strobe),.addr(addr),.in(datain),.out(out[7])); -endmodule \ No newline at end of file +//register declarations + /*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/ + setting_reg #(51) setting_reg1(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1])); + setting_reg #(52) setting_reg2(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2])); + /*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3])); + setting_reg #(54) setting_reg4(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4])); + setting_reg #(55) setting_reg5(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5])); + setting_reg #(56) setting_reg6(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6])); + setting_reg #(57) setting_reg7(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/ + +endmodule diff --git a/inband_lib/rx_buffer_inband.v b/inband_lib/rx_buffer_inband.v index 1eaecabed..cbd2d8958 100755 --- a/inband_lib/rx_buffer_inband.v +++ b/inband_lib/rx_buffer_inband.v @@ -1,179 +1,209 @@ -//`include "../../firmware/include/fpga_regs_common.v" -//`include "../../firmware/include/fpga_regs_standard.v" -module rx_buffer_inband - ( input usbclk, - input bus_reset, - input reset, // DSP side reset (used here), do not reset registers - input reset_regs, //Only reset registers - output [15:0] usbdata, - input RD, - output wire have_pkt_rdy, - output reg rx_overrun, - input wire [3:0] channels, - input wire [15:0] ch_0, - input wire [15:0] ch_1, - input wire [15:0] ch_2, - input wire [15:0] ch_3, - input wire [15:0] ch_4, - input wire [15:0] ch_5, - input wire [15:0] ch_6, - input wire [15:0] ch_7, - input rxclk, - input rxstrobe, - input clear_status, - input [6:0] serial_addr, - input [31:0] serial_data, - input serial_strobe, - output wire [15:0] debugbus, - - //Connection with tx_inband - input rx_WR, - input [15:0] rx_databus, - input rx_WR_done, - output reg rx_WR_enabled, - //signal strength - input wire [31:0] rssi_0, input wire [31:0] rssi_1, - input wire [31:0] rssi_2, input wire [31:0] rssi_3, - input wire [1:0] tx_overrun, input wire [1:0] tx_underrun - ); - - parameter NUM_CHAN = 1; - genvar i ; - - // FX2 Bug Fix - reg [8:0] read_count; - always @(negedge usbclk) - if(bus_reset) - read_count <= #1 9'd0; - else if(RD & ~read_count[8]) - read_count <= #1 read_count + 9'd1; - else - read_count <= #1 RD ? read_count : 9'b0; - - // Time counter - reg [31:0] adctime; - always @(posedge rxclk) - if (reset) - adctime <= 0; - else if (rxstrobe) - adctime <= adctime + 1; - - // USB side fifo - wire [11:0] rdusedw; - wire [11:0] wrusedw; - wire [15:0] fifodata; - wire WR; - wire have_space; - - fifo_4kx16_dc rx_usb_fifo ( - .aclr ( reset ), - .data ( fifodata ), - .rdclk ( ~usbclk ), - .rdreq ( RD & ~read_count[8] ), - .wrclk ( rxclk ), - .wrreq ( WR ), - .q ( usbdata ), - .rdempty ( ), - .rdusedw ( rdusedw ), - .wrfull ( ), - .wrusedw ( wrusedw ) ); - - assign have_pkt_rdy = (rdusedw >= 12'd256); - assign have_space = (wrusedw < 12'd760); - - // Rx side fifos - wire chan_rdreq; - wire [15:0] chan_fifodata; - wire [9:0] chan_usedw; - wire [NUM_CHAN:0] chan_empty; - wire [3:0] rd_select; - wire [NUM_CHAN:0] rx_full; - - packet_builder #(NUM_CHAN) rx_pkt_builer ( - .rxclk ( rxclk ), - .reset ( reset ), - .adctime ( adctime ), - .channels ( 4'd1 ), - .chan_rdreq ( chan_rdreq ), - .chan_fifodata ( chan_fifodata ), - .chan_empty ( chan_empty ), - .rd_select ( rd_select ), - .chan_usedw ( chan_usedw ), - .WR ( WR ), - .fifodata ( fifodata ), - .have_space ( have_space ), - .rssi_0(rssi_0), .rssi_1(rssi_1), - .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug), - .overrun(tx_overrun), .underrun(tx_underrun)); - - // Detect overrun - always @(posedge rxclk) - if(reset) - rx_overrun <= 1'b0; - else if(rx_full[0]) - rx_overrun <= 1'b1; - else if(clear_status) - rx_overrun <= 1'b0; - - reg [6:0] test; - always @(posedge rxclk) - if (reset) - test <= 0; - else - test <= test + 7'd1; - - // TODO write this genericly - wire [15:0]ch[NUM_CHAN:0]; - assign ch[0] = ch_0; - - wire cmd_empty; - always @(posedge rxclk) - if(reset) - rx_WR_enabled <= 1; - else if(cmd_empty) - rx_WR_enabled <= 1; - else if(rx_WR_done) - rx_WR_enabled <= 0; - - wire [15:0] dataout [0:NUM_CHAN]; - wire [9:0] usedw [0:NUM_CHAN]; - wire empty[0:NUM_CHAN]; - - generate for (i = 0 ; i < NUM_CHAN; i = i + 1) - begin : generate_channel_fifos - wire rdreq; - - assign rdreq = (rd_select == i) & chan_rdreq; - //assign chan_empty[i] = usedw[i] < 10'd126; - fifo_1kx16 rx_chan_fifo ( - .aclr ( reset ), - .clock ( rxclk ), - .data ( ch[i] ), - .rdreq ( rdreq ), - .wrreq ( ~rx_full[i] & rxstrobe), - .empty (empty[i]), - .full (rx_full[i]), - .q ( dataout[i]), - .usedw ( usedw[i]), - .almost_empty(chan_empty[i]) - ); - end - endgenerate - wire [7:0] debug; - fifo_1kx16 rx_cmd_fifo ( - .aclr ( reset ), - .clock ( rxclk ), - .data ( rx_databus ), - .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), - .wrreq ( rx_WR & rx_WR_enabled), - .empty ( cmd_empty), - .full ( rx_full[NUM_CHAN] ), - .q ( dataout[NUM_CHAN]), - .usedw ( usedw[NUM_CHAN] ) - ); - assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; - assign chan_fifodata = dataout[rd_select]; - assign chan_usedw = usedw[rd_select]; - assign debugbus = {rxstrobe, chan_rdreq, debug, - rx_full[0], chan_empty[0], empty[0], have_space, RD, rxclk}; -endmodule +//`include "../../firmware/include/fpga_regs_common.v" +//`include "../../firmware/include/fpga_regs_standard.v" +module rx_buffer_inband + ( input usbclk, + input bus_reset, + input reset, // DSP side reset (used here), do not reset registers + input reset_regs, //Only reset registers + output [15:0] usbdata, + input RD, + output wire have_pkt_rdy, + output reg rx_overrun, + input wire [3:0] channels, + input wire [15:0] ch_0, + input wire [15:0] ch_1, + input wire [15:0] ch_2, + input wire [15:0] ch_3, + input wire [15:0] ch_4, + input wire [15:0] ch_5, + input wire [15:0] ch_6, + input wire [15:0] ch_7, + input rxclk, + input rxstrobe, + input clear_status, + input [6:0] serial_addr, + input [31:0] serial_data, + input serial_strobe, + output wire [15:0] debugbus, + + //Connection with tx_inband + input rx_WR, + input [15:0] rx_databus, + input rx_WR_done, + output reg rx_WR_enabled, + //signal strength + input wire [31:0] rssi_0, input wire [31:0] rssi_1, + input wire [31:0] rssi_2, input wire [31:0] rssi_3, + input wire [1:0] tx_underrun + ); + + parameter NUM_CHAN = 1; + genvar i ; + + // FX2 Bug Fix + reg [8:0] read_count; + always @(negedge usbclk) + if(bus_reset) + read_count <= #1 9'd0; + else if(RD & ~read_count[8]) + read_count <= #1 read_count + 9'd1; + else + read_count <= #1 RD ? read_count : 9'b0; + + // Time counter + reg [31:0] timestamp_clock; + always @(posedge rxclk) + if (reset) + timestamp_clock <= 0; + else + timestamp_clock <= timestamp_clock + 1; + + // USB side fifo + wire [11:0] rdusedw; + wire [11:0] wrusedw; + wire [15:0] fifodata; + wire [15:0] fifodata_il[0:NUM_CHAN]; + wire WR; + wire have_space; + reg sel; + reg wr; + + always@(posedge rxclk) + begin + if(reset) + begin + sel<=1; + wr<=0; + end + else if(rxstrobe) + begin + sel<=0; + wr<=1; + end + else if(wr&~sel) + sel<=1; + else if(wr&sel) + wr<=0; + else + wr<=0; + end + + assign fifodata_il[0] = (sel)?ch_1:ch_0; + assign fifodata_il[1] = (sel)?ch_3:ch_2; + + fifo_4kx16_dc rx_usb_fifo ( + .aclr ( reset ), + .data ( fifodata ), + .rdclk ( ~usbclk ), + .rdreq ( RD & ~read_count[8] ), + .wrclk ( rxclk ), + .wrreq ( WR ), + .q ( usbdata ), + .rdempty ( ), + .rdusedw ( rdusedw ), + .wrfull ( ), + .wrusedw ( wrusedw ) ); + + assign have_pkt_rdy = (rdusedw >= 12'd256); + assign have_space = (wrusedw < 12'd760); + + // Rx side fifos + // These are of size [NUM_CHAN:0] because the extra channel is used for the + // RX command channel. If there were no command channel, they would be + // NUM_CHAN-1. + wire chan_rdreq; + wire [15:0] chan_fifodata; + wire [9:0] chan_usedw; + wire [NUM_CHAN:0] chan_empty; + wire [3:0] rd_select; + wire [NUM_CHAN:0] rx_full; + + packet_builder #(NUM_CHAN) rx_pkt_builer ( + .rxclk ( rxclk ), + .reset ( reset ), + .timestamp_clock ( timestamp_clock ), + .channels ( NUM_CHAN ), + .chan_rdreq ( chan_rdreq ), + .chan_fifodata ( chan_fifodata ), + .chan_empty ( chan_empty ), + .rd_select ( rd_select ), + .chan_usedw ( chan_usedw ), + .WR ( WR ), + .fifodata ( fifodata ), + .have_space ( have_space ), + .rssi_0(rssi_0), .rssi_1(rssi_1), + .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug), + .underrun(tx_underrun)); + + // Detect overrun + always @(posedge rxclk) + if(reset) + rx_overrun <= 1'b0; + else if(rx_full[0]) + rx_overrun <= 1'b1; + else if(clear_status) + rx_overrun <= 1'b0; + + + // FIXME: what is the purpose of these two lines? + wire [15:0]ch[NUM_CHAN:0]; + assign ch[0] = ch_0; + + wire cmd_empty; + + always @(posedge rxclk) + if(reset) + rx_WR_enabled <= 1; + else if(cmd_empty) + rx_WR_enabled <= 1; + else if(rx_WR_done) + rx_WR_enabled <= 0; + + + // Of Size 0:NUM_CHAN due to extra command channel. + wire [15:0] dataout [0:NUM_CHAN]; + wire [9:0] usedw [0:NUM_CHAN]; + wire empty[0:NUM_CHAN]; + + generate for (i = 0 ; i < NUM_CHAN; i = i + 1) + begin : generate_channel_fifos + + wire rdreq; + + assign rdreq = (rd_select == i) & chan_rdreq; + + fifo_1kx16 rx_chan_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( fifodata_il[i] ), + .rdreq ( rdreq ), + .wrreq ( ~rx_full[i] & wr), + .empty (empty[i]), + .full (rx_full[i]), + .q ( dataout[i]), + .usedw ( usedw[i]), + .almost_empty(chan_empty[i]) + ); + end + endgenerate + + wire [7:0] debug; + + fifo_1kx16 rx_cmd_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( rx_databus ), + .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), + .wrreq ( rx_WR & rx_WR_enabled), + .empty ( cmd_empty), + .full ( rx_full[NUM_CHAN] ), + .q ( dataout[NUM_CHAN]), + .usedw ( usedw[NUM_CHAN] ) + ); + + assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; + assign chan_fifodata = dataout[rd_select]; + assign chan_usedw = usedw[rd_select]; + assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr}; + +endmodule diff --git a/inband_lib/tx_buffer_inband.v b/inband_lib/tx_buffer_inband.v index fec9dbe31..2dd75f42f 100755 --- a/inband_lib/tx_buffer_inband.v +++ b/inband_lib/tx_buffer_inband.v @@ -1,224 +1,143 @@ module tx_buffer_inband - ( usbclk, bus_reset, reset, usbdata, WR, have_space, - channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1, - tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe, - clear_status, tx_empty, debugbus, - rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable, - reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2, - rssi_3, rssi_wait, threshhold, tx_underrun - ); + ( //System + input wire usbclk, input wire bus_reset, input wire reset, + input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels, + //output transmit signals + output wire [15:0] tx_i_0, output wire [15:0] tx_q_0, + output wire [15:0] tx_i_1, output wire [15:0] tx_q_1, + output wire [15:0] tx_i_2, output wire [15:0] tx_q_2, + output wire [15:0] tx_i_3, output wire [15:0] tx_q_3, + input wire txclk, input wire txstrobe, input wire WR, + input wire clear_status, output wire tx_empty, output wire [15:0] debugbus, + //command reader io + output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done, + input wire rx_WR_enabled, + //register io + output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr, + input wire [31:0] reg_data_out, + //input characteristic signals + input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, + input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold, + output wire [1:0] tx_underrun, + //system stop + output wire stop, output wire [15:0] stop_time); - parameter NUM_CHAN = 2 ; - /* Debug paramters */ - parameter STROBE_RATE_0 = 8'd1 ; - parameter STROBE_RATE_1 = 8'd2 ; + parameter NUM_CHAN = 1 ; - input wire usbclk ; - input wire bus_reset ; // Used here for the 257-Hack to fix the FX2 bug - input wire reset ; // standard DSP-side reset - input wire [15:0] usbdata ; - input wire WR ; - input wire txclk ; - input wire txstrobe ; - input wire rx_WR_enabled; - /* Not used yet */ - input wire [3:0] channels ; - input wire clear_status ; - /*register io*/ - input wire [31:0]reg_data_out; - // rssi - input wire [31:0]rssi_0; - input wire [31:0]rssi_1; - input wire [31:0]rssi_2; - input wire [31:0]rssi_3; - input wire [31:0]threshhold; - input wire [31:0]rssi_wait; - - output wire have_space ; - output wire tx_empty ; - output wire [15:0] tx_i_0 ; - output wire [15:0] tx_q_0 ; - output wire [15:0] tx_i_1 ; - output wire [15:0] tx_q_1 ; - output wire [15:0] debugbus ; - /* Not used yet */ - output wire [15:0] tx_i_2 ; - output wire [15:0] tx_q_2 ; - output wire [15:0] tx_i_3 ; - output wire [15:0] tx_q_3 ; - - output wire [15:0] rx_databus ; - output wire rx_WR; - output wire rx_WR_done; - /* reg_io */ - output wire [31:0] reg_data_in; - output wire [6:0] reg_addr; - output wire [1:0] reg_io_enable; - output wire [NUM_CHAN-1:0] tx_underrun; - - /* To generate channel readers */ - genvar i ; + /* To generate channel readers */ + genvar i ; - /* These will eventually be external register */ - reg [31:0] adc_time ; - wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ; - wire [31:0] rssi [3:0]; - assign rssi[0] = rssi_0; - assign rssi[1] = rssi_1; - assign rssi[2] = rssi_2; - assign rssi[3] = rssi_3; + /* These will eventually be external register */ + reg [31:0] timestamp_clock ; + wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ; + wire [31:0] rssi [3:0]; + assign rssi[0] = rssi_0; + assign rssi[1] = rssi_1; + assign rssi[2] = rssi_2; + assign rssi[3] = rssi_3; - always @(posedge txclk) - if (reset) - adc_time <= 0; - else if (txstrobe) - adc_time <= adc_time + 1; + always @(posedge txclk) + if (reset) + timestamp_clock <= 0; + else + timestamp_clock <= timestamp_clock + 1; /* Connections between tx_usb_fifo_reader and cnannel/command processing blocks */ - wire [31:0] tx_data_bus ; - wire [NUM_CHAN:0] chan_WR ; - wire [NUM_CHAN:0] chan_done ; + wire [31:0] tx_data_bus ; + wire [NUM_CHAN:0] chan_WR ; + wire [NUM_CHAN:0] chan_done ; /* Connections between data block and the FX2/TX chains */ - wire [NUM_CHAN:0] chan_underrun ; - wire [NUM_CHAN:0] chan_txempty ; + wire [NUM_CHAN:0] chan_underrun; + wire [NUM_CHAN:0] chan_txempty; - /* Conections between tx_data_packet_fifo and + /* Conections between tx_data_packet_fifo and its reader + strobe generator */ - wire [31:0] chan_fifodata [NUM_CHAN:0] ; - wire chan_pkt_waiting [NUM_CHAN:0] ; - wire chan_rdreq [NUM_CHAN:0] ; - wire chan_skip [NUM_CHAN:0] ; - wire [NUM_CHAN:0] chan_have_space ; - wire chan_txstrobe [NUM_CHAN-1:0] ; + wire [31:0] chan_fifodata [NUM_CHAN:0] ; + wire chan_pkt_waiting [NUM_CHAN:0] ; + wire chan_rdreq [NUM_CHAN:0] ; + wire chan_skip [NUM_CHAN:0] ; + wire chan_have_space [NUM_CHAN:0] ; - wire [14:0] debug; + wire [14:0] debug [NUM_CHAN:0]; - /* Outputs to transmit chains */ - wire [15:0] tx_i [NUM_CHAN-1:0] ; - wire [15:0] tx_q [NUM_CHAN-1:0] ; + /* Outputs to transmit chains */ + wire [15:0] tx_i [NUM_CHAN:0] ; + wire [15:0] tx_q [NUM_CHAN:0] ; + + assign tx_i[NUM_CHAN] = 0; + assign tx_q[NUM_CHAN] = 0; - /* TODO: Figure out how to write this genericly */ - assign have_space = chan_have_space[0] & chan_have_space[1]; - assign tx_empty = chan_txempty[0] & chan_txempty[1] ; - assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; - assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; - assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; - assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ; + assign have_space = chan_have_space[0] & chan_have_space[1]; + assign tx_empty = chan_txempty[0] & chan_txempty[1] ; + + assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; + assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; + assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; + assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ; - /* Debug statement */ - assign txstrobe_rate[0] = STROBE_RATE_0 ; - assign txstrobe_rate[1] = STROBE_RATE_1 ; - assign tx_q_2 = 16'b0 ; - assign tx_i_2 = 16'b0 ; - assign tx_q_3 = 16'b0 ; - assign tx_i_3 = 16'b0 ; - assign tx_i_3 = 16'b0 ; + assign tx_q_2 = 16'b0 ; + assign tx_i_2 = 16'b0 ; + assign tx_q_3 = 16'b0 ; + assign tx_i_3 = 16'b0 ; + assign tx_i_3 = 16'b0 ; - assign debugbus = {debug, txclk}; + assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done, + chan_pkt_waiting[0], chan_pkt_waiting[1], + chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]}; - wire [31:0] usbdata_final; - wire WR_final; + wire [31:0] usbdata_final; + wire WR_final; - tx_packer tx_usb_packer - ( - .bus_reset (bus_reset), - .usbclk (usbclk), - .WR_fx2 (WR), - .usbdata (usbdata), - .reset (reset), - .txclk (txclk), - .usbdata_final (usbdata_final), - .WR_final (WR_final) - ); + tx_packer tx_usb_packer + (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR), + .usbdata(usbdata), .reset(reset), .txclk(txclk), + .usbdata_final(usbdata_final), .WR_final(WR_final)); - channel_demux channel_demuxer - ( - .usbdata_final (usbdata_final), - .WR_final (WR_final), - .reset (reset), - .txclk (txclk), - .WR_channel (chan_WR), - .WR_done_channel (chan_done), - .ram_data (tx_data_bus) - ); + channel_demux #(NUM_CHAN) channel_demuxer + (.usbdata_final(usbdata_final), .WR_final(WR_final), + .reset(reset), .txclk(txclk), .WR_channel(chan_WR), + .WR_done_channel(chan_done), .ram_data(tx_data_bus)); - generate for (i = 0 ; i < NUM_CHAN; i = i + 1) - begin : generate_channel_readers - assign tx_underrun[i] = chan_underrun[i]; - channel_ram tx_data_packet_fifo - ( .reset (reset), - .txclk (txclk), - .datain (tx_data_bus), - .WR (chan_WR[i]), - .WR_done (chan_done[i]), - .have_space (chan_have_space[i]), - .dataout (chan_fifodata[i]), - .packet_waiting (chan_pkt_waiting[i]), - .RD (chan_rdreq[i]), - .RD_done (chan_skip[i]) - ); + generate for (i = 0 ; i < NUM_CHAN; i = i + 1) + begin : generate_channel_readers + assign tx_underrun[i] = chan_underrun[i]; - chan_fifo_reader tx_chan_reader - ( .reset (reset), - .tx_clock (txclk), - .tx_strobe (txstrobe), - .adc_time (adc_time), - .samples_format (4'b0), - .tx_q (tx_q[i]), - .tx_i (tx_i[i]), - .underrun (chan_underrun[i]), - .skip (chan_skip[i]), - .rdreq (chan_rdreq[i]), - .fifodata (chan_fifodata[i]), - .pkt_waiting (chan_pkt_waiting[i]), - .tx_empty (chan_txempty[i]), - .rssi (rssi[i]), - .threshhold (threshhold), - .rssi_wait (rssi_wait) - ); - + channel_ram tx_data_packet_fifo + (.reset(reset), .txclk(txclk), .datain(tx_data_bus), + .WR(chan_WR[i]), .WR_done(chan_done[i]), + .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]), + .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]), + .RD_done(chan_skip[i])); + + chan_fifo_reader tx_chan_reader + (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe), + .timestamp_clock(timestamp_clock), .samples_format(4'b0), + .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]), + .skip(chan_skip[i]), .rdreq(chan_rdreq[i]), + .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]), + .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]), + .threshhold(threshhold), .rssi_wait(rssi_wait)); end endgenerate - channel_ram tx_cmd_packet_fifo - ( .reset (reset), - .txclk (txclk), - .datain (tx_data_bus), - .WR (chan_WR[NUM_CHAN]), - .WR_done (chan_done[NUM_CHAN]), - .have_space (chan_have_space[NUM_CHAN]), - .dataout (chan_fifodata[NUM_CHAN]), - .packet_waiting (chan_pkt_waiting[NUM_CHAN]), - .RD (chan_rdreq[NUM_CHAN]), - .RD_done (chan_skip[NUM_CHAN]) - ); + channel_ram tx_cmd_packet_fifo + (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]), + .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]), + .dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]), + .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN])); - - cmd_reader tx_cmd_reader - ( .reset (reset), - .txclk (txclk), - .adc_time (adc_time), - .skip (chan_skip[NUM_CHAN]), - .rdreq (chan_rdreq[NUM_CHAN]), - .fifodata (chan_fifodata[NUM_CHAN]), - .pkt_waiting (chan_pkt_waiting[NUM_CHAN]), - .rx_databus (rx_databus), - .rx_WR (rx_WR), - .rx_WR_done (rx_WR_done), - .rx_WR_enabled (rx_WR_enabled), - .reg_data_in (reg_data_in), - .reg_data_out (reg_data_out), - .reg_addr (reg_addr), - .reg_io_enable (reg_io_enable), - .debug (debug) - ); - - - + cmd_reader tx_cmd_reader + (.reset(reset), .txclk(txclk), .timestamp_clock(timestamp_clock), .skip(chan_skip[NUM_CHAN]), + .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]), + .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus), + .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled), + .reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr), + .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time)); + endmodule // tx_buffer diff --git a/inband_lib/usb_fifo_reader.v b/inband_lib/usb_fifo_reader.v deleted file mode 100755 index d002d90ff..000000000 --- a/inband_lib/usb_fifo_reader.v +++ /dev/null @@ -1,25 +0,0 @@ -module usb_fifo_reader ( - input usbclk, - input bus_reset, - input RD, - output rdreq, - ); - - // FX2 Bug Fix - reg [8:0] read_count; - always @(negedge usbclk) - if(bus_reset) - read_count <= #1 9'd0; - else if(RD & ~read_count[8]) - read_count <= #1 read_count + 9'd1; - else - read_count <= #1 RD ? read_count : 9'b0; - - assign rdreq = RD & ~read_count[8]; - - - -endmodule - - - \ No newline at end of file diff --git a/inband_lib/usb_fifo_writer.v b/inband_lib/usb_fifo_writer.v deleted file mode 100755 index abe1dd567..000000000 --- a/inband_lib/usb_fifo_writer.v +++ /dev/null @@ -1,183 +0,0 @@ - -module usb_fifo_writer - #(parameter BUS_WIDTH = 16, - parameter NUM_CHAN = 2, - parameter FIFO_WIDTH = 32) - ( //FX2 Side - input bus_reset, - input usbclk, - input WR_fx2, - input [15:0]usbdata, - - // TX Side - input reset, - input txclk, - output reg [NUM_CHAN:0] WR_channel, - output reg [FIFO_WIDTH-1:0] ram_data, - output reg [NUM_CHAN:0] WR_done_channel ); - - - reg [8:0] write_count; - - /* Fix FX2 bug */ - always @(posedge usbclk) - if(bus_reset) // Use bus reset because this is on usbclk - write_count <= #1 0; - else if(WR_fx2 & ~write_count[8]) - write_count <= #1 write_count + 9'd1; - else - write_count <= #1 WR_fx2 ? write_count : 9'b0; - - reg WR_fx2_fixed; - reg [15:0]usbdata_fixed; - - always @(posedge usbclk) - begin - WR_fx2_fixed <= WR_fx2 & ~write_count[8]; - usbdata_fixed <= usbdata; - end - - /* Used to convert 16 bits bus_data to the 32 bits wide fifo */ - reg word_complete ; - reg [BUS_WIDTH-1:0] usbdata_delayed ; - reg writing ; - wire [FIFO_WIDTH-1:0] usbdata_packed ; - wire WR_packed ; - - always @(posedge usbclk) - begin - if (bus_reset) - begin - word_complete <= 0 ; - writing <= 0 ; - end - else if (WR_fx2_fixed) - begin - writing <= 1 ; - if (word_complete) - word_complete <= 0 ; - else - begin - usbdata_delayed <= usbdata_fixed ; - word_complete <= 1 ; - end - end - else - writing <= 0 ; - end - - assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ; - assign WR_packed = word_complete & writing ; - - /* Make sure data are sync with usbclk */ - reg [31:0]usbdata_usbclk; - reg WR_usbclk; - - always @(posedge usbclk) - begin - if (WR_packed) - usbdata_usbclk <= usbdata_packed; - WR_usbclk <= WR_packed; - end - - /* Cross clock boundaries */ - reg [FIFO_WIDTH-1:0] usbdata_tx ; - reg WR_tx; - reg WR_1; - reg WR_2; - reg [31:0] usbdata_final; - reg WR_final; - - always @(posedge txclk) usbdata_tx <= usbdata_usbclk; - - always @(posedge txclk) - if (reset) - WR_1 <= 0; - else - WR_1 <= WR_usbclk; - - always @(posedge txclk) - if (reset) - WR_2 <= 0; - else - WR_2 <= WR_1; - - always @(posedge txclk) - begin - if (reset) - WR_tx <= 0; - else - WR_tx <= WR_1 & ~WR_2; - end - - always @(posedge txclk) - begin - if (reset) - WR_final <= 0; - else - begin - WR_final <= WR_tx; - if (WR_tx) - usbdata_final <= usbdata_tx; - end - end - - /* Parse header and forward to ram */ - reg [3:0]reader_state; - reg [4:0]channel ; - reg [9:0]read_length ; - - parameter IDLE = 4'd0; - parameter HEADER = 4'd1; - parameter WAIT = 4'd2; - parameter FORWARD = 4'd3; - - `define CHANNEL 20:16 - `define PKT_SIZE 512 - - always @(posedge txclk) - begin - if (reset) - begin - reader_state <= 0; - WR_channel <= 0; - WR_done_channel <= 0; - end - else - case (reader_state) - IDLE: begin - if (WR_final) - reader_state <= HEADER; - end - - // Store channel and forware header - HEADER: begin - channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL]) ; - WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL])] <= 1; - //channel <= usbdata_final[`CHANNEL] ; - //WR_channel[usbdata_final[`CHANNEL]] <= 1; - ram_data <= usbdata_final; - read_length <= 10'd4 ; - - reader_state <= WAIT; - end - - WAIT: begin - WR_channel[channel] <= 0; - - if (read_length == `PKT_SIZE) - reader_state <= IDLE; - else if (WR_final) - reader_state <= FORWARD; - end - - FORWARD: begin - WR_channel[channel] <= 1; - ram_data <= usbdata_final; - read_length <= read_length + 10'd4; - - reader_state <= WAIT; - end - endcase - end -endmodule \ No newline at end of file diff --git a/megacells/fifo_1kx16.bsf b/megacells/fifo_1kx16.bsf index 329be2d44..2de80816f 100755 --- a/megacells/fifo_1kx16.bsf +++ b/megacells/fifo_1kx16.bsf @@ -95,7 +95,7 @@ applicable agreement for further details. ) (drawing (text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial" )) - (text "almost_empty < 126" (rect 58 122 144 134)(font "Arial" )) + (text "almost_empty < 504" (rect 58 122 144 134)(font "Arial" )) (line (pt 16 16)(pt 144 16)(line_width 1)) (line (pt 144 16)(pt 144 144)(line_width 1)) (line (pt 144 144)(pt 16 144)(line_width 1)) diff --git a/megacells/fifo_1kx16.v b/megacells/fifo_1kx16.v index e22b416e5..4f7e94ef5 100755 --- a/megacells/fifo_1kx16.v +++ b/megacells/fifo_1kx16.v @@ -86,7 +86,7 @@ module fifo_1kx16 ( ); defparam scfifo_component.add_ram_output_register = "OFF", - scfifo_component.almost_empty_value = 126, + scfifo_component.almost_empty_value = 504, scfifo_component.intended_device_family = "Cyclone", scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", scfifo_component.lpm_numwords = 1024, @@ -105,7 +105,7 @@ endmodule // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" @@ -133,7 +133,7 @@ endmodule // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" diff --git a/megacells/fifo_1kx16_bb.v b/megacells/fifo_1kx16_bb.v index 283aada81..9d9912bc2 100755 --- a/megacells/fifo_1kx16_bb.v +++ b/megacells/fifo_1kx16_bb.v @@ -57,7 +57,7 @@ endmodule // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" @@ -85,7 +85,7 @@ endmodule // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" diff --git a/rbf/Makefile.am b/rbf/Makefile.am index 49d2f2592..c7c9ce670 100644 --- a/rbf/Makefile.am +++ b/rbf/Makefile.am @@ -26,8 +26,12 @@ datadir = $(prefix)/share/usrp rbfs = \ rev2/std_2rxhb_2tx.rbf \ rev2/std_4rx_0tx.rbf \ + rev2/inband_1rxhb_1tx.rbf \ + rev2/inband_2rxhb_2tx.rbf \ rev4/std_2rxhb_2tx.rbf \ rev4/std_4rx_0tx.rbf \ + rev4/inband_1rxhb_1tx.rbf \ + rev4/inband_2rxhb_2tx.rbf \ rev2/multi_2rxhb_2tx.rbf \ rev4/multi_2rxhb_2tx.rbf diff --git a/rbf/rev2/inband_1rxhb_1tx.rbf b/rbf/rev2/inband_1rxhb_1tx.rbf new file mode 100755 index 000000000..c1c9af2ce Binary files /dev/null and b/rbf/rev2/inband_1rxhb_1tx.rbf differ diff --git a/rbf/rev2/inband_2rxhb_2tx.rbf b/rbf/rev2/inband_2rxhb_2tx.rbf new file mode 100755 index 000000000..ca1a0f92b Binary files /dev/null and b/rbf/rev2/inband_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/inband_1rxhb_1tx.rbf b/rbf/rev4/inband_1rxhb_1tx.rbf new file mode 100755 index 000000000..c1c9af2ce Binary files /dev/null and b/rbf/rev4/inband_1rxhb_1tx.rbf differ diff --git a/rbf/rev4/inband_2rxhb_2tx.rbf b/rbf/rev4/inband_2rxhb_2tx.rbf new file mode 100755 index 000000000..ca1a0f92b Binary files /dev/null and b/rbf/rev4/inband_2rxhb_2tx.rbf differ diff --git a/toplevel/usrp_inband_usb/config.vh b/toplevel/usrp_inband_usb/config.vh index 3291dc10b..007a529e3 100644 --- a/toplevel/usrp_inband_usb/config.vh +++ b/toplevel/usrp_inband_usb/config.vh @@ -34,7 +34,7 @@ `include "../include/common_config_1rxhb_1tx.vh" // Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels -//`include "../include/common_config_2rxhb_2tx.vh" +// `include "../include/common_config_2rxhb_2tx.vh" // Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels //`include "../include/common_config_4rx_0tx.vh" diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf index c9eebc1ad..ae0807f6f 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1" +set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP2" # Pin & Location Assignments # ========================== @@ -392,7 +392,6 @@ set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v @@ -419,4 +418,6 @@ set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v \ No newline at end of file +set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.v b/toplevel/usrp_inband_usb/usrp_inband_usb.v index cc625b0e7..79f0dfa4a 100644 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.v +++ b/toplevel/usrp_inband_usb/usrp_inband_usb.v @@ -97,8 +97,6 @@ module usrp_inband_usb // Tri-state bus macro bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - assign clk64 = master_clk; - wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; @@ -129,19 +127,7 @@ module usrp_inband_usb assign bb_tx_q0 = ch1tx; assign bb_tx_i1 = ch2tx; assign bb_tx_q1 = ch3tx; - -wire [6:0] reg_addr; -wire [31:0] reg_data_out; -wire [31:0] reg_data_in; -wire [1:0] reg_io_enable; -wire [31:0] rssi_threshhold; -wire [31:0] rssi_wait; - -register_io register_control -(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in), - .dataout(reg_data_out),.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), - .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait)); -wire [1:0] tx_overrun; + wire [1:0] tx_underrun; `ifdef TX_IN_BAND @@ -164,9 +150,15 @@ wire [1:0] tx_underrun; .reg_data_out(reg_data_out), .reg_data_in(reg_data_in), .reg_io_enable(reg_io_enable), - .debugbus(), + .debugbus(rx_debugbus), .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), - .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait)); + .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait), + .stop(stop), .stop_time(stop_time)); + + `ifdef TX_DUAL + defparam tx_buffer.NUM_CHAN=2; + `endif + `else tx_buffer tx_buffer ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), @@ -276,14 +268,18 @@ wire [1:0] tx_underrun; .ch_6(ch6rx),.ch_7(ch7rx), .rxclk(clk64),.rxstrobe(hb_strobe), .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), .rx_WR(rx_WR), .rx_databus(rx_databus), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled), .debugbus(tx_debugbus), .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3), - .tx_overrun(tx_overrun), .tx_underrun(tx_underrun)); + .tx_underrun(tx_underrun)); + + `ifdef RX_DUAL + defparam rx_buffer.NUM_CHAN=2; + `endif + `else rx_buffer rx_buffer ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), @@ -357,11 +353,52 @@ wire [1:0] tx_underrun; serial_io serial_io ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db), .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) ); + wire [6:0] reg_addr; + wire [31:0] reg_data_out; + wire [31:0] reg_data_in; + wire [1:0] reg_io_enable; + wire [31:0] rssi_threshhold; + wire [31:0] rssi_wait; + wire [6:0] addr_wr; + wire [31:0] data_wr; + wire strobe_wr; + wire [6:0] addr_db; + wire [31:0] data_db; + wire strobe_db; + assign serial_strobe = strobe_db | strobe_wr; + assign serial_addr = (strobe_db)? (addr_db) : (addr_wr); + assign serial_data = (strobe_db)? (data_db) : (data_wr); + //assign serial_strobe = strobe_wr; + //assign serial_data = data_wr; + //assign serial_addr = addr_wr; + + register_io register_control + (.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in), + .dataout(reg_data_out), .addr_wr(addr_wr), .data_wr(data_wr), .strobe_wr(strobe_wr), + .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), + .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .debug_en(debug_en), .misc(settings), + .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + + //implementing freeze mode + reg [15:0] timestop; + wire stop; + wire [15:0] stop_time; + assign clk64 = (timestop == 0) ? master_clk : 0; + always @(posedge master_clk) + if (timestop[15:0] != 0) + timestop <= timestop - 16'd1; + else if (stop) + timestop <= stop_time; + + wire [15:0] reg_0,reg_1,reg_2,reg_3; master_control master_control ( .master_clk(clk64),.usbclk(usbclk), @@ -374,8 +411,8 @@ wire [1:0] tx_underrun; .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), .tx_empty(tx_empty), //.debug_0(rx_a_a),.debug_1(ddc0_in_i), - .debug_0(tx_debugbus),.debug_1(tx_debugbus), - .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,(tx_underrun == 0),rx_overrun,decim_rate}), + .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); io_pins io_pins -- cgit v1.2.3 From 69bef1c19b287244a4f3fb04cadc06ec49ca328a Mon Sep 17 00:00:00 2001 From: matt Date: Tue, 2 Sep 2008 19:50:09 +0000 Subject: Allows for changing the interpolation rate dynamically. Stop the pipeline, set the rate, restart the pipeline. Fixes bug #248. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9485 221aa14e-8319-0410-a670-987f0aec2ac5 --- sdr_lib/cic_interp.v | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sdr_lib/cic_interp.v b/sdr_lib/cic_interp.v index 732f82ce0..32d106861 100755 --- a/sdr_lib/cic_interp.v +++ b/sdr_lib/cic_interp.v @@ -45,11 +45,12 @@ module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_ sign_extend #(bw,bw+maxbitgain) ext_input (.in(signal_in),.out(signal_in_ext)); - + + wire clear_me = reset | ~enable; //FIXME Note that this section has pipe and diff reversed // It still works, but is confusing always @(posedge clock) - if(reset) + if(clear_me) for(i=0;i Date: Thu, 26 Feb 2009 23:39:17 +0000 Subject: Merged r10504:10528 from michaelld/fix_local_data_install into trunk. Trunk passes distcheck. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10529 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/Makefile.am | 35 ++--------------------------------- rbf/rev2/Makefile.am | 31 +++++++++++++++++++++++++++++++ rbf/rev4/Makefile.am | 31 +++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 33 deletions(-) create mode 100644 rbf/rev2/Makefile.am create mode 100644 rbf/rev4/Makefile.am diff --git a/rbf/Makefile.am b/rbf/Makefile.am index c7c9ce670..7bce77d5f 100644 --- a/rbf/Makefile.am +++ b/rbf/Makefile.am @@ -1,5 +1,5 @@ # -# Copyright 2005,2006 Free Software Foundation, Inc. +# Copyright 2005,2006,2009 Free Software Foundation, Inc. # # This file is part of GNU Radio # @@ -19,35 +19,4 @@ # Boston, MA 02110-1301, USA. # -include $(top_srcdir)/Makefile.common - -datadir = $(prefix)/share/usrp - -rbfs = \ - rev2/std_2rxhb_2tx.rbf \ - rev2/std_4rx_0tx.rbf \ - rev2/inband_1rxhb_1tx.rbf \ - rev2/inband_2rxhb_2tx.rbf \ - rev4/std_2rxhb_2tx.rbf \ - rev4/std_4rx_0tx.rbf \ - rev4/inband_1rxhb_1tx.rbf \ - rev4/inband_2rxhb_2tx.rbf \ - rev2/multi_2rxhb_2tx.rbf \ - rev4/multi_2rxhb_2tx.rbf - - -EXTRA_DIST = \ - $(rbfs) - - -install-data-local: - @for file in $(rbfs); do \ - echo "$(INSTALL_DATA) $(srcdir)/$$file $(DESTDIR)$(datadir)/$$file"; \ - $(INSTALL_DATA) $(srcdir)/$$file $(DESTDIR)$(datadir)/$$file; \ - done - -uninstall-local: - @for file in $(rbfs); do \ - echo "$(RM) $(DESTDIR)$(datadir)/$$file"; \ - $(RM) $(DESTDIR)$(datadir)/$$file; \ - done +SUBDIRS = rev2 rev4 diff --git a/rbf/rev2/Makefile.am b/rbf/rev2/Makefile.am new file mode 100644 index 000000000..487650e18 --- /dev/null +++ b/rbf/rev2/Makefile.am @@ -0,0 +1,31 @@ +# +# Copyright 2009 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +include $(top_srcdir)/Makefile.common + +rbf2datadir = $(prefix)/share/usrp/rev2 + +dist_rbf2data_DATA = \ + std_2rxhb_2tx.rbf \ + std_4rx_0tx.rbf \ + inband_1rxhb_1tx.rbf \ + inband_2rxhb_2tx.rbf \ + multi_2rxhb_2tx.rbf diff --git a/rbf/rev4/Makefile.am b/rbf/rev4/Makefile.am new file mode 100644 index 000000000..54de9b818 --- /dev/null +++ b/rbf/rev4/Makefile.am @@ -0,0 +1,31 @@ +# +# Copyright 2009 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +include $(top_srcdir)/Makefile.common + +rbf4datadir = $(prefix)/share/usrp/rev4 + +dist_rbf4data_DATA = \ + std_2rxhb_2tx.rbf \ + std_4rx_0tx.rbf \ + inband_1rxhb_1tx.rbf \ + inband_2rxhb_2tx.rbf \ + multi_2rxhb_2tx.rbf -- cgit v1.2.3 From aa2933945bf53f11083ac5b272c1d0c4d0b39b49 Mon Sep 17 00:00:00 2001 From: eb Date: Tue, 12 May 2009 21:17:27 +0000 Subject: Built and checked in new rbfs that fix ticket:248 and ticket:290. The rbfs are built from r11012 and were compiled using Quartus II Version 7.1 build 178 06/25/2007 SP 1 SJ Web Edition. ticket:248 was actually fixed in [9485], but the updated rbfs were never checked in. Ticket:290 wasn't really a bug. The host code has always been correct. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11014 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev2/std_2rxhb_2tx.rbf | Bin 181148 -> 181588 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 181148 -> 181588 bytes 2 files changed, 0 insertions(+), 0 deletions(-) diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf index f09848704..ee3c30d66 100755 Binary files a/rbf/rev2/std_2rxhb_2tx.rbf and b/rbf/rev2/std_2rxhb_2tx.rbf differ diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index f09848704..ee3c30d66 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ -- cgit v1.2.3 From 0e3a462242cdcb2e664cbc87db84636bd545c774 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Tue, 14 Jul 2009 17:17:45 +0000 Subject: Reorganization of debian package directory git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11424 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std.qsf | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index e0bac4893..2ef4727e3 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1" +set_global_assignment -name LAST_QUARTUS_VERSION 8.1 # Pin & Location Assignments # ========================== @@ -368,7 +368,7 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk # end ENTITY(usrp_std) # -------------------- -set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v @@ -406,4 +406,7 @@ set_global_assignment -name VERILOG_FILE usrp_std.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file -- cgit v1.2.3 From 569ef2d1e0030c41098b5501eefef6b8c6f220bb Mon Sep 17 00:00:00 2001 From: jcorgan Date: Tue, 14 Jul 2009 17:21:04 +0000 Subject: Revert erroneous file included in r11424 git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11425 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std.qsf | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index 2ef4727e3..e0bac4893 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION 8.1 +set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1" # Pin & Location Assignments # ========================== @@ -368,7 +368,7 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk # end ENTITY(usrp_std) # -------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v @@ -406,7 +406,4 @@ set_global_assignment -name VERILOG_FILE usrp_std.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file -- cgit v1.2.3 From 320c70016f8798cb73c8d02eaa3728df48b5b3ab Mon Sep 17 00:00:00 2001 From: git repository hosting Date: Thu, 13 Aug 2009 22:26:53 -0600 Subject: Added git ignore files auto created from svn:ignore properties. --- .gitignore | 2 ++ megacells/.gitignore | 1 + rbf/.gitignore | 4 ++++ rbf/rev2/.gitignore | 2 ++ rbf/rev4/.gitignore | 2 ++ sdr_lib/.gitignore | 2 ++ tb/.gitignore | 3 +++ toplevel/mrfm/.gitignore | 17 +++++++++++++++++ toplevel/sizetest/.gitignore | 15 +++++++++++++++ toplevel/usrp_inband_usb/.gitignore | 16 ++++++++++++++++ toplevel/usrp_multi/.gitignore | 16 ++++++++++++++++ toplevel/usrp_std/.gitignore | 17 +++++++++++++++++ 12 files changed, 97 insertions(+) create mode 100644 .gitignore create mode 100644 megacells/.gitignore create mode 100644 rbf/.gitignore create mode 100644 rbf/rev2/.gitignore create mode 100644 rbf/rev4/.gitignore create mode 100644 sdr_lib/.gitignore create mode 100644 tb/.gitignore create mode 100644 toplevel/mrfm/.gitignore create mode 100644 toplevel/sizetest/.gitignore create mode 100644 toplevel/usrp_inband_usb/.gitignore create mode 100644 toplevel/usrp_multi/.gitignore create mode 100644 toplevel/usrp_std/.gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..b336cc7ce --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +/Makefile +/Makefile.in diff --git a/megacells/.gitignore b/megacells/.gitignore new file mode 100644 index 000000000..c2de89b27 --- /dev/null +++ b/megacells/.gitignore @@ -0,0 +1 @@ +/db diff --git a/rbf/.gitignore b/rbf/.gitignore new file mode 100644 index 000000000..eb58a95f5 --- /dev/null +++ b/rbf/.gitignore @@ -0,0 +1,4 @@ +/Makefile +/Makefile.in +/usrp_fpga_rev1.rbf +/usrp_fpga_rev2.rbf diff --git a/rbf/rev2/.gitignore b/rbf/rev2/.gitignore new file mode 100644 index 000000000..b336cc7ce --- /dev/null +++ b/rbf/rev2/.gitignore @@ -0,0 +1,2 @@ +/Makefile +/Makefile.in diff --git a/rbf/rev4/.gitignore b/rbf/rev4/.gitignore new file mode 100644 index 000000000..b336cc7ce --- /dev/null +++ b/rbf/rev4/.gitignore @@ -0,0 +1,2 @@ +/Makefile +/Makefile.in diff --git a/sdr_lib/.gitignore b/sdr_lib/.gitignore new file mode 100644 index 000000000..e7fc78c42 --- /dev/null +++ b/sdr_lib/.gitignore @@ -0,0 +1,2 @@ +/db +/*.vcd diff --git a/tb/.gitignore b/tb/.gitignore new file mode 100644 index 000000000..6bc85aa2d --- /dev/null +++ b/tb/.gitignore @@ -0,0 +1,3 @@ +/*.vcd +/*.out +/fullchip_tb diff --git a/toplevel/mrfm/.gitignore b/toplevel/mrfm/.gitignore new file mode 100644 index 000000000..fe06aad0d --- /dev/null +++ b/toplevel/mrfm/.gitignore @@ -0,0 +1,17 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/*.summary +/a.out +/db diff --git a/toplevel/sizetest/.gitignore b/toplevel/sizetest/.gitignore new file mode 100644 index 000000000..201434ddc --- /dev/null +++ b/toplevel/sizetest/.gitignore @@ -0,0 +1,15 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/db diff --git a/toplevel/usrp_inband_usb/.gitignore b/toplevel/usrp_inband_usb/.gitignore new file mode 100644 index 000000000..2cc25f0f2 --- /dev/null +++ b/toplevel/usrp_inband_usb/.gitignore @@ -0,0 +1,16 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/*.summary +/db diff --git a/toplevel/usrp_multi/.gitignore b/toplevel/usrp_multi/.gitignore new file mode 100644 index 000000000..2cc25f0f2 --- /dev/null +++ b/toplevel/usrp_multi/.gitignore @@ -0,0 +1,16 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/*.summary +/db diff --git a/toplevel/usrp_std/.gitignore b/toplevel/usrp_std/.gitignore new file mode 100644 index 000000000..31d6ea9ef --- /dev/null +++ b/toplevel/usrp_std/.gitignore @@ -0,0 +1,17 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/*.summary +/prev* +/db -- cgit v1.2.3 From a170b9b42345794429486dd4f3316e84ea2cc871 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Jan 2010 11:46:58 -0800 Subject: Moved usrp1 fpga files into usrp1 subdir. --- Makefile.am | 24 - Makefile.extra | 181 - TODO | 23 - gen_makefile_extra.py | 67 - inband_lib/chan_fifo_reader.v | 219 -- inband_lib/channel_demux.v | 78 - inband_lib/channel_ram.v | 107 - inband_lib/cmd_reader.v | 305 -- inband_lib/packet_builder.v | 152 - inband_lib/register_io.v | 82 - inband_lib/rx_buffer_inband.v | 209 -- inband_lib/tx_buffer_inband.v | 143 - inband_lib/tx_packer.v | 119 - inband_lib/usb_packet_fifo.v | 112 - megacells/.gitignore | 1 - megacells/accum32.bsf | 86 - megacells/accum32.cmp | 31 - megacells/accum32.inc | 32 - megacells/accum32.v | 765 ----- megacells/accum32_bb.v | 35 - megacells/accum32_inst.v | 7 - megacells/add32.bsf | 62 - megacells/add32.cmp | 29 - megacells/add32.inc | 30 - megacells/add32.v | 221 -- megacells/add32_bb.v | 31 - megacells/add32_inst.v | 5 - megacells/addsub16.bsf | 96 - megacells/addsub16.cmp | 33 - megacells/addsub16.inc | 34 - megacells/addsub16.v | 438 --- megacells/addsub16_bb.v | 39 - megacells/addsub16_inst.v | 9 - megacells/bustri.bsf | 62 - megacells/bustri.cmp | 29 - megacells/bustri.inc | 30 - megacells/bustri.v | 71 - megacells/bustri_bb.v | 31 - megacells/bustri_inst.v | 5 - megacells/clk_doubler.v | 198 -- megacells/clk_doubler_bb.v | 143 - megacells/dspclkpll.v | 237 -- megacells/dspclkpll_bb.v | 31 - megacells/fifo_1kx16.bsf | 107 - megacells/fifo_1kx16.cmp | 30 - megacells/fifo_1kx16.inc | 31 - megacells/fifo_1kx16.v | 175 - megacells/fifo_1kx16_bb.v | 127 - megacells/fifo_1kx16_inst.v | 12 - megacells/fifo_2k.v | 3343 ------------------- megacells/fifo_2k_bb.v | 131 - megacells/fifo_4k.v | 3495 -------------------- megacells/fifo_4k_18.v | 186 -- megacells/fifo_4k_bb.v | 131 - megacells/fifo_4kx16_dc.bsf | 117 - megacells/fifo_4kx16_dc.cmp | 31 - megacells/fifo_4kx16_dc.inc | 32 - megacells/fifo_4kx16_dc.v | 178 - megacells/fifo_4kx16_dc_bb.v | 130 - megacells/fifo_4kx16_dc_inst.v | 13 - megacells/mylpm_addsub.bsf | 80 - megacells/mylpm_addsub.cmp | 31 - megacells/mylpm_addsub.inc | 32 - megacells/mylpm_addsub.v | 102 - megacells/mylpm_addsub_bb.v | 35 - megacells/mylpm_addsub_inst.v | 7 - megacells/pll.v | 207 -- megacells/pll_bb.v | 29 - megacells/pll_inst.v | 4 - megacells/sub32.bsf | 87 - megacells/sub32.cmp | 32 - megacells/sub32.inc | 33 - megacells/sub32.v | 675 ---- megacells/sub32_bb.v | 37 - megacells/sub32_inst.v | 8 - models/bustri.v | 17 - models/fifo.v | 82 - models/fifo_1c_1k.v | 81 - models/fifo_1c_2k.v | 81 - models/fifo_1c_4k.v | 76 - models/fifo_1k.v | 24 - models/fifo_2k.v | 24 - models/fifo_4k.v | 24 - models/fifo_4k_18.v | 26 - models/pll.v | 33 - models/ssram.v | 38 - rbf/.gitignore | 4 - rbf/Makefile.am | 22 - rbf/rev2/.gitignore | 2 - rbf/rev2/Makefile.am | 31 - rbf/rev2/inband_1rxhb_1tx.rbf | Bin 161180 -> 0 bytes rbf/rev2/inband_2rxhb_2tx.rbf | Bin 191849 -> 0 bytes rbf/rev2/multi_2rxhb_2tx.rbf | Bin 180809 -> 0 bytes rbf/rev2/multi_4rx_0tx.rbf | Bin 180537 -> 0 bytes rbf/rev2/std_2rxhb_2tx.rbf | Bin 181588 -> 0 bytes rbf/rev2/std_4rx_0tx.rbf | Bin 183046 -> 0 bytes rbf/rev4/.gitignore | 2 - rbf/rev4/Makefile.am | 31 - rbf/rev4/inband_1rxhb_1tx.rbf | Bin 161180 -> 0 bytes rbf/rev4/inband_2rxhb_2tx.rbf | Bin 191849 -> 0 bytes rbf/rev4/multi_2rxhb_2tx.rbf | Bin 180809 -> 0 bytes rbf/rev4/multi_4rx_0tx.rbf | Bin 180537 -> 0 bytes rbf/rev4/std_2rxhb_2tx.rbf | Bin 181588 -> 0 bytes rbf/rev4/std_4rx_0tx.rbf | Bin 183046 -> 0 bytes sdr_lib/.gitignore | 2 - sdr_lib/adc_interface.v | 71 - sdr_lib/atr_delay.v | 83 - sdr_lib/bidir_reg.v | 29 - sdr_lib/cic_dec_shifter.v | 100 - sdr_lib/cic_decim.v | 93 - sdr_lib/cic_int_shifter.v | 94 - sdr_lib/cic_interp.v | 90 - sdr_lib/clk_divider.v | 43 - sdr_lib/cordic.v | 109 - sdr_lib/cordic_stage.v | 60 - sdr_lib/ddc.v | 97 - sdr_lib/dpram.v | 47 - sdr_lib/duc.v | 95 - sdr_lib/ext_fifo.v | 126 - sdr_lib/gen_cordic_consts.py | 10 - sdr_lib/gen_sync.v | 43 - sdr_lib/hb/acc.v | 22 - sdr_lib/hb/coeff_rom.v | 19 - sdr_lib/hb/halfband_decim.v | 163 - sdr_lib/hb/halfband_interp.v | 121 - sdr_lib/hb/hbd_tb/HBD | 80 - sdr_lib/hb/hbd_tb/really_golden | 142 - sdr_lib/hb/hbd_tb/regression | 95 - sdr_lib/hb/hbd_tb/run_hbd | 4 - sdr_lib/hb/hbd_tb/test_hbd.v | 75 - sdr_lib/hb/mac.v | 58 - sdr_lib/hb/mult.v | 16 - sdr_lib/hb/ram16_2port.v | 22 - sdr_lib/hb/ram16_2sum.v | 27 - sdr_lib/hb/ram32_2sum.v | 22 - sdr_lib/io_pins.v | 52 - sdr_lib/master_control.v | 163 - sdr_lib/master_control_multi.v | 73 - sdr_lib/phase_acc.v | 52 - sdr_lib/ram.v | 16 - sdr_lib/ram16.v | 17 - sdr_lib/ram32.v | 17 - sdr_lib/ram64.v | 16 - sdr_lib/rssi.v | 30 - sdr_lib/rx_buffer.v | 237 -- sdr_lib/rx_chain.v | 106 - sdr_lib/rx_chain_dual.v | 103 - sdr_lib/rx_dcoffset.v | 22 - sdr_lib/serial_io.v | 118 - sdr_lib/setting_reg.v | 23 - sdr_lib/setting_reg_masked.v | 26 - sdr_lib/sign_extend.v | 35 - sdr_lib/strobe_gen.v | 46 - sdr_lib/tx_buffer.v | 170 - sdr_lib/tx_chain.v | 65 - sdr_lib/tx_chain_hb.v | 76 - tb/.gitignore | 3 - tb/cbus_tb.v | 71 - tb/cordic_tb.v | 61 - tb/decim_tb.v | 108 - tb/fullchip_tb.v | 174 - tb/interp_tb.v | 108 - tb/justinterp_tb.v | 73 - tb/makesine.pl | 14 - tb/run_cordic | 4 - tb/run_fullchip | 4 - tb/usrp_tasks.v | 145 - toplevel/include/common_config_1rxhb_1tx.vh | 61 - toplevel/include/common_config_2rx_0tx.vh | 61 - toplevel/include/common_config_2rxhb_0tx.vh | 61 - toplevel/include/common_config_2rxhb_2tx.vh | 61 - toplevel/include/common_config_4rx_0tx.vh | 61 - toplevel/include/common_config_bottom.vh | 104 - toplevel/mrfm/.gitignore | 17 - toplevel/mrfm/biquad_2stage.v | 131 - toplevel/mrfm/biquad_6stage.v | 137 - toplevel/mrfm/mrfm.csf | 444 --- toplevel/mrfm/mrfm.esf | 14 - toplevel/mrfm/mrfm.psf | 312 -- toplevel/mrfm/mrfm.py | 129 - toplevel/mrfm/mrfm.qpf | 29 - toplevel/mrfm/mrfm.qsf | 411 --- toplevel/mrfm/mrfm.v | 199 -- toplevel/mrfm/mrfm.vh | 21 - toplevel/mrfm/mrfm_compensator.v | 80 - toplevel/mrfm/mrfm_fft.py | 319 -- toplevel/mrfm/mrfm_proc.v | 96 - toplevel/mrfm/shifter.v | 106 - toplevel/sizetest/.gitignore | 15 - toplevel/sizetest/sizetest.csf | 160 - toplevel/sizetest/sizetest.psf | 228 -- toplevel/sizetest/sizetest.quartus | 19 - toplevel/sizetest/sizetest.ssf | 14 - toplevel/sizetest/sizetest.v | 39 - toplevel/usrp_inband_usb/.gitignore | 16 - toplevel/usrp_inband_usb/config.vh | 53 - toplevel/usrp_inband_usb/usrp_inband_usb.csf | 444 --- toplevel/usrp_inband_usb/usrp_inband_usb.esf | 14 - toplevel/usrp_inband_usb/usrp_inband_usb.psf | 312 -- toplevel/usrp_inband_usb/usrp_inband_usb.qpf | 29 - toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 423 --- toplevel/usrp_inband_usb/usrp_inband_usb.v | 428 --- toplevel/usrp_multi/.gitignore | 16 - toplevel/usrp_multi/config.vh | 62 - toplevel/usrp_multi/usrp_multi.csf | 444 --- toplevel/usrp_multi/usrp_multi.esf | 14 - toplevel/usrp_multi/usrp_multi.psf | 312 -- toplevel/usrp_multi/usrp_multi.qpf | 29 - toplevel/usrp_multi/usrp_multi.qsf | 408 --- toplevel/usrp_multi/usrp_multi.v | 379 --- toplevel/usrp_std/.gitignore | 17 - toplevel/usrp_std/config.vh | 53 - toplevel/usrp_std/usrp_std.csf | 444 --- toplevel/usrp_std/usrp_std.esf | 14 - toplevel/usrp_std/usrp_std.psf | 312 -- toplevel/usrp_std/usrp_std.qpf | 29 - toplevel/usrp_std/usrp_std.qsf | 409 --- toplevel/usrp_std/usrp_std.v | 333 -- usrp1/Makefile.am | 24 + usrp1/Makefile.extra | 181 + usrp1/TODO | 23 + usrp1/gen_makefile_extra.py | 67 + usrp1/inband_lib/chan_fifo_reader.v | 219 ++ usrp1/inband_lib/channel_demux.v | 78 + usrp1/inband_lib/channel_ram.v | 107 + usrp1/inband_lib/cmd_reader.v | 305 ++ usrp1/inband_lib/packet_builder.v | 152 + usrp1/inband_lib/register_io.v | 82 + usrp1/inband_lib/rx_buffer_inband.v | 209 ++ usrp1/inband_lib/tx_buffer_inband.v | 143 + usrp1/inband_lib/tx_packer.v | 119 + usrp1/inband_lib/usb_packet_fifo.v | 112 + usrp1/megacells/.gitignore | 1 + usrp1/megacells/accum32.bsf | 86 + usrp1/megacells/accum32.cmp | 31 + usrp1/megacells/accum32.inc | 32 + usrp1/megacells/accum32.v | 765 +++++ usrp1/megacells/accum32_bb.v | 35 + usrp1/megacells/accum32_inst.v | 7 + usrp1/megacells/add32.bsf | 62 + usrp1/megacells/add32.cmp | 29 + usrp1/megacells/add32.inc | 30 + usrp1/megacells/add32.v | 221 ++ usrp1/megacells/add32_bb.v | 31 + usrp1/megacells/add32_inst.v | 5 + usrp1/megacells/addsub16.bsf | 96 + usrp1/megacells/addsub16.cmp | 33 + usrp1/megacells/addsub16.inc | 34 + usrp1/megacells/addsub16.v | 438 +++ usrp1/megacells/addsub16_bb.v | 39 + usrp1/megacells/addsub16_inst.v | 9 + usrp1/megacells/bustri.bsf | 62 + usrp1/megacells/bustri.cmp | 29 + usrp1/megacells/bustri.inc | 30 + usrp1/megacells/bustri.v | 71 + usrp1/megacells/bustri_bb.v | 31 + usrp1/megacells/bustri_inst.v | 5 + usrp1/megacells/clk_doubler.v | 198 ++ usrp1/megacells/clk_doubler_bb.v | 143 + usrp1/megacells/dspclkpll.v | 237 ++ usrp1/megacells/dspclkpll_bb.v | 31 + usrp1/megacells/fifo_1kx16.bsf | 107 + usrp1/megacells/fifo_1kx16.cmp | 30 + usrp1/megacells/fifo_1kx16.inc | 31 + usrp1/megacells/fifo_1kx16.v | 175 + usrp1/megacells/fifo_1kx16_bb.v | 127 + usrp1/megacells/fifo_1kx16_inst.v | 12 + usrp1/megacells/fifo_2k.v | 3343 +++++++++++++++++++ usrp1/megacells/fifo_2k_bb.v | 131 + usrp1/megacells/fifo_4k.v | 3495 ++++++++++++++++++++ usrp1/megacells/fifo_4k_18.v | 186 ++ usrp1/megacells/fifo_4k_bb.v | 131 + usrp1/megacells/fifo_4kx16_dc.bsf | 117 + usrp1/megacells/fifo_4kx16_dc.cmp | 31 + usrp1/megacells/fifo_4kx16_dc.inc | 32 + usrp1/megacells/fifo_4kx16_dc.v | 178 + usrp1/megacells/fifo_4kx16_dc_bb.v | 130 + usrp1/megacells/fifo_4kx16_dc_inst.v | 13 + usrp1/megacells/mylpm_addsub.bsf | 80 + usrp1/megacells/mylpm_addsub.cmp | 31 + usrp1/megacells/mylpm_addsub.inc | 32 + usrp1/megacells/mylpm_addsub.v | 102 + usrp1/megacells/mylpm_addsub_bb.v | 35 + usrp1/megacells/mylpm_addsub_inst.v | 7 + usrp1/megacells/pll.v | 207 ++ usrp1/megacells/pll_bb.v | 29 + usrp1/megacells/pll_inst.v | 4 + usrp1/megacells/sub32.bsf | 87 + usrp1/megacells/sub32.cmp | 32 + usrp1/megacells/sub32.inc | 33 + usrp1/megacells/sub32.v | 675 ++++ usrp1/megacells/sub32_bb.v | 37 + usrp1/megacells/sub32_inst.v | 8 + usrp1/models/bustri.v | 17 + usrp1/models/fifo.v | 82 + usrp1/models/fifo_1c_1k.v | 81 + usrp1/models/fifo_1c_2k.v | 81 + usrp1/models/fifo_1c_4k.v | 76 + usrp1/models/fifo_1k.v | 24 + usrp1/models/fifo_2k.v | 24 + usrp1/models/fifo_4k.v | 24 + usrp1/models/fifo_4k_18.v | 26 + usrp1/models/pll.v | 33 + usrp1/models/ssram.v | 38 + usrp1/rbf/.gitignore | 4 + usrp1/rbf/Makefile.am | 22 + usrp1/rbf/rev2/.gitignore | 2 + usrp1/rbf/rev2/Makefile.am | 31 + usrp1/rbf/rev2/inband_1rxhb_1tx.rbf | Bin 0 -> 161180 bytes usrp1/rbf/rev2/inband_2rxhb_2tx.rbf | Bin 0 -> 191849 bytes usrp1/rbf/rev2/multi_2rxhb_2tx.rbf | Bin 0 -> 180809 bytes usrp1/rbf/rev2/multi_4rx_0tx.rbf | Bin 0 -> 180537 bytes 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create mode 100644 usrp1/sdr_lib/hb/mult.v create mode 100644 usrp1/sdr_lib/hb/ram16_2port.v create mode 100644 usrp1/sdr_lib/hb/ram16_2sum.v create mode 100644 usrp1/sdr_lib/hb/ram32_2sum.v create mode 100644 usrp1/sdr_lib/io_pins.v create mode 100644 usrp1/sdr_lib/master_control.v create mode 100644 usrp1/sdr_lib/master_control_multi.v create mode 100755 usrp1/sdr_lib/phase_acc.v create mode 100644 usrp1/sdr_lib/ram.v create mode 100644 usrp1/sdr_lib/ram16.v create mode 100644 usrp1/sdr_lib/ram32.v create mode 100644 usrp1/sdr_lib/ram64.v create mode 100644 usrp1/sdr_lib/rssi.v create mode 100644 usrp1/sdr_lib/rx_buffer.v create mode 100644 usrp1/sdr_lib/rx_chain.v create mode 100644 usrp1/sdr_lib/rx_chain_dual.v create mode 100644 usrp1/sdr_lib/rx_dcoffset.v create mode 100644 usrp1/sdr_lib/serial_io.v create mode 100644 usrp1/sdr_lib/setting_reg.v create mode 100644 usrp1/sdr_lib/setting_reg_masked.v create mode 100644 usrp1/sdr_lib/sign_extend.v create mode 100644 usrp1/sdr_lib/strobe_gen.v create mode 100644 usrp1/sdr_lib/tx_buffer.v create mode 100644 usrp1/sdr_lib/tx_chain.v create mode 100644 usrp1/sdr_lib/tx_chain_hb.v create mode 100644 usrp1/tb/.gitignore create mode 100644 usrp1/tb/cbus_tb.v create mode 100644 usrp1/tb/cordic_tb.v create mode 100644 usrp1/tb/decim_tb.v create mode 100755 usrp1/tb/fullchip_tb.v create mode 100755 usrp1/tb/interp_tb.v create mode 100644 usrp1/tb/justinterp_tb.v create mode 100755 usrp1/tb/makesine.pl create mode 100755 usrp1/tb/run_cordic create mode 100755 usrp1/tb/run_fullchip create mode 100755 usrp1/tb/usrp_tasks.v create mode 100644 usrp1/toplevel/include/common_config_1rxhb_1tx.vh create mode 100644 usrp1/toplevel/include/common_config_2rx_0tx.vh create mode 100644 usrp1/toplevel/include/common_config_2rxhb_0tx.vh create mode 100644 usrp1/toplevel/include/common_config_2rxhb_2tx.vh create mode 100644 usrp1/toplevel/include/common_config_4rx_0tx.vh create mode 100644 usrp1/toplevel/include/common_config_bottom.vh create mode 100644 usrp1/toplevel/mrfm/.gitignore create mode 100644 usrp1/toplevel/mrfm/biquad_2stage.v create mode 100644 usrp1/toplevel/mrfm/biquad_6stage.v create mode 100644 usrp1/toplevel/mrfm/mrfm.csf create mode 100644 usrp1/toplevel/mrfm/mrfm.esf create mode 100644 usrp1/toplevel/mrfm/mrfm.psf create mode 100644 usrp1/toplevel/mrfm/mrfm.py create mode 100644 usrp1/toplevel/mrfm/mrfm.qpf create mode 100644 usrp1/toplevel/mrfm/mrfm.qsf create mode 100644 usrp1/toplevel/mrfm/mrfm.v create mode 100644 usrp1/toplevel/mrfm/mrfm.vh create mode 100644 usrp1/toplevel/mrfm/mrfm_compensator.v create mode 100755 usrp1/toplevel/mrfm/mrfm_fft.py create mode 100644 usrp1/toplevel/mrfm/mrfm_proc.v create mode 100644 usrp1/toplevel/mrfm/shifter.v create mode 100644 usrp1/toplevel/sizetest/.gitignore create mode 100644 usrp1/toplevel/sizetest/sizetest.csf create mode 100644 usrp1/toplevel/sizetest/sizetest.psf create mode 100644 usrp1/toplevel/sizetest/sizetest.quartus create mode 100644 usrp1/toplevel/sizetest/sizetest.ssf create mode 100644 usrp1/toplevel/sizetest/sizetest.v create mode 100644 usrp1/toplevel/usrp_inband_usb/.gitignore create mode 100644 usrp1/toplevel/usrp_inband_usb/config.vh create mode 100644 usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.csf create mode 100644 usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.esf create mode 100644 usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.psf create mode 100644 usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qpf create mode 100644 usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qsf create mode 100644 usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v create mode 100644 usrp1/toplevel/usrp_multi/.gitignore create mode 100644 usrp1/toplevel/usrp_multi/config.vh create mode 100644 usrp1/toplevel/usrp_multi/usrp_multi.csf create mode 100644 usrp1/toplevel/usrp_multi/usrp_multi.esf create mode 100644 usrp1/toplevel/usrp_multi/usrp_multi.psf create mode 100644 usrp1/toplevel/usrp_multi/usrp_multi.qpf create mode 100644 usrp1/toplevel/usrp_multi/usrp_multi.qsf create mode 100644 usrp1/toplevel/usrp_multi/usrp_multi.v create mode 100644 usrp1/toplevel/usrp_std/.gitignore create mode 100644 usrp1/toplevel/usrp_std/config.vh create mode 100644 usrp1/toplevel/usrp_std/usrp_std.csf create mode 100644 usrp1/toplevel/usrp_std/usrp_std.esf create mode 100644 usrp1/toplevel/usrp_std/usrp_std.psf create mode 100644 usrp1/toplevel/usrp_std/usrp_std.qpf create mode 100644 usrp1/toplevel/usrp_std/usrp_std.qsf create mode 100644 usrp1/toplevel/usrp_std/usrp_std.v diff --git a/Makefile.am b/Makefile.am deleted file mode 100644 index 8721af4a7..000000000 --- a/Makefile.am +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright 2004,2005,2006 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -SUBDIRS = rbf - -include Makefile.extra diff --git a/Makefile.extra b/Makefile.extra deleted file mode 100644 index 56df23c98..000000000 --- a/Makefile.extra +++ /dev/null @@ -1,181 +0,0 @@ -EXTRA_DIST = \ - gen_makefile_extra.py \ - inband_lib/chan_fifo_reader.v \ - inband_lib/channel_demux.v \ - inband_lib/channel_ram.v \ - inband_lib/cmd_reader.v \ - inband_lib/packet_builder.v \ - inband_lib/register_io.v \ - inband_lib/rx_buffer_inband.v \ - inband_lib/tx_buffer_inband.v \ - inband_lib/tx_packer.v \ - inband_lib/usb_packet_fifo.v \ - megacells/accum32.bsf \ - megacells/accum32.cmp \ - megacells/accum32.inc \ - megacells/accum32.v \ - megacells/accum32_bb.v \ - megacells/accum32_inst.v \ - megacells/add32.bsf \ - megacells/add32.cmp \ - megacells/add32.inc \ - megacells/add32.v \ - megacells/add32_bb.v \ - megacells/add32_inst.v \ - megacells/addsub16.bsf \ - megacells/addsub16.cmp \ - megacells/addsub16.inc \ - megacells/addsub16.v \ - megacells/addsub16_bb.v \ - megacells/addsub16_inst.v \ - megacells/bustri.bsf \ - megacells/bustri.cmp \ - megacells/bustri.inc \ - megacells/bustri.v \ - megacells/bustri_bb.v \ - megacells/bustri_inst.v \ - megacells/clk_doubler.v \ - megacells/clk_doubler_bb.v \ - megacells/dspclkpll.v \ - megacells/dspclkpll_bb.v \ - megacells/fifo_1kx16.bsf \ - megacells/fifo_1kx16.cmp \ - megacells/fifo_1kx16.inc \ - megacells/fifo_1kx16.v \ - megacells/fifo_1kx16_bb.v \ - megacells/fifo_1kx16_inst.v \ - megacells/fifo_2k.v \ - megacells/fifo_2k_bb.v \ - megacells/fifo_4k.v \ - megacells/fifo_4k_18.v \ - megacells/fifo_4k_bb.v \ - megacells/fifo_4kx16_dc.bsf \ - megacells/fifo_4kx16_dc.cmp \ - megacells/fifo_4kx16_dc.inc \ - megacells/fifo_4kx16_dc.v \ - megacells/fifo_4kx16_dc_bb.v \ - megacells/fifo_4kx16_dc_inst.v \ - megacells/mylpm_addsub.bsf \ - megacells/mylpm_addsub.cmp \ - megacells/mylpm_addsub.inc \ - megacells/mylpm_addsub.v \ - megacells/mylpm_addsub_bb.v \ - megacells/mylpm_addsub_inst.v \ - megacells/pll.v \ - megacells/pll_bb.v \ - megacells/pll_inst.v \ - megacells/sub32.bsf \ - megacells/sub32.cmp \ - megacells/sub32.inc \ - megacells/sub32.v \ - megacells/sub32_bb.v \ - megacells/sub32_inst.v \ - models/bustri.v \ - models/fifo.v \ - models/fifo_1c_1k.v \ - models/fifo_1c_2k.v \ - models/fifo_1c_4k.v \ - models/fifo_1k.v \ - models/fifo_2k.v \ - models/fifo_4k.v \ - models/fifo_4k_18.v \ - models/pll.v \ - models/ssram.v \ - sdr_lib/adc_interface.v \ - sdr_lib/atr_delay.v \ - sdr_lib/bidir_reg.v \ - sdr_lib/cic_dec_shifter.v \ - sdr_lib/cic_decim.v \ - sdr_lib/cic_int_shifter.v \ - sdr_lib/cic_interp.v \ - sdr_lib/clk_divider.v \ - sdr_lib/cordic.v \ - sdr_lib/cordic_stage.v \ - sdr_lib/ddc.v \ - sdr_lib/dpram.v \ - sdr_lib/duc.v \ - sdr_lib/ext_fifo.v \ - sdr_lib/gen_cordic_consts.py \ - sdr_lib/gen_sync.v \ - sdr_lib/hb/acc.v \ - sdr_lib/hb/coeff_rom.v \ - sdr_lib/hb/halfband_decim.v \ - sdr_lib/hb/halfband_interp.v \ - sdr_lib/hb/hbd_tb/test_hbd.v \ - sdr_lib/hb/mac.v \ - sdr_lib/hb/mult.v \ - sdr_lib/hb/ram16_2port.v \ - sdr_lib/hb/ram16_2sum.v \ - sdr_lib/hb/ram32_2sum.v \ - sdr_lib/io_pins.v \ - sdr_lib/master_control.v \ - sdr_lib/master_control_multi.v \ - sdr_lib/phase_acc.v \ - sdr_lib/ram.v \ - sdr_lib/ram16.v \ - sdr_lib/ram32.v \ - sdr_lib/ram64.v \ - sdr_lib/rssi.v \ - sdr_lib/rx_buffer.v \ - sdr_lib/rx_chain.v \ - sdr_lib/rx_chain_dual.v \ - sdr_lib/rx_dcoffset.v \ - sdr_lib/serial_io.v \ - sdr_lib/setting_reg.v \ - sdr_lib/setting_reg_masked.v \ - sdr_lib/sign_extend.v \ - sdr_lib/strobe_gen.v \ - sdr_lib/tx_buffer.v \ - sdr_lib/tx_chain.v \ - sdr_lib/tx_chain_hb.v \ - tb/cbus_tb.v \ - tb/cordic_tb.v \ - tb/decim_tb.v \ - tb/fullchip_tb.v \ - tb/interp_tb.v \ - tb/justinterp_tb.v \ - tb/usrp_tasks.v \ - toplevel/include/common_config_1rxhb_1tx.vh \ - toplevel/include/common_config_2rx_0tx.vh \ - toplevel/include/common_config_2rxhb_0tx.vh \ - toplevel/include/common_config_2rxhb_2tx.vh \ - toplevel/include/common_config_4rx_0tx.vh \ - toplevel/include/common_config_bottom.vh \ - toplevel/mrfm/biquad_2stage.v \ - toplevel/mrfm/biquad_6stage.v \ - toplevel/mrfm/mrfm.csf \ - toplevel/mrfm/mrfm.esf \ - toplevel/mrfm/mrfm.psf \ - toplevel/mrfm/mrfm.py \ - toplevel/mrfm/mrfm.qpf \ - toplevel/mrfm/mrfm.qsf \ - toplevel/mrfm/mrfm.v \ - toplevel/mrfm/mrfm.vh \ - toplevel/mrfm/mrfm_compensator.v \ - toplevel/mrfm/mrfm_fft.py \ - toplevel/mrfm/mrfm_proc.v \ - toplevel/mrfm/shifter.v \ - toplevel/sizetest/sizetest.csf \ - toplevel/sizetest/sizetest.psf \ - toplevel/sizetest/sizetest.v \ - toplevel/usrp_inband_usb/config.vh \ - toplevel/usrp_inband_usb/usrp_inband_usb.csf \ - toplevel/usrp_inband_usb/usrp_inband_usb.esf \ - toplevel/usrp_inband_usb/usrp_inband_usb.psf \ - toplevel/usrp_inband_usb/usrp_inband_usb.qpf \ - toplevel/usrp_inband_usb/usrp_inband_usb.qsf \ - toplevel/usrp_inband_usb/usrp_inband_usb.v \ - toplevel/usrp_multi/config.vh \ - toplevel/usrp_multi/usrp_multi.csf \ - toplevel/usrp_multi/usrp_multi.esf \ - toplevel/usrp_multi/usrp_multi.psf \ - toplevel/usrp_multi/usrp_multi.qpf \ - toplevel/usrp_multi/usrp_multi.qsf \ - toplevel/usrp_multi/usrp_multi.v \ - toplevel/usrp_std/config.vh \ - toplevel/usrp_std/usrp_std.csf \ - toplevel/usrp_std/usrp_std.esf \ - toplevel/usrp_std/usrp_std.psf \ - toplevel/usrp_std/usrp_std.qpf \ - toplevel/usrp_std/usrp_std.qsf \ - toplevel/usrp_std/usrp_std.v diff --git a/TODO b/TODO deleted file mode 100644 index 76287c3d4..000000000 --- a/TODO +++ /dev/null @@ -1,23 +0,0 @@ - - -Area Reduction -============== -Reduce one or both stages of dec/interp to max rate of 8 instead of 16 -Optimize CICs to minimize registers -Reduce width of RX CORDIC -Fix CORDIC wasted logic cells from bad synthesis -Progressively narrow x,y,z on CORDIC -16-bit wide FIFOs, split IQ/channels on other side (?) - -Enhancements -============ -Halfband filter in Spartan 3 -Muxing of inputs -Switch over to newfc -RAM interface? - -Other -===== -Capture/Transmit straight samples (no DUC/DDC) - - diff --git a/gen_makefile_extra.py b/gen_makefile_extra.py deleted file mode 100755 index 9f48802a2..000000000 --- a/gen_makefile_extra.py +++ /dev/null @@ -1,67 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2006 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -""" -Generate Makefile.extra -""" - -import sys -import os.path - -extensions_we_like = ( - '.v', '.vh', - '.csf', '.esf', '.psf', '.qpf', '.qsf', - '.inc', '.cmp', '.bsf', - '.py') - -def visit(keepers, dirname, names): - if 'rbf' in names: - names.remove('rbf') - if 'CVS' in names: - names.remove('CVS') - - if dirname == '.': - dirname = '' - if dirname.startswith('./'): - dirname = dirname[2:] - - for n in names: - base, ext = os.path.splitext(n) - if ext in extensions_we_like: - keepers.append(os.path.join(dirname, n)) - -def generate(f): - keepers = [] - os.path.walk('.', visit, keepers) - keepers.sort() - write_keepers(keepers, f) - -def write_keepers(files, outf): - m = reduce(max, map(len, files), 0) - e = 'EXTRA_DIST =' - outf.write('%s%s \\\n' % (e, (m-len(e)+8) * ' ')) - for f in files[:-1]: - outf.write('\t%s%s \\\n' % (f, (m-len(f)) * ' ')) - outf.write('\t%s\n' % (files[-1],)) - -if __name__ == '__main__': - generate(open('Makefile.extra','w')) diff --git a/inband_lib/chan_fifo_reader.v b/inband_lib/chan_fifo_reader.v deleted file mode 100755 index 69da9ec5a..000000000 --- a/inband_lib/chan_fifo_reader.v +++ /dev/null @@ -1,219 +0,0 @@ -module chan_fifo_reader - (reset, tx_clock, tx_strobe, timestamp_clock, samples_format, - fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i, - underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ; - - input wire reset ; - input wire tx_clock ; - input wire tx_strobe ; //signal to output tx_i and tx_q - input wire [31:0] timestamp_clock ; //current time - input wire [3:0] samples_format ;// not useful at this point - input wire [31:0] fifodata ; //the data input - input wire pkt_waiting ; //signal the next packet is ready - output reg rdreq ; //actually an ack to the current fifodata - output reg skip ; //finish reading current packet - output reg [15:0] tx_q ; //top 16 bit output of fifodata - output reg [15:0] tx_i ; //bottom 16 bit output of fifodata - output reg underrun ; - output reg tx_empty ; //cause 0 to be the output - input wire [31:0] rssi; - input wire [31:0] threshhold; - input wire [31:0] rssi_wait; - - output wire [14:0] debug; - assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock}; - - //Samples format - // 16 bits interleaved complex samples - `define QI16 4'b0 - - // States - parameter IDLE = 3'd0; - parameter HEADER = 3'd1; - parameter TIMESTAMP = 3'd2; - parameter WAIT = 3'd3; - parameter WAITSTROBE = 3'd4; - parameter SEND = 3'd5; - - // Header format - `define PAYLOAD 8:2 - `define ENDOFBURST 27 - `define STARTOFBURST 28 - `define RSSI_FLAG 26 - - - /* State registers */ - reg [2:0] reader_state; - /* Local registers */ - reg [6:0] payload_len; - reg [6:0] read_len; - reg [31:0] timestamp; - reg burst; - reg trash; - reg rssi_flag; - reg [31:0] time_wait; - - always @(posedge tx_clock) - begin - if (reset) - begin - reader_state <= IDLE; - rdreq <= 0; - skip <= 0; - underrun <= 0; - burst <= 0; - tx_empty <= 1; - tx_q <= 0; - tx_i <= 0; - trash <= 0; - rssi_flag <= 0; - time_wait <= 0; - end - else - begin - case (reader_state) - IDLE: - begin - /* - * reset all the variables and wait for a tx_strobe - * it is assumed that the ram connected to this fifo_reader - * is a short hand fifo meaning that the header to the next packet - * is already available to this fifo_reader when pkt_waiting is on - */ - skip <=0; - time_wait <= 0; - if (pkt_waiting == 1) - begin - reader_state <= HEADER; - rdreq <= 1; - underrun <= 0; - end - if (burst == 1 && pkt_waiting == 0) - underrun <= 1; - if (tx_strobe == 1) - tx_empty <= 1 ; - end - - /* Process header */ - HEADER: - begin - if (tx_strobe == 1) - tx_empty <= 1 ; - - rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST]; - //Check Start/End burst flag - if (fifodata[`STARTOFBURST] == 1 - && fifodata[`ENDOFBURST] == 1) - burst <= 0; - else if (fifodata[`STARTOFBURST] == 1) - burst <= 1; - else if (fifodata[`ENDOFBURST] == 1) - burst <= 0; - - if (trash == 1 && fifodata[`STARTOFBURST] == 0) - begin - skip <= 1; - reader_state <= IDLE; - rdreq <= 0; - end - else - begin - payload_len <= fifodata[`PAYLOAD] ; - read_len <= 0; - rdreq <= 1; - reader_state <= TIMESTAMP; - end - end - - TIMESTAMP: - begin - timestamp <= fifodata; - reader_state <= WAIT; - if (tx_strobe == 1) - tx_empty <= 1 ; - rdreq <= 0; - end - - // Decide if we wait, send or discard samples - WAIT: - begin - if (tx_strobe == 1) - tx_empty <= 1 ; - - time_wait <= time_wait + 32'd1; - // Outdated - if ((timestamp < timestamp_clock) || - (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag)) - begin - trash <= 1; - reader_state <= IDLE; - skip <= 1; - end - // Let's send it - else if (timestamp == timestamp_clock - || timestamp == 32'hFFFFFFFF) - begin - if (rssi <= threshhold || rssi_flag == 0) - begin - trash <= 0; - reader_state <= WAITSTROBE; - end - else - reader_state <= WAIT; - end - else - reader_state <= WAIT; - end - - // Wait for the transmit chain to be ready - WAITSTROBE: - begin - // If end of payload... - if (read_len == payload_len) - begin - reader_state <= IDLE; - skip <= 1; - if (tx_strobe == 1) - tx_empty <= 1 ; - end - else if (tx_strobe == 1) - begin - reader_state <= SEND; - rdreq <= 1; - end - end - - // Send the samples to the tx_chain - SEND: - begin - reader_state <= WAITSTROBE; - read_len <= read_len + 7'd1; - tx_empty <= 0; - rdreq <= 0; - - case(samples_format) - `QI16: - begin - tx_i <= fifodata[15:0]; - tx_q <= fifodata[31:16]; - end - - // Assume 16 bits complex samples by default - default: - begin - tx_i <= fifodata[15:0]; - tx_q <= fifodata[31:16]; - end - endcase - end - - default: - begin - //error handling - reader_state <= IDLE; - end - endcase - end - end - -endmodule diff --git a/inband_lib/channel_demux.v b/inband_lib/channel_demux.v deleted file mode 100644 index cca5cdb65..000000000 --- a/inband_lib/channel_demux.v +++ /dev/null @@ -1,78 +0,0 @@ -module channel_demux - #(parameter NUM_CHAN = 2) ( //usb Side - input [31:0]usbdata_final, - input WR_final, - // TX Side - input reset, - input txclk, - output reg [NUM_CHAN:0] WR_channel, - output reg [31:0] ram_data, - output reg [NUM_CHAN:0] WR_done_channel ); - /* Parse header and forward to ram */ - - reg [2:0]reader_state; - reg [4:0]channel ; - reg [6:0]read_length ; - - // States - parameter IDLE = 3'd0; - parameter HEADER = 3'd1; - parameter WAIT = 3'd2; - parameter FORWARD = 3'd3; - - `define CHANNEL 20:16 - `define PKT_SIZE 127 - wire [4:0] true_channel; - assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ? - NUM_CHAN : (usbdata_final[`CHANNEL]); - - always @(posedge txclk) - begin - if (reset) - begin - reader_state <= IDLE; - WR_channel <= 0; - WR_done_channel <= 0; - end - else - case (reader_state) - IDLE: begin - if (WR_final) - reader_state <= HEADER; - end - - // Store channel and forware header - HEADER: begin - channel <= true_channel; - WR_channel[true_channel] <= 1; - ram_data <= usbdata_final; - read_length <= 7'd0 ; - - reader_state <= WAIT; - end - - WAIT: begin - WR_channel[channel] <= 0; - - if (read_length == `PKT_SIZE) - reader_state <= IDLE; - else if (WR_final) - reader_state <= FORWARD; - end - - FORWARD: begin - WR_channel[channel] <= 1; - ram_data <= usbdata_final; - read_length <= read_length + 7'd1; - - reader_state <= WAIT; - end - - default: - begin - //error handling - reader_state <= IDLE; - end - endcase - end -endmodule diff --git a/inband_lib/channel_ram.v b/inband_lib/channel_ram.v deleted file mode 100755 index 9621246c5..000000000 --- a/inband_lib/channel_ram.v +++ /dev/null @@ -1,107 +0,0 @@ -module channel_ram - ( // System - input txclk, input reset, - // USB side - input [31:0] datain, input WR, input WR_done, output have_space, - // Reader side - output [31:0] dataout, input RD, input RD_done, output packet_waiting); - - reg [6:0] wr_addr, rd_addr; - reg [1:0] which_ram_wr, which_ram_rd; - reg [2:0] nb_packets; - - reg [31:0] ram0 [0:127]; - reg [31:0] ram1 [0:127]; - reg [31:0] ram2 [0:127]; - reg [31:0] ram3 [0:127]; - - reg [31:0] dataout0; - reg [31:0] dataout1; - reg [31:0] dataout2; - reg [31:0] dataout3; - - wire wr_done_int; - wire rd_done_int; - wire [6:0] rd_addr_final; - wire [1:0] which_ram_rd_final; - - // USB side - always @(posedge txclk) - if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain; - - always @(posedge txclk) - if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain; - - always @(posedge txclk) - if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain; - - always @(posedge txclk) - if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain; - - assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done); - - always @(posedge txclk) - if(reset) - wr_addr <= 0; - else if (WR_done) - wr_addr <= 0; - else if (WR) - wr_addr <= wr_addr + 7'd1; - - always @(posedge txclk) - if(reset) - which_ram_wr <= 0; - else if (wr_done_int) - which_ram_wr <= which_ram_wr + 2'd1; - - assign have_space = (nb_packets < 3'd3); - - // Reader side - // short hand fifo - // rd_addr_final is what rd_addr is going to be next clock cycle - // which_ram_rd_final is what which_ram_rd is going to be next clock cycle - always @(posedge txclk) dataout0 <= ram0[rd_addr_final]; - always @(posedge txclk) dataout1 <= ram1[rd_addr_final]; - always @(posedge txclk) dataout2 <= ram2[rd_addr_final]; - always @(posedge txclk) dataout3 <= ram3[rd_addr_final]; - - assign dataout = (which_ram_rd_final[1]) ? - (which_ram_rd_final[0] ? dataout3 : dataout2) : - (which_ram_rd_final[0] ? dataout1 : dataout0); - - //RD_done is the only way to signal the end of one packet - assign rd_done_int = RD_done; - - always @(posedge txclk) - if (reset) - rd_addr <= 0; - else if (RD_done) - rd_addr <= 0; - else if (RD) - rd_addr <= rd_addr + 7'd1; - - assign rd_addr_final = (reset|RD_done) ? (6'd0) : - ((RD)?(rd_addr+7'd1):rd_addr); - - always @(posedge txclk) - if (reset) - which_ram_rd <= 0; - else if (rd_done_int) - which_ram_rd <= which_ram_rd + 2'd1; - - assign which_ram_rd_final = (reset) ? (2'd0): - ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd); - - //packet_waiting is set to zero if rd_done_int is high - //because there is no guarantee that nb_packets will be pos. - - assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)); - always @(posedge txclk) - if (reset) - nb_packets <= 0; - else if (wr_done_int & ~rd_done_int) - nb_packets <= nb_packets + 3'd1; - else if (rd_done_int & ~wr_done_int) - nb_packets <= nb_packets - 3'd1; - -endmodule diff --git a/inband_lib/cmd_reader.v b/inband_lib/cmd_reader.v deleted file mode 100755 index b69ea02b7..000000000 --- a/inband_lib/cmd_reader.v +++ /dev/null @@ -1,305 +0,0 @@ -module cmd_reader - (//System - input reset, input txclk, input [31:0] timestamp_clock, - //FX2 Side - output reg skip, output reg rdreq, - input [31:0] fifodata, input pkt_waiting, - //Rx side - input rx_WR_enabled, output reg [15:0] rx_databus, - output reg rx_WR, output reg rx_WR_done, - //register io - input wire [31:0] reg_data_out, output reg [31:0] reg_data_in, - output reg [6:0] reg_addr, output reg [1:0] reg_io_enable, - output wire [14:0] debug, output reg stop, output reg [15:0] stop_time); - - // States - parameter IDLE = 4'd0; - parameter HEADER = 4'd1; - parameter TIMESTAMP = 4'd2; - parameter WAIT = 4'd3; - parameter TEST = 4'd4; - parameter SEND = 4'd5; - parameter PING = 4'd6; - parameter WRITE_REG = 4'd7; - parameter WRITE_REG_MASKED = 4'd8; - parameter READ_REG = 4'd9; - parameter DELAY = 4'd14; - - `define OP_PING_FIXED 8'd0 - `define OP_PING_FIXED_REPLY 8'd1 - `define OP_WRITE_REG 8'd2 - `define OP_WRITE_REG_MASKED 8'd3 - `define OP_READ_REG 8'd4 - `define OP_READ_REG_REPLY 8'd5 - `define OP_DELAY 8'd12 - - reg [6:0] payload; - reg [6:0] payload_read; - reg [3:0] state; - reg [15:0] high; - reg [15:0] low; - reg pending; - reg [31:0] value0; - reg [31:0] value1; - reg [31:0] value2; - reg [1:0] lines_in; - reg [1:0] lines_out; - reg [1:0] lines_out_total; - - `define JITTER 5 - `define OP_CODE 31:24 - `define PAYLOAD 8:2 - - wire [7:0] ops; - assign ops = value0[`OP_CODE]; - assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]}; - - always @(posedge txclk) - if (reset) - begin - pending <= 0; - state <= IDLE; - skip <= 0; - rdreq <= 0; - rx_WR <= 0; - reg_io_enable <= 0; - reg_data_in <= 0; - reg_addr <= 0; - stop <= 0; - end - else case (state) - IDLE : - begin - payload_read <= 0; - skip <= 0; - lines_in <= 0; - if(pkt_waiting) - begin - state <= HEADER; - rdreq <= 1; - end - end - - HEADER : - begin - payload <= fifodata[`PAYLOAD]; - state <= TIMESTAMP; - end - - TIMESTAMP : - begin - value0 <= fifodata; - state <= WAIT; - rdreq <= 0; - end - - WAIT : - begin - // Let's send it - if ((value0 <= timestamp_clock + `JITTER - && value0 > timestamp_clock) - || value0 == 32'hFFFFFFFF) - state <= TEST; - // Wait a little bit more - else if (value0 > timestamp_clock + `JITTER) - state <= WAIT; - // Outdated - else if (value0 < timestamp_clock) - begin - state <= IDLE; - skip <= 1; - end - end - - TEST : - begin - reg_io_enable <= 0; - rx_WR <= 0; - rx_WR_done <= 1; - stop <= 0; - if (payload_read == payload) - begin - skip <= 1; - state <= IDLE; - rdreq <= 0; - end - else - begin - value0 <= fifodata; - lines_in <= 2'd1; - rdreq <= 1; - payload_read <= payload_read + 7'd1; - lines_out <= 0; - case (fifodata[`OP_CODE]) - `OP_PING_FIXED: - begin - state <= PING; - end - `OP_WRITE_REG: - begin - state <= WRITE_REG; - pending <= 1; - end - `OP_WRITE_REG_MASKED: - begin - state <= WRITE_REG_MASKED; - pending <= 1; - end - `OP_READ_REG: - begin - state <= READ_REG; - end - `OP_DELAY: - begin - state <= DELAY; - end - default: - begin - //error, skip this packet - skip <= 1; - state <= IDLE; - end - endcase - end - end - - SEND: - begin - rdreq <= 0; - rx_WR_done <= 0; - if (pending) - begin - rx_WR <= 1; - rx_databus <= high; - pending <= 0; - if (lines_out == lines_out_total) - state <= TEST; - else case (ops) - `OP_READ_REG: - begin - state <= READ_REG; - end - default: - begin - state <= TEST; - end - endcase - end - else - begin - if (rx_WR_enabled) - begin - rx_WR <= 1; - rx_databus <= low; - pending <= 1; - lines_out <= lines_out + 2'd1; - end - else - rx_WR <= 0; - end - end - - PING: - begin - rx_WR <= 0; - rdreq <= 0; - rx_WR_done <= 0; - lines_out_total <= 2'd1; - pending <= 0; - state <= SEND; - high <= {`OP_PING_FIXED_REPLY, 8'd2}; - low <= value0[15:0]; - end - - READ_REG: - begin - rx_WR <= 0; - rx_WR_done <= 0; - rdreq <= 0; - lines_out_total <= 2'd2; - pending <= 0; - state <= SEND; - if (lines_out == 0) - begin - high <= {`OP_READ_REG_REPLY, 8'd6}; - low <= value0[15:0]; - reg_io_enable <= 2'd3; - reg_addr <= value0[6:0]; - end - else - begin - high <= reg_data_out[31:16]; - low <= reg_data_out[15:0]; - end - end - - WRITE_REG: - begin - rx_WR <= 0; - if (pending) - pending <= 0; - else - begin - if (lines_in == 2'd1) - begin - payload_read <= payload_read + 7'd1; - lines_in <= lines_in + 2'd1; - value1 <= fifodata; - rdreq <= 0; - end - else - begin - reg_io_enable <= 2'd2; - reg_data_in <= value1; - reg_addr <= value0[6:0]; - state <= TEST; - end - end - end - - WRITE_REG_MASKED: - begin - rx_WR <= 0; - if (pending) - pending <= 0; - else - begin - if (lines_in == 2'd1) - begin - rdreq <= 1; - payload_read <= payload_read + 7'd1; - lines_in <= lines_in + 2'd1; - value1 <= fifodata; - end - else if (lines_in == 2'd2) - begin - rdreq <= 0; - payload_read <= payload_read + 7'd1; - lines_in <= lines_in + 2'd1; - value2 <= fifodata; - end - else - begin - reg_io_enable <= 2'd2; - reg_data_in <= (value1 & value2); - reg_addr <= value0[6:0]; - state <= TEST; - end - end - end - - DELAY : - begin - rdreq <= 0; - stop <= 1; - stop_time <= value0[15:0]; - state <= TEST; - end - - default : - begin - //error state handling - state <= IDLE; - end - endcase -endmodule diff --git a/inband_lib/packet_builder.v b/inband_lib/packet_builder.v deleted file mode 100755 index 2c9122394..000000000 --- a/inband_lib/packet_builder.v +++ /dev/null @@ -1,152 +0,0 @@ -module packet_builder #(parameter NUM_CHAN = 2)( - // System - input rxclk, - input reset, - input [31:0] timestamp_clock, - input [3:0] channels, - // ADC side - input [15:0]chan_fifodata, - input [NUM_CHAN:0]chan_empty, - input [9:0]chan_usedw, - output reg [3:0]rd_select, - output reg chan_rdreq, - // FX2 side - output reg WR, - output reg [15:0]fifodata, - input have_space, - input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2, - input wire [31:0]rssi_3, output wire [7:0] debugbus, - input [NUM_CHAN:0] underrun); - - - // States - `define IDLE 3'd0 - `define HEADER1 3'd1 - `define HEADER2 3'd2 - `define TIMESTAMP 3'd3 - `define FORWARD 3'd4 - - `define MAXPAYLOAD 504 - - `define PAYLOAD_LEN 8:0 - `define TAG 12:9 - `define MBZ 15:13 - - `define CHAN 4:0 - `define RSSI 10:5 - `define BURST 12:11 - `define DROPPED 13 - `define UNDERRUN 14 - `define OVERRUN 15 - - reg [NUM_CHAN:0] overrun; - reg [2:0] state; - reg [8:0] read_length; - reg [8:0] payload_len; - reg timestamp_complete; - reg [3:0] check_next; - - wire [31:0] true_rssi; - wire [4:0] true_channel; - wire ready_to_send; - - assign debugbus = {chan_empty[0], rd_select[0], have_space, - (chan_usedw >= 10'd504), (chan_usedw ==0), - ready_to_send, state[1:0]}; - - assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) : - ((rd_select[0]) ? rssi_1:rssi_0); - assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); - assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) || - ((rd_select == NUM_CHAN)&&(chan_usedw > 0)); - - always @(posedge rxclk) - begin - if (reset) - begin - overrun <= 0; - WR <= 0; - rd_select <= 0; - chan_rdreq <= 0; - timestamp_complete <= 0; - check_next <= 0; - state <= `IDLE; - end - else case (state) - `IDLE: begin - chan_rdreq <= #1 0; - //check if the channel is full - if(~chan_empty[check_next]) - begin - if (have_space) - begin - //transmit if the usb buffer have space - //check if we should send - if (ready_to_send) - state <= #1 `HEADER1; - - overrun[check_next] <= 0; - end - else - begin - state <= #1 `IDLE; - overrun[check_next] <= 1; - end - rd_select <= #1 check_next; - end - check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1); - end - - `HEADER1: begin - fifodata[`PAYLOAD_LEN] <= #1 9'd504; - payload_len <= #1 9'd504; - fifodata[`TAG] <= #1 0; - fifodata[`MBZ] <= #1 0; - WR <= #1 1; - - state <= #1 `HEADER2; - read_length <= #1 0; - end - - `HEADER2: begin - fifodata[`CHAN] <= #1 true_channel; - fifodata[`RSSI] <= #1 true_rssi[5:0]; - fifodata[`BURST] <= #1 0; - fifodata[`DROPPED] <= #1 0; - fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel]; - fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel]; - state <= #1 `TIMESTAMP; - end - - `TIMESTAMP: begin - fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]); - timestamp_complete <= #1 ~timestamp_complete; - - if (~timestamp_complete) - chan_rdreq <= #1 1; - - state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP); - end - - `FORWARD: begin - read_length <= #1 read_length + 9'd2; - fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata); - - if (read_length >= `MAXPAYLOAD) - begin - WR <= #1 0; - state <= #1 `IDLE; - chan_rdreq <= #1 0; - end - else if (read_length == payload_len - 4) - chan_rdreq <= #1 0; - end - - default: begin - //handling error state - state <= `IDLE; - end - endcase - end -endmodule - diff --git a/inband_lib/register_io.v b/inband_lib/register_io.v deleted file mode 100755 index 2b0cd1732..000000000 --- a/inband_lib/register_io.v +++ /dev/null @@ -1,82 +0,0 @@ -module register_io - (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr, - rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3, - debug_en, misc, txmux); - - input clk; - input reset; - input wire [1:0] enable; - input wire [6:0] addr; - input wire [31:0] datain; - output reg [31:0] dataout; - output wire [15:0] debugbus; - output reg [6:0] addr_wr; - output reg [31:0] data_wr; - output wire strobe_wr; - input wire [31:0] rssi_0; - input wire [31:0] rssi_1; - input wire [31:0] rssi_2; - input wire [31:0] rssi_3; - output wire [31:0] threshhold; - output wire [31:0] rssi_wait; - input wire [15:0] reg_0; - input wire [15:0] reg_1; - input wire [15:0] reg_2; - input wire [15:0] reg_3; - input wire [3:0] debug_en; - input wire [7:0] misc; - input wire [31:0] txmux; - - reg strobe; - wire [31:0] out[2:1]; - assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]}; - assign threshhold = out[1]; - assign rssi_wait = out[2]; - assign strobe_wr = strobe; - - always @(*) - if (reset | ~enable[1]) - begin - strobe <= 0; - dataout <= 0; - end - else - begin - if (enable[0]) - begin - //read - if (addr <= 7'd52 && addr > 7'd50) - dataout <= out[addr-7'd50]; - else - dataout <= 32'hFFFFFFFF; - strobe <= 0; - end - else - begin - //write - dataout <= dataout; - strobe <= 1; - data_wr <= datain; - addr_wr <= addr; - end - end - -//register declarations - /*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset), - .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/ - setting_reg #(51) setting_reg1(.clock(clk),.reset(reset), - .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1])); - setting_reg #(52) setting_reg2(.clock(clk),.reset(reset), - .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2])); - /*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset), - .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3])); - setting_reg #(54) setting_reg4(.clock(clk),.reset(reset), - .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4])); - setting_reg #(55) setting_reg5(.clock(clk),.reset(reset), - .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5])); - setting_reg #(56) setting_reg6(.clock(clk),.reset(reset), - .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6])); - setting_reg #(57) setting_reg7(.clock(clk),.reset(reset), - .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/ - -endmodule diff --git a/inband_lib/rx_buffer_inband.v b/inband_lib/rx_buffer_inband.v deleted file mode 100755 index cbd2d8958..000000000 --- a/inband_lib/rx_buffer_inband.v +++ /dev/null @@ -1,209 +0,0 @@ -//`include "../../firmware/include/fpga_regs_common.v" -//`include "../../firmware/include/fpga_regs_standard.v" -module rx_buffer_inband - ( input usbclk, - input bus_reset, - input reset, // DSP side reset (used here), do not reset registers - input reset_regs, //Only reset registers - output [15:0] usbdata, - input RD, - output wire have_pkt_rdy, - output reg rx_overrun, - input wire [3:0] channels, - input wire [15:0] ch_0, - input wire [15:0] ch_1, - input wire [15:0] ch_2, - input wire [15:0] ch_3, - input wire [15:0] ch_4, - input wire [15:0] ch_5, - input wire [15:0] ch_6, - input wire [15:0] ch_7, - input rxclk, - input rxstrobe, - input clear_status, - input [6:0] serial_addr, - input [31:0] serial_data, - input serial_strobe, - output wire [15:0] debugbus, - - //Connection with tx_inband - input rx_WR, - input [15:0] rx_databus, - input rx_WR_done, - output reg rx_WR_enabled, - //signal strength - input wire [31:0] rssi_0, input wire [31:0] rssi_1, - input wire [31:0] rssi_2, input wire [31:0] rssi_3, - input wire [1:0] tx_underrun - ); - - parameter NUM_CHAN = 1; - genvar i ; - - // FX2 Bug Fix - reg [8:0] read_count; - always @(negedge usbclk) - if(bus_reset) - read_count <= #1 9'd0; - else if(RD & ~read_count[8]) - read_count <= #1 read_count + 9'd1; - else - read_count <= #1 RD ? read_count : 9'b0; - - // Time counter - reg [31:0] timestamp_clock; - always @(posedge rxclk) - if (reset) - timestamp_clock <= 0; - else - timestamp_clock <= timestamp_clock + 1; - - // USB side fifo - wire [11:0] rdusedw; - wire [11:0] wrusedw; - wire [15:0] fifodata; - wire [15:0] fifodata_il[0:NUM_CHAN]; - wire WR; - wire have_space; - reg sel; - reg wr; - - always@(posedge rxclk) - begin - if(reset) - begin - sel<=1; - wr<=0; - end - else if(rxstrobe) - begin - sel<=0; - wr<=1; - end - else if(wr&~sel) - sel<=1; - else if(wr&sel) - wr<=0; - else - wr<=0; - end - - assign fifodata_il[0] = (sel)?ch_1:ch_0; - assign fifodata_il[1] = (sel)?ch_3:ch_2; - - fifo_4kx16_dc rx_usb_fifo ( - .aclr ( reset ), - .data ( fifodata ), - .rdclk ( ~usbclk ), - .rdreq ( RD & ~read_count[8] ), - .wrclk ( rxclk ), - .wrreq ( WR ), - .q ( usbdata ), - .rdempty ( ), - .rdusedw ( rdusedw ), - .wrfull ( ), - .wrusedw ( wrusedw ) ); - - assign have_pkt_rdy = (rdusedw >= 12'd256); - assign have_space = (wrusedw < 12'd760); - - // Rx side fifos - // These are of size [NUM_CHAN:0] because the extra channel is used for the - // RX command channel. If there were no command channel, they would be - // NUM_CHAN-1. - wire chan_rdreq; - wire [15:0] chan_fifodata; - wire [9:0] chan_usedw; - wire [NUM_CHAN:0] chan_empty; - wire [3:0] rd_select; - wire [NUM_CHAN:0] rx_full; - - packet_builder #(NUM_CHAN) rx_pkt_builer ( - .rxclk ( rxclk ), - .reset ( reset ), - .timestamp_clock ( timestamp_clock ), - .channels ( NUM_CHAN ), - .chan_rdreq ( chan_rdreq ), - .chan_fifodata ( chan_fifodata ), - .chan_empty ( chan_empty ), - .rd_select ( rd_select ), - .chan_usedw ( chan_usedw ), - .WR ( WR ), - .fifodata ( fifodata ), - .have_space ( have_space ), - .rssi_0(rssi_0), .rssi_1(rssi_1), - .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug), - .underrun(tx_underrun)); - - // Detect overrun - always @(posedge rxclk) - if(reset) - rx_overrun <= 1'b0; - else if(rx_full[0]) - rx_overrun <= 1'b1; - else if(clear_status) - rx_overrun <= 1'b0; - - - // FIXME: what is the purpose of these two lines? - wire [15:0]ch[NUM_CHAN:0]; - assign ch[0] = ch_0; - - wire cmd_empty; - - always @(posedge rxclk) - if(reset) - rx_WR_enabled <= 1; - else if(cmd_empty) - rx_WR_enabled <= 1; - else if(rx_WR_done) - rx_WR_enabled <= 0; - - - // Of Size 0:NUM_CHAN due to extra command channel. - wire [15:0] dataout [0:NUM_CHAN]; - wire [9:0] usedw [0:NUM_CHAN]; - wire empty[0:NUM_CHAN]; - - generate for (i = 0 ; i < NUM_CHAN; i = i + 1) - begin : generate_channel_fifos - - wire rdreq; - - assign rdreq = (rd_select == i) & chan_rdreq; - - fifo_1kx16 rx_chan_fifo ( - .aclr ( reset ), - .clock ( rxclk ), - .data ( fifodata_il[i] ), - .rdreq ( rdreq ), - .wrreq ( ~rx_full[i] & wr), - .empty (empty[i]), - .full (rx_full[i]), - .q ( dataout[i]), - .usedw ( usedw[i]), - .almost_empty(chan_empty[i]) - ); - end - endgenerate - - wire [7:0] debug; - - fifo_1kx16 rx_cmd_fifo ( - .aclr ( reset ), - .clock ( rxclk ), - .data ( rx_databus ), - .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), - .wrreq ( rx_WR & rx_WR_enabled), - .empty ( cmd_empty), - .full ( rx_full[NUM_CHAN] ), - .q ( dataout[NUM_CHAN]), - .usedw ( usedw[NUM_CHAN] ) - ); - - assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; - assign chan_fifodata = dataout[rd_select]; - assign chan_usedw = usedw[rd_select]; - assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr}; - -endmodule diff --git a/inband_lib/tx_buffer_inband.v b/inband_lib/tx_buffer_inband.v deleted file mode 100755 index 2dd75f42f..000000000 --- a/inband_lib/tx_buffer_inband.v +++ /dev/null @@ -1,143 +0,0 @@ -module tx_buffer_inband - ( //System - input wire usbclk, input wire bus_reset, input wire reset, - input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels, - //output transmit signals - output wire [15:0] tx_i_0, output wire [15:0] tx_q_0, - output wire [15:0] tx_i_1, output wire [15:0] tx_q_1, - output wire [15:0] tx_i_2, output wire [15:0] tx_q_2, - output wire [15:0] tx_i_3, output wire [15:0] tx_q_3, - input wire txclk, input wire txstrobe, input wire WR, - input wire clear_status, output wire tx_empty, output wire [15:0] debugbus, - //command reader io - output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done, - input wire rx_WR_enabled, - //register io - output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr, - input wire [31:0] reg_data_out, - //input characteristic signals - input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, - input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold, - output wire [1:0] tx_underrun, - //system stop - output wire stop, output wire [15:0] stop_time); - - parameter NUM_CHAN = 1 ; - - /* To generate channel readers */ - genvar i ; - - /* These will eventually be external register */ - reg [31:0] timestamp_clock ; - wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ; - wire [31:0] rssi [3:0]; - assign rssi[0] = rssi_0; - assign rssi[1] = rssi_1; - assign rssi[2] = rssi_2; - assign rssi[3] = rssi_3; - - always @(posedge txclk) - if (reset) - timestamp_clock <= 0; - else - timestamp_clock <= timestamp_clock + 1; - - - /* Connections between tx_usb_fifo_reader and - cnannel/command processing blocks */ - wire [31:0] tx_data_bus ; - wire [NUM_CHAN:0] chan_WR ; - wire [NUM_CHAN:0] chan_done ; - - /* Connections between data block and the - FX2/TX chains */ - wire [NUM_CHAN:0] chan_underrun; - wire [NUM_CHAN:0] chan_txempty; - - /* Conections between tx_data_packet_fifo and - its reader + strobe generator */ - wire [31:0] chan_fifodata [NUM_CHAN:0] ; - wire chan_pkt_waiting [NUM_CHAN:0] ; - wire chan_rdreq [NUM_CHAN:0] ; - wire chan_skip [NUM_CHAN:0] ; - wire chan_have_space [NUM_CHAN:0] ; - - wire [14:0] debug [NUM_CHAN:0]; - - /* Outputs to transmit chains */ - wire [15:0] tx_i [NUM_CHAN:0] ; - wire [15:0] tx_q [NUM_CHAN:0] ; - - assign tx_i[NUM_CHAN] = 0; - assign tx_q[NUM_CHAN] = 0; - - assign have_space = chan_have_space[0] & chan_have_space[1]; - assign tx_empty = chan_txempty[0] & chan_txempty[1] ; - - assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; - assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; - assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; - assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ; - - assign tx_q_2 = 16'b0 ; - assign tx_i_2 = 16'b0 ; - assign tx_q_3 = 16'b0 ; - assign tx_i_3 = 16'b0 ; - assign tx_i_3 = 16'b0 ; - - assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done, - chan_pkt_waiting[0], chan_pkt_waiting[1], - chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]}; - - wire [31:0] usbdata_final; - wire WR_final; - - tx_packer tx_usb_packer - (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR), - .usbdata(usbdata), .reset(reset), .txclk(txclk), - .usbdata_final(usbdata_final), .WR_final(WR_final)); - - channel_demux #(NUM_CHAN) channel_demuxer - (.usbdata_final(usbdata_final), .WR_final(WR_final), - .reset(reset), .txclk(txclk), .WR_channel(chan_WR), - .WR_done_channel(chan_done), .ram_data(tx_data_bus)); - - generate for (i = 0 ; i < NUM_CHAN; i = i + 1) - begin : generate_channel_readers - assign tx_underrun[i] = chan_underrun[i]; - - channel_ram tx_data_packet_fifo - (.reset(reset), .txclk(txclk), .datain(tx_data_bus), - .WR(chan_WR[i]), .WR_done(chan_done[i]), - .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]), - .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]), - .RD_done(chan_skip[i])); - - chan_fifo_reader tx_chan_reader - (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe), - .timestamp_clock(timestamp_clock), .samples_format(4'b0), - .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]), - .skip(chan_skip[i]), .rdreq(chan_rdreq[i]), - .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]), - .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]), - .threshhold(threshhold), .rssi_wait(rssi_wait)); - end - endgenerate - - - channel_ram tx_cmd_packet_fifo - (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]), - .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]), - .dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]), - .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN])); - - cmd_reader tx_cmd_reader - (.reset(reset), .txclk(txclk), .timestamp_clock(timestamp_clock), .skip(chan_skip[NUM_CHAN]), - .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]), - .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus), - .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled), - .reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr), - .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time)); - -endmodule // tx_buffer - diff --git a/inband_lib/tx_packer.v b/inband_lib/tx_packer.v deleted file mode 100644 index 2f19b21f3..000000000 --- a/inband_lib/tx_packer.v +++ /dev/null @@ -1,119 +0,0 @@ -module tx_packer - ( //FX2 Side - input bus_reset, - input usbclk, - input WR_fx2, - input [15:0]usbdata, - - // TX Side - input reset, - input txclk, - output reg [31:0] usbdata_final, - output reg WR_final); - - reg [8:0] write_count; - - /* Fix FX2 bug */ - always @(posedge usbclk) - begin - if(bus_reset) // Use bus reset because this is on usbclk - write_count <= #1 0; - else if(WR_fx2 & ~write_count[8]) - write_count <= #1 write_count + 9'd1; - else - write_count <= #1 WR_fx2 ? write_count : 9'b0; - end - - reg WR_fx2_fixed; - reg [15:0]usbdata_fixed; - - always @(posedge usbclk) - begin - WR_fx2_fixed <= WR_fx2 & ~write_count[8]; - usbdata_fixed <= usbdata; - end - - /* Used to convert 16 bits bus_data to the 32 bits wide fifo */ - reg word_complete ; - reg [15:0] usbdata_delayed ; - reg writing ; - wire [31:0] usbdata_packed ; - wire WR_packed ; - - always @(posedge usbclk) - begin - if (bus_reset) - begin - word_complete <= 0 ; - writing <= 0 ; - end - else if (WR_fx2_fixed) - begin - writing <= 1 ; - if (word_complete) - word_complete <= 0 ; - else - begin - usbdata_delayed <= usbdata_fixed ; - word_complete <= 1 ; - end - end - else - writing <= 0 ; - end - - assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ; - assign WR_packed = word_complete & writing ; - - /* Make sure data are sync with usbclk */ - reg [31:0]usbdata_usbclk; - reg WR_usbclk; - - always @(posedge usbclk) - begin - if (WR_packed) - usbdata_usbclk <= usbdata_packed; - WR_usbclk <= WR_packed; - end - - /* Cross clock boundaries */ - reg [31:0] usbdata_tx ; - reg WR_tx; - reg WR_1; - reg WR_2; - - always @(posedge txclk) usbdata_tx <= usbdata_usbclk; - - always @(posedge txclk) - if (reset) - WR_1 <= 0; - else - WR_1 <= WR_usbclk; - - always @(posedge txclk) - if (reset) - WR_2 <= 0; - else - WR_2 <= WR_1; - - always @(posedge txclk) - begin - if (reset) - WR_tx <= 0; - else - WR_tx <= WR_1 & ~WR_2; - end - - always @(posedge txclk) - begin - if (reset) - WR_final <= 0; - else - begin - WR_final <= WR_tx; - if (WR_tx) - usbdata_final <= usbdata_tx; - end - end - -endmodule diff --git a/inband_lib/usb_packet_fifo.v b/inband_lib/usb_packet_fifo.v deleted file mode 100755 index c416e2bdb..000000000 --- a/inband_lib/usb_packet_fifo.v +++ /dev/null @@ -1,112 +0,0 @@ -module usb_packet_fifo - ( input reset, - input clock_in, - input clock_out, - input [15:0]ram_data_in, - input write_enable, - output reg [15:0]ram_data_out, - output reg pkt_waiting, - output reg have_space, - input read_enable, - input skip_packet ) ; - - /* Some parameters for usage later on */ - parameter DATA_WIDTH = 16 ; - parameter NUM_PACKETS = 4 ; - - /* Create the RAM here */ - reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ; - - /* Create the address signals */ - reg [7-2+NUM_PACKETS:0] usb_ram_ain ; - reg [7:0] usb_ram_offset ; - reg [1:0] usb_ram_packet ; - - wire [7-2+NUM_PACKETS:0] usb_ram_aout ; - reg isfull; - - assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ; - - // Check if there is one full packet to process - always @(usb_ram_ain, usb_ram_aout) - begin - if (reset) - pkt_waiting <= 0; - else if (usb_ram_ain == usb_ram_aout) - pkt_waiting <= isfull; - else if (usb_ram_ain > usb_ram_aout) - pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256; - else - pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256; - end - - // Check if there is room - always @(usb_ram_ain, usb_ram_aout) - begin - if (reset) - have_space <= 1; - else if (usb_ram_ain == usb_ram_aout) - have_space <= ~isfull; - else if (usb_ram_ain > usb_ram_aout) - have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1); - else - have_space <= (usb_ram_aout - usb_ram_ain) >= 256; - end - - /* RAM Write Address process */ - always @(posedge clock_in) - begin - if( reset ) - usb_ram_ain <= 0 ; - else - if( write_enable ) - begin - usb_ram_ain <= usb_ram_ain + 1 ; - if (usb_ram_ain + 1 == usb_ram_aout) - isfull <= 1; - end - end - - /* RAM Writing process */ - always @(posedge clock_in) - begin - if( write_enable ) - begin - usb_ram[usb_ram_ain] <= ram_data_in ; - end - end - - /* RAM Read Address process */ - always @(posedge clock_out) - begin - if( reset ) - begin - usb_ram_packet <= 0 ; - usb_ram_offset <= 0 ; - isfull <= 0; - end - else - if( skip_packet ) - begin - usb_ram_packet <= usb_ram_packet + 1 ; - usb_ram_offset <= 0 ; - end - else if(read_enable) - if( usb_ram_offset == 8'b11111111 ) - begin - usb_ram_offset <= 0 ; - usb_ram_packet <= usb_ram_packet + 1 ; - end - else - usb_ram_offset <= usb_ram_offset + 1 ; - if (usb_ram_ain == usb_ram_aout) - isfull <= 0; - end - - /* RAM Reading Process */ - always @(posedge clock_out) - begin - ram_data_out <= usb_ram[usb_ram_aout] ; - end - -endmodule \ No newline at end of file diff --git a/megacells/.gitignore b/megacells/.gitignore deleted file mode 100644 index c2de89b27..000000000 --- a/megacells/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/db diff --git a/megacells/accum32.bsf b/megacells/accum32.bsf deleted file mode 100755 index 494a8200f..000000000 --- a/megacells/accum32.bsf +++ /dev/null @@ -1,86 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2003 Altera Corporation -Any megafunction design, and related netlist (encrypted or decrypted), -support information, device programming or simulation file, and any other -associated documentation or information provided by Altera or a partner -under Altera's Megafunction Partnership Program may be used only -to program PLD devices (but not masked PLD devices) from Altera. Any -other use of such megafunction design, netlist, support information, -device programming or simulation file, or any other related documentation -or information is prohibited for any other purpose, including, but not -limited to modification, reverse engineering, de-compiling, or use with -any other silicon devices, unless such use is explicitly licensed under -a separate agreement with Altera or a megafunction partner. Title to the -intellectual property, including patents, copyrights, trademarks, trade -secrets, or maskworks, embodied in any such megafunction design, netlist, -support information, device programming or simulation file, or any other -related documentation or information provided by Altera or a megafunction -partner, remains with Altera, the megafunction partner, or their respective -licensors. No other licenses, including any licenses needed under any third -party's intellectual property, are provided herein. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 240 120) - (text "accum32" (rect 87 2 166 21)(font "Arial" (font_size 10))) - (text "inst" (rect 8 101 31 116)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) - (text "data[31..0]" (rect 20 24 82 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 16 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clock" (rect 20 40 51 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clken" (rect 20 56 51 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 80 41 96)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 1)) - ) - (port - (pt 240 56) - (output) - (text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) - (text "result[31..0]" (rect 152 40 221 56)(font "Arial" (font_size 8))) - (line (pt 240 56)(pt 224 56)(line_width 3)) - ) - (drawing - (text "acc" (rect 102 48 123 64)(font "Arial" (font_size 8))) - (text "SIGNED" (rect 177 18 214 32)(font "Arial" )) - (line (pt 16 16)(pt 224 16)(line_width 1)) - (line (pt 16 16)(pt 16 104)(line_width 1)) - (line (pt 16 104)(pt 224 104)(line_width 1)) - (line (pt 224 16)(pt 224 104)(line_width 1)) - (line (pt 88 24)(pt 136 48)(line_width 1)) - (line (pt 136 64)(pt 136 48)(line_width 1)) - (line (pt 88 88)(pt 136 64)(line_width 1)) - (line (pt 88 24)(pt 88 88)(line_width 1)) - (line (pt 16 40)(pt 88 40)(line_width 1)) - (line (pt 16 56)(pt 88 56)(line_width 1)) - (line (pt 136 56)(pt 224 56)(line_width 1)) - (line (pt 16 72)(pt 88 72)(line_width 1)) - (line (pt 16 72)(pt 88 72)(line_width 1)) - (line (pt 16 96)(pt 104 96)(line_width 1)) - (line (pt 104 96)(pt 104 80)(line_width 1)) - ) -) diff --git a/megacells/accum32.cmp b/megacells/accum32.cmp deleted file mode 100755 index 55b5fdc22..000000000 --- a/megacells/accum32.cmp +++ /dev/null @@ -1,31 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -component accum32 - PORT - ( - data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - clock : IN STD_LOGIC := '0'; - clken : IN STD_LOGIC := '1'; - aclr : IN STD_LOGIC := '0'; - result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) - ); -end component; diff --git a/megacells/accum32.inc b/megacells/accum32.inc deleted file mode 100755 index 6c6690025..000000000 --- a/megacells/accum32.inc +++ /dev/null @@ -1,32 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -FUNCTION accum32 -( - data[31..0], - clock, - clken, - aclr -) - -RETURNS ( - result[31..0] -); diff --git a/megacells/accum32.v b/megacells/accum32.v deleted file mode 100755 index ce50cbbf1..000000000 --- a/megacells/accum32.v +++ /dev/null @@ -1,765 +0,0 @@ -// megafunction wizard: %ALTACCUMULATE%CBX% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altaccumulate - -// ============================================================ -// File Name: accum32.v -// Megafunction Name(s): -// altaccumulate -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// ************************************************************ - - -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result -//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END - -//synthesis_resources = lut 32 -module accum32_accum_nta - ( - aclr, - clken, - clock, - data, - result) /* synthesis synthesis_clearbox=1 */; - input aclr; - input clken; - input clock; - input [31:0] data; - output [31:0] result; - - wire [0:0] wire_acc_cella_0cout; - wire [0:0] wire_acc_cella_1cout; - wire [0:0] wire_acc_cella_2cout; - wire [0:0] wire_acc_cella_3cout; - wire [0:0] wire_acc_cella_4cout; - wire [0:0] wire_acc_cella_5cout; - wire [0:0] wire_acc_cella_6cout; - wire [0:0] wire_acc_cella_7cout; - wire [0:0] wire_acc_cella_8cout; - wire [0:0] wire_acc_cella_9cout; - wire [0:0] wire_acc_cella_10cout; - wire [0:0] wire_acc_cella_11cout; - wire [0:0] wire_acc_cella_12cout; - wire [0:0] wire_acc_cella_13cout; - wire [0:0] wire_acc_cella_14cout; - wire [0:0] wire_acc_cella_15cout; - wire [0:0] wire_acc_cella_16cout; - wire [0:0] wire_acc_cella_17cout; - wire [0:0] wire_acc_cella_18cout; - wire [0:0] wire_acc_cella_19cout; - wire [0:0] wire_acc_cella_20cout; - wire [0:0] wire_acc_cella_21cout; - wire [0:0] wire_acc_cella_22cout; - wire [0:0] wire_acc_cella_23cout; - wire [0:0] wire_acc_cella_24cout; - wire [0:0] wire_acc_cella_25cout; - wire [0:0] wire_acc_cella_26cout; - wire [0:0] wire_acc_cella_27cout; - wire [0:0] wire_acc_cella_28cout; - wire [0:0] wire_acc_cella_29cout; - wire [0:0] wire_acc_cella_30cout; - wire [31:0] wire_acc_cella_dataa; - wire [31:0] wire_acc_cella_datab; - wire [31:0] wire_acc_cella_datac; - wire [31:0] wire_acc_cella_regout; - wire sload; - - stratix_lcell acc_cella_0 - ( - .aclr(aclr), - .cin(1'b0), - .clk(clock), - .cout(wire_acc_cella_0cout[0:0]), - .dataa(wire_acc_cella_dataa[0:0]), - .datab(wire_acc_cella_datab[0:0]), - .datac(wire_acc_cella_datac[0:0]), - .ena(clken), - .regout(wire_acc_cella_regout[0:0]), - .sload(sload)); - defparam - acc_cella_0.cin_used = "true", - acc_cella_0.lut_mask = "96e8", - acc_cella_0.operation_mode = "arithmetic", - acc_cella_0.sum_lutc_input = "cin", - acc_cella_0.synch_mode = "on", - acc_cella_0.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_1 - ( - .aclr(aclr), - .cin(wire_acc_cella_0cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_1cout[0:0]), - .dataa(wire_acc_cella_dataa[1:1]), - .datab(wire_acc_cella_datab[1:1]), - .datac(wire_acc_cella_datac[1:1]), - .ena(clken), - .regout(wire_acc_cella_regout[1:1]), - .sload(sload)); - defparam - acc_cella_1.cin_used = "true", - acc_cella_1.lut_mask = "96e8", - acc_cella_1.operation_mode = "arithmetic", - acc_cella_1.sum_lutc_input = "cin", - acc_cella_1.synch_mode = "on", - acc_cella_1.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_2 - ( - .aclr(aclr), - .cin(wire_acc_cella_1cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_2cout[0:0]), - .dataa(wire_acc_cella_dataa[2:2]), - .datab(wire_acc_cella_datab[2:2]), - .datac(wire_acc_cella_datac[2:2]), - .ena(clken), - .regout(wire_acc_cella_regout[2:2]), - .sload(sload)); - defparam - acc_cella_2.cin_used = "true", - acc_cella_2.lut_mask = "96e8", - acc_cella_2.operation_mode = "arithmetic", - acc_cella_2.sum_lutc_input = "cin", - acc_cella_2.synch_mode = "on", - acc_cella_2.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_3 - ( - .aclr(aclr), - .cin(wire_acc_cella_2cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_3cout[0:0]), - .dataa(wire_acc_cella_dataa[3:3]), - .datab(wire_acc_cella_datab[3:3]), - .datac(wire_acc_cella_datac[3:3]), - .ena(clken), - .regout(wire_acc_cella_regout[3:3]), - .sload(sload)); - defparam - acc_cella_3.cin_used = "true", - acc_cella_3.lut_mask = "96e8", - acc_cella_3.operation_mode = "arithmetic", - acc_cella_3.sum_lutc_input = "cin", - acc_cella_3.synch_mode = "on", - acc_cella_3.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_4 - ( - .aclr(aclr), - .cin(wire_acc_cella_3cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_4cout[0:0]), - .dataa(wire_acc_cella_dataa[4:4]), - .datab(wire_acc_cella_datab[4:4]), - .datac(wire_acc_cella_datac[4:4]), - .ena(clken), - .regout(wire_acc_cella_regout[4:4]), - .sload(sload)); - defparam - acc_cella_4.cin_used = "true", - acc_cella_4.lut_mask = "96e8", - acc_cella_4.operation_mode = "arithmetic", - acc_cella_4.sum_lutc_input = "cin", - acc_cella_4.synch_mode = "on", - acc_cella_4.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_5 - ( - .aclr(aclr), - .cin(wire_acc_cella_4cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_5cout[0:0]), - .dataa(wire_acc_cella_dataa[5:5]), - .datab(wire_acc_cella_datab[5:5]), - .datac(wire_acc_cella_datac[5:5]), - .ena(clken), - .regout(wire_acc_cella_regout[5:5]), - .sload(sload)); - defparam - acc_cella_5.cin_used = "true", - acc_cella_5.lut_mask = "96e8", - acc_cella_5.operation_mode = "arithmetic", - acc_cella_5.sum_lutc_input = "cin", - acc_cella_5.synch_mode = "on", - acc_cella_5.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_6 - ( - .aclr(aclr), - .cin(wire_acc_cella_5cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_6cout[0:0]), - .dataa(wire_acc_cella_dataa[6:6]), - .datab(wire_acc_cella_datab[6:6]), - .datac(wire_acc_cella_datac[6:6]), - .ena(clken), - .regout(wire_acc_cella_regout[6:6]), - .sload(sload)); - defparam - acc_cella_6.cin_used = "true", - acc_cella_6.lut_mask = "96e8", - acc_cella_6.operation_mode = "arithmetic", - acc_cella_6.sum_lutc_input = "cin", - acc_cella_6.synch_mode = "on", - acc_cella_6.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_7 - ( - .aclr(aclr), - .cin(wire_acc_cella_6cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_7cout[0:0]), - .dataa(wire_acc_cella_dataa[7:7]), - .datab(wire_acc_cella_datab[7:7]), - .datac(wire_acc_cella_datac[7:7]), - .ena(clken), - .regout(wire_acc_cella_regout[7:7]), - .sload(sload)); - defparam - acc_cella_7.cin_used = "true", - acc_cella_7.lut_mask = "96e8", - acc_cella_7.operation_mode = "arithmetic", - acc_cella_7.sum_lutc_input = "cin", - acc_cella_7.synch_mode = "on", - acc_cella_7.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_8 - ( - .aclr(aclr), - .cin(wire_acc_cella_7cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_8cout[0:0]), - .dataa(wire_acc_cella_dataa[8:8]), - .datab(wire_acc_cella_datab[8:8]), - .datac(wire_acc_cella_datac[8:8]), - .ena(clken), - .regout(wire_acc_cella_regout[8:8]), - .sload(sload)); - defparam - acc_cella_8.cin_used = "true", - acc_cella_8.lut_mask = "96e8", - acc_cella_8.operation_mode = "arithmetic", - acc_cella_8.sum_lutc_input = "cin", - acc_cella_8.synch_mode = "on", - acc_cella_8.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_9 - ( - .aclr(aclr), - .cin(wire_acc_cella_8cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_9cout[0:0]), - .dataa(wire_acc_cella_dataa[9:9]), - .datab(wire_acc_cella_datab[9:9]), - .datac(wire_acc_cella_datac[9:9]), - .ena(clken), - .regout(wire_acc_cella_regout[9:9]), - .sload(sload)); - defparam - acc_cella_9.cin_used = "true", - acc_cella_9.lut_mask = "96e8", - acc_cella_9.operation_mode = "arithmetic", - acc_cella_9.sum_lutc_input = "cin", - acc_cella_9.synch_mode = "on", - acc_cella_9.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_10 - ( - .aclr(aclr), - .cin(wire_acc_cella_9cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_10cout[0:0]), - .dataa(wire_acc_cella_dataa[10:10]), - .datab(wire_acc_cella_datab[10:10]), - .datac(wire_acc_cella_datac[10:10]), - .ena(clken), - .regout(wire_acc_cella_regout[10:10]), - .sload(sload)); - defparam - acc_cella_10.cin_used = "true", - acc_cella_10.lut_mask = "96e8", - acc_cella_10.operation_mode = "arithmetic", - acc_cella_10.sum_lutc_input = "cin", - acc_cella_10.synch_mode = "on", - acc_cella_10.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_11 - ( - .aclr(aclr), - .cin(wire_acc_cella_10cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_11cout[0:0]), - .dataa(wire_acc_cella_dataa[11:11]), - .datab(wire_acc_cella_datab[11:11]), - .datac(wire_acc_cella_datac[11:11]), - .ena(clken), - .regout(wire_acc_cella_regout[11:11]), - .sload(sload)); - defparam - acc_cella_11.cin_used = "true", - acc_cella_11.lut_mask = "96e8", - acc_cella_11.operation_mode = "arithmetic", - acc_cella_11.sum_lutc_input = "cin", - acc_cella_11.synch_mode = "on", - acc_cella_11.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_12 - ( - .aclr(aclr), - .cin(wire_acc_cella_11cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_12cout[0:0]), - .dataa(wire_acc_cella_dataa[12:12]), - .datab(wire_acc_cella_datab[12:12]), - .datac(wire_acc_cella_datac[12:12]), - .ena(clken), - .regout(wire_acc_cella_regout[12:12]), - .sload(sload)); - defparam - acc_cella_12.cin_used = "true", - acc_cella_12.lut_mask = "96e8", - acc_cella_12.operation_mode = "arithmetic", - acc_cella_12.sum_lutc_input = "cin", - acc_cella_12.synch_mode = "on", - acc_cella_12.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_13 - ( - .aclr(aclr), - .cin(wire_acc_cella_12cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_13cout[0:0]), - .dataa(wire_acc_cella_dataa[13:13]), - .datab(wire_acc_cella_datab[13:13]), - .datac(wire_acc_cella_datac[13:13]), - .ena(clken), - .regout(wire_acc_cella_regout[13:13]), - .sload(sload)); - defparam - acc_cella_13.cin_used = "true", - acc_cella_13.lut_mask = "96e8", - acc_cella_13.operation_mode = "arithmetic", - acc_cella_13.sum_lutc_input = "cin", - acc_cella_13.synch_mode = "on", - acc_cella_13.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_14 - ( - .aclr(aclr), - .cin(wire_acc_cella_13cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_14cout[0:0]), - .dataa(wire_acc_cella_dataa[14:14]), - .datab(wire_acc_cella_datab[14:14]), - .datac(wire_acc_cella_datac[14:14]), - .ena(clken), - .regout(wire_acc_cella_regout[14:14]), - .sload(sload)); - defparam - acc_cella_14.cin_used = "true", - acc_cella_14.lut_mask = "96e8", - acc_cella_14.operation_mode = "arithmetic", - acc_cella_14.sum_lutc_input = "cin", - acc_cella_14.synch_mode = "on", - acc_cella_14.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_15 - ( - .aclr(aclr), - .cin(wire_acc_cella_14cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_15cout[0:0]), - .dataa(wire_acc_cella_dataa[15:15]), - .datab(wire_acc_cella_datab[15:15]), - .datac(wire_acc_cella_datac[15:15]), - .ena(clken), - .regout(wire_acc_cella_regout[15:15]), - .sload(sload)); - defparam - acc_cella_15.cin_used = "true", - acc_cella_15.lut_mask = "96e8", - acc_cella_15.operation_mode = "arithmetic", - acc_cella_15.sum_lutc_input = "cin", - acc_cella_15.synch_mode = "on", - acc_cella_15.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_16 - ( - .aclr(aclr), - .cin(wire_acc_cella_15cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_16cout[0:0]), - .dataa(wire_acc_cella_dataa[16:16]), - .datab(wire_acc_cella_datab[16:16]), - .datac(wire_acc_cella_datac[16:16]), - .ena(clken), - .regout(wire_acc_cella_regout[16:16]), - .sload(sload)); - defparam - acc_cella_16.cin_used = "true", - acc_cella_16.lut_mask = "96e8", - acc_cella_16.operation_mode = "arithmetic", - acc_cella_16.sum_lutc_input = "cin", - acc_cella_16.synch_mode = "on", - acc_cella_16.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_17 - ( - .aclr(aclr), - .cin(wire_acc_cella_16cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_17cout[0:0]), - .dataa(wire_acc_cella_dataa[17:17]), - .datab(wire_acc_cella_datab[17:17]), - .datac(wire_acc_cella_datac[17:17]), - .ena(clken), - .regout(wire_acc_cella_regout[17:17]), - .sload(sload)); - defparam - acc_cella_17.cin_used = "true", - acc_cella_17.lut_mask = "96e8", - acc_cella_17.operation_mode = "arithmetic", - acc_cella_17.sum_lutc_input = "cin", - acc_cella_17.synch_mode = "on", - acc_cella_17.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_18 - ( - .aclr(aclr), - .cin(wire_acc_cella_17cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_18cout[0:0]), - .dataa(wire_acc_cella_dataa[18:18]), - .datab(wire_acc_cella_datab[18:18]), - .datac(wire_acc_cella_datac[18:18]), - .ena(clken), - .regout(wire_acc_cella_regout[18:18]), - .sload(sload)); - defparam - acc_cella_18.cin_used = "true", - acc_cella_18.lut_mask = "96e8", - acc_cella_18.operation_mode = "arithmetic", - acc_cella_18.sum_lutc_input = "cin", - acc_cella_18.synch_mode = "on", - acc_cella_18.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_19 - ( - .aclr(aclr), - .cin(wire_acc_cella_18cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_19cout[0:0]), - .dataa(wire_acc_cella_dataa[19:19]), - .datab(wire_acc_cella_datab[19:19]), - .datac(wire_acc_cella_datac[19:19]), - .ena(clken), - .regout(wire_acc_cella_regout[19:19]), - .sload(sload)); - defparam - acc_cella_19.cin_used = "true", - acc_cella_19.lut_mask = "96e8", - acc_cella_19.operation_mode = "arithmetic", - acc_cella_19.sum_lutc_input = "cin", - acc_cella_19.synch_mode = "on", - acc_cella_19.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_20 - ( - .aclr(aclr), - .cin(wire_acc_cella_19cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_20cout[0:0]), - .dataa(wire_acc_cella_dataa[20:20]), - .datab(wire_acc_cella_datab[20:20]), - .datac(wire_acc_cella_datac[20:20]), - .ena(clken), - .regout(wire_acc_cella_regout[20:20]), - .sload(sload)); - defparam - acc_cella_20.cin_used = "true", - acc_cella_20.lut_mask = "96e8", - acc_cella_20.operation_mode = "arithmetic", - acc_cella_20.sum_lutc_input = "cin", - acc_cella_20.synch_mode = "on", - acc_cella_20.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_21 - ( - .aclr(aclr), - .cin(wire_acc_cella_20cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_21cout[0:0]), - .dataa(wire_acc_cella_dataa[21:21]), - .datab(wire_acc_cella_datab[21:21]), - .datac(wire_acc_cella_datac[21:21]), - .ena(clken), - .regout(wire_acc_cella_regout[21:21]), - .sload(sload)); - defparam - acc_cella_21.cin_used = "true", - acc_cella_21.lut_mask = "96e8", - acc_cella_21.operation_mode = "arithmetic", - acc_cella_21.sum_lutc_input = "cin", - acc_cella_21.synch_mode = "on", - acc_cella_21.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_22 - ( - .aclr(aclr), - .cin(wire_acc_cella_21cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_22cout[0:0]), - .dataa(wire_acc_cella_dataa[22:22]), - .datab(wire_acc_cella_datab[22:22]), - .datac(wire_acc_cella_datac[22:22]), - .ena(clken), - .regout(wire_acc_cella_regout[22:22]), - .sload(sload)); - defparam - acc_cella_22.cin_used = "true", - acc_cella_22.lut_mask = "96e8", - acc_cella_22.operation_mode = "arithmetic", - acc_cella_22.sum_lutc_input = "cin", - acc_cella_22.synch_mode = "on", - acc_cella_22.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_23 - ( - .aclr(aclr), - .cin(wire_acc_cella_22cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_23cout[0:0]), - .dataa(wire_acc_cella_dataa[23:23]), - .datab(wire_acc_cella_datab[23:23]), - .datac(wire_acc_cella_datac[23:23]), - .ena(clken), - .regout(wire_acc_cella_regout[23:23]), - .sload(sload)); - defparam - acc_cella_23.cin_used = "true", - acc_cella_23.lut_mask = "96e8", - acc_cella_23.operation_mode = "arithmetic", - acc_cella_23.sum_lutc_input = "cin", - acc_cella_23.synch_mode = "on", - acc_cella_23.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_24 - ( - .aclr(aclr), - .cin(wire_acc_cella_23cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_24cout[0:0]), - .dataa(wire_acc_cella_dataa[24:24]), - .datab(wire_acc_cella_datab[24:24]), - .datac(wire_acc_cella_datac[24:24]), - .ena(clken), - .regout(wire_acc_cella_regout[24:24]), - .sload(sload)); - defparam - acc_cella_24.cin_used = "true", - acc_cella_24.lut_mask = "96e8", - acc_cella_24.operation_mode = "arithmetic", - acc_cella_24.sum_lutc_input = "cin", - acc_cella_24.synch_mode = "on", - acc_cella_24.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_25 - ( - .aclr(aclr), - .cin(wire_acc_cella_24cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_25cout[0:0]), - .dataa(wire_acc_cella_dataa[25:25]), - .datab(wire_acc_cella_datab[25:25]), - .datac(wire_acc_cella_datac[25:25]), - .ena(clken), - .regout(wire_acc_cella_regout[25:25]), - .sload(sload)); - defparam - acc_cella_25.cin_used = "true", - acc_cella_25.lut_mask = "96e8", - acc_cella_25.operation_mode = "arithmetic", - acc_cella_25.sum_lutc_input = "cin", - acc_cella_25.synch_mode = "on", - acc_cella_25.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_26 - ( - .aclr(aclr), - .cin(wire_acc_cella_25cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_26cout[0:0]), - .dataa(wire_acc_cella_dataa[26:26]), - .datab(wire_acc_cella_datab[26:26]), - .datac(wire_acc_cella_datac[26:26]), - .ena(clken), - .regout(wire_acc_cella_regout[26:26]), - .sload(sload)); - defparam - acc_cella_26.cin_used = "true", - acc_cella_26.lut_mask = "96e8", - acc_cella_26.operation_mode = "arithmetic", - acc_cella_26.sum_lutc_input = "cin", - acc_cella_26.synch_mode = "on", - acc_cella_26.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_27 - ( - .aclr(aclr), - .cin(wire_acc_cella_26cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_27cout[0:0]), - .dataa(wire_acc_cella_dataa[27:27]), - .datab(wire_acc_cella_datab[27:27]), - .datac(wire_acc_cella_datac[27:27]), - .ena(clken), - .regout(wire_acc_cella_regout[27:27]), - .sload(sload)); - defparam - acc_cella_27.cin_used = "true", - acc_cella_27.lut_mask = "96e8", - acc_cella_27.operation_mode = "arithmetic", - acc_cella_27.sum_lutc_input = "cin", - acc_cella_27.synch_mode = "on", - acc_cella_27.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_28 - ( - .aclr(aclr), - .cin(wire_acc_cella_27cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_28cout[0:0]), - .dataa(wire_acc_cella_dataa[28:28]), - .datab(wire_acc_cella_datab[28:28]), - .datac(wire_acc_cella_datac[28:28]), - .ena(clken), - .regout(wire_acc_cella_regout[28:28]), - .sload(sload)); - defparam - acc_cella_28.cin_used = "true", - acc_cella_28.lut_mask = "96e8", - acc_cella_28.operation_mode = "arithmetic", - acc_cella_28.sum_lutc_input = "cin", - acc_cella_28.synch_mode = "on", - acc_cella_28.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_29 - ( - .aclr(aclr), - .cin(wire_acc_cella_28cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_29cout[0:0]), - .dataa(wire_acc_cella_dataa[29:29]), - .datab(wire_acc_cella_datab[29:29]), - .datac(wire_acc_cella_datac[29:29]), - .ena(clken), - .regout(wire_acc_cella_regout[29:29]), - .sload(sload)); - defparam - acc_cella_29.cin_used = "true", - acc_cella_29.lut_mask = "96e8", - acc_cella_29.operation_mode = "arithmetic", - acc_cella_29.sum_lutc_input = "cin", - acc_cella_29.synch_mode = "on", - acc_cella_29.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_30 - ( - .aclr(aclr), - .cin(wire_acc_cella_29cout[0:0]), - .clk(clock), - .cout(wire_acc_cella_30cout[0:0]), - .dataa(wire_acc_cella_dataa[30:30]), - .datab(wire_acc_cella_datab[30:30]), - .datac(wire_acc_cella_datac[30:30]), - .ena(clken), - .regout(wire_acc_cella_regout[30:30]), - .sload(sload)); - defparam - acc_cella_30.cin_used = "true", - acc_cella_30.lut_mask = "96e8", - acc_cella_30.operation_mode = "arithmetic", - acc_cella_30.sum_lutc_input = "cin", - acc_cella_30.synch_mode = "on", - acc_cella_30.lpm_type = "stratix_lcell"; - stratix_lcell acc_cella_31 - ( - .aclr(aclr), - .cin(wire_acc_cella_30cout[0:0]), - .clk(clock), - .dataa(wire_acc_cella_dataa[31:31]), - .datab(wire_acc_cella_datab[31:31]), - .datac(wire_acc_cella_datac[31:31]), - .ena(clken), - .regout(wire_acc_cella_regout[31:31]), - .sload(sload)); - defparam - acc_cella_31.cin_used = "true", - acc_cella_31.lut_mask = "9696", - acc_cella_31.operation_mode = "normal", - acc_cella_31.sum_lutc_input = "cin", - acc_cella_31.synch_mode = "on", - acc_cella_31.lpm_type = "stratix_lcell"; - assign - wire_acc_cella_dataa = data, - wire_acc_cella_datab = wire_acc_cella_regout, - wire_acc_cella_datac = data; - assign - result = wire_acc_cella_regout, - sload = 1'b0; -endmodule //accum32_accum_nta -//VALID FILE - - -module accum32 ( - data, - clock, - clken, - aclr, - result)/* synthesis synthesis_clearbox = 1 */; - - input [31:0] data; - input clock; - input clken; - input aclr; - output [31:0] result; - - wire [31:0] sub_wire0; - wire [31:0] result = sub_wire0[31:0]; - - accum32_accum_nta accum32_accum_nta_component ( - .clken (clken), - .aclr (aclr), - .clock (clock), - .data (data), - .result (sub_wire0)); - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32" -// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32" -// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0" -// Retrieval info: PRIVATE: SLOAD NUMERIC "0" -// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0" -// Retrieval info: PRIVATE: CIN NUMERIC "0" -// Retrieval info: PRIVATE: CLKEN NUMERIC "1" -// Retrieval info: PRIVATE: ACLR NUMERIC "1" -// Retrieval info: PRIVATE: COUT NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0" -// Retrieval info: PRIVATE: LATENCY NUMERIC "0" -// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32" -// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32" -// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] -// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock -// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 -// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all diff --git a/megacells/accum32_bb.v b/megacells/accum32_bb.v deleted file mode 100755 index 142bde88c..000000000 --- a/megacells/accum32_bb.v +++ /dev/null @@ -1,35 +0,0 @@ -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module accum32 ( - data, - clock, - clken, - aclr, - result)/* synthesis synthesis_clearbox = 1 */; - - input [31:0] data; - input clock; - input clken; - input aclr; - output [31:0] result; - -endmodule - diff --git a/megacells/accum32_inst.v b/megacells/accum32_inst.v deleted file mode 100755 index c354accae..000000000 --- a/megacells/accum32_inst.v +++ /dev/null @@ -1,7 +0,0 @@ -accum32 accum32_inst ( - .data ( data_sig ), - .clock ( clock_sig ), - .clken ( clken_sig ), - .aclr ( aclr_sig ), - .result ( result_sig ) - ); diff --git a/megacells/add32.bsf b/megacells/add32.bsf deleted file mode 100755 index b2da9fc2a..000000000 --- a/megacells/add32.bsf +++ /dev/null @@ -1,62 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2003 Altera Corporation -Any megafunction design, and related netlist (encrypted or decrypted), -support information, device programming or simulation file, and any other -associated documentation or information provided by Altera or a partner -under Altera's Megafunction Partnership Program may be used only -to program PLD devices (but not masked PLD devices) from Altera. Any -other use of such megafunction design, netlist, support information, -device programming or simulation file, or any other related documentation -or information is prohibited for any other purpose, including, but not -limited to modification, reverse engineering, de-compiling, or use with -any other silicon devices, unless such use is explicitly licensed under -a separate agreement with Altera or a megafunction partner. Title to the -intellectual property, including patents, copyrights, trademarks, trade -secrets, or maskworks, embodied in any such megafunction design, netlist, -support information, device programming or simulation file, or any other -related documentation or information provided by Altera or a megafunction -partner, remains with Altera, the megafunction partner, or their respective -licensors. No other licenses, including any licenses needed under any third -party's intellectual property, are provided herein. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 96) - (text "add32" (rect 58 2 111 21)(font "Arial" (font_size 10))) - (text "inst" (rect 8 77 31 92)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "dataa[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) - (text "dataa[7..0]" (rect 4 24 66 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "datab[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) - (text "datab[7..0]" (rect 4 56 66 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (port - (pt 160 56) - (output) - (text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) - (text "result[7..0]" (rect 95 40 157 56)(font "Arial" (font_size 8))) - (line (pt 160 56)(pt 96 56)(line_width 3)) - ) - (drawing - (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8))) - (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8))) - (text "A+B" (rect 68 48 94 64)(font "Arial" (font_size 8))) - (line (pt 64 32)(pt 96 40)(line_width 1)) - (line (pt 96 40)(pt 96 72)(line_width 1)) - (line (pt 96 72)(pt 64 80)(line_width 1)) - (line (pt 64 80)(pt 64 32)(line_width 1)) - ) -) diff --git a/megacells/add32.cmp b/megacells/add32.cmp deleted file mode 100755 index 3b120176d..000000000 --- a/megacells/add32.cmp +++ /dev/null @@ -1,29 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -component add32 - PORT - ( - dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -end component; diff --git a/megacells/add32.inc b/megacells/add32.inc deleted file mode 100755 index 675525713..000000000 --- a/megacells/add32.inc +++ /dev/null @@ -1,30 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -FUNCTION add32 -( - dataa[7..0], - datab[7..0] -) - -RETURNS ( - result[7..0] -); diff --git a/megacells/add32.v b/megacells/add32.v deleted file mode 100755 index d8090617a..000000000 --- a/megacells/add32.v +++ /dev/null @@ -1,221 +0,0 @@ -// megafunction wizard: %LPM_ADD_SUB%CBX% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: lpm_add_sub - -// ============================================================ -// File Name: add32.v -// Megafunction Name(s): -// lpm_add_sub -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// ************************************************************ - - -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result -//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END - -//synthesis_resources = lut 8 -module add32_add_sub_nq7 - ( - dataa, - datab, - result) /* synthesis synthesis_clearbox=1 */; - input [7:0] dataa; - input [7:0] datab; - output [7:0] result; - - wire [7:0] wire_add_sub_cella_combout; - wire [0:0] wire_add_sub_cella_0cout; - wire [0:0] wire_add_sub_cella_1cout; - wire [0:0] wire_add_sub_cella_2cout; - wire [0:0] wire_add_sub_cella_3cout; - wire [0:0] wire_add_sub_cella_4cout; - wire [0:0] wire_add_sub_cella_5cout; - wire [0:0] wire_add_sub_cella_6cout; - wire [7:0] wire_add_sub_cella_dataa; - wire [7:0] wire_add_sub_cella_datab; - - stratix_lcell add_sub_cella_0 - ( - .cin(1'b0), - .combout(wire_add_sub_cella_combout[0:0]), - .cout(wire_add_sub_cella_0cout[0:0]), - .dataa(wire_add_sub_cella_dataa[0:0]), - .datab(wire_add_sub_cella_datab[0:0])); - defparam - add_sub_cella_0.cin_used = "true", - add_sub_cella_0.lut_mask = "96e8", - add_sub_cella_0.operation_mode = "arithmetic", - add_sub_cella_0.sum_lutc_input = "cin", - add_sub_cella_0.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_1 - ( - .cin(wire_add_sub_cella_0cout[0:0]), - .combout(wire_add_sub_cella_combout[1:1]), - .cout(wire_add_sub_cella_1cout[0:0]), - .dataa(wire_add_sub_cella_dataa[1:1]), - .datab(wire_add_sub_cella_datab[1:1])); - defparam - add_sub_cella_1.cin_used = "true", - add_sub_cella_1.lut_mask = "96e8", - add_sub_cella_1.operation_mode = "arithmetic", - add_sub_cella_1.sum_lutc_input = "cin", - add_sub_cella_1.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_2 - ( - .cin(wire_add_sub_cella_1cout[0:0]), - .combout(wire_add_sub_cella_combout[2:2]), - .cout(wire_add_sub_cella_2cout[0:0]), - .dataa(wire_add_sub_cella_dataa[2:2]), - .datab(wire_add_sub_cella_datab[2:2])); - defparam - add_sub_cella_2.cin_used = "true", - add_sub_cella_2.lut_mask = "96e8", - add_sub_cella_2.operation_mode = "arithmetic", - add_sub_cella_2.sum_lutc_input = "cin", - add_sub_cella_2.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_3 - ( - .cin(wire_add_sub_cella_2cout[0:0]), - .combout(wire_add_sub_cella_combout[3:3]), - .cout(wire_add_sub_cella_3cout[0:0]), - .dataa(wire_add_sub_cella_dataa[3:3]), - .datab(wire_add_sub_cella_datab[3:3])); - defparam - add_sub_cella_3.cin_used = "true", - add_sub_cella_3.lut_mask = "96e8", - add_sub_cella_3.operation_mode = "arithmetic", - add_sub_cella_3.sum_lutc_input = "cin", - add_sub_cella_3.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_4 - ( - .cin(wire_add_sub_cella_3cout[0:0]), - .combout(wire_add_sub_cella_combout[4:4]), - .cout(wire_add_sub_cella_4cout[0:0]), - .dataa(wire_add_sub_cella_dataa[4:4]), - .datab(wire_add_sub_cella_datab[4:4])); - defparam - add_sub_cella_4.cin_used = "true", - add_sub_cella_4.lut_mask = "96e8", - add_sub_cella_4.operation_mode = "arithmetic", - add_sub_cella_4.sum_lutc_input = "cin", - add_sub_cella_4.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_5 - ( - .cin(wire_add_sub_cella_4cout[0:0]), - .combout(wire_add_sub_cella_combout[5:5]), - .cout(wire_add_sub_cella_5cout[0:0]), - .dataa(wire_add_sub_cella_dataa[5:5]), - .datab(wire_add_sub_cella_datab[5:5])); - defparam - add_sub_cella_5.cin_used = "true", - add_sub_cella_5.lut_mask = "96e8", - add_sub_cella_5.operation_mode = "arithmetic", - add_sub_cella_5.sum_lutc_input = "cin", - add_sub_cella_5.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_6 - ( - .cin(wire_add_sub_cella_5cout[0:0]), - .combout(wire_add_sub_cella_combout[6:6]), - .cout(wire_add_sub_cella_6cout[0:0]), - .dataa(wire_add_sub_cella_dataa[6:6]), - .datab(wire_add_sub_cella_datab[6:6])); - defparam - add_sub_cella_6.cin_used = "true", - add_sub_cella_6.lut_mask = "96e8", - add_sub_cella_6.operation_mode = "arithmetic", - add_sub_cella_6.sum_lutc_input = "cin", - add_sub_cella_6.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_7 - ( - .cin(wire_add_sub_cella_6cout[0:0]), - .combout(wire_add_sub_cella_combout[7:7]), - .dataa(wire_add_sub_cella_dataa[7:7]), - .datab(wire_add_sub_cella_datab[7:7])); - defparam - add_sub_cella_7.cin_used = "true", - add_sub_cella_7.lut_mask = "9696", - add_sub_cella_7.operation_mode = "normal", - add_sub_cella_7.sum_lutc_input = "cin", - add_sub_cella_7.lpm_type = "stratix_lcell"; - assign - wire_add_sub_cella_dataa = dataa, - wire_add_sub_cella_datab = datab; - assign - result = wire_add_sub_cella_combout; -endmodule //add32_add_sub_nq7 -//VALID FILE - - -module add32 ( - dataa, - datab, - result)/* synthesis synthesis_clearbox = 1 */; - - input [7:0] dataa; - input [7:0] datab; - output [7:0] result; - - wire [7:0] sub_wire0; - wire [7:0] result = sub_wire0[7:0]; - - add32_add_sub_nq7 add32_add_sub_nq7_component ( - .dataa (dataa), - .datab (datab), - .result (sub_wire0)); - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: nBit NUMERIC "8" -// Retrieval info: PRIVATE: Function NUMERIC "0" -// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" -// Retrieval info: PRIVATE: ConstantA NUMERIC "0" -// Retrieval info: PRIVATE: ConstantB NUMERIC "0" -// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" -// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" -// Retrieval info: PRIVATE: CarryIn NUMERIC "0" -// Retrieval info: PRIVATE: CarryOut NUMERIC "0" -// Retrieval info: PRIVATE: Overflow NUMERIC "0" -// Retrieval info: PRIVATE: Latency NUMERIC "0" -// Retrieval info: PRIVATE: aclr NUMERIC "0" -// Retrieval info: PRIVATE: clken NUMERIC "0" -// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" -// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD" -// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" -// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] -// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0] -// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0] -// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 -// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0 -// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0 -// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/add32_bb.v b/megacells/add32_bb.v deleted file mode 100755 index 8d1588cc6..000000000 --- a/megacells/add32_bb.v +++ /dev/null @@ -1,31 +0,0 @@ -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module add32 ( - dataa, - datab, - result)/* synthesis synthesis_clearbox = 1 */; - - input [7:0] dataa; - input [7:0] datab; - output [7:0] result; - -endmodule - diff --git a/megacells/add32_inst.v b/megacells/add32_inst.v deleted file mode 100755 index bc7e6d441..000000000 --- a/megacells/add32_inst.v +++ /dev/null @@ -1,5 +0,0 @@ -add32 add32_inst ( - .dataa ( dataa_sig ), - .datab ( datab_sig ), - .result ( result_sig ) - ); diff --git a/megacells/addsub16.bsf b/megacells/addsub16.bsf deleted file mode 100755 index 9ed6b72ae..000000000 --- a/megacells/addsub16.bsf +++ /dev/null @@ -1,96 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2003 Altera Corporation -Any megafunction design, and related netlist (encrypted or decrypted), -support information, device programming or simulation file, and any other -associated documentation or information provided by Altera or a partner -under Altera's Megafunction Partnership Program may be used only -to program PLD devices (but not masked PLD devices) from Altera. Any -other use of such megafunction design, netlist, support information, -device programming or simulation file, or any other related documentation -or information is prohibited for any other purpose, including, but not -limited to modification, reverse engineering, de-compiling, or use with -any other silicon devices, unless such use is explicitly licensed under -a separate agreement with Altera or a megafunction partner. Title to the -intellectual property, including patents, copyrights, trademarks, trade -secrets, or maskworks, embodied in any such megafunction design, netlist, -support information, device programming or simulation file, or any other -related documentation or information provided by Altera or a megafunction -partner, remains with Altera, the megafunction partner, or their respective -licensors. No other licenses, including any licenses needed under any third -party's intellectual property, are provided herein. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 144) - (text "addsub16" (rect 45 2 128 21)(font "Arial" (font_size 10))) - (text "inst" (rect 8 125 31 140)(font "Arial" )) - (port - (pt 0 56) - (input) - (text "dataa[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) - (text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "datab[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) - (text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 1)) - ) - (port - (pt 0 32) - (input) - (text "add_sub" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 80 32)(line_width 1)) - ) - (port - (pt 0 112) - (input) - (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clken" (rect 4 96 35 112)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 74 112)(line_width 1)) - ) - (port - (pt 0 128) - (input) - (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) - (text "aclr" (rect 4 112 25 128)(font "Arial" (font_size 8))) - (line (pt 0 128)(pt 85 128)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "result[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) - (text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 96 72)(line_width 3)) - ) - (drawing - (text "A" (rect 66 48 75 64)(font "Arial" (font_size 8))) - (text "B" (rect 66 80 75 96)(font "Arial" (font_size 8))) - (text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8))) - (line (pt 64 48)(pt 96 56)(line_width 1)) - (line (pt 96 56)(pt 96 88)(line_width 1)) - (line (pt 96 88)(pt 64 96)(line_width 1)) - (line (pt 64 96)(pt 64 48)(line_width 1)) - (line (pt 80 32)(pt 80 52)(line_width 1)) - (line (pt 106 40)(pt 125 40)(line_width 1)) - (line (pt 74 112)(pt 74 93)(line_width 1)) - (line (pt 85 128)(pt 85 90)(line_width 1)) - (line (pt 64 66)(pt 70 72)(line_width 1)) - (line (pt 70 72)(pt 64 78)(line_width 1)) - ) -) diff --git a/megacells/addsub16.cmp b/megacells/addsub16.cmp deleted file mode 100755 index e32e01b31..000000000 --- a/megacells/addsub16.cmp +++ /dev/null @@ -1,33 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -component addsub16 - PORT - ( - add_sub : IN STD_LOGIC ; - dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - clock : IN STD_LOGIC ; - aclr : IN STD_LOGIC ; - clken : IN STD_LOGIC ; - result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) - ); -end component; diff --git a/megacells/addsub16.inc b/megacells/addsub16.inc deleted file mode 100755 index 846f301d2..000000000 --- a/megacells/addsub16.inc +++ /dev/null @@ -1,34 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -FUNCTION addsub16 -( - add_sub, - dataa[15..0], - datab[15..0], - clock, - aclr, - clken -) - -RETURNS ( - result[15..0] -); diff --git a/megacells/addsub16.v b/megacells/addsub16.v deleted file mode 100755 index 431af3e43..000000000 --- a/megacells/addsub16.v +++ /dev/null @@ -1,438 +0,0 @@ -// megafunction wizard: %LPM_ADD_SUB%CBX% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: lpm_add_sub - -// ============================================================ -// File Name: addsub16.v -// Megafunction Name(s): -// lpm_add_sub -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// ************************************************************ - - -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result -//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END - -//synthesis_resources = lut 17 -module addsub16_add_sub_gp9 - ( - aclr, - add_sub, - clken, - clock, - dataa, - datab, - result) /* synthesis synthesis_clearbox=1 */; - input aclr; - input add_sub; - input clken; - input clock; - input [15:0] dataa; - input [15:0] datab; - output [15:0] result; - - wire [0:0] wire_add_sub_cella_0cout; - wire [0:0] wire_add_sub_cella_1cout; - wire [0:0] wire_add_sub_cella_2cout; - wire [0:0] wire_add_sub_cella_3cout; - wire [0:0] wire_add_sub_cella_4cout; - wire [0:0] wire_add_sub_cella_5cout; - wire [0:0] wire_add_sub_cella_6cout; - wire [0:0] wire_add_sub_cella_7cout; - wire [0:0] wire_add_sub_cella_8cout; - wire [0:0] wire_add_sub_cella_9cout; - wire [0:0] wire_add_sub_cella_10cout; - wire [0:0] wire_add_sub_cella_11cout; - wire [0:0] wire_add_sub_cella_12cout; - wire [0:0] wire_add_sub_cella_13cout; - wire [0:0] wire_add_sub_cella_14cout; - wire [15:0] wire_add_sub_cella_dataa; - wire [15:0] wire_add_sub_cella_datab; - wire [15:0] wire_add_sub_cella_regout; - wire wire_strx_lcell1_cout; - - stratix_lcell add_sub_cella_0 - ( - .aclr(aclr), - .cin(wire_strx_lcell1_cout), - .clk(clock), - .cout(wire_add_sub_cella_0cout[0:0]), - .dataa(wire_add_sub_cella_dataa[0:0]), - .datab(wire_add_sub_cella_datab[0:0]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[0:0])); - defparam - add_sub_cella_0.cin_used = "true", - add_sub_cella_0.lut_mask = "96e8", - add_sub_cella_0.operation_mode = "arithmetic", - add_sub_cella_0.sum_lutc_input = "cin", - add_sub_cella_0.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_1 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_0cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_1cout[0:0]), - .dataa(wire_add_sub_cella_dataa[1:1]), - .datab(wire_add_sub_cella_datab[1:1]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[1:1])); - defparam - add_sub_cella_1.cin_used = "true", - add_sub_cella_1.lut_mask = "96e8", - add_sub_cella_1.operation_mode = "arithmetic", - add_sub_cella_1.sum_lutc_input = "cin", - add_sub_cella_1.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_2 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_1cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_2cout[0:0]), - .dataa(wire_add_sub_cella_dataa[2:2]), - .datab(wire_add_sub_cella_datab[2:2]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[2:2])); - defparam - add_sub_cella_2.cin_used = "true", - add_sub_cella_2.lut_mask = "96e8", - add_sub_cella_2.operation_mode = "arithmetic", - add_sub_cella_2.sum_lutc_input = "cin", - add_sub_cella_2.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_3 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_2cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_3cout[0:0]), - .dataa(wire_add_sub_cella_dataa[3:3]), - .datab(wire_add_sub_cella_datab[3:3]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[3:3])); - defparam - add_sub_cella_3.cin_used = "true", - add_sub_cella_3.lut_mask = "96e8", - add_sub_cella_3.operation_mode = "arithmetic", - add_sub_cella_3.sum_lutc_input = "cin", - add_sub_cella_3.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_4 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_3cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_4cout[0:0]), - .dataa(wire_add_sub_cella_dataa[4:4]), - .datab(wire_add_sub_cella_datab[4:4]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[4:4])); - defparam - add_sub_cella_4.cin_used = "true", - add_sub_cella_4.lut_mask = "96e8", - add_sub_cella_4.operation_mode = "arithmetic", - add_sub_cella_4.sum_lutc_input = "cin", - add_sub_cella_4.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_5 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_4cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_5cout[0:0]), - .dataa(wire_add_sub_cella_dataa[5:5]), - .datab(wire_add_sub_cella_datab[5:5]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[5:5])); - defparam - add_sub_cella_5.cin_used = "true", - add_sub_cella_5.lut_mask = "96e8", - add_sub_cella_5.operation_mode = "arithmetic", - add_sub_cella_5.sum_lutc_input = "cin", - add_sub_cella_5.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_6 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_5cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_6cout[0:0]), - .dataa(wire_add_sub_cella_dataa[6:6]), - .datab(wire_add_sub_cella_datab[6:6]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[6:6])); - defparam - add_sub_cella_6.cin_used = "true", - add_sub_cella_6.lut_mask = "96e8", - add_sub_cella_6.operation_mode = "arithmetic", - add_sub_cella_6.sum_lutc_input = "cin", - add_sub_cella_6.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_7 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_6cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_7cout[0:0]), - .dataa(wire_add_sub_cella_dataa[7:7]), - .datab(wire_add_sub_cella_datab[7:7]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[7:7])); - defparam - add_sub_cella_7.cin_used = "true", - add_sub_cella_7.lut_mask = "96e8", - add_sub_cella_7.operation_mode = "arithmetic", - add_sub_cella_7.sum_lutc_input = "cin", - add_sub_cella_7.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_8 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_7cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_8cout[0:0]), - .dataa(wire_add_sub_cella_dataa[8:8]), - .datab(wire_add_sub_cella_datab[8:8]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[8:8])); - defparam - add_sub_cella_8.cin_used = "true", - add_sub_cella_8.lut_mask = "96e8", - add_sub_cella_8.operation_mode = "arithmetic", - add_sub_cella_8.sum_lutc_input = "cin", - add_sub_cella_8.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_9 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_8cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_9cout[0:0]), - .dataa(wire_add_sub_cella_dataa[9:9]), - .datab(wire_add_sub_cella_datab[9:9]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[9:9])); - defparam - add_sub_cella_9.cin_used = "true", - add_sub_cella_9.lut_mask = "96e8", - add_sub_cella_9.operation_mode = "arithmetic", - add_sub_cella_9.sum_lutc_input = "cin", - add_sub_cella_9.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_10 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_9cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_10cout[0:0]), - .dataa(wire_add_sub_cella_dataa[10:10]), - .datab(wire_add_sub_cella_datab[10:10]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[10:10])); - defparam - add_sub_cella_10.cin_used = "true", - add_sub_cella_10.lut_mask = "96e8", - add_sub_cella_10.operation_mode = "arithmetic", - add_sub_cella_10.sum_lutc_input = "cin", - add_sub_cella_10.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_11 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_10cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_11cout[0:0]), - .dataa(wire_add_sub_cella_dataa[11:11]), - .datab(wire_add_sub_cella_datab[11:11]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[11:11])); - defparam - add_sub_cella_11.cin_used = "true", - add_sub_cella_11.lut_mask = "96e8", - add_sub_cella_11.operation_mode = "arithmetic", - add_sub_cella_11.sum_lutc_input = "cin", - add_sub_cella_11.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_12 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_11cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_12cout[0:0]), - .dataa(wire_add_sub_cella_dataa[12:12]), - .datab(wire_add_sub_cella_datab[12:12]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[12:12])); - defparam - add_sub_cella_12.cin_used = "true", - add_sub_cella_12.lut_mask = "96e8", - add_sub_cella_12.operation_mode = "arithmetic", - add_sub_cella_12.sum_lutc_input = "cin", - add_sub_cella_12.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_13 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_12cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_13cout[0:0]), - .dataa(wire_add_sub_cella_dataa[13:13]), - .datab(wire_add_sub_cella_datab[13:13]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[13:13])); - defparam - add_sub_cella_13.cin_used = "true", - add_sub_cella_13.lut_mask = "96e8", - add_sub_cella_13.operation_mode = "arithmetic", - add_sub_cella_13.sum_lutc_input = "cin", - add_sub_cella_13.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_14 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_13cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_14cout[0:0]), - .dataa(wire_add_sub_cella_dataa[14:14]), - .datab(wire_add_sub_cella_datab[14:14]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[14:14])); - defparam - add_sub_cella_14.cin_used = "true", - add_sub_cella_14.lut_mask = "96e8", - add_sub_cella_14.operation_mode = "arithmetic", - add_sub_cella_14.sum_lutc_input = "cin", - add_sub_cella_14.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_15 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_14cout[0:0]), - .clk(clock), - .dataa(wire_add_sub_cella_dataa[15:15]), - .datab(wire_add_sub_cella_datab[15:15]), - .ena(clken), - .inverta((~ add_sub)), - .regout(wire_add_sub_cella_regout[15:15])); - defparam - add_sub_cella_15.cin_used = "true", - add_sub_cella_15.lut_mask = "9696", - add_sub_cella_15.operation_mode = "normal", - add_sub_cella_15.sum_lutc_input = "cin", - add_sub_cella_15.lpm_type = "stratix_lcell"; - assign - wire_add_sub_cella_dataa = datab, - wire_add_sub_cella_datab = dataa; - stratix_lcell strx_lcell1 - ( - .cout(wire_strx_lcell1_cout), - .dataa(1'b0), - .datab((~ add_sub)), - .inverta((~ add_sub))); - defparam - strx_lcell1.cin_used = "false", - strx_lcell1.lut_mask = "00cc", - strx_lcell1.operation_mode = "arithmetic", - strx_lcell1.lpm_type = "stratix_lcell"; - assign - result = wire_add_sub_cella_regout; -endmodule //addsub16_add_sub_gp9 -//VALID FILE - - -module addsub16 ( - add_sub, - dataa, - datab, - clock, - aclr, - clken, - result)/* synthesis synthesis_clearbox = 1 */; - - input add_sub; - input [15:0] dataa; - input [15:0] datab; - input clock; - input aclr; - input clken; - output [15:0] result; - - wire [15:0] sub_wire0; - wire [15:0] result = sub_wire0[15:0]; - - addsub16_add_sub_gp9 addsub16_add_sub_gp9_component ( - .dataa (dataa), - .add_sub (add_sub), - .datab (datab), - .clken (clken), - .aclr (aclr), - .clock (clock), - .result (sub_wire0)); - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: nBit NUMERIC "16" -// Retrieval info: PRIVATE: Function NUMERIC "2" -// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" -// Retrieval info: PRIVATE: ConstantA NUMERIC "0" -// Retrieval info: PRIVATE: ConstantB NUMERIC "0" -// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" -// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" -// Retrieval info: PRIVATE: CarryIn NUMERIC "0" -// Retrieval info: PRIVATE: CarryOut NUMERIC "0" -// Retrieval info: PRIVATE: Overflow NUMERIC "0" -// Retrieval info: PRIVATE: Latency NUMERIC "1" -// Retrieval info: PRIVATE: aclr NUMERIC "1" -// Retrieval info: PRIVATE: clken NUMERIC "1" -// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED" -// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" -// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" -// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub -// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] -// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0] -// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0] -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken -// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0 -// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 -// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0 -// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 -// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/addsub16_bb.v b/megacells/addsub16_bb.v deleted file mode 100755 index 8e1e7c69f..000000000 --- a/megacells/addsub16_bb.v +++ /dev/null @@ -1,39 +0,0 @@ -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module addsub16 ( - add_sub, - dataa, - datab, - clock, - aclr, - clken, - result)/* synthesis synthesis_clearbox = 1 */; - - input add_sub; - input [15:0] dataa; - input [15:0] datab; - input clock; - input aclr; - input clken; - output [15:0] result; - -endmodule - diff --git a/megacells/addsub16_inst.v b/megacells/addsub16_inst.v deleted file mode 100755 index 4a81ff2ee..000000000 --- a/megacells/addsub16_inst.v +++ /dev/null @@ -1,9 +0,0 @@ -addsub16 addsub16_inst ( - .add_sub ( add_sub_sig ), - .dataa ( dataa_sig ), - .datab ( datab_sig ), - .clock ( clock_sig ), - .aclr ( aclr_sig ), - .clken ( clken_sig ), - .result ( result_sig ) - ); diff --git a/megacells/bustri.bsf b/megacells/bustri.bsf deleted file mode 100755 index f1bc3ca7f..000000000 --- a/megacells/bustri.bsf +++ /dev/null @@ -1,62 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2003 Altera Corporation -Any megafunction design, and related netlist (encrypted or decrypted), -support information, device programming or simulation file, and any other -associated documentation or information provided by Altera or a partner -under Altera's Megafunction Partnership Program may be used only -to program PLD devices (but not masked PLD devices) from Altera. Any -other use of such megafunction design, netlist, support information, -device programming or simulation file, or any other related documentation -or information is prohibited for any other purpose, including, but not -limited to modification, reverse engineering, de-compiling, or use with -any other silicon devices, unless such use is explicitly licensed under -a separate agreement with Altera or a megafunction partner. Title to the -intellectual property, including patents, copyrights, trademarks, trade -secrets, or maskworks, embodied in any such megafunction design, netlist, -support information, device programming or simulation file, or any other -related documentation or information provided by Altera or a megafunction -partner, remains with Altera, the megafunction partner, or their respective -licensors. No other licenses, including any licenses needed under any third -party's intellectual property, are provided herein. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 40) - (text "bustri" (rect 24 1 61 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 80 24) - (bidir) - (text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) - (text "tridata[15..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 80 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "16" (rect 61 25 71 37)(font "Arial" )) - (text "16" (rect 13 25 23 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 56 28)(pt 64 20)(line_width 1)) - (line (pt 8 28)(pt 16 20)(line_width 1)) - ) -) diff --git a/megacells/bustri.cmp b/megacells/bustri.cmp deleted file mode 100755 index 87599ca66..000000000 --- a/megacells/bustri.cmp +++ /dev/null @@ -1,29 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -component bustri - PORT - ( - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - enabledt : IN STD_LOGIC ; - tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) - ); -end component; diff --git a/megacells/bustri.inc b/megacells/bustri.inc deleted file mode 100755 index 399950389..000000000 --- a/megacells/bustri.inc +++ /dev/null @@ -1,30 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -FUNCTION bustri -( - data[15..0], - enabledt -) - -RETURNS ( - tridata[15..0] -); diff --git a/megacells/bustri.v b/megacells/bustri.v deleted file mode 100755 index e40c69476..000000000 --- a/megacells/bustri.v +++ /dev/null @@ -1,71 +0,0 @@ -// megafunction wizard: %LPM_BUSTRI% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: lpm_bustri - -// ============================================================ -// File Name: bustri.v -// Megafunction Name(s): -// lpm_bustri -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// ************************************************************ - - -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -module bustri ( - data, - enabledt, - tridata); - - input [15:0] data; - input enabledt; - inout [15:0] tridata; - - - lpm_bustri lpm_bustri_component ( - .tridata (tridata), - .enabledt (enabledt), - .data (data)); - defparam - lpm_bustri_component.lpm_width = 16, - lpm_bustri_component.lpm_type = "LPM_BUSTRI"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: nBit NUMERIC "16" -// Retrieval info: PRIVATE: BiDir NUMERIC "0" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" -// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0] -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt -// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0 -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 -// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/bustri_bb.v b/megacells/bustri_bb.v deleted file mode 100755 index 4cbc1609c..000000000 --- a/megacells/bustri_bb.v +++ /dev/null @@ -1,31 +0,0 @@ -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module bustri ( - data, - enabledt, - tridata); - - input [15:0] data; - input enabledt; - inout [15:0] tridata; - -endmodule - diff --git a/megacells/bustri_inst.v b/megacells/bustri_inst.v deleted file mode 100755 index 2b4e49638..000000000 --- a/megacells/bustri_inst.v +++ /dev/null @@ -1,5 +0,0 @@ -bustri bustri_inst ( - .data ( data_sig ), - .enabledt ( enabledt_sig ), - .tridata ( tridata_sig ) - ); diff --git a/megacells/clk_doubler.v b/megacells/clk_doubler.v deleted file mode 100644 index b3762a960..000000000 --- a/megacells/clk_doubler.v +++ /dev/null @@ -1,198 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: clk_doubler.v -// Megafunction Name(s): -// altpll -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 4.2 Build 156 11/29/2004 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2004 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module clk_doubler ( - inclk0, - c0); - - input inclk0; - output c0; - - wire [5:0] sub_wire0; - wire [0:0] sub_wire4 = 1'h0; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; - wire sub_wire2 = inclk0; - wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; - - altpll altpll_component ( - .inclk (sub_wire3), - .clk (sub_wire0) - // synopsys translate_off - , - .activeclock (), - .areset (), - .clkbad (), - .clkena (), - .clkloss (), - .clkswitch (), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena (), - .fbin (), - .locked (), - .pfdena (), - .pllena (), - .scanaclr (), - .scanclk (), - .scandata (), - .scandataout (), - .scandone (), - .scanread (), - .scanwrite (), - .sclkout0 (), - .sclkout1 () - // synopsys translate_on - ); - defparam - altpll_component.clk0_duty_cycle = 50, - altpll_component.lpm_type = "altpll", - altpll_component.clk0_multiply_by = 2, - altpll_component.inclk0_input_frequency = 15625, - altpll_component.clk0_divide_by = 1, - altpll_component.pll_type = "AUTO", - altpll_component.intended_device_family = "Cyclone", - altpll_component.operation_mode = "NORMAL", - altpll_component.compensate_clock = "CLK0", - altpll_component.clk0_phase_shift = "0"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" -// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" -// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE diff --git a/megacells/clk_doubler_bb.v b/megacells/clk_doubler_bb.v deleted file mode 100644 index 48c52e795..000000000 --- a/megacells/clk_doubler_bb.v +++ /dev/null @@ -1,143 +0,0 @@ -// megafunction wizard: %ALTPLL%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: clk_doubler.v -// Megafunction Name(s): -// altpll -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 4.2 Build 156 11/29/2004 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2004 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module clk_doubler ( - inclk0, - c0); - - input inclk0; - output c0; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" -// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" -// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE diff --git a/megacells/dspclkpll.v b/megacells/dspclkpll.v deleted file mode 100644 index 81e622137..000000000 --- a/megacells/dspclkpll.v +++ /dev/null @@ -1,237 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: dspclkpll.v -// Megafunction Name(s): -// altpll -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2004 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module dspclkpll ( - inclk0, - c0, - c1); - - input inclk0; - output c0; - output c1; - - wire [5:0] sub_wire0; - wire [0:0] sub_wire5 = 1'h0; - wire [1:1] sub_wire2 = sub_wire0[1:1]; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; - wire c1 = sub_wire2; - wire sub_wire3 = inclk0; - wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; - - altpll altpll_component ( - .inclk (sub_wire4), - .clk (sub_wire0) - // synopsys translate_off -, - .fbin (), - .pllena (), - .clkswitch (), - .areset (), - .pfdena (), - .clkena (), - .extclkena (), - .scanclk (), - .scanaclr (), - .scandata (), - .scanread (), - .scanwrite (), - .extclk (), - .clkbad (), - .activeclock (), - .locked (), - .clkloss (), - .scandataout (), - .scandone (), - .sclkout1 (), - .sclkout0 (), - .enable0 (), - .enable1 () - // synopsys translate_on - -); - defparam - altpll_component.clk1_divide_by = 1, - altpll_component.clk1_phase_shift = "0", - altpll_component.clk0_duty_cycle = 50, - altpll_component.lpm_type = "altpll", - altpll_component.clk0_multiply_by = 1, - altpll_component.inclk0_input_frequency = 15625, - altpll_component.clk0_divide_by = 1, - altpll_component.clk1_duty_cycle = 50, - altpll_component.pll_type = "AUTO", - altpll_component.clk1_multiply_by = 2, - altpll_component.clk0_time_delay = "0", - altpll_component.intended_device_family = "Cyclone", - altpll_component.operation_mode = "NORMAL", - altpll_component.compensate_clock = "CLK0", - altpll_component.clk1_time_delay = "0", - altpll_component.clk0_phase_shift = "0"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000" -// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" -// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" -// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE diff --git a/megacells/dspclkpll_bb.v b/megacells/dspclkpll_bb.v deleted file mode 100644 index 489be7bd4..000000000 --- a/megacells/dspclkpll_bb.v +++ /dev/null @@ -1,31 +0,0 @@ -//Copyright (C) 1991-2004 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module dspclkpll ( - inclk0, - c0, - c1); - - input inclk0; - output c0; - output c1; - -endmodule - diff --git a/megacells/fifo_1kx16.bsf b/megacells/fifo_1kx16.bsf deleted file mode 100755 index 2de80816f..000000000 --- a/megacells/fifo_1kx16.bsf +++ /dev/null @@ -1,107 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2006 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 160) - (text "fifo_1kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 144 25 156)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 1)) - ) - (port - (pt 0 128) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8))) - (line (pt 0 128)(pt 16 128)(line_width 1)) - ) - (port - (pt 160 32) - (output) - (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) - (line (pt 160 32)(pt 144 32)(line_width 3)) - ) - (port - (pt 160 56) - (output) - (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) - (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) - (line (pt 160 56)(pt 144 56)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 144 72)(line_width 1)) - ) - (port - (pt 160 88) - (output) - (text "almost_empty" (rect 0 0 77 14)(font "Arial" (font_size 8))) - (text "almost_empty" (rect 75 82 141 95)(font "Arial" (font_size 8))) - (line (pt 160 88)(pt 144 88)(line_width 1)) - ) - (port - (pt 160 104) - (output) - (text "usedw[9..0]" (rect 0 0 68 14)(font "Arial" (font_size 8))) - (text "usedw[9..0]" (rect 83 98 136 111)(font "Arial" (font_size 8))) - (line (pt 160 104)(pt 144 104)(line_width 3)) - ) - (drawing - (text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial" )) - (text "almost_empty < 504" (rect 58 122 144 134)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 144)(line_width 1)) - (line (pt 144 144)(pt 16 144)(line_width 1)) - (line (pt 16 144)(pt 16 16)(line_width 1)) - (line (pt 16 116)(pt 144 116)(line_width 1)) - (line (pt 16 90)(pt 22 96)(line_width 1)) - (line (pt 22 96)(pt 16 102)(line_width 1)) - ) -) diff --git a/megacells/fifo_1kx16.cmp b/megacells/fifo_1kx16.cmp deleted file mode 100755 index 9b2c2c0c3..000000000 --- a/megacells/fifo_1kx16.cmp +++ /dev/null @@ -1,30 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component fifo_1kx16 - PORT - ( - aclr : IN STD_LOGIC ; - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rdreq : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - almost_empty : OUT STD_LOGIC ; - empty : OUT STD_LOGIC ; - full : OUT STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) - ); -end component; diff --git a/megacells/fifo_1kx16.inc b/megacells/fifo_1kx16.inc deleted file mode 100755 index 0b70afe62..000000000 --- a/megacells/fifo_1kx16.inc +++ /dev/null @@ -1,31 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION fifo_1kx16 -( - aclr, - clock, - data[15..0], - rdreq, - wrreq -) - -RETURNS ( - almost_empty, - empty, - full, - q[15..0], - usedw[9..0] -); diff --git a/megacells/fifo_1kx16.v b/megacells/fifo_1kx16.v deleted file mode 100755 index 4f7e94ef5..000000000 --- a/megacells/fifo_1kx16.v +++ /dev/null @@ -1,175 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_1kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_1kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - almost_empty, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output almost_empty; - output empty; - output full; - output [15:0] q; - output [9:0] usedw; - - wire [9:0] sub_wire0; - wire sub_wire1; - wire sub_wire2; - wire [15:0] sub_wire3; - wire sub_wire4; - wire [9:0] usedw = sub_wire0[9:0]; - wire empty = sub_wire1; - wire almost_empty = sub_wire2; - wire [15:0] q = sub_wire3[15:0]; - wire full = sub_wire4; - - scfifo scfifo_component ( - .rdreq (rdreq), - .aclr (aclr), - .clock (clock), - .wrreq (wrreq), - .data (data), - .usedw (sub_wire0), - .empty (sub_wire1), - .almost_empty (sub_wire2), - .q (sub_wire3), - .full (sub_wire4) - // synopsys translate_off - , - .sclr (), - .almost_full () - // synopsys translate_on - ); - defparam - scfifo_component.add_ram_output_register = "OFF", - scfifo_component.almost_empty_value = 504, - scfifo_component.intended_device_family = "Cyclone", - scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", - scfifo_component.lpm_numwords = 1024, - scfifo_component.lpm_showahead = "OFF", - scfifo_component.lpm_type = "scfifo", - scfifo_component.lpm_width = 16, - scfifo_component.lpm_widthu = 10, - scfifo_component.overflow_checking = "ON", - scfifo_component.underflow_checking = "ON", - scfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "1024" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 -// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE diff --git a/megacells/fifo_1kx16_bb.v b/megacells/fifo_1kx16_bb.v deleted file mode 100755 index 9d9912bc2..000000000 --- a/megacells/fifo_1kx16_bb.v +++ /dev/null @@ -1,127 +0,0 @@ -// megafunction wizard: %FIFO%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_1kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_1kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - almost_empty, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output almost_empty; - output empty; - output full; - output [15:0] q; - output [9:0] usedw; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "1024" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 -// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE diff --git a/megacells/fifo_1kx16_inst.v b/megacells/fifo_1kx16_inst.v deleted file mode 100755 index 73662dea3..000000000 --- a/megacells/fifo_1kx16_inst.v +++ /dev/null @@ -1,12 +0,0 @@ -fifo_1kx16 fifo_1kx16_inst ( - .aclr ( aclr_sig ), - .clock ( clock_sig ), - .data ( data_sig ), - .rdreq ( rdreq_sig ), - .wrreq ( wrreq_sig ), - .almost_empty ( almost_empty_sig ), - .empty ( empty_sig ), - .full ( full_sig ), - .q ( q_sig ), - .usedw ( usedw_sig ) - ); diff --git a/megacells/fifo_2k.v b/megacells/fifo_2k.v deleted file mode 100644 index 5e2a38520..000000000 --- a/megacells/fifo_2k.v +++ /dev/null @@ -1,3343 +0,0 @@ -// megafunction wizard: %FIFO%CBX% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_2k.v -// Megafunction Name(s): -// dcfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2005 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - - -//a_gray2bin device_family="Cyclone" WIDTH=11 bin gray -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END - -//synthesis_resources = -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_a_gray2bin_8m4 - ( - bin, - gray) /* synthesis synthesis_clearbox=1 */; - output [10:0] bin; - input [10:0] gray; - - wire xor0; - wire xor1; - wire xor2; - wire xor3; - wire xor4; - wire xor5; - wire xor6; - wire xor7; - wire xor8; - wire xor9; - - assign - bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, - xor0 = (gray[0] ^ xor1), - xor1 = (gray[1] ^ xor2), - xor2 = (gray[2] ^ xor3), - xor3 = (gray[3] ^ xor4), - xor4 = (gray[4] ^ xor5), - xor5 = (gray[5] ^ xor6), - xor6 = (gray[6] ^ xor7), - xor7 = (gray[7] ^ xor8), - xor8 = (gray[8] ^ xor9), - xor9 = (gray[10] ^ gray[9]); -endmodule //fifo_2k_a_gray2bin_8m4 - - -//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - -//synthesis_resources = lut 12 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_a_graycounter_726 - ( - aclr, - clock, - cnt_en, - q) /* synthesis synthesis_clearbox=1 */; - input aclr; - input clock; - input cnt_en; - output [10:0] q; - - wire [0:0] wire_countera_0cout; - wire [0:0] wire_countera_1cout; - wire [0:0] wire_countera_2cout; - wire [0:0] wire_countera_3cout; - wire [0:0] wire_countera_4cout; - wire [0:0] wire_countera_5cout; - wire [0:0] wire_countera_6cout; - wire [0:0] wire_countera_7cout; - wire [0:0] wire_countera_8cout; - wire [0:0] wire_countera_9cout; - wire [10:0] wire_countera_regout; - wire wire_parity_cout; - wire wire_parity_regout; - wire [10:0] power_modified_counter_values; - wire sclr; - wire updown; - - cyclone_lcell countera_0 - ( - .aclr(aclr), - .cin(wire_parity_cout), - .clk(clock), - .combout(), - .cout(wire_countera_0cout[0:0]), - .dataa(cnt_en), - .datab(wire_countera_regout[0:0]), - .ena(1'b1), - .regout(wire_countera_regout[0:0]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_0.cin_used = "true", - countera_0.lut_mask = "c6a0", - countera_0.operation_mode = "arithmetic", - countera_0.sum_lutc_input = "cin", - countera_0.synch_mode = "on", - countera_0.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_1 - ( - .aclr(aclr), - .cin(wire_countera_0cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_1cout[0:0]), - .dataa(power_modified_counter_values[0]), - .datab(power_modified_counter_values[1]), - .ena(1'b1), - .regout(wire_countera_regout[1:1]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_1.cin_used = "true", - countera_1.lut_mask = "6c50", - countera_1.operation_mode = "arithmetic", - countera_1.sum_lutc_input = "cin", - countera_1.synch_mode = "on", - countera_1.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_2 - ( - .aclr(aclr), - .cin(wire_countera_1cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_2cout[0:0]), - .dataa(power_modified_counter_values[1]), - .datab(power_modified_counter_values[2]), - .ena(1'b1), - .regout(wire_countera_regout[2:2]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_2.cin_used = "true", - countera_2.lut_mask = "6c50", - countera_2.operation_mode = "arithmetic", - countera_2.sum_lutc_input = "cin", - countera_2.synch_mode = "on", - countera_2.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_3 - ( - .aclr(aclr), - .cin(wire_countera_2cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_3cout[0:0]), - .dataa(power_modified_counter_values[2]), - .datab(power_modified_counter_values[3]), - .ena(1'b1), - .regout(wire_countera_regout[3:3]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_3.cin_used = "true", - countera_3.lut_mask = "6c50", - countera_3.operation_mode = "arithmetic", - countera_3.sum_lutc_input = "cin", - countera_3.synch_mode = "on", - countera_3.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_4 - ( - .aclr(aclr), - .cin(wire_countera_3cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_4cout[0:0]), - .dataa(power_modified_counter_values[3]), - .datab(power_modified_counter_values[4]), - .ena(1'b1), - .regout(wire_countera_regout[4:4]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_4.cin_used = "true", - countera_4.lut_mask = "6c50", - countera_4.operation_mode = "arithmetic", - countera_4.sum_lutc_input = "cin", - countera_4.synch_mode = "on", - countera_4.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_5 - ( - .aclr(aclr), - .cin(wire_countera_4cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_5cout[0:0]), - .dataa(power_modified_counter_values[4]), - .datab(power_modified_counter_values[5]), - .ena(1'b1), - .regout(wire_countera_regout[5:5]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_5.cin_used = "true", - countera_5.lut_mask = "6c50", - countera_5.operation_mode = "arithmetic", - countera_5.sum_lutc_input = "cin", - countera_5.synch_mode = "on", - countera_5.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_6 - ( - .aclr(aclr), - .cin(wire_countera_5cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_6cout[0:0]), - .dataa(power_modified_counter_values[5]), - .datab(power_modified_counter_values[6]), - .ena(1'b1), - .regout(wire_countera_regout[6:6]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_6.cin_used = "true", - countera_6.lut_mask = "6c50", - countera_6.operation_mode = "arithmetic", - countera_6.sum_lutc_input = "cin", - countera_6.synch_mode = "on", - countera_6.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_7 - ( - .aclr(aclr), - .cin(wire_countera_6cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_7cout[0:0]), - .dataa(power_modified_counter_values[6]), - .datab(power_modified_counter_values[7]), - .ena(1'b1), - .regout(wire_countera_regout[7:7]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_7.cin_used = "true", - countera_7.lut_mask = "6c50", - countera_7.operation_mode = "arithmetic", - countera_7.sum_lutc_input = "cin", - countera_7.synch_mode = "on", - countera_7.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_8 - ( - .aclr(aclr), - .cin(wire_countera_7cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_8cout[0:0]), - .dataa(power_modified_counter_values[7]), - .datab(power_modified_counter_values[8]), - .ena(1'b1), - .regout(wire_countera_regout[8:8]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_8.cin_used = "true", - countera_8.lut_mask = "6c50", - countera_8.operation_mode = "arithmetic", - countera_8.sum_lutc_input = "cin", - countera_8.synch_mode = "on", - countera_8.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_9 - ( - .aclr(aclr), - .cin(wire_countera_8cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_9cout[0:0]), - .dataa(power_modified_counter_values[8]), - .datab(power_modified_counter_values[9]), - .ena(1'b1), - .regout(wire_countera_regout[9:9]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_9.cin_used = "true", - countera_9.lut_mask = "6c50", - countera_9.operation_mode = "arithmetic", - countera_9.sum_lutc_input = "cin", - countera_9.synch_mode = "on", - countera_9.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_10 - ( - .aclr(aclr), - .cin(wire_countera_9cout[0:0]), - .clk(clock), - .combout(), - .cout(), - .dataa(power_modified_counter_values[10]), - .ena(1'b1), - .regout(wire_countera_regout[10:10]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datab(1'b1), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_10.cin_used = "true", - countera_10.lut_mask = "5a5a", - countera_10.operation_mode = "normal", - countera_10.sum_lutc_input = "cin", - countera_10.synch_mode = "on", - countera_10.lpm_type = "cyclone_lcell"; - cyclone_lcell parity - ( - .aclr(aclr), - .cin(updown), - .clk(clock), - .combout(), - .cout(wire_parity_cout), - .dataa(cnt_en), - .datab(wire_parity_regout), - .ena(1'b1), - .regout(wire_parity_regout), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - parity.cin_used = "true", - parity.lut_mask = "6682", - parity.operation_mode = "arithmetic", - parity.synch_mode = "on", - parity.lpm_type = "cyclone_lcell"; - assign - power_modified_counter_values = {wire_countera_regout[10:0]}, - q = power_modified_counter_values, - sclr = 1'b0, - updown = 1'b1; -endmodule //fifo_2k_a_graycounter_726 - - -//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - -//synthesis_resources = lut 12 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_a_graycounter_2r6 - ( - aclr, - clock, - cnt_en, - q) /* synthesis synthesis_clearbox=1 */; - input aclr; - input clock; - input cnt_en; - output [10:0] q; - - wire [0:0] wire_countera_0cout; - wire [0:0] wire_countera_1cout; - wire [0:0] wire_countera_2cout; - wire [0:0] wire_countera_3cout; - wire [0:0] wire_countera_4cout; - wire [0:0] wire_countera_5cout; - wire [0:0] wire_countera_6cout; - wire [0:0] wire_countera_7cout; - wire [0:0] wire_countera_8cout; - wire [0:0] wire_countera_9cout; - wire [10:0] wire_countera_regout; - wire wire_parity_cout; - wire wire_parity_regout; - wire [10:0] power_modified_counter_values; - wire sclr; - wire updown; - - cyclone_lcell countera_0 - ( - .aclr(aclr), - .cin(wire_parity_cout), - .clk(clock), - .combout(), - .cout(wire_countera_0cout[0:0]), - .dataa(cnt_en), - .datab(wire_countera_regout[0:0]), - .ena(1'b1), - .regout(wire_countera_regout[0:0]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_0.cin_used = "true", - countera_0.lut_mask = "c6a0", - countera_0.operation_mode = "arithmetic", - countera_0.sum_lutc_input = "cin", - countera_0.synch_mode = "on", - countera_0.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_1 - ( - .aclr(aclr), - .cin(wire_countera_0cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_1cout[0:0]), - .dataa(power_modified_counter_values[0]), - .datab(power_modified_counter_values[1]), - .ena(1'b1), - .regout(wire_countera_regout[1:1]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_1.cin_used = "true", - countera_1.lut_mask = "6c50", - countera_1.operation_mode = "arithmetic", - countera_1.sum_lutc_input = "cin", - countera_1.synch_mode = "on", - countera_1.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_2 - ( - .aclr(aclr), - .cin(wire_countera_1cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_2cout[0:0]), - .dataa(power_modified_counter_values[1]), - .datab(power_modified_counter_values[2]), - .ena(1'b1), - .regout(wire_countera_regout[2:2]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_2.cin_used = "true", - countera_2.lut_mask = "6c50", - countera_2.operation_mode = "arithmetic", - countera_2.sum_lutc_input = "cin", - countera_2.synch_mode = "on", - countera_2.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_3 - ( - .aclr(aclr), - .cin(wire_countera_2cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_3cout[0:0]), - .dataa(power_modified_counter_values[2]), - .datab(power_modified_counter_values[3]), - .ena(1'b1), - .regout(wire_countera_regout[3:3]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_3.cin_used = "true", - countera_3.lut_mask = "6c50", - countera_3.operation_mode = "arithmetic", - countera_3.sum_lutc_input = "cin", - countera_3.synch_mode = "on", - countera_3.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_4 - ( - .aclr(aclr), - .cin(wire_countera_3cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_4cout[0:0]), - .dataa(power_modified_counter_values[3]), - .datab(power_modified_counter_values[4]), - .ena(1'b1), - .regout(wire_countera_regout[4:4]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_4.cin_used = "true", - countera_4.lut_mask = "6c50", - countera_4.operation_mode = "arithmetic", - countera_4.sum_lutc_input = "cin", - countera_4.synch_mode = "on", - countera_4.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_5 - ( - .aclr(aclr), - .cin(wire_countera_4cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_5cout[0:0]), - .dataa(power_modified_counter_values[4]), - .datab(power_modified_counter_values[5]), - .ena(1'b1), - .regout(wire_countera_regout[5:5]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_5.cin_used = "true", - countera_5.lut_mask = "6c50", - countera_5.operation_mode = "arithmetic", - countera_5.sum_lutc_input = "cin", - countera_5.synch_mode = "on", - countera_5.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_6 - ( - .aclr(aclr), - .cin(wire_countera_5cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_6cout[0:0]), - .dataa(power_modified_counter_values[5]), - .datab(power_modified_counter_values[6]), - .ena(1'b1), - .regout(wire_countera_regout[6:6]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_6.cin_used = "true", - countera_6.lut_mask = "6c50", - countera_6.operation_mode = "arithmetic", - countera_6.sum_lutc_input = "cin", - countera_6.synch_mode = "on", - countera_6.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_7 - ( - .aclr(aclr), - .cin(wire_countera_6cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_7cout[0:0]), - .dataa(power_modified_counter_values[6]), - .datab(power_modified_counter_values[7]), - .ena(1'b1), - .regout(wire_countera_regout[7:7]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_7.cin_used = "true", - countera_7.lut_mask = "6c50", - countera_7.operation_mode = "arithmetic", - countera_7.sum_lutc_input = "cin", - countera_7.synch_mode = "on", - countera_7.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_8 - ( - .aclr(aclr), - .cin(wire_countera_7cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_8cout[0:0]), - .dataa(power_modified_counter_values[7]), - .datab(power_modified_counter_values[8]), - .ena(1'b1), - .regout(wire_countera_regout[8:8]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_8.cin_used = "true", - countera_8.lut_mask = "6c50", - countera_8.operation_mode = "arithmetic", - countera_8.sum_lutc_input = "cin", - countera_8.synch_mode = "on", - countera_8.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_9 - ( - .aclr(aclr), - .cin(wire_countera_8cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_9cout[0:0]), - .dataa(power_modified_counter_values[8]), - .datab(power_modified_counter_values[9]), - .ena(1'b1), - .regout(wire_countera_regout[9:9]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_9.cin_used = "true", - countera_9.lut_mask = "6c50", - countera_9.operation_mode = "arithmetic", - countera_9.sum_lutc_input = "cin", - countera_9.synch_mode = "on", - countera_9.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_10 - ( - .aclr(aclr), - .cin(wire_countera_9cout[0:0]), - .clk(clock), - .combout(), - .cout(), - .dataa(power_modified_counter_values[10]), - .ena(1'b1), - .regout(wire_countera_regout[10:10]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datab(1'b1), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_10.cin_used = "true", - countera_10.lut_mask = "5a5a", - countera_10.operation_mode = "normal", - countera_10.sum_lutc_input = "cin", - countera_10.synch_mode = "on", - countera_10.lpm_type = "cyclone_lcell"; - cyclone_lcell parity - ( - .aclr(aclr), - .cin(updown), - .clk(clock), - .combout(), - .cout(wire_parity_cout), - .dataa(cnt_en), - .datab((~ wire_parity_regout)), - .ena(1'b1), - .regout(wire_parity_regout), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - parity.cin_used = "true", - parity.lut_mask = "9982", - parity.operation_mode = "arithmetic", - parity.synch_mode = "on", - parity.lpm_type = "cyclone_lcell"; - assign - power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])}, - q = power_modified_counter_values, - sclr = 1'b0, - updown = 1'b1; -endmodule //fifo_2k_a_graycounter_2r6 - - -//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a -//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - -//synthesis_resources = M4K 8 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_altsyncram_6pl - ( - address_a, - address_b, - clock0, - clock1, - clocken1, - data_a, - q_b, - wren_a) /* synthesis synthesis_clearbox=1 */; - input [10:0] address_a; - input [10:0] address_b; - input clock0; - input clock1; - input clocken1; - input [15:0] data_a; - output [15:0] q_b; - input wren_a; - - wire [0:0] wire_ram_block3a_0portbdataout; - wire [0:0] wire_ram_block3a_1portbdataout; - wire [0:0] wire_ram_block3a_2portbdataout; - wire [0:0] wire_ram_block3a_3portbdataout; - wire [0:0] wire_ram_block3a_4portbdataout; - wire [0:0] wire_ram_block3a_5portbdataout; - wire [0:0] wire_ram_block3a_6portbdataout; - wire [0:0] wire_ram_block3a_7portbdataout; - wire [0:0] wire_ram_block3a_8portbdataout; - wire [0:0] wire_ram_block3a_9portbdataout; - wire [0:0] wire_ram_block3a_10portbdataout; - wire [0:0] wire_ram_block3a_11portbdataout; - wire [0:0] wire_ram_block3a_12portbdataout; - wire [0:0] wire_ram_block3a_13portbdataout; - wire [0:0] wire_ram_block3a_14portbdataout; - wire [0:0] wire_ram_block3a_15portbdataout; - wire [10:0] address_a_wire; - wire [10:0] address_b_wire; - - cyclone_ram_block ram_block3a_0 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[0]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_0portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_0.connectivity_checking = "OFF", - ram_block3a_0.logical_ram_name = "ALTSYNCRAM", - ram_block3a_0.mixed_port_feed_through_mode = "dont_care", - ram_block3a_0.operation_mode = "dual_port", - ram_block3a_0.port_a_address_width = 11, - ram_block3a_0.port_a_data_width = 1, - ram_block3a_0.port_a_first_address = 0, - ram_block3a_0.port_a_first_bit_number = 0, - ram_block3a_0.port_a_last_address = 2047, - ram_block3a_0.port_a_logical_ram_depth = 2048, - ram_block3a_0.port_a_logical_ram_width = 16, - ram_block3a_0.port_b_address_clear = "none", - ram_block3a_0.port_b_address_clock = "clock1", - ram_block3a_0.port_b_address_width = 11, - ram_block3a_0.port_b_data_out_clear = "none", - ram_block3a_0.port_b_data_out_clock = "none", - ram_block3a_0.port_b_data_width = 1, - ram_block3a_0.port_b_first_address = 0, - ram_block3a_0.port_b_first_bit_number = 0, - ram_block3a_0.port_b_last_address = 2047, - ram_block3a_0.port_b_logical_ram_depth = 2048, - ram_block3a_0.port_b_logical_ram_width = 16, - ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_0.ram_block_type = "auto", - ram_block3a_0.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_1 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[1]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_1portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_1.connectivity_checking = "OFF", - ram_block3a_1.logical_ram_name = "ALTSYNCRAM", - ram_block3a_1.mixed_port_feed_through_mode = "dont_care", - ram_block3a_1.operation_mode = "dual_port", - ram_block3a_1.port_a_address_width = 11, - ram_block3a_1.port_a_data_width = 1, - ram_block3a_1.port_a_first_address = 0, - ram_block3a_1.port_a_first_bit_number = 1, - ram_block3a_1.port_a_last_address = 2047, - ram_block3a_1.port_a_logical_ram_depth = 2048, - ram_block3a_1.port_a_logical_ram_width = 16, - ram_block3a_1.port_b_address_clear = "none", - ram_block3a_1.port_b_address_clock = "clock1", - ram_block3a_1.port_b_address_width = 11, - ram_block3a_1.port_b_data_out_clear = "none", - ram_block3a_1.port_b_data_out_clock = "none", - ram_block3a_1.port_b_data_width = 1, - ram_block3a_1.port_b_first_address = 0, - ram_block3a_1.port_b_first_bit_number = 1, - ram_block3a_1.port_b_last_address = 2047, - ram_block3a_1.port_b_logical_ram_depth = 2048, - ram_block3a_1.port_b_logical_ram_width = 16, - ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_1.ram_block_type = "auto", - ram_block3a_1.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_2 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[2]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_2portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_2.connectivity_checking = "OFF", - ram_block3a_2.logical_ram_name = "ALTSYNCRAM", - ram_block3a_2.mixed_port_feed_through_mode = "dont_care", - ram_block3a_2.operation_mode = "dual_port", - ram_block3a_2.port_a_address_width = 11, - ram_block3a_2.port_a_data_width = 1, - ram_block3a_2.port_a_first_address = 0, - ram_block3a_2.port_a_first_bit_number = 2, - ram_block3a_2.port_a_last_address = 2047, - ram_block3a_2.port_a_logical_ram_depth = 2048, - ram_block3a_2.port_a_logical_ram_width = 16, - ram_block3a_2.port_b_address_clear = "none", - ram_block3a_2.port_b_address_clock = "clock1", - ram_block3a_2.port_b_address_width = 11, - ram_block3a_2.port_b_data_out_clear = "none", - ram_block3a_2.port_b_data_out_clock = "none", - ram_block3a_2.port_b_data_width = 1, - ram_block3a_2.port_b_first_address = 0, - ram_block3a_2.port_b_first_bit_number = 2, - ram_block3a_2.port_b_last_address = 2047, - ram_block3a_2.port_b_logical_ram_depth = 2048, - ram_block3a_2.port_b_logical_ram_width = 16, - ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_2.ram_block_type = "auto", - ram_block3a_2.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_3 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[3]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_3portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_3.connectivity_checking = "OFF", - ram_block3a_3.logical_ram_name = "ALTSYNCRAM", - ram_block3a_3.mixed_port_feed_through_mode = "dont_care", - ram_block3a_3.operation_mode = "dual_port", - ram_block3a_3.port_a_address_width = 11, - ram_block3a_3.port_a_data_width = 1, - ram_block3a_3.port_a_first_address = 0, - ram_block3a_3.port_a_first_bit_number = 3, - ram_block3a_3.port_a_last_address = 2047, - ram_block3a_3.port_a_logical_ram_depth = 2048, - ram_block3a_3.port_a_logical_ram_width = 16, - ram_block3a_3.port_b_address_clear = "none", - ram_block3a_3.port_b_address_clock = "clock1", - ram_block3a_3.port_b_address_width = 11, - ram_block3a_3.port_b_data_out_clear = "none", - ram_block3a_3.port_b_data_out_clock = "none", - ram_block3a_3.port_b_data_width = 1, - ram_block3a_3.port_b_first_address = 0, - ram_block3a_3.port_b_first_bit_number = 3, - ram_block3a_3.port_b_last_address = 2047, - ram_block3a_3.port_b_logical_ram_depth = 2048, - ram_block3a_3.port_b_logical_ram_width = 16, - ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_3.ram_block_type = "auto", - ram_block3a_3.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_4 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[4]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_4portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_4.connectivity_checking = "OFF", - ram_block3a_4.logical_ram_name = "ALTSYNCRAM", - ram_block3a_4.mixed_port_feed_through_mode = "dont_care", - ram_block3a_4.operation_mode = "dual_port", - ram_block3a_4.port_a_address_width = 11, - ram_block3a_4.port_a_data_width = 1, - ram_block3a_4.port_a_first_address = 0, - ram_block3a_4.port_a_first_bit_number = 4, - ram_block3a_4.port_a_last_address = 2047, - ram_block3a_4.port_a_logical_ram_depth = 2048, - ram_block3a_4.port_a_logical_ram_width = 16, - ram_block3a_4.port_b_address_clear = "none", - ram_block3a_4.port_b_address_clock = "clock1", - ram_block3a_4.port_b_address_width = 11, - ram_block3a_4.port_b_data_out_clear = "none", - ram_block3a_4.port_b_data_out_clock = "none", - ram_block3a_4.port_b_data_width = 1, - ram_block3a_4.port_b_first_address = 0, - ram_block3a_4.port_b_first_bit_number = 4, - ram_block3a_4.port_b_last_address = 2047, - ram_block3a_4.port_b_logical_ram_depth = 2048, - ram_block3a_4.port_b_logical_ram_width = 16, - ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_4.ram_block_type = "auto", - ram_block3a_4.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_5 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[5]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_5portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_5.connectivity_checking = "OFF", - ram_block3a_5.logical_ram_name = "ALTSYNCRAM", - ram_block3a_5.mixed_port_feed_through_mode = "dont_care", - ram_block3a_5.operation_mode = "dual_port", - ram_block3a_5.port_a_address_width = 11, - ram_block3a_5.port_a_data_width = 1, - ram_block3a_5.port_a_first_address = 0, - ram_block3a_5.port_a_first_bit_number = 5, - ram_block3a_5.port_a_last_address = 2047, - ram_block3a_5.port_a_logical_ram_depth = 2048, - ram_block3a_5.port_a_logical_ram_width = 16, - ram_block3a_5.port_b_address_clear = "none", - ram_block3a_5.port_b_address_clock = "clock1", - ram_block3a_5.port_b_address_width = 11, - ram_block3a_5.port_b_data_out_clear = "none", - ram_block3a_5.port_b_data_out_clock = "none", - ram_block3a_5.port_b_data_width = 1, - ram_block3a_5.port_b_first_address = 0, - ram_block3a_5.port_b_first_bit_number = 5, - ram_block3a_5.port_b_last_address = 2047, - ram_block3a_5.port_b_logical_ram_depth = 2048, - ram_block3a_5.port_b_logical_ram_width = 16, - ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_5.ram_block_type = "auto", - ram_block3a_5.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_6 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[6]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_6portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_6.connectivity_checking = "OFF", - ram_block3a_6.logical_ram_name = "ALTSYNCRAM", - ram_block3a_6.mixed_port_feed_through_mode = "dont_care", - ram_block3a_6.operation_mode = "dual_port", - ram_block3a_6.port_a_address_width = 11, - ram_block3a_6.port_a_data_width = 1, - ram_block3a_6.port_a_first_address = 0, - ram_block3a_6.port_a_first_bit_number = 6, - ram_block3a_6.port_a_last_address = 2047, - ram_block3a_6.port_a_logical_ram_depth = 2048, - ram_block3a_6.port_a_logical_ram_width = 16, - ram_block3a_6.port_b_address_clear = "none", - ram_block3a_6.port_b_address_clock = "clock1", - ram_block3a_6.port_b_address_width = 11, - ram_block3a_6.port_b_data_out_clear = "none", - ram_block3a_6.port_b_data_out_clock = "none", - ram_block3a_6.port_b_data_width = 1, - ram_block3a_6.port_b_first_address = 0, - ram_block3a_6.port_b_first_bit_number = 6, - ram_block3a_6.port_b_last_address = 2047, - ram_block3a_6.port_b_logical_ram_depth = 2048, - ram_block3a_6.port_b_logical_ram_width = 16, - ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_6.ram_block_type = "auto", - ram_block3a_6.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_7 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[7]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_7portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_7.connectivity_checking = "OFF", - ram_block3a_7.logical_ram_name = "ALTSYNCRAM", - ram_block3a_7.mixed_port_feed_through_mode = "dont_care", - ram_block3a_7.operation_mode = "dual_port", - ram_block3a_7.port_a_address_width = 11, - ram_block3a_7.port_a_data_width = 1, - ram_block3a_7.port_a_first_address = 0, - ram_block3a_7.port_a_first_bit_number = 7, - ram_block3a_7.port_a_last_address = 2047, - ram_block3a_7.port_a_logical_ram_depth = 2048, - ram_block3a_7.port_a_logical_ram_width = 16, - ram_block3a_7.port_b_address_clear = "none", - ram_block3a_7.port_b_address_clock = "clock1", - ram_block3a_7.port_b_address_width = 11, - ram_block3a_7.port_b_data_out_clear = "none", - ram_block3a_7.port_b_data_out_clock = "none", - ram_block3a_7.port_b_data_width = 1, - ram_block3a_7.port_b_first_address = 0, - ram_block3a_7.port_b_first_bit_number = 7, - ram_block3a_7.port_b_last_address = 2047, - ram_block3a_7.port_b_logical_ram_depth = 2048, - ram_block3a_7.port_b_logical_ram_width = 16, - ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_7.ram_block_type = "auto", - ram_block3a_7.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_8 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[8]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_8portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_8.connectivity_checking = "OFF", - ram_block3a_8.logical_ram_name = "ALTSYNCRAM", - ram_block3a_8.mixed_port_feed_through_mode = "dont_care", - ram_block3a_8.operation_mode = "dual_port", - ram_block3a_8.port_a_address_width = 11, - ram_block3a_8.port_a_data_width = 1, - ram_block3a_8.port_a_first_address = 0, - ram_block3a_8.port_a_first_bit_number = 8, - ram_block3a_8.port_a_last_address = 2047, - ram_block3a_8.port_a_logical_ram_depth = 2048, - ram_block3a_8.port_a_logical_ram_width = 16, - ram_block3a_8.port_b_address_clear = "none", - ram_block3a_8.port_b_address_clock = "clock1", - ram_block3a_8.port_b_address_width = 11, - ram_block3a_8.port_b_data_out_clear = "none", - ram_block3a_8.port_b_data_out_clock = "none", - ram_block3a_8.port_b_data_width = 1, - ram_block3a_8.port_b_first_address = 0, - ram_block3a_8.port_b_first_bit_number = 8, - ram_block3a_8.port_b_last_address = 2047, - ram_block3a_8.port_b_logical_ram_depth = 2048, - ram_block3a_8.port_b_logical_ram_width = 16, - ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_8.ram_block_type = "auto", - ram_block3a_8.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_9 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[9]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_9portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_9.connectivity_checking = "OFF", - ram_block3a_9.logical_ram_name = "ALTSYNCRAM", - ram_block3a_9.mixed_port_feed_through_mode = "dont_care", - ram_block3a_9.operation_mode = "dual_port", - ram_block3a_9.port_a_address_width = 11, - ram_block3a_9.port_a_data_width = 1, - ram_block3a_9.port_a_first_address = 0, - ram_block3a_9.port_a_first_bit_number = 9, - ram_block3a_9.port_a_last_address = 2047, - ram_block3a_9.port_a_logical_ram_depth = 2048, - ram_block3a_9.port_a_logical_ram_width = 16, - ram_block3a_9.port_b_address_clear = "none", - ram_block3a_9.port_b_address_clock = "clock1", - ram_block3a_9.port_b_address_width = 11, - ram_block3a_9.port_b_data_out_clear = "none", - ram_block3a_9.port_b_data_out_clock = "none", - ram_block3a_9.port_b_data_width = 1, - ram_block3a_9.port_b_first_address = 0, - ram_block3a_9.port_b_first_bit_number = 9, - ram_block3a_9.port_b_last_address = 2047, - ram_block3a_9.port_b_logical_ram_depth = 2048, - ram_block3a_9.port_b_logical_ram_width = 16, - ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_9.ram_block_type = "auto", - ram_block3a_9.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_10 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[10]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_10portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_10.connectivity_checking = "OFF", - ram_block3a_10.logical_ram_name = "ALTSYNCRAM", - ram_block3a_10.mixed_port_feed_through_mode = "dont_care", - ram_block3a_10.operation_mode = "dual_port", - ram_block3a_10.port_a_address_width = 11, - ram_block3a_10.port_a_data_width = 1, - ram_block3a_10.port_a_first_address = 0, - ram_block3a_10.port_a_first_bit_number = 10, - ram_block3a_10.port_a_last_address = 2047, - ram_block3a_10.port_a_logical_ram_depth = 2048, - ram_block3a_10.port_a_logical_ram_width = 16, - ram_block3a_10.port_b_address_clear = "none", - ram_block3a_10.port_b_address_clock = "clock1", - ram_block3a_10.port_b_address_width = 11, - ram_block3a_10.port_b_data_out_clear = "none", - ram_block3a_10.port_b_data_out_clock = "none", - ram_block3a_10.port_b_data_width = 1, - ram_block3a_10.port_b_first_address = 0, - ram_block3a_10.port_b_first_bit_number = 10, - ram_block3a_10.port_b_last_address = 2047, - ram_block3a_10.port_b_logical_ram_depth = 2048, - ram_block3a_10.port_b_logical_ram_width = 16, - ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_10.ram_block_type = "auto", - ram_block3a_10.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_11 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[11]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_11portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_11.connectivity_checking = "OFF", - ram_block3a_11.logical_ram_name = "ALTSYNCRAM", - ram_block3a_11.mixed_port_feed_through_mode = "dont_care", - ram_block3a_11.operation_mode = "dual_port", - ram_block3a_11.port_a_address_width = 11, - ram_block3a_11.port_a_data_width = 1, - ram_block3a_11.port_a_first_address = 0, - ram_block3a_11.port_a_first_bit_number = 11, - ram_block3a_11.port_a_last_address = 2047, - ram_block3a_11.port_a_logical_ram_depth = 2048, - ram_block3a_11.port_a_logical_ram_width = 16, - ram_block3a_11.port_b_address_clear = "none", - ram_block3a_11.port_b_address_clock = "clock1", - ram_block3a_11.port_b_address_width = 11, - ram_block3a_11.port_b_data_out_clear = "none", - ram_block3a_11.port_b_data_out_clock = "none", - ram_block3a_11.port_b_data_width = 1, - ram_block3a_11.port_b_first_address = 0, - ram_block3a_11.port_b_first_bit_number = 11, - ram_block3a_11.port_b_last_address = 2047, - ram_block3a_11.port_b_logical_ram_depth = 2048, - ram_block3a_11.port_b_logical_ram_width = 16, - ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_11.ram_block_type = "auto", - ram_block3a_11.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_12 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[12]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_12portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_12.connectivity_checking = "OFF", - ram_block3a_12.logical_ram_name = "ALTSYNCRAM", - ram_block3a_12.mixed_port_feed_through_mode = "dont_care", - ram_block3a_12.operation_mode = "dual_port", - ram_block3a_12.port_a_address_width = 11, - ram_block3a_12.port_a_data_width = 1, - ram_block3a_12.port_a_first_address = 0, - ram_block3a_12.port_a_first_bit_number = 12, - ram_block3a_12.port_a_last_address = 2047, - ram_block3a_12.port_a_logical_ram_depth = 2048, - ram_block3a_12.port_a_logical_ram_width = 16, - ram_block3a_12.port_b_address_clear = "none", - ram_block3a_12.port_b_address_clock = "clock1", - ram_block3a_12.port_b_address_width = 11, - ram_block3a_12.port_b_data_out_clear = "none", - ram_block3a_12.port_b_data_out_clock = "none", - ram_block3a_12.port_b_data_width = 1, - ram_block3a_12.port_b_first_address = 0, - ram_block3a_12.port_b_first_bit_number = 12, - ram_block3a_12.port_b_last_address = 2047, - ram_block3a_12.port_b_logical_ram_depth = 2048, - ram_block3a_12.port_b_logical_ram_width = 16, - ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_12.ram_block_type = "auto", - ram_block3a_12.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_13 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[13]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_13portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_13.connectivity_checking = "OFF", - ram_block3a_13.logical_ram_name = "ALTSYNCRAM", - ram_block3a_13.mixed_port_feed_through_mode = "dont_care", - ram_block3a_13.operation_mode = "dual_port", - ram_block3a_13.port_a_address_width = 11, - ram_block3a_13.port_a_data_width = 1, - ram_block3a_13.port_a_first_address = 0, - ram_block3a_13.port_a_first_bit_number = 13, - ram_block3a_13.port_a_last_address = 2047, - ram_block3a_13.port_a_logical_ram_depth = 2048, - ram_block3a_13.port_a_logical_ram_width = 16, - ram_block3a_13.port_b_address_clear = "none", - ram_block3a_13.port_b_address_clock = "clock1", - ram_block3a_13.port_b_address_width = 11, - ram_block3a_13.port_b_data_out_clear = "none", - ram_block3a_13.port_b_data_out_clock = "none", - ram_block3a_13.port_b_data_width = 1, - ram_block3a_13.port_b_first_address = 0, - ram_block3a_13.port_b_first_bit_number = 13, - ram_block3a_13.port_b_last_address = 2047, - ram_block3a_13.port_b_logical_ram_depth = 2048, - ram_block3a_13.port_b_logical_ram_width = 16, - ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_13.ram_block_type = "auto", - ram_block3a_13.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_14 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[14]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_14portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_14.connectivity_checking = "OFF", - ram_block3a_14.logical_ram_name = "ALTSYNCRAM", - ram_block3a_14.mixed_port_feed_through_mode = "dont_care", - ram_block3a_14.operation_mode = "dual_port", - ram_block3a_14.port_a_address_width = 11, - ram_block3a_14.port_a_data_width = 1, - ram_block3a_14.port_a_first_address = 0, - ram_block3a_14.port_a_first_bit_number = 14, - ram_block3a_14.port_a_last_address = 2047, - ram_block3a_14.port_a_logical_ram_depth = 2048, - ram_block3a_14.port_a_logical_ram_width = 16, - ram_block3a_14.port_b_address_clear = "none", - ram_block3a_14.port_b_address_clock = "clock1", - ram_block3a_14.port_b_address_width = 11, - ram_block3a_14.port_b_data_out_clear = "none", - ram_block3a_14.port_b_data_out_clock = "none", - ram_block3a_14.port_b_data_width = 1, - ram_block3a_14.port_b_first_address = 0, - ram_block3a_14.port_b_first_bit_number = 14, - ram_block3a_14.port_b_last_address = 2047, - ram_block3a_14.port_b_logical_ram_depth = 2048, - ram_block3a_14.port_b_logical_ram_width = 16, - ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_14.ram_block_type = "auto", - ram_block3a_14.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_15 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[10:0]}), - .portadatain({data_a[15]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[10:0]}), - .portbdataout(wire_ram_block3a_15portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_15.connectivity_checking = "OFF", - ram_block3a_15.logical_ram_name = "ALTSYNCRAM", - ram_block3a_15.mixed_port_feed_through_mode = "dont_care", - ram_block3a_15.operation_mode = "dual_port", - ram_block3a_15.port_a_address_width = 11, - ram_block3a_15.port_a_data_width = 1, - ram_block3a_15.port_a_first_address = 0, - ram_block3a_15.port_a_first_bit_number = 15, - ram_block3a_15.port_a_last_address = 2047, - ram_block3a_15.port_a_logical_ram_depth = 2048, - ram_block3a_15.port_a_logical_ram_width = 16, - ram_block3a_15.port_b_address_clear = "none", - ram_block3a_15.port_b_address_clock = "clock1", - ram_block3a_15.port_b_address_width = 11, - ram_block3a_15.port_b_data_out_clear = "none", - ram_block3a_15.port_b_data_out_clock = "none", - ram_block3a_15.port_b_data_width = 1, - ram_block3a_15.port_b_first_address = 0, - ram_block3a_15.port_b_first_bit_number = 15, - ram_block3a_15.port_b_last_address = 2047, - ram_block3a_15.port_b_logical_ram_depth = 2048, - ram_block3a_15.port_b_logical_ram_width = 16, - ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_15.ram_block_type = "auto", - ram_block3a_15.lpm_type = "cyclone_ram_block"; - assign - address_a_wire = address_a, - address_b_wire = address_b, - q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; -endmodule //fifo_2k_altsyncram_6pl - - -//dffpipe DELAY=1 WIDTH=11 clock clrn d q -//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - -//synthesis_resources = lut 11 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_dffpipe_ab3 - ( - clock, - clrn, - d, - q) /* synthesis synthesis_clearbox=1 */ - /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; - input clock; - input clrn; - input [10:0] d; - output [10:0] q; - - wire [10:0] wire_dffe4a_D; - reg [10:0] dffe4a; - wire ena; - wire prn; - wire sclr; - - // synopsys translate_off - initial - dffe4a[0:0] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[0:0] <= 1'b1; - else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; - else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; - // synopsys translate_off - initial - dffe4a[1:1] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[1:1] <= 1'b1; - else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; - else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; - // synopsys translate_off - initial - dffe4a[2:2] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[2:2] <= 1'b1; - else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; - else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; - // synopsys translate_off - initial - dffe4a[3:3] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[3:3] <= 1'b1; - else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; - else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; - // synopsys translate_off - initial - dffe4a[4:4] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[4:4] <= 1'b1; - else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; - else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; - // synopsys translate_off - initial - dffe4a[5:5] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[5:5] <= 1'b1; - else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; - else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; - // synopsys translate_off - initial - dffe4a[6:6] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[6:6] <= 1'b1; - else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; - else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; - // synopsys translate_off - initial - dffe4a[7:7] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[7:7] <= 1'b1; - else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; - else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; - // synopsys translate_off - initial - dffe4a[8:8] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[8:8] <= 1'b1; - else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; - else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; - // synopsys translate_off - initial - dffe4a[9:9] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[9:9] <= 1'b1; - else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; - else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; - // synopsys translate_off - initial - dffe4a[10:10] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[10:10] <= 1'b1; - else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; - else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; - assign - wire_dffe4a_D = (d & {11{(~ sclr)}}); - assign - ena = 1'b1, - prn = 1'b1, - q = dffe4a, - sclr = 1'b0; -endmodule //fifo_2k_dffpipe_ab3 - - -//dffpipe WIDTH=11 clock clrn d q -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - - -//dffpipe WIDTH=11 clock clrn d q -//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - -//synthesis_resources = lut 11 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_dffpipe_dm2 - ( - clock, - clrn, - d, - q) /* synthesis synthesis_clearbox=1 */ - /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; - input clock; - input clrn; - input [10:0] d; - output [10:0] q; - - wire [10:0] wire_dffe6a_D; - reg [10:0] dffe6a; - wire ena; - wire prn; - wire sclr; - - // synopsys translate_off - initial - dffe6a[0:0] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[0:0] <= 1'b1; - else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; - else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; - // synopsys translate_off - initial - dffe6a[1:1] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[1:1] <= 1'b1; - else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; - else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; - // synopsys translate_off - initial - dffe6a[2:2] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[2:2] <= 1'b1; - else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; - else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; - // synopsys translate_off - initial - dffe6a[3:3] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[3:3] <= 1'b1; - else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; - else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; - // synopsys translate_off - initial - dffe6a[4:4] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[4:4] <= 1'b1; - else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; - else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; - // synopsys translate_off - initial - dffe6a[5:5] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[5:5] <= 1'b1; - else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; - else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; - // synopsys translate_off - initial - dffe6a[6:6] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[6:6] <= 1'b1; - else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; - else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; - // synopsys translate_off - initial - dffe6a[7:7] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[7:7] <= 1'b1; - else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; - else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; - // synopsys translate_off - initial - dffe6a[8:8] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[8:8] <= 1'b1; - else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; - else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; - // synopsys translate_off - initial - dffe6a[9:9] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[9:9] <= 1'b1; - else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; - else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; - // synopsys translate_off - initial - dffe6a[10:10] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[10:10] <= 1'b1; - else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; - else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; - assign - wire_dffe6a_D = (d & {11{(~ sclr)}}); - assign - ena = 1'b1, - prn = 1'b1, - q = dffe6a, - sclr = 1'b0; -endmodule //fifo_2k_dffpipe_dm2 - -//synthesis_resources = lut 11 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_alt_synch_pipe_dm2 - ( - clock, - clrn, - d, - q) /* synthesis synthesis_clearbox=1 */ - /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; - input clock; - input clrn; - input [10:0] d; - output [10:0] q; - - wire [10:0] wire_dffpipe5_q; - - fifo_2k_dffpipe_dm2 dffpipe5 - ( - .clock(clock), - .clrn(clrn), - .d(d), - .q(wire_dffpipe5_q)); - assign - q = wire_dffpipe5_q; -endmodule //fifo_2k_alt_synch_pipe_dm2 - - -//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result -//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - -//synthesis_resources = lut 11 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_add_sub_a18 - ( - dataa, - datab, - result) /* synthesis synthesis_clearbox=1 */; - input [10:0] dataa; - input [10:0] datab; - output [10:0] result; - - wire [10:0] wire_add_sub_cella_combout; - wire [0:0] wire_add_sub_cella_0cout; - wire [0:0] wire_add_sub_cella_1cout; - wire [0:0] wire_add_sub_cella_2cout; - wire [0:0] wire_add_sub_cella_3cout; - wire [0:0] wire_add_sub_cella_4cout; - wire [0:0] wire_add_sub_cella_5cout; - wire [0:0] wire_add_sub_cella_6cout; - wire [0:0] wire_add_sub_cella_7cout; - wire [0:0] wire_add_sub_cella_8cout; - wire [0:0] wire_add_sub_cella_9cout; - wire [10:0] wire_add_sub_cella_dataa; - wire [10:0] wire_add_sub_cella_datab; - - cyclone_lcell add_sub_cella_0 - ( - .cin(1'b1), - .combout(wire_add_sub_cella_combout[0:0]), - .cout(wire_add_sub_cella_0cout[0:0]), - .dataa(wire_add_sub_cella_dataa[0:0]), - .datab(wire_add_sub_cella_datab[0:0]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_0.cin_used = "true", - add_sub_cella_0.lut_mask = "69b2", - add_sub_cella_0.operation_mode = "arithmetic", - add_sub_cella_0.sum_lutc_input = "cin", - add_sub_cella_0.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_1 - ( - .cin(wire_add_sub_cella_0cout[0:0]), - .combout(wire_add_sub_cella_combout[1:1]), - .cout(wire_add_sub_cella_1cout[0:0]), - .dataa(wire_add_sub_cella_dataa[1:1]), - .datab(wire_add_sub_cella_datab[1:1]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_1.cin_used = "true", - add_sub_cella_1.lut_mask = "69b2", - add_sub_cella_1.operation_mode = "arithmetic", - add_sub_cella_1.sum_lutc_input = "cin", - add_sub_cella_1.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_2 - ( - .cin(wire_add_sub_cella_1cout[0:0]), - .combout(wire_add_sub_cella_combout[2:2]), - .cout(wire_add_sub_cella_2cout[0:0]), - .dataa(wire_add_sub_cella_dataa[2:2]), - .datab(wire_add_sub_cella_datab[2:2]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_2.cin_used = "true", - add_sub_cella_2.lut_mask = "69b2", - add_sub_cella_2.operation_mode = "arithmetic", - add_sub_cella_2.sum_lutc_input = "cin", - add_sub_cella_2.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_3 - ( - .cin(wire_add_sub_cella_2cout[0:0]), - .combout(wire_add_sub_cella_combout[3:3]), - .cout(wire_add_sub_cella_3cout[0:0]), - .dataa(wire_add_sub_cella_dataa[3:3]), - .datab(wire_add_sub_cella_datab[3:3]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_3.cin_used = "true", - add_sub_cella_3.lut_mask = "69b2", - add_sub_cella_3.operation_mode = "arithmetic", - add_sub_cella_3.sum_lutc_input = "cin", - add_sub_cella_3.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_4 - ( - .cin(wire_add_sub_cella_3cout[0:0]), - .combout(wire_add_sub_cella_combout[4:4]), - .cout(wire_add_sub_cella_4cout[0:0]), - .dataa(wire_add_sub_cella_dataa[4:4]), - .datab(wire_add_sub_cella_datab[4:4]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_4.cin_used = "true", - add_sub_cella_4.lut_mask = "69b2", - add_sub_cella_4.operation_mode = "arithmetic", - add_sub_cella_4.sum_lutc_input = "cin", - add_sub_cella_4.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_5 - ( - .cin(wire_add_sub_cella_4cout[0:0]), - .combout(wire_add_sub_cella_combout[5:5]), - .cout(wire_add_sub_cella_5cout[0:0]), - .dataa(wire_add_sub_cella_dataa[5:5]), - .datab(wire_add_sub_cella_datab[5:5]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_5.cin_used = "true", - add_sub_cella_5.lut_mask = "69b2", - add_sub_cella_5.operation_mode = "arithmetic", - add_sub_cella_5.sum_lutc_input = "cin", - add_sub_cella_5.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_6 - ( - .cin(wire_add_sub_cella_5cout[0:0]), - .combout(wire_add_sub_cella_combout[6:6]), - .cout(wire_add_sub_cella_6cout[0:0]), - .dataa(wire_add_sub_cella_dataa[6:6]), - .datab(wire_add_sub_cella_datab[6:6]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_6.cin_used = "true", - add_sub_cella_6.lut_mask = "69b2", - add_sub_cella_6.operation_mode = "arithmetic", - add_sub_cella_6.sum_lutc_input = "cin", - add_sub_cella_6.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_7 - ( - .cin(wire_add_sub_cella_6cout[0:0]), - .combout(wire_add_sub_cella_combout[7:7]), - .cout(wire_add_sub_cella_7cout[0:0]), - .dataa(wire_add_sub_cella_dataa[7:7]), - .datab(wire_add_sub_cella_datab[7:7]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_7.cin_used = "true", - add_sub_cella_7.lut_mask = "69b2", - add_sub_cella_7.operation_mode = "arithmetic", - add_sub_cella_7.sum_lutc_input = "cin", - add_sub_cella_7.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_8 - ( - .cin(wire_add_sub_cella_7cout[0:0]), - .combout(wire_add_sub_cella_combout[8:8]), - .cout(wire_add_sub_cella_8cout[0:0]), - .dataa(wire_add_sub_cella_dataa[8:8]), - .datab(wire_add_sub_cella_datab[8:8]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_8.cin_used = "true", - add_sub_cella_8.lut_mask = "69b2", - add_sub_cella_8.operation_mode = "arithmetic", - add_sub_cella_8.sum_lutc_input = "cin", - add_sub_cella_8.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_9 - ( - .cin(wire_add_sub_cella_8cout[0:0]), - .combout(wire_add_sub_cella_combout[9:9]), - .cout(wire_add_sub_cella_9cout[0:0]), - .dataa(wire_add_sub_cella_dataa[9:9]), - .datab(wire_add_sub_cella_datab[9:9]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_9.cin_used = "true", - add_sub_cella_9.lut_mask = "69b2", - add_sub_cella_9.operation_mode = "arithmetic", - add_sub_cella_9.sum_lutc_input = "cin", - add_sub_cella_9.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_10 - ( - .cin(wire_add_sub_cella_9cout[0:0]), - .combout(wire_add_sub_cella_combout[10:10]), - .cout(), - .dataa(wire_add_sub_cella_dataa[10:10]), - .datab(wire_add_sub_cella_datab[10:10]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_10.cin_used = "true", - add_sub_cella_10.lut_mask = "6969", - add_sub_cella_10.operation_mode = "normal", - add_sub_cella_10.sum_lutc_input = "cin", - add_sub_cella_10.lpm_type = "cyclone_lcell"; - assign - wire_add_sub_cella_dataa = dataa, - wire_add_sub_cella_datab = datab; - assign - result = wire_add_sub_cella_combout; -endmodule //fifo_2k_add_sub_a18 - - -//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab -//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - - -//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab -//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - -//synthesis_resources = lut 97 M4K 8 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_2k_dcfifo_0cq - ( - aclr, - data, - q, - rdclk, - rdempty, - rdreq, - rdusedw, - wrclk, - wrfull, - wrreq, - wrusedw) /* synthesis synthesis_clearbox=1 */ - /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; - input aclr; - input [15:0] data; - output [15:0] q; - input rdclk; - output rdempty; - input rdreq; - output [10:0] rdusedw; - input wrclk; - output wrfull; - input wrreq; - output [10:0] wrusedw; - - wire [10:0] wire_rdptr_g_gray2bin_bin; - wire [10:0] wire_rs_dgwp_gray2bin_bin; - wire [10:0] wire_wrptr_g_gray2bin_bin; - wire [10:0] wire_ws_dgrp_gray2bin_bin; - wire [10:0] wire_rdptr_g_q; - wire [10:0] wire_rdptr_g1p_q; - wire [10:0] wire_wrptr_g1p_q; - wire [15:0] wire_fifo_ram_q_b; - reg [10:0] delayed_wrptr_g; - reg [10:0] wrptr_g; - wire [10:0] wire_rs_brp_q; - wire [10:0] wire_rs_bwp_q; - wire [10:0] wire_rs_dgwp_q; - wire [10:0] wire_ws_brp_q; - wire [10:0] wire_ws_bwp_q; - wire [10:0] wire_ws_dgrp_q; - wire [10:0] wire_rdusedw_sub_result; - wire [10:0] wire_wrusedw_sub_result; - reg wire_rdempty_eq_comp_aeb_int; - wire wire_rdempty_eq_comp_aeb; - wire [10:0] wire_rdempty_eq_comp_dataa; - wire [10:0] wire_rdempty_eq_comp_datab; - reg wire_wrfull_eq_comp_aeb_int; - wire wire_wrfull_eq_comp_aeb; - wire [10:0] wire_wrfull_eq_comp_dataa; - wire [10:0] wire_wrfull_eq_comp_datab; - wire int_rdempty; - wire int_wrfull; - wire valid_rdreq; - wire valid_wrreq; - - fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin - ( - .bin(wire_rdptr_g_gray2bin_bin), - .gray(wire_rdptr_g_q)); - fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin - ( - .bin(wire_rs_dgwp_gray2bin_bin), - .gray(wire_rs_dgwp_q)); - fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin - ( - .bin(wire_wrptr_g_gray2bin_bin), - .gray(wrptr_g)); - fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin - ( - .bin(wire_ws_dgrp_gray2bin_bin), - .gray(wire_ws_dgrp_q)); - fifo_2k_a_graycounter_726 rdptr_g - ( - .aclr(aclr), - .clock(rdclk), - .cnt_en(valid_rdreq), - .q(wire_rdptr_g_q)); - fifo_2k_a_graycounter_2r6 rdptr_g1p - ( - .aclr(aclr), - .clock(rdclk), - .cnt_en(valid_rdreq), - .q(wire_rdptr_g1p_q)); - fifo_2k_a_graycounter_2r6 wrptr_g1p - ( - .aclr(aclr), - .clock(wrclk), - .cnt_en(valid_wrreq), - .q(wire_wrptr_g1p_q)); - fifo_2k_altsyncram_6pl fifo_ram - ( - .address_a(wrptr_g), - .address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))), - .clock0(wrclk), - .clock1(rdclk), - .clocken1((valid_rdreq | int_rdempty)), - .data_a(data), - .q_b(wire_fifo_ram_q_b), - .wren_a(valid_wrreq)); - // synopsys translate_off - initial - delayed_wrptr_g = 0; - // synopsys translate_on - always @ ( posedge wrclk or posedge aclr) - if (aclr == 1'b1) delayed_wrptr_g <= 11'b0; - else delayed_wrptr_g <= wrptr_g; - // synopsys translate_off - initial - wrptr_g = 0; - // synopsys translate_on - always @ ( posedge wrclk or posedge aclr) - if (aclr == 1'b1) wrptr_g <= 11'b0; - else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; - fifo_2k_dffpipe_ab3 rs_brp - ( - .clock(rdclk), - .clrn((~ aclr)), - .d(wire_rdptr_g_gray2bin_bin), - .q(wire_rs_brp_q)); - fifo_2k_dffpipe_ab3 rs_bwp - ( - .clock(rdclk), - .clrn((~ aclr)), - .d(wire_rs_dgwp_gray2bin_bin), - .q(wire_rs_bwp_q)); - fifo_2k_alt_synch_pipe_dm2 rs_dgwp - ( - .clock(rdclk), - .clrn((~ aclr)), - .d(delayed_wrptr_g), - .q(wire_rs_dgwp_q)); - fifo_2k_dffpipe_ab3 ws_brp - ( - .clock(wrclk), - .clrn((~ aclr)), - .d(wire_ws_dgrp_gray2bin_bin), - .q(wire_ws_brp_q)); - fifo_2k_dffpipe_ab3 ws_bwp - ( - .clock(wrclk), - .clrn((~ aclr)), - .d(wire_wrptr_g_gray2bin_bin), - .q(wire_ws_bwp_q)); - fifo_2k_alt_synch_pipe_dm2 ws_dgrp - ( - .clock(wrclk), - .clrn((~ aclr)), - .d(wire_rdptr_g_q), - .q(wire_ws_dgrp_q)); - fifo_2k_add_sub_a18 rdusedw_sub - ( - .dataa(wire_rs_bwp_q), - .datab(wire_rs_brp_q), - .result(wire_rdusedw_sub_result)); - fifo_2k_add_sub_a18 wrusedw_sub - ( - .dataa(wire_ws_bwp_q), - .datab(wire_ws_brp_q), - .result(wire_wrusedw_sub_result)); - always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) - if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) - begin - wire_rdempty_eq_comp_aeb_int = 1'b1; - end - else - begin - wire_rdempty_eq_comp_aeb_int = 1'b0; - end - assign - wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; - assign - wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, - wire_rdempty_eq_comp_datab = wire_rdptr_g_q; - always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) - if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) - begin - wire_wrfull_eq_comp_aeb_int = 1'b1; - end - else - begin - wire_wrfull_eq_comp_aeb_int = 1'b0; - end - assign - wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; - assign - wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, - wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; - assign - int_rdempty = wire_rdempty_eq_comp_aeb, - int_wrfull = wire_wrfull_eq_comp_aeb, - q = wire_fifo_ram_q_b, - rdempty = int_rdempty, - rdusedw = wire_rdusedw_sub_result, - valid_rdreq = rdreq, - valid_wrreq = wrreq, - wrfull = int_wrfull, - wrusedw = wire_wrusedw_sub_result; -endmodule //fifo_2k_dcfifo_0cq -//VALID FILE - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_2k ( - data, - wrreq, - rdreq, - rdclk, - wrclk, - aclr, - q, - rdempty, - rdusedw, - wrfull, - wrusedw)/* synthesis synthesis_clearbox = 1 */; - - input [15:0] data; - input wrreq; - input rdreq; - input rdclk; - input wrclk; - input aclr; - output [15:0] q; - output rdempty; - output [10:0] rdusedw; - output wrfull; - output [10:0] wrusedw; - - wire sub_wire0; - wire [10:0] sub_wire1; - wire sub_wire2; - wire [15:0] sub_wire3; - wire [10:0] sub_wire4; - wire rdempty = sub_wire0; - wire [10:0] wrusedw = sub_wire1[10:0]; - wire wrfull = sub_wire2; - wire [15:0] q = sub_wire3[15:0]; - wire [10:0] rdusedw = sub_wire4[10:0]; - - fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component ( - .wrclk (wrclk), - .rdreq (rdreq), - .aclr (aclr), - .rdclk (rdclk), - .wrreq (wrreq), - .data (data), - .rdempty (sub_wire0), - .wrusedw (sub_wire1), - .wrfull (sub_wire2), - .q (sub_wire3), - .rdusedw (sub_wire4)); - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: Depth NUMERIC "2048" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0] -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0] -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE diff --git a/megacells/fifo_2k_bb.v b/megacells/fifo_2k_bb.v deleted file mode 100644 index 3fcc2a496..000000000 --- a/megacells/fifo_2k_bb.v +++ /dev/null @@ -1,131 +0,0 @@ -// megafunction wizard: %FIFO%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_2k.v -// Megafunction Name(s): -// dcfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2005 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_2k ( - data, - wrreq, - rdreq, - rdclk, - wrclk, - aclr, - q, - rdempty, - rdusedw, - wrfull, - wrusedw)/* synthesis synthesis_clearbox = 1 */; - - input [15:0] data; - input wrreq; - input rdreq; - input rdclk; - input wrclk; - input aclr; - output [15:0] q; - output rdempty; - output [10:0] rdusedw; - output wrfull; - output [10:0] wrusedw; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: Depth NUMERIC "2048" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0] -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0] -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE diff --git a/megacells/fifo_4k.v b/megacells/fifo_4k.v deleted file mode 100644 index a5ab46677..000000000 --- a/megacells/fifo_4k.v +++ /dev/null @@ -1,3495 +0,0 @@ -// megafunction wizard: %FIFO%CBX% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_4k.v -// Megafunction Name(s): -// dcfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2005 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - - -//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END - -//synthesis_resources = -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_a_gray2bin_9m4 - ( - bin, - gray) /* synthesis synthesis_clearbox=1 */; - output [11:0] bin; - input [11:0] gray; - - wire xor0; - wire xor1; - wire xor10; - wire xor2; - wire xor3; - wire xor4; - wire xor5; - wire xor6; - wire xor7; - wire xor8; - wire xor9; - - assign - bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, - xor0 = (gray[0] ^ xor1), - xor1 = (gray[1] ^ xor2), - xor10 = (gray[11] ^ gray[10]), - xor2 = (gray[2] ^ xor3), - xor3 = (gray[3] ^ xor4), - xor4 = (gray[4] ^ xor5), - xor5 = (gray[5] ^ xor6), - xor6 = (gray[6] ^ xor7), - xor7 = (gray[7] ^ xor8), - xor8 = (gray[8] ^ xor9), - xor9 = (gray[9] ^ xor10); -endmodule //fifo_4k_a_gray2bin_9m4 - - -//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - -//synthesis_resources = lut 13 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_a_graycounter_826 - ( - aclr, - clock, - cnt_en, - q) /* synthesis synthesis_clearbox=1 */; - input aclr; - input clock; - input cnt_en; - output [11:0] q; - - wire [0:0] wire_countera_0cout; - wire [0:0] wire_countera_1cout; - wire [0:0] wire_countera_2cout; - wire [0:0] wire_countera_3cout; - wire [0:0] wire_countera_4cout; - wire [0:0] wire_countera_5cout; - wire [0:0] wire_countera_6cout; - wire [0:0] wire_countera_7cout; - wire [0:0] wire_countera_8cout; - wire [0:0] wire_countera_9cout; - wire [0:0] wire_countera_10cout; - wire [11:0] wire_countera_regout; - wire wire_parity_cout; - wire wire_parity_regout; - wire [11:0] power_modified_counter_values; - wire sclr; - wire updown; - - cyclone_lcell countera_0 - ( - .aclr(aclr), - .cin(wire_parity_cout), - .clk(clock), - .combout(), - .cout(wire_countera_0cout[0:0]), - .dataa(cnt_en), - .datab(wire_countera_regout[0:0]), - .ena(1'b1), - .regout(wire_countera_regout[0:0]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_0.cin_used = "true", - countera_0.lut_mask = "c6a0", - countera_0.operation_mode = "arithmetic", - countera_0.sum_lutc_input = "cin", - countera_0.synch_mode = "on", - countera_0.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_1 - ( - .aclr(aclr), - .cin(wire_countera_0cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_1cout[0:0]), - .dataa(power_modified_counter_values[0]), - .datab(power_modified_counter_values[1]), - .ena(1'b1), - .regout(wire_countera_regout[1:1]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_1.cin_used = "true", - countera_1.lut_mask = "6c50", - countera_1.operation_mode = "arithmetic", - countera_1.sum_lutc_input = "cin", - countera_1.synch_mode = "on", - countera_1.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_2 - ( - .aclr(aclr), - .cin(wire_countera_1cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_2cout[0:0]), - .dataa(power_modified_counter_values[1]), - .datab(power_modified_counter_values[2]), - .ena(1'b1), - .regout(wire_countera_regout[2:2]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_2.cin_used = "true", - countera_2.lut_mask = "6c50", - countera_2.operation_mode = "arithmetic", - countera_2.sum_lutc_input = "cin", - countera_2.synch_mode = "on", - countera_2.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_3 - ( - .aclr(aclr), - .cin(wire_countera_2cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_3cout[0:0]), - .dataa(power_modified_counter_values[2]), - .datab(power_modified_counter_values[3]), - .ena(1'b1), - .regout(wire_countera_regout[3:3]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_3.cin_used = "true", - countera_3.lut_mask = "6c50", - countera_3.operation_mode = "arithmetic", - countera_3.sum_lutc_input = "cin", - countera_3.synch_mode = "on", - countera_3.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_4 - ( - .aclr(aclr), - .cin(wire_countera_3cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_4cout[0:0]), - .dataa(power_modified_counter_values[3]), - .datab(power_modified_counter_values[4]), - .ena(1'b1), - .regout(wire_countera_regout[4:4]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_4.cin_used = "true", - countera_4.lut_mask = "6c50", - countera_4.operation_mode = "arithmetic", - countera_4.sum_lutc_input = "cin", - countera_4.synch_mode = "on", - countera_4.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_5 - ( - .aclr(aclr), - .cin(wire_countera_4cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_5cout[0:0]), - .dataa(power_modified_counter_values[4]), - .datab(power_modified_counter_values[5]), - .ena(1'b1), - .regout(wire_countera_regout[5:5]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_5.cin_used = "true", - countera_5.lut_mask = "6c50", - countera_5.operation_mode = "arithmetic", - countera_5.sum_lutc_input = "cin", - countera_5.synch_mode = "on", - countera_5.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_6 - ( - .aclr(aclr), - .cin(wire_countera_5cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_6cout[0:0]), - .dataa(power_modified_counter_values[5]), - .datab(power_modified_counter_values[6]), - .ena(1'b1), - .regout(wire_countera_regout[6:6]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_6.cin_used = "true", - countera_6.lut_mask = "6c50", - countera_6.operation_mode = "arithmetic", - countera_6.sum_lutc_input = "cin", - countera_6.synch_mode = "on", - countera_6.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_7 - ( - .aclr(aclr), - .cin(wire_countera_6cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_7cout[0:0]), - .dataa(power_modified_counter_values[6]), - .datab(power_modified_counter_values[7]), - .ena(1'b1), - .regout(wire_countera_regout[7:7]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_7.cin_used = "true", - countera_7.lut_mask = "6c50", - countera_7.operation_mode = "arithmetic", - countera_7.sum_lutc_input = "cin", - countera_7.synch_mode = "on", - countera_7.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_8 - ( - .aclr(aclr), - .cin(wire_countera_7cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_8cout[0:0]), - .dataa(power_modified_counter_values[7]), - .datab(power_modified_counter_values[8]), - .ena(1'b1), - .regout(wire_countera_regout[8:8]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_8.cin_used = "true", - countera_8.lut_mask = "6c50", - countera_8.operation_mode = "arithmetic", - countera_8.sum_lutc_input = "cin", - countera_8.synch_mode = "on", - countera_8.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_9 - ( - .aclr(aclr), - .cin(wire_countera_8cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_9cout[0:0]), - .dataa(power_modified_counter_values[8]), - .datab(power_modified_counter_values[9]), - .ena(1'b1), - .regout(wire_countera_regout[9:9]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_9.cin_used = "true", - countera_9.lut_mask = "6c50", - countera_9.operation_mode = "arithmetic", - countera_9.sum_lutc_input = "cin", - countera_9.synch_mode = "on", - countera_9.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_10 - ( - .aclr(aclr), - .cin(wire_countera_9cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_10cout[0:0]), - .dataa(power_modified_counter_values[9]), - .datab(power_modified_counter_values[10]), - .ena(1'b1), - .regout(wire_countera_regout[10:10]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_10.cin_used = "true", - countera_10.lut_mask = "6c50", - countera_10.operation_mode = "arithmetic", - countera_10.sum_lutc_input = "cin", - countera_10.synch_mode = "on", - countera_10.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_11 - ( - .aclr(aclr), - .cin(wire_countera_10cout[0:0]), - .clk(clock), - .combout(), - .cout(), - .dataa(power_modified_counter_values[11]), - .ena(1'b1), - .regout(wire_countera_regout[11:11]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datab(1'b1), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_11.cin_used = "true", - countera_11.lut_mask = "5a5a", - countera_11.operation_mode = "normal", - countera_11.sum_lutc_input = "cin", - countera_11.synch_mode = "on", - countera_11.lpm_type = "cyclone_lcell"; - cyclone_lcell parity - ( - .aclr(aclr), - .cin(updown), - .clk(clock), - .combout(), - .cout(wire_parity_cout), - .dataa(cnt_en), - .datab(wire_parity_regout), - .ena(1'b1), - .regout(wire_parity_regout), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - parity.cin_used = "true", - parity.lut_mask = "6682", - parity.operation_mode = "arithmetic", - parity.synch_mode = "on", - parity.lpm_type = "cyclone_lcell"; - assign - power_modified_counter_values = {wire_countera_regout[11:0]}, - q = power_modified_counter_values, - sclr = 1'b0, - updown = 1'b1; -endmodule //fifo_4k_a_graycounter_826 - - -//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - -//synthesis_resources = lut 13 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_a_graycounter_3r6 - ( - aclr, - clock, - cnt_en, - q) /* synthesis synthesis_clearbox=1 */; - input aclr; - input clock; - input cnt_en; - output [11:0] q; - - wire [0:0] wire_countera_0cout; - wire [0:0] wire_countera_1cout; - wire [0:0] wire_countera_2cout; - wire [0:0] wire_countera_3cout; - wire [0:0] wire_countera_4cout; - wire [0:0] wire_countera_5cout; - wire [0:0] wire_countera_6cout; - wire [0:0] wire_countera_7cout; - wire [0:0] wire_countera_8cout; - wire [0:0] wire_countera_9cout; - wire [0:0] wire_countera_10cout; - wire [11:0] wire_countera_regout; - wire wire_parity_cout; - wire wire_parity_regout; - wire [11:0] power_modified_counter_values; - wire sclr; - wire updown; - - cyclone_lcell countera_0 - ( - .aclr(aclr), - .cin(wire_parity_cout), - .clk(clock), - .combout(), - .cout(wire_countera_0cout[0:0]), - .dataa(cnt_en), - .datab(wire_countera_regout[0:0]), - .ena(1'b1), - .regout(wire_countera_regout[0:0]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_0.cin_used = "true", - countera_0.lut_mask = "c6a0", - countera_0.operation_mode = "arithmetic", - countera_0.sum_lutc_input = "cin", - countera_0.synch_mode = "on", - countera_0.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_1 - ( - .aclr(aclr), - .cin(wire_countera_0cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_1cout[0:0]), - .dataa(power_modified_counter_values[0]), - .datab(power_modified_counter_values[1]), - .ena(1'b1), - .regout(wire_countera_regout[1:1]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_1.cin_used = "true", - countera_1.lut_mask = "6c50", - countera_1.operation_mode = "arithmetic", - countera_1.sum_lutc_input = "cin", - countera_1.synch_mode = "on", - countera_1.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_2 - ( - .aclr(aclr), - .cin(wire_countera_1cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_2cout[0:0]), - .dataa(power_modified_counter_values[1]), - .datab(power_modified_counter_values[2]), - .ena(1'b1), - .regout(wire_countera_regout[2:2]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_2.cin_used = "true", - countera_2.lut_mask = "6c50", - countera_2.operation_mode = "arithmetic", - countera_2.sum_lutc_input = "cin", - countera_2.synch_mode = "on", - countera_2.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_3 - ( - .aclr(aclr), - .cin(wire_countera_2cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_3cout[0:0]), - .dataa(power_modified_counter_values[2]), - .datab(power_modified_counter_values[3]), - .ena(1'b1), - .regout(wire_countera_regout[3:3]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_3.cin_used = "true", - countera_3.lut_mask = "6c50", - countera_3.operation_mode = "arithmetic", - countera_3.sum_lutc_input = "cin", - countera_3.synch_mode = "on", - countera_3.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_4 - ( - .aclr(aclr), - .cin(wire_countera_3cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_4cout[0:0]), - .dataa(power_modified_counter_values[3]), - .datab(power_modified_counter_values[4]), - .ena(1'b1), - .regout(wire_countera_regout[4:4]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_4.cin_used = "true", - countera_4.lut_mask = "6c50", - countera_4.operation_mode = "arithmetic", - countera_4.sum_lutc_input = "cin", - countera_4.synch_mode = "on", - countera_4.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_5 - ( - .aclr(aclr), - .cin(wire_countera_4cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_5cout[0:0]), - .dataa(power_modified_counter_values[4]), - .datab(power_modified_counter_values[5]), - .ena(1'b1), - .regout(wire_countera_regout[5:5]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_5.cin_used = "true", - countera_5.lut_mask = "6c50", - countera_5.operation_mode = "arithmetic", - countera_5.sum_lutc_input = "cin", - countera_5.synch_mode = "on", - countera_5.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_6 - ( - .aclr(aclr), - .cin(wire_countera_5cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_6cout[0:0]), - .dataa(power_modified_counter_values[5]), - .datab(power_modified_counter_values[6]), - .ena(1'b1), - .regout(wire_countera_regout[6:6]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_6.cin_used = "true", - countera_6.lut_mask = "6c50", - countera_6.operation_mode = "arithmetic", - countera_6.sum_lutc_input = "cin", - countera_6.synch_mode = "on", - countera_6.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_7 - ( - .aclr(aclr), - .cin(wire_countera_6cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_7cout[0:0]), - .dataa(power_modified_counter_values[6]), - .datab(power_modified_counter_values[7]), - .ena(1'b1), - .regout(wire_countera_regout[7:7]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_7.cin_used = "true", - countera_7.lut_mask = "6c50", - countera_7.operation_mode = "arithmetic", - countera_7.sum_lutc_input = "cin", - countera_7.synch_mode = "on", - countera_7.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_8 - ( - .aclr(aclr), - .cin(wire_countera_7cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_8cout[0:0]), - .dataa(power_modified_counter_values[7]), - .datab(power_modified_counter_values[8]), - .ena(1'b1), - .regout(wire_countera_regout[8:8]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_8.cin_used = "true", - countera_8.lut_mask = "6c50", - countera_8.operation_mode = "arithmetic", - countera_8.sum_lutc_input = "cin", - countera_8.synch_mode = "on", - countera_8.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_9 - ( - .aclr(aclr), - .cin(wire_countera_8cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_9cout[0:0]), - .dataa(power_modified_counter_values[8]), - .datab(power_modified_counter_values[9]), - .ena(1'b1), - .regout(wire_countera_regout[9:9]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_9.cin_used = "true", - countera_9.lut_mask = "6c50", - countera_9.operation_mode = "arithmetic", - countera_9.sum_lutc_input = "cin", - countera_9.synch_mode = "on", - countera_9.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_10 - ( - .aclr(aclr), - .cin(wire_countera_9cout[0:0]), - .clk(clock), - .combout(), - .cout(wire_countera_10cout[0:0]), - .dataa(power_modified_counter_values[9]), - .datab(power_modified_counter_values[10]), - .ena(1'b1), - .regout(wire_countera_regout[10:10]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_10.cin_used = "true", - countera_10.lut_mask = "6c50", - countera_10.operation_mode = "arithmetic", - countera_10.sum_lutc_input = "cin", - countera_10.synch_mode = "on", - countera_10.lpm_type = "cyclone_lcell"; - cyclone_lcell countera_11 - ( - .aclr(aclr), - .cin(wire_countera_10cout[0:0]), - .clk(clock), - .combout(), - .cout(), - .dataa(power_modified_counter_values[11]), - .ena(1'b1), - .regout(wire_countera_regout[11:11]), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datab(1'b1), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - countera_11.cin_used = "true", - countera_11.lut_mask = "5a5a", - countera_11.operation_mode = "normal", - countera_11.sum_lutc_input = "cin", - countera_11.synch_mode = "on", - countera_11.lpm_type = "cyclone_lcell"; - cyclone_lcell parity - ( - .aclr(aclr), - .cin(updown), - .clk(clock), - .combout(), - .cout(wire_parity_cout), - .dataa(cnt_en), - .datab((~ wire_parity_regout)), - .ena(1'b1), - .regout(wire_parity_regout), - .sclr(sclr) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aload(1'b0), - .datac(1'b1), - .datad(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - parity.cin_used = "true", - parity.lut_mask = "9982", - parity.operation_mode = "arithmetic", - parity.synch_mode = "on", - parity.lpm_type = "cyclone_lcell"; - assign - power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])}, - q = power_modified_counter_values, - sclr = 1'b0, - updown = 1'b1; -endmodule //fifo_4k_a_graycounter_3r6 - - -//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a -//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - -//synthesis_resources = M4K 16 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_altsyncram_8pl - ( - address_a, - address_b, - clock0, - clock1, - clocken1, - data_a, - q_b, - wren_a) /* synthesis synthesis_clearbox=1 */; - input [11:0] address_a; - input [11:0] address_b; - input clock0; - input clock1; - input clocken1; - input [15:0] data_a; - output [15:0] q_b; - input wren_a; - - wire [0:0] wire_ram_block3a_0portbdataout; - wire [0:0] wire_ram_block3a_1portbdataout; - wire [0:0] wire_ram_block3a_2portbdataout; - wire [0:0] wire_ram_block3a_3portbdataout; - wire [0:0] wire_ram_block3a_4portbdataout; - wire [0:0] wire_ram_block3a_5portbdataout; - wire [0:0] wire_ram_block3a_6portbdataout; - wire [0:0] wire_ram_block3a_7portbdataout; - wire [0:0] wire_ram_block3a_8portbdataout; - wire [0:0] wire_ram_block3a_9portbdataout; - wire [0:0] wire_ram_block3a_10portbdataout; - wire [0:0] wire_ram_block3a_11portbdataout; - wire [0:0] wire_ram_block3a_12portbdataout; - wire [0:0] wire_ram_block3a_13portbdataout; - wire [0:0] wire_ram_block3a_14portbdataout; - wire [0:0] wire_ram_block3a_15portbdataout; - wire [11:0] address_a_wire; - wire [11:0] address_b_wire; - - cyclone_ram_block ram_block3a_0 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[0]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_0portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_0.connectivity_checking = "OFF", - ram_block3a_0.logical_ram_name = "ALTSYNCRAM", - ram_block3a_0.mixed_port_feed_through_mode = "dont_care", - ram_block3a_0.operation_mode = "dual_port", - ram_block3a_0.port_a_address_width = 12, - ram_block3a_0.port_a_data_width = 1, - ram_block3a_0.port_a_first_address = 0, - ram_block3a_0.port_a_first_bit_number = 0, - ram_block3a_0.port_a_last_address = 4095, - ram_block3a_0.port_a_logical_ram_depth = 4096, - ram_block3a_0.port_a_logical_ram_width = 16, - ram_block3a_0.port_b_address_clear = "none", - ram_block3a_0.port_b_address_clock = "clock1", - ram_block3a_0.port_b_address_width = 12, - ram_block3a_0.port_b_data_out_clear = "none", - ram_block3a_0.port_b_data_out_clock = "none", - ram_block3a_0.port_b_data_width = 1, - ram_block3a_0.port_b_first_address = 0, - ram_block3a_0.port_b_first_bit_number = 0, - ram_block3a_0.port_b_last_address = 4095, - ram_block3a_0.port_b_logical_ram_depth = 4096, - ram_block3a_0.port_b_logical_ram_width = 16, - ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_0.ram_block_type = "auto", - ram_block3a_0.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_1 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[1]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_1portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_1.connectivity_checking = "OFF", - ram_block3a_1.logical_ram_name = "ALTSYNCRAM", - ram_block3a_1.mixed_port_feed_through_mode = "dont_care", - ram_block3a_1.operation_mode = "dual_port", - ram_block3a_1.port_a_address_width = 12, - ram_block3a_1.port_a_data_width = 1, - ram_block3a_1.port_a_first_address = 0, - ram_block3a_1.port_a_first_bit_number = 1, - ram_block3a_1.port_a_last_address = 4095, - ram_block3a_1.port_a_logical_ram_depth = 4096, - ram_block3a_1.port_a_logical_ram_width = 16, - ram_block3a_1.port_b_address_clear = "none", - ram_block3a_1.port_b_address_clock = "clock1", - ram_block3a_1.port_b_address_width = 12, - ram_block3a_1.port_b_data_out_clear = "none", - ram_block3a_1.port_b_data_out_clock = "none", - ram_block3a_1.port_b_data_width = 1, - ram_block3a_1.port_b_first_address = 0, - ram_block3a_1.port_b_first_bit_number = 1, - ram_block3a_1.port_b_last_address = 4095, - ram_block3a_1.port_b_logical_ram_depth = 4096, - ram_block3a_1.port_b_logical_ram_width = 16, - ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_1.ram_block_type = "auto", - ram_block3a_1.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_2 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[2]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_2portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_2.connectivity_checking = "OFF", - ram_block3a_2.logical_ram_name = "ALTSYNCRAM", - ram_block3a_2.mixed_port_feed_through_mode = "dont_care", - ram_block3a_2.operation_mode = "dual_port", - ram_block3a_2.port_a_address_width = 12, - ram_block3a_2.port_a_data_width = 1, - ram_block3a_2.port_a_first_address = 0, - ram_block3a_2.port_a_first_bit_number = 2, - ram_block3a_2.port_a_last_address = 4095, - ram_block3a_2.port_a_logical_ram_depth = 4096, - ram_block3a_2.port_a_logical_ram_width = 16, - ram_block3a_2.port_b_address_clear = "none", - ram_block3a_2.port_b_address_clock = "clock1", - ram_block3a_2.port_b_address_width = 12, - ram_block3a_2.port_b_data_out_clear = "none", - ram_block3a_2.port_b_data_out_clock = "none", - ram_block3a_2.port_b_data_width = 1, - ram_block3a_2.port_b_first_address = 0, - ram_block3a_2.port_b_first_bit_number = 2, - ram_block3a_2.port_b_last_address = 4095, - ram_block3a_2.port_b_logical_ram_depth = 4096, - ram_block3a_2.port_b_logical_ram_width = 16, - ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_2.ram_block_type = "auto", - ram_block3a_2.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_3 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[3]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_3portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_3.connectivity_checking = "OFF", - ram_block3a_3.logical_ram_name = "ALTSYNCRAM", - ram_block3a_3.mixed_port_feed_through_mode = "dont_care", - ram_block3a_3.operation_mode = "dual_port", - ram_block3a_3.port_a_address_width = 12, - ram_block3a_3.port_a_data_width = 1, - ram_block3a_3.port_a_first_address = 0, - ram_block3a_3.port_a_first_bit_number = 3, - ram_block3a_3.port_a_last_address = 4095, - ram_block3a_3.port_a_logical_ram_depth = 4096, - ram_block3a_3.port_a_logical_ram_width = 16, - ram_block3a_3.port_b_address_clear = "none", - ram_block3a_3.port_b_address_clock = "clock1", - ram_block3a_3.port_b_address_width = 12, - ram_block3a_3.port_b_data_out_clear = "none", - ram_block3a_3.port_b_data_out_clock = "none", - ram_block3a_3.port_b_data_width = 1, - ram_block3a_3.port_b_first_address = 0, - ram_block3a_3.port_b_first_bit_number = 3, - ram_block3a_3.port_b_last_address = 4095, - ram_block3a_3.port_b_logical_ram_depth = 4096, - ram_block3a_3.port_b_logical_ram_width = 16, - ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_3.ram_block_type = "auto", - ram_block3a_3.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_4 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[4]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_4portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_4.connectivity_checking = "OFF", - ram_block3a_4.logical_ram_name = "ALTSYNCRAM", - ram_block3a_4.mixed_port_feed_through_mode = "dont_care", - ram_block3a_4.operation_mode = "dual_port", - ram_block3a_4.port_a_address_width = 12, - ram_block3a_4.port_a_data_width = 1, - ram_block3a_4.port_a_first_address = 0, - ram_block3a_4.port_a_first_bit_number = 4, - ram_block3a_4.port_a_last_address = 4095, - ram_block3a_4.port_a_logical_ram_depth = 4096, - ram_block3a_4.port_a_logical_ram_width = 16, - ram_block3a_4.port_b_address_clear = "none", - ram_block3a_4.port_b_address_clock = "clock1", - ram_block3a_4.port_b_address_width = 12, - ram_block3a_4.port_b_data_out_clear = "none", - ram_block3a_4.port_b_data_out_clock = "none", - ram_block3a_4.port_b_data_width = 1, - ram_block3a_4.port_b_first_address = 0, - ram_block3a_4.port_b_first_bit_number = 4, - ram_block3a_4.port_b_last_address = 4095, - ram_block3a_4.port_b_logical_ram_depth = 4096, - ram_block3a_4.port_b_logical_ram_width = 16, - ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_4.ram_block_type = "auto", - ram_block3a_4.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_5 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[5]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_5portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_5.connectivity_checking = "OFF", - ram_block3a_5.logical_ram_name = "ALTSYNCRAM", - ram_block3a_5.mixed_port_feed_through_mode = "dont_care", - ram_block3a_5.operation_mode = "dual_port", - ram_block3a_5.port_a_address_width = 12, - ram_block3a_5.port_a_data_width = 1, - ram_block3a_5.port_a_first_address = 0, - ram_block3a_5.port_a_first_bit_number = 5, - ram_block3a_5.port_a_last_address = 4095, - ram_block3a_5.port_a_logical_ram_depth = 4096, - ram_block3a_5.port_a_logical_ram_width = 16, - ram_block3a_5.port_b_address_clear = "none", - ram_block3a_5.port_b_address_clock = "clock1", - ram_block3a_5.port_b_address_width = 12, - ram_block3a_5.port_b_data_out_clear = "none", - ram_block3a_5.port_b_data_out_clock = "none", - ram_block3a_5.port_b_data_width = 1, - ram_block3a_5.port_b_first_address = 0, - ram_block3a_5.port_b_first_bit_number = 5, - ram_block3a_5.port_b_last_address = 4095, - ram_block3a_5.port_b_logical_ram_depth = 4096, - ram_block3a_5.port_b_logical_ram_width = 16, - ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_5.ram_block_type = "auto", - ram_block3a_5.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_6 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[6]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_6portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_6.connectivity_checking = "OFF", - ram_block3a_6.logical_ram_name = "ALTSYNCRAM", - ram_block3a_6.mixed_port_feed_through_mode = "dont_care", - ram_block3a_6.operation_mode = "dual_port", - ram_block3a_6.port_a_address_width = 12, - ram_block3a_6.port_a_data_width = 1, - ram_block3a_6.port_a_first_address = 0, - ram_block3a_6.port_a_first_bit_number = 6, - ram_block3a_6.port_a_last_address = 4095, - ram_block3a_6.port_a_logical_ram_depth = 4096, - ram_block3a_6.port_a_logical_ram_width = 16, - ram_block3a_6.port_b_address_clear = "none", - ram_block3a_6.port_b_address_clock = "clock1", - ram_block3a_6.port_b_address_width = 12, - ram_block3a_6.port_b_data_out_clear = "none", - ram_block3a_6.port_b_data_out_clock = "none", - ram_block3a_6.port_b_data_width = 1, - ram_block3a_6.port_b_first_address = 0, - ram_block3a_6.port_b_first_bit_number = 6, - ram_block3a_6.port_b_last_address = 4095, - ram_block3a_6.port_b_logical_ram_depth = 4096, - ram_block3a_6.port_b_logical_ram_width = 16, - ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_6.ram_block_type = "auto", - ram_block3a_6.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_7 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[7]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_7portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_7.connectivity_checking = "OFF", - ram_block3a_7.logical_ram_name = "ALTSYNCRAM", - ram_block3a_7.mixed_port_feed_through_mode = "dont_care", - ram_block3a_7.operation_mode = "dual_port", - ram_block3a_7.port_a_address_width = 12, - ram_block3a_7.port_a_data_width = 1, - ram_block3a_7.port_a_first_address = 0, - ram_block3a_7.port_a_first_bit_number = 7, - ram_block3a_7.port_a_last_address = 4095, - ram_block3a_7.port_a_logical_ram_depth = 4096, - ram_block3a_7.port_a_logical_ram_width = 16, - ram_block3a_7.port_b_address_clear = "none", - ram_block3a_7.port_b_address_clock = "clock1", - ram_block3a_7.port_b_address_width = 12, - ram_block3a_7.port_b_data_out_clear = "none", - ram_block3a_7.port_b_data_out_clock = "none", - ram_block3a_7.port_b_data_width = 1, - ram_block3a_7.port_b_first_address = 0, - ram_block3a_7.port_b_first_bit_number = 7, - ram_block3a_7.port_b_last_address = 4095, - ram_block3a_7.port_b_logical_ram_depth = 4096, - ram_block3a_7.port_b_logical_ram_width = 16, - ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_7.ram_block_type = "auto", - ram_block3a_7.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_8 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[8]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_8portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_8.connectivity_checking = "OFF", - ram_block3a_8.logical_ram_name = "ALTSYNCRAM", - ram_block3a_8.mixed_port_feed_through_mode = "dont_care", - ram_block3a_8.operation_mode = "dual_port", - ram_block3a_8.port_a_address_width = 12, - ram_block3a_8.port_a_data_width = 1, - ram_block3a_8.port_a_first_address = 0, - ram_block3a_8.port_a_first_bit_number = 8, - ram_block3a_8.port_a_last_address = 4095, - ram_block3a_8.port_a_logical_ram_depth = 4096, - ram_block3a_8.port_a_logical_ram_width = 16, - ram_block3a_8.port_b_address_clear = "none", - ram_block3a_8.port_b_address_clock = "clock1", - ram_block3a_8.port_b_address_width = 12, - ram_block3a_8.port_b_data_out_clear = "none", - ram_block3a_8.port_b_data_out_clock = "none", - ram_block3a_8.port_b_data_width = 1, - ram_block3a_8.port_b_first_address = 0, - ram_block3a_8.port_b_first_bit_number = 8, - ram_block3a_8.port_b_last_address = 4095, - ram_block3a_8.port_b_logical_ram_depth = 4096, - ram_block3a_8.port_b_logical_ram_width = 16, - ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_8.ram_block_type = "auto", - ram_block3a_8.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_9 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[9]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_9portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_9.connectivity_checking = "OFF", - ram_block3a_9.logical_ram_name = "ALTSYNCRAM", - ram_block3a_9.mixed_port_feed_through_mode = "dont_care", - ram_block3a_9.operation_mode = "dual_port", - ram_block3a_9.port_a_address_width = 12, - ram_block3a_9.port_a_data_width = 1, - ram_block3a_9.port_a_first_address = 0, - ram_block3a_9.port_a_first_bit_number = 9, - ram_block3a_9.port_a_last_address = 4095, - ram_block3a_9.port_a_logical_ram_depth = 4096, - ram_block3a_9.port_a_logical_ram_width = 16, - ram_block3a_9.port_b_address_clear = "none", - ram_block3a_9.port_b_address_clock = "clock1", - ram_block3a_9.port_b_address_width = 12, - ram_block3a_9.port_b_data_out_clear = "none", - ram_block3a_9.port_b_data_out_clock = "none", - ram_block3a_9.port_b_data_width = 1, - ram_block3a_9.port_b_first_address = 0, - ram_block3a_9.port_b_first_bit_number = 9, - ram_block3a_9.port_b_last_address = 4095, - ram_block3a_9.port_b_logical_ram_depth = 4096, - ram_block3a_9.port_b_logical_ram_width = 16, - ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_9.ram_block_type = "auto", - ram_block3a_9.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_10 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[10]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_10portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_10.connectivity_checking = "OFF", - ram_block3a_10.logical_ram_name = "ALTSYNCRAM", - ram_block3a_10.mixed_port_feed_through_mode = "dont_care", - ram_block3a_10.operation_mode = "dual_port", - ram_block3a_10.port_a_address_width = 12, - ram_block3a_10.port_a_data_width = 1, - ram_block3a_10.port_a_first_address = 0, - ram_block3a_10.port_a_first_bit_number = 10, - ram_block3a_10.port_a_last_address = 4095, - ram_block3a_10.port_a_logical_ram_depth = 4096, - ram_block3a_10.port_a_logical_ram_width = 16, - ram_block3a_10.port_b_address_clear = "none", - ram_block3a_10.port_b_address_clock = "clock1", - ram_block3a_10.port_b_address_width = 12, - ram_block3a_10.port_b_data_out_clear = "none", - ram_block3a_10.port_b_data_out_clock = "none", - ram_block3a_10.port_b_data_width = 1, - ram_block3a_10.port_b_first_address = 0, - ram_block3a_10.port_b_first_bit_number = 10, - ram_block3a_10.port_b_last_address = 4095, - ram_block3a_10.port_b_logical_ram_depth = 4096, - ram_block3a_10.port_b_logical_ram_width = 16, - ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_10.ram_block_type = "auto", - ram_block3a_10.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_11 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[11]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_11portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_11.connectivity_checking = "OFF", - ram_block3a_11.logical_ram_name = "ALTSYNCRAM", - ram_block3a_11.mixed_port_feed_through_mode = "dont_care", - ram_block3a_11.operation_mode = "dual_port", - ram_block3a_11.port_a_address_width = 12, - ram_block3a_11.port_a_data_width = 1, - ram_block3a_11.port_a_first_address = 0, - ram_block3a_11.port_a_first_bit_number = 11, - ram_block3a_11.port_a_last_address = 4095, - ram_block3a_11.port_a_logical_ram_depth = 4096, - ram_block3a_11.port_a_logical_ram_width = 16, - ram_block3a_11.port_b_address_clear = "none", - ram_block3a_11.port_b_address_clock = "clock1", - ram_block3a_11.port_b_address_width = 12, - ram_block3a_11.port_b_data_out_clear = "none", - ram_block3a_11.port_b_data_out_clock = "none", - ram_block3a_11.port_b_data_width = 1, - ram_block3a_11.port_b_first_address = 0, - ram_block3a_11.port_b_first_bit_number = 11, - ram_block3a_11.port_b_last_address = 4095, - ram_block3a_11.port_b_logical_ram_depth = 4096, - ram_block3a_11.port_b_logical_ram_width = 16, - ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_11.ram_block_type = "auto", - ram_block3a_11.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_12 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[12]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_12portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_12.connectivity_checking = "OFF", - ram_block3a_12.logical_ram_name = "ALTSYNCRAM", - ram_block3a_12.mixed_port_feed_through_mode = "dont_care", - ram_block3a_12.operation_mode = "dual_port", - ram_block3a_12.port_a_address_width = 12, - ram_block3a_12.port_a_data_width = 1, - ram_block3a_12.port_a_first_address = 0, - ram_block3a_12.port_a_first_bit_number = 12, - ram_block3a_12.port_a_last_address = 4095, - ram_block3a_12.port_a_logical_ram_depth = 4096, - ram_block3a_12.port_a_logical_ram_width = 16, - ram_block3a_12.port_b_address_clear = "none", - ram_block3a_12.port_b_address_clock = "clock1", - ram_block3a_12.port_b_address_width = 12, - ram_block3a_12.port_b_data_out_clear = "none", - ram_block3a_12.port_b_data_out_clock = "none", - ram_block3a_12.port_b_data_width = 1, - ram_block3a_12.port_b_first_address = 0, - ram_block3a_12.port_b_first_bit_number = 12, - ram_block3a_12.port_b_last_address = 4095, - ram_block3a_12.port_b_logical_ram_depth = 4096, - ram_block3a_12.port_b_logical_ram_width = 16, - ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_12.ram_block_type = "auto", - ram_block3a_12.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_13 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[13]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_13portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_13.connectivity_checking = "OFF", - ram_block3a_13.logical_ram_name = "ALTSYNCRAM", - ram_block3a_13.mixed_port_feed_through_mode = "dont_care", - ram_block3a_13.operation_mode = "dual_port", - ram_block3a_13.port_a_address_width = 12, - ram_block3a_13.port_a_data_width = 1, - ram_block3a_13.port_a_first_address = 0, - ram_block3a_13.port_a_first_bit_number = 13, - ram_block3a_13.port_a_last_address = 4095, - ram_block3a_13.port_a_logical_ram_depth = 4096, - ram_block3a_13.port_a_logical_ram_width = 16, - ram_block3a_13.port_b_address_clear = "none", - ram_block3a_13.port_b_address_clock = "clock1", - ram_block3a_13.port_b_address_width = 12, - ram_block3a_13.port_b_data_out_clear = "none", - ram_block3a_13.port_b_data_out_clock = "none", - ram_block3a_13.port_b_data_width = 1, - ram_block3a_13.port_b_first_address = 0, - ram_block3a_13.port_b_first_bit_number = 13, - ram_block3a_13.port_b_last_address = 4095, - ram_block3a_13.port_b_logical_ram_depth = 4096, - ram_block3a_13.port_b_logical_ram_width = 16, - ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_13.ram_block_type = "auto", - ram_block3a_13.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_14 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[14]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_14portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_14.connectivity_checking = "OFF", - ram_block3a_14.logical_ram_name = "ALTSYNCRAM", - ram_block3a_14.mixed_port_feed_through_mode = "dont_care", - ram_block3a_14.operation_mode = "dual_port", - ram_block3a_14.port_a_address_width = 12, - ram_block3a_14.port_a_data_width = 1, - ram_block3a_14.port_a_first_address = 0, - ram_block3a_14.port_a_first_bit_number = 14, - ram_block3a_14.port_a_last_address = 4095, - ram_block3a_14.port_a_logical_ram_depth = 4096, - ram_block3a_14.port_a_logical_ram_width = 16, - ram_block3a_14.port_b_address_clear = "none", - ram_block3a_14.port_b_address_clock = "clock1", - ram_block3a_14.port_b_address_width = 12, - ram_block3a_14.port_b_data_out_clear = "none", - ram_block3a_14.port_b_data_out_clock = "none", - ram_block3a_14.port_b_data_width = 1, - ram_block3a_14.port_b_first_address = 0, - ram_block3a_14.port_b_first_bit_number = 14, - ram_block3a_14.port_b_last_address = 4095, - ram_block3a_14.port_b_logical_ram_depth = 4096, - ram_block3a_14.port_b_logical_ram_width = 16, - ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_14.ram_block_type = "auto", - ram_block3a_14.lpm_type = "cyclone_ram_block"; - cyclone_ram_block ram_block3a_15 - ( - .clk0(clock0), - .clk1(clock1), - .ena0(wren_a), - .ena1(clocken1), - .portaaddr({address_a_wire[11:0]}), - .portadatain({data_a[15]}), - .portadataout(), - .portawe(1'b1), - .portbaddr({address_b_wire[11:0]}), - .portbdataout(wire_ram_block3a_15portbdataout[0:0]), - .portbrewe(1'b1) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .clr0(1'b0), - .clr1(1'b0), - .portabyteenamasks(1'b1), - .portbbyteenamasks(1'b1), - .portbdatain(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - ram_block3a_15.connectivity_checking = "OFF", - ram_block3a_15.logical_ram_name = "ALTSYNCRAM", - ram_block3a_15.mixed_port_feed_through_mode = "dont_care", - ram_block3a_15.operation_mode = "dual_port", - ram_block3a_15.port_a_address_width = 12, - ram_block3a_15.port_a_data_width = 1, - ram_block3a_15.port_a_first_address = 0, - ram_block3a_15.port_a_first_bit_number = 15, - ram_block3a_15.port_a_last_address = 4095, - ram_block3a_15.port_a_logical_ram_depth = 4096, - ram_block3a_15.port_a_logical_ram_width = 16, - ram_block3a_15.port_b_address_clear = "none", - ram_block3a_15.port_b_address_clock = "clock1", - ram_block3a_15.port_b_address_width = 12, - ram_block3a_15.port_b_data_out_clear = "none", - ram_block3a_15.port_b_data_out_clock = "none", - ram_block3a_15.port_b_data_width = 1, - ram_block3a_15.port_b_first_address = 0, - ram_block3a_15.port_b_first_bit_number = 15, - ram_block3a_15.port_b_last_address = 4095, - ram_block3a_15.port_b_logical_ram_depth = 4096, - ram_block3a_15.port_b_logical_ram_width = 16, - ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", - ram_block3a_15.ram_block_type = "auto", - ram_block3a_15.lpm_type = "cyclone_ram_block"; - assign - address_a_wire = address_a, - address_b_wire = address_b, - q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; -endmodule //fifo_4k_altsyncram_8pl - - -//dffpipe DELAY=1 WIDTH=12 clock clrn d q -//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - -//synthesis_resources = lut 12 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_dffpipe_bb3 - ( - clock, - clrn, - d, - q) /* synthesis synthesis_clearbox=1 */ - /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; - input clock; - input clrn; - input [11:0] d; - output [11:0] q; - - wire [11:0] wire_dffe4a_D; - reg [11:0] dffe4a; - wire ena; - wire prn; - wire sclr; - - // synopsys translate_off - initial - dffe4a[0:0] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[0:0] <= 1'b1; - else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; - else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; - // synopsys translate_off - initial - dffe4a[1:1] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[1:1] <= 1'b1; - else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; - else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; - // synopsys translate_off - initial - dffe4a[2:2] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[2:2] <= 1'b1; - else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; - else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; - // synopsys translate_off - initial - dffe4a[3:3] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[3:3] <= 1'b1; - else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; - else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; - // synopsys translate_off - initial - dffe4a[4:4] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[4:4] <= 1'b1; - else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; - else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; - // synopsys translate_off - initial - dffe4a[5:5] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[5:5] <= 1'b1; - else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; - else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; - // synopsys translate_off - initial - dffe4a[6:6] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[6:6] <= 1'b1; - else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; - else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; - // synopsys translate_off - initial - dffe4a[7:7] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[7:7] <= 1'b1; - else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; - else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; - // synopsys translate_off - initial - dffe4a[8:8] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[8:8] <= 1'b1; - else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; - else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; - // synopsys translate_off - initial - dffe4a[9:9] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[9:9] <= 1'b1; - else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; - else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; - // synopsys translate_off - initial - dffe4a[10:10] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[10:10] <= 1'b1; - else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; - else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; - // synopsys translate_off - initial - dffe4a[11:11] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe4a[11:11] <= 1'b1; - else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0; - else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11]; - assign - wire_dffe4a_D = (d & {12{(~ sclr)}}); - assign - ena = 1'b1, - prn = 1'b1, - q = dffe4a, - sclr = 1'b0; -endmodule //fifo_4k_dffpipe_bb3 - - -//dffpipe WIDTH=12 clock clrn d q -//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - - -//dffpipe WIDTH=12 clock clrn d q -//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END - -//synthesis_resources = lut 12 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_dffpipe_em2 - ( - clock, - clrn, - d, - q) /* synthesis synthesis_clearbox=1 */ - /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; - input clock; - input clrn; - input [11:0] d; - output [11:0] q; - - wire [11:0] wire_dffe6a_D; - reg [11:0] dffe6a; - wire ena; - wire prn; - wire sclr; - - // synopsys translate_off - initial - dffe6a[0:0] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[0:0] <= 1'b1; - else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; - else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; - // synopsys translate_off - initial - dffe6a[1:1] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[1:1] <= 1'b1; - else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; - else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; - // synopsys translate_off - initial - dffe6a[2:2] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[2:2] <= 1'b1; - else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; - else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; - // synopsys translate_off - initial - dffe6a[3:3] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[3:3] <= 1'b1; - else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; - else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; - // synopsys translate_off - initial - dffe6a[4:4] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[4:4] <= 1'b1; - else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; - else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; - // synopsys translate_off - initial - dffe6a[5:5] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[5:5] <= 1'b1; - else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; - else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; - // synopsys translate_off - initial - dffe6a[6:6] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[6:6] <= 1'b1; - else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; - else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; - // synopsys translate_off - initial - dffe6a[7:7] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[7:7] <= 1'b1; - else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; - else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; - // synopsys translate_off - initial - dffe6a[8:8] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[8:8] <= 1'b1; - else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; - else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; - // synopsys translate_off - initial - dffe6a[9:9] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[9:9] <= 1'b1; - else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; - else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; - // synopsys translate_off - initial - dffe6a[10:10] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[10:10] <= 1'b1; - else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; - else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; - // synopsys translate_off - initial - dffe6a[11:11] = 0; - // synopsys translate_on - always @ ( posedge clock or negedge prn or negedge clrn) - if (prn == 1'b0) dffe6a[11:11] <= 1'b1; - else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0; - else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11]; - assign - wire_dffe6a_D = (d & {12{(~ sclr)}}); - assign - ena = 1'b1, - prn = 1'b1, - q = dffe6a, - sclr = 1'b0; -endmodule //fifo_4k_dffpipe_em2 - -//synthesis_resources = lut 12 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_alt_synch_pipe_em2 - ( - clock, - clrn, - d, - q) /* synthesis synthesis_clearbox=1 */ - /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; - input clock; - input clrn; - input [11:0] d; - output [11:0] q; - - wire [11:0] wire_dffpipe5_q; - - fifo_4k_dffpipe_em2 dffpipe5 - ( - .clock(clock), - .clrn(clrn), - .d(d), - .q(wire_dffpipe5_q)); - assign - q = wire_dffpipe5_q; -endmodule //fifo_4k_alt_synch_pipe_em2 - - -//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result -//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - -//synthesis_resources = lut 12 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_add_sub_b18 - ( - dataa, - datab, - result) /* synthesis synthesis_clearbox=1 */; - input [11:0] dataa; - input [11:0] datab; - output [11:0] result; - - wire [11:0] wire_add_sub_cella_combout; - wire [0:0] wire_add_sub_cella_0cout; - wire [0:0] wire_add_sub_cella_1cout; - wire [0:0] wire_add_sub_cella_2cout; - wire [0:0] wire_add_sub_cella_3cout; - wire [0:0] wire_add_sub_cella_4cout; - wire [0:0] wire_add_sub_cella_5cout; - wire [0:0] wire_add_sub_cella_6cout; - wire [0:0] wire_add_sub_cella_7cout; - wire [0:0] wire_add_sub_cella_8cout; - wire [0:0] wire_add_sub_cella_9cout; - wire [0:0] wire_add_sub_cella_10cout; - wire [11:0] wire_add_sub_cella_dataa; - wire [11:0] wire_add_sub_cella_datab; - - cyclone_lcell add_sub_cella_0 - ( - .cin(1'b1), - .combout(wire_add_sub_cella_combout[0:0]), - .cout(wire_add_sub_cella_0cout[0:0]), - .dataa(wire_add_sub_cella_dataa[0:0]), - .datab(wire_add_sub_cella_datab[0:0]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_0.cin_used = "true", - add_sub_cella_0.lut_mask = "69b2", - add_sub_cella_0.operation_mode = "arithmetic", - add_sub_cella_0.sum_lutc_input = "cin", - add_sub_cella_0.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_1 - ( - .cin(wire_add_sub_cella_0cout[0:0]), - .combout(wire_add_sub_cella_combout[1:1]), - .cout(wire_add_sub_cella_1cout[0:0]), - .dataa(wire_add_sub_cella_dataa[1:1]), - .datab(wire_add_sub_cella_datab[1:1]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_1.cin_used = "true", - add_sub_cella_1.lut_mask = "69b2", - add_sub_cella_1.operation_mode = "arithmetic", - add_sub_cella_1.sum_lutc_input = "cin", - add_sub_cella_1.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_2 - ( - .cin(wire_add_sub_cella_1cout[0:0]), - .combout(wire_add_sub_cella_combout[2:2]), - .cout(wire_add_sub_cella_2cout[0:0]), - .dataa(wire_add_sub_cella_dataa[2:2]), - .datab(wire_add_sub_cella_datab[2:2]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_2.cin_used = "true", - add_sub_cella_2.lut_mask = "69b2", - add_sub_cella_2.operation_mode = "arithmetic", - add_sub_cella_2.sum_lutc_input = "cin", - add_sub_cella_2.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_3 - ( - .cin(wire_add_sub_cella_2cout[0:0]), - .combout(wire_add_sub_cella_combout[3:3]), - .cout(wire_add_sub_cella_3cout[0:0]), - .dataa(wire_add_sub_cella_dataa[3:3]), - .datab(wire_add_sub_cella_datab[3:3]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_3.cin_used = "true", - add_sub_cella_3.lut_mask = "69b2", - add_sub_cella_3.operation_mode = "arithmetic", - add_sub_cella_3.sum_lutc_input = "cin", - add_sub_cella_3.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_4 - ( - .cin(wire_add_sub_cella_3cout[0:0]), - .combout(wire_add_sub_cella_combout[4:4]), - .cout(wire_add_sub_cella_4cout[0:0]), - .dataa(wire_add_sub_cella_dataa[4:4]), - .datab(wire_add_sub_cella_datab[4:4]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_4.cin_used = "true", - add_sub_cella_4.lut_mask = "69b2", - add_sub_cella_4.operation_mode = "arithmetic", - add_sub_cella_4.sum_lutc_input = "cin", - add_sub_cella_4.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_5 - ( - .cin(wire_add_sub_cella_4cout[0:0]), - .combout(wire_add_sub_cella_combout[5:5]), - .cout(wire_add_sub_cella_5cout[0:0]), - .dataa(wire_add_sub_cella_dataa[5:5]), - .datab(wire_add_sub_cella_datab[5:5]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_5.cin_used = "true", - add_sub_cella_5.lut_mask = "69b2", - add_sub_cella_5.operation_mode = "arithmetic", - add_sub_cella_5.sum_lutc_input = "cin", - add_sub_cella_5.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_6 - ( - .cin(wire_add_sub_cella_5cout[0:0]), - .combout(wire_add_sub_cella_combout[6:6]), - .cout(wire_add_sub_cella_6cout[0:0]), - .dataa(wire_add_sub_cella_dataa[6:6]), - .datab(wire_add_sub_cella_datab[6:6]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_6.cin_used = "true", - add_sub_cella_6.lut_mask = "69b2", - add_sub_cella_6.operation_mode = "arithmetic", - add_sub_cella_6.sum_lutc_input = "cin", - add_sub_cella_6.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_7 - ( - .cin(wire_add_sub_cella_6cout[0:0]), - .combout(wire_add_sub_cella_combout[7:7]), - .cout(wire_add_sub_cella_7cout[0:0]), - .dataa(wire_add_sub_cella_dataa[7:7]), - .datab(wire_add_sub_cella_datab[7:7]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_7.cin_used = "true", - add_sub_cella_7.lut_mask = "69b2", - add_sub_cella_7.operation_mode = "arithmetic", - add_sub_cella_7.sum_lutc_input = "cin", - add_sub_cella_7.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_8 - ( - .cin(wire_add_sub_cella_7cout[0:0]), - .combout(wire_add_sub_cella_combout[8:8]), - .cout(wire_add_sub_cella_8cout[0:0]), - .dataa(wire_add_sub_cella_dataa[8:8]), - .datab(wire_add_sub_cella_datab[8:8]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_8.cin_used = "true", - add_sub_cella_8.lut_mask = "69b2", - add_sub_cella_8.operation_mode = "arithmetic", - add_sub_cella_8.sum_lutc_input = "cin", - add_sub_cella_8.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_9 - ( - .cin(wire_add_sub_cella_8cout[0:0]), - .combout(wire_add_sub_cella_combout[9:9]), - .cout(wire_add_sub_cella_9cout[0:0]), - .dataa(wire_add_sub_cella_dataa[9:9]), - .datab(wire_add_sub_cella_datab[9:9]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_9.cin_used = "true", - add_sub_cella_9.lut_mask = "69b2", - add_sub_cella_9.operation_mode = "arithmetic", - add_sub_cella_9.sum_lutc_input = "cin", - add_sub_cella_9.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_10 - ( - .cin(wire_add_sub_cella_9cout[0:0]), - .combout(wire_add_sub_cella_combout[10:10]), - .cout(wire_add_sub_cella_10cout[0:0]), - .dataa(wire_add_sub_cella_dataa[10:10]), - .datab(wire_add_sub_cella_datab[10:10]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_10.cin_used = "true", - add_sub_cella_10.lut_mask = "69b2", - add_sub_cella_10.operation_mode = "arithmetic", - add_sub_cella_10.sum_lutc_input = "cin", - add_sub_cella_10.lpm_type = "cyclone_lcell"; - cyclone_lcell add_sub_cella_11 - ( - .cin(wire_add_sub_cella_10cout[0:0]), - .combout(wire_add_sub_cella_combout[11:11]), - .cout(), - .dataa(wire_add_sub_cella_dataa[11:11]), - .datab(wire_add_sub_cella_datab[11:11]), - .regout() - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_off - `endif - , - .aclr(1'b0), - .aload(1'b0), - .clk(1'b1), - .datac(1'b1), - .datad(1'b1), - .ena(1'b1), - .inverta(1'b0), - .regcascin(1'b0), - .sclr(1'b0), - .sload(1'b0) - `ifdef FORMAL_VERIFICATION - `else - // synopsys translate_on - `endif - // synopsys translate_off - , - .cin0(), - .cin1(), - .cout0(), - .cout1(), - .devclrn(), - .devpor() - // synopsys translate_on - ); - defparam - add_sub_cella_11.cin_used = "true", - add_sub_cella_11.lut_mask = "6969", - add_sub_cella_11.operation_mode = "normal", - add_sub_cella_11.sum_lutc_input = "cin", - add_sub_cella_11.lpm_type = "cyclone_lcell"; - assign - wire_add_sub_cella_dataa = dataa, - wire_add_sub_cella_datab = datab; - assign - result = wire_add_sub_cella_combout; -endmodule //fifo_4k_add_sub_b18 - - -//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab -//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - - -//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab -//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END - -//synthesis_resources = lut 104 M4K 16 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module fifo_4k_dcfifo_6cq - ( - aclr, - data, - q, - rdclk, - rdempty, - rdreq, - rdusedw, - wrclk, - wrfull, - wrreq, - wrusedw) /* synthesis synthesis_clearbox=1 */ - /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; - input aclr; - input [15:0] data; - output [15:0] q; - input rdclk; - output rdempty; - input rdreq; - output [11:0] rdusedw; - input wrclk; - output wrfull; - input wrreq; - output [11:0] wrusedw; - - wire [11:0] wire_rdptr_g_gray2bin_bin; - wire [11:0] wire_rs_dgwp_gray2bin_bin; - wire [11:0] wire_wrptr_g_gray2bin_bin; - wire [11:0] wire_ws_dgrp_gray2bin_bin; - wire [11:0] wire_rdptr_g_q; - wire [11:0] wire_rdptr_g1p_q; - wire [11:0] wire_wrptr_g1p_q; - wire [15:0] wire_fifo_ram_q_b; - reg [11:0] delayed_wrptr_g; - reg [11:0] wrptr_g; - wire [11:0] wire_rs_brp_q; - wire [11:0] wire_rs_bwp_q; - wire [11:0] wire_rs_dgwp_q; - wire [11:0] wire_ws_brp_q; - wire [11:0] wire_ws_bwp_q; - wire [11:0] wire_ws_dgrp_q; - wire [11:0] wire_rdusedw_sub_result; - wire [11:0] wire_wrusedw_sub_result; - reg wire_rdempty_eq_comp_aeb_int; - wire wire_rdempty_eq_comp_aeb; - wire [11:0] wire_rdempty_eq_comp_dataa; - wire [11:0] wire_rdempty_eq_comp_datab; - reg wire_wrfull_eq_comp_aeb_int; - wire wire_wrfull_eq_comp_aeb; - wire [11:0] wire_wrfull_eq_comp_dataa; - wire [11:0] wire_wrfull_eq_comp_datab; - wire int_rdempty; - wire int_wrfull; - wire valid_rdreq; - wire valid_wrreq; - - fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin - ( - .bin(wire_rdptr_g_gray2bin_bin), - .gray(wire_rdptr_g_q)); - fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin - ( - .bin(wire_rs_dgwp_gray2bin_bin), - .gray(wire_rs_dgwp_q)); - fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin - ( - .bin(wire_wrptr_g_gray2bin_bin), - .gray(wrptr_g)); - fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin - ( - .bin(wire_ws_dgrp_gray2bin_bin), - .gray(wire_ws_dgrp_q)); - fifo_4k_a_graycounter_826 rdptr_g - ( - .aclr(aclr), - .clock(rdclk), - .cnt_en(valid_rdreq), - .q(wire_rdptr_g_q)); - fifo_4k_a_graycounter_3r6 rdptr_g1p - ( - .aclr(aclr), - .clock(rdclk), - .cnt_en(valid_rdreq), - .q(wire_rdptr_g1p_q)); - fifo_4k_a_graycounter_3r6 wrptr_g1p - ( - .aclr(aclr), - .clock(wrclk), - .cnt_en(valid_wrreq), - .q(wire_wrptr_g1p_q)); - fifo_4k_altsyncram_8pl fifo_ram - ( - .address_a(wrptr_g), - .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))), - .clock0(wrclk), - .clock1(rdclk), - .clocken1((valid_rdreq | int_rdempty)), - .data_a(data), - .q_b(wire_fifo_ram_q_b), - .wren_a(valid_wrreq)); - // synopsys translate_off - initial - delayed_wrptr_g = 0; - // synopsys translate_on - always @ ( posedge wrclk or posedge aclr) - if (aclr == 1'b1) delayed_wrptr_g <= 12'b0; - else delayed_wrptr_g <= wrptr_g; - // synopsys translate_off - initial - wrptr_g = 0; - // synopsys translate_on - always @ ( posedge wrclk or posedge aclr) - if (aclr == 1'b1) wrptr_g <= 12'b0; - else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; - fifo_4k_dffpipe_bb3 rs_brp - ( - .clock(rdclk), - .clrn((~ aclr)), - .d(wire_rdptr_g_gray2bin_bin), - .q(wire_rs_brp_q)); - fifo_4k_dffpipe_bb3 rs_bwp - ( - .clock(rdclk), - .clrn((~ aclr)), - .d(wire_rs_dgwp_gray2bin_bin), - .q(wire_rs_bwp_q)); - fifo_4k_alt_synch_pipe_em2 rs_dgwp - ( - .clock(rdclk), - .clrn((~ aclr)), - .d(delayed_wrptr_g), - .q(wire_rs_dgwp_q)); - fifo_4k_dffpipe_bb3 ws_brp - ( - .clock(wrclk), - .clrn((~ aclr)), - .d(wire_ws_dgrp_gray2bin_bin), - .q(wire_ws_brp_q)); - fifo_4k_dffpipe_bb3 ws_bwp - ( - .clock(wrclk), - .clrn((~ aclr)), - .d(wire_wrptr_g_gray2bin_bin), - .q(wire_ws_bwp_q)); - fifo_4k_alt_synch_pipe_em2 ws_dgrp - ( - .clock(wrclk), - .clrn((~ aclr)), - .d(wire_rdptr_g_q), - .q(wire_ws_dgrp_q)); - fifo_4k_add_sub_b18 rdusedw_sub - ( - .dataa(wire_rs_bwp_q), - .datab(wire_rs_brp_q), - .result(wire_rdusedw_sub_result)); - fifo_4k_add_sub_b18 wrusedw_sub - ( - .dataa(wire_ws_bwp_q), - .datab(wire_ws_brp_q), - .result(wire_wrusedw_sub_result)); - always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) - if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) - begin - wire_rdempty_eq_comp_aeb_int = 1'b1; - end - else - begin - wire_rdempty_eq_comp_aeb_int = 1'b0; - end - assign - wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; - assign - wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, - wire_rdempty_eq_comp_datab = wire_rdptr_g_q; - always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) - if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) - begin - wire_wrfull_eq_comp_aeb_int = 1'b1; - end - else - begin - wire_wrfull_eq_comp_aeb_int = 1'b0; - end - assign - wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; - assign - wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, - wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; - assign - int_rdempty = wire_rdempty_eq_comp_aeb, - int_wrfull = wire_wrfull_eq_comp_aeb, - q = wire_fifo_ram_q_b, - rdempty = int_rdempty, - rdusedw = wire_rdusedw_sub_result, - valid_rdreq = rdreq, - valid_wrreq = wrreq, - wrfull = int_wrfull, - wrusedw = wire_wrusedw_sub_result; -endmodule //fifo_4k_dcfifo_6cq -//VALID FILE - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_4k ( - data, - wrreq, - rdreq, - rdclk, - wrclk, - aclr, - q, - rdempty, - rdusedw, - wrfull, - wrusedw)/* synthesis synthesis_clearbox = 1 */; - - input [15:0] data; - input wrreq; - input rdreq; - input rdclk; - input wrclk; - input aclr; - output [15:0] q; - output rdempty; - output [11:0] rdusedw; - output wrfull; - output [11:0] wrusedw; - - wire sub_wire0; - wire [11:0] sub_wire1; - wire sub_wire2; - wire [15:0] sub_wire3; - wire [11:0] sub_wire4; - wire rdempty = sub_wire0; - wire [11:0] wrusedw = sub_wire1[11:0]; - wire wrfull = sub_wire2; - wire [15:0] q = sub_wire3[15:0]; - wire [11:0] rdusedw = sub_wire4[11:0]; - - fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component ( - .wrclk (wrclk), - .rdreq (rdreq), - .aclr (aclr), - .rdclk (rdclk), - .wrreq (wrreq), - .data (data), - .rdempty (sub_wire0), - .wrusedw (sub_wire1), - .wrfull (sub_wire2), - .q (sub_wire3), - .rdusedw (sub_wire4)); - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE diff --git a/megacells/fifo_4k_18.v b/megacells/fifo_4k_18.v deleted file mode 100755 index ad76121bb..000000000 --- a/megacells/fifo_4k_18.v +++ /dev/null @@ -1,186 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_4k_18.v -// Megafunction Name(s): -// dcfifo -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2007 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_4k_18 ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - rdusedw, - wrfull, - wrusedw); - - input aclr; - input [17:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [17:0] q; - output rdempty; - output [11:0] rdusedw; - output wrfull; - output [11:0] wrusedw; - - wire sub_wire0; - wire [11:0] sub_wire1; - wire sub_wire2; - wire [17:0] sub_wire3; - wire [11:0] sub_wire4; - wire rdempty = sub_wire0; - wire [11:0] wrusedw = sub_wire1[11:0]; - wire wrfull = sub_wire2; - wire [17:0] q = sub_wire3[17:0]; - wire [11:0] rdusedw = sub_wire4[11:0]; - - dcfifo dcfifo_component ( - .wrclk (wrclk), - .rdreq (rdreq), - .aclr (aclr), - .rdclk (rdclk), - .wrreq (wrreq), - .data (data), - .rdempty (sub_wire0), - .wrusedw (sub_wire1), - .wrfull (sub_wire2), - .q (sub_wire3), - .rdusedw (sub_wire4) - // synopsys translate_off - , - .rdfull (), - .wrempty () - // synopsys translate_on - ); - defparam - dcfifo_component.add_ram_output_register = "OFF", - dcfifo_component.clocks_are_synchronized = "FALSE", - dcfifo_component.intended_device_family = "Cyclone", - dcfifo_component.lpm_numwords = 4096, - dcfifo_component.lpm_showahead = "ON", - dcfifo_component.lpm_type = "dcfifo", - dcfifo_component.lpm_width = 18, - dcfifo_component.lpm_widthu = 12, - dcfifo_component.overflow_checking = "OFF", - dcfifo_component.underflow_checking = "OFF", - dcfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "18" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: diff_widths NUMERIC "0" -// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" -// Retrieval info: PRIVATE: output_width NUMERIC "18" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0] -// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0] -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] -// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0 -// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/megacells/fifo_4k_bb.v b/megacells/fifo_4k_bb.v deleted file mode 100644 index fc4ca9797..000000000 --- a/megacells/fifo_4k_bb.v +++ /dev/null @@ -1,131 +0,0 @@ -// megafunction wizard: %FIFO%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_4k.v -// Megafunction Name(s): -// dcfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2005 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_4k ( - data, - wrreq, - rdreq, - rdclk, - wrclk, - aclr, - q, - rdempty, - rdusedw, - wrfull, - wrusedw)/* synthesis synthesis_clearbox = 1 */; - - input [15:0] data; - input wrreq; - input rdreq; - input rdclk; - input wrclk; - input aclr; - output [15:0] q; - output rdempty; - output [11:0] rdusedw; - output wrfull; - output [11:0] wrusedw; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_dc.bsf b/megacells/fifo_4kx16_dc.bsf deleted file mode 100755 index b80add8de..000000000 --- a/megacells/fifo_4kx16_dc.bsf +++ /dev/null @@ -1,117 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2006 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 184) - (text "fifo_4kx16_dc" (rect 41 1 134 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 168 25 180)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 104) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 16 104)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) - (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 0 160) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8))) - (line (pt 0 160)(pt 16 160)(line_width 1)) - ) - (port - (pt 160 40) - (output) - (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8))) - (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8))) - (line (pt 160 40)(pt 144 40)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "wrusedw[11..0]" (rect 0 0 92 14)(font "Arial" (font_size 8))) - (text "wrusedw[11..0]" (rect 63 66 132 79)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 144 72)(line_width 3)) - ) - (port - (pt 160 96) - (output) - (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) - (line (pt 160 96)(pt 144 96)(line_width 3)) - ) - (port - (pt 160 120) - (output) - (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) - (text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8))) - (line (pt 160 120)(pt 144 120)(line_width 1)) - ) - (port - (pt 160 136) - (output) - (text "rdusedw[11..0]" (rect 0 0 87 14)(font "Arial" (font_size 8))) - (text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8))) - (line (pt 160 136)(pt 144 136)(line_width 3)) - ) - (drawing - (text "(ack)" (rect 51 99 72 111)(font "Arial" )) - (text "16 bits x 4096 words" (rect 58 156 144 168)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 168)(line_width 1)) - (line (pt 144 168)(pt 16 168)(line_width 1)) - (line (pt 16 168)(pt 16 16)(line_width 1)) - (line (pt 16 84)(pt 144 84)(line_width 1)) - (line (pt 16 148)(pt 144 148)(line_width 1)) - (line (pt 16 66)(pt 22 72)(line_width 1)) - (line (pt 22 72)(pt 16 78)(line_width 1)) - (line (pt 16 114)(pt 22 120)(line_width 1)) - (line (pt 22 120)(pt 16 126)(line_width 1)) - ) -) diff --git a/megacells/fifo_4kx16_dc.cmp b/megacells/fifo_4kx16_dc.cmp deleted file mode 100755 index 356de4d62..000000000 --- a/megacells/fifo_4kx16_dc.cmp +++ /dev/null @@ -1,31 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component fifo_4kx16_dc - PORT - ( - aclr : IN STD_LOGIC := '0'; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - rdempty : OUT STD_LOGIC ; - rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); - wrfull : OUT STD_LOGIC ; - wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) - ); -end component; diff --git a/megacells/fifo_4kx16_dc.inc b/megacells/fifo_4kx16_dc.inc deleted file mode 100755 index c14c01836..000000000 --- a/megacells/fifo_4kx16_dc.inc +++ /dev/null @@ -1,32 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION fifo_4kx16_dc -( - aclr, - data[15..0], - rdclk, - rdreq, - wrclk, - wrreq -) - -RETURNS ( - q[15..0], - rdempty, - rdusedw[11..0], - wrfull, - wrusedw[11..0] -); diff --git a/megacells/fifo_4kx16_dc.v b/megacells/fifo_4kx16_dc.v deleted file mode 100755 index 1f09000e3..000000000 --- a/megacells/fifo_4kx16_dc.v +++ /dev/null @@ -1,178 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_4kx16_dc.v -// Megafunction Name(s): -// dcfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_4kx16_dc ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - rdusedw, - wrfull, - wrusedw); - - input aclr; - input [15:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [15:0] q; - output rdempty; - output [11:0] rdusedw; - output wrfull; - output [11:0] wrusedw; - - wire sub_wire0; - wire [11:0] sub_wire1; - wire sub_wire2; - wire [15:0] sub_wire3; - wire [11:0] sub_wire4; - wire rdempty = sub_wire0; - wire [11:0] wrusedw = sub_wire1[11:0]; - wire wrfull = sub_wire2; - wire [15:0] q = sub_wire3[15:0]; - wire [11:0] rdusedw = sub_wire4[11:0]; - - dcfifo dcfifo_component ( - .wrclk (wrclk), - .rdreq (rdreq), - .aclr (aclr), - .rdclk (rdclk), - .wrreq (wrreq), - .data (data), - .rdempty (sub_wire0), - .wrusedw (sub_wire1), - .wrfull (sub_wire2), - .q (sub_wire3), - .rdusedw (sub_wire4) - // synopsys translate_off - , - .wrempty (), - .rdfull () - // synopsys translate_on - ); - defparam - dcfifo_component.add_ram_output_register = "OFF", - dcfifo_component.clocks_are_synchronized = "FALSE", - dcfifo_component.intended_device_family = "Cyclone", - dcfifo_component.lpm_numwords = 4096, - dcfifo_component.lpm_showahead = "ON", - dcfifo_component.lpm_type = "dcfifo", - dcfifo_component.lpm_width = 16, - dcfifo_component.lpm_widthu = 12, - dcfifo_component.overflow_checking = "OFF", - dcfifo_component.underflow_checking = "OFF", - dcfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_dc_bb.v b/megacells/fifo_4kx16_dc_bb.v deleted file mode 100755 index 91c3c322f..000000000 --- a/megacells/fifo_4kx16_dc_bb.v +++ /dev/null @@ -1,130 +0,0 @@ -// megafunction wizard: %FIFO%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo_4kx16_dc.v -// Megafunction Name(s): -// dcfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_4kx16_dc ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - rdusedw, - wrfull, - wrusedw); - - input aclr; - input [15:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [15:0] q; - output rdempty; - output [11:0] rdusedw; - output wrfull; - output [11:0] wrusedw; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE diff --git a/megacells/fifo_4kx16_dc_inst.v b/megacells/fifo_4kx16_dc_inst.v deleted file mode 100755 index 566f27a17..000000000 --- a/megacells/fifo_4kx16_dc_inst.v +++ /dev/null @@ -1,13 +0,0 @@ -fifo_4kx16_dc fifo_4kx16_dc_inst ( - .aclr ( aclr_sig ), - .data ( data_sig ), - .rdclk ( rdclk_sig ), - .rdreq ( rdreq_sig ), - .wrclk ( wrclk_sig ), - .wrreq ( wrreq_sig ), - .q ( q_sig ), - .rdempty ( rdempty_sig ), - .rdusedw ( rdusedw_sig ), - .wrfull ( wrfull_sig ), - .wrusedw ( wrusedw_sig ) - ); diff --git a/megacells/mylpm_addsub.bsf b/megacells/mylpm_addsub.bsf deleted file mode 100755 index e5c1ded7f..000000000 --- a/megacells/mylpm_addsub.bsf +++ /dev/null @@ -1,80 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2003 Altera Corporation -Any megafunction design, and related netlist (encrypted or decrypted), -support information, device programming or simulation file, and any other -associated documentation or information provided by Altera or a partner -under Altera's Megafunction Partnership Program may be used only -to program PLD devices (but not masked PLD devices) from Altera. Any -other use of such megafunction design, netlist, support information, -device programming or simulation file, or any other related documentation -or information is prohibited for any other purpose, including, but not -limited to modification, reverse engineering, de-compiling, or use with -any other silicon devices, unless such use is explicitly licensed under -a separate agreement with Altera or a megafunction partner. Title to the -intellectual property, including patents, copyrights, trademarks, trade -secrets, or maskworks, embodied in any such megafunction design, netlist, -support information, device programming or simulation file, or any other -related documentation or information provided by Altera or a megafunction -partner, remains with Altera, the megafunction partner, or their respective -licensors. No other licenses, including any licenses needed under any third -party's intellectual property, are provided herein. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 112) - (text "mylpm_addsub" (rect 26 2 145 21)(font "Arial" (font_size 10))) - (text "inst" (rect 8 93 30 108)(font "Arial" )) - (port - (pt 0 56) - (input) - (text "dataa[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) - (text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "datab[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) - (text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "clock" (rect 0 0 34 16)(font "Arial" (font_size 8))) - (text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 1)) - ) - (port - (pt 0 32) - (input) - (text "add_sub" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 80 32)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "result[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) - (text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 96 72)(line_width 3)) - ) - (drawing - (text "A" (rect 66 48 75 64)(font "Arial" (font_size 8))) - (text "B" (rect 66 80 75 96)(font "Arial" (font_size 8))) - (text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8))) - (line (pt 64 48)(pt 96 56)(line_width 1)) - (line (pt 96 56)(pt 96 88)(line_width 1)) - (line (pt 96 88)(pt 64 96)(line_width 1)) - (line (pt 64 96)(pt 64 48)(line_width 1)) - (line (pt 80 32)(pt 80 52)(line_width 1)) - (line (pt 106 40)(pt 125 40)(line_width 1)) - (line (pt 64 66)(pt 70 72)(line_width 1)) - (line (pt 70 72)(pt 64 78)(line_width 1)) - ) -) diff --git a/megacells/mylpm_addsub.cmp b/megacells/mylpm_addsub.cmp deleted file mode 100755 index 311c54a5b..000000000 --- a/megacells/mylpm_addsub.cmp +++ /dev/null @@ -1,31 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -component mylpm_addsub - PORT - ( - add_sub : IN STD_LOGIC ; - dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - clock : IN STD_LOGIC ; - result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) - ); -end component; diff --git a/megacells/mylpm_addsub.inc b/megacells/mylpm_addsub.inc deleted file mode 100755 index d8b283f49..000000000 --- a/megacells/mylpm_addsub.inc +++ /dev/null @@ -1,32 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -FUNCTION mylpm_addsub -( - add_sub, - dataa[15..0], - datab[15..0], - clock -) - -RETURNS ( - result[15..0] -); diff --git a/megacells/mylpm_addsub.v b/megacells/mylpm_addsub.v deleted file mode 100755 index 0566f7e57..000000000 --- a/megacells/mylpm_addsub.v +++ /dev/null @@ -1,102 +0,0 @@ -// megafunction wizard: %LPM_ADD_SUB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: lpm_add_sub - -// ============================================================ -// File Name: mylpm_addsub.v -// Megafunction Name(s): -// lpm_add_sub -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// ************************************************************ - - -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -module mylpm_addsub ( - add_sub, - dataa, - datab, - clock, - result); - - input add_sub; - input [15:0] dataa; - input [15:0] datab; - input clock; - output [15:0] result; - - wire [15:0] sub_wire0; - wire [15:0] result = sub_wire0[15:0]; - - lpm_add_sub lpm_add_sub_component ( - .dataa (dataa), - .add_sub (add_sub), - .datab (datab), - .clock (clock), - .result (sub_wire0)); - defparam - lpm_add_sub_component.lpm_width = 16, - lpm_add_sub_component.lpm_direction = "UNUSED", - lpm_add_sub_component.lpm_type = "LPM_ADD_SUB", - lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO", - lpm_add_sub_component.lpm_pipeline = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: nBit NUMERIC "16" -// Retrieval info: PRIVATE: Function NUMERIC "2" -// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" -// Retrieval info: PRIVATE: ConstantA NUMERIC "0" -// Retrieval info: PRIVATE: ConstantB NUMERIC "0" -// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" -// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" -// Retrieval info: PRIVATE: CarryIn NUMERIC "0" -// Retrieval info: PRIVATE: CarryOut NUMERIC "0" -// Retrieval info: PRIVATE: Overflow NUMERIC "0" -// Retrieval info: PRIVATE: Latency NUMERIC "1" -// Retrieval info: PRIVATE: aclr NUMERIC "0" -// Retrieval info: PRIVATE: clken NUMERIC "0" -// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED" -// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" -// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" -// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" -// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub -// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] -// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0] -// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0] -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0 -// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 -// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0 -// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/mylpm_addsub_bb.v b/megacells/mylpm_addsub_bb.v deleted file mode 100755 index 598d3da52..000000000 --- a/megacells/mylpm_addsub_bb.v +++ /dev/null @@ -1,35 +0,0 @@ -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module mylpm_addsub ( - add_sub, - dataa, - datab, - clock, - result); - - input add_sub; - input [15:0] dataa; - input [15:0] datab; - input clock; - output [15:0] result; - -endmodule - diff --git a/megacells/mylpm_addsub_inst.v b/megacells/mylpm_addsub_inst.v deleted file mode 100755 index dd732bd6d..000000000 --- a/megacells/mylpm_addsub_inst.v +++ /dev/null @@ -1,7 +0,0 @@ -mylpm_addsub mylpm_addsub_inst ( - .add_sub ( add_sub_sig ), - .dataa ( dataa_sig ), - .datab ( datab_sig ), - .clock ( clock_sig ), - .result ( result_sig ) - ); diff --git a/megacells/pll.v b/megacells/pll.v deleted file mode 100644 index dacd11f23..000000000 --- a/megacells/pll.v +++ /dev/null @@ -1,207 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: pll.v -// Megafunction Name(s): -// altpll -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2004 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module pll ( - inclk0, - c0); - - input inclk0; - output c0; - - wire [5:0] sub_wire0; - wire [0:0] sub_wire4 = 1'h0; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; - wire sub_wire2 = inclk0; - wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; - - altpll altpll_component ( - .inclk (sub_wire3), - .clk (sub_wire0) - // synopsys translate_off -, - .fbin (), - .pllena (), - .clkswitch (), - .areset (), - .pfdena (), - .clkena (), - .extclkena (), - .scanclk (), - .scanaclr (), - .scandata (), - .scanread (), - .scanwrite (), - .extclk (), - .clkbad (), - .activeclock (), - .locked (), - .clkloss (), - .scandataout (), - .scandone (), - .sclkout1 (), - .sclkout0 (), - .enable0 (), - .enable1 () - // synopsys translate_on - -); - defparam - altpll_component.clk0_duty_cycle = 50, - altpll_component.lpm_type = "altpll", - altpll_component.clk0_multiply_by = 1, - altpll_component.inclk0_input_frequency = 20833, - altpll_component.clk0_divide_by = 1, - altpll_component.pll_type = "AUTO", - altpll_component.clk0_time_delay = "0", - altpll_component.intended_device_family = "Cyclone", - altpll_component.operation_mode = "NORMAL", - altpll_component.compensate_clock = "CLK0", - altpll_component.clk0_phase_shift = "-3000"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" -// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" -// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" -// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE diff --git a/megacells/pll_bb.v b/megacells/pll_bb.v deleted file mode 100644 index debadaa25..000000000 --- a/megacells/pll_bb.v +++ /dev/null @@ -1,29 +0,0 @@ -//Copyright (C) 1991-2004 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module pll ( - inclk0, - c0); - - input inclk0; - output c0; - -endmodule - diff --git a/megacells/pll_inst.v b/megacells/pll_inst.v deleted file mode 100644 index 97db58ba0..000000000 --- a/megacells/pll_inst.v +++ /dev/null @@ -1,4 +0,0 @@ -pll pll_inst ( - .inclk0 ( inclk0_sig ), - .c0 ( c0_sig ) - ); diff --git a/megacells/sub32.bsf b/megacells/sub32.bsf deleted file mode 100755 index 753fdc738..000000000 --- a/megacells/sub32.bsf +++ /dev/null @@ -1,87 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2003 Altera Corporation -Any megafunction design, and related netlist (encrypted or decrypted), -support information, device programming or simulation file, and any other -associated documentation or information provided by Altera or a partner -under Altera's Megafunction Partnership Program may be used only -to program PLD devices (but not masked PLD devices) from Altera. Any -other use of such megafunction design, netlist, support information, -device programming or simulation file, or any other related documentation -or information is prohibited for any other purpose, including, but not -limited to modification, reverse engineering, de-compiling, or use with -any other silicon devices, unless such use is explicitly licensed under -a separate agreement with Altera or a megafunction partner. Title to the -intellectual property, including patents, copyrights, trademarks, trade -secrets, or maskworks, embodied in any such megafunction design, netlist, -support information, device programming or simulation file, or any other -related documentation or information provided by Altera or a megafunction -partner, remains with Altera, the megafunction partner, or their respective -licensors. No other licenses, including any licenses needed under any third -party's intellectual property, are provided herein. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 128) - (text "sub32" (rect 58 2 109 21)(font "Arial" (font_size 10))) - (text "inst" (rect 8 109 31 124)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "dataa[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) - (text "dataa[31..0]" (rect 4 24 73 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "datab[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) - (text "datab[31..0]" (rect 4 56 73 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clock" (rect 4 40 35 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clken" (rect 4 80 35 96)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 74 96)(line_width 1)) - ) - (port - (pt 0 112) - (input) - (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) - (text "aclr" (rect 4 96 25 112)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 85 112)(line_width 1)) - ) - (port - (pt 160 56) - (output) - (text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) - (text "result[31..0]" (rect 88 40 157 56)(font "Arial" (font_size 8))) - (line (pt 160 56)(pt 96 56)(line_width 3)) - ) - (drawing - (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8))) - (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8))) - (text "A-B" (rect 72 48 94 64)(font "Arial" (font_size 8))) - (line (pt 64 32)(pt 96 40)(line_width 1)) - (line (pt 96 40)(pt 96 72)(line_width 1)) - (line (pt 96 72)(pt 64 80)(line_width 1)) - (line (pt 64 80)(pt 64 32)(line_width 1)) - (line (pt 74 96)(pt 74 77)(line_width 1)) - (line (pt 85 112)(pt 85 74)(line_width 1)) - (line (pt 64 50)(pt 70 56)(line_width 1)) - (line (pt 70 56)(pt 64 62)(line_width 1)) - ) -) diff --git a/megacells/sub32.cmp b/megacells/sub32.cmp deleted file mode 100755 index 0d5b62ef9..000000000 --- a/megacells/sub32.cmp +++ /dev/null @@ -1,32 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -component sub32 - PORT - ( - dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - clock : IN STD_LOGIC ; - aclr : IN STD_LOGIC ; - clken : IN STD_LOGIC ; - result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) - ); -end component; diff --git a/megacells/sub32.inc b/megacells/sub32.inc deleted file mode 100755 index 3c64e21c5..000000000 --- a/megacells/sub32.inc +++ /dev/null @@ -1,33 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -FUNCTION sub32 -( - dataa[31..0], - datab[31..0], - clock, - aclr, - clken -) - -RETURNS ( - result[31..0] -); diff --git a/megacells/sub32.v b/megacells/sub32.v deleted file mode 100755 index dd825d91a..000000000 --- a/megacells/sub32.v +++ /dev/null @@ -1,675 +0,0 @@ -// megafunction wizard: %LPM_ADD_SUB%CBX% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: lpm_add_sub - -// ============================================================ -// File Name: sub32.v -// Megafunction Name(s): -// lpm_add_sub -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// ************************************************************ - - -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - - -//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result -//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END - -//synthesis_resources = lut 32 -module sub32_add_sub_cqa - ( - aclr, - clken, - clock, - dataa, - datab, - result) /* synthesis synthesis_clearbox=1 */; - input aclr; - input clken; - input clock; - input [31:0] dataa; - input [31:0] datab; - output [31:0] result; - - wire [0:0] wire_add_sub_cella_0cout; - wire [0:0] wire_add_sub_cella_1cout; - wire [0:0] wire_add_sub_cella_2cout; - wire [0:0] wire_add_sub_cella_3cout; - wire [0:0] wire_add_sub_cella_4cout; - wire [0:0] wire_add_sub_cella_5cout; - wire [0:0] wire_add_sub_cella_6cout; - wire [0:0] wire_add_sub_cella_7cout; - wire [0:0] wire_add_sub_cella_8cout; - wire [0:0] wire_add_sub_cella_9cout; - wire [0:0] wire_add_sub_cella_10cout; - wire [0:0] wire_add_sub_cella_11cout; - wire [0:0] wire_add_sub_cella_12cout; - wire [0:0] wire_add_sub_cella_13cout; - wire [0:0] wire_add_sub_cella_14cout; - wire [0:0] wire_add_sub_cella_15cout; - wire [0:0] wire_add_sub_cella_16cout; - wire [0:0] wire_add_sub_cella_17cout; - wire [0:0] wire_add_sub_cella_18cout; - wire [0:0] wire_add_sub_cella_19cout; - wire [0:0] wire_add_sub_cella_20cout; - wire [0:0] wire_add_sub_cella_21cout; - wire [0:0] wire_add_sub_cella_22cout; - wire [0:0] wire_add_sub_cella_23cout; - wire [0:0] wire_add_sub_cella_24cout; - wire [0:0] wire_add_sub_cella_25cout; - wire [0:0] wire_add_sub_cella_26cout; - wire [0:0] wire_add_sub_cella_27cout; - wire [0:0] wire_add_sub_cella_28cout; - wire [0:0] wire_add_sub_cella_29cout; - wire [0:0] wire_add_sub_cella_30cout; - wire [31:0] wire_add_sub_cella_dataa; - wire [31:0] wire_add_sub_cella_datab; - wire [31:0] wire_add_sub_cella_regout; - - stratix_lcell add_sub_cella_0 - ( - .aclr(aclr), - .cin(1'b1), - .clk(clock), - .cout(wire_add_sub_cella_0cout[0:0]), - .dataa(wire_add_sub_cella_dataa[0:0]), - .datab(wire_add_sub_cella_datab[0:0]), - .ena(clken), - .regout(wire_add_sub_cella_regout[0:0])); - defparam - add_sub_cella_0.cin_used = "true", - add_sub_cella_0.lut_mask = "69b2", - add_sub_cella_0.operation_mode = "arithmetic", - add_sub_cella_0.sum_lutc_input = "cin", - add_sub_cella_0.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_1 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_0cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_1cout[0:0]), - .dataa(wire_add_sub_cella_dataa[1:1]), - .datab(wire_add_sub_cella_datab[1:1]), - .ena(clken), - .regout(wire_add_sub_cella_regout[1:1])); - defparam - add_sub_cella_1.cin_used = "true", - add_sub_cella_1.lut_mask = "69b2", - add_sub_cella_1.operation_mode = "arithmetic", - add_sub_cella_1.sum_lutc_input = "cin", - add_sub_cella_1.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_2 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_1cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_2cout[0:0]), - .dataa(wire_add_sub_cella_dataa[2:2]), - .datab(wire_add_sub_cella_datab[2:2]), - .ena(clken), - .regout(wire_add_sub_cella_regout[2:2])); - defparam - add_sub_cella_2.cin_used = "true", - add_sub_cella_2.lut_mask = "69b2", - add_sub_cella_2.operation_mode = "arithmetic", - add_sub_cella_2.sum_lutc_input = "cin", - add_sub_cella_2.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_3 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_2cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_3cout[0:0]), - .dataa(wire_add_sub_cella_dataa[3:3]), - .datab(wire_add_sub_cella_datab[3:3]), - .ena(clken), - .regout(wire_add_sub_cella_regout[3:3])); - defparam - add_sub_cella_3.cin_used = "true", - add_sub_cella_3.lut_mask = "69b2", - add_sub_cella_3.operation_mode = "arithmetic", - add_sub_cella_3.sum_lutc_input = "cin", - add_sub_cella_3.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_4 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_3cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_4cout[0:0]), - .dataa(wire_add_sub_cella_dataa[4:4]), - .datab(wire_add_sub_cella_datab[4:4]), - .ena(clken), - .regout(wire_add_sub_cella_regout[4:4])); - defparam - add_sub_cella_4.cin_used = "true", - add_sub_cella_4.lut_mask = "69b2", - add_sub_cella_4.operation_mode = "arithmetic", - add_sub_cella_4.sum_lutc_input = "cin", - add_sub_cella_4.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_5 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_4cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_5cout[0:0]), - .dataa(wire_add_sub_cella_dataa[5:5]), - .datab(wire_add_sub_cella_datab[5:5]), - .ena(clken), - .regout(wire_add_sub_cella_regout[5:5])); - defparam - add_sub_cella_5.cin_used = "true", - add_sub_cella_5.lut_mask = "69b2", - add_sub_cella_5.operation_mode = "arithmetic", - add_sub_cella_5.sum_lutc_input = "cin", - add_sub_cella_5.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_6 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_5cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_6cout[0:0]), - .dataa(wire_add_sub_cella_dataa[6:6]), - .datab(wire_add_sub_cella_datab[6:6]), - .ena(clken), - .regout(wire_add_sub_cella_regout[6:6])); - defparam - add_sub_cella_6.cin_used = "true", - add_sub_cella_6.lut_mask = "69b2", - add_sub_cella_6.operation_mode = "arithmetic", - add_sub_cella_6.sum_lutc_input = "cin", - add_sub_cella_6.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_7 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_6cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_7cout[0:0]), - .dataa(wire_add_sub_cella_dataa[7:7]), - .datab(wire_add_sub_cella_datab[7:7]), - .ena(clken), - .regout(wire_add_sub_cella_regout[7:7])); - defparam - add_sub_cella_7.cin_used = "true", - add_sub_cella_7.lut_mask = "69b2", - add_sub_cella_7.operation_mode = "arithmetic", - add_sub_cella_7.sum_lutc_input = "cin", - add_sub_cella_7.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_8 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_7cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_8cout[0:0]), - .dataa(wire_add_sub_cella_dataa[8:8]), - .datab(wire_add_sub_cella_datab[8:8]), - .ena(clken), - .regout(wire_add_sub_cella_regout[8:8])); - defparam - add_sub_cella_8.cin_used = "true", - add_sub_cella_8.lut_mask = "69b2", - add_sub_cella_8.operation_mode = "arithmetic", - add_sub_cella_8.sum_lutc_input = "cin", - add_sub_cella_8.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_9 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_8cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_9cout[0:0]), - .dataa(wire_add_sub_cella_dataa[9:9]), - .datab(wire_add_sub_cella_datab[9:9]), - .ena(clken), - .regout(wire_add_sub_cella_regout[9:9])); - defparam - add_sub_cella_9.cin_used = "true", - add_sub_cella_9.lut_mask = "69b2", - add_sub_cella_9.operation_mode = "arithmetic", - add_sub_cella_9.sum_lutc_input = "cin", - add_sub_cella_9.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_10 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_9cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_10cout[0:0]), - .dataa(wire_add_sub_cella_dataa[10:10]), - .datab(wire_add_sub_cella_datab[10:10]), - .ena(clken), - .regout(wire_add_sub_cella_regout[10:10])); - defparam - add_sub_cella_10.cin_used = "true", - add_sub_cella_10.lut_mask = "69b2", - add_sub_cella_10.operation_mode = "arithmetic", - add_sub_cella_10.sum_lutc_input = "cin", - add_sub_cella_10.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_11 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_10cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_11cout[0:0]), - .dataa(wire_add_sub_cella_dataa[11:11]), - .datab(wire_add_sub_cella_datab[11:11]), - .ena(clken), - .regout(wire_add_sub_cella_regout[11:11])); - defparam - add_sub_cella_11.cin_used = "true", - add_sub_cella_11.lut_mask = "69b2", - add_sub_cella_11.operation_mode = "arithmetic", - add_sub_cella_11.sum_lutc_input = "cin", - add_sub_cella_11.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_12 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_11cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_12cout[0:0]), - .dataa(wire_add_sub_cella_dataa[12:12]), - .datab(wire_add_sub_cella_datab[12:12]), - .ena(clken), - .regout(wire_add_sub_cella_regout[12:12])); - defparam - add_sub_cella_12.cin_used = "true", - add_sub_cella_12.lut_mask = "69b2", - add_sub_cella_12.operation_mode = "arithmetic", - add_sub_cella_12.sum_lutc_input = "cin", - add_sub_cella_12.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_13 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_12cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_13cout[0:0]), - .dataa(wire_add_sub_cella_dataa[13:13]), - .datab(wire_add_sub_cella_datab[13:13]), - .ena(clken), - .regout(wire_add_sub_cella_regout[13:13])); - defparam - add_sub_cella_13.cin_used = "true", - add_sub_cella_13.lut_mask = "69b2", - add_sub_cella_13.operation_mode = "arithmetic", - add_sub_cella_13.sum_lutc_input = "cin", - add_sub_cella_13.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_14 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_13cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_14cout[0:0]), - .dataa(wire_add_sub_cella_dataa[14:14]), - .datab(wire_add_sub_cella_datab[14:14]), - .ena(clken), - .regout(wire_add_sub_cella_regout[14:14])); - defparam - add_sub_cella_14.cin_used = "true", - add_sub_cella_14.lut_mask = "69b2", - add_sub_cella_14.operation_mode = "arithmetic", - add_sub_cella_14.sum_lutc_input = "cin", - add_sub_cella_14.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_15 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_14cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_15cout[0:0]), - .dataa(wire_add_sub_cella_dataa[15:15]), - .datab(wire_add_sub_cella_datab[15:15]), - .ena(clken), - .regout(wire_add_sub_cella_regout[15:15])); - defparam - add_sub_cella_15.cin_used = "true", - add_sub_cella_15.lut_mask = "69b2", - add_sub_cella_15.operation_mode = "arithmetic", - add_sub_cella_15.sum_lutc_input = "cin", - add_sub_cella_15.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_16 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_15cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_16cout[0:0]), - .dataa(wire_add_sub_cella_dataa[16:16]), - .datab(wire_add_sub_cella_datab[16:16]), - .ena(clken), - .regout(wire_add_sub_cella_regout[16:16])); - defparam - add_sub_cella_16.cin_used = "true", - add_sub_cella_16.lut_mask = "69b2", - add_sub_cella_16.operation_mode = "arithmetic", - add_sub_cella_16.sum_lutc_input = "cin", - add_sub_cella_16.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_17 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_16cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_17cout[0:0]), - .dataa(wire_add_sub_cella_dataa[17:17]), - .datab(wire_add_sub_cella_datab[17:17]), - .ena(clken), - .regout(wire_add_sub_cella_regout[17:17])); - defparam - add_sub_cella_17.cin_used = "true", - add_sub_cella_17.lut_mask = "69b2", - add_sub_cella_17.operation_mode = "arithmetic", - add_sub_cella_17.sum_lutc_input = "cin", - add_sub_cella_17.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_18 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_17cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_18cout[0:0]), - .dataa(wire_add_sub_cella_dataa[18:18]), - .datab(wire_add_sub_cella_datab[18:18]), - .ena(clken), - .regout(wire_add_sub_cella_regout[18:18])); - defparam - add_sub_cella_18.cin_used = "true", - add_sub_cella_18.lut_mask = "69b2", - add_sub_cella_18.operation_mode = "arithmetic", - add_sub_cella_18.sum_lutc_input = "cin", - add_sub_cella_18.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_19 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_18cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_19cout[0:0]), - .dataa(wire_add_sub_cella_dataa[19:19]), - .datab(wire_add_sub_cella_datab[19:19]), - .ena(clken), - .regout(wire_add_sub_cella_regout[19:19])); - defparam - add_sub_cella_19.cin_used = "true", - add_sub_cella_19.lut_mask = "69b2", - add_sub_cella_19.operation_mode = "arithmetic", - add_sub_cella_19.sum_lutc_input = "cin", - add_sub_cella_19.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_20 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_19cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_20cout[0:0]), - .dataa(wire_add_sub_cella_dataa[20:20]), - .datab(wire_add_sub_cella_datab[20:20]), - .ena(clken), - .regout(wire_add_sub_cella_regout[20:20])); - defparam - add_sub_cella_20.cin_used = "true", - add_sub_cella_20.lut_mask = "69b2", - add_sub_cella_20.operation_mode = "arithmetic", - add_sub_cella_20.sum_lutc_input = "cin", - add_sub_cella_20.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_21 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_20cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_21cout[0:0]), - .dataa(wire_add_sub_cella_dataa[21:21]), - .datab(wire_add_sub_cella_datab[21:21]), - .ena(clken), - .regout(wire_add_sub_cella_regout[21:21])); - defparam - add_sub_cella_21.cin_used = "true", - add_sub_cella_21.lut_mask = "69b2", - add_sub_cella_21.operation_mode = "arithmetic", - add_sub_cella_21.sum_lutc_input = "cin", - add_sub_cella_21.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_22 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_21cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_22cout[0:0]), - .dataa(wire_add_sub_cella_dataa[22:22]), - .datab(wire_add_sub_cella_datab[22:22]), - .ena(clken), - .regout(wire_add_sub_cella_regout[22:22])); - defparam - add_sub_cella_22.cin_used = "true", - add_sub_cella_22.lut_mask = "69b2", - add_sub_cella_22.operation_mode = "arithmetic", - add_sub_cella_22.sum_lutc_input = "cin", - add_sub_cella_22.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_23 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_22cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_23cout[0:0]), - .dataa(wire_add_sub_cella_dataa[23:23]), - .datab(wire_add_sub_cella_datab[23:23]), - .ena(clken), - .regout(wire_add_sub_cella_regout[23:23])); - defparam - add_sub_cella_23.cin_used = "true", - add_sub_cella_23.lut_mask = "69b2", - add_sub_cella_23.operation_mode = "arithmetic", - add_sub_cella_23.sum_lutc_input = "cin", - add_sub_cella_23.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_24 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_23cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_24cout[0:0]), - .dataa(wire_add_sub_cella_dataa[24:24]), - .datab(wire_add_sub_cella_datab[24:24]), - .ena(clken), - .regout(wire_add_sub_cella_regout[24:24])); - defparam - add_sub_cella_24.cin_used = "true", - add_sub_cella_24.lut_mask = "69b2", - add_sub_cella_24.operation_mode = "arithmetic", - add_sub_cella_24.sum_lutc_input = "cin", - add_sub_cella_24.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_25 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_24cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_25cout[0:0]), - .dataa(wire_add_sub_cella_dataa[25:25]), - .datab(wire_add_sub_cella_datab[25:25]), - .ena(clken), - .regout(wire_add_sub_cella_regout[25:25])); - defparam - add_sub_cella_25.cin_used = "true", - add_sub_cella_25.lut_mask = "69b2", - add_sub_cella_25.operation_mode = "arithmetic", - add_sub_cella_25.sum_lutc_input = "cin", - add_sub_cella_25.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_26 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_25cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_26cout[0:0]), - .dataa(wire_add_sub_cella_dataa[26:26]), - .datab(wire_add_sub_cella_datab[26:26]), - .ena(clken), - .regout(wire_add_sub_cella_regout[26:26])); - defparam - add_sub_cella_26.cin_used = "true", - add_sub_cella_26.lut_mask = "69b2", - add_sub_cella_26.operation_mode = "arithmetic", - add_sub_cella_26.sum_lutc_input = "cin", - add_sub_cella_26.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_27 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_26cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_27cout[0:0]), - .dataa(wire_add_sub_cella_dataa[27:27]), - .datab(wire_add_sub_cella_datab[27:27]), - .ena(clken), - .regout(wire_add_sub_cella_regout[27:27])); - defparam - add_sub_cella_27.cin_used = "true", - add_sub_cella_27.lut_mask = "69b2", - add_sub_cella_27.operation_mode = "arithmetic", - add_sub_cella_27.sum_lutc_input = "cin", - add_sub_cella_27.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_28 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_27cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_28cout[0:0]), - .dataa(wire_add_sub_cella_dataa[28:28]), - .datab(wire_add_sub_cella_datab[28:28]), - .ena(clken), - .regout(wire_add_sub_cella_regout[28:28])); - defparam - add_sub_cella_28.cin_used = "true", - add_sub_cella_28.lut_mask = "69b2", - add_sub_cella_28.operation_mode = "arithmetic", - add_sub_cella_28.sum_lutc_input = "cin", - add_sub_cella_28.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_29 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_28cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_29cout[0:0]), - .dataa(wire_add_sub_cella_dataa[29:29]), - .datab(wire_add_sub_cella_datab[29:29]), - .ena(clken), - .regout(wire_add_sub_cella_regout[29:29])); - defparam - add_sub_cella_29.cin_used = "true", - add_sub_cella_29.lut_mask = "69b2", - add_sub_cella_29.operation_mode = "arithmetic", - add_sub_cella_29.sum_lutc_input = "cin", - add_sub_cella_29.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_30 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_29cout[0:0]), - .clk(clock), - .cout(wire_add_sub_cella_30cout[0:0]), - .dataa(wire_add_sub_cella_dataa[30:30]), - .datab(wire_add_sub_cella_datab[30:30]), - .ena(clken), - .regout(wire_add_sub_cella_regout[30:30])); - defparam - add_sub_cella_30.cin_used = "true", - add_sub_cella_30.lut_mask = "69b2", - add_sub_cella_30.operation_mode = "arithmetic", - add_sub_cella_30.sum_lutc_input = "cin", - add_sub_cella_30.lpm_type = "stratix_lcell"; - stratix_lcell add_sub_cella_31 - ( - .aclr(aclr), - .cin(wire_add_sub_cella_30cout[0:0]), - .clk(clock), - .dataa(wire_add_sub_cella_dataa[31:31]), - .datab(wire_add_sub_cella_datab[31:31]), - .ena(clken), - .regout(wire_add_sub_cella_regout[31:31])); - defparam - add_sub_cella_31.cin_used = "true", - add_sub_cella_31.lut_mask = "6969", - add_sub_cella_31.operation_mode = "normal", - add_sub_cella_31.sum_lutc_input = "cin", - add_sub_cella_31.lpm_type = "stratix_lcell"; - assign - wire_add_sub_cella_dataa = dataa, - wire_add_sub_cella_datab = datab; - assign - result = wire_add_sub_cella_regout; -endmodule //sub32_add_sub_cqa -//VALID FILE - - -module sub32 ( - dataa, - datab, - clock, - aclr, - clken, - result)/* synthesis synthesis_clearbox = 1 */; - - input [31:0] dataa; - input [31:0] datab; - input clock; - input aclr; - input clken; - output [31:0] result; - - wire [31:0] sub_wire0; - wire [31:0] result = sub_wire0[31:0]; - - sub32_add_sub_cqa sub32_add_sub_cqa_component ( - .dataa (dataa), - .datab (datab), - .clken (clken), - .aclr (aclr), - .clock (clock), - .result (sub_wire0)); - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: nBit NUMERIC "32" -// Retrieval info: PRIVATE: Function NUMERIC "1" -// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" -// Retrieval info: PRIVATE: ConstantA NUMERIC "0" -// Retrieval info: PRIVATE: ConstantB NUMERIC "0" -// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" -// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" -// Retrieval info: PRIVATE: CarryIn NUMERIC "0" -// Retrieval info: PRIVATE: CarryOut NUMERIC "0" -// Retrieval info: PRIVATE: Overflow NUMERIC "0" -// Retrieval info: PRIVATE: Latency NUMERIC "1" -// Retrieval info: PRIVATE: aclr NUMERIC "1" -// Retrieval info: PRIVATE: clken NUMERIC "1" -// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" -// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB" -// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" -// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" -// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] -// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0] -// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0] -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken -// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 -// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0 -// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 -// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/megacells/sub32_bb.v b/megacells/sub32_bb.v deleted file mode 100755 index 488ab51cf..000000000 --- a/megacells/sub32_bb.v +++ /dev/null @@ -1,37 +0,0 @@ -//Copyright (C) 1991-2003 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module sub32 ( - dataa, - datab, - clock, - aclr, - clken, - result)/* synthesis synthesis_clearbox = 1 */; - - input [31:0] dataa; - input [31:0] datab; - input clock; - input aclr; - input clken; - output [31:0] result; - -endmodule - diff --git a/megacells/sub32_inst.v b/megacells/sub32_inst.v deleted file mode 100755 index 1916fc524..000000000 --- a/megacells/sub32_inst.v +++ /dev/null @@ -1,8 +0,0 @@ -sub32 sub32_inst ( - .dataa ( dataa_sig ), - .datab ( datab_sig ), - .clock ( clock_sig ), - .aclr ( aclr_sig ), - .clken ( clken_sig ), - .result ( result_sig ) - ); diff --git a/models/bustri.v b/models/bustri.v deleted file mode 100644 index 6e5a0f74c..000000000 --- a/models/bustri.v +++ /dev/null @@ -1,17 +0,0 @@ - -// Model for tristate bus on altera -// FIXME do we really need to use a megacell for this? - -module bustri (data, - enabledt, - tridata); - - input [15:0] data; - input enabledt; - inout [15:0] tridata; - - assign tridata = enabledt ? data :16'bz; - -endmodule // bustri - - diff --git a/models/fifo.v b/models/fifo.v deleted file mode 100644 index 0ade49e9c..000000000 --- a/models/fifo.v +++ /dev/null @@ -1,82 +0,0 @@ -// Model of FIFO in Altera - -module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q, - rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); - - parameter width = 16; - parameter depth = 1024; - parameter addr_bits = 10; - - //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req - - input [width-1:0] data; - input wrreq; - input rdreq; - input rdclk; - input wrclk; - input aclr; - output [width-1:0] q; - output rdfull; - output rdempty; - output reg [addr_bits-1:0] rdusedw; - output wrfull; - output wrempty; - output reg [addr_bits-1:0] wrusedw; - - reg [width-1:0] mem [0:depth-1]; - reg [addr_bits-1:0] rdptr; - reg [addr_bits-1:0] wrptr; - -`ifdef rd_req - reg [width-1:0] q; -`else - wire [width-1:0] q; -`endif - - integer i; - - always @( aclr) - begin - wrptr <= #1 0; - rdptr <= #1 0; - for(i=0;i=0;i=i-1) - bin_val[i] = bin_val[i+1] ^ gray_val[i]; - end -endmodule // gray2bin diff --git a/sdr_lib/gen_cordic_consts.py b/sdr_lib/gen_cordic_consts.py deleted file mode 100755 index ab66cfe01..000000000 --- a/sdr_lib/gen_cordic_consts.py +++ /dev/null @@ -1,10 +0,0 @@ -#!/usr/bin/env python - -import math - -zwidth = 16 - -for i in range(17): - c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth) - print "`define c%02d %d'd%d" % (i, zwidth, round (c)) - diff --git a/sdr_lib/gen_sync.v b/sdr_lib/gen_sync.v deleted file mode 100644 index d6efdba98..000000000 --- a/sdr_lib/gen_sync.v +++ /dev/null @@ -1,43 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module gen_sync - ( input clock, - input reset, - input enable, - input [7:0] rate, - output wire sync ); - -// parameter width = 8; - - reg [7:0] counter; - assign sync = |(((rate+1)>>1)& counter); - - always @(posedge clock) - if(reset || ~enable) - counter <= #1 0; - else if(counter == rate) - counter <= #1 0; - else - counter <= #1 counter + 8'd1; - -endmodule // gen_sync - diff --git a/sdr_lib/hb/acc.v b/sdr_lib/hb/acc.v deleted file mode 100644 index 195d5ea94..000000000 --- a/sdr_lib/hb/acc.v +++ /dev/null @@ -1,22 +0,0 @@ - - -module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, - input signed [30:0] addend, output reg signed [33:0] sum ); - - always @(posedge clock) - if(reset) - sum <= #1 34'd0; - //else if(clear & enable_in) - // sum <= #1 addend; - //else if(clear) - // sum <= #1 34'd0; - else if(clear) - sum <= #1 addend; - else if(enable_in) - sum <= #1 sum + addend; - - always @(posedge clock) - enable_out <= #1 enable_in; - -endmodule // acc - diff --git a/sdr_lib/hb/coeff_rom.v b/sdr_lib/hb/coeff_rom.v deleted file mode 100644 index 7f8886b4e..000000000 --- a/sdr_lib/hb/coeff_rom.v +++ /dev/null @@ -1,19 +0,0 @@ - - -module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); - - always @(posedge clock) - case (addr) - 3'd0 : data <= #1 -16'd49; - 3'd1 : data <= #1 16'd165; - 3'd2 : data <= #1 -16'd412; - 3'd3 : data <= #1 16'd873; - 3'd4 : data <= #1 -16'd1681; - 3'd5 : data <= #1 16'd3135; - 3'd6 : data <= #1 -16'd6282; - 3'd7 : data <= #1 16'd20628; - endcase // case(addr) - -endmodule // coeff_rom - - diff --git a/sdr_lib/hb/halfband_decim.v b/sdr_lib/hb/halfband_decim.v deleted file mode 100644 index dff4d902c..000000000 --- a/sdr_lib/hb/halfband_decim.v +++ /dev/null @@ -1,163 +0,0 @@ -/* -*- verilog -*- - * - * USRP - Universal Software Radio Peripheral - * - * Copyright (C) 2005 Matt Ettus - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA - */ - -/* - * This implements a 31-tap halfband filter that decimates by two. - * The coefficients are symmetric, and with the exception of the middle tap, - * every other coefficient is zero. The middle section of taps looks like this: - * - * ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ... - * | - * middle tap -------+ - * - * See coeff_rom.v for the full set. The taps are scaled relative to 32768, - * thus the middle tap equals 1.0. Not counting the middle tap, there are 8 - * non-zero taps on each side, and they are symmetric. A naive implementation - * requires a mulitply for each non-zero tap. Because of symmetry, we can - * replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output - * sample, we need to perform 8 multiplications. Since the middle tap is 1.0, - * we just add the corresponding delay line value. - * - * About timing: We implement this with a single multiplier, so it takes - * 8 cycles to compute a single output. However, since we're decimating by two - * we can accept a new input value every 4 cycles. strobe_in is asserted when - * there's a new input sample available. Depending on the overall decimation - * rate, strobe_in may be asserted less frequently than once every 4 clocks. - * On the output side, we assert strobe_out when output contains a new sample. - * - * Implementation: Every time strobe_in is asserted we store the new data into - * the delay line. We split the delay line into two components, one for the - * even samples, and one for the odd samples. ram16_odd is the delay line for - * the odd samples. This ram is written on each odd assertion of strobe_in, and - * is read on each clock when we're computing the dot product. ram16_even is - * similar, although because it holds the even samples we must be able to read - * two samples from different addresses at the same time, while writing the incoming - * even samples. Thus it's "triple-ported". - */ - -module halfband_decim - (input clock, input reset, input enable, input strobe_in, output wire strobe_out, - input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl); - - reg [3:0] rd_addr1; - reg [3:0] rd_addr2; - reg [3:0] phase; - reg [3:0] base_addr; - - wire signed [15:0] mac_out,middle_data, sum, coeff; - wire signed [30:0] product; - wire signed [33:0] sum_even; - wire clear; - reg store_odd; - - always @(posedge clock) - if(reset) - store_odd <= #1 1'b0; - else - if(strobe_in) - store_odd <= #1 ~store_odd; - - wire start = strobe_in & store_odd; - always @(posedge clock) - if(reset) - base_addr <= #1 4'd0; - else if(start) - base_addr <= #1 base_addr + 4'd1; - - always @(posedge clock) - if(reset) - phase <= #1 4'd8; - else if (start) - phase <= #1 4'd0; - else if(phase != 4'd8) - phase <= #1 phase + 4'd1; - - reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD; - always @(posedge clock) - begin - start_d1 <= #1 start; - start_d2 <= #1 start_d1; - start_d3 <= #1 start_d2; - start_d4 <= #1 start_d3; - start_d5 <= #1 start_d4; - start_d6 <= #1 start_d5; - start_d7 <= #1 start_d6; - start_d8 <= #1 start_d7; - start_d9 <= #1 start_d8; - start_dA <= #1 start_d9; - start_dB <= #1 start_dA; - start_dC <= #1 start_dB; - start_dD <= #1 start_dC; - end // always @ (posedge clock) - - reg mult_en, mult_en_pre; - always @(posedge clock) - begin - mult_en_pre <= #1 phase!=8; - mult_en <= #1 mult_en_pre; - end - - assign clear = start_d4; // was dC - wire latch_result = start_d4; // was dC - assign strobe_out = start_d5; // was dD - wire acc_en; - - always @* - case(phase[2:0]) - 3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end - 3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end - 3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end - 3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end - 3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end - 3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end - 3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end - 3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end - default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end - endcase // case(phase) - - coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff)); - - ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), - .wr_addr(base_addr),.wr_data(data_in), - .rd_addr1(rd_addr1),.rd_addr2(rd_addr2), - .sum(sum)); - - ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items - .wr_addr(base_addr),.wr_data(data_in), - //.rd_addr(base_addr+4'd7),.rd_data(middle_data)); - .rd_addr(base_addr+4'd6),.rd_data(middle_data)); - - mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en)); - - acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(), - .clear(clear),.addend(product),.sum(sum_even)); - - wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!! - - always @(posedge clock) - if(reset) - data_out <= #1 16'd0; - else if(latch_result) - data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]); - - assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase}; - -endmodule // halfband_decim diff --git a/sdr_lib/hb/halfband_interp.v b/sdr_lib/hb/halfband_interp.v deleted file mode 100644 index cdb11c1f6..000000000 --- a/sdr_lib/hb/halfband_interp.v +++ /dev/null @@ -1,121 +0,0 @@ - - -module halfband_interp - (input clock, input reset, input enable, - input strobe_in, input strobe_out, - input [15:0] signal_in_i, input [15:0] signal_in_q, - output reg [15:0] signal_out_i, output reg [15:0] signal_out_q, - output wire [12:0] debug); - - wire [15:0] coeff_ram_out; - wire [15:0] data_ram_out_i; - wire [15:0] data_ram_out_q; - - wire [3:0] data_rd_addr; - reg [3:0] data_wr_addr; - reg [2:0] coeff_rd_addr; - - wire filt_done; - - wire [15:0] mac_out_i; - wire [15:0] mac_out_q; - reg [15:0] delayed_middle_i, delayed_middle_q; - wire [7:0] shift = 8'd9; - - reg stb_out_happened; - - wire [15:0] data_ram_out_i_b; - - always @(posedge clock) - if(strobe_in) - stb_out_happened <= #1 1'b0; - else if(strobe_out) - stb_out_happened <= #1 1'b1; - -assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr}; - - wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i; - wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q; - -/* always @(posedge clock) - if(reset) - begin - signal_out_i <= #1 16'd0; - signal_out_q <= #1 16'd0; - end - else if(strobe_in) - begin - signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff - signal_out_q <= #1 delayed_middle_q; - end - //else if(filt_done&stb_out_happened) - else if(stb_out_happened) - begin - signal_out_i <= #1 mac_out_i; - signal_out_q <= #1 mac_out_q; - end -*/ - - always @(posedge clock) - if(reset) - coeff_rd_addr <= #1 3'd0; - else if(coeff_rd_addr != 3'd0) - coeff_rd_addr <= #1 coeff_rd_addr + 3'd1; - else if(strobe_in) - coeff_rd_addr <= #1 3'd1; - - reg filt_done_d1; - always@(posedge clock) - filt_done_d1 <= #1 filt_done; - - always @(posedge clock) - if(reset) - data_wr_addr <= #1 4'd0; - //else if(strobe_in) - else if(filt_done & ~filt_done_d1) - data_wr_addr <= #1 data_wr_addr + 4'd1; - - always @(posedge clock) - if(coeff_rd_addr == 3'd7) - begin - delayed_middle_i <= #1 data_ram_out_i_b; - // delayed_middle_q <= #1 data_ram_out_q_b; - end - -// always @(posedge clock) -// if(reset) -// data_rd_addr <= #1 4'd0; -// else if(strobe_in) -// data_rd_addr <= #1 data_wr_addr + 4'd1; -// else if(!filt_done) -// data_rd_addr <= #1 data_rd_addr + 4'd1; -// else -// data_rd_addr <= #1 data_wr_addr; - - wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr}; - wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr}; -// always @(posedge clock) -// if(reset) -// filt_done <= #1 1'b1; -// else if(strobe_in) - // filt_done <= #1 1'b0; -// else if(coeff_rd_addr == 4'd0) -// filt_done <= #1 1'b1; - - assign filt_done = (coeff_rd_addr == 3'd0); - - coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) ); - - ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i), - .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i)); - - ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q), - .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q)); - - mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), - .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) ); - - mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), - .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) ); - -endmodule // halfband_interp diff --git a/sdr_lib/hb/hbd_tb/HBD b/sdr_lib/hb/hbd_tb/HBD deleted file mode 100644 index 574fbba91..000000000 --- a/sdr_lib/hb/hbd_tb/HBD +++ /dev/null @@ -1,80 +0,0 @@ -*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -test_hbd.clock -test_hbd.reset -@420 -test_hbd.halfband_decim.middle_data[15:0] -@22 -test_hbd.halfband_decim.sum_even[33:0] -test_hbd.halfband_decim.base_addr[3:0] -@420 -test_hbd.i_in[15:0] -@24 -test_hbd.halfband_decim.phase[3:0] -test_hbd.halfband_decim.ram16_even.rd_addr1[3:0] -test_hbd.halfband_decim.ram16_even.rd_addr2[3:0] -test_hbd.halfband_decim.ram16_even.wr_addr[3:0] -test_hbd.halfband_decim.ram16_even.wr_data[15:0] -@28 -test_hbd.halfband_decim.ram16_even.write -@420 -test_hbd.halfband_decim.sum[15:0] -test_hbd.halfband_decim.product[30:0] -test_hbd.halfband_decim.dout[33:0] -test_hbd.halfband_decim.sum_even[33:0] -@22 -test_hbd.halfband_decim.acc.addend[30:0] -@28 -test_hbd.halfband_decim.acc.reset -@420 -test_hbd.halfband_decim.acc.sum[33:0] -test_hbd.halfband_decim.mult.x[15:0] -test_hbd.halfband_decim.mult.y[15:0] -@28 -test_hbd.halfband_decim.acc.clear -test_hbd.strobe_in -test_hbd.strobe_out -test_hbd.halfband_decim.acc_en -@420 -test_hbd.i_out[15:0] -@28 -test_hbd.halfband_decim.mult_en -test_hbd.halfband_decim.latch_result -@420 -test_hbd.halfband_decim.sum[15:0] -test_hbd.halfband_decim.sum_even[33:0] -test_hbd.halfband_decim.dout[33:0] -test_hbd.halfband_decim.data_out[15:0] -@22 -test_hbd.halfband_decim.data_out[15:0] -@28 -test_hbd.halfband_decim.dout[33:0] -@29 -test_hbd.halfband_decim.acc_en -@22 -test_hbd.halfband_decim.base_addr[3:0] -@28 -test_hbd.halfband_decim.clear -test_hbd.halfband_decim.latch_result -test_hbd.halfband_decim.mult_en -test_hbd.halfband_decim.mult_en_pre -@22 -test_hbd.halfband_decim.phase[3:0] -@28 -test_hbd.halfband_decim.start -test_hbd.halfband_decim.start_d1 -test_hbd.halfband_decim.start_d2 -test_hbd.halfband_decim.start_d3 -test_hbd.halfband_decim.start_d4 -test_hbd.halfband_decim.start_d5 -test_hbd.halfband_decim.start_d6 -test_hbd.halfband_decim.start_d7 -test_hbd.halfband_decim.start_d8 -test_hbd.halfband_decim.start_d9 -test_hbd.halfband_decim.start_dA -test_hbd.halfband_decim.start_dB -test_hbd.halfband_decim.start_dC -test_hbd.halfband_decim.start_dD -test_hbd.halfband_decim.store_odd -test_hbd.halfband_decim.strobe_in -test_hbd.halfband_decim.strobe_out diff --git a/sdr_lib/hb/hbd_tb/really_golden b/sdr_lib/hb/hbd_tb/really_golden deleted file mode 100644 index 2d24a9e14..000000000 --- a/sdr_lib/hb/hbd_tb/really_golden +++ /dev/null @@ -1,142 +0,0 @@ -VCD info: dumpfile test_hbd.vcd opened for output. - x - x - x - x - x - x - x - x - x - x - x - x - x - x - x - x - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8192 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 -- 4 - 18 -- 63 - 167 -- 367 - 737 -- 1539 - 5146 - 5146 -- 1539 - 737 -- 367 - 167 -- 63 - 18 -- 4 - 0 - 0 - 0 - 0 - 0 -- 4 - 14 -- 49 - 118 -- 249 - 488 - 7141 -12287 -17433 -15894 -16631 -16264 -16432 -16368 -16387 -16383 -16383 -16383 -16383 -16383 -16387 -16368 -16432 -16264 -16631 -15894 - 9241 - 4095 -- 1051 - 488 -- 249 - 118 -- 49 - 14 -- 4 - 0 - 0 - 0 - 0 - 0 -- 4 - 14 -- 49 - 118 -- 249 - 488 -- 1051 -12287 -17433 -15894 -16631 -16264 -16432 -16368 -16387 -16383 -16383 -16383 -16383 -16383 -16387 -16368 -16432 -16264 -16631 -15894 -17433 - 4095 -- 1051 - 488 -- 249 - 118 -- 49 - 14 -- 4 - 0 - 0 - 0 - 0 diff --git a/sdr_lib/hb/hbd_tb/regression b/sdr_lib/hb/hbd_tb/regression deleted file mode 100644 index fc279c2f2..000000000 --- a/sdr_lib/hb/hbd_tb/regression +++ /dev/null @@ -1,95 +0,0 @@ -echo "Baseline 1000" -iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden -diff golden really_golden - -echo -echo "Test 100" -iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 50" -iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 40" -iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 30" -iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 25" -iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 20" -iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 19" -iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 18" -iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 17" -iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 16" -iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 15" -iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 14" -iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 13" -iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 12" -iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 11" -iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 10" -iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 9" -iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 8" -iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 7" -iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 6" -iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 5" -iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 4" -iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 3" -iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden diff --git a/sdr_lib/hb/hbd_tb/run_hbd b/sdr_lib/hb/hbd_tb/run_hbd deleted file mode 100755 index b8aec7574..000000000 --- a/sdr_lib/hb/hbd_tb/run_hbd +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -iverilog -y .. -o test_hbd test_hbd.v -./test_hbd diff --git a/sdr_lib/hb/hbd_tb/test_hbd.v b/sdr_lib/hb/hbd_tb/test_hbd.v deleted file mode 100644 index 01ab5e7e0..000000000 --- a/sdr_lib/hb/hbd_tb/test_hbd.v +++ /dev/null @@ -1,75 +0,0 @@ - - -module test_hbd(); - - reg clock; - initial clock = 1'b0; - always #5 clock <= ~clock; - - reg reset; - initial reset = 1'b1; - initial #1000 reset = 1'b0; - - initial $dumpfile("test_hbd.vcd"); - initial $dumpvars(0,test_hbd); - - reg [15:0] i_in, q_in; - wire [15:0] i_out, q_out; - - reg strobe_in; - wire strobe_out; - reg coeff_write; - reg [15:0] coeff_data; - reg [4:0] coeff_addr; - - halfband_decim halfband_decim - ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), - .data_in(i_in),.data_out(i_out) ); - - always @(posedge strobe_out) - if(i_out[15]) - $display("-%d",65536-i_out); - else - $display("%d",i_out); - - initial - begin - strobe_in = 1'b0; - @(negedge reset); - @(posedge clock); - while(1) - begin - strobe_in <= #1 1'b1; - @(posedge clock); - strobe_in <= #1 1'b0; - repeat (`RATE) - @(posedge clock); - end - end - - initial #10000000 $finish; // Just in case... - - initial - begin - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (41) @(posedge strobe_in); - i_in <= #1 16'd16384; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - repeat (7) @(posedge clock); - $finish; - end // initial begin -endmodule // test_hb diff --git a/sdr_lib/hb/mac.v b/sdr_lib/hb/mac.v deleted file mode 100644 index 5a270bc73..000000000 --- a/sdr_lib/hb/mac.v +++ /dev/null @@ -1,58 +0,0 @@ - - -module mac (input clock, input reset, input enable, input clear, - input signed [15:0] x, input signed [15:0] y, - input [7:0] shift, output [15:0] z ); - - reg signed [30:0] product; - reg signed [39:0] z_int; - reg signed [15:0] z_shift; - - reg enable_d1; - always @(posedge clock) - enable_d1 <= #1 enable; - - always @(posedge clock) - if(reset | clear) - z_int <= #1 40'd0; - else if(enable_d1) - z_int <= #1 z_int + {{9{product[30]}},product}; - - always @(posedge clock) - product <= #1 x*y; - - always @* // FIXME full case? parallel case? - case(shift) - //8'd0 : z_shift <= z_int[39:24]; - //8'd1 : z_shift <= z_int[38:23]; - //8'd2 : z_shift <= z_int[37:22]; - //8'd3 : z_shift <= z_int[36:21]; - //8'd4 : z_shift <= z_int[35:20]; - //8'd5 : z_shift <= z_int[34:19]; - 8'd6 : z_shift <= z_int[33:18]; - 8'd7 : z_shift <= z_int[32:17]; - 8'd8 : z_shift <= z_int[31:16]; - 8'd9 : z_shift <= z_int[30:15]; - 8'd10 : z_shift <= z_int[29:14]; - 8'd11 : z_shift <= z_int[28:13]; - //8'd12 : z_shift <= z_int[27:12]; - //8'd13 : z_shift <= z_int[26:11]; - //8'd14 : z_shift <= z_int[25:10]; - //8'd15 : z_shift <= z_int[24:9]; - //8'd16 : z_shift <= z_int[23:8]; - //8'd17 : z_shift <= z_int[22:7]; - //8'd18 : z_shift <= z_int[21:6]; - //8'd19 : z_shift <= z_int[20:5]; - //8'd20 : z_shift <= z_int[19:4]; - //8'd21 : z_shift <= z_int[18:3]; - //8'd22 : z_shift <= z_int[17:2]; - //8'd23 : z_shift <= z_int[16:1]; - //8'd24 : z_shift <= z_int[15:0]; - default : z_shift <= z_int[15:0]; - endcase // case(shift) - - // FIXME do we need to saturate? - //assign z = z_shift; - assign z = z_int[15:0]; - -endmodule // mac diff --git a/sdr_lib/hb/mult.v b/sdr_lib/hb/mult.v deleted file mode 100644 index a8d4cb1b7..000000000 --- a/sdr_lib/hb/mult.v +++ /dev/null @@ -1,16 +0,0 @@ - - -module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, - input enable_in, output reg enable_out ); - - always @(posedge clock) - if(enable_in) - product <= #1 x*y; - else - product <= #1 31'd0; - - always @(posedge clock) - enable_out <= #1 enable_in; - -endmodule // mult - diff --git a/sdr_lib/hb/ram16_2port.v b/sdr_lib/hb/ram16_2port.v deleted file mode 100644 index e1761a926..000000000 --- a/sdr_lib/hb/ram16_2port.v +++ /dev/null @@ -1,22 +0,0 @@ - - -module ram16_2port (input clock, input write, - input [3:0] wr_addr, input [15:0] wr_data, - input [3:0] rd_addr1, output reg [15:0] rd_data1, - input [3:0] rd_addr2, output reg [15:0] rd_data2); - - reg [15:0] ram_array [0:31]; - - always @(posedge clock) - rd_data1 <= #1 ram_array[rd_addr1]; - - always @(posedge clock) - rd_data2 <= #1 ram_array[rd_addr2]; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - -endmodule // ram16_2port - - diff --git a/sdr_lib/hb/ram16_2sum.v b/sdr_lib/hb/ram16_2sum.v deleted file mode 100644 index 559b06fd5..000000000 --- a/sdr_lib/hb/ram16_2sum.v +++ /dev/null @@ -1,27 +0,0 @@ - - -module ram16_2sum (input clock, input write, - input [3:0] wr_addr, input [15:0] wr_data, - input [3:0] rd_addr1, input [3:0] rd_addr2, - output reg [15:0] sum); - - reg signed [15:0] ram_array [0:15]; - reg signed [15:0] a,b; - wire signed [16:0] sum_int; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - - always @(posedge clock) - begin - a <= #1 ram_array[rd_addr1]; - b <= #1 ram_array[rd_addr2]; - end - - assign sum_int = {a[15],a} + {b[15],b}; - - always @(posedge clock) - sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); - -endmodule // ram16_2sum diff --git a/sdr_lib/hb/ram32_2sum.v b/sdr_lib/hb/ram32_2sum.v deleted file mode 100644 index d1f55b7d0..000000000 --- a/sdr_lib/hb/ram32_2sum.v +++ /dev/null @@ -1,22 +0,0 @@ - - -module ram32_2sum (input clock, input write, - input [4:0] wr_addr, input [15:0] wr_data, - input [4:0] rd_addr1, input [4:0] rd_addr2, - output reg [15:0] sum); - - reg [15:0] ram_array [0:31]; - wire [16:0] sum_int; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - - assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; - - always @(posedge clock) - sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); - - -endmodule // ram32_2sum - diff --git a/sdr_lib/io_pins.v b/sdr_lib/io_pins.v deleted file mode 100644 index ad1b7b4a8..000000000 --- a/sdr_lib/io_pins.v +++ /dev/null @@ -1,52 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2005,2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../firmware/include/fpga_regs_common.v" -`include "../../firmware/include/fpga_regs_standard.v" - -module io_pins - ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3, - input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3, - input clock, input rx_reset, input tx_reset, - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe); - - reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe; - - bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0)); - bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1)); - bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe),.reg_val(reg_2)); - bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe),.reg_val(reg_3)); - - // Upper 16 bits are mask for lower 16 - always @(posedge clock) - if(serial_strobe) - case(serial_addr) - `FR_OE_0 : io_0_oe - <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_1 : io_1_oe - <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_2 : io_2_oe - <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_3 : io_3_oe - <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - endcase // case(serial_addr) - -endmodule // io_pins diff --git a/sdr_lib/master_control.v b/sdr_lib/master_control.v deleted file mode 100644 index 3bce55f23..000000000 --- a/sdr_lib/master_control.v +++ /dev/null @@ -1,163 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2005 Matt Ettus -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Clock, enable, and reset controls for whole system - -module master_control - ( input master_clk, input usbclk, - input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe, - output tx_bus_reset, output rx_bus_reset, - output wire tx_dsp_reset, output wire rx_dsp_reset, - output wire enable_tx, output wire enable_rx, - output wire [7:0] interp_rate, output wire [7:0] decim_rate, - output tx_sample_strobe, output strobe_interp, - output rx_sample_strobe, output strobe_decim, - input tx_empty, - input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3, - output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3 - ); - - // FIXME need a separate reset for all control settings - // Master Controls assignments - wire [7:0] master_controls; - setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls)); - assign enable_tx = master_controls[0]; - assign enable_rx = master_controls[1]; - assign tx_dsp_reset = master_controls[2]; - assign rx_dsp_reset = master_controls[3]; - // Unused - 4-7 - - // Strobe Generators - setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate)); - setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate)); - - strobe_gen da_strobe_gen - ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx), - .rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) ); - - strobe_gen tx_strobe_gen - ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx), - .rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) ); - - assign rx_sample_strobe = 1'b1; - - strobe_gen decim_strobe_gen - ( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx), - .rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) ); - - // Reset syncs for bus (usbclk) side - // The RX bus side reset isn't used, the TX bus side one may not be needed - reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2; - - always @(posedge usbclk) - begin - tx_reset_bus_sync1 <= #1 tx_dsp_reset; - rx_reset_bus_sync1 <= #1 rx_dsp_reset; - tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1; - rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1; - end - - assign tx_bus_reset = tx_reset_bus_sync2; - assign rx_bus_reset = rx_reset_bus_sync2; - - wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk; - wire txaclk,txbclk,rxaclk,rxbclk; - wire [3:0] debug_en, txcvr_ctrl; - - wire [31:0] txcvr_rxlines, txcvr_txlines; - - setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk)); - setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk)); - setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk)); - setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk)); - - setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en)); - - clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0])); - clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0])); - clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0])); - clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0])); - - reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg; - // Upper 16 bits are mask for lower 16 - always @(posedge master_clk) - if(serial_strobe) - case(serial_addr) - `FR_IO_0 : io_0_reg - <= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_IO_1 : io_1_reg - <= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_IO_2 : io_2_reg - <= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_IO_3 : io_3_reg - <= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - endcase // case(serial_addr) - - wire transmit_now; - wire atr_ctl; - wire [11:0] atr_tx_delay, atr_rx_delay; - wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3; - - setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0)); - setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0)); - setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0)); - - setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1)); - setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1)); - setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1)); - - setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2)); - setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2)); - setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2)); - - setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3)); - setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3)); - setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3)); - - //setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl)); - setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay)); - setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay)); - - assign atr_ctl = 1'b1; - - atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty), - .tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now)); - - wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0; - wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg); - - wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1; - wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg); - - wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2; - wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg); - - wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3; - wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg); - - assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0; - assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1; - assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2; - assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3; - - -endmodule // master_control diff --git a/sdr_lib/master_control_multi.v b/sdr_lib/master_control_multi.v deleted file mode 100644 index cab96a79f..000000000 --- a/sdr_lib/master_control_multi.v +++ /dev/null @@ -1,73 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -`include "config.vh" -`include "../../../firmware/include/fpga_regs_common.v" -`include "../../../firmware/include/fpga_regs_standard.v" -// Clock, enable, and reset controls for whole system -// Modified version to enable multi_usrp synchronisation - -module master_control_multi - ( input master_clk, input usbclk, - input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe, - input wire rx_slave_sync, - output tx_bus_reset, output rx_bus_reset, - output wire tx_dsp_reset, output wire rx_dsp_reset, - output wire enable_tx, output wire enable_rx, - output wire sync_rx, - output wire [7:0] interp_rate, output wire [7:0] decim_rate, - output tx_sample_strobe, output strobe_interp, - output rx_sample_strobe, output strobe_decim, - input tx_empty, - input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3, - output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3 - ); - - wire [15:0] reg_1_std; - - master_control master_control_standard - ( .master_clk(master_clk),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), - .tx_empty(tx_empty), - .debug_0(debug_0),.debug_1(debug_1), - .debug_2(debug_2),.debug_3(debug_3), - .reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) ); - - // FIXME need a separate reset for all control settings - // Master/slave Controls assignments - wire [7:0] rx_master_slave_controls; - setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls)); - - assign sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync); - //sync if we are told by master_control or if we get a hardware slave sync - //TODO There can be a one sample difference between master and slave sync. - // Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger - // Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind) - //TODO make output pin not hardwired -assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]}; - - -endmodule // master_control diff --git a/sdr_lib/phase_acc.v b/sdr_lib/phase_acc.v deleted file mode 100755 index f44853d36..000000000 --- a/sdr_lib/phase_acc.v +++ /dev/null @@ -1,52 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - - -// Basic Phase accumulator for DDS - - -module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase); - parameter FREQADDR = 0; - parameter PHASEADDR = 0; - parameter resolution = 32; - - input clk, reset, enable, strobe; - input [6:0] serial_addr; - input [31:0] serial_data; - input serial_strobe; - - output reg [resolution-1:0] phase; - wire [resolution-1:0] freq; - - setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq)); - - always @(posedge clk) - if(reset) - phase <= #1 32'b0; - else if(serial_strobe & (serial_addr == PHASEADDR)) - phase <= #1 serial_data; - else if(enable & strobe) - phase <= #1 phase + freq; - -endmodule // phase_acc - - diff --git a/sdr_lib/ram.v b/sdr_lib/ram.v deleted file mode 100644 index fb64cdeae..000000000 --- a/sdr_lib/ram.v +++ /dev/null @@ -1,16 +0,0 @@ - - -module ram (input clock, input write, - input [4:0] wr_addr, input [15:0] wr_data, - input [4:0] rd_addr, output reg [15:0] rd_data); - - reg [15:0] ram_array [0:31]; - - always @(posedge clock) - rd_data <= #1 ram_array[rd_addr]; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - -endmodule // ram diff --git a/sdr_lib/ram16.v b/sdr_lib/ram16.v deleted file mode 100644 index 0c93da2be..000000000 --- a/sdr_lib/ram16.v +++ /dev/null @@ -1,17 +0,0 @@ - - -module ram16 (input clock, input write, - input [3:0] wr_addr, input [15:0] wr_data, - input [3:0] rd_addr, output reg [15:0] rd_data); - - reg [15:0] ram_array [0:15]; - - always @(posedge clock) - rd_data <= #1 ram_array[rd_addr]; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - -endmodule // ram16 - diff --git a/sdr_lib/ram32.v b/sdr_lib/ram32.v deleted file mode 100644 index 064e2735a..000000000 --- a/sdr_lib/ram32.v +++ /dev/null @@ -1,17 +0,0 @@ - - -module ram32 (input clock, input write, - input [4:0] wr_addr, input [15:0] wr_data, - input [4:0] rd_addr, output reg [15:0] rd_data); - - reg [15:0] ram_array [0:31]; - - always @(posedge clock) - rd_data <= #1 ram_array[rd_addr]; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - -endmodule // ram32 - diff --git a/sdr_lib/ram64.v b/sdr_lib/ram64.v deleted file mode 100644 index 084545808..000000000 --- a/sdr_lib/ram64.v +++ /dev/null @@ -1,16 +0,0 @@ - - -module ram64 (input clock, input write, - input [5:0] wr_addr, input [15:0] wr_data, - input [5:0] rd_addr, output reg [15:0] rd_data); - - reg [15:0] ram_array [0:63]; - - always @(posedge clock) - rd_data <= #1 ram_array[rd_addr]; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - -endmodule // ram64 diff --git a/sdr_lib/rssi.v b/sdr_lib/rssi.v deleted file mode 100644 index e45e2148c..000000000 --- a/sdr_lib/rssi.v +++ /dev/null @@ -1,30 +0,0 @@ - - -module rssi (input clock, input reset, input enable, - input [11:0] adc, output [15:0] rssi, output [15:0] over_count); - - wire over_hi = (adc == 12'h7FF); - wire over_lo = (adc == 12'h800); - wire over = over_hi | over_lo; - - reg [25:0] over_count_int; - always @(posedge clock) - if(reset | ~enable) - over_count_int <= #1 26'd0; - else - over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10]; - - assign over_count = over_count_int[25:10]; - - wire [11:0] abs_adc = adc[11] ? ~adc : adc; - - reg [25:0] rssi_int; - always @(posedge clock) - if(reset | ~enable) - rssi_int <= #1 26'd0; - else - rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10]; - - assign rssi = rssi_int[25:10]; - -endmodule // rssi diff --git a/sdr_lib/rx_buffer.v b/sdr_lib/rx_buffer.v deleted file mode 100644 index d17294b98..000000000 --- a/sdr_lib/rx_buffer.v +++ /dev/null @@ -1,237 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Interface to Cypress FX2 bus -// A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each - -`include "../../firmware/include/fpga_regs_common.v" -`include "../../firmware/include/fpga_regs_standard.v" - -module rx_buffer - ( // Read/USB side - input usbclk, - input bus_reset, - output [15:0] usbdata, - input RD, - output reg have_pkt_rdy, - output reg rx_overrun, - input clear_status, - // Write/DSP side - input rxclk, - input reset, // DSP side reset (used here), do not reset registers - input rxstrobe, - input wire [3:0] channels, - input wire [15:0] ch_0, - input wire [15:0] ch_1, - input wire [15:0] ch_2, - input wire [15:0] ch_3, - input wire [15:0] ch_4, - input wire [15:0] ch_5, - input wire [15:0] ch_6, - input wire [15:0] ch_7, - // Settings, on rxclk also - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, - input reset_regs, //Only reset registers - output [31:0] debugbus - ); - - wire [15:0] fifodata, fifodata_8; - reg [15:0] fifodata_16; - - wire [11:0] rxfifolevel; - wire rx_full; - - wire bypass_hb, want_q; - wire [4:0] bitwidth; - wire [3:0] bitshift; - - setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({bypass_hb,want_q,bitwidth,bitshift})); - - // USB Read Side of FIFO - always @(negedge usbclk) - have_pkt_rdy <= (rxfifolevel >= 256); - - // 257 Bug Fix - reg [8:0] read_count; - always @(negedge usbclk) - if(bus_reset) - read_count <= 0; - else if(RD) - read_count <= read_count + 1; - else - read_count <= 0; - - // FIFO - wire ch0_in, ch0_out, iq_out; - assign ch0_in = (phase == 1); - - fifo_4k_18 rxfifo - ( // DSP Write Side - .data ( {ch0_in, phase[0], fifodata} ), - .wrreq (~rx_full & (phase != 0)), - .wrclk ( rxclk ), - .wrfull ( rx_full ), - .wrempty ( ), - .wrusedw ( ), - // USB Read Side - .q ( {ch0_out,iq_out,usbdata} ), - .rdreq ( RD & ~read_count[8] ), - .rdclk ( ~usbclk ), - .rdfull ( ), - .rdempty ( ), - .rdusedw ( rxfifolevel ), - // Async, shared - .aclr ( reset ) ); - - // DSP Write Side of FIFO - reg [15:0] ch_0_reg; - reg [15:0] ch_1_reg; - reg [15:0] ch_2_reg; - reg [15:0] ch_3_reg; - reg [15:0] ch_4_reg; - reg [15:0] ch_5_reg; - reg [15:0] ch_6_reg; - reg [15:0] ch_7_reg; - - always @(posedge rxclk) - if (rxstrobe) - begin - ch_0_reg <= ch_0; - ch_1_reg <= ch_1; - ch_2_reg <= ch_2; - ch_3_reg <= ch_3; - ch_4_reg <= ch_4; - ch_5_reg <= ch_5; - ch_6_reg <= ch_6; - ch_7_reg <= ch_7; - end - - reg [3:0] phase; - always @(posedge rxclk) - if(reset) - phase <= 4'd0; - else if(phase == 0) - begin - if(rxstrobe) - phase <= 4'd1; - end - else if(~rx_full) - if(phase == ((bitwidth == 5'd8) ? (channels>>1) : channels)) - phase <= 4'd0; - else - phase <= phase + 4'd1; - - assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16; - - assign fifodata_8 = {round_8(top),round_8(bottom)}; - reg [15:0] top,bottom; - - function [7:0] round_8; - input [15:0] in_val; - - round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]); - endfunction // round_8 - - always @* - case(phase) - 4'd1 : begin - bottom = ch_0_reg; - top = ch_1_reg; - end - 4'd2 : begin - bottom = ch_2_reg; - top = ch_3_reg; - end - 4'd3 : begin - bottom = ch_4_reg; - top = ch_5_reg; - end - 4'd4 : begin - bottom = ch_6_reg; - top = ch_7_reg; - end - default : begin - top = 16'hFFFF; - bottom = 16'hFFFF; - end - endcase // case(phase) - - always @* - case(phase) - 4'd1 : fifodata_16 = ch_0_reg; - 4'd2 : fifodata_16 = ch_1_reg; - 4'd3 : fifodata_16 = ch_2_reg; - 4'd4 : fifodata_16 = ch_3_reg; - 4'd5 : fifodata_16 = ch_4_reg; - 4'd6 : fifodata_16 = ch_5_reg; - 4'd7 : fifodata_16 = ch_6_reg; - 4'd8 : fifodata_16 = ch_7_reg; - default : fifodata_16 = 16'hFFFF; - endcase // case(phase) - - // Detect overrun - reg clear_status_dsp, rx_overrun_dsp; - always @(posedge rxclk) - clear_status_dsp <= clear_status; - - always @(negedge usbclk) - rx_overrun <= rx_overrun_dsp; - - always @(posedge rxclk) - if(reset) - rx_overrun_dsp <= 1'b0; - else if(rxstrobe & (phase != 0)) - rx_overrun_dsp <= 1'b1; - else if(clear_status_dsp) - rx_overrun_dsp <= 1'b0; - - // Debug bus - // - // 15:0 rxclk domain => TXA 15:0 - // 31:16 usbclk domain => RXA 15:0 - - assign debugbus[0] = reset; - assign debugbus[1] = reset_regs; - assign debugbus[2] = rxstrobe; - assign debugbus[6:3] = channels; - assign debugbus[7] = rx_full; - assign debugbus[11:8] = phase; - assign debugbus[12] = ch0_in; - assign debugbus[13] = clear_status_dsp; - assign debugbus[14] = rx_overrun_dsp; - assign debugbus[15] = rxclk; - - assign debugbus[16] = bus_reset; - assign debugbus[17] = RD; - assign debugbus[18] = have_pkt_rdy; - assign debugbus[19] = rx_overrun; - assign debugbus[20] = read_count[0]; - assign debugbus[21] = read_count[8]; - assign debugbus[22] = ch0_out; - assign debugbus[23] = iq_out; - assign debugbus[24] = clear_status; - assign debugbus[30:25] = 0; - assign debugbus[31] = usbclk; - -endmodule // rx_buffer - diff --git a/sdr_lib/rx_chain.v b/sdr_lib/rx_chain.v deleted file mode 100644 index bc4336e41..000000000 --- a/sdr_lib/rx_chain.v +++ /dev/null @@ -1,106 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Following defines conditionally include RX path circuitry - -`include "config.vh" // resolved relative to project root - -module rx_chain - (input clock, - input reset, - input enable, - input wire [7:0] decim_rate, - input sample_strobe, - input decimator_strobe, - output wire hb_strobe, - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, - input wire [15:0] i_in, - input wire [15:0] q_in, - output wire [15:0] i_out, - output wire [15:0] q_out, - output wire [15:0] debugdata,output wire [15:0] debugctrl - ); - - parameter FREQADDR = 0; - parameter PHASEADDR = 0; - - wire [31:0] phase; - wire [15:0] bb_i, bb_q; - wire [15:0] hb_in_i, hb_in_q; - - assign debugdata = hb_in_i; - -`ifdef RX_NCO_ON - phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc - (.clk(clock),.reset(reset),.enable(enable), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .strobe(sample_strobe),.phase(phase) ); - - cordic rx_cordic - ( .clock(clock),.reset(reset),.enable(enable), - .xi(i_in),.yi(q_in),.zi(phase[31:16]), - .xo(bb_i),.yo(bb_q),.zo() ); -`else - assign bb_i = i_in; - assign bb_q = q_in; - assign sample_strobe = 1; -`endif // !`ifdef RX_NCO_ON - -`ifdef RX_CIC_ON - cic_decim cic_decim_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_i),.signal_out(hb_in_i) ); -`else - assign hb_in_i = bb_i; - assign decimator_strobe = sample_strobe; -`endif - -`ifdef RX_HB_ON - halfband_decim hbd_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .strobe_in(decimator_strobe),.strobe_out(hb_strobe), - .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) ); -`else - assign i_out = hb_in_i; - assign hb_strobe = decimator_strobe; -`endif - -`ifdef RX_CIC_ON - cic_decim cic_decim_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_q),.signal_out(hb_in_q) ); -`else - assign hb_in_q = bb_q; -`endif - -`ifdef RX_HB_ON - halfband_decim hbd_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .strobe_in(decimator_strobe),.strobe_out(), - .data_in(hb_in_q),.data_out(q_out) ); -`else - assign q_out = hb_in_q; -`endif - - -endmodule // rx_chain diff --git a/sdr_lib/rx_chain_dual.v b/sdr_lib/rx_chain_dual.v deleted file mode 100644 index d9d98f3fc..000000000 --- a/sdr_lib/rx_chain_dual.v +++ /dev/null @@ -1,103 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module rx_chain_dual - (input clock, - input clock_2x, - input reset, - input enable, - input wire [7:0] decim_rate, - input sample_strobe, - input decimator_strobe, - input wire [31:0] freq0, - input wire [15:0] i_in0, - input wire [15:0] q_in0, - output wire [15:0] i_out0, - output wire [15:0] q_out0, - input wire [31:0] freq1, - input wire [15:0] i_in1, - input wire [15:0] q_in1, - output wire [15:0] i_out1, - output wire [15:0] q_out1 - ); - - wire [15:0] phase; - wire [15:0] bb_i, bb_q; - wire [15:0] i_in, q_in; - - wire [31:0] phase0; - wire [31:0] phase1; - reg [15:0] bb_i0, bb_q0; - reg [15:0] bb_i1, bb_q1; - - // We want to time-share the CORDIC by double-clocking it - - phase_acc rx_phase_acc_0 - (.clk(clock),.reset(reset),.enable(enable), - .strobe(sample_strobe),.freq(freq0),.phase(phase0) ); - - phase_acc rx_phase_acc_1 - (.clk(clock),.reset(reset),.enable(enable), - .strobe(sample_strobe),.freq(freq1),.phase(phase1) ); - - assign phase = clock ? phase0[31:16] : phase1[31:16]; - assign i_in = clock ? i_in0 : i_in1; - assign q_in = clock ? q_in0 : q_in1; - -// This appears reversed because of the number of CORDIC stages - always @(posedge clock_2x) - if(clock) - begin - bb_i1 <= #1 bb_i; - bb_q1 <= #1 bb_q; - end - else - begin - bb_i0 <= #1 bb_i; - bb_q0 <= #1 bb_q; - end - - cordic rx_cordic - ( .clock(clock_2x),.reset(reset),.enable(enable), - .xi(i_in),.yi(q_in),.zi(phase), - .xo(bb_i),.yo(bb_q),.zo() ); - - cic_decim cic_decim_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_i0),.signal_out(i_out0) ); - - cic_decim cic_decim_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_q0),.signal_out(q_out0) ); - - cic_decim cic_decim_i_1 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_i1),.signal_out(i_out1) ); - - cic_decim cic_decim_q_1 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_q1),.signal_out(q_out1) ); - -endmodule // rx_chain diff --git a/sdr_lib/rx_dcoffset.v b/sdr_lib/rx_dcoffset.v deleted file mode 100644 index 3be475ed6..000000000 --- a/sdr_lib/rx_dcoffset.v +++ /dev/null @@ -1,22 +0,0 @@ - - -module rx_dcoffset (input clock, input enable, input reset, - input signed [15:0] adc_in, output signed [15:0] adc_out, - input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe); - parameter MYADDR = 0; - - reg signed [31:0] integrator; - wire signed [15:0] scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]); - assign adc_out = adc_in - scaled_integrator; - - // FIXME do we need signed? - //FIXME What do we do when clipping? - always @(posedge clock) - if(reset) - integrator <= #1 32'd0; - else if(serial_strobe & (MYADDR == serial_addr)) - integrator <= #1 {serial_data[15:0],16'd0}; - else if(enable) - integrator <= #1 integrator + adc_out; - -endmodule // rx_dcoffset diff --git a/sdr_lib/serial_io.v b/sdr_lib/serial_io.v deleted file mode 100644 index 62f92bed2..000000000 --- a/sdr_lib/serial_io.v +++ /dev/null @@ -1,118 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2004 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - - -// Serial Control Bus from Cypress chip - -module serial_io - ( input master_clk, - input serial_clock, - input serial_data_in, - input enable, - input reset, - inout wire serial_data_out, - output reg [6:0] serial_addr, - output reg [31:0] serial_data, - output wire serial_strobe, - input wire [31:0] readback_0, - input wire [31:0] readback_1, - input wire [31:0] readback_2, - input wire [31:0] readback_3, - input wire [31:0] readback_4, - input wire [31:0] readback_5, - input wire [31:0] readback_6, - input wire [31:0] readback_7 - ); - - reg is_read; - reg [7:0] ser_ctr; - reg write_done; - - assign serial_data_out = is_read ? serial_data[31] : 1'bz; - - always @(posedge serial_clock, posedge reset, negedge enable) - if(reset) - ser_ctr <= #1 8'd0; - else if(~enable) - ser_ctr <= #1 8'd0; - else if(ser_ctr == 39) - ser_ctr <= #1 8'd0; - else - ser_ctr <= #1 ser_ctr + 8'd1; - - always @(posedge serial_clock, posedge reset, negedge enable) - if(reset) - is_read <= #1 1'b0; - else if(~enable) - is_read <= #1 1'b0; - else if((ser_ctr == 7)&&(serial_addr[6]==1)) - is_read <= #1 1'b1; - - always @(posedge serial_clock, posedge reset) - if(reset) - begin - serial_addr <= #1 7'b0; - serial_data <= #1 32'b0; - write_done <= #1 1'b0; - end - else if(~enable) - begin - //serial_addr <= #1 7'b0; - //serial_data <= #1 32'b0; - write_done <= #1 1'b0; - end - else - begin - if(~is_read && (ser_ctr == 39)) - write_done <= #1 1'b1; - else - write_done <= #1 1'b0; - if(is_read & (ser_ctr==8)) - case (serial_addr) - 7'd1: serial_data <= #1 readback_0; - 7'd2: serial_data <= #1 readback_1; - 7'd3: serial_data <= #1 readback_2; - 7'd4: serial_data <= #1 readback_3; - 7'd5: serial_data <= #1 readback_4; - 7'd6: serial_data <= #1 readback_5; - 7'd7: serial_data <= #1 readback_6; - 7'd8: serial_data <= #1 readback_7; - default: serial_data <= #1 32'd0; - endcase // case(serial_addr) - else if(ser_ctr >= 8) - serial_data <= #1 {serial_data[30:0],serial_data_in}; - else if(ser_ctr < 8) - serial_addr <= #1 {serial_addr[5:0],serial_data_in}; - end // else: !if(~enable) - - reg enable_d1, enable_d2; - always @(posedge master_clk) - begin - enable_d1 <= #1 enable; - enable_d2 <= #1 enable_d1; - end - - assign serial_strobe = enable_d2 & ~enable_d1; - -endmodule // serial_io - - diff --git a/sdr_lib/setting_reg.v b/sdr_lib/setting_reg.v deleted file mode 100644 index 3d31a9efb..000000000 --- a/sdr_lib/setting_reg.v +++ /dev/null @@ -1,23 +0,0 @@ - - -module setting_reg - ( input clock, input reset, input strobe, input wire [6:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); - parameter my_addr = 0; - - always @(posedge clock) - if(reset) - begin - out <= #1 32'd0; - changed <= #1 1'b0; - end - else - if(strobe & (my_addr==addr)) - begin - out <= #1 in; - changed <= #1 1'b1; - end - else - changed <= #1 1'b0; - -endmodule // setting_reg diff --git a/sdr_lib/setting_reg_masked.v b/sdr_lib/setting_reg_masked.v deleted file mode 100644 index 72f7e21eb..000000000 --- a/sdr_lib/setting_reg_masked.v +++ /dev/null @@ -1,26 +0,0 @@ - - -module setting_reg_masked - ( input clock, input reset, input strobe, input wire [6:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); -/* upper 16 bits are mask, lower 16 bits are value - * Note that you get a 16 bit register, not a 32 bit one */ - - parameter my_addr = 0; - - always @(posedge clock) - if(reset) - begin - out <= #1 32'd0; - changed <= #1 1'b0; - end - else - if(strobe & (my_addr==addr)) - begin - out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] ); - changed <= #1 1'b1; - end - else - changed <= #1 1'b0; - -endmodule // setting_reg_masked diff --git a/sdr_lib/sign_extend.v b/sdr_lib/sign_extend.v deleted file mode 100644 index eae67faf2..000000000 --- a/sdr_lib/sign_extend.v +++ /dev/null @@ -1,35 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// Sign extension "macro" -// bits_out should be greater than bits_in - -module sign_extend (in,out); - parameter bits_in=0; // FIXME Quartus insists on a default - parameter bits_out=0; - - input [bits_in-1:0] in; - output [bits_out-1:0] out; - - assign out = {{(bits_out-bits_in){in[bits_in-1]}},in}; - -endmodule diff --git a/sdr_lib/strobe_gen.v b/sdr_lib/strobe_gen.v deleted file mode 100644 index ba1a8ab28..000000000 --- a/sdr_lib/strobe_gen.v +++ /dev/null @@ -1,46 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - - -module strobe_gen - ( input clock, - input reset, - input enable, - input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio - input strobe_in, - output wire strobe ); - -// parameter width = 8; - - reg [7:0] counter; - assign strobe = ~|counter && enable && strobe_in; - - always @(posedge clock) - if(reset | ~enable) - counter <= #1 8'd0; - else if(strobe_in) - if(counter == 0) - counter <= #1 rate; - else - counter <= #1 counter - 8'd1; - -endmodule // strobe_gen diff --git a/sdr_lib/tx_buffer.v b/sdr_lib/tx_buffer.v deleted file mode 100644 index 58642229d..000000000 --- a/sdr_lib/tx_buffer.v +++ /dev/null @@ -1,170 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Interface to Cypress FX2 bus -// A packet is 512 Bytes. Each fifo line is 2 bytes -// Fifo has 1024 or 2048 lines - -module tx_buffer - ( // USB Side - input usbclk, - input bus_reset, // Used here for the 257-Hack to fix the FX2 bug - input [15:0] usbdata, - input wire WR, - output reg have_space, - output reg tx_underrun, - input clear_status, - - // DSP Side - input txclk, - input reset, // standard DSP-side reset - input wire [3:0] channels, - output reg [15:0] tx_i_0, - output reg [15:0] tx_q_0, - output reg [15:0] tx_i_1, - output reg [15:0] tx_q_1, - input txstrobe, - output wire tx_empty, - output [31:0] debugbus - ); - - wire [11:0] txfifolevel; - wire [15:0] fifodata; - wire rdreq; - reg [3:0] phase; - wire sop_f, iq_f; - reg sop; - - // USB Side of FIFO - reg [15:0] usbdata_reg; - reg wr_reg; - reg [8:0] write_count; - - always @(posedge usbclk) - have_space <= (txfifolevel < (4092-256)); // be extra conservative - - always @(posedge usbclk) - begin - wr_reg <= WR; - usbdata_reg <= usbdata; - end - - always @(posedge usbclk) - if(bus_reset) - write_count <= 0; - else if(wr_reg) - write_count <= write_count + 1; - else - write_count <= 0; - - always @(posedge usbclk) - sop <= WR & ~wr_reg; // Edge detect - - // FIFO - fifo_4k_18 txfifo - ( // USB Write Side - .data ( {sop,write_count[0],usbdata_reg} ), - .wrreq ( wr_reg & ~write_count[8] ), - .wrclk ( usbclk ), - .wrfull ( ), - .wrempty ( ), - .wrusedw ( txfifolevel ), - // DSP Read Side - .q ( {sop_f, iq_f, fifodata} ), - .rdreq ( rdreq ), - .rdclk ( txclk ), - .rdfull ( ), - .rdempty ( tx_empty ), - .rdusedw ( ), - // Async, shared - .aclr ( reset ) ); - - // DAC Side of FIFO - always @(posedge txclk) - if(reset) - begin - {tx_i_0,tx_q_0,tx_i_1,tx_q_1} <= 64'h0; - phase <= 4'd0; - end - else if(phase == channels) - begin - if(txstrobe) - phase <= 4'd0; - end - else - if(~tx_empty) - begin - case(phase) - 4'd0 : tx_i_0 <= fifodata; - 4'd1 : tx_q_0 <= fifodata; - 4'd2 : tx_i_1 <= fifodata; - 4'd3 : tx_q_1 <= fifodata; - endcase // case(phase) - phase <= phase + 4'd1; - end - - assign rdreq = ((phase != channels) & ~tx_empty); - - // Detect Underruns, cross clock domains - reg clear_status_dsp, tx_underrun_dsp; - always @(posedge txclk) - clear_status_dsp <= clear_status; - - always @(posedge usbclk) - tx_underrun <= tx_underrun_dsp; - - always @(posedge txclk) - if(reset) - tx_underrun_dsp <= 1'b0; - else if(txstrobe & (phase != channels)) - tx_underrun_dsp <= 1'b1; - else if(clear_status_dsp) - tx_underrun_dsp <= 1'b0; - - // TX debug bus - // - // 15:0 txclk domain => TXA [15:0] - // 31:16 usbclk domain => RXA [15:0] - - assign debugbus[0] = reset; - assign debugbus[1] = txstrobe; - assign debugbus[2] = rdreq; - assign debugbus[6:3] = phase; - assign debugbus[7] = tx_empty; - assign debugbus[8] = tx_underrun_dsp; - assign debugbus[9] = iq_f; - assign debugbus[10] = sop_f; - assign debugbus[14:11] = 0; - assign debugbus[15] = txclk; - - assign debugbus[16] = bus_reset; - assign debugbus[17] = WR; - assign debugbus[18] = wr_reg; - assign debugbus[19] = have_space; - assign debugbus[20] = write_count[8]; - assign debugbus[21] = write_count[0]; - assign debugbus[22] = sop; - assign debugbus[23] = tx_underrun; - assign debugbus[30:24] = 0; - assign debugbus[31] = usbclk; - -endmodule // tx_buffer - diff --git a/sdr_lib/tx_chain.v b/sdr_lib/tx_chain.v deleted file mode 100644 index 60f868475..000000000 --- a/sdr_lib/tx_chain.v +++ /dev/null @@ -1,65 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module tx_chain - (input clock, - input reset, - input enable, - input wire [7:0] interp_rate, - input sample_strobe, - input interpolator_strobe, - input wire [31:0] freq, - input wire [15:0] i_in, - input wire [15:0] q_in, - output wire [15:0] i_out, - output wire [15:0] q_out - ); - - wire [15:0] bb_i, bb_q; - - cic_interp cic_interp_i - ( .clock(clock),.reset(reset),.enable(enable), - .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe), - .signal_in(i_in),.signal_out(bb_i) ); - - cic_interp cic_interp_q - ( .clock(clock),.reset(reset),.enable(enable), - .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe), - .signal_in(q_in),.signal_out(bb_q) ); - -`define NOCORDIC_TX -`ifdef NOCORDIC_TX - assign i_out = bb_i; - assign q_out = bb_q; -`else - wire [31:0] phase; - - phase_acc phase_acc_tx - (.clk(clock),.reset(reset),.enable(enable), - .strobe(sample_strobe),.freq(freq),.phase(phase) ); - - cordic tx_cordic_0 - ( .clock(clock),.reset(reset),.enable(sample_strobe), - .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), - .xo(i_out),.yo(q_out),.zo() ); -`endif - -endmodule // tx_chain diff --git a/sdr_lib/tx_chain_hb.v b/sdr_lib/tx_chain_hb.v deleted file mode 100644 index 5594348b4..000000000 --- a/sdr_lib/tx_chain_hb.v +++ /dev/null @@ -1,76 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module tx_chain_hb - (input clock, - input reset, - input enable, - input wire [7:0] interp_rate, - input sample_strobe, - input interpolator_strobe, - input hb_strobe, - input wire [31:0] freq, - input wire [15:0] i_in, - input wire [15:0] q_in, - output wire [15:0] i_out, - output wire [15:0] q_out, -output wire [15:0] debug, output [15:0] hb_i_out - ); -assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe}; - - wire [15:0] bb_i, bb_q; - wire [15:0] hb_i_out, hb_q_out; - - halfband_interp hb - (.clock(clock),.reset(reset),.enable(enable), - .strobe_in(interpolator_strobe),.strobe_out(hb_strobe), - .signal_in_i(i_in),.signal_in_q(q_in), - .signal_out_i(hb_i_out),.signal_out_q(hb_q_out), - .debug(debug[12:0])); - - cic_interp cic_interp_i - ( .clock(clock),.reset(reset),.enable(enable), - .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), - .signal_in(hb_i_out),.signal_out(bb_i) ); - - cic_interp cic_interp_q - ( .clock(clock),.reset(reset),.enable(enable), - .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), - .signal_in(hb_q_out),.signal_out(bb_q) ); - -`define NOCORDIC_TX -`ifdef NOCORDIC_TX - assign i_out = bb_i; - assign q_out = bb_q; -`else - wire [31:0] phase; - - phase_acc phase_acc_tx - (.clk(clock),.reset(reset),.enable(enable), - .strobe(sample_strobe),.freq(freq),.phase(phase) ); - - cordic tx_cordic_0 - ( .clock(clock),.reset(reset),.enable(sample_strobe), - .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), - .xo(i_out),.yo(q_out),.zo() ); -`endif - -endmodule // tx_chain diff --git a/tb/.gitignore b/tb/.gitignore deleted file mode 100644 index 6bc85aa2d..000000000 --- a/tb/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/*.vcd -/*.out -/fullchip_tb diff --git a/tb/cbus_tb.v b/tb/cbus_tb.v deleted file mode 100644 index 53cc1272b..000000000 --- a/tb/cbus_tb.v +++ /dev/null @@ -1,71 +0,0 @@ -module cbus_tb; - -`define ch1in_freq 0 -`define ch2in_freq 1 -`define ch3in_freq 2 -`define ch4in_freq 3 -`define ch1out_freq 4 -`define ch2out_freq 5 -`define ch3out_freq 6 -`define ch4out_freq 7 -`define rates 8 -`define misc 9 - - task send_config_word; - input [7:0] addr; - input [31:0] data; - integer i; - - begin - #10 serenable = 1; - for(i=7;i>=0;i=i-1) - begin - #10 serdata = addr[i]; - #10 serclk = 0; - #10 serclk = 1; - #10 serclk = 0; - end - for(i=31;i>=0;i=i-1) - begin - #10 serdata = data[i]; - #10 serclk = 0; - #10 serclk = 1; - #10 serclk = 0; - end - #10 serenable = 0; - // #10 serclk = 1; - // #10 serclk = 0; - end - endtask // send_config_word - - initial $dumpfile("cbus_tb.vcd"); - initial $dumpvars(0,cbus_tb); - - initial reset = 1; - initial #500 reset = 0; - - reg serclk, serdata, serenable, reset; - wire SDO; - - control_bus control_bus - ( .serial_clock(serclk), - .serial_data_in(serdata), - .enable(serenable), - .reset(reset), - .serial_data_out(SDO) ); - - - initial - begin - #1000 send_config_word(8'd1,32'hDEAD_BEEF); - #1000 send_config_word(8'd3,32'hDDEE_FF01); - #1000 send_config_word(8'd19,32'hFFFF_FFFF); - #1000 send_config_word(8'd23,32'h1234_FEDC); - #1000 send_config_word(8'h80,32'h0); - #1000 send_config_word(8'h81,32'h0); - #1000 send_config_word(8'h82,32'h0); - #1000 reset = 1; - #1 $finish; - end - -endmodule // cbus_tb diff --git a/tb/cordic_tb.v b/tb/cordic_tb.v deleted file mode 100644 index 946fc776c..000000000 --- a/tb/cordic_tb.v +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - - -module cordic_tb(); - - cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo ); - - reg reset; - reg clk; - reg enable; - reg [15:0] xi, yi, zi; - - initial reset = 1'b1; - initial #1000 reset = 1'b0; - - initial clk = 1'b0; - always #50 clk <= ~clk; - - initial enable = 1'b1; - - initial zi = 16'b0; - - always @(posedge clk) - zi <= #1 zi + 16'd0; - - wire [15:0] xo,yo,zo; - - initial $dumpfile("cordic.vcd"); - initial $dumpvars(0,cordic_tb); - initial - begin -`include "sine.txt" - end - - wire [15:0] xiu = {~xi[15],xi[14:0]}; - wire [15:0] yiu = {~yi[15],yi[14:0]}; - wire [15:0] xou = {~xo[15],xo[14:0]}; - wire [15:0] you = {~yo[15],yo[14:0]}; - initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you); - -endmodule // cordic_tb diff --git a/tb/decim_tb.v b/tb/decim_tb.v deleted file mode 100644 index d9a926125..000000000 --- a/tb/decim_tb.v +++ /dev/null @@ -1,108 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// testbench for fullchip - -module decim_tb(); - -`include "usrp_tasks.v" - - reg clk_120mhz; - reg usbclk; - reg reset; - - reg [11:0] adc1_data, adc2_data; - wire [13:0] dac1_data, dac2_data; - - wire [5:0] usbctl; - wire [5:0] usbrdy; - - wire [15:0] usbdata; - - reg WE, RD, OE; - - assign usbctl[0] = WE; - assign usbctl[1] = RD; - assign usbctl[2] = OE; - assign usbctl[5:3] = 0; - - reg tb_oe; - assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; - reg serload, serenable, serclk, serdata; - reg enable_tx, enable_rx; - reg [15:0] usbdatareg; - -/////////////////////////////////////////////// -// Simulation Control -initial -begin - $dumpfile("decim_tb.vcd"); - $dumpvars(0, fc_tb); -end - -initial #100000 $finish; - -/////////////////////////////////////////////// -// Monitors - -reg [7:0] counter_decim; -wire [7:0] decim_rate; -assign decim_rate = 32; -initial $monitor(dac1_data); - - always @(posedge clk_120mhz) - begin - if(reset | ~enable_tx) - counter_decim <= #1 0; - else if(counter_decim == 0) - counter_decim <= #1 decim_rate - 8'b1; - else - counter_decim <= #1 counter_decim - 8'b1; - end - -/////////////////////////////////////////////// -// Clock and reset - -initial clk_120mhz = 0; -initial usbclk = 0; -always #48 clk_120mhz = ~clk_120mhz; -always #120 usbclk = ~usbclk; - -initial reset = 1'b1; -initial #500 reset = 1'b0; - - -initial enable_tx = 1'b1; - - wire [31:0] decim_out, q_decim_out; - wire [31:0] decim_out; - wire [31:0] phase; - - cic_decim #(.bitwidth(32),.stages(4)) - decim_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), - .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); - - cic_decim #(.bitwidth(32),.stages(4)) - decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), - .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); - -endmodule diff --git a/tb/fullchip_tb.v b/tb/fullchip_tb.v deleted file mode 100755 index 2406fa777..000000000 --- a/tb/fullchip_tb.v +++ /dev/null @@ -1,174 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// testbench for fullchip - -`timescale 1ns/1ns - -module fullchip_tb(); - -`include "usrp_tasks.v" - -fullchip fullchip - ( - .clk_120mhz(clk_120mhz), - .reset(reset), - .enable_rx(enable_rx), - .enable_tx(enable_tx), - .SLD(serload), - .SEN(serenable), - .clear_status(), - .SDI(serdata), - .SCLK(serclk), - - .adc1_data(adc1_data), - .adc2_data(adc2_data), - .adc3_data(adc1_data), - .adc4_data(adc2_data), - - .dac1_data(dac1_data), - .dac2_data(dac2_data), - .dac3_data(),.dac4_data(), - - .adclk0(adclk),.adclk1(), - - .adc_oeb(),.adc_otr(4'b0), - - .clk_out(clk_out), - - .misc_pins(), - - // USB interface - .usbclk(usbclk),.usbctl(usbctl), - .usbrdy(usbrdy),.usbdata(usbdata) - ); - - reg clk_120mhz; - reg usbclk; - reg reset; - - reg [11:0] adc1_data, adc2_data; - wire [13:0] dac1_data, dac2_data; - - wire [5:0] usbctl; - wire [5:0] usbrdy; - - wire [15:0] usbdata; - - reg WE, RD, OE; - - assign usbctl[0] = WE; - assign usbctl[1] = RD; - assign usbctl[2] = OE; - assign usbctl[5:3] = 0; - - wire have_packet_rdy = usbrdy[1]; - - reg tb_oe; - initial tb_oe=1'b1; - - assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; - reg serload, serenable, serclk, serdata; - reg enable_tx, enable_rx; - reg [15:0] usbdatareg; - -/////////////////////////////////////////////// -// Simulation Control -initial -begin - $dumpfile("fullchip_tb.vcd"); - $dumpvars(0, fullchip_tb); -end - -//initial #1000000 $finish; - -/////////////////////////////////////////////// -// Monitors - -//initial $monitor(dac1_data); - -/////////////////////////////////////////////// -// Clock and reset - -initial clk_120mhz = 0; -initial usbclk = 0; -always #24 clk_120mhz = ~clk_120mhz; -always #60 usbclk = ~usbclk; - -initial reset = 1'b1; -initial #500 reset = 1'b0; - -///////////////////////////////////////////////// -// Run AD input - -always @(posedge adclk) adc1_data <= #1 12'd1234; -always @(posedge adclk) adc2_data <= #1 12'd1234; - -///////////////////////////////////////////////// -// USB interface - - initial - begin - initialize_usb; - #30000 @(posedge usbclk); - burst_usb_write(257); - - #30000 burst_usb_read(256); - #10000 $finish; - -// repeat(30) -// begin -// write_from_usb; -// read_from_usb; -// end -end - -///////////////////////////////////////////////// -// TX and RX enable - -initial enable_tx = 1'b0; -initial #40000 enable_tx = 1'b1; -initial enable_rx = 1'b0; -initial #40000 enable_rx = 1'b1; - -////////////////////////////////////////////////// -// Set up control bus - -initial -begin - #1000 send_config_word(`ch1in_freq,32'h0); // 1 MHz on 60 MHz clock - send_config_word(`ch2in_freq,32'h0); - send_config_word(`ch3in_freq,32'h0); - send_config_word(`ch4in_freq,32'h0); - send_config_word(`ch1out_freq,32'h01234567); - send_config_word(`ch2out_freq,32'h0); - send_config_word(`ch3out_freq,32'h0); - send_config_word(`ch4out_freq,32'h0); - send_config_word(`misc,32'h0); - send_config_word(`rates,{8'd2,8'd12,8'h0f,8'h07}); - // adc, ext, interp, decim -end - -///////////////////////////////////////////////////////// - -endmodule - diff --git a/tb/interp_tb.v b/tb/interp_tb.v deleted file mode 100755 index 830fceb31..000000000 --- a/tb/interp_tb.v +++ /dev/null @@ -1,108 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// testbench for fullchip - -module interp_tb(); - -`include "usrp_tasks.v" - - reg clk_120mhz; - reg usbclk; - reg reset; - - reg [11:0] adc1_data, adc2_data; - wire [13:0] dac1_data, dac2_data; - - wire [5:0] usbctl; - wire [5:0] usbrdy; - - wire [15:0] usbdata; - - reg WE, RD, OE; - - assign usbctl[0] = WE; - assign usbctl[1] = RD; - assign usbctl[2] = OE; - assign usbctl[5:3] = 0; - - reg tb_oe; - assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; - reg serload, serenable, serclk, serdata; - reg enable_tx, enable_rx; - reg [15:0] usbdatareg; - -/////////////////////////////////////////////// -// Simulation Control -initial -begin - $dumpfile("interp_tb.vcd"); - $dumpvars(0, fc_tb); -end - -initial #100000 $finish; - -/////////////////////////////////////////////// -// Monitors - -reg [7:0] counter_interp; -wire [7:0] interp_rate; -assign interp_rate = 32; -initial $monitor(dac1_data); - - always @(posedge clk_120mhz) - begin - if(reset | ~enable_tx) - counter_interp <= #1 0; - else if(counter_interp == 0) - counter_interp <= #1 interp_rate - 8'b1; - else - counter_interp <= #1 counter_interp - 8'b1; - end - -/////////////////////////////////////////////// -// Clock and reset - -initial clk_120mhz = 0; -initial usbclk = 0; -always #48 clk_120mhz = ~clk_120mhz; -always #120 usbclk = ~usbclk; - -initial reset = 1'b1; -initial #500 reset = 1'b0; - - -initial enable_tx = 1'b1; - - wire [31:0] interp_out, q_interp_out; - wire [31:0] decim_out; - wire [31:0] phase; - - cic_interp #(.bitwidth(32),.stages(4)) - interp_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), - .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(interp_out)); - - cic_decim #(.bitwidth(32),.stages(4)) - decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), - .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); - -endmodule diff --git a/tb/justinterp_tb.v b/tb/justinterp_tb.v deleted file mode 100644 index f97696488..000000000 --- a/tb/justinterp_tb.v +++ /dev/null @@ -1,73 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -module cic_decim_tb; - -cic_decim #(.bitwidth(16),.stages(4)) - decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out); - - reg clock; - reg reset; - reg enable; - wire strobe; - reg [15:0] signal_in; - wire [15:0] signal_out; - - assign strobe_in = 1'b1; - reg strobe_out; - - always @(posedge clock) - while(1) - begin - @(posedge clock); - @(posedge clock); - @(posedge clock); - @(posedge clock); - strobe_out <= 1'b1; - @(posedge clock); - @(posedge clock); - @(posedge clock); - @(posedge clock); - strobe_out <= 1'b0; - end - - initial clock = 0; - always #50 clock = ~clock; - - initial reset = 1; - initial #1000 reset = 0; - - initial enable = 0; - initial #2000 enable = 1; - - initial signal_in = 16'h1; - initial #500000 signal_in = 16'h7fff; - initial #1000000 signal_in = 16'h8000; - initial #1500000 signal_in = 16'hffff; - - - initial $dumpfile("decim.vcd"); - initial $dumpvars(0,cic_decim_tb); - - initial #10000000 $finish; - -endmodule // cic_decim_tb diff --git a/tb/makesine.pl b/tb/makesine.pl deleted file mode 100755 index 9aebd6947..000000000 --- a/tb/makesine.pl +++ /dev/null @@ -1,14 +0,0 @@ -#!/usr/bin/perl - -$angle = 0; -$angle_inc = 2*3.14159/87.2; -$amp = 1; -$amp_rate = 1.0035; -for($i=0;$i<3500;$i++) - { - printf("@(posedge clk);xi<= #1 16'h%x;yi<= #1 16'h%x;\n",65535&int($amp*cos($angle)),65535&int($amp*sin($angle))); - $angle += $angle_inc; - $amp *= $amp_rate; - } - -printf("\$finish;\n"); diff --git a/tb/run_cordic b/tb/run_cordic deleted file mode 100755 index 68144fc83..000000000 --- a/tb/run_cordic +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -iverilog -y ../sdr_lib -o cordic_tb cordic_tb.v - diff --git a/tb/run_fullchip b/tb/run_fullchip deleted file mode 100755 index eb81d7ff7..000000000 --- a/tb/run_fullchip +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -iverilog -y ../toplevel/fullchip -y ../sdr_lib -y ../models -y . -o fullchip_tb fullchip_tb.v - diff --git a/tb/usrp_tasks.v b/tb/usrp_tasks.v deleted file mode 100755 index 93395f96a..000000000 --- a/tb/usrp_tasks.v +++ /dev/null @@ -1,145 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Tasks - -///////////////////////////////////////////////// -// USB interface - -task initialize_usb; -begin - OE = 0;WE = 0;RD = 0; - usbdatareg <= 16'h0; -end -endtask - -task write_from_usb; -begin - tb_oe <= 1'b1; - @(posedge usbclk); - usbdatareg <= #1 $random % 65536; - WE <= #1 1'b1; - @(posedge usbclk) - WE <= #1 1'b0; - tb_oe <= #1 1'b0; -end -endtask - -task burst_usb_write; - input [31:0] repeat_count; - - begin - tb_oe <= 1'b1; - repeat(repeat_count) - begin - @(posedge usbclk) - usbdatareg <= #1 usbdatareg + 1; //$random % 65536; - WE <= #1 1'b1; - end - @(posedge usbclk) - WE <= #1 1'b0; - tb_oe <= 1'b0; - end -endtask // burst_usb_write - - -task read_from_usb; -begin - @(posedge usbclk); - RD <= #1 1'b1; - @(posedge usbclk); - RD <= #1 1'b0; - OE <= #1 1'b1; - @(posedge usbclk); - OE <= #1 1'b0; -end -endtask - -task burst_usb_read; - input [31:0] repeat_count; - begin - while (~have_packet_rdy) begin - @(posedge usbclk); - end - - @(posedge usbclk) - RD <= #1 1'b1; - repeat(repeat_count) - begin - @(posedge usbclk) - OE <= #1 1'b1; - end - RD <= #1 1'b0; - @(posedge usbclk); - OE <= #1 1'b0; - end -endtask // burst_usb_read - -///////////////////////////////////////////////// -// TX and RX enable - -////////////////////////////////////////////////// -// Set up control bus - -`define ch1in_freq 0 -`define ch2in_freq 1 -`define ch3in_freq 2 -`define ch4in_freq 3 -`define ch1out_freq 4 -`define ch2out_freq 5 -`define ch3out_freq 6 -`define ch4out_freq 7 -`define rates 8 -`define misc 9 - - task send_config_word; - input [7:0] addr; - input [31:0] data; - integer i; - - begin - #10 serenable = 1; - for(i=7;i>=0;i=i-1) - begin - #10 serdata = addr[i]; - #10 serclk = 0; - #10 serclk = 1; - #10 serclk = 0; - end - for(i=31;i>=0;i=i-1) - begin - #10 serdata = data[i]; - #10 serclk = 0; - #10 serclk = 1; - #10 serclk = 0; - end - #10 serenable = 0; - // #10 serload = 0; - // #10 serload = 1; - #10 serclk = 1; - #10 serclk = 0; - //#10 serload = 0; - end - endtask // send_config_word - - -///////////////////////////////////////////////////////// - diff --git a/toplevel/include/common_config_1rxhb_1tx.vh b/toplevel/include/common_config_1rxhb_1tx.vh deleted file mode 100644 index fb2e915b1..000000000 --- a/toplevel/include/common_config_1rxhb_1tx.vh +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built - `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_SINGLE and TX_DUAL are currently valid] - `define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* receive circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - - `define RX_SINGLE -//`define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter - `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/include/common_config_2rx_0tx.vh b/toplevel/include/common_config_2rx_0tx.vh deleted file mode 100644 index c97c5a32b..000000000 --- a/toplevel/include/common_config_2rx_0tx.vh +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built -// `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_SINGLE and TX_DUAL are currently valid] -//`define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* receive circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE -`define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter -//`define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/include/common_config_2rxhb_0tx.vh b/toplevel/include/common_config_2rxhb_0tx.vh deleted file mode 100644 index 459268b6a..000000000 --- a/toplevel/include/common_config_2rxhb_0tx.vh +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built -// `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_SINGLE and TX_DUAL are currently valid] -//`define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* transmit circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE - `define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter - `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/include/common_config_2rxhb_2tx.vh b/toplevel/include/common_config_2rxhb_2tx.vh deleted file mode 100644 index ecf0fa03e..000000000 --- a/toplevel/include/common_config_2rxhb_2tx.vh +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built - `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_SINGLE and TX_DUAL are currently valid] -//`define TX_SINGLE - `define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* receive circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE - `define RX_DUAL -//`define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter - `define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/include/common_config_4rx_0tx.vh b/toplevel/include/common_config_4rx_0tx.vh deleted file mode 100644 index 498419570..000000000 --- a/toplevel/include/common_config_4rx_0tx.vh +++ /dev/null @@ -1,61 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ------------------------------------------------------------ -// If TX_ON is not defined, there is *no* transmit circuitry built -// `define TX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD -// to respectively enable 1, 2 or 4 transmit channels. -// [Please note that only TX_SINGLE and TX_DUAL are currently valid] -//`define TX_SINGLE -//`define TX_DUAL -//`define TX_QUAD - -// ------------------------------------------------------------ -// Define TX_HB_ON to enable the transmit halfband filter -// [Not implemented] -//`define TX_HB_ON - -// ------------------------------------------------------------ -// IF RX_ON is not defined, there is *no* receive circuitry built - `define RX_ON - -// ------------------------------------------------------------ -// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD -// to respectively define 1, 2 or 4 receive channels. - -//`define RX_SINGLE -//`define RX_DUAL - `define RX_QUAD - -// ------------------------------------------------------------ -// Define RX_HB_ON to enable the receive halfband filter -//`define RX_HB_ON - -// ------------------------------------------------------------ -// Define RX_NCO_ON to enable the receive Numerical Controlled Osc - `define RX_NCO_ON - -// ------------------------------------------------------------ -// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter - `define RX_CIC_ON diff --git a/toplevel/include/common_config_bottom.vh b/toplevel/include/common_config_bottom.vh deleted file mode 100644 index 3129798a1..000000000 --- a/toplevel/include/common_config_bottom.vh +++ /dev/null @@ -1,104 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006,2007 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// This is the common tail for standard configuation -// ==================================================================== -// -// >>>> DO NOT EDIT BELOW HERE <<<< -// -// N.B., *all* the remainder of the code should be conditionalized -// only in terms of: -// -// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB, -// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB, -// RX_NCO_ON, RX_CIC_ON -// ==================================================================== - -`ifdef TX_ON - - `ifdef TX_SINGLE - `define TX_EN_0 - `define TX_CAP_NCHAN 3'd1 - `endif - - `ifdef TX_DUAL - `define TX_EN_0 - `define TX_EN_1 - `define TX_CAP_NCHAN 3'd2 - `endif - - `ifdef TX_QUAD - `define TX_EN_0 - `define TX_EN_1 - `define TX_EN_2 - `define TX_EN_3 - `define TX_CAP_NCHAN 3'd4 - `endif - - `ifdef TX_HB_ON - `define TX_CAP_HB 1 - `else - `define TX_CAP_HB 0 - `endif - -`else // !ifdef TX_ON - - `define TX_CAP_NCHAN 3'd0 - `define TX_CAP_HB 0 - -`endif // !ifdef TX_ON - -// -------------------------------------------------------------------- - -`ifdef RX_ON - - `ifdef RX_SINGLE - `define RX_EN_0 - `define RX_CAP_NCHAN 3'd1 - `endif - - `ifdef RX_DUAL - `define RX_EN_0 - `define RX_EN_1 - `define RX_CAP_NCHAN 3'd2 - `endif - - `ifdef RX_QUAD - `define RX_EN_0 - `define RX_EN_1 - `define RX_EN_2 - `define RX_EN_3 - `define RX_CAP_NCHAN 3'd4 - `endif - - `ifdef RX_HB_ON - `define RX_CAP_HB 1 - `else - `define RX_CAP_HB 0 - `endif - -`else // !ifdef RX_ON - - `define RX_CAP_NCHAN 3'd0 - `define RX_CAP_HB 0 - -`endif // !ifdef RX_ON diff --git a/toplevel/mrfm/.gitignore b/toplevel/mrfm/.gitignore deleted file mode 100644 index fe06aad0d..000000000 --- a/toplevel/mrfm/.gitignore +++ /dev/null @@ -1,17 +0,0 @@ -/*.qws -/*.eqn -/*.done -/*.htm -/*.rpt -/*.ini -/*.fsf -/*.jam -/*.jbc -/*.pin -/*.pof -/*.sof -/*.rbf -/*.ttf -/*.summary -/a.out -/db diff --git a/toplevel/mrfm/biquad_2stage.v b/toplevel/mrfm/biquad_2stage.v deleted file mode 100644 index 9b769014d..000000000 --- a/toplevel/mrfm/biquad_2stage.v +++ /dev/null @@ -1,131 +0,0 @@ -`include "mrfm.vh" - -module biquad_2stage (input clock, input reset, input strobe_in, - input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, - input wire [15:0] sample_in, output reg [15:0] sample_out, output wire [63:0] debugbus); - - wire [3:0] coeff_addr, coeff_wr_addr; - wire [3:0] data_addr, data_wr_addr; - reg [3:0] cur_offset, data_addr_int, data_wr_addr_int; - - wire [15:0] coeff, coeff_wr_data, data, data_wr_data; - wire coeff_wr; - reg data_wr; - - wire [30:0] product; - wire [33:0] accum; - wire [15:0] scaled_accum; - - wire [7:0] shift; - reg [3:0] phase; - wire enable_mult, enable_acc, latch_out, select_input; - reg done, clear_acc; - - setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr)); - - setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(shift),.changed()); - - ram16 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data), - .rd_addr(coeff_addr),.rd_data(coeff)); - - ram16 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data), - .rd_addr(data_addr),.rd_data(data)); - - mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() ); - - acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), - .addend(product),.sum(accum) ); - - shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); - - assign data_wr_data = select_input ? sample_in : scaled_accum; - assign enable_mult = 1'b1; - - always @(posedge clock) - if(reset) - cur_offset <= #1 4'd0; - else if(latch_out) - cur_offset <= #1 cur_offset + 4'd1; - - assign data_addr = data_addr_int + cur_offset; - assign data_wr_addr = data_wr_addr_int + cur_offset; - - always @(posedge clock) - if(reset) - done <= #1 1'b0; - else if(latch_out) - done <= #1 1'b1; - else if(strobe_in) - done <= #1 1'b0; - - always @(posedge clock) - if(reset) - phase <= #1 4'd0; - else if(strobe_in) - phase <= #1 4'd0; - else if(!done) - phase <= #1 phase + 4'd1; - - assign coeff_addr = phase; - - always @(phase) - case(phase) - 4'd01 : data_addr_int = 4'd00; 4'd02 : data_addr_int = 4'd01; 4'd03 : data_addr_int = 4'd02; - 4'd04 : data_addr_int = 4'd03; 4'd05 : data_addr_int = 4'd04; - - 4'd07 : data_addr_int = 4'd03; 4'd08 : data_addr_int = 4'd04; 4'd09 : data_addr_int = 4'd05; - 4'd10 : data_addr_int = 4'd06; 4'd11 : data_addr_int = 4'd07; - default : data_addr_int = 4'd00; - endcase // case(phase) - - always @(phase) - case(phase) - 4'd0 : data_wr_addr_int = 4'd2; - 4'd8 : data_wr_addr_int = 4'd5; - 4'd14 : data_wr_addr_int = 4'd8; - default : data_wr_addr_int = 4'd0; - endcase // case(phase) - - always @(phase) - case(phase) - 4'd0, 4'd8, 4'd14 : data_wr = 1'b1; - default : data_wr = 1'b0; - endcase // case(phase) - - assign select_input = (phase == 4'd0); - - always @(phase) - case(phase) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd9, 4'd15 : clear_acc = 1'd1; - default : clear_acc = 1'b0; - endcase // case(phase) - - assign enable_acc = ~clear_acc; - assign latch_out = (phase == 4'd14); - - always @(posedge clock) - if(reset) - sample_out <= #1 16'd0; - else if(latch_out) - sample_out <= #1 scaled_accum; - - //////////////////////////////////////////////////////// - // Debug - - wire [3:0] debugmux; - - setting_reg #(`FR_MRFM_DEBUG) sr_debugmux(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(debugmux),.changed()); - - assign debugbus[15:0] = debugmux[0] ? {coeff_addr,data_addr,data_wr_addr,cur_offset} : {phase,data_addr_int,data_wr_addr_int,cur_offset}; - assign debugbus[31:16] = debugmux[1] ? scaled_accum : {clock, strobe_in, data_wr, enable_mult, enable_acc, clear_acc, latch_out,select_input,done, data_addr_int}; - assign debugbus[47:32] = debugmux[2] ? sample_out : coeff; - assign debugbus[63:48] = debugmux[3] ? sample_in : data; - -endmodule // biquad_2stage - diff --git a/toplevel/mrfm/biquad_6stage.v b/toplevel/mrfm/biquad_6stage.v deleted file mode 100644 index 2b0c511ce..000000000 --- a/toplevel/mrfm/biquad_6stage.v +++ /dev/null @@ -1,137 +0,0 @@ -`include "mrfm.vh" - -module mrfm_iir (input clock, input reset, input strobe_in, - input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, - input wire [15:0] sample_in, output reg [15:0] sample_out); - - wire [5:0] coeff_addr, coeff_wr_addr; - wire [4:0] data_addr, data_wr_addr; - reg [4:0] cur_offset, data_addr_int, data_wr_addr_int; - - wire [15:0] coeff, coeff_wr_data, data, data_wr_data; - wire coeff_wr; - reg data_wr; - - wire [30:0] product; - wire [33:0] accum; - wire [15:0] scaled_accum; - - wire [7:0] shift; - reg [5:0] phase; - wire enable_mult, enable_acc, latch_out, select_input; - reg done, clear_acc; - - setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr)); - - setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(shift),.changed()); - - ram64 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data), - .rd_addr(coeff_addr),.rd_data(coeff)); - - ram32 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data), - .rd_addr(data_addr),.rd_data(data)); - - mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() ); - - acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), - .addend(product),.sum(accum) ); - - shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); - - assign data_wr_data = select_input ? sample_in : scaled_accum; - assign enable_mult = 1'b1; - - always @(posedge clock) - if(reset) - cur_offset <= #1 5'd0; - else if(latch_out) - cur_offset <= #1 cur_offset + 5'd1; - - assign data_addr = data_addr_int + cur_offset; - assign data_wr_addr = data_wr_addr_int + cur_offset; - - always @(posedge clock) - if(reset) - done <= #1 1'b0; - else if(latch_out) - done <= #1 1'b1; - else if(strobe_in) - done <= #1 1'b0; - - always @(posedge clock) - if(reset) - phase <= #1 6'd0; - else if(strobe_in) - phase <= #1 6'd0; - else if(!done) - phase <= #1 phase + 6'd1; - - always @(phase) - case(phase) - 6'd0 : data_addr_int = 5'd0; - default : data_addr_int = 5'd0; - endcase // case(phase) - - assign coeff_addr = phase; - - always @(phase) - case(phase) - 6'd01 : data_addr_int = 5'd00; 6'd02 : data_addr_int = 5'd01; 6'd03 : data_addr_int = 5'd02; - 6'd04 : data_addr_int = 5'd03; 6'd05 : data_addr_int = 5'd04; - - 6'd07 : data_addr_int = 5'd03; 6'd08 : data_addr_int = 5'd04; 6'd09 : data_addr_int = 5'd05; - 6'd10 : data_addr_int = 5'd06; 6'd11 : data_addr_int = 5'd07; - - 6'd13 : data_addr_int = 5'd06; 6'd14 : data_addr_int = 5'd07; 6'd15 : data_addr_int = 5'd08; - 6'd16 : data_addr_int = 5'd09; 6'd17 : data_addr_int = 5'd10; - - 6'd19 : data_addr_int = 5'd09; 6'd20 : data_addr_int = 5'd10; 6'd21 : data_addr_int = 5'd11; - 6'd22 : data_addr_int = 5'd12; 6'd23 : data_addr_int = 5'd13; - - 6'd25 : data_addr_int = 5'd12; 6'd26 : data_addr_int = 5'd13; 6'd27 : data_addr_int = 5'd14; - 6'd28 : data_addr_int = 5'd15; 6'd29 : data_addr_int = 5'd16; - - 6'd31 : data_addr_int = 5'd15; 6'd32 : data_addr_int = 5'd16; 6'd33 : data_addr_int = 5'd17; - 6'd34 : data_addr_int = 5'd18; 6'd35 : data_addr_int = 5'd19; - - default : data_addr_int = 5'd00; - endcase // case(phase) - - always @(phase) - case(phase) - 6'd0 : data_wr_addr_int = 5'd2; - 6'd8 : data_wr_addr_int = 5'd5; - 6'd14 : data_wr_addr_int = 5'd8; - 6'd20 : data_wr_addr_int = 5'd11; - 6'd26 : data_wr_addr_int = 5'd14; - 6'd32 : data_wr_addr_int = 5'd17; - 6'd38 : data_wr_addr_int = 5'd20; - default : data_wr_addr_int = 5'd0; - endcase // case(phase) - - always @(phase) - case(phase) - 6'd0, 6'd8, 6'd14, 6'd20, 6'd26, 6'd32, 6'd38: data_wr = 1'b1; - default : data_wr = 1'b0; - endcase // case(phase) - - always @(phase) - case(phase) - 6'd0, 6'd1, 6'd2, 6'd3, 6'd9, 6'd15, 6'd21, 6'd27, 6'd33 : clear_acc = 1'd1; - default : clear_acc = 1'b0; - endcase // case(phase) - - assign enable_acc = ~clear_acc; - assign latch_out = (phase == 6'd38); - - always @(posedge clock) - if(reset) - sample_out <= #1 16'd0; - else if(latch_out) - sample_out <= #1 scaled_accum; - -endmodule // mrfm_iir diff --git a/toplevel/mrfm/mrfm.csf b/toplevel/mrfm/mrfm.csf deleted file mode 100644 index 2c30b996b..000000000 --- a/toplevel/mrfm/mrfm.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |mrfm; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(mrfm) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/toplevel/mrfm/mrfm.esf b/toplevel/mrfm/mrfm.esf deleted file mode 100644 index 72b84e39e..000000000 --- a/toplevel/mrfm/mrfm.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = mrfm; -} diff --git a/toplevel/mrfm/mrfm.psf b/toplevel/mrfm/mrfm.psf deleted file mode 100644 index 678a7faa2..000000000 --- a/toplevel/mrfm/mrfm.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(mrfm) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "e:\usrp\fpga\megacells"; -} -THIRD_PARTY_EDA_TOOLS(mrfm) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; - EDA_SIMULATION_TOOL = ""; - EDA_TIMING_ANALYSIS_TOOL = ""; - EDA_BOARD_DESIGN_TOOL = ""; - EDA_FORMAL_VERIFICATION_TOOL = ""; - EDA_RESYNTHESIS_TOOL = ""; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/toplevel/mrfm/mrfm.py b/toplevel/mrfm/mrfm.py deleted file mode 100644 index 100db69eb..000000000 --- a/toplevel/mrfm/mrfm.py +++ /dev/null @@ -1,129 +0,0 @@ -#!/usr/bin/env python -# -# This is mrfm_fft_sos.py -# Modification of Matt's mrfm_fft.py that reads filter coefs from file -# -# Copyright 2004,2005 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru -from gnuradio import usrp - -class source_c(usrp.source_c): - def __init__(self,fpga_filename): - usrp.source_c.__init__(self,which=0, decim_rate=64, nchan=2, mux=0x32103210, mode=0, - fpga_filename=fpga_filename) - - self._write_9862(0,2,0x80) # Bypass ADC buffer, minimum gain - self._write_9862(0,3,0x80) # Bypass ADC buffer, minimum gain - - self._write_9862(0,8,0) # TX PWR Down - self._write_9862(0,10,0) # DAC offset - self._write_9862(0,11,0) # DAC offset - self._write_9862(0,14,0x80) # gain - self._write_9862(0,16,0xff) # pga - self._write_9862(0,18,0x0c) # TX IF - self._write_9862(0,19,0x01) # TX Digital - self._write_9862(0,20,0x00) # TX Mod - - # max/min values are +/-2, so scale is set to make 2 = 32767 - - self._write_fpga_reg(69,0x0e) # debug mux - self._write_fpga_reg(5,-1) - self._write_fpga_reg(7,-1) - self._write_oe(0,0xffff, 0xffff) - self._write_oe(1,0xffff, 0xffff) - self._write_fpga_reg(14,0xf) - - self.decim = None - - def set_coeffs(self,frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11): - def make_val(address,value): - return (address << 16) | (value & 0xffff) - - # gain, scale already included in a's and b's from file - - self._write_fpga_reg(67,make_val(1,b20)) - self._write_fpga_reg(67,make_val(2,b10)) - self._write_fpga_reg(67,make_val(3,b00)) - self._write_fpga_reg(67,make_val(4,a20)) - self._write_fpga_reg(67,make_val(5,a10)) - - self._write_fpga_reg(67,make_val(7,b21)) - self._write_fpga_reg(67,make_val(8,b11)) - self._write_fpga_reg(67,make_val(9,b01)) - self._write_fpga_reg(67,make_val(10,a21)) - self._write_fpga_reg(67,make_val(11,a11)) - - self._write_fpga_reg(68,frac_bits) # Shift - - print "Biquad 0 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b20,b10,b00,a20,a10) - print "Biquad 1 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b21,b11,b01,a21,a11) - - def set_decim_rate(self,rate=None): - i=2 - turn=1 - a=1 - b=1 - while (rate>1) and (i<257): - if (rate/i) * i == rate: - if turn == 1: - if a*i<257: - a = a * i - turn = 0 - elif b*i<257: - b = b * i - turn = 0 - else: - print "Failed to set DECIMATOR" - return self.decim - elif b*i<257: - b = b * i - turn = 1 - elif a*i<257: - a = a * i - turn = 1 - else: - print "Failed to set DECIMATOR" - return self.decim - rate=rate/i - continue - i = i + 1 - if rate > 1: - print "Failed to set DECIMATOR" - return self.decim - else: - self.decim = a*b - print "a = %d b = %d" % (a,b) - self._write_fpga_reg(64,(a-1)*256+(b-1)) # Set actual decimation - - def decim_rate(self): - return self.decim - - def set_center_freq(self,freq): - self._write_fpga_reg(65,int(-freq/64e6*65536*65536)) # set center freq - - def set_compensator(self,a11,a12,a21,a22,shift): - self._write_fpga_reg(70,a11) - self._write_fpga_reg(71,a12) - self._write_fpga_reg(72,a21) - self._write_fpga_reg(73,a22) - self._write_fpga_reg(74,shift) # comp shift - diff --git a/toplevel/mrfm/mrfm.qpf b/toplevel/mrfm/mrfm.qpf deleted file mode 100644 index 959140875..000000000 --- a/toplevel/mrfm/mrfm.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.0" -DATE = "17:10:11 December 20, 2004" - - -# Active Revisions - -PROJECT_REVISION = "mrfm" diff --git a/toplevel/mrfm/mrfm.qsf b/toplevel/mrfm/mrfm.qsf deleted file mode 100644 index ba1ae0223..000000000 --- a/toplevel/mrfm/mrfm.qsf +++ /dev/null @@ -1,411 +0,0 @@ -# Copyright (C) 1991-2005 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# The default values for assignments are stored in the file -# mrfm_assignment_defaults.qdf -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2" - -# Pin & Location Assignments -# ========================== -set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -set_location_assignment PIN_29 -to SCLK -set_location_assignment PIN_117 -to SDI -set_location_assignment PIN_28 -to usbclk -set_location_assignment PIN_107 -to usbctl[0] -set_location_assignment PIN_106 -to usbctl[1] -set_location_assignment PIN_105 -to usbctl[2] -set_location_assignment PIN_100 -to usbdata[0] -set_location_assignment PIN_84 -to usbdata[10] -set_location_assignment PIN_83 -to usbdata[11] -set_location_assignment PIN_82 -to usbdata[12] -set_location_assignment PIN_79 -to usbdata[13] -set_location_assignment PIN_78 -to usbdata[14] -set_location_assignment PIN_77 -to usbdata[15] -set_location_assignment PIN_99 -to usbdata[1] -set_location_assignment PIN_98 -to usbdata[2] -set_location_assignment PIN_95 -to usbdata[3] -set_location_assignment PIN_94 -to usbdata[4] -set_location_assignment PIN_93 -to usbdata[5] -set_location_assignment PIN_88 -to usbdata[6] -set_location_assignment PIN_87 -to usbdata[7] -set_location_assignment PIN_86 -to usbdata[8] -set_location_assignment PIN_85 -to usbdata[9] -set_location_assignment PIN_104 -to usbrdy[0] -set_location_assignment PIN_101 -to usbrdy[1] -set_location_assignment PIN_76 -to FX2_1 -set_location_assignment PIN_75 -to FX2_2 -set_location_assignment PIN_74 -to FX2_3 -set_location_assignment PIN_116 -to io_rx_a[0] -set_location_assignment PIN_115 -to io_rx_a[1] -set_location_assignment PIN_114 -to io_rx_a[2] -set_location_assignment PIN_113 -to io_rx_a[3] -set_location_assignment PIN_108 -to io_rx_a[4] -set_location_assignment PIN_195 -to io_rx_a[5] -set_location_assignment PIN_196 -to io_rx_a[6] -set_location_assignment PIN_197 -to io_rx_a[7] -set_location_assignment PIN_200 -to io_rx_a[8] -set_location_assignment PIN_201 -to io_rx_a[9] -set_location_assignment PIN_202 -to io_rx_a[10] -set_location_assignment PIN_203 -to io_rx_a[11] -set_location_assignment PIN_206 -to io_rx_a[12] -set_location_assignment PIN_207 -to io_rx_a[13] -set_location_assignment PIN_208 -to io_rx_a[14] -set_location_assignment PIN_214 -to io_rx_b[0] -set_location_assignment PIN_215 -to io_rx_b[1] -set_location_assignment PIN_216 -to io_rx_b[2] -set_location_assignment PIN_217 -to io_rx_b[3] -set_location_assignment PIN_218 -to io_rx_b[4] -set_location_assignment PIN_219 -to io_rx_b[5] -set_location_assignment PIN_222 -to io_rx_b[6] -set_location_assignment PIN_223 -to io_rx_b[7] -set_location_assignment PIN_224 -to io_rx_b[8] -set_location_assignment PIN_225 -to io_rx_b[9] -set_location_assignment PIN_226 -to io_rx_b[10] -set_location_assignment PIN_227 -to io_rx_b[11] -set_location_assignment PIN_228 -to io_rx_b[12] -set_location_assignment PIN_233 -to io_rx_b[13] -set_location_assignment PIN_234 -to io_rx_b[14] -set_location_assignment PIN_175 -to io_tx_a[0] -set_location_assignment PIN_176 -to io_tx_a[1] -set_location_assignment PIN_177 -to io_tx_a[2] -set_location_assignment PIN_178 -to io_tx_a[3] -set_location_assignment PIN_179 -to io_tx_a[4] -set_location_assignment PIN_180 -to io_tx_a[5] -set_location_assignment PIN_181 -to io_tx_a[6] -set_location_assignment PIN_182 -to io_tx_a[7] -set_location_assignment PIN_183 -to io_tx_a[8] -set_location_assignment PIN_184 -to io_tx_a[9] -set_location_assignment PIN_185 -to io_tx_a[10] -set_location_assignment PIN_186 -to io_tx_a[11] -set_location_assignment PIN_187 -to io_tx_a[12] -set_location_assignment PIN_188 -to io_tx_a[13] -set_location_assignment PIN_193 -to io_tx_a[14] -set_location_assignment PIN_73 -to io_tx_b[0] -set_location_assignment PIN_68 -to io_tx_b[1] -set_location_assignment PIN_67 -to io_tx_b[2] -set_location_assignment PIN_66 -to io_tx_b[3] -set_location_assignment PIN_65 -to io_tx_b[4] -set_location_assignment PIN_64 -to io_tx_b[5] -set_location_assignment PIN_63 -to io_tx_b[6] -set_location_assignment PIN_62 -to io_tx_b[7] -set_location_assignment PIN_61 -to io_tx_b[8] -set_location_assignment PIN_60 -to io_tx_b[9] -set_location_assignment PIN_59 -to io_tx_b[10] -set_location_assignment PIN_58 -to io_tx_b[11] -set_location_assignment PIN_57 -to io_tx_b[12] -set_location_assignment PIN_56 -to io_tx_b[13] -set_location_assignment PIN_55 -to io_tx_b[14] -set_location_assignment PIN_152 -to master_clk -set_location_assignment PIN_144 -to rx_a_a[0] -set_location_assignment PIN_143 -to rx_a_a[1] -set_location_assignment PIN_141 -to rx_a_a[2] -set_location_assignment PIN_140 -to rx_a_a[3] -set_location_assignment PIN_139 -to rx_a_a[4] -set_location_assignment PIN_138 -to rx_a_a[5] -set_location_assignment PIN_137 -to rx_a_a[6] -set_location_assignment PIN_136 -to rx_a_a[7] -set_location_assignment PIN_135 -to rx_a_a[8] -set_location_assignment PIN_134 -to rx_a_a[9] -set_location_assignment PIN_133 -to rx_a_a[10] -set_location_assignment PIN_132 -to rx_a_a[11] -set_location_assignment PIN_23 -to rx_a_b[0] -set_location_assignment PIN_21 -to rx_a_b[1] -set_location_assignment PIN_20 -to rx_a_b[2] -set_location_assignment PIN_19 -to rx_a_b[3] -set_location_assignment PIN_18 -to rx_a_b[4] -set_location_assignment PIN_17 -to rx_a_b[5] -set_location_assignment PIN_16 -to rx_a_b[6] -set_location_assignment PIN_15 -to rx_a_b[7] -set_location_assignment PIN_14 -to rx_a_b[8] -set_location_assignment PIN_13 -to rx_a_b[9] -set_location_assignment PIN_12 -to rx_a_b[10] -set_location_assignment PIN_11 -to rx_a_b[11] -set_location_assignment PIN_131 -to rx_b_a[0] -set_location_assignment PIN_128 -to rx_b_a[1] -set_location_assignment PIN_127 -to rx_b_a[2] -set_location_assignment PIN_126 -to rx_b_a[3] -set_location_assignment PIN_125 -to rx_b_a[4] -set_location_assignment PIN_124 -to rx_b_a[5] -set_location_assignment PIN_123 -to rx_b_a[6] -set_location_assignment PIN_122 -to rx_b_a[7] -set_location_assignment PIN_121 -to rx_b_a[8] -set_location_assignment PIN_120 -to rx_b_a[9] -set_location_assignment PIN_119 -to rx_b_a[10] -set_location_assignment PIN_118 -to rx_b_a[11] -set_location_assignment PIN_8 -to rx_b_b[0] -set_location_assignment PIN_7 -to rx_b_b[1] -set_location_assignment PIN_6 -to rx_b_b[2] -set_location_assignment PIN_5 -to rx_b_b[3] -set_location_assignment PIN_4 -to rx_b_b[4] -set_location_assignment PIN_3 -to rx_b_b[5] -set_location_assignment PIN_2 -to rx_b_b[6] -set_location_assignment PIN_240 -to rx_b_b[7] -set_location_assignment PIN_239 -to rx_b_b[8] -set_location_assignment PIN_238 -to rx_b_b[9] -set_location_assignment PIN_237 -to rx_b_b[10] -set_location_assignment PIN_236 -to rx_b_b[11] -set_location_assignment PIN_156 -to SDO -set_location_assignment PIN_153 -to SEN_FPGA -set_location_assignment PIN_159 -to tx_a[0] -set_location_assignment PIN_160 -to tx_a[1] -set_location_assignment PIN_161 -to tx_a[2] -set_location_assignment PIN_162 -to tx_a[3] -set_location_assignment PIN_163 -to tx_a[4] -set_location_assignment PIN_164 -to tx_a[5] -set_location_assignment PIN_165 -to tx_a[6] -set_location_assignment PIN_166 -to tx_a[7] -set_location_assignment PIN_167 -to tx_a[8] -set_location_assignment PIN_168 -to tx_a[9] -set_location_assignment PIN_169 -to tx_a[10] -set_location_assignment PIN_170 -to tx_a[11] -set_location_assignment PIN_173 -to tx_a[12] -set_location_assignment PIN_174 -to tx_a[13] -set_location_assignment PIN_38 -to tx_b[0] -set_location_assignment PIN_39 -to tx_b[1] -set_location_assignment PIN_41 -to tx_b[2] -set_location_assignment PIN_42 -to tx_b[3] -set_location_assignment PIN_43 -to tx_b[4] -set_location_assignment PIN_44 -to tx_b[5] -set_location_assignment PIN_45 -to tx_b[6] -set_location_assignment PIN_46 -to tx_b[7] -set_location_assignment PIN_47 -to tx_b[8] -set_location_assignment PIN_48 -to tx_b[9] -set_location_assignment PIN_49 -to tx_b[10] -set_location_assignment PIN_50 -to tx_b[11] -set_location_assignment PIN_53 -to tx_b[12] -set_location_assignment PIN_54 -to tx_b[13] -set_location_assignment PIN_158 -to TXSYNC_A -set_location_assignment PIN_37 -to TXSYNC_B -set_location_assignment PIN_235 -to io_rx_b[15] -set_location_assignment PIN_24 -to io_tx_b[15] -set_location_assignment PIN_213 -to io_rx_a[15] -set_location_assignment PIN_194 -to io_tx_a[15] -set_location_assignment PIN_1 -to MYSTERY_SIGNAL - -# Timing Assignments -# ================== -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name TOP_LEVEL_ENTITY mrfm -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP1C12Q240C8 -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name INC_PLC_MODE OFF -set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF -set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -# Timing Analysis Assignments -# =========================== -set_global_assignment -name MAX_SCC_SIZE 50 - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" -set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF - -# Simulator Assignments -# ===================== -set_global_assignment -name START_TIME "0 ns" -set_global_assignment -name GLITCH_INTERVAL "1 ns" - -# Design Assistant Assignments -# ============================ -set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF -set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF -set_global_assignment -name ASSG_CAT OFF -set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF -set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF -set_global_assignment -name CLK_CAT OFF -set_global_assignment -name CLK_RULE_COMB_CLOCK OFF -set_global_assignment -name CLK_RULE_INV_CLOCK OFF -set_global_assignment -name CLK_RULE_GATING_SCHEME OFF -set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF -set_global_assignment -name CLK_RULE_MIX_EDGES OFF -set_global_assignment -name RESET_CAT OFF -set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name TIMING_CAT OFF -set_global_assignment -name TIMING_RULE_SHIFT_REG OFF -set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF -set_global_assignment -name NONSYNCHSTRUCT_CAT OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF -set_global_assignment -name SIGNALRACE_CAT OFF -set_global_assignment -name ACLK_CAT OFF -set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF -set_global_assignment -name HCPY_CAT OFF -set_global_assignment -name HCPY_VREF_PINS OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name HUB_ENTITY_NAME SLD_HUB -set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP OFF - -# LogicLock Region Assignments -# ============================ -set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF - -# ----------------- -# start CLOCK(SCLK) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK -set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK - -# end CLOCK(SCLK) -# --------------- - -# ----------------------- -# start CLOCK(master_clk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk -set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk - -# end CLOCK(master_clk) -# --------------------- - -# ------------------- -# start CLOCK(usbclk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk -set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk - -# end CLOCK(usbclk) -# ----------------- - -# ---------------------- -# start ENTITY(mrfm) - - # Timing Assignments - # ================== -set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK -set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk -set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk - -# end ENTITY(mrfm) -# -------------------- - - -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name VERILOG_FILE mrfm.vh -set_global_assignment -name VERILOG_FILE biquad_2stage.v -set_global_assignment -name VERILOG_FILE mrfm_compensator.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE mrfm_proc.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v -set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v -set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v -set_global_assignment -name VERILOG_FILE mrfm.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" \ No newline at end of file diff --git a/toplevel/mrfm/mrfm.v b/toplevel/mrfm/mrfm.v deleted file mode 100644 index 7a0e38059..000000000 --- a/toplevel/mrfm/mrfm.v +++ /dev/null @@ -1,199 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Top level module for a full setup with DUCs and DDCs - -// Uncomment the following to include optional circuitry - -`include "mrfm.vh" -`include "../../../firmware/include/fpga_regs_common.v" -`include "../../../firmware/include/fpga_regs_standard.v" - -module mrfm -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64; - - wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_space, have_pkt_rdy; - assign usbrdy[0] = have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire tx_underrun, rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = tx_underrun; - - wire [15:0] usbdata_out; - - wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; - - wire tx_realsignals; - wire [3:0] rx_numchan; - - wire [15:0] tx_debugbus, rx_debugbus; - - wire enable_tx, enable_rx; - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - wire [7:0] settings; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - assign clk64 = master_clk; - - wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; - wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - ///////////////////////////////////////////////////////////////////////////////////////////////////// - - setting_reg #(`FR_TX_MUX) - sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); - - ////////////////////////////////////////////////////////////////////////////////////////////////////// - // Signal Processing Chain - - reg [15:0] adc0; - wire [15:0] dac0; - wire [15:0] i,q,ip,qp; - wire strobe_out; - wire sync_out; - - always @(posedge clk64) - adc0 <= #1 {rx_a_a[11],rx_a_a[11:0],3'b0}; - - wire [15:0] adc0_corr; - rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0_corr), - .serial_addr(7'd0),.serial_data(32'd0),.serial_strobe(1'b0)); - - //wire [63:0] filt_debug = 64'd0; - - mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .signal_in(adc0_corr),.signal_out(dac0),.sync_out(sync_out), - .i(i),.q(q),.ip(ip),.qp(qp),.strobe_out(strobe_out), - .debugbus( /* filt_debug */ )); - - wire txsync = 1'b0; - assign TXSYNC_A = txsync; - assign TXSYNC_B = txsync; - - assign tx_a = dac0[15:2]; - - ////////////////////////////////////////////////////////////////////////////////////////////////// - // Data Collection on RX Buffer - - assign rx_numchan[0] = 1'b0; - setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr), - .in(serial_data),.out(rx_numchan[3:1])); - - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(i),.ch_1(q), - .ch_2(ip),.ch_3(qp), - .ch_4(16'd0),.ch_5(16'd0), - .ch_6(16'd0),.ch_7(16'd0), - .rxclk(clk64),.rxstrobe(strobe_out), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus(rx_debugbus) ); - - ////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities = 32'd2; - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) ); - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), - .tx_empty(tx_empty), - .debug_0({15'd0,sync_out}), //filt_debug[63:48]), - .debug_1({15'd0,sync_out}), //filt_debug[47:32]), - .debug_2({15'd0,sync_out}), //filt_debug[31:16]), - .debug_3({15'd0,sync_out}), //filt_debug[15:0]), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - - io_pins io_pins - (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - -endmodule // mrfm - diff --git a/toplevel/mrfm/mrfm.vh b/toplevel/mrfm/mrfm.vh deleted file mode 100644 index 808342d8d..000000000 --- a/toplevel/mrfm/mrfm.vh +++ /dev/null @@ -1,21 +0,0 @@ - - -// MRFM Register defines - -`define FR_MRFM_DECIM 7'd64 -`define FR_MRFM_FREQ 7'd65 -`define FR_MRFM_PHASE 7'd66 -`define FR_MRFM_IIR_COEFF 7'd67 -`define FR_MRFM_IIR_SHIFT 7'd68 -`define FR_MRFM_DEBUG 7'd69 -`define FR_MRFM_COMP_A11 7'd70 -`define FR_MRFM_COMP_A12 7'd71 -`define FR_MRFM_COMP_A21 7'd72 -`define FR_MRFM_COMP_A22 7'd73 -`define FR_MRFM_COMP_SHIFT 7'd74 -`define FR_USER_11 7'd75 -`define FR_USER_12 7'd76 -`define FR_USER_13 7'd77 -`define FR_USER_14 7'd78 -`define FR_USER_15 7'd79 - diff --git a/toplevel/mrfm/mrfm_compensator.v b/toplevel/mrfm/mrfm_compensator.v deleted file mode 100644 index f44b73b2f..000000000 --- a/toplevel/mrfm/mrfm_compensator.v +++ /dev/null @@ -1,80 +0,0 @@ - - -module mrfm_compensator (input clock, input reset, input strobe_in, - input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, - input [15:0] i_in, input [15:0] q_in, output reg [15:0] i_out, output reg [15:0] q_out); - - wire [15:0] a11,a12,a21,a22; - reg [15:0] i_in_reg, q_in_reg; - wire [30:0] product; - reg [3:0] phase; - wire [15:0] data,coeff; - wire [7:0] shift; - wire [33:0] accum; - wire [15:0] scaled_accum; - wire enable_acc; - - setting_reg #(`FR_MRFM_COMP_A11) sr_a11(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(a11),.changed()); - setting_reg #(`FR_MRFM_COMP_A12) sr_a12(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(a12),.changed()); - setting_reg #(`FR_MRFM_COMP_A21) sr_a21(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(a21),.changed()); - setting_reg #(`FR_MRFM_COMP_A22) sr_a22(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(a22),.changed()); - setting_reg #(`FR_MRFM_COMP_SHIFT) sr_cshift(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(shift),.changed()); - - mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(1'b1),.enable_out() ); - acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), - .addend(product),.sum(accum) ); - shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); - - always @(posedge clock) - if(reset) - begin - i_in_reg <= #1 16'd0; - q_in_reg <= #1 16'd0; - end - else if(strobe_in) - begin - i_in_reg <= #1 i_in; - q_in_reg <= #1 q_in; - end - - always @(posedge clock) - if(reset) - phase <= #1 4'd0; - else if(strobe_in) - phase <= #1 4'd1; - else if(strobe_in != 4'd8) - phase <= #1 phase + 4'd1; - - assign data = ((phase == 4'd1)||(phase === 4'd4)) ? i_in_reg : - ((phase == 4'd2)||(phase == 4'd5)) ? q_in_reg : 16'd0; - - assign coeff = (phase == 4'd1) ? a11 : (phase == 4'd2) ? a12 : - (phase == 4'd4) ? a21 : (phase == 4'd5) ? a22 : 16'd0; - - assign clear_acc = (phase == 4'd0) || (phase == 4'd1) || (phase == 4'd4) || (phase==4'd8); - assign enable_acc = ~clear_acc; - - always @(posedge clock) - if(reset) - i_out <= #1 16'd0; - else if(phase == 4'd4) - i_out <= #1 scaled_accum; - - always @(posedge clock) - if(reset) - q_out <= #1 16'd0; - else if(phase == 4'd7) - q_out <= #1 scaled_accum; - - -endmodule // mrfm_compensator diff --git a/toplevel/mrfm/mrfm_fft.py b/toplevel/mrfm/mrfm_fft.py deleted file mode 100755 index a4db0a53d..000000000 --- a/toplevel/mrfm/mrfm_fft.py +++ /dev/null @@ -1,319 +0,0 @@ -#!/usr/bin/env python -# -# This is mrfm_fft_sos.py -# Modification of Matt's mrfm_fft.py that reads filter coefs from file -# -# Copyright 2004,2005 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru -from gnuradio import usrp -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from gnuradio.wxgui import stdgui, fftsink, waterfallsink, scopesink, form, slider -from optparse import OptionParser -import wx -import sys -import mrfm - - -def pick_subdevice(u): - """ - The user didn't specify a subdevice on the command line. - If there's a daughterboard on A, select A. - If there's a daughterboard on B, select B. - Otherwise, select A. - """ - if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a problem - return (0, 0) - if u.db[1][0].dbid() >= 0: - return (1, 0) - return (0, 0) - -def read_ints(filename): - try: - f = open(filename) - ints = [ int(i) for i in f.read().split() ] - f.close() - return ints - except: - return [] - -class app_flow_graph(stdgui.gui_flow_graph): - def __init__(self, frame, panel, vbox, argv): - stdgui.gui_flow_graph.__init__(self) - - self.frame = frame - self.panel = panel - - parser = OptionParser(option_class=eng_option) - parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, - help="select USRP Rx side A or B (default=first one with a daughterboard)") - parser.add_option("-d", "--decim", type="int", default=16, - help="set fgpa decimation rate to DECIM [default=%default]") - parser.add_option("-f", "--freq", type="eng_float", default=None, - help="set frequency to FREQ", metavar="FREQ") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-W", "--waterfall", action="store_true", default=False, - help="Enable waterfall display") - parser.add_option("-8", "--width-8", action="store_true", default=False, - help="Enable 8-bit samples across USB") - parser.add_option("-S", "--oscilloscope", action="store_true", default=False, - help="Enable oscilloscope display") - parser.add_option("-F", "--filename", default=None, - help="Name of file with filter coefficients") - parser.add_option("-C", "--cfilename", default=None, - help="Name of file with compensator coefficients") - parser.add_option("-B", "--bitstream", default="mrfm.rbf", - help="Name of FPGA Bitstream file (.rbf)") - parser.add_option("-n", "--frame-decim", type="int", default=20, - help="set oscope frame decimation factor to n [default=12]") - (options, args) = parser.parse_args() - if len(args) != 0: - parser.print_help() - sys.exit(1) - - self.show_debug_info = True - - # default filter coefs - b00 = b01 = 16384 - b10 = b20 = a10 = a20 = b11 = b21 = a11 = a21 = 0 - - ba = read_ints(options.filename) - if len(ba) >= 6: - b00 = ba[0]; b10 = ba[1]; b20 = ba[2]; a10 = ba[4]; a20 = ba[5] - if len(ba) >= 12: - b01 = ba[6]; b11 = ba[7]; b21 = ba[8]; a11 = ba[10]; a21=ba[11] - print b00, b10, b20, a10, a20, b01, b11, b21, a11, a21 - - # default compensator coefficients - c11 = c22 = 1 - c12 = c21 = cscale = 0 - - cs = read_ints(options.cfilename) - if len(cs) >= 5: - c11 = cs[0]; c12 = cs[1]; c21 = cs[2]; c22 = cs[3]; cscale = cs[4] - print c11, c12, c21, c22, cscale - - # build the graph - self.u = mrfm.source_c(options.bitstream) - - self.u.set_decim_rate(options.decim) - self.u.set_center_freq(options.freq) - - frac_bits = 14 - self.u.set_coeffs(frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11) - - self.u.set_compensator(c11,c12,c21,c22,cscale) - - if options.rx_subdev_spec is None: - options.rx_subdev_spec = pick_subdevice(self.u) - self.u.set_mux(usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec)) - - if options.width_8: - width = 8 - shift = 8 - format = self.u.make_format(width, shift) - print "format =", hex(format) - r = self.u.set_format(format) - print "set_format =", r - - # determine the daughterboard subdevice we're using - self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec) - - #input_rate = self.u.adc_freq() / self.u.decim_rate() - input_rate = self.u.adc_freq() / options.decim - - # fft_rate = 15 - fft_rate = 5 - - self.deint = gr.deinterleave(gr.sizeof_gr_complex) - self.connect(self.u,self.deint) - - if options.waterfall: - self.scope1=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, - fft_rate=fft_rate) - self.scope2=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, - fft_rate=fft_rate) - - elif options.oscilloscope: - self.scope1 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) # added option JPJ 4/21/2006 - self.scope2 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) - - else: - self.scope1 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, - fft_rate=fft_rate) - self.scope2 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, - fft_rate=fft_rate) - - # Show I, I' on top scope panel, Q, Q' on bottom - #self.fin = gr.complex_to_float() - #self.fout = gr.complex_to_float() - - #self.connect((self.deint,0), self.fin) - #self.connect((self.deint,1), self.fout) - - #self.ii = gr.float_to_complex() - #self.qq = gr.float_to_complex() - - #self.connect((self.fin,0), (self.ii,0)) - #self.connect((self.fout,0), (self.ii,1)) - #self.connect((self.fin,1), (self.qq,0)) - #self.connect((self.fout,1), (self.qq,1)) - - #self.connect(self.ii, self.scope1) - #self.connect(self.qq, self.scope2) - - self.connect ((self.deint,0),self.scope1) - self.connect ((self.deint,1),self.scope2) - - self._build_gui(vbox) - - # set initial values - - if options.gain is None: - # if no gain was specified, use the mid-point in dB - g = self.subdev.gain_range() - options.gain = float(g[0]+g[1])/2 - - if options.freq is None: - # if no freq was specified, use the mid-point - r = self.subdev.freq_range() - options.freq = float(r[0]+r[1])/2 - - self.set_gain(options.gain) - - if not(self.set_freq(options.freq)): - self._set_status_msg("Failed to set initial frequency") - - if self.show_debug_info: - self.myform['decim'].set_value(self.u.decim_rate()) - self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) - self.myform['dbname'].set_value(self.subdev.name()) - - - def _set_status_msg(self, msg): - self.frame.GetStatusBar().SetStatusText(msg, 0) - - def _build_gui(self, vbox): - - def _form_set_freq(kv): - return self.set_freq(kv['freq']) - - vbox.Add(self.scope1.win, 10, wx.EXPAND) - vbox.Add(self.scope2.win, 10, wx.EXPAND) - - # add control area at the bottom - self.myform = myform = form.form() - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0, 0) - myform['freq'] = form.float_field( - parent=self.panel, sizer=hbox, label="Center freq", weight=1, - callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) - - hbox.Add((5,0), 0, 0) - g = self.subdev.gain_range() - myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain", - weight=3, - min=int(g[0]), max=int(g[1]), - callback=self.set_gain) - - hbox.Add((5,0), 0, 0) - vbox.Add(hbox, 0, wx.EXPAND) - - self._build_subpanel(vbox) - - def _build_subpanel(self, vbox_arg): - # build a secondary information panel (sometimes hidden) - - # FIXME figure out how to have this be a subpanel that is always - # created, but has its visibility controlled by foo.Show(True/False) - - if not(self.show_debug_info): - return - - panel = self.panel - vbox = vbox_arg - myform = self.myform - - #panel = wx.Panel(self.panel, -1) - #vbox = wx.BoxSizer(wx.VERTICAL) - - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0) - myform['decim'] = form.static_float_field( - parent=panel, sizer=hbox, label="Decim") - - hbox.Add((5,0), 1) - myform['fs@usb'] = form.static_float_field( - parent=panel, sizer=hbox, label="Fs@USB") - - hbox.Add((5,0), 1) - myform['dbname'] = form.static_text_field( - parent=panel, sizer=hbox) - - hbox.Add((5,0), 1) - myform['baseband'] = form.static_float_field( - parent=panel, sizer=hbox, label="Analog BB") - - hbox.Add((5,0), 1) - myform['ddc'] = form.static_float_field( - parent=panel, sizer=hbox, label="DDC") - - hbox.Add((5,0), 0) - vbox.Add(hbox, 0, wx.EXPAND) - - - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - Tuning is a two step process. First we ask the front-end to - tune as close to the desired frequency as it can. Then we use - the result of that operation and our target_frequency to - determine the value for the digital down converter. - """ - r = self.u.tune(0, self.subdev, target_freq) - - if r: - self.myform['freq'].set_value(target_freq) # update displayed value - if self.show_debug_info: - self.myform['baseband'].set_value(r.baseband_freq) - self.myform['ddc'].set_value(r.dxc_freq) - return True - - return False - - def set_gain(self, gain): - self.myform['gain'].set_value(gain) # update displayed value - self.subdev.set_gain(gain) - - -def main (): - app = stdgui.stdapp(app_flow_graph, "USRP FFT", nstatus=1) - app.MainLoop() - -if __name__ == '__main__': - main () diff --git a/toplevel/mrfm/mrfm_proc.v b/toplevel/mrfm/mrfm_proc.v deleted file mode 100644 index 80de9fc90..000000000 --- a/toplevel/mrfm/mrfm_proc.v +++ /dev/null @@ -1,96 +0,0 @@ - -`include "mrfm.vh" -`include "../../../firmware/include/fpga_regs_common.v" -`include "../../../firmware/include/fpga_regs_standard.v" - -module mrfm_proc (input clock, input reset, input enable, - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, - input [15:0] signal_in, output wire [15:0] signal_out, output wire sync_out, - output wire [15:0] i, output wire [15:0] q, - output wire [15:0] ip, output wire [15:0] qp, - output wire strobe_out, output wire [63:0] debugbus); - - // Strobes - wire sample_strobe, strobe_0, strobe_1, strobe_2; - assign sample_strobe = 1'b1; - wire [7:0] rate_0, rate_1, rate_2; - - setting_reg #(`FR_MRFM_DECIM) sr_decim(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out({rate_2,rate_1,rate_0})); - - strobe_gen strobe_gen_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(sample_strobe),.strobe(strobe_0) ); - strobe_gen strobe_gen_1 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_0),.strobe(strobe_1) ); - - wire [31:0] phase; - - assign sync_out = phase[31]; - wire [15:0] i_decim_0, i_decim_1, i_decim_2; - wire [15:0] q_decim_0, q_decim_1, q_decim_2; - - wire [15:0] i_interp_0, i_interp_1, i_interp_2; - wire [15:0] q_interp_0, q_interp_1, q_interp_2; - - wire [15:0] i_filt, q_filt, i_comp, q_comp; - - assign ip=i_comp; - assign qp=q_comp; - - phase_acc #(`FR_MRFM_FREQ,`FR_MRFM_PHASE,32) rx_phase_acc - (.clk(clock),.reset(reset),.enable(enable), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .strobe(sample_strobe),.phase(phase) ); - - cordic rx_cordic (.clock(clock),.reset(reset),.enable(enable), - .xi(signal_in),.yi(16'd0),.zi(phase[31:16]), - .xo(i_decim_0),.yo(q_decim_0),.zo() ); - - cic_decim cic_decim_i_0 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), - .signal_in(i_decim_0),.signal_out(i_decim_1)); - cic_decim cic_decim_i_1 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), - .signal_in(i_decim_1),.signal_out(i)); - - cic_decim cic_decim_q_0 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), - .signal_in(q_decim_0),.signal_out(q_decim_1)); - cic_decim cic_decim_q_1 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), - .signal_in(q_decim_1),.signal_out(q)); - - assign strobe_out = strobe_1; - - biquad_2stage iir_i (.clock(clock),.reset(reset),.strobe_in(strobe_1), - .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), - .sample_in(i),.sample_out(i_filt),.debugbus(debugbus)); - - biquad_2stage iir_q (.clock(clock),.reset(reset),.strobe_in(strobe_1), - .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), - .sample_in(q),.sample_out(q_filt),.debugbus()); - - mrfm_compensator compensator (.clock(clock),.reset(reset),.strobe_in(strobe_1), - .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), - .i_in(i_filt),.q_in(q_filt),.i_out(i_comp),.q_out(q_comp)); - - cic_interp cic_interp_i_0 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), - .signal_in(i_comp),.signal_out(i_interp_0)); - cic_interp cic_interp_i_1 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), - .signal_in(i_interp_0),.signal_out(i_interp_1)); - - cic_interp cic_interp_q_0 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), - .signal_in(q_comp),.signal_out(q_interp_0)); - cic_interp cic_interp_q_1 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), - .signal_in(q_interp_0),.signal_out(q_interp_1)); - - cordic tx_cordic (.clock(clock),.reset(reset),.enable(enable), - .xi(i_interp_1),.yi(q_interp_1),.zi(-phase[31:16]), - .xo(signal_out),.yo(),.zo() ); - -endmodule // mrfm_proc diff --git a/toplevel/mrfm/shifter.v b/toplevel/mrfm/shifter.v deleted file mode 100644 index dd4d4b527..000000000 --- a/toplevel/mrfm/shifter.v +++ /dev/null @@ -1,106 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2005,2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module shifter(input wire [33:0] in, output wire [15:0] out, input wire [7:0] shift); - // Wish we could do assign out = in[15+shift:shift]; - - reg [15:0] quotient, remainder; - wire [15:0] out_unclipped; - reg [18:0] msbs; - wire in_range; - - always @* - case(shift) - 0 : quotient = in[15:0]; - 1 : quotient = in[16:1]; - 2 : quotient = in[17:2]; - 3 : quotient = in[18:3]; - 4 : quotient = in[19:4]; - 5 : quotient = in[20:5]; - 6 : quotient = in[21:6]; - 7 : quotient = in[22:7]; - 8 : quotient = in[23:8]; - 9 : quotient = in[24:9]; - 10 : quotient = in[25:10]; - 11 : quotient = in[26:11]; - 12 : quotient = in[27:12]; - 13 : quotient = in[28:13]; - 14 : quotient = in[29:14]; - 15 : quotient = in[30:15]; - 16 : quotient = in[31:16]; - 17 : quotient = in[32:17]; - 18 : quotient = in[33:18]; - default : quotient = in[15:0]; - endcase // case(shift) - - always @* - case(shift) - 0 : remainder = 16'b0; - 1 : remainder = {in[0],15'b0}; - 2 : remainder = {in[1:0],14'b0}; - 3 : remainder = {in[2:0],13'b0}; - 4 : remainder = {in[3:0],12'b0}; - 5 : remainder = {in[4:0],11'b0}; - 6 : remainder = {in[5:0],10'b0}; - 7 : remainder = {in[6:0],9'b0}; - 8 : remainder = {in[7:0],8'b0}; - 9 : remainder = {in[8:0],7'b0}; - 10 : remainder = {in[9:0],6'b0}; - 11 : remainder = {in[10:0],5'b0}; - 12 : remainder = {in[11:0],4'b0}; - 13 : remainder = {in[12:0],3'b0}; - 14 : remainder = {in[13:0],2'b0}; - 15 : remainder = {in[14:0],1'b0}; - 16 : remainder = in[15:0]; - 17 : remainder = in[16:1]; - 18 : remainder = in[17:2]; - default : remainder = 16'b0; - endcase // case(shift) - - always @* - case(shift) - 0 : msbs = in[33:15]; - 1 : msbs = {in[33],in[33:16]}; - 2 : msbs = {{2{in[33]}},in[33:17]}; - 3 : msbs = {{3{in[33]}},in[33:18]}; - 4 : msbs = {{4{in[33]}},in[33:19]}; - 5 : msbs = {{5{in[33]}},in[33:20]}; - 6 : msbs = {{6{in[33]}},in[33:21]}; - 7 : msbs = {{7{in[33]}},in[33:22]}; - 8 : msbs = {{8{in[33]}},in[33:23]}; - 9 : msbs = {{9{in[33]}},in[33:24]}; - 10 : msbs = {{10{in[33]}},in[33:25]}; - 11 : msbs = {{11{in[33]}},in[33:26]}; - 12 : msbs = {{12{in[33]}},in[33:27]}; - 13 : msbs = {{13{in[33]}},in[33:28]}; - 14 : msbs = {{14{in[33]}},in[33:29]}; - 15 : msbs = {{15{in[33]}},in[33:30]}; - 16 : msbs = {{16{in[33]}},in[33:31]}; - 17 : msbs = {{17{in[33]}},in[33:32]}; - 18 : msbs = {{18{in[33]}},in[33]}; - default : msbs = in[33:15]; - endcase // case(shift) - - assign in_range = &msbs | ~(|msbs); - assign out_unclipped = quotient + (in[33] & |remainder); - assign out = in_range ? out_unclipped : {in[33],{15{~in[33]}}}; - -endmodule // shifter diff --git a/toplevel/sizetest/.gitignore b/toplevel/sizetest/.gitignore deleted file mode 100644 index 201434ddc..000000000 --- a/toplevel/sizetest/.gitignore +++ /dev/null @@ -1,15 +0,0 @@ -/*.qws -/*.eqn -/*.done -/*.htm -/*.rpt -/*.ini -/*.fsf -/*.jam -/*.jbc -/*.pin -/*.pof -/*.sof -/*.rbf -/*.ttf -/db diff --git a/toplevel/sizetest/sizetest.csf b/toplevel/sizetest/sizetest.csf deleted file mode 100644 index 4b724e7f5..000000000 --- a/toplevel/sizetest/sizetest.csf +++ /dev/null @@ -1,160 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = OFF; - OPTIMIZE_TIMING = OFF; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = ON; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |sizetest; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -CHIP(sizetest) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} diff --git a/toplevel/sizetest/sizetest.psf b/toplevel/sizetest/sizetest.psf deleted file mode 100644 index e4fc6aa27..000000000 --- a/toplevel/sizetest/sizetest.psf +++ /dev/null @@ -1,228 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - STRATIX_CARRY_CHAIN_LENGTH = 70; - AUTO_PACKED_REG_CYCLONE = "MINIMIZE AREA WITH CHAINS"; - CYCLONE_OPTIMIZATION_TECHNIQUE = SPEED; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_CLOCK = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - IGNORE_SOFT_BUFFERS = ON; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(sizetest) -{ - USER_LIBRARIES = "e:\fpga\megacells\"; - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "22:00:25 SEPTEMBER 28, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; -} -THIRD_PARTY_EDA_TOOLS(sizetest) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; - EDA_SIMULATION_TOOL = ""; - EDA_TIMING_ANALYSIS_TOOL = ""; - EDA_BOARD_DESIGN_TOOL = ""; - EDA_FORMAL_VERIFICATION_TOOL = ""; - EDA_RESYNTHESIS_TOOL = ""; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} diff --git a/toplevel/sizetest/sizetest.quartus b/toplevel/sizetest/sizetest.quartus deleted file mode 100644 index d1eaf227a..000000000 --- a/toplevel/sizetest/sizetest.quartus +++ /dev/null @@ -1,19 +0,0 @@ -COMPILER_SETTINGS_LIST -{ - COMPILER_SETTINGS = sizetest; -} -SIMULATOR_SETTINGS_LIST -{ - SIMULATOR_SETTINGS = sizetest; -} -SOFTWARE_SETTINGS_LIST -{ - SOFTWARE_SETTINGS = Debug; - SOFTWARE_SETTINGS = Release; -} -FILES -{ - VERILOG_FILE = ..\..\sdr_lib\cordic_stage.v; - VERILOG_FILE = ..\..\sdr_lib\cordic.v; - VERILOG_FILE = sizetest.v; -} diff --git a/toplevel/sizetest/sizetest.ssf b/toplevel/sizetest/sizetest.ssf deleted file mode 100644 index 1aceab1f1..000000000 --- a/toplevel/sizetest/sizetest.ssf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = sizetest; -} diff --git a/toplevel/sizetest/sizetest.v b/toplevel/sizetest/sizetest.v deleted file mode 100644 index 5a847b961..000000000 --- a/toplevel/sizetest/sizetest.v +++ /dev/null @@ -1,39 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -module sizetest(input clock, - input reset, - input enable, - input [15:0]xi, - input [15:0] yi, - input [15:0] zi, - output [15:0] xo, - output [15:0] yo, - output [15:0] zo -// input [15:0] constant - ); - -wire [16:0] zo; - -cordic_stage cordic_stage(clock, reset, enable, xi, yi, zi, 16'd16383, xo, yo, zo ); - -endmodule diff --git a/toplevel/usrp_inband_usb/.gitignore b/toplevel/usrp_inband_usb/.gitignore deleted file mode 100644 index 2cc25f0f2..000000000 --- a/toplevel/usrp_inband_usb/.gitignore +++ /dev/null @@ -1,16 +0,0 @@ -/*.qws -/*.eqn -/*.done -/*.htm -/*.rpt -/*.ini -/*.fsf -/*.jam -/*.jbc -/*.pin -/*.pof -/*.sof -/*.rbf -/*.ttf -/*.summary -/db diff --git a/toplevel/usrp_inband_usb/config.vh b/toplevel/usrp_inband_usb/config.vh deleted file mode 100644 index 007a529e3..000000000 --- a/toplevel/usrp_inband_usb/config.vh +++ /dev/null @@ -1,53 +0,0 @@ - // -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006,2007 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// User control over what parts get included -// -// >>>> EDIT ONLY THIS SECTION <<<< -// Uncomment only ONE configuration -// ==================================================================== - -// ==================================================================== -// FIXME drive configuration selection from the command line and/or gui -// ==================================================================== - -// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel - `include "../include/common_config_1rxhb_1tx.vh" - -// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels -// `include "../include/common_config_2rxhb_2tx.vh" - -// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels -//`include "../include/common_config_4rx_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels -//`include "../include/common_config_2rxhb_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels -//`include "../include/common_config_2rx_0tx.vh" - -// Add other "known to fit" configurations here... - -// ==================================================================== -// Now include the common footer -// ==================================================================== - `include "../include/common_config_bottom.vh" diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.csf b/toplevel/usrp_inband_usb/usrp_inband_usb.csf deleted file mode 100644 index c10cff92c..000000000 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |usrp_inband_usb; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(usrp_inband_usb) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.esf b/toplevel/usrp_inband_usb/usrp_inband_usb.esf deleted file mode 100644 index 6079e9795..000000000 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = usrp_inband_usb; -} diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.psf b/toplevel/usrp_inband_usb/usrp_inband_usb.psf deleted file mode 100644 index 85276ecc4..000000000 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(usrp_inband_usb) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "e:\usrp\fpga\megacells"; -} -THIRD_PARTY_EDA_TOOLS(usrp_inband_usb) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; - EDA_SIMULATION_TOOL = ""; - EDA_TIMING_ANALYSIS_TOOL = ""; - EDA_BOARD_DESIGN_TOOL = ""; - EDA_FORMAL_VERIFICATION_TOOL = ""; - EDA_RESYNTHESIS_TOOL = ""; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qpf b/toplevel/usrp_inband_usb/usrp_inband_usb.qpf deleted file mode 100644 index f6220e320..000000000 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.0" -DATE = "17:10:11 December 20, 2004" - - -# Active Revisions - -PROJECT_REVISION = "usrp_inband_usb" diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf deleted file mode 100644 index ae0807f6f..000000000 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf +++ /dev/null @@ -1,423 +0,0 @@ -# Copyright (C) 1991-2005 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# The default values for assignments are stored in the file -# usrp_inband_usb_assignment_defaults.qdf -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP2" - -# Pin & Location Assignments -# ========================== -set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -set_location_assignment PIN_29 -to SCLK -set_location_assignment PIN_117 -to SDI -set_location_assignment PIN_28 -to usbclk -set_location_assignment PIN_107 -to usbctl[0] -set_location_assignment PIN_106 -to usbctl[1] -set_location_assignment PIN_105 -to usbctl[2] -set_location_assignment PIN_100 -to usbdata[0] -set_location_assignment PIN_84 -to usbdata[10] -set_location_assignment PIN_83 -to usbdata[11] -set_location_assignment PIN_82 -to usbdata[12] -set_location_assignment PIN_79 -to usbdata[13] -set_location_assignment PIN_78 -to usbdata[14] -set_location_assignment PIN_77 -to usbdata[15] -set_location_assignment PIN_99 -to usbdata[1] -set_location_assignment PIN_98 -to usbdata[2] -set_location_assignment PIN_95 -to usbdata[3] -set_location_assignment PIN_94 -to usbdata[4] -set_location_assignment PIN_93 -to usbdata[5] -set_location_assignment PIN_88 -to usbdata[6] -set_location_assignment PIN_87 -to usbdata[7] -set_location_assignment PIN_86 -to usbdata[8] -set_location_assignment PIN_85 -to usbdata[9] -set_location_assignment PIN_104 -to usbrdy[0] -set_location_assignment PIN_101 -to usbrdy[1] -set_location_assignment PIN_76 -to FX2_1 -set_location_assignment PIN_75 -to FX2_2 -set_location_assignment PIN_74 -to FX2_3 -set_location_assignment PIN_116 -to io_rx_a[0] -set_location_assignment PIN_115 -to io_rx_a[1] -set_location_assignment PIN_114 -to io_rx_a[2] -set_location_assignment PIN_113 -to io_rx_a[3] -set_location_assignment PIN_108 -to io_rx_a[4] -set_location_assignment PIN_195 -to io_rx_a[5] -set_location_assignment PIN_196 -to io_rx_a[6] -set_location_assignment PIN_197 -to io_rx_a[7] -set_location_assignment PIN_200 -to io_rx_a[8] -set_location_assignment PIN_201 -to io_rx_a[9] -set_location_assignment PIN_202 -to io_rx_a[10] -set_location_assignment PIN_203 -to io_rx_a[11] -set_location_assignment PIN_206 -to io_rx_a[12] -set_location_assignment PIN_207 -to io_rx_a[13] -set_location_assignment PIN_208 -to io_rx_a[14] -set_location_assignment PIN_214 -to io_rx_b[0] -set_location_assignment PIN_215 -to io_rx_b[1] -set_location_assignment PIN_216 -to io_rx_b[2] -set_location_assignment PIN_217 -to io_rx_b[3] -set_location_assignment PIN_218 -to io_rx_b[4] -set_location_assignment PIN_219 -to io_rx_b[5] -set_location_assignment PIN_222 -to io_rx_b[6] -set_location_assignment PIN_223 -to io_rx_b[7] -set_location_assignment PIN_224 -to io_rx_b[8] -set_location_assignment PIN_225 -to io_rx_b[9] -set_location_assignment PIN_226 -to io_rx_b[10] -set_location_assignment PIN_227 -to io_rx_b[11] -set_location_assignment PIN_228 -to io_rx_b[12] -set_location_assignment PIN_233 -to io_rx_b[13] -set_location_assignment PIN_234 -to io_rx_b[14] -set_location_assignment PIN_175 -to io_tx_a[0] -set_location_assignment PIN_176 -to io_tx_a[1] -set_location_assignment PIN_177 -to io_tx_a[2] -set_location_assignment PIN_178 -to io_tx_a[3] -set_location_assignment PIN_179 -to io_tx_a[4] -set_location_assignment PIN_180 -to io_tx_a[5] -set_location_assignment PIN_181 -to io_tx_a[6] -set_location_assignment PIN_182 -to io_tx_a[7] -set_location_assignment PIN_183 -to io_tx_a[8] -set_location_assignment PIN_184 -to io_tx_a[9] -set_location_assignment PIN_185 -to io_tx_a[10] -set_location_assignment PIN_186 -to io_tx_a[11] -set_location_assignment PIN_187 -to io_tx_a[12] -set_location_assignment PIN_188 -to io_tx_a[13] -set_location_assignment PIN_193 -to io_tx_a[14] -set_location_assignment PIN_73 -to io_tx_b[0] -set_location_assignment PIN_68 -to io_tx_b[1] -set_location_assignment PIN_67 -to io_tx_b[2] -set_location_assignment PIN_66 -to io_tx_b[3] -set_location_assignment PIN_65 -to io_tx_b[4] -set_location_assignment PIN_64 -to io_tx_b[5] -set_location_assignment PIN_63 -to io_tx_b[6] -set_location_assignment PIN_62 -to io_tx_b[7] -set_location_assignment PIN_61 -to io_tx_b[8] -set_location_assignment PIN_60 -to io_tx_b[9] -set_location_assignment PIN_59 -to io_tx_b[10] -set_location_assignment PIN_58 -to io_tx_b[11] -set_location_assignment PIN_57 -to io_tx_b[12] -set_location_assignment PIN_56 -to io_tx_b[13] -set_location_assignment PIN_55 -to io_tx_b[14] -set_location_assignment PIN_152 -to master_clk -set_location_assignment PIN_144 -to rx_a_a[0] -set_location_assignment PIN_143 -to rx_a_a[1] -set_location_assignment PIN_141 -to rx_a_a[2] -set_location_assignment PIN_140 -to rx_a_a[3] -set_location_assignment PIN_139 -to rx_a_a[4] -set_location_assignment PIN_138 -to rx_a_a[5] -set_location_assignment PIN_137 -to rx_a_a[6] -set_location_assignment PIN_136 -to rx_a_a[7] -set_location_assignment PIN_135 -to rx_a_a[8] -set_location_assignment PIN_134 -to rx_a_a[9] -set_location_assignment PIN_133 -to rx_a_a[10] -set_location_assignment PIN_132 -to rx_a_a[11] -set_location_assignment PIN_23 -to rx_a_b[0] -set_location_assignment PIN_21 -to rx_a_b[1] -set_location_assignment PIN_20 -to rx_a_b[2] -set_location_assignment PIN_19 -to rx_a_b[3] -set_location_assignment PIN_18 -to rx_a_b[4] -set_location_assignment PIN_17 -to rx_a_b[5] -set_location_assignment PIN_16 -to rx_a_b[6] -set_location_assignment PIN_15 -to rx_a_b[7] -set_location_assignment PIN_14 -to rx_a_b[8] -set_location_assignment PIN_13 -to rx_a_b[9] -set_location_assignment PIN_12 -to rx_a_b[10] -set_location_assignment PIN_11 -to rx_a_b[11] -set_location_assignment PIN_131 -to rx_b_a[0] -set_location_assignment PIN_128 -to rx_b_a[1] -set_location_assignment PIN_127 -to rx_b_a[2] -set_location_assignment PIN_126 -to rx_b_a[3] -set_location_assignment PIN_125 -to rx_b_a[4] -set_location_assignment PIN_124 -to rx_b_a[5] -set_location_assignment PIN_123 -to rx_b_a[6] -set_location_assignment PIN_122 -to rx_b_a[7] -set_location_assignment PIN_121 -to rx_b_a[8] -set_location_assignment PIN_120 -to rx_b_a[9] -set_location_assignment PIN_119 -to rx_b_a[10] -set_location_assignment PIN_118 -to rx_b_a[11] -set_location_assignment PIN_8 -to rx_b_b[0] -set_location_assignment PIN_7 -to rx_b_b[1] -set_location_assignment PIN_6 -to rx_b_b[2] -set_location_assignment PIN_5 -to rx_b_b[3] -set_location_assignment PIN_4 -to rx_b_b[4] -set_location_assignment PIN_3 -to rx_b_b[5] -set_location_assignment PIN_2 -to rx_b_b[6] -set_location_assignment PIN_240 -to rx_b_b[7] -set_location_assignment PIN_239 -to rx_b_b[8] -set_location_assignment PIN_238 -to rx_b_b[9] -set_location_assignment PIN_237 -to rx_b_b[10] -set_location_assignment PIN_236 -to rx_b_b[11] -set_location_assignment PIN_156 -to SDO -set_location_assignment PIN_153 -to SEN_FPGA -set_location_assignment PIN_159 -to tx_a[0] -set_location_assignment PIN_160 -to tx_a[1] -set_location_assignment PIN_161 -to tx_a[2] -set_location_assignment PIN_162 -to tx_a[3] -set_location_assignment PIN_163 -to tx_a[4] -set_location_assignment PIN_164 -to tx_a[5] -set_location_assignment PIN_165 -to tx_a[6] -set_location_assignment PIN_166 -to tx_a[7] -set_location_assignment PIN_167 -to tx_a[8] -set_location_assignment PIN_168 -to tx_a[9] -set_location_assignment PIN_169 -to tx_a[10] -set_location_assignment PIN_170 -to tx_a[11] -set_location_assignment PIN_173 -to tx_a[12] -set_location_assignment PIN_174 -to tx_a[13] -set_location_assignment PIN_38 -to tx_b[0] -set_location_assignment PIN_39 -to tx_b[1] -set_location_assignment PIN_41 -to tx_b[2] -set_location_assignment PIN_42 -to tx_b[3] -set_location_assignment PIN_43 -to tx_b[4] -set_location_assignment PIN_44 -to tx_b[5] -set_location_assignment PIN_45 -to tx_b[6] -set_location_assignment PIN_46 -to tx_b[7] -set_location_assignment PIN_47 -to tx_b[8] -set_location_assignment PIN_48 -to tx_b[9] -set_location_assignment PIN_49 -to tx_b[10] -set_location_assignment PIN_50 -to tx_b[11] -set_location_assignment PIN_53 -to tx_b[12] -set_location_assignment PIN_54 -to tx_b[13] -set_location_assignment PIN_158 -to TXSYNC_A -set_location_assignment PIN_37 -to TXSYNC_B -set_location_assignment PIN_235 -to io_rx_b[15] -set_location_assignment PIN_24 -to io_tx_b[15] -set_location_assignment PIN_213 -to io_rx_a[15] -set_location_assignment PIN_194 -to io_tx_a[15] -set_location_assignment PIN_1 -to MYSTERY_SIGNAL - -# Timing Assignments -# ================== -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name TOP_LEVEL_ENTITY usrp_inband_usb -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP1C12Q240C8 -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name INC_PLC_MODE OFF -set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF -set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -# Timing Analysis Assignments -# =========================== -set_global_assignment -name MAX_SCC_SIZE 50 - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" -set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF - -# Simulator Assignments -# ===================== -set_global_assignment -name START_TIME "0 ns" -set_global_assignment -name GLITCH_INTERVAL "1 ns" - -# Design Assistant Assignments -# ============================ -set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF -set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF -set_global_assignment -name ASSG_CAT OFF -set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF -set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF -set_global_assignment -name CLK_CAT OFF -set_global_assignment -name CLK_RULE_COMB_CLOCK OFF -set_global_assignment -name CLK_RULE_INV_CLOCK OFF -set_global_assignment -name CLK_RULE_GATING_SCHEME OFF -set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF -set_global_assignment -name CLK_RULE_MIX_EDGES OFF -set_global_assignment -name RESET_CAT OFF -set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name TIMING_CAT OFF -set_global_assignment -name TIMING_RULE_SHIFT_REG OFF -set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF -set_global_assignment -name NONSYNCHSTRUCT_CAT OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF -set_global_assignment -name SIGNALRACE_CAT OFF -set_global_assignment -name ACLK_CAT OFF -set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF -set_global_assignment -name HCPY_CAT OFF -set_global_assignment -name HCPY_VREF_PINS OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name HUB_ENTITY_NAME SLD_HUB -set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP OFF - -# LogicLock Region Assignments -# ============================ -set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF - -# ----------------- -# start CLOCK(SCLK) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK -set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK - -# end CLOCK(SCLK) -# --------------- - -# ----------------------- -# start CLOCK(master_clk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk -set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk - -# end CLOCK(master_clk) -# --------------------- - -# ------------------- -# start CLOCK(usbclk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk -set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk - -# end CLOCK(usbclk) -# ----------------- - -# ---------------------- -# start ENTITY(usrp_inband_usb) - - # Timing Assignments - # ================== -set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK -set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk -set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk - -# end ENTITY(usrp_inband_usb) -# -------------------- - - -set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4kx16_dc.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v -set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v -set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v -set_global_assignment -name VERILOG_FILE usrp_inband_usb.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v -set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.v b/toplevel/usrp_inband_usb/usrp_inband_usb.v deleted file mode 100644 index 79f0dfa4a..000000000 --- a/toplevel/usrp_inband_usb/usrp_inband_usb.v +++ /dev/null @@ -1,428 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2004 Matt Ettus -// Copyright 2007 Free Software Foundation, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// -`define TX_IN_BAND -`define RX_IN_BAND - -`include "config.vh" -`include "../../../firmware/include/fpga_regs_common.v" -`include "../../../firmware/include/fpga_regs_standard.v" - -module usrp_inband_usb -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64,clk128; - - wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_space, have_pkt_rdy; - assign usbrdy[0] = have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = (tx_underrun == 0); - - wire [15:0] usbdata_out; - - wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; - - wire tx_realsignals; - wire [3:0] rx_numchan; - wire [2:0] tx_numchan; - - wire [7:0] interp_rate, decim_rate; - wire [15:0] tx_debugbus, rx_debugbus; - - wire enable_tx, enable_rx; - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - wire [7:0] settings; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; - wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; - - // TX - wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; - wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; - - wire strobe_interp, tx_sample_strobe; - wire tx_empty; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - reg [15:0] debug_counter; - reg [15:0] loopback_i_0,loopback_q_0; - - - //Connection RX inband <-> TX inband - wire rx_WR; - wire [15:0] rx_databus; - wire rx_WR_done; - wire rx_WR_enabled; - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Transmit Side -`ifdef TX_ON - assign bb_tx_i0 = ch0tx; - assign bb_tx_q0 = ch1tx; - assign bb_tx_i1 = ch2tx; - assign bb_tx_q1 = ch3tx; - -wire [1:0] tx_underrun; - -`ifdef TX_IN_BAND - tx_buffer_inband tx_buffer - ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), - .usbdata(usbdata),.WR(WR),.have_space(have_space), - .tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}), - .tx_i_0(ch0tx),.tx_q_0(ch1tx), - .tx_i_1(ch2tx),.tx_q_1(ch3tx), - .tx_i_2(),.tx_q_2(), - .tx_i_3(),.tx_q_3(), - .txclk(clk64),.txstrobe(strobe_interp), - .clear_status(clear_status), - .tx_empty(tx_empty), - .rx_WR(rx_WR), - .rx_databus(rx_databus), - .rx_WR_done(rx_WR_done), - .rx_WR_enabled(rx_WR_enabled), - .reg_addr(reg_addr), - .reg_data_out(reg_data_out), - .reg_data_in(reg_data_in), - .reg_io_enable(reg_io_enable), - .debugbus(rx_debugbus), - .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), - .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait), - .stop(stop), .stop_time(stop_time)); - - `ifdef TX_DUAL - defparam tx_buffer.NUM_CHAN=2; - `endif - -`else - tx_buffer tx_buffer - ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), - .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), - .channels({tx_numchan,1'b0}), - .tx_i_0(ch0tx),.tx_q_0(ch1tx), - .tx_i_1(ch2tx),.tx_q_1(ch3tx), - .tx_i_2(),.tx_q_2(), - .tx_i_3(),.tx_q_3(), - .txclk(clk64),.txstrobe(strobe_interp), - .clear_status(clear_status), - .tx_empty(tx_empty)); -`endif - - `ifdef TX_EN_0 - tx_chain tx_chain_0 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), - .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); - `else - assign i_out_0=16'd0; - assign q_out_0=16'd0; - `endif - - `ifdef TX_EN_1 - tx_chain tx_chain_1 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), - .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); - `else - assign i_out_1=16'd0; - assign q_out_1=16'd0; - `endif - - setting_reg #(`FR_TX_MUX) - sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); - - wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; - - wire txsync = tx_sample_strobe; - assign TXSYNC_A = txsync; - assign TXSYNC_B = txsync; - - assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; - assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; -`endif // `ifdef TX_ON - - ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Receive Side -`ifdef RX_ON - wire rx_sample_strobe,strobe_decim,hb_strobe; - wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, - bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; - - wire loopback = settings[0]; - wire counter = settings[1]; - - always @(posedge clk64) - if(rx_dsp_reset) - debug_counter <= #1 16'd0; - else if(~enable_rx) - debug_counter <= #1 16'd0; - else if(hb_strobe) - debug_counter <=#1 debug_counter + 16'd2; - - always @(posedge clk64) - if(strobe_interp) - begin - loopback_i_0 <= #1 ch0tx; - loopback_q_0 <= #1 ch1tx; - end - - assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; - assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; - assign ch2rx = bb_rx_i1; - assign ch3rx = bb_rx_q1; - assign ch4rx = bb_rx_i2; - assign ch5rx = bb_rx_q2; - assign ch6rx = bb_rx_i3; - assign ch7rx = bb_rx_q3; - - wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; - wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; - adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), - .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3), - .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), - .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), - .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), - .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan)); - `ifdef RX_IN_BAND - rx_buffer_inband rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .reset_regs(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(ch0rx),.ch_1(ch1rx), - .ch_2(ch2rx),.ch_3(ch3rx), - .ch_4(ch4rx),.ch_5(ch5rx), - .ch_6(ch6rx),.ch_7(ch7rx), - .rxclk(clk64),.rxstrobe(hb_strobe), - .clear_status(clear_status), - .rx_WR(rx_WR), - .rx_databus(rx_databus), - .rx_WR_done(rx_WR_done), - .rx_WR_enabled(rx_WR_enabled), - .debugbus(tx_debugbus), - .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3), - .tx_underrun(tx_underrun)); - - `ifdef RX_DUAL - defparam rx_buffer.NUM_CHAN=2; - `endif - - `else - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .reset_regs(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(ch0rx),.ch_1(ch1rx), - .ch_2(ch2rx),.ch_3(ch3rx), - .ch_4(ch4rx),.ch_5(ch5rx), - .ch_6(ch6rx),.ch_7(ch7rx), - .rxclk(clk64),.rxstrobe(hb_strobe), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - `endif - - `ifdef RX_EN_0 - rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); - `else - assign bb_rx_i0=16'd0; - assign bb_rx_q0=16'd0; - `endif - - `ifdef RX_EN_1 - rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); - `else - assign bb_rx_i1=16'd0; - assign bb_rx_q1=16'd0; - `endif - - `ifdef RX_EN_2 - rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); - `else - assign bb_rx_i2=16'd0; - assign bb_rx_q2=16'd0; - `endif - - `ifdef RX_EN_3 - rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); - `else - assign bb_rx_i3=16'd0; - assign bb_rx_q3=16'd0; - `endif - -`endif // `ifdef RX_ON - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities; - assign capabilities[7] = `TX_CAP_HB; - assign capabilities[6:4] = `TX_CAP_NCHAN; - assign capabilities[3] = `RX_CAP_HB; - assign capabilities[2:0] = `RX_CAP_NCHAN; - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), - .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) - ); - - wire [6:0] reg_addr; - wire [31:0] reg_data_out; - wire [31:0] reg_data_in; - wire [1:0] reg_io_enable; - wire [31:0] rssi_threshhold; - wire [31:0] rssi_wait; - wire [6:0] addr_wr; - wire [31:0] data_wr; - wire strobe_wr; - wire [6:0] addr_db; - wire [31:0] data_db; - wire strobe_db; - assign serial_strobe = strobe_db | strobe_wr; - assign serial_addr = (strobe_db)? (addr_db) : (addr_wr); - assign serial_data = (strobe_db)? (data_db) : (data_wr); - //assign serial_strobe = strobe_wr; - //assign serial_data = data_wr; - //assign serial_addr = addr_wr; - - register_io register_control - (.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in), - .dataout(reg_data_out), .addr_wr(addr_wr), .data_wr(data_wr), .strobe_wr(strobe_wr), - .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), - .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .debug_en(debug_en), .misc(settings), - .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); - - - //implementing freeze mode - reg [15:0] timestop; - wire stop; - wire [15:0] stop_time; - assign clk64 = (timestop == 0) ? master_clk : 0; - always @(posedge master_clk) - if (timestop[15:0] != 0) - timestop <= timestop - 16'd1; - else if (stop) - timestop <= stop_time; - - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), - .tx_empty(tx_empty), - //.debug_0(rx_a_a),.debug_1(ddc0_in_i), - .debug_0(rx_debugbus),.debug_1(ddc0_in_i), - .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - - io_pins io_pins - (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Misc Settings - setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); - -endmodule // usrp_inband_usb diff --git a/toplevel/usrp_multi/.gitignore b/toplevel/usrp_multi/.gitignore deleted file mode 100644 index 2cc25f0f2..000000000 --- a/toplevel/usrp_multi/.gitignore +++ /dev/null @@ -1,16 +0,0 @@ -/*.qws -/*.eqn -/*.done -/*.htm -/*.rpt -/*.ini -/*.fsf -/*.jam -/*.jbc -/*.pin -/*.pof -/*.sof -/*.rbf -/*.ttf -/*.summary -/db diff --git a/toplevel/usrp_multi/config.vh b/toplevel/usrp_multi/config.vh deleted file mode 100644 index 07011bd48..000000000 --- a/toplevel/usrp_multi/config.vh +++ /dev/null @@ -1,62 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006,2007 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// User control over what parts get included -// -// >>>> EDIT ONLY THIS SECTION <<<< -// Uncomment only ONE configuration -// ==================================================================== - -// ==================================================================== -// FIXME drive configuration selection from the command line and/or gui -// ==================================================================== - -`define MULTI_ON // enable multi usrp configuration - -// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel -//`include "../include/common_config_1rxhb_1tx.vh" - -// Uncomment this for multi with 2 rx channels (w/ halfband) & 2 transmit channels -`include "../include/common_config_2rxhb_2tx.vh" - -// Uncomment this for multi with 4 rx channels (w/o halfband) & 0 transmit channels -//`include "../include/common_config_4rx_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels -//`include "../include/common_config_2rxhb_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels -//`include "../include/common_config_2rx_0tx.vh" - - -// Add other "known to fit" configurations here... - -// ==================================================================== -// Now include the common footer -// ==================================================================== - -`ifdef MULTI_ON - `define COUNTER_32BIT_ON -`endif - -`include "../include/common_config_bottom.vh" diff --git a/toplevel/usrp_multi/usrp_multi.csf b/toplevel/usrp_multi/usrp_multi.csf deleted file mode 100644 index 2f5df2bca..000000000 --- a/toplevel/usrp_multi/usrp_multi.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |usrp_multi; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(usrp_multi) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/toplevel/usrp_multi/usrp_multi.esf b/toplevel/usrp_multi/usrp_multi.esf deleted file mode 100644 index df45f676b..000000000 --- a/toplevel/usrp_multi/usrp_multi.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = usrp_multi; -} diff --git a/toplevel/usrp_multi/usrp_multi.psf b/toplevel/usrp_multi/usrp_multi.psf deleted file mode 100644 index 68c2d12f9..000000000 --- a/toplevel/usrp_multi/usrp_multi.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(usrp_multi) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "e:\usrp\fpga\megacells"; -} -THIRD_PARTY_EDA_TOOLS(usrp_multi) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; - EDA_SIMULATION_TOOL = ""; - EDA_TIMING_ANALYSIS_TOOL = ""; - EDA_BOARD_DESIGN_TOOL = ""; - EDA_FORMAL_VERIFICATION_TOOL = ""; - EDA_RESYNTHESIS_TOOL = ""; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/toplevel/usrp_multi/usrp_multi.qpf b/toplevel/usrp_multi/usrp_multi.qpf deleted file mode 100644 index 1524de1bb..000000000 --- a/toplevel/usrp_multi/usrp_multi.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.0" -DATE = "17:10:11 December 20, 2004" - - -# Active Revisions - -PROJECT_REVISION = "usrp_multi" diff --git a/toplevel/usrp_multi/usrp_multi.qsf b/toplevel/usrp_multi/usrp_multi.qsf deleted file mode 100644 index 9f0efbd83..000000000 --- a/toplevel/usrp_multi/usrp_multi.qsf +++ /dev/null @@ -1,408 +0,0 @@ -# Copyright (C) 1991-2005 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# The default values for assignments are stored in the file -# usrp_multi_assignment_defaults.qdf -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION 6.1 - -# Pin & Location Assignments -# ========================== -set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -set_location_assignment PIN_29 -to SCLK -set_location_assignment PIN_117 -to SDI -set_location_assignment PIN_28 -to usbclk -set_location_assignment PIN_107 -to usbctl[0] -set_location_assignment PIN_106 -to usbctl[1] -set_location_assignment PIN_105 -to usbctl[2] -set_location_assignment PIN_100 -to usbdata[0] -set_location_assignment PIN_84 -to usbdata[10] -set_location_assignment PIN_83 -to usbdata[11] -set_location_assignment PIN_82 -to usbdata[12] -set_location_assignment PIN_79 -to usbdata[13] -set_location_assignment PIN_78 -to usbdata[14] -set_location_assignment PIN_77 -to usbdata[15] -set_location_assignment PIN_99 -to usbdata[1] -set_location_assignment PIN_98 -to usbdata[2] -set_location_assignment PIN_95 -to usbdata[3] -set_location_assignment PIN_94 -to usbdata[4] -set_location_assignment PIN_93 -to usbdata[5] -set_location_assignment PIN_88 -to usbdata[6] -set_location_assignment PIN_87 -to usbdata[7] -set_location_assignment PIN_86 -to usbdata[8] -set_location_assignment PIN_85 -to usbdata[9] -set_location_assignment PIN_104 -to usbrdy[0] -set_location_assignment PIN_101 -to usbrdy[1] -set_location_assignment PIN_76 -to FX2_1 -set_location_assignment PIN_75 -to FX2_2 -set_location_assignment PIN_74 -to FX2_3 -set_location_assignment PIN_116 -to io_rx_a[0] -set_location_assignment PIN_115 -to io_rx_a[1] -set_location_assignment PIN_114 -to io_rx_a[2] -set_location_assignment PIN_113 -to io_rx_a[3] -set_location_assignment PIN_108 -to io_rx_a[4] -set_location_assignment PIN_195 -to io_rx_a[5] -set_location_assignment PIN_196 -to io_rx_a[6] -set_location_assignment PIN_197 -to io_rx_a[7] -set_location_assignment PIN_200 -to io_rx_a[8] -set_location_assignment PIN_201 -to io_rx_a[9] -set_location_assignment PIN_202 -to io_rx_a[10] -set_location_assignment PIN_203 -to io_rx_a[11] -set_location_assignment PIN_206 -to io_rx_a[12] -set_location_assignment PIN_207 -to io_rx_a[13] -set_location_assignment PIN_208 -to io_rx_a[14] -set_location_assignment PIN_214 -to io_rx_b[0] -set_location_assignment PIN_215 -to io_rx_b[1] -set_location_assignment PIN_216 -to io_rx_b[2] -set_location_assignment PIN_217 -to io_rx_b[3] -set_location_assignment PIN_218 -to io_rx_b[4] -set_location_assignment PIN_219 -to io_rx_b[5] -set_location_assignment PIN_222 -to io_rx_b[6] -set_location_assignment PIN_223 -to io_rx_b[7] -set_location_assignment PIN_224 -to io_rx_b[8] -set_location_assignment PIN_225 -to io_rx_b[9] -set_location_assignment PIN_226 -to io_rx_b[10] -set_location_assignment PIN_227 -to io_rx_b[11] -set_location_assignment PIN_228 -to io_rx_b[12] -set_location_assignment PIN_233 -to io_rx_b[13] -set_location_assignment PIN_234 -to io_rx_b[14] -set_location_assignment PIN_175 -to io_tx_a[0] -set_location_assignment PIN_176 -to io_tx_a[1] -set_location_assignment PIN_177 -to io_tx_a[2] -set_location_assignment PIN_178 -to io_tx_a[3] -set_location_assignment PIN_179 -to io_tx_a[4] -set_location_assignment PIN_180 -to io_tx_a[5] -set_location_assignment PIN_181 -to io_tx_a[6] -set_location_assignment PIN_182 -to io_tx_a[7] -set_location_assignment PIN_183 -to io_tx_a[8] -set_location_assignment PIN_184 -to io_tx_a[9] -set_location_assignment PIN_185 -to io_tx_a[10] -set_location_assignment PIN_186 -to io_tx_a[11] -set_location_assignment PIN_187 -to io_tx_a[12] -set_location_assignment PIN_188 -to io_tx_a[13] -set_location_assignment PIN_193 -to io_tx_a[14] -set_location_assignment PIN_73 -to io_tx_b[0] -set_location_assignment PIN_68 -to io_tx_b[1] -set_location_assignment PIN_67 -to io_tx_b[2] -set_location_assignment PIN_66 -to io_tx_b[3] -set_location_assignment PIN_65 -to io_tx_b[4] -set_location_assignment PIN_64 -to io_tx_b[5] -set_location_assignment PIN_63 -to io_tx_b[6] -set_location_assignment PIN_62 -to io_tx_b[7] -set_location_assignment PIN_61 -to io_tx_b[8] -set_location_assignment PIN_60 -to io_tx_b[9] -set_location_assignment PIN_59 -to io_tx_b[10] -set_location_assignment PIN_58 -to io_tx_b[11] -set_location_assignment PIN_57 -to io_tx_b[12] -set_location_assignment PIN_56 -to io_tx_b[13] -set_location_assignment PIN_55 -to io_tx_b[14] -set_location_assignment PIN_152 -to master_clk -set_location_assignment PIN_144 -to rx_a_a[0] -set_location_assignment PIN_143 -to rx_a_a[1] -set_location_assignment PIN_141 -to rx_a_a[2] -set_location_assignment PIN_140 -to rx_a_a[3] -set_location_assignment PIN_139 -to rx_a_a[4] -set_location_assignment PIN_138 -to rx_a_a[5] -set_location_assignment PIN_137 -to rx_a_a[6] -set_location_assignment PIN_136 -to rx_a_a[7] -set_location_assignment PIN_135 -to rx_a_a[8] -set_location_assignment PIN_134 -to rx_a_a[9] -set_location_assignment PIN_133 -to rx_a_a[10] -set_location_assignment PIN_132 -to rx_a_a[11] -set_location_assignment PIN_23 -to rx_a_b[0] -set_location_assignment PIN_21 -to rx_a_b[1] -set_location_assignment PIN_20 -to rx_a_b[2] -set_location_assignment PIN_19 -to rx_a_b[3] -set_location_assignment PIN_18 -to rx_a_b[4] -set_location_assignment PIN_17 -to rx_a_b[5] -set_location_assignment PIN_16 -to rx_a_b[6] -set_location_assignment PIN_15 -to rx_a_b[7] -set_location_assignment PIN_14 -to rx_a_b[8] -set_location_assignment PIN_13 -to rx_a_b[9] -set_location_assignment PIN_12 -to rx_a_b[10] -set_location_assignment PIN_11 -to rx_a_b[11] -set_location_assignment PIN_131 -to rx_b_a[0] -set_location_assignment PIN_128 -to rx_b_a[1] -set_location_assignment PIN_127 -to rx_b_a[2] -set_location_assignment PIN_126 -to rx_b_a[3] -set_location_assignment PIN_125 -to rx_b_a[4] -set_location_assignment PIN_124 -to rx_b_a[5] -set_location_assignment PIN_123 -to rx_b_a[6] -set_location_assignment PIN_122 -to rx_b_a[7] -set_location_assignment PIN_121 -to rx_b_a[8] -set_location_assignment PIN_120 -to rx_b_a[9] -set_location_assignment PIN_119 -to rx_b_a[10] -set_location_assignment PIN_118 -to rx_b_a[11] -set_location_assignment PIN_8 -to rx_b_b[0] -set_location_assignment PIN_7 -to rx_b_b[1] -set_location_assignment PIN_6 -to rx_b_b[2] -set_location_assignment PIN_5 -to rx_b_b[3] -set_location_assignment PIN_4 -to rx_b_b[4] -set_location_assignment PIN_3 -to rx_b_b[5] -set_location_assignment PIN_2 -to rx_b_b[6] -set_location_assignment PIN_240 -to rx_b_b[7] -set_location_assignment PIN_239 -to rx_b_b[8] -set_location_assignment PIN_238 -to rx_b_b[9] -set_location_assignment PIN_237 -to rx_b_b[10] -set_location_assignment PIN_236 -to rx_b_b[11] -set_location_assignment PIN_156 -to SDO -set_location_assignment PIN_153 -to SEN_FPGA -set_location_assignment PIN_159 -to tx_a[0] -set_location_assignment PIN_160 -to tx_a[1] -set_location_assignment PIN_161 -to tx_a[2] -set_location_assignment PIN_162 -to tx_a[3] -set_location_assignment PIN_163 -to tx_a[4] -set_location_assignment PIN_164 -to tx_a[5] -set_location_assignment PIN_165 -to tx_a[6] -set_location_assignment PIN_166 -to tx_a[7] -set_location_assignment PIN_167 -to tx_a[8] -set_location_assignment PIN_168 -to tx_a[9] -set_location_assignment PIN_169 -to tx_a[10] -set_location_assignment PIN_170 -to tx_a[11] -set_location_assignment PIN_173 -to tx_a[12] -set_location_assignment PIN_174 -to tx_a[13] -set_location_assignment PIN_38 -to tx_b[0] -set_location_assignment PIN_39 -to tx_b[1] -set_location_assignment PIN_41 -to tx_b[2] -set_location_assignment PIN_42 -to tx_b[3] -set_location_assignment PIN_43 -to tx_b[4] -set_location_assignment PIN_44 -to tx_b[5] -set_location_assignment PIN_45 -to tx_b[6] -set_location_assignment PIN_46 -to tx_b[7] -set_location_assignment PIN_47 -to tx_b[8] -set_location_assignment PIN_48 -to tx_b[9] -set_location_assignment PIN_49 -to tx_b[10] -set_location_assignment PIN_50 -to tx_b[11] -set_location_assignment PIN_53 -to tx_b[12] -set_location_assignment PIN_54 -to tx_b[13] -set_location_assignment PIN_158 -to TXSYNC_A -set_location_assignment PIN_37 -to TXSYNC_B -set_location_assignment PIN_235 -to io_rx_b[15] -set_location_assignment PIN_24 -to io_tx_b[15] -set_location_assignment PIN_213 -to io_rx_a[15] -set_location_assignment PIN_194 -to io_tx_a[15] -set_location_assignment PIN_1 -to MYSTERY_SIGNAL - -# Timing Assignments -# ================== -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name TOP_LEVEL_ENTITY usrp_multi -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name USER_LIBRARIES "H:\\usrp-for2.7\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP1C12Q240C8 -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name INC_PLC_MODE OFF -set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF -set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -# Timing Analysis Assignments -# =========================== -set_global_assignment -name MAX_SCC_SIZE 50 - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" -set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF - -# Simulator Assignments -# ===================== -set_global_assignment -name START_TIME "0 ns" -set_global_assignment -name GLITCH_INTERVAL "1 ns" - -# Design Assistant Assignments -# ============================ -set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF -set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF -set_global_assignment -name ASSG_CAT OFF -set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF -set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF -set_global_assignment -name CLK_CAT OFF -set_global_assignment -name CLK_RULE_COMB_CLOCK OFF -set_global_assignment -name CLK_RULE_INV_CLOCK OFF -set_global_assignment -name CLK_RULE_GATING_SCHEME OFF -set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF -set_global_assignment -name CLK_RULE_MIX_EDGES OFF -set_global_assignment -name RESET_CAT OFF -set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name TIMING_CAT OFF -set_global_assignment -name TIMING_RULE_SHIFT_REG OFF -set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF -set_global_assignment -name NONSYNCHSTRUCT_CAT OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF -set_global_assignment -name SIGNALRACE_CAT OFF -set_global_assignment -name ACLK_CAT OFF -set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF -set_global_assignment -name HCPY_CAT OFF -set_global_assignment -name HCPY_VREF_PINS OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name HUB_ENTITY_NAME SLD_HUB -set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP OFF - -# LogicLock Region Assignments -# ============================ -set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF - -# ----------------- -# start CLOCK(SCLK) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK -set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK - -# end CLOCK(SCLK) -# --------------- - -# ----------------------- -# start CLOCK(master_clk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk -set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk - -# end CLOCK(master_clk) -# --------------------- - -# ------------------- -# start CLOCK(usbclk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk -set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk - -# end CLOCK(usbclk) -# ----------------- - -# ---------------------- -# start ENTITY(usrp_multi) - - # Timing Assignments - # ================== -set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK -set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk -set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk - -# end ENTITY(usrp_multi) -# -------------------- - - -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg_masked.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control_multi.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v -set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v -set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v -set_global_assignment -name VERILOG_FILE usrp_multi.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file diff --git a/toplevel/usrp_multi/usrp_multi.v b/toplevel/usrp_multi/usrp_multi.v deleted file mode 100644 index ce484fc1c..000000000 --- a/toplevel/usrp_multi/usrp_multi.v +++ /dev/null @@ -1,379 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2004,2005,2006 Matt Ettus -// Copyright (C) 2006 Martin Dudok van Heel -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Top level module for a full setup with DUCs and DDCs - -// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins -// for debugging info. NB, This can kill the m'board and/or d'board if you -// have anything except basic d'boards installed. - -// Uncomment the following to include optional circuitry - -`include "config.vh" -`include "../../../firmware/include/fpga_regs_common.v" -`include "../../../firmware/include/fpga_regs_standard.v" - -module usrp_multi -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64,clk128; - - wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_space, have_pkt_rdy; - assign usbrdy[0] = have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire tx_underrun, rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = tx_underrun; - - wire [15:0] usbdata_out; - - wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; - - wire tx_realsignals; - wire [3:0] rx_numchan; - wire [2:0] tx_numchan; - - wire [7:0] interp_rate, decim_rate; - wire [15:0] tx_debugbus, rx_debugbus; - - wire enable_tx, enable_rx; - wire reset_data; -`ifdef MULTI_ON - wire sync_rx; - assign reset_data = sync_rx; -`else - assign reset_data = 1'b0; -`endif // `ifdef MULTI_ON - - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - wire [7:0] settings; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - assign clk64 = master_clk; - - wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; - wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; - - // TX - wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; - wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; - - wire strobe_interp, tx_sample_strobe; - wire tx_empty; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - reg [15:0] debug_counter; -`ifdef COUNTER_32BIT_ON - reg [31:0] sample_counter_32bit; -`endif // `ifdef COUNTER_32BIT_ON - reg [15:0] loopback_i_0,loopback_q_0; - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Transmit Side -`ifdef TX_ON - assign bb_tx_i0 = ch0tx; - assign bb_tx_q0 = ch1tx; - assign bb_tx_i1 = ch2tx; - assign bb_tx_q1 = ch3tx; - - tx_buffer tx_buffer - ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), - .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), - .channels({tx_numchan,1'b0}), - .tx_i_0(ch0tx),.tx_q_0(ch1tx), - .tx_i_1(ch2tx),.tx_q_1(ch3tx), - .tx_i_2(),.tx_q_2(), - .tx_i_3(),.tx_q_3(), - .txclk(clk64),.txstrobe(strobe_interp), - .clear_status(clear_status), - .tx_empty(tx_empty), - .debugbus(tx_debugbus) ); - - tx_chain tx_chain_0 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), - .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); - - tx_chain tx_chain_1 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), - .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); - - setting_reg #(`FR_TX_MUX) - sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); - - wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; - - wire txsync = tx_sample_strobe; - assign TXSYNC_A = txsync; - assign TXSYNC_B = txsync; - - assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; - assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; -`endif // `ifdef TX_ON - - ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Receive Side -`ifdef RX_ON - wire rx_sample_strobe,strobe_decim,hb_strobe; - wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, - bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; - - wire loopback = settings[0]; - wire counter = settings[1]; -`ifdef COUNTER_32BIT_ON - wire counter_32bit = settings[2]; - - always @(posedge clk64) - if(rx_dsp_reset) - sample_counter_32bit <= #1 32'd0; - else if(~enable_rx | reset_data) - sample_counter_32bit <=#1 32'd0; - else if(hb_strobe) - sample_counter_32bit <=#1 sample_counter_32bit + 32'd1; -`endif // `ifdef COUNTER_32BIT_ON - - always @(posedge clk64) - if(rx_dsp_reset) - debug_counter <= #1 16'd0; - else if(~enable_rx) - debug_counter <= #1 16'd0; - else if(hb_strobe) - debug_counter <=#1 debug_counter + 16'd2; - - always @(posedge clk64) - if(strobe_interp) - begin - loopback_i_0 <= #1 ch0tx; - loopback_q_0 <= #1 ch1tx; - end - -`ifdef COUNTER_32BIT_ON - assign ch0rx = counter_32bit?sample_counter_32bit[31:16]:counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; - assign ch1rx = counter_32bit?sample_counter_32bit[15:0]:counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; - assign ch2rx = bb_rx_i1; - assign ch3rx = bb_rx_q1; - assign ch4rx = counter_32bit?bb_rx_i0:bb_rx_i2; - assign ch5rx = counter_32bit?bb_rx_q0:bb_rx_q2;// If using counter replicate channels here to be able to get rx_i0 when using counter - //This means if you use 4 channels that channel 3 will be replaced by channel 0 - // and channel 0 will output the 32 bit counter. - assign ch6rx = bb_rx_i3; - assign ch7rx = bb_rx_q3; -`else - assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; - assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; - assign ch2rx = bb_rx_i1; - assign ch3rx = bb_rx_q1; - assign ch4rx = bb_rx_i2; - assign ch5rx = bb_rx_q2; - assign ch6rx = bb_rx_i3; - assign ch7rx = bb_rx_q3; -`endif // `ifdef COUNTER_32BIT_ON - - - wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; - adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), - .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), - .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), - .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), - .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); - - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset | reset_data), - .reset_regs(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(ch0rx),.ch_1(ch1rx), - .ch_2(ch2rx),.ch_3(ch3rx), - .ch_4(ch4rx),.ch_5(ch5rx), - .ch_6(ch6rx),.ch_7(ch7rx), - .rxclk(clk64),.rxstrobe(hb_strobe), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus(rx_debugbus) ); - - `ifdef RX_EN_0 - rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 - ( .clock(clk64),.reset(reset_data),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); - `else - assign bb_rx_i0=16'd0; - assign bb_rx_q0=16'd0; - `endif - - `ifdef RX_EN_1 - rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 - ( .clock(clk64),.reset(reset_data),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); - `else - assign bb_rx_i1=16'd0; - assign bb_rx_q1=16'd0; - `endif - - `ifdef RX_EN_2 - rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 - ( .clock(clk64),.reset(reset_data),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); - `else - assign bb_rx_i2=16'd0; - assign bb_rx_q2=16'd0; - `endif - - `ifdef RX_EN_3 - rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 - ( .clock(clk64),.reset(reset_data),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); - assign bb_rx_i3=16'd0; - assign bb_rx_q3=16'd0; - `endif - -`endif // `ifdef RX_ON - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities; - assign capabilities[7] = `TX_CAP_HB; - assign capabilities[6:4] = `TX_CAP_NCHAN; - assign capabilities[3] = `RX_CAP_HB; - assign capabilities[2:0] = `RX_CAP_NCHAN; - - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) ); - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - -`ifdef MULTI_ON - - master_control_multi master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .rx_slave_sync(io_rx_a[`bitnoFR_RX_SYNC_INPUT_IOPIN]), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .sync_rx(sync_rx), - .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), - .tx_empty(tx_empty), - //.debug_0(rx_a_a),.debug_1(ddc0_in_i), - .debug_0(rx_debugbus),.debug_1(ddc0_in_i), - .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - -`else //`ifdef MULTI_ON - - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), - .tx_empty(tx_empty), - //.debug_0(rx_a_a),.debug_1(ddc0_in_i), - .debug_0(rx_debugbus),.debug_1(ddc0_in_i), - .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - -`endif //`ifdef MULTI_ON - - io_pins io_pins - (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Misc Settings - setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); - -endmodule // usrp_multi diff --git a/toplevel/usrp_std/.gitignore b/toplevel/usrp_std/.gitignore deleted file mode 100644 index 31d6ea9ef..000000000 --- a/toplevel/usrp_std/.gitignore +++ /dev/null @@ -1,17 +0,0 @@ -/*.qws -/*.eqn -/*.done -/*.htm -/*.rpt -/*.ini -/*.fsf -/*.jam -/*.jbc -/*.pin -/*.pof -/*.sof -/*.rbf -/*.ttf -/*.summary -/prev* -/db diff --git a/toplevel/usrp_std/config.vh b/toplevel/usrp_std/config.vh deleted file mode 100644 index f1f8ec40e..000000000 --- a/toplevel/usrp_std/config.vh +++ /dev/null @@ -1,53 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006,2007 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// ==================================================================== -// User control over what parts get included -// -// >>>> EDIT ONLY THIS SECTION <<<< -// Uncomment only ONE configuration -// ==================================================================== - -// ==================================================================== -// FIXME drive configuration selection from the command line and/or gui -// ==================================================================== - -// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel -//`include "../include/common_config_1rxhb_1tx.vh" - -// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels - `include "../include/common_config_2rxhb_2tx.vh" - -// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels -//`include "../include/common_config_4rx_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels -//`include "../include/common_config_2rxhb_0tx.vh" - -// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels -//`include "../include/common_config_2rx_0tx.vh" - -// Add other "known to fit" configurations here... - -// ==================================================================== -// Now include the common footer -// ==================================================================== - `include "../include/common_config_bottom.vh" diff --git a/toplevel/usrp_std/usrp_std.csf b/toplevel/usrp_std/usrp_std.csf deleted file mode 100644 index 627197caf..000000000 --- a/toplevel/usrp_std/usrp_std.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |usrp_std; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(usrp_std) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/toplevel/usrp_std/usrp_std.esf b/toplevel/usrp_std/usrp_std.esf deleted file mode 100644 index b88c15994..000000000 --- a/toplevel/usrp_std/usrp_std.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = usrp_std; -} diff --git a/toplevel/usrp_std/usrp_std.psf b/toplevel/usrp_std/usrp_std.psf deleted file mode 100644 index 506c81b6a..000000000 --- a/toplevel/usrp_std/usrp_std.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(usrp_std) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "e:\usrp\fpga\megacells"; -} -THIRD_PARTY_EDA_TOOLS(usrp_std) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; - EDA_SIMULATION_TOOL = ""; - EDA_TIMING_ANALYSIS_TOOL = ""; - EDA_BOARD_DESIGN_TOOL = ""; - EDA_FORMAL_VERIFICATION_TOOL = ""; - EDA_RESYNTHESIS_TOOL = ""; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/toplevel/usrp_std/usrp_std.qpf b/toplevel/usrp_std/usrp_std.qpf deleted file mode 100644 index e8b27505c..000000000 --- a/toplevel/usrp_std/usrp_std.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.0" -DATE = "17:10:11 December 20, 2004" - - -# Active Revisions - -PROJECT_REVISION = "usrp_std" diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf deleted file mode 100644 index e0bac4893..000000000 --- a/toplevel/usrp_std/usrp_std.qsf +++ /dev/null @@ -1,409 +0,0 @@ -# Copyright (C) 1991-2005 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# The default values for assignments are stored in the file -# usrp_std_assignment_defaults.qdf -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1" - -# Pin & Location Assignments -# ========================== -set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -set_location_assignment PIN_29 -to SCLK -set_location_assignment PIN_117 -to SDI -set_location_assignment PIN_28 -to usbclk -set_location_assignment PIN_107 -to usbctl[0] -set_location_assignment PIN_106 -to usbctl[1] -set_location_assignment PIN_105 -to usbctl[2] -set_location_assignment PIN_100 -to usbdata[0] -set_location_assignment PIN_84 -to usbdata[10] -set_location_assignment PIN_83 -to usbdata[11] -set_location_assignment PIN_82 -to usbdata[12] -set_location_assignment PIN_79 -to usbdata[13] -set_location_assignment PIN_78 -to usbdata[14] -set_location_assignment PIN_77 -to usbdata[15] -set_location_assignment PIN_99 -to usbdata[1] -set_location_assignment PIN_98 -to usbdata[2] -set_location_assignment PIN_95 -to usbdata[3] -set_location_assignment PIN_94 -to usbdata[4] -set_location_assignment PIN_93 -to usbdata[5] -set_location_assignment PIN_88 -to usbdata[6] -set_location_assignment PIN_87 -to usbdata[7] -set_location_assignment PIN_86 -to usbdata[8] -set_location_assignment PIN_85 -to usbdata[9] -set_location_assignment PIN_104 -to usbrdy[0] -set_location_assignment PIN_101 -to usbrdy[1] -set_location_assignment PIN_76 -to FX2_1 -set_location_assignment PIN_75 -to FX2_2 -set_location_assignment PIN_74 -to FX2_3 -set_location_assignment PIN_116 -to io_rx_a[0] -set_location_assignment PIN_115 -to io_rx_a[1] -set_location_assignment PIN_114 -to io_rx_a[2] -set_location_assignment PIN_113 -to io_rx_a[3] -set_location_assignment PIN_108 -to io_rx_a[4] -set_location_assignment PIN_195 -to io_rx_a[5] -set_location_assignment PIN_196 -to io_rx_a[6] -set_location_assignment PIN_197 -to io_rx_a[7] -set_location_assignment PIN_200 -to io_rx_a[8] -set_location_assignment PIN_201 -to io_rx_a[9] -set_location_assignment PIN_202 -to io_rx_a[10] -set_location_assignment PIN_203 -to io_rx_a[11] -set_location_assignment PIN_206 -to io_rx_a[12] -set_location_assignment PIN_207 -to io_rx_a[13] -set_location_assignment PIN_208 -to io_rx_a[14] -set_location_assignment PIN_214 -to io_rx_b[0] -set_location_assignment PIN_215 -to io_rx_b[1] -set_location_assignment PIN_216 -to io_rx_b[2] -set_location_assignment PIN_217 -to io_rx_b[3] -set_location_assignment PIN_218 -to io_rx_b[4] -set_location_assignment PIN_219 -to io_rx_b[5] -set_location_assignment PIN_222 -to io_rx_b[6] -set_location_assignment PIN_223 -to io_rx_b[7] -set_location_assignment PIN_224 -to io_rx_b[8] -set_location_assignment PIN_225 -to io_rx_b[9] -set_location_assignment PIN_226 -to io_rx_b[10] -set_location_assignment PIN_227 -to io_rx_b[11] -set_location_assignment PIN_228 -to io_rx_b[12] -set_location_assignment PIN_233 -to io_rx_b[13] -set_location_assignment PIN_234 -to io_rx_b[14] -set_location_assignment PIN_175 -to io_tx_a[0] -set_location_assignment PIN_176 -to io_tx_a[1] -set_location_assignment PIN_177 -to io_tx_a[2] -set_location_assignment PIN_178 -to io_tx_a[3] -set_location_assignment PIN_179 -to io_tx_a[4] -set_location_assignment PIN_180 -to io_tx_a[5] -set_location_assignment PIN_181 -to io_tx_a[6] -set_location_assignment PIN_182 -to io_tx_a[7] -set_location_assignment PIN_183 -to io_tx_a[8] -set_location_assignment PIN_184 -to io_tx_a[9] -set_location_assignment PIN_185 -to io_tx_a[10] -set_location_assignment PIN_186 -to io_tx_a[11] -set_location_assignment PIN_187 -to io_tx_a[12] -set_location_assignment PIN_188 -to io_tx_a[13] -set_location_assignment PIN_193 -to io_tx_a[14] -set_location_assignment PIN_73 -to io_tx_b[0] -set_location_assignment PIN_68 -to io_tx_b[1] -set_location_assignment PIN_67 -to io_tx_b[2] -set_location_assignment PIN_66 -to io_tx_b[3] -set_location_assignment PIN_65 -to io_tx_b[4] -set_location_assignment PIN_64 -to io_tx_b[5] -set_location_assignment PIN_63 -to io_tx_b[6] -set_location_assignment PIN_62 -to io_tx_b[7] -set_location_assignment PIN_61 -to io_tx_b[8] -set_location_assignment PIN_60 -to io_tx_b[9] -set_location_assignment PIN_59 -to io_tx_b[10] -set_location_assignment PIN_58 -to io_tx_b[11] -set_location_assignment PIN_57 -to io_tx_b[12] -set_location_assignment PIN_56 -to io_tx_b[13] -set_location_assignment PIN_55 -to io_tx_b[14] -set_location_assignment PIN_152 -to master_clk -set_location_assignment PIN_144 -to rx_a_a[0] -set_location_assignment PIN_143 -to rx_a_a[1] -set_location_assignment PIN_141 -to rx_a_a[2] -set_location_assignment PIN_140 -to rx_a_a[3] -set_location_assignment PIN_139 -to rx_a_a[4] -set_location_assignment PIN_138 -to rx_a_a[5] -set_location_assignment PIN_137 -to rx_a_a[6] -set_location_assignment PIN_136 -to rx_a_a[7] -set_location_assignment PIN_135 -to rx_a_a[8] -set_location_assignment PIN_134 -to rx_a_a[9] -set_location_assignment PIN_133 -to rx_a_a[10] -set_location_assignment PIN_132 -to rx_a_a[11] -set_location_assignment PIN_23 -to rx_a_b[0] -set_location_assignment PIN_21 -to rx_a_b[1] -set_location_assignment PIN_20 -to rx_a_b[2] -set_location_assignment PIN_19 -to rx_a_b[3] -set_location_assignment PIN_18 -to rx_a_b[4] -set_location_assignment PIN_17 -to rx_a_b[5] -set_location_assignment PIN_16 -to rx_a_b[6] -set_location_assignment PIN_15 -to rx_a_b[7] -set_location_assignment PIN_14 -to rx_a_b[8] -set_location_assignment PIN_13 -to rx_a_b[9] -set_location_assignment PIN_12 -to rx_a_b[10] -set_location_assignment PIN_11 -to rx_a_b[11] -set_location_assignment PIN_131 -to rx_b_a[0] -set_location_assignment PIN_128 -to rx_b_a[1] -set_location_assignment PIN_127 -to rx_b_a[2] -set_location_assignment PIN_126 -to rx_b_a[3] -set_location_assignment PIN_125 -to rx_b_a[4] -set_location_assignment PIN_124 -to rx_b_a[5] -set_location_assignment PIN_123 -to rx_b_a[6] -set_location_assignment PIN_122 -to rx_b_a[7] -set_location_assignment PIN_121 -to rx_b_a[8] -set_location_assignment PIN_120 -to rx_b_a[9] -set_location_assignment PIN_119 -to rx_b_a[10] -set_location_assignment PIN_118 -to rx_b_a[11] -set_location_assignment PIN_8 -to rx_b_b[0] -set_location_assignment PIN_7 -to rx_b_b[1] -set_location_assignment PIN_6 -to rx_b_b[2] -set_location_assignment PIN_5 -to rx_b_b[3] -set_location_assignment PIN_4 -to rx_b_b[4] -set_location_assignment PIN_3 -to rx_b_b[5] -set_location_assignment PIN_2 -to rx_b_b[6] -set_location_assignment PIN_240 -to rx_b_b[7] -set_location_assignment PIN_239 -to rx_b_b[8] -set_location_assignment PIN_238 -to rx_b_b[9] -set_location_assignment PIN_237 -to rx_b_b[10] -set_location_assignment PIN_236 -to rx_b_b[11] -set_location_assignment PIN_156 -to SDO -set_location_assignment PIN_153 -to SEN_FPGA -set_location_assignment PIN_159 -to tx_a[0] -set_location_assignment PIN_160 -to tx_a[1] -set_location_assignment PIN_161 -to tx_a[2] -set_location_assignment PIN_162 -to tx_a[3] -set_location_assignment PIN_163 -to tx_a[4] -set_location_assignment PIN_164 -to tx_a[5] -set_location_assignment PIN_165 -to tx_a[6] -set_location_assignment PIN_166 -to tx_a[7] -set_location_assignment PIN_167 -to tx_a[8] -set_location_assignment PIN_168 -to tx_a[9] -set_location_assignment PIN_169 -to tx_a[10] -set_location_assignment PIN_170 -to tx_a[11] -set_location_assignment PIN_173 -to tx_a[12] -set_location_assignment PIN_174 -to tx_a[13] -set_location_assignment PIN_38 -to tx_b[0] -set_location_assignment PIN_39 -to tx_b[1] -set_location_assignment PIN_41 -to tx_b[2] -set_location_assignment PIN_42 -to tx_b[3] -set_location_assignment PIN_43 -to tx_b[4] -set_location_assignment PIN_44 -to tx_b[5] -set_location_assignment PIN_45 -to tx_b[6] -set_location_assignment PIN_46 -to tx_b[7] -set_location_assignment PIN_47 -to tx_b[8] -set_location_assignment PIN_48 -to tx_b[9] -set_location_assignment PIN_49 -to tx_b[10] -set_location_assignment PIN_50 -to tx_b[11] -set_location_assignment PIN_53 -to tx_b[12] -set_location_assignment PIN_54 -to tx_b[13] -set_location_assignment PIN_158 -to TXSYNC_A -set_location_assignment PIN_37 -to TXSYNC_B -set_location_assignment PIN_235 -to io_rx_b[15] -set_location_assignment PIN_24 -to io_tx_b[15] -set_location_assignment PIN_213 -to io_rx_a[15] -set_location_assignment PIN_194 -to io_tx_a[15] -set_location_assignment PIN_1 -to MYSTERY_SIGNAL - -# Timing Assignments -# ================== -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name TOP_LEVEL_ENTITY usrp_std -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP1C12Q240C8 -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name INC_PLC_MODE OFF -set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF -set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -# Timing Analysis Assignments -# =========================== -set_global_assignment -name MAX_SCC_SIZE 50 - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" -set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF - -# Simulator Assignments -# ===================== -set_global_assignment -name START_TIME "0 ns" -set_global_assignment -name GLITCH_INTERVAL "1 ns" - -# Design Assistant Assignments -# ============================ -set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF -set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF -set_global_assignment -name ASSG_CAT OFF -set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF -set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF -set_global_assignment -name CLK_CAT OFF -set_global_assignment -name CLK_RULE_COMB_CLOCK OFF -set_global_assignment -name CLK_RULE_INV_CLOCK OFF -set_global_assignment -name CLK_RULE_GATING_SCHEME OFF -set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF -set_global_assignment -name CLK_RULE_MIX_EDGES OFF -set_global_assignment -name RESET_CAT OFF -set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name TIMING_CAT OFF -set_global_assignment -name TIMING_RULE_SHIFT_REG OFF -set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF -set_global_assignment -name NONSYNCHSTRUCT_CAT OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF -set_global_assignment -name SIGNALRACE_CAT OFF -set_global_assignment -name ACLK_CAT OFF -set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF -set_global_assignment -name HCPY_CAT OFF -set_global_assignment -name HCPY_VREF_PINS OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name HUB_ENTITY_NAME SLD_HUB -set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP OFF - -# LogicLock Region Assignments -# ============================ -set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF - -# ----------------- -# start CLOCK(SCLK) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK -set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK - -# end CLOCK(SCLK) -# --------------- - -# ----------------------- -# start CLOCK(master_clk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk -set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk - -# end CLOCK(master_clk) -# --------------------- - -# ------------------- -# start CLOCK(usbclk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk -set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk - -# end CLOCK(usbclk) -# ----------------- - -# ---------------------- -# start ENTITY(usrp_std) - - # Timing Assignments - # ================== -set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK -set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk -set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk - -# end ENTITY(usrp_std) -# -------------------- - -set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v -set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v -set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v -set_global_assignment -name VERILOG_FILE usrp_std.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v deleted file mode 100644 index 8b29a9c21..000000000 --- a/toplevel/usrp_std/usrp_std.v +++ /dev/null @@ -1,333 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2004 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Top level module for a full setup with DUCs and DDCs - -// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins -// for debugging info. NB, This can kill the m'board and/or d'board if you -// have anything except basic d'boards installed. - -// Uncomment the following to include optional circuitry - -`include "config.vh" -`include "../../../firmware/include/fpga_regs_common.v" -`include "../../../firmware/include/fpga_regs_standard.v" - -module usrp_std -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64,clk128; - - wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_space, have_pkt_rdy; - assign usbrdy[0] = have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire tx_underrun, rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = tx_underrun; - - wire [15:0] usbdata_out; - - wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; - - wire tx_realsignals; - wire [3:0] rx_numchan; - wire [2:0] tx_numchan; - - wire [7:0] interp_rate, decim_rate; - wire [31:0] tx_debugbus, rx_debugbus; - - wire enable_tx, enable_rx; - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - wire [7:0] settings; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - assign clk64 = master_clk; - - wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; - wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; - - // TX - wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; - wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; - - wire strobe_interp, tx_sample_strobe; - wire tx_empty; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - reg [15:0] debug_counter; - reg [15:0] loopback_i_0,loopback_q_0; - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Transmit Side -`ifdef TX_ON - assign bb_tx_i0 = ch0tx; - assign bb_tx_q0 = ch1tx; - assign bb_tx_i1 = ch2tx; - assign bb_tx_q1 = ch3tx; - - tx_buffer tx_buffer - ( .usbclk(usbclk), .bus_reset(tx_bus_reset), - .usbdata(usbdata),.WR(WR), .have_space(have_space), - .tx_underrun(tx_underrun), .clear_status(clear_status), - .txclk(clk64), .reset(tx_dsp_reset), - .channels({tx_numchan,1'b0}), - .tx_i_0(ch0tx),.tx_q_0(ch1tx), - .tx_i_1(ch2tx),.tx_q_1(ch3tx), - .txstrobe(strobe_interp), - .tx_empty(tx_empty), - .debugbus(tx_debugbus) ); - - `ifdef TX_EN_0 - tx_chain tx_chain_0 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), - .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); - `else - assign i_out_0=16'd0; - assign q_out_0=16'd0; - `endif - - `ifdef TX_EN_1 - tx_chain tx_chain_1 - ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), - .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), - .interpolator_strobe(strobe_interp),.freq(), - .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); - `else - assign i_out_1=16'd0; - assign q_out_1=16'd0; - `endif - - setting_reg #(`FR_TX_MUX) - sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); - - wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; - wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; - - wire txsync = tx_sample_strobe; - assign TXSYNC_A = txsync; - assign TXSYNC_B = txsync; - - assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; - assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; -`endif // `ifdef TX_ON - - ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Receive Side -`ifdef RX_ON - wire rx_sample_strobe,strobe_decim,hb_strobe; - wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, - bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; - - wire loopback = settings[0]; - wire counter = settings[1]; - - always @(posedge clk64) - if(rx_dsp_reset) - debug_counter <= #1 16'd0; - else if(~enable_rx) - debug_counter <= #1 16'd0; - else if(hb_strobe) - debug_counter <=#1 debug_counter + 16'd2; - - always @(posedge clk64) - if(strobe_interp) - begin - loopback_i_0 <= #1 ch0tx; - loopback_q_0 <= #1 ch1tx; - end - - assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; - assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; - assign ch2rx = bb_rx_i1; - assign ch3rx = bb_rx_q1; - assign ch4rx = bb_rx_i2; - assign ch5rx = bb_rx_q2; - assign ch6rx = bb_rx_i3; - assign ch7rx = bb_rx_q3; - - wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; - wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; - - adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), - .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3), - .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), - .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), - .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), - .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); - - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .reset_regs(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(ch0rx),.ch_1(ch1rx), - .ch_2(ch2rx),.ch_3(ch3rx), - .ch_4(ch4rx),.ch_5(ch5rx), - .ch_6(ch6rx),.ch_7(ch7rx), - .rxclk(clk64),.rxstrobe(hb_strobe), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus(rx_debugbus) ); - - `ifdef RX_EN_0 - rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); - `else - assign bb_rx_i0=16'd0; - assign bb_rx_q0=16'd0; - `endif - - `ifdef RX_EN_1 - rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); - `else - assign bb_rx_i1=16'd0; - assign bb_rx_q1=16'd0; - `endif - - `ifdef RX_EN_2 - rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); - `else - assign bb_rx_i2=16'd0; - assign bb_rx_q2=16'd0; - `endif - - `ifdef RX_EN_3 - rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 - ( .clock(clk64),.reset(1'b0),.enable(enable_rx), - .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); - `else - assign bb_rx_i3=16'd0; - assign bb_rx_q3=16'd0; - `endif - -`endif // `ifdef RX_ON - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities; - assign capabilities[7] = `TX_CAP_HB; - assign capabilities[6:4] = `TX_CAP_NCHAN; - assign capabilities[3] = `RX_CAP_HB; - assign capabilities[2:0] = `RX_CAP_NCHAN; - - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), - .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) - ); - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), - .tx_empty(tx_empty), - //.debug_0(rx_a_a),.debug_1(ddc0_in_i), - .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]), - .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - - io_pins io_pins - (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Misc Settings - setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); - -endmodule // usrp_std diff --git a/usrp1/Makefile.am b/usrp1/Makefile.am new file mode 100644 index 000000000..8721af4a7 --- /dev/null +++ b/usrp1/Makefile.am @@ -0,0 +1,24 @@ +# +# Copyright 2004,2005,2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +SUBDIRS = rbf + +include Makefile.extra diff --git a/usrp1/Makefile.extra b/usrp1/Makefile.extra new file mode 100644 index 000000000..56df23c98 --- /dev/null +++ b/usrp1/Makefile.extra @@ -0,0 +1,181 @@ +EXTRA_DIST = \ + gen_makefile_extra.py \ + inband_lib/chan_fifo_reader.v \ + inband_lib/channel_demux.v \ + inband_lib/channel_ram.v \ + inband_lib/cmd_reader.v \ + inband_lib/packet_builder.v \ + inband_lib/register_io.v \ + inband_lib/rx_buffer_inband.v \ + inband_lib/tx_buffer_inband.v \ + inband_lib/tx_packer.v \ + inband_lib/usb_packet_fifo.v \ + megacells/accum32.bsf \ + megacells/accum32.cmp \ + megacells/accum32.inc \ + megacells/accum32.v \ + megacells/accum32_bb.v \ + megacells/accum32_inst.v \ + megacells/add32.bsf \ + megacells/add32.cmp \ + megacells/add32.inc \ + megacells/add32.v \ + megacells/add32_bb.v \ + megacells/add32_inst.v \ + megacells/addsub16.bsf \ + megacells/addsub16.cmp \ + megacells/addsub16.inc \ + megacells/addsub16.v \ + megacells/addsub16_bb.v \ + megacells/addsub16_inst.v \ + megacells/bustri.bsf \ + megacells/bustri.cmp \ + megacells/bustri.inc \ + megacells/bustri.v \ + megacells/bustri_bb.v \ + megacells/bustri_inst.v \ + megacells/clk_doubler.v \ + megacells/clk_doubler_bb.v \ + megacells/dspclkpll.v \ + megacells/dspclkpll_bb.v \ + megacells/fifo_1kx16.bsf \ + megacells/fifo_1kx16.cmp \ + megacells/fifo_1kx16.inc \ + megacells/fifo_1kx16.v \ + megacells/fifo_1kx16_bb.v \ + megacells/fifo_1kx16_inst.v \ + megacells/fifo_2k.v \ + megacells/fifo_2k_bb.v \ + megacells/fifo_4k.v \ + megacells/fifo_4k_18.v \ + megacells/fifo_4k_bb.v \ + megacells/fifo_4kx16_dc.bsf \ + megacells/fifo_4kx16_dc.cmp \ + megacells/fifo_4kx16_dc.inc \ + megacells/fifo_4kx16_dc.v \ + megacells/fifo_4kx16_dc_bb.v \ + megacells/fifo_4kx16_dc_inst.v \ + megacells/mylpm_addsub.bsf \ + megacells/mylpm_addsub.cmp \ + megacells/mylpm_addsub.inc \ + megacells/mylpm_addsub.v \ + megacells/mylpm_addsub_bb.v \ + megacells/mylpm_addsub_inst.v \ + megacells/pll.v \ + megacells/pll_bb.v \ + megacells/pll_inst.v \ + megacells/sub32.bsf \ + megacells/sub32.cmp \ + megacells/sub32.inc \ + megacells/sub32.v \ + megacells/sub32_bb.v \ + megacells/sub32_inst.v \ + models/bustri.v \ + models/fifo.v \ + models/fifo_1c_1k.v \ + models/fifo_1c_2k.v \ + models/fifo_1c_4k.v \ + models/fifo_1k.v \ + models/fifo_2k.v \ + models/fifo_4k.v \ + models/fifo_4k_18.v \ + models/pll.v \ + models/ssram.v \ + sdr_lib/adc_interface.v \ + sdr_lib/atr_delay.v \ + sdr_lib/bidir_reg.v \ + sdr_lib/cic_dec_shifter.v \ + sdr_lib/cic_decim.v \ + sdr_lib/cic_int_shifter.v \ + sdr_lib/cic_interp.v \ + sdr_lib/clk_divider.v \ + sdr_lib/cordic.v \ + sdr_lib/cordic_stage.v \ + sdr_lib/ddc.v \ + sdr_lib/dpram.v \ + sdr_lib/duc.v \ + sdr_lib/ext_fifo.v \ + sdr_lib/gen_cordic_consts.py \ + sdr_lib/gen_sync.v \ + sdr_lib/hb/acc.v \ + sdr_lib/hb/coeff_rom.v \ + sdr_lib/hb/halfband_decim.v \ + sdr_lib/hb/halfband_interp.v \ + sdr_lib/hb/hbd_tb/test_hbd.v \ + sdr_lib/hb/mac.v \ + sdr_lib/hb/mult.v \ + sdr_lib/hb/ram16_2port.v \ + sdr_lib/hb/ram16_2sum.v \ + sdr_lib/hb/ram32_2sum.v \ + sdr_lib/io_pins.v \ + sdr_lib/master_control.v \ + sdr_lib/master_control_multi.v \ + sdr_lib/phase_acc.v \ + sdr_lib/ram.v \ + sdr_lib/ram16.v \ + sdr_lib/ram32.v \ + sdr_lib/ram64.v \ + sdr_lib/rssi.v \ + sdr_lib/rx_buffer.v \ + sdr_lib/rx_chain.v \ + sdr_lib/rx_chain_dual.v \ + sdr_lib/rx_dcoffset.v \ + sdr_lib/serial_io.v \ + sdr_lib/setting_reg.v \ + sdr_lib/setting_reg_masked.v \ + sdr_lib/sign_extend.v \ + sdr_lib/strobe_gen.v \ + sdr_lib/tx_buffer.v \ + sdr_lib/tx_chain.v \ + sdr_lib/tx_chain_hb.v \ + tb/cbus_tb.v \ + tb/cordic_tb.v \ + tb/decim_tb.v \ + tb/fullchip_tb.v \ + tb/interp_tb.v \ + tb/justinterp_tb.v \ + tb/usrp_tasks.v \ + toplevel/include/common_config_1rxhb_1tx.vh \ + toplevel/include/common_config_2rx_0tx.vh \ + toplevel/include/common_config_2rxhb_0tx.vh \ + toplevel/include/common_config_2rxhb_2tx.vh \ + toplevel/include/common_config_4rx_0tx.vh \ + toplevel/include/common_config_bottom.vh \ + toplevel/mrfm/biquad_2stage.v \ + toplevel/mrfm/biquad_6stage.v \ + toplevel/mrfm/mrfm.csf \ + toplevel/mrfm/mrfm.esf \ + toplevel/mrfm/mrfm.psf \ + toplevel/mrfm/mrfm.py \ + toplevel/mrfm/mrfm.qpf \ + toplevel/mrfm/mrfm.qsf \ + toplevel/mrfm/mrfm.v \ + toplevel/mrfm/mrfm.vh \ + toplevel/mrfm/mrfm_compensator.v \ + toplevel/mrfm/mrfm_fft.py \ + toplevel/mrfm/mrfm_proc.v \ + toplevel/mrfm/shifter.v \ + toplevel/sizetest/sizetest.csf \ + toplevel/sizetest/sizetest.psf \ + toplevel/sizetest/sizetest.v \ + toplevel/usrp_inband_usb/config.vh \ + toplevel/usrp_inband_usb/usrp_inband_usb.csf \ + toplevel/usrp_inband_usb/usrp_inband_usb.esf \ + toplevel/usrp_inband_usb/usrp_inband_usb.psf \ + toplevel/usrp_inband_usb/usrp_inband_usb.qpf \ + toplevel/usrp_inband_usb/usrp_inband_usb.qsf \ + toplevel/usrp_inband_usb/usrp_inband_usb.v \ + toplevel/usrp_multi/config.vh \ + toplevel/usrp_multi/usrp_multi.csf \ + toplevel/usrp_multi/usrp_multi.esf \ + toplevel/usrp_multi/usrp_multi.psf \ + toplevel/usrp_multi/usrp_multi.qpf \ + toplevel/usrp_multi/usrp_multi.qsf \ + toplevel/usrp_multi/usrp_multi.v \ + toplevel/usrp_std/config.vh \ + toplevel/usrp_std/usrp_std.csf \ + toplevel/usrp_std/usrp_std.esf \ + toplevel/usrp_std/usrp_std.psf \ + toplevel/usrp_std/usrp_std.qpf \ + toplevel/usrp_std/usrp_std.qsf \ + toplevel/usrp_std/usrp_std.v diff --git a/usrp1/TODO b/usrp1/TODO new file mode 100644 index 000000000..76287c3d4 --- /dev/null +++ b/usrp1/TODO @@ -0,0 +1,23 @@ + + +Area Reduction +============== +Reduce one or both stages of dec/interp to max rate of 8 instead of 16 +Optimize CICs to minimize registers +Reduce width of RX CORDIC +Fix CORDIC wasted logic cells from bad synthesis +Progressively narrow x,y,z on CORDIC +16-bit wide FIFOs, split IQ/channels on other side (?) + +Enhancements +============ +Halfband filter in Spartan 3 +Muxing of inputs +Switch over to newfc +RAM interface? + +Other +===== +Capture/Transmit straight samples (no DUC/DDC) + + diff --git a/usrp1/gen_makefile_extra.py b/usrp1/gen_makefile_extra.py new file mode 100755 index 000000000..9f48802a2 --- /dev/null +++ b/usrp1/gen_makefile_extra.py @@ -0,0 +1,67 @@ +#!/usr/bin/env python +# +# Copyright 2006 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +""" +Generate Makefile.extra +""" + +import sys +import os.path + +extensions_we_like = ( + '.v', '.vh', + '.csf', '.esf', '.psf', '.qpf', '.qsf', + '.inc', '.cmp', '.bsf', + '.py') + +def visit(keepers, dirname, names): + if 'rbf' in names: + names.remove('rbf') + if 'CVS' in names: + names.remove('CVS') + + if dirname == '.': + dirname = '' + if dirname.startswith('./'): + dirname = dirname[2:] + + for n in names: + base, ext = os.path.splitext(n) + if ext in extensions_we_like: + keepers.append(os.path.join(dirname, n)) + +def generate(f): + keepers = [] + os.path.walk('.', visit, keepers) + keepers.sort() + write_keepers(keepers, f) + +def write_keepers(files, outf): + m = reduce(max, map(len, files), 0) + e = 'EXTRA_DIST =' + outf.write('%s%s \\\n' % (e, (m-len(e)+8) * ' ')) + for f in files[:-1]: + outf.write('\t%s%s \\\n' % (f, (m-len(f)) * ' ')) + outf.write('\t%s\n' % (files[-1],)) + +if __name__ == '__main__': + generate(open('Makefile.extra','w')) diff --git a/usrp1/inband_lib/chan_fifo_reader.v b/usrp1/inband_lib/chan_fifo_reader.v new file mode 100755 index 000000000..69da9ec5a --- /dev/null +++ b/usrp1/inband_lib/chan_fifo_reader.v @@ -0,0 +1,219 @@ +module chan_fifo_reader + (reset, tx_clock, tx_strobe, timestamp_clock, samples_format, + fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i, + underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ; + + input wire reset ; + input wire tx_clock ; + input wire tx_strobe ; //signal to output tx_i and tx_q + input wire [31:0] timestamp_clock ; //current time + input wire [3:0] samples_format ;// not useful at this point + input wire [31:0] fifodata ; //the data input + input wire pkt_waiting ; //signal the next packet is ready + output reg rdreq ; //actually an ack to the current fifodata + output reg skip ; //finish reading current packet + output reg [15:0] tx_q ; //top 16 bit output of fifodata + output reg [15:0] tx_i ; //bottom 16 bit output of fifodata + output reg underrun ; + output reg tx_empty ; //cause 0 to be the output + input wire [31:0] rssi; + input wire [31:0] threshhold; + input wire [31:0] rssi_wait; + + output wire [14:0] debug; + assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock}; + + //Samples format + // 16 bits interleaved complex samples + `define QI16 4'b0 + + // States + parameter IDLE = 3'd0; + parameter HEADER = 3'd1; + parameter TIMESTAMP = 3'd2; + parameter WAIT = 3'd3; + parameter WAITSTROBE = 3'd4; + parameter SEND = 3'd5; + + // Header format + `define PAYLOAD 8:2 + `define ENDOFBURST 27 + `define STARTOFBURST 28 + `define RSSI_FLAG 26 + + + /* State registers */ + reg [2:0] reader_state; + /* Local registers */ + reg [6:0] payload_len; + reg [6:0] read_len; + reg [31:0] timestamp; + reg burst; + reg trash; + reg rssi_flag; + reg [31:0] time_wait; + + always @(posedge tx_clock) + begin + if (reset) + begin + reader_state <= IDLE; + rdreq <= 0; + skip <= 0; + underrun <= 0; + burst <= 0; + tx_empty <= 1; + tx_q <= 0; + tx_i <= 0; + trash <= 0; + rssi_flag <= 0; + time_wait <= 0; + end + else + begin + case (reader_state) + IDLE: + begin + /* + * reset all the variables and wait for a tx_strobe + * it is assumed that the ram connected to this fifo_reader + * is a short hand fifo meaning that the header to the next packet + * is already available to this fifo_reader when pkt_waiting is on + */ + skip <=0; + time_wait <= 0; + if (pkt_waiting == 1) + begin + reader_state <= HEADER; + rdreq <= 1; + underrun <= 0; + end + if (burst == 1 && pkt_waiting == 0) + underrun <= 1; + if (tx_strobe == 1) + tx_empty <= 1 ; + end + + /* Process header */ + HEADER: + begin + if (tx_strobe == 1) + tx_empty <= 1 ; + + rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST]; + //Check Start/End burst flag + if (fifodata[`STARTOFBURST] == 1 + && fifodata[`ENDOFBURST] == 1) + burst <= 0; + else if (fifodata[`STARTOFBURST] == 1) + burst <= 1; + else if (fifodata[`ENDOFBURST] == 1) + burst <= 0; + + if (trash == 1 && fifodata[`STARTOFBURST] == 0) + begin + skip <= 1; + reader_state <= IDLE; + rdreq <= 0; + end + else + begin + payload_len <= fifodata[`PAYLOAD] ; + read_len <= 0; + rdreq <= 1; + reader_state <= TIMESTAMP; + end + end + + TIMESTAMP: + begin + timestamp <= fifodata; + reader_state <= WAIT; + if (tx_strobe == 1) + tx_empty <= 1 ; + rdreq <= 0; + end + + // Decide if we wait, send or discard samples + WAIT: + begin + if (tx_strobe == 1) + tx_empty <= 1 ; + + time_wait <= time_wait + 32'd1; + // Outdated + if ((timestamp < timestamp_clock) || + (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag)) + begin + trash <= 1; + reader_state <= IDLE; + skip <= 1; + end + // Let's send it + else if (timestamp == timestamp_clock + || timestamp == 32'hFFFFFFFF) + begin + if (rssi <= threshhold || rssi_flag == 0) + begin + trash <= 0; + reader_state <= WAITSTROBE; + end + else + reader_state <= WAIT; + end + else + reader_state <= WAIT; + end + + // Wait for the transmit chain to be ready + WAITSTROBE: + begin + // If end of payload... + if (read_len == payload_len) + begin + reader_state <= IDLE; + skip <= 1; + if (tx_strobe == 1) + tx_empty <= 1 ; + end + else if (tx_strobe == 1) + begin + reader_state <= SEND; + rdreq <= 1; + end + end + + // Send the samples to the tx_chain + SEND: + begin + reader_state <= WAITSTROBE; + read_len <= read_len + 7'd1; + tx_empty <= 0; + rdreq <= 0; + + case(samples_format) + `QI16: + begin + tx_i <= fifodata[15:0]; + tx_q <= fifodata[31:16]; + end + + // Assume 16 bits complex samples by default + default: + begin + tx_i <= fifodata[15:0]; + tx_q <= fifodata[31:16]; + end + endcase + end + + default: + begin + //error handling + reader_state <= IDLE; + end + endcase + end + end + +endmodule diff --git a/usrp1/inband_lib/channel_demux.v b/usrp1/inband_lib/channel_demux.v new file mode 100644 index 000000000..cca5cdb65 --- /dev/null +++ b/usrp1/inband_lib/channel_demux.v @@ -0,0 +1,78 @@ +module channel_demux + #(parameter NUM_CHAN = 2) ( //usb Side + input [31:0]usbdata_final, + input WR_final, + // TX Side + input reset, + input txclk, + output reg [NUM_CHAN:0] WR_channel, + output reg [31:0] ram_data, + output reg [NUM_CHAN:0] WR_done_channel ); + /* Parse header and forward to ram */ + + reg [2:0]reader_state; + reg [4:0]channel ; + reg [6:0]read_length ; + + // States + parameter IDLE = 3'd0; + parameter HEADER = 3'd1; + parameter WAIT = 3'd2; + parameter FORWARD = 3'd3; + + `define CHANNEL 20:16 + `define PKT_SIZE 127 + wire [4:0] true_channel; + assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ? + NUM_CHAN : (usbdata_final[`CHANNEL]); + + always @(posedge txclk) + begin + if (reset) + begin + reader_state <= IDLE; + WR_channel <= 0; + WR_done_channel <= 0; + end + else + case (reader_state) + IDLE: begin + if (WR_final) + reader_state <= HEADER; + end + + // Store channel and forware header + HEADER: begin + channel <= true_channel; + WR_channel[true_channel] <= 1; + ram_data <= usbdata_final; + read_length <= 7'd0 ; + + reader_state <= WAIT; + end + + WAIT: begin + WR_channel[channel] <= 0; + + if (read_length == `PKT_SIZE) + reader_state <= IDLE; + else if (WR_final) + reader_state <= FORWARD; + end + + FORWARD: begin + WR_channel[channel] <= 1; + ram_data <= usbdata_final; + read_length <= read_length + 7'd1; + + reader_state <= WAIT; + end + + default: + begin + //error handling + reader_state <= IDLE; + end + endcase + end +endmodule diff --git a/usrp1/inband_lib/channel_ram.v b/usrp1/inband_lib/channel_ram.v new file mode 100755 index 000000000..9621246c5 --- /dev/null +++ b/usrp1/inband_lib/channel_ram.v @@ -0,0 +1,107 @@ +module channel_ram + ( // System + input txclk, input reset, + // USB side + input [31:0] datain, input WR, input WR_done, output have_space, + // Reader side + output [31:0] dataout, input RD, input RD_done, output packet_waiting); + + reg [6:0] wr_addr, rd_addr; + reg [1:0] which_ram_wr, which_ram_rd; + reg [2:0] nb_packets; + + reg [31:0] ram0 [0:127]; + reg [31:0] ram1 [0:127]; + reg [31:0] ram2 [0:127]; + reg [31:0] ram3 [0:127]; + + reg [31:0] dataout0; + reg [31:0] dataout1; + reg [31:0] dataout2; + reg [31:0] dataout3; + + wire wr_done_int; + wire rd_done_int; + wire [6:0] rd_addr_final; + wire [1:0] which_ram_rd_final; + + // USB side + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain; + + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain; + + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain; + + always @(posedge txclk) + if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain; + + assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done); + + always @(posedge txclk) + if(reset) + wr_addr <= 0; + else if (WR_done) + wr_addr <= 0; + else if (WR) + wr_addr <= wr_addr + 7'd1; + + always @(posedge txclk) + if(reset) + which_ram_wr <= 0; + else if (wr_done_int) + which_ram_wr <= which_ram_wr + 2'd1; + + assign have_space = (nb_packets < 3'd3); + + // Reader side + // short hand fifo + // rd_addr_final is what rd_addr is going to be next clock cycle + // which_ram_rd_final is what which_ram_rd is going to be next clock cycle + always @(posedge txclk) dataout0 <= ram0[rd_addr_final]; + always @(posedge txclk) dataout1 <= ram1[rd_addr_final]; + always @(posedge txclk) dataout2 <= ram2[rd_addr_final]; + always @(posedge txclk) dataout3 <= ram3[rd_addr_final]; + + assign dataout = (which_ram_rd_final[1]) ? + (which_ram_rd_final[0] ? dataout3 : dataout2) : + (which_ram_rd_final[0] ? dataout1 : dataout0); + + //RD_done is the only way to signal the end of one packet + assign rd_done_int = RD_done; + + always @(posedge txclk) + if (reset) + rd_addr <= 0; + else if (RD_done) + rd_addr <= 0; + else if (RD) + rd_addr <= rd_addr + 7'd1; + + assign rd_addr_final = (reset|RD_done) ? (6'd0) : + ((RD)?(rd_addr+7'd1):rd_addr); + + always @(posedge txclk) + if (reset) + which_ram_rd <= 0; + else if (rd_done_int) + which_ram_rd <= which_ram_rd + 2'd1; + + assign which_ram_rd_final = (reset) ? (2'd0): + ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd); + + //packet_waiting is set to zero if rd_done_int is high + //because there is no guarantee that nb_packets will be pos. + + assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)); + always @(posedge txclk) + if (reset) + nb_packets <= 0; + else if (wr_done_int & ~rd_done_int) + nb_packets <= nb_packets + 3'd1; + else if (rd_done_int & ~wr_done_int) + nb_packets <= nb_packets - 3'd1; + +endmodule diff --git a/usrp1/inband_lib/cmd_reader.v b/usrp1/inband_lib/cmd_reader.v new file mode 100755 index 000000000..b69ea02b7 --- /dev/null +++ b/usrp1/inband_lib/cmd_reader.v @@ -0,0 +1,305 @@ +module cmd_reader + (//System + input reset, input txclk, input [31:0] timestamp_clock, + //FX2 Side + output reg skip, output reg rdreq, + input [31:0] fifodata, input pkt_waiting, + //Rx side + input rx_WR_enabled, output reg [15:0] rx_databus, + output reg rx_WR, output reg rx_WR_done, + //register io + input wire [31:0] reg_data_out, output reg [31:0] reg_data_in, + output reg [6:0] reg_addr, output reg [1:0] reg_io_enable, + output wire [14:0] debug, output reg stop, output reg [15:0] stop_time); + + // States + parameter IDLE = 4'd0; + parameter HEADER = 4'd1; + parameter TIMESTAMP = 4'd2; + parameter WAIT = 4'd3; + parameter TEST = 4'd4; + parameter SEND = 4'd5; + parameter PING = 4'd6; + parameter WRITE_REG = 4'd7; + parameter WRITE_REG_MASKED = 4'd8; + parameter READ_REG = 4'd9; + parameter DELAY = 4'd14; + + `define OP_PING_FIXED 8'd0 + `define OP_PING_FIXED_REPLY 8'd1 + `define OP_WRITE_REG 8'd2 + `define OP_WRITE_REG_MASKED 8'd3 + `define OP_READ_REG 8'd4 + `define OP_READ_REG_REPLY 8'd5 + `define OP_DELAY 8'd12 + + reg [6:0] payload; + reg [6:0] payload_read; + reg [3:0] state; + reg [15:0] high; + reg [15:0] low; + reg pending; + reg [31:0] value0; + reg [31:0] value1; + reg [31:0] value2; + reg [1:0] lines_in; + reg [1:0] lines_out; + reg [1:0] lines_out_total; + + `define JITTER 5 + `define OP_CODE 31:24 + `define PAYLOAD 8:2 + + wire [7:0] ops; + assign ops = value0[`OP_CODE]; + assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]}; + + always @(posedge txclk) + if (reset) + begin + pending <= 0; + state <= IDLE; + skip <= 0; + rdreq <= 0; + rx_WR <= 0; + reg_io_enable <= 0; + reg_data_in <= 0; + reg_addr <= 0; + stop <= 0; + end + else case (state) + IDLE : + begin + payload_read <= 0; + skip <= 0; + lines_in <= 0; + if(pkt_waiting) + begin + state <= HEADER; + rdreq <= 1; + end + end + + HEADER : + begin + payload <= fifodata[`PAYLOAD]; + state <= TIMESTAMP; + end + + TIMESTAMP : + begin + value0 <= fifodata; + state <= WAIT; + rdreq <= 0; + end + + WAIT : + begin + // Let's send it + if ((value0 <= timestamp_clock + `JITTER + && value0 > timestamp_clock) + || value0 == 32'hFFFFFFFF) + state <= TEST; + // Wait a little bit more + else if (value0 > timestamp_clock + `JITTER) + state <= WAIT; + // Outdated + else if (value0 < timestamp_clock) + begin + state <= IDLE; + skip <= 1; + end + end + + TEST : + begin + reg_io_enable <= 0; + rx_WR <= 0; + rx_WR_done <= 1; + stop <= 0; + if (payload_read == payload) + begin + skip <= 1; + state <= IDLE; + rdreq <= 0; + end + else + begin + value0 <= fifodata; + lines_in <= 2'd1; + rdreq <= 1; + payload_read <= payload_read + 7'd1; + lines_out <= 0; + case (fifodata[`OP_CODE]) + `OP_PING_FIXED: + begin + state <= PING; + end + `OP_WRITE_REG: + begin + state <= WRITE_REG; + pending <= 1; + end + `OP_WRITE_REG_MASKED: + begin + state <= WRITE_REG_MASKED; + pending <= 1; + end + `OP_READ_REG: + begin + state <= READ_REG; + end + `OP_DELAY: + begin + state <= DELAY; + end + default: + begin + //error, skip this packet + skip <= 1; + state <= IDLE; + end + endcase + end + end + + SEND: + begin + rdreq <= 0; + rx_WR_done <= 0; + if (pending) + begin + rx_WR <= 1; + rx_databus <= high; + pending <= 0; + if (lines_out == lines_out_total) + state <= TEST; + else case (ops) + `OP_READ_REG: + begin + state <= READ_REG; + end + default: + begin + state <= TEST; + end + endcase + end + else + begin + if (rx_WR_enabled) + begin + rx_WR <= 1; + rx_databus <= low; + pending <= 1; + lines_out <= lines_out + 2'd1; + end + else + rx_WR <= 0; + end + end + + PING: + begin + rx_WR <= 0; + rdreq <= 0; + rx_WR_done <= 0; + lines_out_total <= 2'd1; + pending <= 0; + state <= SEND; + high <= {`OP_PING_FIXED_REPLY, 8'd2}; + low <= value0[15:0]; + end + + READ_REG: + begin + rx_WR <= 0; + rx_WR_done <= 0; + rdreq <= 0; + lines_out_total <= 2'd2; + pending <= 0; + state <= SEND; + if (lines_out == 0) + begin + high <= {`OP_READ_REG_REPLY, 8'd6}; + low <= value0[15:0]; + reg_io_enable <= 2'd3; + reg_addr <= value0[6:0]; + end + else + begin + high <= reg_data_out[31:16]; + low <= reg_data_out[15:0]; + end + end + + WRITE_REG: + begin + rx_WR <= 0; + if (pending) + pending <= 0; + else + begin + if (lines_in == 2'd1) + begin + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value1 <= fifodata; + rdreq <= 0; + end + else + begin + reg_io_enable <= 2'd2; + reg_data_in <= value1; + reg_addr <= value0[6:0]; + state <= TEST; + end + end + end + + WRITE_REG_MASKED: + begin + rx_WR <= 0; + if (pending) + pending <= 0; + else + begin + if (lines_in == 2'd1) + begin + rdreq <= 1; + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value1 <= fifodata; + end + else if (lines_in == 2'd2) + begin + rdreq <= 0; + payload_read <= payload_read + 7'd1; + lines_in <= lines_in + 2'd1; + value2 <= fifodata; + end + else + begin + reg_io_enable <= 2'd2; + reg_data_in <= (value1 & value2); + reg_addr <= value0[6:0]; + state <= TEST; + end + end + end + + DELAY : + begin + rdreq <= 0; + stop <= 1; + stop_time <= value0[15:0]; + state <= TEST; + end + + default : + begin + //error state handling + state <= IDLE; + end + endcase +endmodule diff --git a/usrp1/inband_lib/packet_builder.v b/usrp1/inband_lib/packet_builder.v new file mode 100755 index 000000000..2c9122394 --- /dev/null +++ b/usrp1/inband_lib/packet_builder.v @@ -0,0 +1,152 @@ +module packet_builder #(parameter NUM_CHAN = 2)( + // System + input rxclk, + input reset, + input [31:0] timestamp_clock, + input [3:0] channels, + // ADC side + input [15:0]chan_fifodata, + input [NUM_CHAN:0]chan_empty, + input [9:0]chan_usedw, + output reg [3:0]rd_select, + output reg chan_rdreq, + // FX2 side + output reg WR, + output reg [15:0]fifodata, + input have_space, + input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2, + input wire [31:0]rssi_3, output wire [7:0] debugbus, + input [NUM_CHAN:0] underrun); + + + // States + `define IDLE 3'd0 + `define HEADER1 3'd1 + `define HEADER2 3'd2 + `define TIMESTAMP 3'd3 + `define FORWARD 3'd4 + + `define MAXPAYLOAD 504 + + `define PAYLOAD_LEN 8:0 + `define TAG 12:9 + `define MBZ 15:13 + + `define CHAN 4:0 + `define RSSI 10:5 + `define BURST 12:11 + `define DROPPED 13 + `define UNDERRUN 14 + `define OVERRUN 15 + + reg [NUM_CHAN:0] overrun; + reg [2:0] state; + reg [8:0] read_length; + reg [8:0] payload_len; + reg timestamp_complete; + reg [3:0] check_next; + + wire [31:0] true_rssi; + wire [4:0] true_channel; + wire ready_to_send; + + assign debugbus = {chan_empty[0], rd_select[0], have_space, + (chan_usedw >= 10'd504), (chan_usedw ==0), + ready_to_send, state[1:0]}; + + assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) : + ((rd_select[0]) ? rssi_1:rssi_0); + assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); + assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) || + ((rd_select == NUM_CHAN)&&(chan_usedw > 0)); + + always @(posedge rxclk) + begin + if (reset) + begin + overrun <= 0; + WR <= 0; + rd_select <= 0; + chan_rdreq <= 0; + timestamp_complete <= 0; + check_next <= 0; + state <= `IDLE; + end + else case (state) + `IDLE: begin + chan_rdreq <= #1 0; + //check if the channel is full + if(~chan_empty[check_next]) + begin + if (have_space) + begin + //transmit if the usb buffer have space + //check if we should send + if (ready_to_send) + state <= #1 `HEADER1; + + overrun[check_next] <= 0; + end + else + begin + state <= #1 `IDLE; + overrun[check_next] <= 1; + end + rd_select <= #1 check_next; + end + check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1); + end + + `HEADER1: begin + fifodata[`PAYLOAD_LEN] <= #1 9'd504; + payload_len <= #1 9'd504; + fifodata[`TAG] <= #1 0; + fifodata[`MBZ] <= #1 0; + WR <= #1 1; + + state <= #1 `HEADER2; + read_length <= #1 0; + end + + `HEADER2: begin + fifodata[`CHAN] <= #1 true_channel; + fifodata[`RSSI] <= #1 true_rssi[5:0]; + fifodata[`BURST] <= #1 0; + fifodata[`DROPPED] <= #1 0; + fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel]; + fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel]; + state <= #1 `TIMESTAMP; + end + + `TIMESTAMP: begin + fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]); + timestamp_complete <= #1 ~timestamp_complete; + + if (~timestamp_complete) + chan_rdreq <= #1 1; + + state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP); + end + + `FORWARD: begin + read_length <= #1 read_length + 9'd2; + fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata); + + if (read_length >= `MAXPAYLOAD) + begin + WR <= #1 0; + state <= #1 `IDLE; + chan_rdreq <= #1 0; + end + else if (read_length == payload_len - 4) + chan_rdreq <= #1 0; + end + + default: begin + //handling error state + state <= `IDLE; + end + endcase + end +endmodule + diff --git a/usrp1/inband_lib/register_io.v b/usrp1/inband_lib/register_io.v new file mode 100755 index 000000000..2b0cd1732 --- /dev/null +++ b/usrp1/inband_lib/register_io.v @@ -0,0 +1,82 @@ +module register_io + (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr, + rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3, + debug_en, misc, txmux); + + input clk; + input reset; + input wire [1:0] enable; + input wire [6:0] addr; + input wire [31:0] datain; + output reg [31:0] dataout; + output wire [15:0] debugbus; + output reg [6:0] addr_wr; + output reg [31:0] data_wr; + output wire strobe_wr; + input wire [31:0] rssi_0; + input wire [31:0] rssi_1; + input wire [31:0] rssi_2; + input wire [31:0] rssi_3; + output wire [31:0] threshhold; + output wire [31:0] rssi_wait; + input wire [15:0] reg_0; + input wire [15:0] reg_1; + input wire [15:0] reg_2; + input wire [15:0] reg_3; + input wire [3:0] debug_en; + input wire [7:0] misc; + input wire [31:0] txmux; + + reg strobe; + wire [31:0] out[2:1]; + assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]}; + assign threshhold = out[1]; + assign rssi_wait = out[2]; + assign strobe_wr = strobe; + + always @(*) + if (reset | ~enable[1]) + begin + strobe <= 0; + dataout <= 0; + end + else + begin + if (enable[0]) + begin + //read + if (addr <= 7'd52 && addr > 7'd50) + dataout <= out[addr-7'd50]; + else + dataout <= 32'hFFFFFFFF; + strobe <= 0; + end + else + begin + //write + dataout <= dataout; + strobe <= 1; + data_wr <= datain; + addr_wr <= addr; + end + end + +//register declarations + /*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/ + setting_reg #(51) setting_reg1(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1])); + setting_reg #(52) setting_reg2(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2])); + /*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3])); + setting_reg #(54) setting_reg4(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4])); + setting_reg #(55) setting_reg5(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5])); + setting_reg #(56) setting_reg6(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6])); + setting_reg #(57) setting_reg7(.clock(clk),.reset(reset), + .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/ + +endmodule diff --git a/usrp1/inband_lib/rx_buffer_inband.v b/usrp1/inband_lib/rx_buffer_inband.v new file mode 100755 index 000000000..cbd2d8958 --- /dev/null +++ b/usrp1/inband_lib/rx_buffer_inband.v @@ -0,0 +1,209 @@ +//`include "../../firmware/include/fpga_regs_common.v" +//`include "../../firmware/include/fpga_regs_standard.v" +module rx_buffer_inband + ( input usbclk, + input bus_reset, + input reset, // DSP side reset (used here), do not reset registers + input reset_regs, //Only reset registers + output [15:0] usbdata, + input RD, + output wire have_pkt_rdy, + output reg rx_overrun, + input wire [3:0] channels, + input wire [15:0] ch_0, + input wire [15:0] ch_1, + input wire [15:0] ch_2, + input wire [15:0] ch_3, + input wire [15:0] ch_4, + input wire [15:0] ch_5, + input wire [15:0] ch_6, + input wire [15:0] ch_7, + input rxclk, + input rxstrobe, + input clear_status, + input [6:0] serial_addr, + input [31:0] serial_data, + input serial_strobe, + output wire [15:0] debugbus, + + //Connection with tx_inband + input rx_WR, + input [15:0] rx_databus, + input rx_WR_done, + output reg rx_WR_enabled, + //signal strength + input wire [31:0] rssi_0, input wire [31:0] rssi_1, + input wire [31:0] rssi_2, input wire [31:0] rssi_3, + input wire [1:0] tx_underrun + ); + + parameter NUM_CHAN = 1; + genvar i ; + + // FX2 Bug Fix + reg [8:0] read_count; + always @(negedge usbclk) + if(bus_reset) + read_count <= #1 9'd0; + else if(RD & ~read_count[8]) + read_count <= #1 read_count + 9'd1; + else + read_count <= #1 RD ? read_count : 9'b0; + + // Time counter + reg [31:0] timestamp_clock; + always @(posedge rxclk) + if (reset) + timestamp_clock <= 0; + else + timestamp_clock <= timestamp_clock + 1; + + // USB side fifo + wire [11:0] rdusedw; + wire [11:0] wrusedw; + wire [15:0] fifodata; + wire [15:0] fifodata_il[0:NUM_CHAN]; + wire WR; + wire have_space; + reg sel; + reg wr; + + always@(posedge rxclk) + begin + if(reset) + begin + sel<=1; + wr<=0; + end + else if(rxstrobe) + begin + sel<=0; + wr<=1; + end + else if(wr&~sel) + sel<=1; + else if(wr&sel) + wr<=0; + else + wr<=0; + end + + assign fifodata_il[0] = (sel)?ch_1:ch_0; + assign fifodata_il[1] = (sel)?ch_3:ch_2; + + fifo_4kx16_dc rx_usb_fifo ( + .aclr ( reset ), + .data ( fifodata ), + .rdclk ( ~usbclk ), + .rdreq ( RD & ~read_count[8] ), + .wrclk ( rxclk ), + .wrreq ( WR ), + .q ( usbdata ), + .rdempty ( ), + .rdusedw ( rdusedw ), + .wrfull ( ), + .wrusedw ( wrusedw ) ); + + assign have_pkt_rdy = (rdusedw >= 12'd256); + assign have_space = (wrusedw < 12'd760); + + // Rx side fifos + // These are of size [NUM_CHAN:0] because the extra channel is used for the + // RX command channel. If there were no command channel, they would be + // NUM_CHAN-1. + wire chan_rdreq; + wire [15:0] chan_fifodata; + wire [9:0] chan_usedw; + wire [NUM_CHAN:0] chan_empty; + wire [3:0] rd_select; + wire [NUM_CHAN:0] rx_full; + + packet_builder #(NUM_CHAN) rx_pkt_builer ( + .rxclk ( rxclk ), + .reset ( reset ), + .timestamp_clock ( timestamp_clock ), + .channels ( NUM_CHAN ), + .chan_rdreq ( chan_rdreq ), + .chan_fifodata ( chan_fifodata ), + .chan_empty ( chan_empty ), + .rd_select ( rd_select ), + .chan_usedw ( chan_usedw ), + .WR ( WR ), + .fifodata ( fifodata ), + .have_space ( have_space ), + .rssi_0(rssi_0), .rssi_1(rssi_1), + .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug), + .underrun(tx_underrun)); + + // Detect overrun + always @(posedge rxclk) + if(reset) + rx_overrun <= 1'b0; + else if(rx_full[0]) + rx_overrun <= 1'b1; + else if(clear_status) + rx_overrun <= 1'b0; + + + // FIXME: what is the purpose of these two lines? + wire [15:0]ch[NUM_CHAN:0]; + assign ch[0] = ch_0; + + wire cmd_empty; + + always @(posedge rxclk) + if(reset) + rx_WR_enabled <= 1; + else if(cmd_empty) + rx_WR_enabled <= 1; + else if(rx_WR_done) + rx_WR_enabled <= 0; + + + // Of Size 0:NUM_CHAN due to extra command channel. + wire [15:0] dataout [0:NUM_CHAN]; + wire [9:0] usedw [0:NUM_CHAN]; + wire empty[0:NUM_CHAN]; + + generate for (i = 0 ; i < NUM_CHAN; i = i + 1) + begin : generate_channel_fifos + + wire rdreq; + + assign rdreq = (rd_select == i) & chan_rdreq; + + fifo_1kx16 rx_chan_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( fifodata_il[i] ), + .rdreq ( rdreq ), + .wrreq ( ~rx_full[i] & wr), + .empty (empty[i]), + .full (rx_full[i]), + .q ( dataout[i]), + .usedw ( usedw[i]), + .almost_empty(chan_empty[i]) + ); + end + endgenerate + + wire [7:0] debug; + + fifo_1kx16 rx_cmd_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( rx_databus ), + .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), + .wrreq ( rx_WR & rx_WR_enabled), + .empty ( cmd_empty), + .full ( rx_full[NUM_CHAN] ), + .q ( dataout[NUM_CHAN]), + .usedw ( usedw[NUM_CHAN] ) + ); + + assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; + assign chan_fifodata = dataout[rd_select]; + assign chan_usedw = usedw[rd_select]; + assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr}; + +endmodule diff --git a/usrp1/inband_lib/tx_buffer_inband.v b/usrp1/inband_lib/tx_buffer_inband.v new file mode 100755 index 000000000..2dd75f42f --- /dev/null +++ b/usrp1/inband_lib/tx_buffer_inband.v @@ -0,0 +1,143 @@ +module tx_buffer_inband + ( //System + input wire usbclk, input wire bus_reset, input wire reset, + input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels, + //output transmit signals + output wire [15:0] tx_i_0, output wire [15:0] tx_q_0, + output wire [15:0] tx_i_1, output wire [15:0] tx_q_1, + output wire [15:0] tx_i_2, output wire [15:0] tx_q_2, + output wire [15:0] tx_i_3, output wire [15:0] tx_q_3, + input wire txclk, input wire txstrobe, input wire WR, + input wire clear_status, output wire tx_empty, output wire [15:0] debugbus, + //command reader io + output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done, + input wire rx_WR_enabled, + //register io + output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr, + input wire [31:0] reg_data_out, + //input characteristic signals + input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, + input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold, + output wire [1:0] tx_underrun, + //system stop + output wire stop, output wire [15:0] stop_time); + + parameter NUM_CHAN = 1 ; + + /* To generate channel readers */ + genvar i ; + + /* These will eventually be external register */ + reg [31:0] timestamp_clock ; + wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ; + wire [31:0] rssi [3:0]; + assign rssi[0] = rssi_0; + assign rssi[1] = rssi_1; + assign rssi[2] = rssi_2; + assign rssi[3] = rssi_3; + + always @(posedge txclk) + if (reset) + timestamp_clock <= 0; + else + timestamp_clock <= timestamp_clock + 1; + + + /* Connections between tx_usb_fifo_reader and + cnannel/command processing blocks */ + wire [31:0] tx_data_bus ; + wire [NUM_CHAN:0] chan_WR ; + wire [NUM_CHAN:0] chan_done ; + + /* Connections between data block and the + FX2/TX chains */ + wire [NUM_CHAN:0] chan_underrun; + wire [NUM_CHAN:0] chan_txempty; + + /* Conections between tx_data_packet_fifo and + its reader + strobe generator */ + wire [31:0] chan_fifodata [NUM_CHAN:0] ; + wire chan_pkt_waiting [NUM_CHAN:0] ; + wire chan_rdreq [NUM_CHAN:0] ; + wire chan_skip [NUM_CHAN:0] ; + wire chan_have_space [NUM_CHAN:0] ; + + wire [14:0] debug [NUM_CHAN:0]; + + /* Outputs to transmit chains */ + wire [15:0] tx_i [NUM_CHAN:0] ; + wire [15:0] tx_q [NUM_CHAN:0] ; + + assign tx_i[NUM_CHAN] = 0; + assign tx_q[NUM_CHAN] = 0; + + assign have_space = chan_have_space[0] & chan_have_space[1]; + assign tx_empty = chan_txempty[0] & chan_txempty[1] ; + + assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; + assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; + assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; + assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ; + + assign tx_q_2 = 16'b0 ; + assign tx_i_2 = 16'b0 ; + assign tx_q_3 = 16'b0 ; + assign tx_i_3 = 16'b0 ; + assign tx_i_3 = 16'b0 ; + + assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done, + chan_pkt_waiting[0], chan_pkt_waiting[1], + chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]}; + + wire [31:0] usbdata_final; + wire WR_final; + + tx_packer tx_usb_packer + (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR), + .usbdata(usbdata), .reset(reset), .txclk(txclk), + .usbdata_final(usbdata_final), .WR_final(WR_final)); + + channel_demux #(NUM_CHAN) channel_demuxer + (.usbdata_final(usbdata_final), .WR_final(WR_final), + .reset(reset), .txclk(txclk), .WR_channel(chan_WR), + .WR_done_channel(chan_done), .ram_data(tx_data_bus)); + + generate for (i = 0 ; i < NUM_CHAN; i = i + 1) + begin : generate_channel_readers + assign tx_underrun[i] = chan_underrun[i]; + + channel_ram tx_data_packet_fifo + (.reset(reset), .txclk(txclk), .datain(tx_data_bus), + .WR(chan_WR[i]), .WR_done(chan_done[i]), + .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]), + .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]), + .RD_done(chan_skip[i])); + + chan_fifo_reader tx_chan_reader + (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe), + .timestamp_clock(timestamp_clock), .samples_format(4'b0), + .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]), + .skip(chan_skip[i]), .rdreq(chan_rdreq[i]), + .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]), + .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]), + .threshhold(threshhold), .rssi_wait(rssi_wait)); + end + endgenerate + + + channel_ram tx_cmd_packet_fifo + (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]), + .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]), + .dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]), + .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN])); + + cmd_reader tx_cmd_reader + (.reset(reset), .txclk(txclk), .timestamp_clock(timestamp_clock), .skip(chan_skip[NUM_CHAN]), + .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]), + .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus), + .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled), + .reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr), + .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time)); + +endmodule // tx_buffer + diff --git a/usrp1/inband_lib/tx_packer.v b/usrp1/inband_lib/tx_packer.v new file mode 100644 index 000000000..2f19b21f3 --- /dev/null +++ b/usrp1/inband_lib/tx_packer.v @@ -0,0 +1,119 @@ +module tx_packer + ( //FX2 Side + input bus_reset, + input usbclk, + input WR_fx2, + input [15:0]usbdata, + + // TX Side + input reset, + input txclk, + output reg [31:0] usbdata_final, + output reg WR_final); + + reg [8:0] write_count; + + /* Fix FX2 bug */ + always @(posedge usbclk) + begin + if(bus_reset) // Use bus reset because this is on usbclk + write_count <= #1 0; + else if(WR_fx2 & ~write_count[8]) + write_count <= #1 write_count + 9'd1; + else + write_count <= #1 WR_fx2 ? write_count : 9'b0; + end + + reg WR_fx2_fixed; + reg [15:0]usbdata_fixed; + + always @(posedge usbclk) + begin + WR_fx2_fixed <= WR_fx2 & ~write_count[8]; + usbdata_fixed <= usbdata; + end + + /* Used to convert 16 bits bus_data to the 32 bits wide fifo */ + reg word_complete ; + reg [15:0] usbdata_delayed ; + reg writing ; + wire [31:0] usbdata_packed ; + wire WR_packed ; + + always @(posedge usbclk) + begin + if (bus_reset) + begin + word_complete <= 0 ; + writing <= 0 ; + end + else if (WR_fx2_fixed) + begin + writing <= 1 ; + if (word_complete) + word_complete <= 0 ; + else + begin + usbdata_delayed <= usbdata_fixed ; + word_complete <= 1 ; + end + end + else + writing <= 0 ; + end + + assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ; + assign WR_packed = word_complete & writing ; + + /* Make sure data are sync with usbclk */ + reg [31:0]usbdata_usbclk; + reg WR_usbclk; + + always @(posedge usbclk) + begin + if (WR_packed) + usbdata_usbclk <= usbdata_packed; + WR_usbclk <= WR_packed; + end + + /* Cross clock boundaries */ + reg [31:0] usbdata_tx ; + reg WR_tx; + reg WR_1; + reg WR_2; + + always @(posedge txclk) usbdata_tx <= usbdata_usbclk; + + always @(posedge txclk) + if (reset) + WR_1 <= 0; + else + WR_1 <= WR_usbclk; + + always @(posedge txclk) + if (reset) + WR_2 <= 0; + else + WR_2 <= WR_1; + + always @(posedge txclk) + begin + if (reset) + WR_tx <= 0; + else + WR_tx <= WR_1 & ~WR_2; + end + + always @(posedge txclk) + begin + if (reset) + WR_final <= 0; + else + begin + WR_final <= WR_tx; + if (WR_tx) + usbdata_final <= usbdata_tx; + end + end + +endmodule diff --git a/usrp1/inband_lib/usb_packet_fifo.v b/usrp1/inband_lib/usb_packet_fifo.v new file mode 100755 index 000000000..c416e2bdb --- /dev/null +++ b/usrp1/inband_lib/usb_packet_fifo.v @@ -0,0 +1,112 @@ +module usb_packet_fifo + ( input reset, + input clock_in, + input clock_out, + input [15:0]ram_data_in, + input write_enable, + output reg [15:0]ram_data_out, + output reg pkt_waiting, + output reg have_space, + input read_enable, + input skip_packet ) ; + + /* Some parameters for usage later on */ + parameter DATA_WIDTH = 16 ; + parameter NUM_PACKETS = 4 ; + + /* Create the RAM here */ + reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ; + + /* Create the address signals */ + reg [7-2+NUM_PACKETS:0] usb_ram_ain ; + reg [7:0] usb_ram_offset ; + reg [1:0] usb_ram_packet ; + + wire [7-2+NUM_PACKETS:0] usb_ram_aout ; + reg isfull; + + assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ; + + // Check if there is one full packet to process + always @(usb_ram_ain, usb_ram_aout) + begin + if (reset) + pkt_waiting <= 0; + else if (usb_ram_ain == usb_ram_aout) + pkt_waiting <= isfull; + else if (usb_ram_ain > usb_ram_aout) + pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256; + else + pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256; + end + + // Check if there is room + always @(usb_ram_ain, usb_ram_aout) + begin + if (reset) + have_space <= 1; + else if (usb_ram_ain == usb_ram_aout) + have_space <= ~isfull; + else if (usb_ram_ain > usb_ram_aout) + have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1); + else + have_space <= (usb_ram_aout - usb_ram_ain) >= 256; + end + + /* RAM Write Address process */ + always @(posedge clock_in) + begin + if( reset ) + usb_ram_ain <= 0 ; + else + if( write_enable ) + begin + usb_ram_ain <= usb_ram_ain + 1 ; + if (usb_ram_ain + 1 == usb_ram_aout) + isfull <= 1; + end + end + + /* RAM Writing process */ + always @(posedge clock_in) + begin + if( write_enable ) + begin + usb_ram[usb_ram_ain] <= ram_data_in ; + end + end + + /* RAM Read Address process */ + always @(posedge clock_out) + begin + if( reset ) + begin + usb_ram_packet <= 0 ; + usb_ram_offset <= 0 ; + isfull <= 0; + end + else + if( skip_packet ) + begin + usb_ram_packet <= usb_ram_packet + 1 ; + usb_ram_offset <= 0 ; + end + else if(read_enable) + if( usb_ram_offset == 8'b11111111 ) + begin + usb_ram_offset <= 0 ; + usb_ram_packet <= usb_ram_packet + 1 ; + end + else + usb_ram_offset <= usb_ram_offset + 1 ; + if (usb_ram_ain == usb_ram_aout) + isfull <= 0; + end + + /* RAM Reading Process */ + always @(posedge clock_out) + begin + ram_data_out <= usb_ram[usb_ram_aout] ; + end + +endmodule \ No newline at end of file diff --git a/usrp1/megacells/.gitignore b/usrp1/megacells/.gitignore new file mode 100644 index 000000000..c2de89b27 --- /dev/null +++ b/usrp1/megacells/.gitignore @@ -0,0 +1 @@ +/db diff --git a/usrp1/megacells/accum32.bsf b/usrp1/megacells/accum32.bsf new file mode 100755 index 000000000..494a8200f --- /dev/null +++ b/usrp1/megacells/accum32.bsf @@ -0,0 +1,86 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 240 120) + (text "accum32" (rect 87 2 166 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 101 31 116)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 24 82 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 16 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 20 40 51 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clken" (rect 20 56 51 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 80 41 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 240 56) + (output) + (text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "result[31..0]" (rect 152 40 221 56)(font "Arial" (font_size 8))) + (line (pt 240 56)(pt 224 56)(line_width 3)) + ) + (drawing + (text "acc" (rect 102 48 123 64)(font "Arial" (font_size 8))) + (text "SIGNED" (rect 177 18 214 32)(font "Arial" )) + (line (pt 16 16)(pt 224 16)(line_width 1)) + (line (pt 16 16)(pt 16 104)(line_width 1)) + (line (pt 16 104)(pt 224 104)(line_width 1)) + (line (pt 224 16)(pt 224 104)(line_width 1)) + (line (pt 88 24)(pt 136 48)(line_width 1)) + (line (pt 136 64)(pt 136 48)(line_width 1)) + (line (pt 88 88)(pt 136 64)(line_width 1)) + (line (pt 88 24)(pt 88 88)(line_width 1)) + (line (pt 16 40)(pt 88 40)(line_width 1)) + (line (pt 16 56)(pt 88 56)(line_width 1)) + (line (pt 136 56)(pt 224 56)(line_width 1)) + (line (pt 16 72)(pt 88 72)(line_width 1)) + (line (pt 16 72)(pt 88 72)(line_width 1)) + (line (pt 16 96)(pt 104 96)(line_width 1)) + (line (pt 104 96)(pt 104 80)(line_width 1)) + ) +) diff --git a/usrp1/megacells/accum32.cmp b/usrp1/megacells/accum32.cmp new file mode 100755 index 000000000..55b5fdc22 --- /dev/null +++ b/usrp1/megacells/accum32.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component accum32 + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + clock : IN STD_LOGIC := '0'; + clken : IN STD_LOGIC := '1'; + aclr : IN STD_LOGIC := '0'; + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/usrp1/megacells/accum32.inc b/usrp1/megacells/accum32.inc new file mode 100755 index 000000000..6c6690025 --- /dev/null +++ b/usrp1/megacells/accum32.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION accum32 +( + data[31..0], + clock, + clken, + aclr +) + +RETURNS ( + result[31..0] +); diff --git a/usrp1/megacells/accum32.v b/usrp1/megacells/accum32.v new file mode 100755 index 000000000..ce50cbbf1 --- /dev/null +++ b/usrp1/megacells/accum32.v @@ -0,0 +1,765 @@ +// megafunction wizard: %ALTACCUMULATE%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altaccumulate + +// ============================================================ +// File Name: accum32.v +// Megafunction Name(s): +// altaccumulate +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result +//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END + +//synthesis_resources = lut 32 +module accum32_accum_nta + ( + aclr, + clken, + clock, + data, + result) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clken; + input clock; + input [31:0] data; + output [31:0] result; + + wire [0:0] wire_acc_cella_0cout; + wire [0:0] wire_acc_cella_1cout; + wire [0:0] wire_acc_cella_2cout; + wire [0:0] wire_acc_cella_3cout; + wire [0:0] wire_acc_cella_4cout; + wire [0:0] wire_acc_cella_5cout; + wire [0:0] wire_acc_cella_6cout; + wire [0:0] wire_acc_cella_7cout; + wire [0:0] wire_acc_cella_8cout; + wire [0:0] wire_acc_cella_9cout; + wire [0:0] wire_acc_cella_10cout; + wire [0:0] wire_acc_cella_11cout; + wire [0:0] wire_acc_cella_12cout; + wire [0:0] wire_acc_cella_13cout; + wire [0:0] wire_acc_cella_14cout; + wire [0:0] wire_acc_cella_15cout; + wire [0:0] wire_acc_cella_16cout; + wire [0:0] wire_acc_cella_17cout; + wire [0:0] wire_acc_cella_18cout; + wire [0:0] wire_acc_cella_19cout; + wire [0:0] wire_acc_cella_20cout; + wire [0:0] wire_acc_cella_21cout; + wire [0:0] wire_acc_cella_22cout; + wire [0:0] wire_acc_cella_23cout; + wire [0:0] wire_acc_cella_24cout; + wire [0:0] wire_acc_cella_25cout; + wire [0:0] wire_acc_cella_26cout; + wire [0:0] wire_acc_cella_27cout; + wire [0:0] wire_acc_cella_28cout; + wire [0:0] wire_acc_cella_29cout; + wire [0:0] wire_acc_cella_30cout; + wire [31:0] wire_acc_cella_dataa; + wire [31:0] wire_acc_cella_datab; + wire [31:0] wire_acc_cella_datac; + wire [31:0] wire_acc_cella_regout; + wire sload; + + stratix_lcell acc_cella_0 + ( + .aclr(aclr), + .cin(1'b0), + .clk(clock), + .cout(wire_acc_cella_0cout[0:0]), + .dataa(wire_acc_cella_dataa[0:0]), + .datab(wire_acc_cella_datab[0:0]), + .datac(wire_acc_cella_datac[0:0]), + .ena(clken), + .regout(wire_acc_cella_regout[0:0]), + .sload(sload)); + defparam + acc_cella_0.cin_used = "true", + acc_cella_0.lut_mask = "96e8", + acc_cella_0.operation_mode = "arithmetic", + acc_cella_0.sum_lutc_input = "cin", + acc_cella_0.synch_mode = "on", + acc_cella_0.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_1 + ( + .aclr(aclr), + .cin(wire_acc_cella_0cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_1cout[0:0]), + .dataa(wire_acc_cella_dataa[1:1]), + .datab(wire_acc_cella_datab[1:1]), + .datac(wire_acc_cella_datac[1:1]), + .ena(clken), + .regout(wire_acc_cella_regout[1:1]), + .sload(sload)); + defparam + acc_cella_1.cin_used = "true", + acc_cella_1.lut_mask = "96e8", + acc_cella_1.operation_mode = "arithmetic", + acc_cella_1.sum_lutc_input = "cin", + acc_cella_1.synch_mode = "on", + acc_cella_1.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_2 + ( + .aclr(aclr), + .cin(wire_acc_cella_1cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_2cout[0:0]), + .dataa(wire_acc_cella_dataa[2:2]), + .datab(wire_acc_cella_datab[2:2]), + .datac(wire_acc_cella_datac[2:2]), + .ena(clken), + .regout(wire_acc_cella_regout[2:2]), + .sload(sload)); + defparam + acc_cella_2.cin_used = "true", + acc_cella_2.lut_mask = "96e8", + acc_cella_2.operation_mode = "arithmetic", + acc_cella_2.sum_lutc_input = "cin", + acc_cella_2.synch_mode = "on", + acc_cella_2.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_3 + ( + .aclr(aclr), + .cin(wire_acc_cella_2cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_3cout[0:0]), + .dataa(wire_acc_cella_dataa[3:3]), + .datab(wire_acc_cella_datab[3:3]), + .datac(wire_acc_cella_datac[3:3]), + .ena(clken), + .regout(wire_acc_cella_regout[3:3]), + .sload(sload)); + defparam + acc_cella_3.cin_used = "true", + acc_cella_3.lut_mask = "96e8", + acc_cella_3.operation_mode = "arithmetic", + acc_cella_3.sum_lutc_input = "cin", + acc_cella_3.synch_mode = "on", + acc_cella_3.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_4 + ( + .aclr(aclr), + .cin(wire_acc_cella_3cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_4cout[0:0]), + .dataa(wire_acc_cella_dataa[4:4]), + .datab(wire_acc_cella_datab[4:4]), + .datac(wire_acc_cella_datac[4:4]), + .ena(clken), + .regout(wire_acc_cella_regout[4:4]), + .sload(sload)); + defparam + acc_cella_4.cin_used = "true", + acc_cella_4.lut_mask = "96e8", + acc_cella_4.operation_mode = "arithmetic", + acc_cella_4.sum_lutc_input = "cin", + acc_cella_4.synch_mode = "on", + acc_cella_4.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_5 + ( + .aclr(aclr), + .cin(wire_acc_cella_4cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_5cout[0:0]), + .dataa(wire_acc_cella_dataa[5:5]), + .datab(wire_acc_cella_datab[5:5]), + .datac(wire_acc_cella_datac[5:5]), + .ena(clken), + .regout(wire_acc_cella_regout[5:5]), + .sload(sload)); + defparam + acc_cella_5.cin_used = "true", + acc_cella_5.lut_mask = "96e8", + acc_cella_5.operation_mode = "arithmetic", + acc_cella_5.sum_lutc_input = "cin", + acc_cella_5.synch_mode = "on", + acc_cella_5.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_6 + ( + .aclr(aclr), + .cin(wire_acc_cella_5cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_6cout[0:0]), + .dataa(wire_acc_cella_dataa[6:6]), + .datab(wire_acc_cella_datab[6:6]), + .datac(wire_acc_cella_datac[6:6]), + .ena(clken), + .regout(wire_acc_cella_regout[6:6]), + .sload(sload)); + defparam + acc_cella_6.cin_used = "true", + acc_cella_6.lut_mask = "96e8", + acc_cella_6.operation_mode = "arithmetic", + acc_cella_6.sum_lutc_input = "cin", + acc_cella_6.synch_mode = "on", + acc_cella_6.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_7 + ( + .aclr(aclr), + .cin(wire_acc_cella_6cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_7cout[0:0]), + .dataa(wire_acc_cella_dataa[7:7]), + .datab(wire_acc_cella_datab[7:7]), + .datac(wire_acc_cella_datac[7:7]), + .ena(clken), + .regout(wire_acc_cella_regout[7:7]), + .sload(sload)); + defparam + acc_cella_7.cin_used = "true", + acc_cella_7.lut_mask = "96e8", + acc_cella_7.operation_mode = "arithmetic", + acc_cella_7.sum_lutc_input = "cin", + acc_cella_7.synch_mode = "on", + acc_cella_7.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_8 + ( + .aclr(aclr), + .cin(wire_acc_cella_7cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_8cout[0:0]), + .dataa(wire_acc_cella_dataa[8:8]), + .datab(wire_acc_cella_datab[8:8]), + .datac(wire_acc_cella_datac[8:8]), + .ena(clken), + .regout(wire_acc_cella_regout[8:8]), + .sload(sload)); + defparam + acc_cella_8.cin_used = "true", + acc_cella_8.lut_mask = "96e8", + acc_cella_8.operation_mode = "arithmetic", + acc_cella_8.sum_lutc_input = "cin", + acc_cella_8.synch_mode = "on", + acc_cella_8.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_9 + ( + .aclr(aclr), + .cin(wire_acc_cella_8cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_9cout[0:0]), + .dataa(wire_acc_cella_dataa[9:9]), + .datab(wire_acc_cella_datab[9:9]), + .datac(wire_acc_cella_datac[9:9]), + .ena(clken), + .regout(wire_acc_cella_regout[9:9]), + .sload(sload)); + defparam + acc_cella_9.cin_used = "true", + acc_cella_9.lut_mask = "96e8", + acc_cella_9.operation_mode = "arithmetic", + acc_cella_9.sum_lutc_input = "cin", + acc_cella_9.synch_mode = "on", + acc_cella_9.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_10 + ( + .aclr(aclr), + .cin(wire_acc_cella_9cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_10cout[0:0]), + .dataa(wire_acc_cella_dataa[10:10]), + .datab(wire_acc_cella_datab[10:10]), + .datac(wire_acc_cella_datac[10:10]), + .ena(clken), + .regout(wire_acc_cella_regout[10:10]), + .sload(sload)); + defparam + acc_cella_10.cin_used = "true", + acc_cella_10.lut_mask = "96e8", + acc_cella_10.operation_mode = "arithmetic", + acc_cella_10.sum_lutc_input = "cin", + acc_cella_10.synch_mode = "on", + acc_cella_10.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_11 + ( + .aclr(aclr), + .cin(wire_acc_cella_10cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_11cout[0:0]), + .dataa(wire_acc_cella_dataa[11:11]), + .datab(wire_acc_cella_datab[11:11]), + .datac(wire_acc_cella_datac[11:11]), + .ena(clken), + .regout(wire_acc_cella_regout[11:11]), + .sload(sload)); + defparam + acc_cella_11.cin_used = "true", + acc_cella_11.lut_mask = "96e8", + acc_cella_11.operation_mode = "arithmetic", + acc_cella_11.sum_lutc_input = "cin", + acc_cella_11.synch_mode = "on", + acc_cella_11.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_12 + ( + .aclr(aclr), + .cin(wire_acc_cella_11cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_12cout[0:0]), + .dataa(wire_acc_cella_dataa[12:12]), + .datab(wire_acc_cella_datab[12:12]), + .datac(wire_acc_cella_datac[12:12]), + .ena(clken), + .regout(wire_acc_cella_regout[12:12]), + .sload(sload)); + defparam + acc_cella_12.cin_used = "true", + acc_cella_12.lut_mask = "96e8", + acc_cella_12.operation_mode = "arithmetic", + acc_cella_12.sum_lutc_input = "cin", + acc_cella_12.synch_mode = "on", + acc_cella_12.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_13 + ( + .aclr(aclr), + .cin(wire_acc_cella_12cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_13cout[0:0]), + .dataa(wire_acc_cella_dataa[13:13]), + .datab(wire_acc_cella_datab[13:13]), + .datac(wire_acc_cella_datac[13:13]), + .ena(clken), + .regout(wire_acc_cella_regout[13:13]), + .sload(sload)); + defparam + acc_cella_13.cin_used = "true", + acc_cella_13.lut_mask = "96e8", + acc_cella_13.operation_mode = "arithmetic", + acc_cella_13.sum_lutc_input = "cin", + acc_cella_13.synch_mode = "on", + acc_cella_13.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_14 + ( + .aclr(aclr), + .cin(wire_acc_cella_13cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_14cout[0:0]), + .dataa(wire_acc_cella_dataa[14:14]), + .datab(wire_acc_cella_datab[14:14]), + .datac(wire_acc_cella_datac[14:14]), + .ena(clken), + .regout(wire_acc_cella_regout[14:14]), + .sload(sload)); + defparam + acc_cella_14.cin_used = "true", + acc_cella_14.lut_mask = "96e8", + acc_cella_14.operation_mode = "arithmetic", + acc_cella_14.sum_lutc_input = "cin", + acc_cella_14.synch_mode = "on", + acc_cella_14.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_15 + ( + .aclr(aclr), + .cin(wire_acc_cella_14cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_15cout[0:0]), + .dataa(wire_acc_cella_dataa[15:15]), + .datab(wire_acc_cella_datab[15:15]), + .datac(wire_acc_cella_datac[15:15]), + .ena(clken), + .regout(wire_acc_cella_regout[15:15]), + .sload(sload)); + defparam + acc_cella_15.cin_used = "true", + acc_cella_15.lut_mask = "96e8", + acc_cella_15.operation_mode = "arithmetic", + acc_cella_15.sum_lutc_input = "cin", + acc_cella_15.synch_mode = "on", + acc_cella_15.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_16 + ( + .aclr(aclr), + .cin(wire_acc_cella_15cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_16cout[0:0]), + .dataa(wire_acc_cella_dataa[16:16]), + .datab(wire_acc_cella_datab[16:16]), + .datac(wire_acc_cella_datac[16:16]), + .ena(clken), + .regout(wire_acc_cella_regout[16:16]), + .sload(sload)); + defparam + acc_cella_16.cin_used = "true", + acc_cella_16.lut_mask = "96e8", + acc_cella_16.operation_mode = "arithmetic", + acc_cella_16.sum_lutc_input = "cin", + acc_cella_16.synch_mode = "on", + acc_cella_16.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_17 + ( + .aclr(aclr), + .cin(wire_acc_cella_16cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_17cout[0:0]), + .dataa(wire_acc_cella_dataa[17:17]), + .datab(wire_acc_cella_datab[17:17]), + .datac(wire_acc_cella_datac[17:17]), + .ena(clken), + .regout(wire_acc_cella_regout[17:17]), + .sload(sload)); + defparam + acc_cella_17.cin_used = "true", + acc_cella_17.lut_mask = "96e8", + acc_cella_17.operation_mode = "arithmetic", + acc_cella_17.sum_lutc_input = "cin", + acc_cella_17.synch_mode = "on", + acc_cella_17.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_18 + ( + .aclr(aclr), + .cin(wire_acc_cella_17cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_18cout[0:0]), + .dataa(wire_acc_cella_dataa[18:18]), + .datab(wire_acc_cella_datab[18:18]), + .datac(wire_acc_cella_datac[18:18]), + .ena(clken), + .regout(wire_acc_cella_regout[18:18]), + .sload(sload)); + defparam + acc_cella_18.cin_used = "true", + acc_cella_18.lut_mask = "96e8", + acc_cella_18.operation_mode = "arithmetic", + acc_cella_18.sum_lutc_input = "cin", + acc_cella_18.synch_mode = "on", + acc_cella_18.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_19 + ( + .aclr(aclr), + .cin(wire_acc_cella_18cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_19cout[0:0]), + .dataa(wire_acc_cella_dataa[19:19]), + .datab(wire_acc_cella_datab[19:19]), + .datac(wire_acc_cella_datac[19:19]), + .ena(clken), + .regout(wire_acc_cella_regout[19:19]), + .sload(sload)); + defparam + acc_cella_19.cin_used = "true", + acc_cella_19.lut_mask = "96e8", + acc_cella_19.operation_mode = "arithmetic", + acc_cella_19.sum_lutc_input = "cin", + acc_cella_19.synch_mode = "on", + acc_cella_19.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_20 + ( + .aclr(aclr), + .cin(wire_acc_cella_19cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_20cout[0:0]), + .dataa(wire_acc_cella_dataa[20:20]), + .datab(wire_acc_cella_datab[20:20]), + .datac(wire_acc_cella_datac[20:20]), + .ena(clken), + .regout(wire_acc_cella_regout[20:20]), + .sload(sload)); + defparam + acc_cella_20.cin_used = "true", + acc_cella_20.lut_mask = "96e8", + acc_cella_20.operation_mode = "arithmetic", + acc_cella_20.sum_lutc_input = "cin", + acc_cella_20.synch_mode = "on", + acc_cella_20.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_21 + ( + .aclr(aclr), + .cin(wire_acc_cella_20cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_21cout[0:0]), + .dataa(wire_acc_cella_dataa[21:21]), + .datab(wire_acc_cella_datab[21:21]), + .datac(wire_acc_cella_datac[21:21]), + .ena(clken), + .regout(wire_acc_cella_regout[21:21]), + .sload(sload)); + defparam + acc_cella_21.cin_used = "true", + acc_cella_21.lut_mask = "96e8", + acc_cella_21.operation_mode = "arithmetic", + acc_cella_21.sum_lutc_input = "cin", + acc_cella_21.synch_mode = "on", + acc_cella_21.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_22 + ( + .aclr(aclr), + .cin(wire_acc_cella_21cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_22cout[0:0]), + .dataa(wire_acc_cella_dataa[22:22]), + .datab(wire_acc_cella_datab[22:22]), + .datac(wire_acc_cella_datac[22:22]), + .ena(clken), + .regout(wire_acc_cella_regout[22:22]), + .sload(sload)); + defparam + acc_cella_22.cin_used = "true", + acc_cella_22.lut_mask = "96e8", + acc_cella_22.operation_mode = "arithmetic", + acc_cella_22.sum_lutc_input = "cin", + acc_cella_22.synch_mode = "on", + acc_cella_22.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_23 + ( + .aclr(aclr), + .cin(wire_acc_cella_22cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_23cout[0:0]), + .dataa(wire_acc_cella_dataa[23:23]), + .datab(wire_acc_cella_datab[23:23]), + .datac(wire_acc_cella_datac[23:23]), + .ena(clken), + .regout(wire_acc_cella_regout[23:23]), + .sload(sload)); + defparam + acc_cella_23.cin_used = "true", + acc_cella_23.lut_mask = "96e8", + acc_cella_23.operation_mode = "arithmetic", + acc_cella_23.sum_lutc_input = "cin", + acc_cella_23.synch_mode = "on", + acc_cella_23.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_24 + ( + .aclr(aclr), + .cin(wire_acc_cella_23cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_24cout[0:0]), + .dataa(wire_acc_cella_dataa[24:24]), + .datab(wire_acc_cella_datab[24:24]), + .datac(wire_acc_cella_datac[24:24]), + .ena(clken), + .regout(wire_acc_cella_regout[24:24]), + .sload(sload)); + defparam + acc_cella_24.cin_used = "true", + acc_cella_24.lut_mask = "96e8", + acc_cella_24.operation_mode = "arithmetic", + acc_cella_24.sum_lutc_input = "cin", + acc_cella_24.synch_mode = "on", + acc_cella_24.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_25 + ( + .aclr(aclr), + .cin(wire_acc_cella_24cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_25cout[0:0]), + .dataa(wire_acc_cella_dataa[25:25]), + .datab(wire_acc_cella_datab[25:25]), + .datac(wire_acc_cella_datac[25:25]), + .ena(clken), + .regout(wire_acc_cella_regout[25:25]), + .sload(sload)); + defparam + acc_cella_25.cin_used = "true", + acc_cella_25.lut_mask = "96e8", + acc_cella_25.operation_mode = "arithmetic", + acc_cella_25.sum_lutc_input = "cin", + acc_cella_25.synch_mode = "on", + acc_cella_25.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_26 + ( + .aclr(aclr), + .cin(wire_acc_cella_25cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_26cout[0:0]), + .dataa(wire_acc_cella_dataa[26:26]), + .datab(wire_acc_cella_datab[26:26]), + .datac(wire_acc_cella_datac[26:26]), + .ena(clken), + .regout(wire_acc_cella_regout[26:26]), + .sload(sload)); + defparam + acc_cella_26.cin_used = "true", + acc_cella_26.lut_mask = "96e8", + acc_cella_26.operation_mode = "arithmetic", + acc_cella_26.sum_lutc_input = "cin", + acc_cella_26.synch_mode = "on", + acc_cella_26.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_27 + ( + .aclr(aclr), + .cin(wire_acc_cella_26cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_27cout[0:0]), + .dataa(wire_acc_cella_dataa[27:27]), + .datab(wire_acc_cella_datab[27:27]), + .datac(wire_acc_cella_datac[27:27]), + .ena(clken), + .regout(wire_acc_cella_regout[27:27]), + .sload(sload)); + defparam + acc_cella_27.cin_used = "true", + acc_cella_27.lut_mask = "96e8", + acc_cella_27.operation_mode = "arithmetic", + acc_cella_27.sum_lutc_input = "cin", + acc_cella_27.synch_mode = "on", + acc_cella_27.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_28 + ( + .aclr(aclr), + .cin(wire_acc_cella_27cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_28cout[0:0]), + .dataa(wire_acc_cella_dataa[28:28]), + .datab(wire_acc_cella_datab[28:28]), + .datac(wire_acc_cella_datac[28:28]), + .ena(clken), + .regout(wire_acc_cella_regout[28:28]), + .sload(sload)); + defparam + acc_cella_28.cin_used = "true", + acc_cella_28.lut_mask = "96e8", + acc_cella_28.operation_mode = "arithmetic", + acc_cella_28.sum_lutc_input = "cin", + acc_cella_28.synch_mode = "on", + acc_cella_28.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_29 + ( + .aclr(aclr), + .cin(wire_acc_cella_28cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_29cout[0:0]), + .dataa(wire_acc_cella_dataa[29:29]), + .datab(wire_acc_cella_datab[29:29]), + .datac(wire_acc_cella_datac[29:29]), + .ena(clken), + .regout(wire_acc_cella_regout[29:29]), + .sload(sload)); + defparam + acc_cella_29.cin_used = "true", + acc_cella_29.lut_mask = "96e8", + acc_cella_29.operation_mode = "arithmetic", + acc_cella_29.sum_lutc_input = "cin", + acc_cella_29.synch_mode = "on", + acc_cella_29.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_30 + ( + .aclr(aclr), + .cin(wire_acc_cella_29cout[0:0]), + .clk(clock), + .cout(wire_acc_cella_30cout[0:0]), + .dataa(wire_acc_cella_dataa[30:30]), + .datab(wire_acc_cella_datab[30:30]), + .datac(wire_acc_cella_datac[30:30]), + .ena(clken), + .regout(wire_acc_cella_regout[30:30]), + .sload(sload)); + defparam + acc_cella_30.cin_used = "true", + acc_cella_30.lut_mask = "96e8", + acc_cella_30.operation_mode = "arithmetic", + acc_cella_30.sum_lutc_input = "cin", + acc_cella_30.synch_mode = "on", + acc_cella_30.lpm_type = "stratix_lcell"; + stratix_lcell acc_cella_31 + ( + .aclr(aclr), + .cin(wire_acc_cella_30cout[0:0]), + .clk(clock), + .dataa(wire_acc_cella_dataa[31:31]), + .datab(wire_acc_cella_datab[31:31]), + .datac(wire_acc_cella_datac[31:31]), + .ena(clken), + .regout(wire_acc_cella_regout[31:31]), + .sload(sload)); + defparam + acc_cella_31.cin_used = "true", + acc_cella_31.lut_mask = "9696", + acc_cella_31.operation_mode = "normal", + acc_cella_31.sum_lutc_input = "cin", + acc_cella_31.synch_mode = "on", + acc_cella_31.lpm_type = "stratix_lcell"; + assign + wire_acc_cella_dataa = data, + wire_acc_cella_datab = wire_acc_cella_regout, + wire_acc_cella_datac = data; + assign + result = wire_acc_cella_regout, + sload = 1'b0; +endmodule //accum32_accum_nta +//VALID FILE + + +module accum32 ( + data, + clock, + clken, + aclr, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] data; + input clock; + input clken; + input aclr; + output [31:0] result; + + wire [31:0] sub_wire0; + wire [31:0] result = sub_wire0[31:0]; + + accum32_accum_nta accum32_accum_nta_component ( + .clken (clken), + .aclr (aclr), + .clock (clock), + .data (data), + .result (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32" +// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0" +// Retrieval info: PRIVATE: SLOAD NUMERIC "0" +// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0" +// Retrieval info: PRIVATE: CIN NUMERIC "0" +// Retrieval info: PRIVATE: CLKEN NUMERIC "1" +// Retrieval info: PRIVATE: ACLR NUMERIC "1" +// Retrieval info: PRIVATE: COUT NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0" +// Retrieval info: PRIVATE: LATENCY NUMERIC "0" +// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32" +// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all diff --git a/usrp1/megacells/accum32_bb.v b/usrp1/megacells/accum32_bb.v new file mode 100755 index 000000000..142bde88c --- /dev/null +++ b/usrp1/megacells/accum32_bb.v @@ -0,0 +1,35 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module accum32 ( + data, + clock, + clken, + aclr, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] data; + input clock; + input clken; + input aclr; + output [31:0] result; + +endmodule + diff --git a/usrp1/megacells/accum32_inst.v b/usrp1/megacells/accum32_inst.v new file mode 100755 index 000000000..c354accae --- /dev/null +++ b/usrp1/megacells/accum32_inst.v @@ -0,0 +1,7 @@ +accum32 accum32_inst ( + .data ( data_sig ), + .clock ( clock_sig ), + .clken ( clken_sig ), + .aclr ( aclr_sig ), + .result ( result_sig ) + ); diff --git a/usrp1/megacells/add32.bsf b/usrp1/megacells/add32.bsf new file mode 100755 index 000000000..b2da9fc2a --- /dev/null +++ b/usrp1/megacells/add32.bsf @@ -0,0 +1,62 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 96) + (text "add32" (rect 58 2 111 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 77 31 92)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "dataa[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) + (text "dataa[7..0]" (rect 4 24 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 64 40)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "datab[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) + (text "datab[7..0]" (rect 4 56 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 3)) + ) + (port + (pt 160 56) + (output) + (text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) + (text "result[7..0]" (rect 95 40 157 56)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 96 56)(line_width 3)) + ) + (drawing + (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8))) + (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8))) + (text "A+B" (rect 68 48 94 64)(font "Arial" (font_size 8))) + (line (pt 64 32)(pt 96 40)(line_width 1)) + (line (pt 96 40)(pt 96 72)(line_width 1)) + (line (pt 96 72)(pt 64 80)(line_width 1)) + (line (pt 64 80)(pt 64 32)(line_width 1)) + ) +) diff --git a/usrp1/megacells/add32.cmp b/usrp1/megacells/add32.cmp new file mode 100755 index 000000000..3b120176d --- /dev/null +++ b/usrp1/megacells/add32.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component add32 + PORT + ( + dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/usrp1/megacells/add32.inc b/usrp1/megacells/add32.inc new file mode 100755 index 000000000..675525713 --- /dev/null +++ b/usrp1/megacells/add32.inc @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION add32 +( + dataa[7..0], + datab[7..0] +) + +RETURNS ( + result[7..0] +); diff --git a/usrp1/megacells/add32.v b/usrp1/megacells/add32.v new file mode 100755 index 000000000..d8090617a --- /dev/null +++ b/usrp1/megacells/add32.v @@ -0,0 +1,221 @@ +// megafunction wizard: %LPM_ADD_SUB%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_add_sub + +// ============================================================ +// File Name: add32.v +// Megafunction Name(s): +// lpm_add_sub +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result +//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END + +//synthesis_resources = lut 8 +module add32_add_sub_nq7 + ( + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input [7:0] dataa; + input [7:0] datab; + output [7:0] result; + + wire [7:0] wire_add_sub_cella_combout; + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [7:0] wire_add_sub_cella_dataa; + wire [7:0] wire_add_sub_cella_datab; + + stratix_lcell add_sub_cella_0 + ( + .cin(1'b0), + .combout(wire_add_sub_cella_combout[0:0]), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0])); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "96e8", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_1 + ( + .cin(wire_add_sub_cella_0cout[0:0]), + .combout(wire_add_sub_cella_combout[1:1]), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1])); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "96e8", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_2 + ( + .cin(wire_add_sub_cella_1cout[0:0]), + .combout(wire_add_sub_cella_combout[2:2]), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2])); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "96e8", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_3 + ( + .cin(wire_add_sub_cella_2cout[0:0]), + .combout(wire_add_sub_cella_combout[3:3]), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3])); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "96e8", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_4 + ( + .cin(wire_add_sub_cella_3cout[0:0]), + .combout(wire_add_sub_cella_combout[4:4]), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4])); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "96e8", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_5 + ( + .cin(wire_add_sub_cella_4cout[0:0]), + .combout(wire_add_sub_cella_combout[5:5]), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5])); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "96e8", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_6 + ( + .cin(wire_add_sub_cella_5cout[0:0]), + .combout(wire_add_sub_cella_combout[6:6]), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6])); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "96e8", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_7 + ( + .cin(wire_add_sub_cella_6cout[0:0]), + .combout(wire_add_sub_cella_combout[7:7]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7])); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "9696", + add_sub_cella_7.operation_mode = "normal", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "stratix_lcell"; + assign + wire_add_sub_cella_dataa = dataa, + wire_add_sub_cella_datab = datab; + assign + result = wire_add_sub_cella_combout; +endmodule //add32_add_sub_nq7 +//VALID FILE + + +module add32 ( + dataa, + datab, + result)/* synthesis synthesis_clearbox = 1 */; + + input [7:0] dataa; + input [7:0] datab; + output [7:0] result; + + wire [7:0] sub_wire0; + wire [7:0] result = sub_wire0[7:0]; + + add32_add_sub_nq7 add32_add_sub_nq7_component ( + .dataa (dataa), + .datab (datab), + .result (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "8" +// Retrieval info: PRIVATE: Function NUMERIC "0" +// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantA NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Overflow NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "0" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] +// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0] +// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0] +// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 +// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0 +// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/usrp1/megacells/add32_bb.v b/usrp1/megacells/add32_bb.v new file mode 100755 index 000000000..8d1588cc6 --- /dev/null +++ b/usrp1/megacells/add32_bb.v @@ -0,0 +1,31 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module add32 ( + dataa, + datab, + result)/* synthesis synthesis_clearbox = 1 */; + + input [7:0] dataa; + input [7:0] datab; + output [7:0] result; + +endmodule + diff --git a/usrp1/megacells/add32_inst.v b/usrp1/megacells/add32_inst.v new file mode 100755 index 000000000..bc7e6d441 --- /dev/null +++ b/usrp1/megacells/add32_inst.v @@ -0,0 +1,5 @@ +add32 add32_inst ( + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .result ( result_sig ) + ); diff --git a/usrp1/megacells/addsub16.bsf b/usrp1/megacells/addsub16.bsf new file mode 100755 index 000000000..9ed6b72ae --- /dev/null +++ b/usrp1/megacells/addsub16.bsf @@ -0,0 +1,96 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 144) + (text "addsub16" (rect 45 2 128 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 125 31 140)(font "Arial" )) + (port + (pt 0 56) + (input) + (text "dataa[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "datab[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 64 88)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 1)) + ) + (port + (pt 0 32) + (input) + (text "add_sub" (rect 0 0 57 16)(font "Arial" (font_size 8))) + (text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 80 32)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clken" (rect 4 96 35 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 74 112)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) + (text "aclr" (rect 4 112 25 128)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 85 128)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "result[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 96 72)(line_width 3)) + ) + (drawing + (text "A" (rect 66 48 75 64)(font "Arial" (font_size 8))) + (text "B" (rect 66 80 75 96)(font "Arial" (font_size 8))) + (text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8))) + (line (pt 64 48)(pt 96 56)(line_width 1)) + (line (pt 96 56)(pt 96 88)(line_width 1)) + (line (pt 96 88)(pt 64 96)(line_width 1)) + (line (pt 64 96)(pt 64 48)(line_width 1)) + (line (pt 80 32)(pt 80 52)(line_width 1)) + (line (pt 106 40)(pt 125 40)(line_width 1)) + (line (pt 74 112)(pt 74 93)(line_width 1)) + (line (pt 85 128)(pt 85 90)(line_width 1)) + (line (pt 64 66)(pt 70 72)(line_width 1)) + (line (pt 70 72)(pt 64 78)(line_width 1)) + ) +) diff --git a/usrp1/megacells/addsub16.cmp b/usrp1/megacells/addsub16.cmp new file mode 100755 index 000000000..e32e01b31 --- /dev/null +++ b/usrp1/megacells/addsub16.cmp @@ -0,0 +1,33 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component addsub16 + PORT + ( + add_sub : IN STD_LOGIC ; + dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + clock : IN STD_LOGIC ; + aclr : IN STD_LOGIC ; + clken : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/usrp1/megacells/addsub16.inc b/usrp1/megacells/addsub16.inc new file mode 100755 index 000000000..846f301d2 --- /dev/null +++ b/usrp1/megacells/addsub16.inc @@ -0,0 +1,34 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION addsub16 +( + add_sub, + dataa[15..0], + datab[15..0], + clock, + aclr, + clken +) + +RETURNS ( + result[15..0] +); diff --git a/usrp1/megacells/addsub16.v b/usrp1/megacells/addsub16.v new file mode 100755 index 000000000..431af3e43 --- /dev/null +++ b/usrp1/megacells/addsub16.v @@ -0,0 +1,438 @@ +// megafunction wizard: %LPM_ADD_SUB%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_add_sub + +// ============================================================ +// File Name: addsub16.v +// Megafunction Name(s): +// lpm_add_sub +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result +//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END + +//synthesis_resources = lut 17 +module addsub16_add_sub_gp9 + ( + aclr, + add_sub, + clken, + clock, + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input aclr; + input add_sub; + input clken; + input clock; + input [15:0] dataa; + input [15:0] datab; + output [15:0] result; + + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [0:0] wire_add_sub_cella_7cout; + wire [0:0] wire_add_sub_cella_8cout; + wire [0:0] wire_add_sub_cella_9cout; + wire [0:0] wire_add_sub_cella_10cout; + wire [0:0] wire_add_sub_cella_11cout; + wire [0:0] wire_add_sub_cella_12cout; + wire [0:0] wire_add_sub_cella_13cout; + wire [0:0] wire_add_sub_cella_14cout; + wire [15:0] wire_add_sub_cella_dataa; + wire [15:0] wire_add_sub_cella_datab; + wire [15:0] wire_add_sub_cella_regout; + wire wire_strx_lcell1_cout; + + stratix_lcell add_sub_cella_0 + ( + .aclr(aclr), + .cin(wire_strx_lcell1_cout), + .clk(clock), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[0:0])); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "96e8", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_1 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_0cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[1:1])); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "96e8", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_2 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_1cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[2:2])); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "96e8", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_3 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_2cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[3:3])); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "96e8", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_4 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_3cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[4:4])); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "96e8", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_5 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_4cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[5:5])); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "96e8", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_6 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_5cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[6:6])); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "96e8", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_7 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_6cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_7cout[0:0]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[7:7])); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "96e8", + add_sub_cella_7.operation_mode = "arithmetic", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_8 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_7cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_8cout[0:0]), + .dataa(wire_add_sub_cella_dataa[8:8]), + .datab(wire_add_sub_cella_datab[8:8]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[8:8])); + defparam + add_sub_cella_8.cin_used = "true", + add_sub_cella_8.lut_mask = "96e8", + add_sub_cella_8.operation_mode = "arithmetic", + add_sub_cella_8.sum_lutc_input = "cin", + add_sub_cella_8.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_9 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_8cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_9cout[0:0]), + .dataa(wire_add_sub_cella_dataa[9:9]), + .datab(wire_add_sub_cella_datab[9:9]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[9:9])); + defparam + add_sub_cella_9.cin_used = "true", + add_sub_cella_9.lut_mask = "96e8", + add_sub_cella_9.operation_mode = "arithmetic", + add_sub_cella_9.sum_lutc_input = "cin", + add_sub_cella_9.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_10 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_9cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_10cout[0:0]), + .dataa(wire_add_sub_cella_dataa[10:10]), + .datab(wire_add_sub_cella_datab[10:10]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[10:10])); + defparam + add_sub_cella_10.cin_used = "true", + add_sub_cella_10.lut_mask = "96e8", + add_sub_cella_10.operation_mode = "arithmetic", + add_sub_cella_10.sum_lutc_input = "cin", + add_sub_cella_10.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_11 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_10cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_11cout[0:0]), + .dataa(wire_add_sub_cella_dataa[11:11]), + .datab(wire_add_sub_cella_datab[11:11]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[11:11])); + defparam + add_sub_cella_11.cin_used = "true", + add_sub_cella_11.lut_mask = "96e8", + add_sub_cella_11.operation_mode = "arithmetic", + add_sub_cella_11.sum_lutc_input = "cin", + add_sub_cella_11.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_12 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_11cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_12cout[0:0]), + .dataa(wire_add_sub_cella_dataa[12:12]), + .datab(wire_add_sub_cella_datab[12:12]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[12:12])); + defparam + add_sub_cella_12.cin_used = "true", + add_sub_cella_12.lut_mask = "96e8", + add_sub_cella_12.operation_mode = "arithmetic", + add_sub_cella_12.sum_lutc_input = "cin", + add_sub_cella_12.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_13 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_12cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_13cout[0:0]), + .dataa(wire_add_sub_cella_dataa[13:13]), + .datab(wire_add_sub_cella_datab[13:13]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[13:13])); + defparam + add_sub_cella_13.cin_used = "true", + add_sub_cella_13.lut_mask = "96e8", + add_sub_cella_13.operation_mode = "arithmetic", + add_sub_cella_13.sum_lutc_input = "cin", + add_sub_cella_13.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_14 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_13cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_14cout[0:0]), + .dataa(wire_add_sub_cella_dataa[14:14]), + .datab(wire_add_sub_cella_datab[14:14]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[14:14])); + defparam + add_sub_cella_14.cin_used = "true", + add_sub_cella_14.lut_mask = "96e8", + add_sub_cella_14.operation_mode = "arithmetic", + add_sub_cella_14.sum_lutc_input = "cin", + add_sub_cella_14.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_15 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_14cout[0:0]), + .clk(clock), + .dataa(wire_add_sub_cella_dataa[15:15]), + .datab(wire_add_sub_cella_datab[15:15]), + .ena(clken), + .inverta((~ add_sub)), + .regout(wire_add_sub_cella_regout[15:15])); + defparam + add_sub_cella_15.cin_used = "true", + add_sub_cella_15.lut_mask = "9696", + add_sub_cella_15.operation_mode = "normal", + add_sub_cella_15.sum_lutc_input = "cin", + add_sub_cella_15.lpm_type = "stratix_lcell"; + assign + wire_add_sub_cella_dataa = datab, + wire_add_sub_cella_datab = dataa; + stratix_lcell strx_lcell1 + ( + .cout(wire_strx_lcell1_cout), + .dataa(1'b0), + .datab((~ add_sub)), + .inverta((~ add_sub))); + defparam + strx_lcell1.cin_used = "false", + strx_lcell1.lut_mask = "00cc", + strx_lcell1.operation_mode = "arithmetic", + strx_lcell1.lpm_type = "stratix_lcell"; + assign + result = wire_add_sub_cella_regout; +endmodule //addsub16_add_sub_gp9 +//VALID FILE + + +module addsub16 ( + add_sub, + dataa, + datab, + clock, + aclr, + clken, + result)/* synthesis synthesis_clearbox = 1 */; + + input add_sub; + input [15:0] dataa; + input [15:0] datab; + input clock; + input aclr; + input clken; + output [15:0] result; + + wire [15:0] sub_wire0; + wire [15:0] result = sub_wire0[15:0]; + + addsub16_add_sub_gp9 addsub16_add_sub_gp9_component ( + .dataa (dataa), + .add_sub (add_sub), + .datab (datab), + .clken (clken), + .aclr (aclr), + .clock (clock), + .result (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "16" +// Retrieval info: PRIVATE: Function NUMERIC "2" +// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantA NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Overflow NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "1" +// Retrieval info: PRIVATE: aclr NUMERIC "1" +// Retrieval info: PRIVATE: clken NUMERIC "1" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub +// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] +// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0] +// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0] +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken +// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0 +// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 +// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0 +// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/usrp1/megacells/addsub16_bb.v b/usrp1/megacells/addsub16_bb.v new file mode 100755 index 000000000..8e1e7c69f --- /dev/null +++ b/usrp1/megacells/addsub16_bb.v @@ -0,0 +1,39 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module addsub16 ( + add_sub, + dataa, + datab, + clock, + aclr, + clken, + result)/* synthesis synthesis_clearbox = 1 */; + + input add_sub; + input [15:0] dataa; + input [15:0] datab; + input clock; + input aclr; + input clken; + output [15:0] result; + +endmodule + diff --git a/usrp1/megacells/addsub16_inst.v b/usrp1/megacells/addsub16_inst.v new file mode 100755 index 000000000..4a81ff2ee --- /dev/null +++ b/usrp1/megacells/addsub16_inst.v @@ -0,0 +1,9 @@ +addsub16 addsub16_inst ( + .add_sub ( add_sub_sig ), + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .clock ( clock_sig ), + .aclr ( aclr_sig ), + .clken ( clken_sig ), + .result ( result_sig ) + ); diff --git a/usrp1/megacells/bustri.bsf b/usrp1/megacells/bustri.bsf new file mode 100755 index 000000000..f1bc3ca7f --- /dev/null +++ b/usrp1/megacells/bustri.bsf @@ -0,0 +1,62 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "bustri" (rect 24 1 61 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[15..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "16" (rect 61 25 71 37)(font "Arial" )) + (text "16" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 56 28)(pt 64 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/usrp1/megacells/bustri.cmp b/usrp1/megacells/bustri.cmp new file mode 100755 index 000000000..87599ca66 --- /dev/null +++ b/usrp1/megacells/bustri.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component bustri + PORT + ( + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/usrp1/megacells/bustri.inc b/usrp1/megacells/bustri.inc new file mode 100755 index 000000000..399950389 --- /dev/null +++ b/usrp1/megacells/bustri.inc @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION bustri +( + data[15..0], + enabledt +) + +RETURNS ( + tridata[15..0] +); diff --git a/usrp1/megacells/bustri.v b/usrp1/megacells/bustri.v new file mode 100755 index 000000000..e40c69476 --- /dev/null +++ b/usrp1/megacells/bustri.v @@ -0,0 +1,71 @@ +// megafunction wizard: %LPM_BUSTRI% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_bustri + +// ============================================================ +// File Name: bustri.v +// Megafunction Name(s): +// lpm_bustri +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +module bustri ( + data, + enabledt, + tridata); + + input [15:0] data; + input enabledt; + inout [15:0] tridata; + + + lpm_bustri lpm_bustri_component ( + .tridata (tridata), + .enabledt (enabledt), + .data (data)); + defparam + lpm_bustri_component.lpm_width = 16, + lpm_bustri_component.lpm_type = "LPM_BUSTRI"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "16" +// Retrieval info: PRIVATE: BiDir NUMERIC "0" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0] +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0 +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/usrp1/megacells/bustri_bb.v b/usrp1/megacells/bustri_bb.v new file mode 100755 index 000000000..4cbc1609c --- /dev/null +++ b/usrp1/megacells/bustri_bb.v @@ -0,0 +1,31 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module bustri ( + data, + enabledt, + tridata); + + input [15:0] data; + input enabledt; + inout [15:0] tridata; + +endmodule + diff --git a/usrp1/megacells/bustri_inst.v b/usrp1/megacells/bustri_inst.v new file mode 100755 index 000000000..2b4e49638 --- /dev/null +++ b/usrp1/megacells/bustri_inst.v @@ -0,0 +1,5 @@ +bustri bustri_inst ( + .data ( data_sig ), + .enabledt ( enabledt_sig ), + .tridata ( tridata_sig ) + ); diff --git a/usrp1/megacells/clk_doubler.v b/usrp1/megacells/clk_doubler.v new file mode 100644 index 000000000..b3762a960 --- /dev/null +++ b/usrp1/megacells/clk_doubler.v @@ -0,0 +1,198 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_doubler.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 156 11/29/2004 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_doubler ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [5:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0) + // synopsys translate_off + , + .activeclock (), + .areset (), + .clkbad (), + .clkena (), + .clkloss (), + .clkswitch (), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena (), + .fbin (), + .locked (), + .pfdena (), + .pllena (), + .scanaclr (), + .scanclk (), + .scandata (), + .scandataout (), + .scandone (), + .scanread (), + .scanwrite (), + .sclkout0 (), + .sclkout1 () + // synopsys translate_on + ); + defparam + altpll_component.clk0_duty_cycle = 50, + altpll_component.lpm_type = "altpll", + altpll_component.clk0_multiply_by = 2, + altpll_component.inclk0_input_frequency = 15625, + altpll_component.clk0_divide_by = 1, + altpll_component.pll_type = "AUTO", + altpll_component.intended_device_family = "Cyclone", + altpll_component.operation_mode = "NORMAL", + altpll_component.compensate_clock = "CLK0", + altpll_component.clk0_phase_shift = "0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE diff --git a/usrp1/megacells/clk_doubler_bb.v b/usrp1/megacells/clk_doubler_bb.v new file mode 100644 index 000000000..48c52e795 --- /dev/null +++ b/usrp1/megacells/clk_doubler_bb.v @@ -0,0 +1,143 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_doubler.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.2 Build 156 11/29/2004 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module clk_doubler ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE diff --git a/usrp1/megacells/dspclkpll.v b/usrp1/megacells/dspclkpll.v new file mode 100644 index 000000000..81e622137 --- /dev/null +++ b/usrp1/megacells/dspclkpll.v @@ -0,0 +1,237 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: dspclkpll.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module dspclkpll ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + + wire [5:0] sub_wire0; + wire [0:0] sub_wire5 = 1'h0; + wire [1:1] sub_wire2 = sub_wire0[1:1]; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire c1 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0) + // synopsys translate_off +, + .fbin (), + .pllena (), + .clkswitch (), + .areset (), + .pfdena (), + .clkena (), + .extclkena (), + .scanclk (), + .scanaclr (), + .scandata (), + .scanread (), + .scanwrite (), + .extclk (), + .clkbad (), + .activeclock (), + .locked (), + .clkloss (), + .scandataout (), + .scandone (), + .sclkout1 (), + .sclkout0 (), + .enable0 (), + .enable1 () + // synopsys translate_on + +); + defparam + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk0_duty_cycle = 50, + altpll_component.lpm_type = "altpll", + altpll_component.clk0_multiply_by = 1, + altpll_component.inclk0_input_frequency = 15625, + altpll_component.clk0_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.pll_type = "AUTO", + altpll_component.clk1_multiply_by = 2, + altpll_component.clk0_time_delay = "0", + altpll_component.intended_device_family = "Cyclone", + altpll_component.operation_mode = "NORMAL", + altpll_component.compensate_clock = "CLK0", + altpll_component.clk1_time_delay = "0", + altpll_component.clk0_phase_shift = "0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE diff --git a/usrp1/megacells/dspclkpll_bb.v b/usrp1/megacells/dspclkpll_bb.v new file mode 100644 index 000000000..489be7bd4 --- /dev/null +++ b/usrp1/megacells/dspclkpll_bb.v @@ -0,0 +1,31 @@ +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module dspclkpll ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + +endmodule + diff --git a/usrp1/megacells/fifo_1kx16.bsf b/usrp1/megacells/fifo_1kx16.bsf new file mode 100755 index 000000000..2de80816f --- /dev/null +++ b/usrp1/megacells/fifo_1kx16.bsf @@ -0,0 +1,107 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 160) + (text "fifo_1kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 144 25 156)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 56) + (output) + (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 144 56)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 1)) + ) + (port + (pt 160 88) + (output) + (text "almost_empty" (rect 0 0 77 14)(font "Arial" (font_size 8))) + (text "almost_empty" (rect 75 82 141 95)(font "Arial" (font_size 8))) + (line (pt 160 88)(pt 144 88)(line_width 1)) + ) + (port + (pt 160 104) + (output) + (text "usedw[9..0]" (rect 0 0 68 14)(font "Arial" (font_size 8))) + (text "usedw[9..0]" (rect 83 98 136 111)(font "Arial" (font_size 8))) + (line (pt 160 104)(pt 144 104)(line_width 3)) + ) + (drawing + (text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial" )) + (text "almost_empty < 504" (rect 58 122 144 134)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 144)(line_width 1)) + (line (pt 144 144)(pt 16 144)(line_width 1)) + (line (pt 16 144)(pt 16 16)(line_width 1)) + (line (pt 16 116)(pt 144 116)(line_width 1)) + (line (pt 16 90)(pt 22 96)(line_width 1)) + (line (pt 22 96)(pt 16 102)(line_width 1)) + ) +) diff --git a/usrp1/megacells/fifo_1kx16.cmp b/usrp1/megacells/fifo_1kx16.cmp new file mode 100755 index 000000000..9b2c2c0c3 --- /dev/null +++ b/usrp1/megacells/fifo_1kx16.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_1kx16 + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + almost_empty : OUT STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +end component; diff --git a/usrp1/megacells/fifo_1kx16.inc b/usrp1/megacells/fifo_1kx16.inc new file mode 100755 index 000000000..0b70afe62 --- /dev/null +++ b/usrp1/megacells/fifo_1kx16.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_1kx16 +( + aclr, + clock, + data[15..0], + rdreq, + wrreq +) + +RETURNS ( + almost_empty, + empty, + full, + q[15..0], + usedw[9..0] +); diff --git a/usrp1/megacells/fifo_1kx16.v b/usrp1/megacells/fifo_1kx16.v new file mode 100755 index 000000000..4f7e94ef5 --- /dev/null +++ b/usrp1/megacells/fifo_1kx16.v @@ -0,0 +1,175 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_1kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_1kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + almost_empty, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output almost_empty; + output empty; + output full; + output [15:0] q; + output [9:0] usedw; + + wire [9:0] sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire sub_wire4; + wire [9:0] usedw = sub_wire0[9:0]; + wire empty = sub_wire1; + wire almost_empty = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire full = sub_wire4; + + scfifo scfifo_component ( + .rdreq (rdreq), + .aclr (aclr), + .clock (clock), + .wrreq (wrreq), + .data (data), + .usedw (sub_wire0), + .empty (sub_wire1), + .almost_empty (sub_wire2), + .q (sub_wire3), + .full (sub_wire4) + // synopsys translate_off + , + .sclr (), + .almost_full () + // synopsys translate_on + ); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.almost_empty_value = 504, + scfifo_component.intended_device_family = "Cyclone", + scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", + scfifo_component.lpm_numwords = 1024, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 16, + scfifo_component.lpm_widthu = 10, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE diff --git a/usrp1/megacells/fifo_1kx16_bb.v b/usrp1/megacells/fifo_1kx16_bb.v new file mode 100755 index 000000000..9d9912bc2 --- /dev/null +++ b/usrp1/megacells/fifo_1kx16_bb.v @@ -0,0 +1,127 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_1kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_1kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + almost_empty, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output almost_empty; + output empty; + output full; + output [15:0] q; + output [9:0] usedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE diff --git a/usrp1/megacells/fifo_1kx16_inst.v b/usrp1/megacells/fifo_1kx16_inst.v new file mode 100755 index 000000000..73662dea3 --- /dev/null +++ b/usrp1/megacells/fifo_1kx16_inst.v @@ -0,0 +1,12 @@ +fifo_1kx16 fifo_1kx16_inst ( + .aclr ( aclr_sig ), + .clock ( clock_sig ), + .data ( data_sig ), + .rdreq ( rdreq_sig ), + .wrreq ( wrreq_sig ), + .almost_empty ( almost_empty_sig ), + .empty ( empty_sig ), + .full ( full_sig ), + .q ( q_sig ), + .usedw ( usedw_sig ) + ); diff --git a/usrp1/megacells/fifo_2k.v b/usrp1/megacells/fifo_2k.v new file mode 100644 index 000000000..5e2a38520 --- /dev/null +++ b/usrp1/megacells/fifo_2k.v @@ -0,0 +1,3343 @@ +// megafunction wizard: %FIFO%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_2k.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + + +//a_gray2bin device_family="Cyclone" WIDTH=11 bin gray +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END + +//synthesis_resources = +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_a_gray2bin_8m4 + ( + bin, + gray) /* synthesis synthesis_clearbox=1 */; + output [10:0] bin; + input [10:0] gray; + + wire xor0; + wire xor1; + wire xor2; + wire xor3; + wire xor4; + wire xor5; + wire xor6; + wire xor7; + wire xor8; + wire xor9; + + assign + bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, + xor0 = (gray[0] ^ xor1), + xor1 = (gray[1] ^ xor2), + xor2 = (gray[2] ^ xor3), + xor3 = (gray[3] ^ xor4), + xor4 = (gray[4] ^ xor5), + xor5 = (gray[5] ^ xor6), + xor6 = (gray[6] ^ xor7), + xor7 = (gray[7] ^ xor8), + xor8 = (gray[8] ^ xor9), + xor9 = (gray[10] ^ gray[9]); +endmodule //fifo_2k_a_gray2bin_8m4 + + +//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_a_graycounter_726 + ( + aclr, + clock, + cnt_en, + q) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clock; + input cnt_en; + output [10:0] q; + + wire [0:0] wire_countera_0cout; + wire [0:0] wire_countera_1cout; + wire [0:0] wire_countera_2cout; + wire [0:0] wire_countera_3cout; + wire [0:0] wire_countera_4cout; + wire [0:0] wire_countera_5cout; + wire [0:0] wire_countera_6cout; + wire [0:0] wire_countera_7cout; + wire [0:0] wire_countera_8cout; + wire [0:0] wire_countera_9cout; + wire [10:0] wire_countera_regout; + wire wire_parity_cout; + wire wire_parity_regout; + wire [10:0] power_modified_counter_values; + wire sclr; + wire updown; + + cyclone_lcell countera_0 + ( + .aclr(aclr), + .cin(wire_parity_cout), + .clk(clock), + .combout(), + .cout(wire_countera_0cout[0:0]), + .dataa(cnt_en), + .datab(wire_countera_regout[0:0]), + .ena(1'b1), + .regout(wire_countera_regout[0:0]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_0.cin_used = "true", + countera_0.lut_mask = "c6a0", + countera_0.operation_mode = "arithmetic", + countera_0.sum_lutc_input = "cin", + countera_0.synch_mode = "on", + countera_0.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_1 + ( + .aclr(aclr), + .cin(wire_countera_0cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_1cout[0:0]), + .dataa(power_modified_counter_values[0]), + .datab(power_modified_counter_values[1]), + .ena(1'b1), + .regout(wire_countera_regout[1:1]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_1.cin_used = "true", + countera_1.lut_mask = "6c50", + countera_1.operation_mode = "arithmetic", + countera_1.sum_lutc_input = "cin", + countera_1.synch_mode = "on", + countera_1.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_2 + ( + .aclr(aclr), + .cin(wire_countera_1cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_2cout[0:0]), + .dataa(power_modified_counter_values[1]), + .datab(power_modified_counter_values[2]), + .ena(1'b1), + .regout(wire_countera_regout[2:2]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_2.cin_used = "true", + countera_2.lut_mask = "6c50", + countera_2.operation_mode = "arithmetic", + countera_2.sum_lutc_input = "cin", + countera_2.synch_mode = "on", + countera_2.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_3 + ( + .aclr(aclr), + .cin(wire_countera_2cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_3cout[0:0]), + .dataa(power_modified_counter_values[2]), + .datab(power_modified_counter_values[3]), + .ena(1'b1), + .regout(wire_countera_regout[3:3]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_3.cin_used = "true", + countera_3.lut_mask = "6c50", + countera_3.operation_mode = "arithmetic", + countera_3.sum_lutc_input = "cin", + countera_3.synch_mode = "on", + countera_3.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_4 + ( + .aclr(aclr), + .cin(wire_countera_3cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_4cout[0:0]), + .dataa(power_modified_counter_values[3]), + .datab(power_modified_counter_values[4]), + .ena(1'b1), + .regout(wire_countera_regout[4:4]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_4.cin_used = "true", + countera_4.lut_mask = "6c50", + countera_4.operation_mode = "arithmetic", + countera_4.sum_lutc_input = "cin", + countera_4.synch_mode = "on", + countera_4.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_5 + ( + .aclr(aclr), + .cin(wire_countera_4cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_5cout[0:0]), + .dataa(power_modified_counter_values[4]), + .datab(power_modified_counter_values[5]), + .ena(1'b1), + .regout(wire_countera_regout[5:5]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_5.cin_used = "true", + countera_5.lut_mask = "6c50", + countera_5.operation_mode = "arithmetic", + countera_5.sum_lutc_input = "cin", + countera_5.synch_mode = "on", + countera_5.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_6 + ( + .aclr(aclr), + .cin(wire_countera_5cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_6cout[0:0]), + .dataa(power_modified_counter_values[5]), + .datab(power_modified_counter_values[6]), + .ena(1'b1), + .regout(wire_countera_regout[6:6]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_6.cin_used = "true", + countera_6.lut_mask = "6c50", + countera_6.operation_mode = "arithmetic", + countera_6.sum_lutc_input = "cin", + countera_6.synch_mode = "on", + countera_6.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_7 + ( + .aclr(aclr), + .cin(wire_countera_6cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_7cout[0:0]), + .dataa(power_modified_counter_values[6]), + .datab(power_modified_counter_values[7]), + .ena(1'b1), + .regout(wire_countera_regout[7:7]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_7.cin_used = "true", + countera_7.lut_mask = "6c50", + countera_7.operation_mode = "arithmetic", + countera_7.sum_lutc_input = "cin", + countera_7.synch_mode = "on", + countera_7.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_8 + ( + .aclr(aclr), + .cin(wire_countera_7cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_8cout[0:0]), + .dataa(power_modified_counter_values[7]), + .datab(power_modified_counter_values[8]), + .ena(1'b1), + .regout(wire_countera_regout[8:8]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_8.cin_used = "true", + countera_8.lut_mask = "6c50", + countera_8.operation_mode = "arithmetic", + countera_8.sum_lutc_input = "cin", + countera_8.synch_mode = "on", + countera_8.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_9 + ( + .aclr(aclr), + .cin(wire_countera_8cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_9cout[0:0]), + .dataa(power_modified_counter_values[8]), + .datab(power_modified_counter_values[9]), + .ena(1'b1), + .regout(wire_countera_regout[9:9]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_9.cin_used = "true", + countera_9.lut_mask = "6c50", + countera_9.operation_mode = "arithmetic", + countera_9.sum_lutc_input = "cin", + countera_9.synch_mode = "on", + countera_9.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_10 + ( + .aclr(aclr), + .cin(wire_countera_9cout[0:0]), + .clk(clock), + .combout(), + .cout(), + .dataa(power_modified_counter_values[10]), + .ena(1'b1), + .regout(wire_countera_regout[10:10]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datab(1'b1), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_10.cin_used = "true", + countera_10.lut_mask = "5a5a", + countera_10.operation_mode = "normal", + countera_10.sum_lutc_input = "cin", + countera_10.synch_mode = "on", + countera_10.lpm_type = "cyclone_lcell"; + cyclone_lcell parity + ( + .aclr(aclr), + .cin(updown), + .clk(clock), + .combout(), + .cout(wire_parity_cout), + .dataa(cnt_en), + .datab(wire_parity_regout), + .ena(1'b1), + .regout(wire_parity_regout), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + parity.cin_used = "true", + parity.lut_mask = "6682", + parity.operation_mode = "arithmetic", + parity.synch_mode = "on", + parity.lpm_type = "cyclone_lcell"; + assign + power_modified_counter_values = {wire_countera_regout[10:0]}, + q = power_modified_counter_values, + sclr = 1'b0, + updown = 1'b1; +endmodule //fifo_2k_a_graycounter_726 + + +//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_a_graycounter_2r6 + ( + aclr, + clock, + cnt_en, + q) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clock; + input cnt_en; + output [10:0] q; + + wire [0:0] wire_countera_0cout; + wire [0:0] wire_countera_1cout; + wire [0:0] wire_countera_2cout; + wire [0:0] wire_countera_3cout; + wire [0:0] wire_countera_4cout; + wire [0:0] wire_countera_5cout; + wire [0:0] wire_countera_6cout; + wire [0:0] wire_countera_7cout; + wire [0:0] wire_countera_8cout; + wire [0:0] wire_countera_9cout; + wire [10:0] wire_countera_regout; + wire wire_parity_cout; + wire wire_parity_regout; + wire [10:0] power_modified_counter_values; + wire sclr; + wire updown; + + cyclone_lcell countera_0 + ( + .aclr(aclr), + .cin(wire_parity_cout), + .clk(clock), + .combout(), + .cout(wire_countera_0cout[0:0]), + .dataa(cnt_en), + .datab(wire_countera_regout[0:0]), + .ena(1'b1), + .regout(wire_countera_regout[0:0]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_0.cin_used = "true", + countera_0.lut_mask = "c6a0", + countera_0.operation_mode = "arithmetic", + countera_0.sum_lutc_input = "cin", + countera_0.synch_mode = "on", + countera_0.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_1 + ( + .aclr(aclr), + .cin(wire_countera_0cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_1cout[0:0]), + .dataa(power_modified_counter_values[0]), + .datab(power_modified_counter_values[1]), + .ena(1'b1), + .regout(wire_countera_regout[1:1]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_1.cin_used = "true", + countera_1.lut_mask = "6c50", + countera_1.operation_mode = "arithmetic", + countera_1.sum_lutc_input = "cin", + countera_1.synch_mode = "on", + countera_1.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_2 + ( + .aclr(aclr), + .cin(wire_countera_1cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_2cout[0:0]), + .dataa(power_modified_counter_values[1]), + .datab(power_modified_counter_values[2]), + .ena(1'b1), + .regout(wire_countera_regout[2:2]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_2.cin_used = "true", + countera_2.lut_mask = "6c50", + countera_2.operation_mode = "arithmetic", + countera_2.sum_lutc_input = "cin", + countera_2.synch_mode = "on", + countera_2.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_3 + ( + .aclr(aclr), + .cin(wire_countera_2cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_3cout[0:0]), + .dataa(power_modified_counter_values[2]), + .datab(power_modified_counter_values[3]), + .ena(1'b1), + .regout(wire_countera_regout[3:3]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_3.cin_used = "true", + countera_3.lut_mask = "6c50", + countera_3.operation_mode = "arithmetic", + countera_3.sum_lutc_input = "cin", + countera_3.synch_mode = "on", + countera_3.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_4 + ( + .aclr(aclr), + .cin(wire_countera_3cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_4cout[0:0]), + .dataa(power_modified_counter_values[3]), + .datab(power_modified_counter_values[4]), + .ena(1'b1), + .regout(wire_countera_regout[4:4]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_4.cin_used = "true", + countera_4.lut_mask = "6c50", + countera_4.operation_mode = "arithmetic", + countera_4.sum_lutc_input = "cin", + countera_4.synch_mode = "on", + countera_4.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_5 + ( + .aclr(aclr), + .cin(wire_countera_4cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_5cout[0:0]), + .dataa(power_modified_counter_values[4]), + .datab(power_modified_counter_values[5]), + .ena(1'b1), + .regout(wire_countera_regout[5:5]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_5.cin_used = "true", + countera_5.lut_mask = "6c50", + countera_5.operation_mode = "arithmetic", + countera_5.sum_lutc_input = "cin", + countera_5.synch_mode = "on", + countera_5.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_6 + ( + .aclr(aclr), + .cin(wire_countera_5cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_6cout[0:0]), + .dataa(power_modified_counter_values[5]), + .datab(power_modified_counter_values[6]), + .ena(1'b1), + .regout(wire_countera_regout[6:6]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_6.cin_used = "true", + countera_6.lut_mask = "6c50", + countera_6.operation_mode = "arithmetic", + countera_6.sum_lutc_input = "cin", + countera_6.synch_mode = "on", + countera_6.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_7 + ( + .aclr(aclr), + .cin(wire_countera_6cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_7cout[0:0]), + .dataa(power_modified_counter_values[6]), + .datab(power_modified_counter_values[7]), + .ena(1'b1), + .regout(wire_countera_regout[7:7]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_7.cin_used = "true", + countera_7.lut_mask = "6c50", + countera_7.operation_mode = "arithmetic", + countera_7.sum_lutc_input = "cin", + countera_7.synch_mode = "on", + countera_7.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_8 + ( + .aclr(aclr), + .cin(wire_countera_7cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_8cout[0:0]), + .dataa(power_modified_counter_values[7]), + .datab(power_modified_counter_values[8]), + .ena(1'b1), + .regout(wire_countera_regout[8:8]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_8.cin_used = "true", + countera_8.lut_mask = "6c50", + countera_8.operation_mode = "arithmetic", + countera_8.sum_lutc_input = "cin", + countera_8.synch_mode = "on", + countera_8.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_9 + ( + .aclr(aclr), + .cin(wire_countera_8cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_9cout[0:0]), + .dataa(power_modified_counter_values[8]), + .datab(power_modified_counter_values[9]), + .ena(1'b1), + .regout(wire_countera_regout[9:9]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_9.cin_used = "true", + countera_9.lut_mask = "6c50", + countera_9.operation_mode = "arithmetic", + countera_9.sum_lutc_input = "cin", + countera_9.synch_mode = "on", + countera_9.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_10 + ( + .aclr(aclr), + .cin(wire_countera_9cout[0:0]), + .clk(clock), + .combout(), + .cout(), + .dataa(power_modified_counter_values[10]), + .ena(1'b1), + .regout(wire_countera_regout[10:10]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datab(1'b1), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_10.cin_used = "true", + countera_10.lut_mask = "5a5a", + countera_10.operation_mode = "normal", + countera_10.sum_lutc_input = "cin", + countera_10.synch_mode = "on", + countera_10.lpm_type = "cyclone_lcell"; + cyclone_lcell parity + ( + .aclr(aclr), + .cin(updown), + .clk(clock), + .combout(), + .cout(wire_parity_cout), + .dataa(cnt_en), + .datab((~ wire_parity_regout)), + .ena(1'b1), + .regout(wire_parity_regout), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + parity.cin_used = "true", + parity.lut_mask = "9982", + parity.operation_mode = "arithmetic", + parity.synch_mode = "on", + parity.lpm_type = "cyclone_lcell"; + assign + power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])}, + q = power_modified_counter_values, + sclr = 1'b0, + updown = 1'b1; +endmodule //fifo_2k_a_graycounter_2r6 + + +//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a +//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = M4K 8 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_altsyncram_6pl + ( + address_a, + address_b, + clock0, + clock1, + clocken1, + data_a, + q_b, + wren_a) /* synthesis synthesis_clearbox=1 */; + input [10:0] address_a; + input [10:0] address_b; + input clock0; + input clock1; + input clocken1; + input [15:0] data_a; + output [15:0] q_b; + input wren_a; + + wire [0:0] wire_ram_block3a_0portbdataout; + wire [0:0] wire_ram_block3a_1portbdataout; + wire [0:0] wire_ram_block3a_2portbdataout; + wire [0:0] wire_ram_block3a_3portbdataout; + wire [0:0] wire_ram_block3a_4portbdataout; + wire [0:0] wire_ram_block3a_5portbdataout; + wire [0:0] wire_ram_block3a_6portbdataout; + wire [0:0] wire_ram_block3a_7portbdataout; + wire [0:0] wire_ram_block3a_8portbdataout; + wire [0:0] wire_ram_block3a_9portbdataout; + wire [0:0] wire_ram_block3a_10portbdataout; + wire [0:0] wire_ram_block3a_11portbdataout; + wire [0:0] wire_ram_block3a_12portbdataout; + wire [0:0] wire_ram_block3a_13portbdataout; + wire [0:0] wire_ram_block3a_14portbdataout; + wire [0:0] wire_ram_block3a_15portbdataout; + wire [10:0] address_a_wire; + wire [10:0] address_b_wire; + + cyclone_ram_block ram_block3a_0 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[0]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_0portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_0.connectivity_checking = "OFF", + ram_block3a_0.logical_ram_name = "ALTSYNCRAM", + ram_block3a_0.mixed_port_feed_through_mode = "dont_care", + ram_block3a_0.operation_mode = "dual_port", + ram_block3a_0.port_a_address_width = 11, + ram_block3a_0.port_a_data_width = 1, + ram_block3a_0.port_a_first_address = 0, + ram_block3a_0.port_a_first_bit_number = 0, + ram_block3a_0.port_a_last_address = 2047, + ram_block3a_0.port_a_logical_ram_depth = 2048, + ram_block3a_0.port_a_logical_ram_width = 16, + ram_block3a_0.port_b_address_clear = "none", + ram_block3a_0.port_b_address_clock = "clock1", + ram_block3a_0.port_b_address_width = 11, + ram_block3a_0.port_b_data_out_clear = "none", + ram_block3a_0.port_b_data_out_clock = "none", + ram_block3a_0.port_b_data_width = 1, + ram_block3a_0.port_b_first_address = 0, + ram_block3a_0.port_b_first_bit_number = 0, + ram_block3a_0.port_b_last_address = 2047, + ram_block3a_0.port_b_logical_ram_depth = 2048, + ram_block3a_0.port_b_logical_ram_width = 16, + ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_0.ram_block_type = "auto", + ram_block3a_0.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_1 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[1]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_1portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_1.connectivity_checking = "OFF", + ram_block3a_1.logical_ram_name = "ALTSYNCRAM", + ram_block3a_1.mixed_port_feed_through_mode = "dont_care", + ram_block3a_1.operation_mode = "dual_port", + ram_block3a_1.port_a_address_width = 11, + ram_block3a_1.port_a_data_width = 1, + ram_block3a_1.port_a_first_address = 0, + ram_block3a_1.port_a_first_bit_number = 1, + ram_block3a_1.port_a_last_address = 2047, + ram_block3a_1.port_a_logical_ram_depth = 2048, + ram_block3a_1.port_a_logical_ram_width = 16, + ram_block3a_1.port_b_address_clear = "none", + ram_block3a_1.port_b_address_clock = "clock1", + ram_block3a_1.port_b_address_width = 11, + ram_block3a_1.port_b_data_out_clear = "none", + ram_block3a_1.port_b_data_out_clock = "none", + ram_block3a_1.port_b_data_width = 1, + ram_block3a_1.port_b_first_address = 0, + ram_block3a_1.port_b_first_bit_number = 1, + ram_block3a_1.port_b_last_address = 2047, + ram_block3a_1.port_b_logical_ram_depth = 2048, + ram_block3a_1.port_b_logical_ram_width = 16, + ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_1.ram_block_type = "auto", + ram_block3a_1.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_2 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[2]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_2portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_2.connectivity_checking = "OFF", + ram_block3a_2.logical_ram_name = "ALTSYNCRAM", + ram_block3a_2.mixed_port_feed_through_mode = "dont_care", + ram_block3a_2.operation_mode = "dual_port", + ram_block3a_2.port_a_address_width = 11, + ram_block3a_2.port_a_data_width = 1, + ram_block3a_2.port_a_first_address = 0, + ram_block3a_2.port_a_first_bit_number = 2, + ram_block3a_2.port_a_last_address = 2047, + ram_block3a_2.port_a_logical_ram_depth = 2048, + ram_block3a_2.port_a_logical_ram_width = 16, + ram_block3a_2.port_b_address_clear = "none", + ram_block3a_2.port_b_address_clock = "clock1", + ram_block3a_2.port_b_address_width = 11, + ram_block3a_2.port_b_data_out_clear = "none", + ram_block3a_2.port_b_data_out_clock = "none", + ram_block3a_2.port_b_data_width = 1, + ram_block3a_2.port_b_first_address = 0, + ram_block3a_2.port_b_first_bit_number = 2, + ram_block3a_2.port_b_last_address = 2047, + ram_block3a_2.port_b_logical_ram_depth = 2048, + ram_block3a_2.port_b_logical_ram_width = 16, + ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_2.ram_block_type = "auto", + ram_block3a_2.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_3 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[3]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_3portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_3.connectivity_checking = "OFF", + ram_block3a_3.logical_ram_name = "ALTSYNCRAM", + ram_block3a_3.mixed_port_feed_through_mode = "dont_care", + ram_block3a_3.operation_mode = "dual_port", + ram_block3a_3.port_a_address_width = 11, + ram_block3a_3.port_a_data_width = 1, + ram_block3a_3.port_a_first_address = 0, + ram_block3a_3.port_a_first_bit_number = 3, + ram_block3a_3.port_a_last_address = 2047, + ram_block3a_3.port_a_logical_ram_depth = 2048, + ram_block3a_3.port_a_logical_ram_width = 16, + ram_block3a_3.port_b_address_clear = "none", + ram_block3a_3.port_b_address_clock = "clock1", + ram_block3a_3.port_b_address_width = 11, + ram_block3a_3.port_b_data_out_clear = "none", + ram_block3a_3.port_b_data_out_clock = "none", + ram_block3a_3.port_b_data_width = 1, + ram_block3a_3.port_b_first_address = 0, + ram_block3a_3.port_b_first_bit_number = 3, + ram_block3a_3.port_b_last_address = 2047, + ram_block3a_3.port_b_logical_ram_depth = 2048, + ram_block3a_3.port_b_logical_ram_width = 16, + ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_3.ram_block_type = "auto", + ram_block3a_3.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_4 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[4]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_4portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_4.connectivity_checking = "OFF", + ram_block3a_4.logical_ram_name = "ALTSYNCRAM", + ram_block3a_4.mixed_port_feed_through_mode = "dont_care", + ram_block3a_4.operation_mode = "dual_port", + ram_block3a_4.port_a_address_width = 11, + ram_block3a_4.port_a_data_width = 1, + ram_block3a_4.port_a_first_address = 0, + ram_block3a_4.port_a_first_bit_number = 4, + ram_block3a_4.port_a_last_address = 2047, + ram_block3a_4.port_a_logical_ram_depth = 2048, + ram_block3a_4.port_a_logical_ram_width = 16, + ram_block3a_4.port_b_address_clear = "none", + ram_block3a_4.port_b_address_clock = "clock1", + ram_block3a_4.port_b_address_width = 11, + ram_block3a_4.port_b_data_out_clear = "none", + ram_block3a_4.port_b_data_out_clock = "none", + ram_block3a_4.port_b_data_width = 1, + ram_block3a_4.port_b_first_address = 0, + ram_block3a_4.port_b_first_bit_number = 4, + ram_block3a_4.port_b_last_address = 2047, + ram_block3a_4.port_b_logical_ram_depth = 2048, + ram_block3a_4.port_b_logical_ram_width = 16, + ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_4.ram_block_type = "auto", + ram_block3a_4.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_5 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[5]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_5portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_5.connectivity_checking = "OFF", + ram_block3a_5.logical_ram_name = "ALTSYNCRAM", + ram_block3a_5.mixed_port_feed_through_mode = "dont_care", + ram_block3a_5.operation_mode = "dual_port", + ram_block3a_5.port_a_address_width = 11, + ram_block3a_5.port_a_data_width = 1, + ram_block3a_5.port_a_first_address = 0, + ram_block3a_5.port_a_first_bit_number = 5, + ram_block3a_5.port_a_last_address = 2047, + ram_block3a_5.port_a_logical_ram_depth = 2048, + ram_block3a_5.port_a_logical_ram_width = 16, + ram_block3a_5.port_b_address_clear = "none", + ram_block3a_5.port_b_address_clock = "clock1", + ram_block3a_5.port_b_address_width = 11, + ram_block3a_5.port_b_data_out_clear = "none", + ram_block3a_5.port_b_data_out_clock = "none", + ram_block3a_5.port_b_data_width = 1, + ram_block3a_5.port_b_first_address = 0, + ram_block3a_5.port_b_first_bit_number = 5, + ram_block3a_5.port_b_last_address = 2047, + ram_block3a_5.port_b_logical_ram_depth = 2048, + ram_block3a_5.port_b_logical_ram_width = 16, + ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_5.ram_block_type = "auto", + ram_block3a_5.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_6 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[6]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_6portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_6.connectivity_checking = "OFF", + ram_block3a_6.logical_ram_name = "ALTSYNCRAM", + ram_block3a_6.mixed_port_feed_through_mode = "dont_care", + ram_block3a_6.operation_mode = "dual_port", + ram_block3a_6.port_a_address_width = 11, + ram_block3a_6.port_a_data_width = 1, + ram_block3a_6.port_a_first_address = 0, + ram_block3a_6.port_a_first_bit_number = 6, + ram_block3a_6.port_a_last_address = 2047, + ram_block3a_6.port_a_logical_ram_depth = 2048, + ram_block3a_6.port_a_logical_ram_width = 16, + ram_block3a_6.port_b_address_clear = "none", + ram_block3a_6.port_b_address_clock = "clock1", + ram_block3a_6.port_b_address_width = 11, + ram_block3a_6.port_b_data_out_clear = "none", + ram_block3a_6.port_b_data_out_clock = "none", + ram_block3a_6.port_b_data_width = 1, + ram_block3a_6.port_b_first_address = 0, + ram_block3a_6.port_b_first_bit_number = 6, + ram_block3a_6.port_b_last_address = 2047, + ram_block3a_6.port_b_logical_ram_depth = 2048, + ram_block3a_6.port_b_logical_ram_width = 16, + ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_6.ram_block_type = "auto", + ram_block3a_6.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_7 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[7]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_7portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_7.connectivity_checking = "OFF", + ram_block3a_7.logical_ram_name = "ALTSYNCRAM", + ram_block3a_7.mixed_port_feed_through_mode = "dont_care", + ram_block3a_7.operation_mode = "dual_port", + ram_block3a_7.port_a_address_width = 11, + ram_block3a_7.port_a_data_width = 1, + ram_block3a_7.port_a_first_address = 0, + ram_block3a_7.port_a_first_bit_number = 7, + ram_block3a_7.port_a_last_address = 2047, + ram_block3a_7.port_a_logical_ram_depth = 2048, + ram_block3a_7.port_a_logical_ram_width = 16, + ram_block3a_7.port_b_address_clear = "none", + ram_block3a_7.port_b_address_clock = "clock1", + ram_block3a_7.port_b_address_width = 11, + ram_block3a_7.port_b_data_out_clear = "none", + ram_block3a_7.port_b_data_out_clock = "none", + ram_block3a_7.port_b_data_width = 1, + ram_block3a_7.port_b_first_address = 0, + ram_block3a_7.port_b_first_bit_number = 7, + ram_block3a_7.port_b_last_address = 2047, + ram_block3a_7.port_b_logical_ram_depth = 2048, + ram_block3a_7.port_b_logical_ram_width = 16, + ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_7.ram_block_type = "auto", + ram_block3a_7.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_8 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[8]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_8portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_8.connectivity_checking = "OFF", + ram_block3a_8.logical_ram_name = "ALTSYNCRAM", + ram_block3a_8.mixed_port_feed_through_mode = "dont_care", + ram_block3a_8.operation_mode = "dual_port", + ram_block3a_8.port_a_address_width = 11, + ram_block3a_8.port_a_data_width = 1, + ram_block3a_8.port_a_first_address = 0, + ram_block3a_8.port_a_first_bit_number = 8, + ram_block3a_8.port_a_last_address = 2047, + ram_block3a_8.port_a_logical_ram_depth = 2048, + ram_block3a_8.port_a_logical_ram_width = 16, + ram_block3a_8.port_b_address_clear = "none", + ram_block3a_8.port_b_address_clock = "clock1", + ram_block3a_8.port_b_address_width = 11, + ram_block3a_8.port_b_data_out_clear = "none", + ram_block3a_8.port_b_data_out_clock = "none", + ram_block3a_8.port_b_data_width = 1, + ram_block3a_8.port_b_first_address = 0, + ram_block3a_8.port_b_first_bit_number = 8, + ram_block3a_8.port_b_last_address = 2047, + ram_block3a_8.port_b_logical_ram_depth = 2048, + ram_block3a_8.port_b_logical_ram_width = 16, + ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_8.ram_block_type = "auto", + ram_block3a_8.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_9 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[9]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_9portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_9.connectivity_checking = "OFF", + ram_block3a_9.logical_ram_name = "ALTSYNCRAM", + ram_block3a_9.mixed_port_feed_through_mode = "dont_care", + ram_block3a_9.operation_mode = "dual_port", + ram_block3a_9.port_a_address_width = 11, + ram_block3a_9.port_a_data_width = 1, + ram_block3a_9.port_a_first_address = 0, + ram_block3a_9.port_a_first_bit_number = 9, + ram_block3a_9.port_a_last_address = 2047, + ram_block3a_9.port_a_logical_ram_depth = 2048, + ram_block3a_9.port_a_logical_ram_width = 16, + ram_block3a_9.port_b_address_clear = "none", + ram_block3a_9.port_b_address_clock = "clock1", + ram_block3a_9.port_b_address_width = 11, + ram_block3a_9.port_b_data_out_clear = "none", + ram_block3a_9.port_b_data_out_clock = "none", + ram_block3a_9.port_b_data_width = 1, + ram_block3a_9.port_b_first_address = 0, + ram_block3a_9.port_b_first_bit_number = 9, + ram_block3a_9.port_b_last_address = 2047, + ram_block3a_9.port_b_logical_ram_depth = 2048, + ram_block3a_9.port_b_logical_ram_width = 16, + ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_9.ram_block_type = "auto", + ram_block3a_9.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_10 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[10]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_10portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_10.connectivity_checking = "OFF", + ram_block3a_10.logical_ram_name = "ALTSYNCRAM", + ram_block3a_10.mixed_port_feed_through_mode = "dont_care", + ram_block3a_10.operation_mode = "dual_port", + ram_block3a_10.port_a_address_width = 11, + ram_block3a_10.port_a_data_width = 1, + ram_block3a_10.port_a_first_address = 0, + ram_block3a_10.port_a_first_bit_number = 10, + ram_block3a_10.port_a_last_address = 2047, + ram_block3a_10.port_a_logical_ram_depth = 2048, + ram_block3a_10.port_a_logical_ram_width = 16, + ram_block3a_10.port_b_address_clear = "none", + ram_block3a_10.port_b_address_clock = "clock1", + ram_block3a_10.port_b_address_width = 11, + ram_block3a_10.port_b_data_out_clear = "none", + ram_block3a_10.port_b_data_out_clock = "none", + ram_block3a_10.port_b_data_width = 1, + ram_block3a_10.port_b_first_address = 0, + ram_block3a_10.port_b_first_bit_number = 10, + ram_block3a_10.port_b_last_address = 2047, + ram_block3a_10.port_b_logical_ram_depth = 2048, + ram_block3a_10.port_b_logical_ram_width = 16, + ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_10.ram_block_type = "auto", + ram_block3a_10.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_11 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[11]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_11portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_11.connectivity_checking = "OFF", + ram_block3a_11.logical_ram_name = "ALTSYNCRAM", + ram_block3a_11.mixed_port_feed_through_mode = "dont_care", + ram_block3a_11.operation_mode = "dual_port", + ram_block3a_11.port_a_address_width = 11, + ram_block3a_11.port_a_data_width = 1, + ram_block3a_11.port_a_first_address = 0, + ram_block3a_11.port_a_first_bit_number = 11, + ram_block3a_11.port_a_last_address = 2047, + ram_block3a_11.port_a_logical_ram_depth = 2048, + ram_block3a_11.port_a_logical_ram_width = 16, + ram_block3a_11.port_b_address_clear = "none", + ram_block3a_11.port_b_address_clock = "clock1", + ram_block3a_11.port_b_address_width = 11, + ram_block3a_11.port_b_data_out_clear = "none", + ram_block3a_11.port_b_data_out_clock = "none", + ram_block3a_11.port_b_data_width = 1, + ram_block3a_11.port_b_first_address = 0, + ram_block3a_11.port_b_first_bit_number = 11, + ram_block3a_11.port_b_last_address = 2047, + ram_block3a_11.port_b_logical_ram_depth = 2048, + ram_block3a_11.port_b_logical_ram_width = 16, + ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_11.ram_block_type = "auto", + ram_block3a_11.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_12 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[12]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_12portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_12.connectivity_checking = "OFF", + ram_block3a_12.logical_ram_name = "ALTSYNCRAM", + ram_block3a_12.mixed_port_feed_through_mode = "dont_care", + ram_block3a_12.operation_mode = "dual_port", + ram_block3a_12.port_a_address_width = 11, + ram_block3a_12.port_a_data_width = 1, + ram_block3a_12.port_a_first_address = 0, + ram_block3a_12.port_a_first_bit_number = 12, + ram_block3a_12.port_a_last_address = 2047, + ram_block3a_12.port_a_logical_ram_depth = 2048, + ram_block3a_12.port_a_logical_ram_width = 16, + ram_block3a_12.port_b_address_clear = "none", + ram_block3a_12.port_b_address_clock = "clock1", + ram_block3a_12.port_b_address_width = 11, + ram_block3a_12.port_b_data_out_clear = "none", + ram_block3a_12.port_b_data_out_clock = "none", + ram_block3a_12.port_b_data_width = 1, + ram_block3a_12.port_b_first_address = 0, + ram_block3a_12.port_b_first_bit_number = 12, + ram_block3a_12.port_b_last_address = 2047, + ram_block3a_12.port_b_logical_ram_depth = 2048, + ram_block3a_12.port_b_logical_ram_width = 16, + ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_12.ram_block_type = "auto", + ram_block3a_12.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_13 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[13]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_13portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_13.connectivity_checking = "OFF", + ram_block3a_13.logical_ram_name = "ALTSYNCRAM", + ram_block3a_13.mixed_port_feed_through_mode = "dont_care", + ram_block3a_13.operation_mode = "dual_port", + ram_block3a_13.port_a_address_width = 11, + ram_block3a_13.port_a_data_width = 1, + ram_block3a_13.port_a_first_address = 0, + ram_block3a_13.port_a_first_bit_number = 13, + ram_block3a_13.port_a_last_address = 2047, + ram_block3a_13.port_a_logical_ram_depth = 2048, + ram_block3a_13.port_a_logical_ram_width = 16, + ram_block3a_13.port_b_address_clear = "none", + ram_block3a_13.port_b_address_clock = "clock1", + ram_block3a_13.port_b_address_width = 11, + ram_block3a_13.port_b_data_out_clear = "none", + ram_block3a_13.port_b_data_out_clock = "none", + ram_block3a_13.port_b_data_width = 1, + ram_block3a_13.port_b_first_address = 0, + ram_block3a_13.port_b_first_bit_number = 13, + ram_block3a_13.port_b_last_address = 2047, + ram_block3a_13.port_b_logical_ram_depth = 2048, + ram_block3a_13.port_b_logical_ram_width = 16, + ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_13.ram_block_type = "auto", + ram_block3a_13.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_14 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[14]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_14portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_14.connectivity_checking = "OFF", + ram_block3a_14.logical_ram_name = "ALTSYNCRAM", + ram_block3a_14.mixed_port_feed_through_mode = "dont_care", + ram_block3a_14.operation_mode = "dual_port", + ram_block3a_14.port_a_address_width = 11, + ram_block3a_14.port_a_data_width = 1, + ram_block3a_14.port_a_first_address = 0, + ram_block3a_14.port_a_first_bit_number = 14, + ram_block3a_14.port_a_last_address = 2047, + ram_block3a_14.port_a_logical_ram_depth = 2048, + ram_block3a_14.port_a_logical_ram_width = 16, + ram_block3a_14.port_b_address_clear = "none", + ram_block3a_14.port_b_address_clock = "clock1", + ram_block3a_14.port_b_address_width = 11, + ram_block3a_14.port_b_data_out_clear = "none", + ram_block3a_14.port_b_data_out_clock = "none", + ram_block3a_14.port_b_data_width = 1, + ram_block3a_14.port_b_first_address = 0, + ram_block3a_14.port_b_first_bit_number = 14, + ram_block3a_14.port_b_last_address = 2047, + ram_block3a_14.port_b_logical_ram_depth = 2048, + ram_block3a_14.port_b_logical_ram_width = 16, + ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_14.ram_block_type = "auto", + ram_block3a_14.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_15 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[10:0]}), + .portadatain({data_a[15]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[10:0]}), + .portbdataout(wire_ram_block3a_15portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_15.connectivity_checking = "OFF", + ram_block3a_15.logical_ram_name = "ALTSYNCRAM", + ram_block3a_15.mixed_port_feed_through_mode = "dont_care", + ram_block3a_15.operation_mode = "dual_port", + ram_block3a_15.port_a_address_width = 11, + ram_block3a_15.port_a_data_width = 1, + ram_block3a_15.port_a_first_address = 0, + ram_block3a_15.port_a_first_bit_number = 15, + ram_block3a_15.port_a_last_address = 2047, + ram_block3a_15.port_a_logical_ram_depth = 2048, + ram_block3a_15.port_a_logical_ram_width = 16, + ram_block3a_15.port_b_address_clear = "none", + ram_block3a_15.port_b_address_clock = "clock1", + ram_block3a_15.port_b_address_width = 11, + ram_block3a_15.port_b_data_out_clear = "none", + ram_block3a_15.port_b_data_out_clock = "none", + ram_block3a_15.port_b_data_width = 1, + ram_block3a_15.port_b_first_address = 0, + ram_block3a_15.port_b_first_bit_number = 15, + ram_block3a_15.port_b_last_address = 2047, + ram_block3a_15.port_b_logical_ram_depth = 2048, + ram_block3a_15.port_b_logical_ram_width = 16, + ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_15.ram_block_type = "auto", + ram_block3a_15.lpm_type = "cyclone_ram_block"; + assign + address_a_wire = address_a, + address_b_wire = address_b, + q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; +endmodule //fifo_2k_altsyncram_6pl + + +//dffpipe DELAY=1 WIDTH=11 clock clrn d q +//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = lut 11 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_dffpipe_ab3 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; + input clock; + input clrn; + input [10:0] d; + output [10:0] q; + + wire [10:0] wire_dffe4a_D; + reg [10:0] dffe4a; + wire ena; + wire prn; + wire sclr; + + // synopsys translate_off + initial + dffe4a[0:0] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[0:0] <= 1'b1; + else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; + else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; + // synopsys translate_off + initial + dffe4a[1:1] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[1:1] <= 1'b1; + else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; + else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; + // synopsys translate_off + initial + dffe4a[2:2] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[2:2] <= 1'b1; + else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; + else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; + // synopsys translate_off + initial + dffe4a[3:3] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[3:3] <= 1'b1; + else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; + else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; + // synopsys translate_off + initial + dffe4a[4:4] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[4:4] <= 1'b1; + else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; + else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; + // synopsys translate_off + initial + dffe4a[5:5] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[5:5] <= 1'b1; + else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; + else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; + // synopsys translate_off + initial + dffe4a[6:6] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[6:6] <= 1'b1; + else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; + else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; + // synopsys translate_off + initial + dffe4a[7:7] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[7:7] <= 1'b1; + else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; + else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; + // synopsys translate_off + initial + dffe4a[8:8] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[8:8] <= 1'b1; + else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; + else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; + // synopsys translate_off + initial + dffe4a[9:9] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[9:9] <= 1'b1; + else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; + else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; + // synopsys translate_off + initial + dffe4a[10:10] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[10:10] <= 1'b1; + else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; + else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; + assign + wire_dffe4a_D = (d & {11{(~ sclr)}}); + assign + ena = 1'b1, + prn = 1'b1, + q = dffe4a, + sclr = 1'b0; +endmodule //fifo_2k_dffpipe_ab3 + + +//dffpipe WIDTH=11 clock clrn d q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + + +//dffpipe WIDTH=11 clock clrn d q +//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = lut 11 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_dffpipe_dm2 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; + input clock; + input clrn; + input [10:0] d; + output [10:0] q; + + wire [10:0] wire_dffe6a_D; + reg [10:0] dffe6a; + wire ena; + wire prn; + wire sclr; + + // synopsys translate_off + initial + dffe6a[0:0] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[0:0] <= 1'b1; + else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; + else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; + // synopsys translate_off + initial + dffe6a[1:1] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[1:1] <= 1'b1; + else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; + else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; + // synopsys translate_off + initial + dffe6a[2:2] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[2:2] <= 1'b1; + else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; + else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; + // synopsys translate_off + initial + dffe6a[3:3] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[3:3] <= 1'b1; + else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; + else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; + // synopsys translate_off + initial + dffe6a[4:4] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[4:4] <= 1'b1; + else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; + else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; + // synopsys translate_off + initial + dffe6a[5:5] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[5:5] <= 1'b1; + else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; + else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; + // synopsys translate_off + initial + dffe6a[6:6] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[6:6] <= 1'b1; + else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; + else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; + // synopsys translate_off + initial + dffe6a[7:7] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[7:7] <= 1'b1; + else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; + else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; + // synopsys translate_off + initial + dffe6a[8:8] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[8:8] <= 1'b1; + else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; + else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; + // synopsys translate_off + initial + dffe6a[9:9] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[9:9] <= 1'b1; + else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; + else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; + // synopsys translate_off + initial + dffe6a[10:10] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[10:10] <= 1'b1; + else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; + else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; + assign + wire_dffe6a_D = (d & {11{(~ sclr)}}); + assign + ena = 1'b1, + prn = 1'b1, + q = dffe6a, + sclr = 1'b0; +endmodule //fifo_2k_dffpipe_dm2 + +//synthesis_resources = lut 11 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_alt_synch_pipe_dm2 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; + input clock; + input clrn; + input [10:0] d; + output [10:0] q; + + wire [10:0] wire_dffpipe5_q; + + fifo_2k_dffpipe_dm2 dffpipe5 + ( + .clock(clock), + .clrn(clrn), + .d(d), + .q(wire_dffpipe5_q)); + assign + q = wire_dffpipe5_q; +endmodule //fifo_2k_alt_synch_pipe_dm2 + + +//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 11 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_add_sub_a18 + ( + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input [10:0] dataa; + input [10:0] datab; + output [10:0] result; + + wire [10:0] wire_add_sub_cella_combout; + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [0:0] wire_add_sub_cella_7cout; + wire [0:0] wire_add_sub_cella_8cout; + wire [0:0] wire_add_sub_cella_9cout; + wire [10:0] wire_add_sub_cella_dataa; + wire [10:0] wire_add_sub_cella_datab; + + cyclone_lcell add_sub_cella_0 + ( + .cin(1'b1), + .combout(wire_add_sub_cella_combout[0:0]), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "69b2", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_1 + ( + .cin(wire_add_sub_cella_0cout[0:0]), + .combout(wire_add_sub_cella_combout[1:1]), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "69b2", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_2 + ( + .cin(wire_add_sub_cella_1cout[0:0]), + .combout(wire_add_sub_cella_combout[2:2]), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "69b2", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_3 + ( + .cin(wire_add_sub_cella_2cout[0:0]), + .combout(wire_add_sub_cella_combout[3:3]), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "69b2", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_4 + ( + .cin(wire_add_sub_cella_3cout[0:0]), + .combout(wire_add_sub_cella_combout[4:4]), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "69b2", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_5 + ( + .cin(wire_add_sub_cella_4cout[0:0]), + .combout(wire_add_sub_cella_combout[5:5]), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "69b2", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_6 + ( + .cin(wire_add_sub_cella_5cout[0:0]), + .combout(wire_add_sub_cella_combout[6:6]), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "69b2", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_7 + ( + .cin(wire_add_sub_cella_6cout[0:0]), + .combout(wire_add_sub_cella_combout[7:7]), + .cout(wire_add_sub_cella_7cout[0:0]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "69b2", + add_sub_cella_7.operation_mode = "arithmetic", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_8 + ( + .cin(wire_add_sub_cella_7cout[0:0]), + .combout(wire_add_sub_cella_combout[8:8]), + .cout(wire_add_sub_cella_8cout[0:0]), + .dataa(wire_add_sub_cella_dataa[8:8]), + .datab(wire_add_sub_cella_datab[8:8]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_8.cin_used = "true", + add_sub_cella_8.lut_mask = "69b2", + add_sub_cella_8.operation_mode = "arithmetic", + add_sub_cella_8.sum_lutc_input = "cin", + add_sub_cella_8.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_9 + ( + .cin(wire_add_sub_cella_8cout[0:0]), + .combout(wire_add_sub_cella_combout[9:9]), + .cout(wire_add_sub_cella_9cout[0:0]), + .dataa(wire_add_sub_cella_dataa[9:9]), + .datab(wire_add_sub_cella_datab[9:9]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_9.cin_used = "true", + add_sub_cella_9.lut_mask = "69b2", + add_sub_cella_9.operation_mode = "arithmetic", + add_sub_cella_9.sum_lutc_input = "cin", + add_sub_cella_9.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_10 + ( + .cin(wire_add_sub_cella_9cout[0:0]), + .combout(wire_add_sub_cella_combout[10:10]), + .cout(), + .dataa(wire_add_sub_cella_dataa[10:10]), + .datab(wire_add_sub_cella_datab[10:10]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_10.cin_used = "true", + add_sub_cella_10.lut_mask = "6969", + add_sub_cella_10.operation_mode = "normal", + add_sub_cella_10.sum_lutc_input = "cin", + add_sub_cella_10.lpm_type = "cyclone_lcell"; + assign + wire_add_sub_cella_dataa = dataa, + wire_add_sub_cella_datab = datab; + assign + result = wire_add_sub_cella_combout; +endmodule //fifo_2k_add_sub_a18 + + +//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + + +//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 97 M4K 8 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_2k_dcfifo_0cq + ( + aclr, + data, + q, + rdclk, + rdempty, + rdreq, + rdusedw, + wrclk, + wrfull, + wrreq, + wrusedw) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; + input aclr; + input [15:0] data; + output [15:0] q; + input rdclk; + output rdempty; + input rdreq; + output [10:0] rdusedw; + input wrclk; + output wrfull; + input wrreq; + output [10:0] wrusedw; + + wire [10:0] wire_rdptr_g_gray2bin_bin; + wire [10:0] wire_rs_dgwp_gray2bin_bin; + wire [10:0] wire_wrptr_g_gray2bin_bin; + wire [10:0] wire_ws_dgrp_gray2bin_bin; + wire [10:0] wire_rdptr_g_q; + wire [10:0] wire_rdptr_g1p_q; + wire [10:0] wire_wrptr_g1p_q; + wire [15:0] wire_fifo_ram_q_b; + reg [10:0] delayed_wrptr_g; + reg [10:0] wrptr_g; + wire [10:0] wire_rs_brp_q; + wire [10:0] wire_rs_bwp_q; + wire [10:0] wire_rs_dgwp_q; + wire [10:0] wire_ws_brp_q; + wire [10:0] wire_ws_bwp_q; + wire [10:0] wire_ws_dgrp_q; + wire [10:0] wire_rdusedw_sub_result; + wire [10:0] wire_wrusedw_sub_result; + reg wire_rdempty_eq_comp_aeb_int; + wire wire_rdempty_eq_comp_aeb; + wire [10:0] wire_rdempty_eq_comp_dataa; + wire [10:0] wire_rdempty_eq_comp_datab; + reg wire_wrfull_eq_comp_aeb_int; + wire wire_wrfull_eq_comp_aeb; + wire [10:0] wire_wrfull_eq_comp_dataa; + wire [10:0] wire_wrfull_eq_comp_datab; + wire int_rdempty; + wire int_wrfull; + wire valid_rdreq; + wire valid_wrreq; + + fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin + ( + .bin(wire_rdptr_g_gray2bin_bin), + .gray(wire_rdptr_g_q)); + fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin + ( + .bin(wire_rs_dgwp_gray2bin_bin), + .gray(wire_rs_dgwp_q)); + fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin + ( + .bin(wire_wrptr_g_gray2bin_bin), + .gray(wrptr_g)); + fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin + ( + .bin(wire_ws_dgrp_gray2bin_bin), + .gray(wire_ws_dgrp_q)); + fifo_2k_a_graycounter_726 rdptr_g + ( + .aclr(aclr), + .clock(rdclk), + .cnt_en(valid_rdreq), + .q(wire_rdptr_g_q)); + fifo_2k_a_graycounter_2r6 rdptr_g1p + ( + .aclr(aclr), + .clock(rdclk), + .cnt_en(valid_rdreq), + .q(wire_rdptr_g1p_q)); + fifo_2k_a_graycounter_2r6 wrptr_g1p + ( + .aclr(aclr), + .clock(wrclk), + .cnt_en(valid_wrreq), + .q(wire_wrptr_g1p_q)); + fifo_2k_altsyncram_6pl fifo_ram + ( + .address_a(wrptr_g), + .address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))), + .clock0(wrclk), + .clock1(rdclk), + .clocken1((valid_rdreq | int_rdempty)), + .data_a(data), + .q_b(wire_fifo_ram_q_b), + .wren_a(valid_wrreq)); + // synopsys translate_off + initial + delayed_wrptr_g = 0; + // synopsys translate_on + always @ ( posedge wrclk or posedge aclr) + if (aclr == 1'b1) delayed_wrptr_g <= 11'b0; + else delayed_wrptr_g <= wrptr_g; + // synopsys translate_off + initial + wrptr_g = 0; + // synopsys translate_on + always @ ( posedge wrclk or posedge aclr) + if (aclr == 1'b1) wrptr_g <= 11'b0; + else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; + fifo_2k_dffpipe_ab3 rs_brp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(wire_rdptr_g_gray2bin_bin), + .q(wire_rs_brp_q)); + fifo_2k_dffpipe_ab3 rs_bwp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(wire_rs_dgwp_gray2bin_bin), + .q(wire_rs_bwp_q)); + fifo_2k_alt_synch_pipe_dm2 rs_dgwp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(delayed_wrptr_g), + .q(wire_rs_dgwp_q)); + fifo_2k_dffpipe_ab3 ws_brp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_ws_dgrp_gray2bin_bin), + .q(wire_ws_brp_q)); + fifo_2k_dffpipe_ab3 ws_bwp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_wrptr_g_gray2bin_bin), + .q(wire_ws_bwp_q)); + fifo_2k_alt_synch_pipe_dm2 ws_dgrp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_rdptr_g_q), + .q(wire_ws_dgrp_q)); + fifo_2k_add_sub_a18 rdusedw_sub + ( + .dataa(wire_rs_bwp_q), + .datab(wire_rs_brp_q), + .result(wire_rdusedw_sub_result)); + fifo_2k_add_sub_a18 wrusedw_sub + ( + .dataa(wire_ws_bwp_q), + .datab(wire_ws_brp_q), + .result(wire_wrusedw_sub_result)); + always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) + if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) + begin + wire_rdempty_eq_comp_aeb_int = 1'b1; + end + else + begin + wire_rdempty_eq_comp_aeb_int = 1'b0; + end + assign + wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; + assign + wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, + wire_rdempty_eq_comp_datab = wire_rdptr_g_q; + always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) + if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) + begin + wire_wrfull_eq_comp_aeb_int = 1'b1; + end + else + begin + wire_wrfull_eq_comp_aeb_int = 1'b0; + end + assign + wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; + assign + wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, + wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; + assign + int_rdempty = wire_rdempty_eq_comp_aeb, + int_wrfull = wire_wrfull_eq_comp_aeb, + q = wire_fifo_ram_q_b, + rdempty = int_rdempty, + rdusedw = wire_rdusedw_sub_result, + valid_rdreq = rdreq, + valid_wrreq = wrreq, + wrfull = int_wrfull, + wrusedw = wire_wrusedw_sub_result; +endmodule //fifo_2k_dcfifo_0cq +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_2k ( + data, + wrreq, + rdreq, + rdclk, + wrclk, + aclr, + q, + rdempty, + rdusedw, + wrfull, + wrusedw)/* synthesis synthesis_clearbox = 1 */; + + input [15:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [15:0] q; + output rdempty; + output [10:0] rdusedw; + output wrfull; + output [10:0] wrusedw; + + wire sub_wire0; + wire [10:0] sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire [10:0] sub_wire4; + wire rdempty = sub_wire0; + wire [10:0] wrusedw = sub_wire1[10:0]; + wire wrfull = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire [10:0] rdusedw = sub_wire4[10:0]; + + fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: Depth NUMERIC "2048" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0] +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0] +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE diff --git a/usrp1/megacells/fifo_2k_bb.v b/usrp1/megacells/fifo_2k_bb.v new file mode 100644 index 000000000..3fcc2a496 --- /dev/null +++ b/usrp1/megacells/fifo_2k_bb.v @@ -0,0 +1,131 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_2k.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_2k ( + data, + wrreq, + rdreq, + rdclk, + wrclk, + aclr, + q, + rdempty, + rdusedw, + wrfull, + wrusedw)/* synthesis synthesis_clearbox = 1 */; + + input [15:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [15:0] q; + output rdempty; + output [10:0] rdusedw; + output wrfull; + output [10:0] wrusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: Depth NUMERIC "2048" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0] +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0] +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE diff --git a/usrp1/megacells/fifo_4k.v b/usrp1/megacells/fifo_4k.v new file mode 100644 index 000000000..a5ab46677 --- /dev/null +++ b/usrp1/megacells/fifo_4k.v @@ -0,0 +1,3495 @@ +// megafunction wizard: %FIFO%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4k.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + + +//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END + +//synthesis_resources = +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_a_gray2bin_9m4 + ( + bin, + gray) /* synthesis synthesis_clearbox=1 */; + output [11:0] bin; + input [11:0] gray; + + wire xor0; + wire xor1; + wire xor10; + wire xor2; + wire xor3; + wire xor4; + wire xor5; + wire xor6; + wire xor7; + wire xor8; + wire xor9; + + assign + bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, + xor0 = (gray[0] ^ xor1), + xor1 = (gray[1] ^ xor2), + xor10 = (gray[11] ^ gray[10]), + xor2 = (gray[2] ^ xor3), + xor3 = (gray[3] ^ xor4), + xor4 = (gray[4] ^ xor5), + xor5 = (gray[5] ^ xor6), + xor6 = (gray[6] ^ xor7), + xor7 = (gray[7] ^ xor8), + xor8 = (gray[8] ^ xor9), + xor9 = (gray[9] ^ xor10); +endmodule //fifo_4k_a_gray2bin_9m4 + + +//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 13 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_a_graycounter_826 + ( + aclr, + clock, + cnt_en, + q) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clock; + input cnt_en; + output [11:0] q; + + wire [0:0] wire_countera_0cout; + wire [0:0] wire_countera_1cout; + wire [0:0] wire_countera_2cout; + wire [0:0] wire_countera_3cout; + wire [0:0] wire_countera_4cout; + wire [0:0] wire_countera_5cout; + wire [0:0] wire_countera_6cout; + wire [0:0] wire_countera_7cout; + wire [0:0] wire_countera_8cout; + wire [0:0] wire_countera_9cout; + wire [0:0] wire_countera_10cout; + wire [11:0] wire_countera_regout; + wire wire_parity_cout; + wire wire_parity_regout; + wire [11:0] power_modified_counter_values; + wire sclr; + wire updown; + + cyclone_lcell countera_0 + ( + .aclr(aclr), + .cin(wire_parity_cout), + .clk(clock), + .combout(), + .cout(wire_countera_0cout[0:0]), + .dataa(cnt_en), + .datab(wire_countera_regout[0:0]), + .ena(1'b1), + .regout(wire_countera_regout[0:0]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_0.cin_used = "true", + countera_0.lut_mask = "c6a0", + countera_0.operation_mode = "arithmetic", + countera_0.sum_lutc_input = "cin", + countera_0.synch_mode = "on", + countera_0.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_1 + ( + .aclr(aclr), + .cin(wire_countera_0cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_1cout[0:0]), + .dataa(power_modified_counter_values[0]), + .datab(power_modified_counter_values[1]), + .ena(1'b1), + .regout(wire_countera_regout[1:1]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_1.cin_used = "true", + countera_1.lut_mask = "6c50", + countera_1.operation_mode = "arithmetic", + countera_1.sum_lutc_input = "cin", + countera_1.synch_mode = "on", + countera_1.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_2 + ( + .aclr(aclr), + .cin(wire_countera_1cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_2cout[0:0]), + .dataa(power_modified_counter_values[1]), + .datab(power_modified_counter_values[2]), + .ena(1'b1), + .regout(wire_countera_regout[2:2]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_2.cin_used = "true", + countera_2.lut_mask = "6c50", + countera_2.operation_mode = "arithmetic", + countera_2.sum_lutc_input = "cin", + countera_2.synch_mode = "on", + countera_2.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_3 + ( + .aclr(aclr), + .cin(wire_countera_2cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_3cout[0:0]), + .dataa(power_modified_counter_values[2]), + .datab(power_modified_counter_values[3]), + .ena(1'b1), + .regout(wire_countera_regout[3:3]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_3.cin_used = "true", + countera_3.lut_mask = "6c50", + countera_3.operation_mode = "arithmetic", + countera_3.sum_lutc_input = "cin", + countera_3.synch_mode = "on", + countera_3.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_4 + ( + .aclr(aclr), + .cin(wire_countera_3cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_4cout[0:0]), + .dataa(power_modified_counter_values[3]), + .datab(power_modified_counter_values[4]), + .ena(1'b1), + .regout(wire_countera_regout[4:4]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_4.cin_used = "true", + countera_4.lut_mask = "6c50", + countera_4.operation_mode = "arithmetic", + countera_4.sum_lutc_input = "cin", + countera_4.synch_mode = "on", + countera_4.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_5 + ( + .aclr(aclr), + .cin(wire_countera_4cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_5cout[0:0]), + .dataa(power_modified_counter_values[4]), + .datab(power_modified_counter_values[5]), + .ena(1'b1), + .regout(wire_countera_regout[5:5]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_5.cin_used = "true", + countera_5.lut_mask = "6c50", + countera_5.operation_mode = "arithmetic", + countera_5.sum_lutc_input = "cin", + countera_5.synch_mode = "on", + countera_5.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_6 + ( + .aclr(aclr), + .cin(wire_countera_5cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_6cout[0:0]), + .dataa(power_modified_counter_values[5]), + .datab(power_modified_counter_values[6]), + .ena(1'b1), + .regout(wire_countera_regout[6:6]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_6.cin_used = "true", + countera_6.lut_mask = "6c50", + countera_6.operation_mode = "arithmetic", + countera_6.sum_lutc_input = "cin", + countera_6.synch_mode = "on", + countera_6.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_7 + ( + .aclr(aclr), + .cin(wire_countera_6cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_7cout[0:0]), + .dataa(power_modified_counter_values[6]), + .datab(power_modified_counter_values[7]), + .ena(1'b1), + .regout(wire_countera_regout[7:7]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_7.cin_used = "true", + countera_7.lut_mask = "6c50", + countera_7.operation_mode = "arithmetic", + countera_7.sum_lutc_input = "cin", + countera_7.synch_mode = "on", + countera_7.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_8 + ( + .aclr(aclr), + .cin(wire_countera_7cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_8cout[0:0]), + .dataa(power_modified_counter_values[7]), + .datab(power_modified_counter_values[8]), + .ena(1'b1), + .regout(wire_countera_regout[8:8]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_8.cin_used = "true", + countera_8.lut_mask = "6c50", + countera_8.operation_mode = "arithmetic", + countera_8.sum_lutc_input = "cin", + countera_8.synch_mode = "on", + countera_8.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_9 + ( + .aclr(aclr), + .cin(wire_countera_8cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_9cout[0:0]), + .dataa(power_modified_counter_values[8]), + .datab(power_modified_counter_values[9]), + .ena(1'b1), + .regout(wire_countera_regout[9:9]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_9.cin_used = "true", + countera_9.lut_mask = "6c50", + countera_9.operation_mode = "arithmetic", + countera_9.sum_lutc_input = "cin", + countera_9.synch_mode = "on", + countera_9.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_10 + ( + .aclr(aclr), + .cin(wire_countera_9cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_10cout[0:0]), + .dataa(power_modified_counter_values[9]), + .datab(power_modified_counter_values[10]), + .ena(1'b1), + .regout(wire_countera_regout[10:10]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_10.cin_used = "true", + countera_10.lut_mask = "6c50", + countera_10.operation_mode = "arithmetic", + countera_10.sum_lutc_input = "cin", + countera_10.synch_mode = "on", + countera_10.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_11 + ( + .aclr(aclr), + .cin(wire_countera_10cout[0:0]), + .clk(clock), + .combout(), + .cout(), + .dataa(power_modified_counter_values[11]), + .ena(1'b1), + .regout(wire_countera_regout[11:11]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datab(1'b1), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_11.cin_used = "true", + countera_11.lut_mask = "5a5a", + countera_11.operation_mode = "normal", + countera_11.sum_lutc_input = "cin", + countera_11.synch_mode = "on", + countera_11.lpm_type = "cyclone_lcell"; + cyclone_lcell parity + ( + .aclr(aclr), + .cin(updown), + .clk(clock), + .combout(), + .cout(wire_parity_cout), + .dataa(cnt_en), + .datab(wire_parity_regout), + .ena(1'b1), + .regout(wire_parity_regout), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + parity.cin_used = "true", + parity.lut_mask = "6682", + parity.operation_mode = "arithmetic", + parity.synch_mode = "on", + parity.lpm_type = "cyclone_lcell"; + assign + power_modified_counter_values = {wire_countera_regout[11:0]}, + q = power_modified_counter_values, + sclr = 1'b0, + updown = 1'b1; +endmodule //fifo_4k_a_graycounter_826 + + +//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 13 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_a_graycounter_3r6 + ( + aclr, + clock, + cnt_en, + q) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clock; + input cnt_en; + output [11:0] q; + + wire [0:0] wire_countera_0cout; + wire [0:0] wire_countera_1cout; + wire [0:0] wire_countera_2cout; + wire [0:0] wire_countera_3cout; + wire [0:0] wire_countera_4cout; + wire [0:0] wire_countera_5cout; + wire [0:0] wire_countera_6cout; + wire [0:0] wire_countera_7cout; + wire [0:0] wire_countera_8cout; + wire [0:0] wire_countera_9cout; + wire [0:0] wire_countera_10cout; + wire [11:0] wire_countera_regout; + wire wire_parity_cout; + wire wire_parity_regout; + wire [11:0] power_modified_counter_values; + wire sclr; + wire updown; + + cyclone_lcell countera_0 + ( + .aclr(aclr), + .cin(wire_parity_cout), + .clk(clock), + .combout(), + .cout(wire_countera_0cout[0:0]), + .dataa(cnt_en), + .datab(wire_countera_regout[0:0]), + .ena(1'b1), + .regout(wire_countera_regout[0:0]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_0.cin_used = "true", + countera_0.lut_mask = "c6a0", + countera_0.operation_mode = "arithmetic", + countera_0.sum_lutc_input = "cin", + countera_0.synch_mode = "on", + countera_0.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_1 + ( + .aclr(aclr), + .cin(wire_countera_0cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_1cout[0:0]), + .dataa(power_modified_counter_values[0]), + .datab(power_modified_counter_values[1]), + .ena(1'b1), + .regout(wire_countera_regout[1:1]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_1.cin_used = "true", + countera_1.lut_mask = "6c50", + countera_1.operation_mode = "arithmetic", + countera_1.sum_lutc_input = "cin", + countera_1.synch_mode = "on", + countera_1.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_2 + ( + .aclr(aclr), + .cin(wire_countera_1cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_2cout[0:0]), + .dataa(power_modified_counter_values[1]), + .datab(power_modified_counter_values[2]), + .ena(1'b1), + .regout(wire_countera_regout[2:2]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_2.cin_used = "true", + countera_2.lut_mask = "6c50", + countera_2.operation_mode = "arithmetic", + countera_2.sum_lutc_input = "cin", + countera_2.synch_mode = "on", + countera_2.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_3 + ( + .aclr(aclr), + .cin(wire_countera_2cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_3cout[0:0]), + .dataa(power_modified_counter_values[2]), + .datab(power_modified_counter_values[3]), + .ena(1'b1), + .regout(wire_countera_regout[3:3]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_3.cin_used = "true", + countera_3.lut_mask = "6c50", + countera_3.operation_mode = "arithmetic", + countera_3.sum_lutc_input = "cin", + countera_3.synch_mode = "on", + countera_3.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_4 + ( + .aclr(aclr), + .cin(wire_countera_3cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_4cout[0:0]), + .dataa(power_modified_counter_values[3]), + .datab(power_modified_counter_values[4]), + .ena(1'b1), + .regout(wire_countera_regout[4:4]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_4.cin_used = "true", + countera_4.lut_mask = "6c50", + countera_4.operation_mode = "arithmetic", + countera_4.sum_lutc_input = "cin", + countera_4.synch_mode = "on", + countera_4.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_5 + ( + .aclr(aclr), + .cin(wire_countera_4cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_5cout[0:0]), + .dataa(power_modified_counter_values[4]), + .datab(power_modified_counter_values[5]), + .ena(1'b1), + .regout(wire_countera_regout[5:5]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_5.cin_used = "true", + countera_5.lut_mask = "6c50", + countera_5.operation_mode = "arithmetic", + countera_5.sum_lutc_input = "cin", + countera_5.synch_mode = "on", + countera_5.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_6 + ( + .aclr(aclr), + .cin(wire_countera_5cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_6cout[0:0]), + .dataa(power_modified_counter_values[5]), + .datab(power_modified_counter_values[6]), + .ena(1'b1), + .regout(wire_countera_regout[6:6]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_6.cin_used = "true", + countera_6.lut_mask = "6c50", + countera_6.operation_mode = "arithmetic", + countera_6.sum_lutc_input = "cin", + countera_6.synch_mode = "on", + countera_6.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_7 + ( + .aclr(aclr), + .cin(wire_countera_6cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_7cout[0:0]), + .dataa(power_modified_counter_values[6]), + .datab(power_modified_counter_values[7]), + .ena(1'b1), + .regout(wire_countera_regout[7:7]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_7.cin_used = "true", + countera_7.lut_mask = "6c50", + countera_7.operation_mode = "arithmetic", + countera_7.sum_lutc_input = "cin", + countera_7.synch_mode = "on", + countera_7.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_8 + ( + .aclr(aclr), + .cin(wire_countera_7cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_8cout[0:0]), + .dataa(power_modified_counter_values[7]), + .datab(power_modified_counter_values[8]), + .ena(1'b1), + .regout(wire_countera_regout[8:8]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_8.cin_used = "true", + countera_8.lut_mask = "6c50", + countera_8.operation_mode = "arithmetic", + countera_8.sum_lutc_input = "cin", + countera_8.synch_mode = "on", + countera_8.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_9 + ( + .aclr(aclr), + .cin(wire_countera_8cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_9cout[0:0]), + .dataa(power_modified_counter_values[8]), + .datab(power_modified_counter_values[9]), + .ena(1'b1), + .regout(wire_countera_regout[9:9]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_9.cin_used = "true", + countera_9.lut_mask = "6c50", + countera_9.operation_mode = "arithmetic", + countera_9.sum_lutc_input = "cin", + countera_9.synch_mode = "on", + countera_9.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_10 + ( + .aclr(aclr), + .cin(wire_countera_9cout[0:0]), + .clk(clock), + .combout(), + .cout(wire_countera_10cout[0:0]), + .dataa(power_modified_counter_values[9]), + .datab(power_modified_counter_values[10]), + .ena(1'b1), + .regout(wire_countera_regout[10:10]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_10.cin_used = "true", + countera_10.lut_mask = "6c50", + countera_10.operation_mode = "arithmetic", + countera_10.sum_lutc_input = "cin", + countera_10.synch_mode = "on", + countera_10.lpm_type = "cyclone_lcell"; + cyclone_lcell countera_11 + ( + .aclr(aclr), + .cin(wire_countera_10cout[0:0]), + .clk(clock), + .combout(), + .cout(), + .dataa(power_modified_counter_values[11]), + .ena(1'b1), + .regout(wire_countera_regout[11:11]), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datab(1'b1), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + countera_11.cin_used = "true", + countera_11.lut_mask = "5a5a", + countera_11.operation_mode = "normal", + countera_11.sum_lutc_input = "cin", + countera_11.synch_mode = "on", + countera_11.lpm_type = "cyclone_lcell"; + cyclone_lcell parity + ( + .aclr(aclr), + .cin(updown), + .clk(clock), + .combout(), + .cout(wire_parity_cout), + .dataa(cnt_en), + .datab((~ wire_parity_regout)), + .ena(1'b1), + .regout(wire_parity_regout), + .sclr(sclr) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aload(1'b0), + .datac(1'b1), + .datad(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + parity.cin_used = "true", + parity.lut_mask = "9982", + parity.operation_mode = "arithmetic", + parity.synch_mode = "on", + parity.lpm_type = "cyclone_lcell"; + assign + power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])}, + q = power_modified_counter_values, + sclr = 1'b0, + updown = 1'b1; +endmodule //fifo_4k_a_graycounter_3r6 + + +//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a +//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = M4K 16 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_altsyncram_8pl + ( + address_a, + address_b, + clock0, + clock1, + clocken1, + data_a, + q_b, + wren_a) /* synthesis synthesis_clearbox=1 */; + input [11:0] address_a; + input [11:0] address_b; + input clock0; + input clock1; + input clocken1; + input [15:0] data_a; + output [15:0] q_b; + input wren_a; + + wire [0:0] wire_ram_block3a_0portbdataout; + wire [0:0] wire_ram_block3a_1portbdataout; + wire [0:0] wire_ram_block3a_2portbdataout; + wire [0:0] wire_ram_block3a_3portbdataout; + wire [0:0] wire_ram_block3a_4portbdataout; + wire [0:0] wire_ram_block3a_5portbdataout; + wire [0:0] wire_ram_block3a_6portbdataout; + wire [0:0] wire_ram_block3a_7portbdataout; + wire [0:0] wire_ram_block3a_8portbdataout; + wire [0:0] wire_ram_block3a_9portbdataout; + wire [0:0] wire_ram_block3a_10portbdataout; + wire [0:0] wire_ram_block3a_11portbdataout; + wire [0:0] wire_ram_block3a_12portbdataout; + wire [0:0] wire_ram_block3a_13portbdataout; + wire [0:0] wire_ram_block3a_14portbdataout; + wire [0:0] wire_ram_block3a_15portbdataout; + wire [11:0] address_a_wire; + wire [11:0] address_b_wire; + + cyclone_ram_block ram_block3a_0 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[0]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_0portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_0.connectivity_checking = "OFF", + ram_block3a_0.logical_ram_name = "ALTSYNCRAM", + ram_block3a_0.mixed_port_feed_through_mode = "dont_care", + ram_block3a_0.operation_mode = "dual_port", + ram_block3a_0.port_a_address_width = 12, + ram_block3a_0.port_a_data_width = 1, + ram_block3a_0.port_a_first_address = 0, + ram_block3a_0.port_a_first_bit_number = 0, + ram_block3a_0.port_a_last_address = 4095, + ram_block3a_0.port_a_logical_ram_depth = 4096, + ram_block3a_0.port_a_logical_ram_width = 16, + ram_block3a_0.port_b_address_clear = "none", + ram_block3a_0.port_b_address_clock = "clock1", + ram_block3a_0.port_b_address_width = 12, + ram_block3a_0.port_b_data_out_clear = "none", + ram_block3a_0.port_b_data_out_clock = "none", + ram_block3a_0.port_b_data_width = 1, + ram_block3a_0.port_b_first_address = 0, + ram_block3a_0.port_b_first_bit_number = 0, + ram_block3a_0.port_b_last_address = 4095, + ram_block3a_0.port_b_logical_ram_depth = 4096, + ram_block3a_0.port_b_logical_ram_width = 16, + ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_0.ram_block_type = "auto", + ram_block3a_0.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_1 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[1]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_1portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_1.connectivity_checking = "OFF", + ram_block3a_1.logical_ram_name = "ALTSYNCRAM", + ram_block3a_1.mixed_port_feed_through_mode = "dont_care", + ram_block3a_1.operation_mode = "dual_port", + ram_block3a_1.port_a_address_width = 12, + ram_block3a_1.port_a_data_width = 1, + ram_block3a_1.port_a_first_address = 0, + ram_block3a_1.port_a_first_bit_number = 1, + ram_block3a_1.port_a_last_address = 4095, + ram_block3a_1.port_a_logical_ram_depth = 4096, + ram_block3a_1.port_a_logical_ram_width = 16, + ram_block3a_1.port_b_address_clear = "none", + ram_block3a_1.port_b_address_clock = "clock1", + ram_block3a_1.port_b_address_width = 12, + ram_block3a_1.port_b_data_out_clear = "none", + ram_block3a_1.port_b_data_out_clock = "none", + ram_block3a_1.port_b_data_width = 1, + ram_block3a_1.port_b_first_address = 0, + ram_block3a_1.port_b_first_bit_number = 1, + ram_block3a_1.port_b_last_address = 4095, + ram_block3a_1.port_b_logical_ram_depth = 4096, + ram_block3a_1.port_b_logical_ram_width = 16, + ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_1.ram_block_type = "auto", + ram_block3a_1.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_2 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[2]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_2portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_2.connectivity_checking = "OFF", + ram_block3a_2.logical_ram_name = "ALTSYNCRAM", + ram_block3a_2.mixed_port_feed_through_mode = "dont_care", + ram_block3a_2.operation_mode = "dual_port", + ram_block3a_2.port_a_address_width = 12, + ram_block3a_2.port_a_data_width = 1, + ram_block3a_2.port_a_first_address = 0, + ram_block3a_2.port_a_first_bit_number = 2, + ram_block3a_2.port_a_last_address = 4095, + ram_block3a_2.port_a_logical_ram_depth = 4096, + ram_block3a_2.port_a_logical_ram_width = 16, + ram_block3a_2.port_b_address_clear = "none", + ram_block3a_2.port_b_address_clock = "clock1", + ram_block3a_2.port_b_address_width = 12, + ram_block3a_2.port_b_data_out_clear = "none", + ram_block3a_2.port_b_data_out_clock = "none", + ram_block3a_2.port_b_data_width = 1, + ram_block3a_2.port_b_first_address = 0, + ram_block3a_2.port_b_first_bit_number = 2, + ram_block3a_2.port_b_last_address = 4095, + ram_block3a_2.port_b_logical_ram_depth = 4096, + ram_block3a_2.port_b_logical_ram_width = 16, + ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_2.ram_block_type = "auto", + ram_block3a_2.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_3 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[3]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_3portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_3.connectivity_checking = "OFF", + ram_block3a_3.logical_ram_name = "ALTSYNCRAM", + ram_block3a_3.mixed_port_feed_through_mode = "dont_care", + ram_block3a_3.operation_mode = "dual_port", + ram_block3a_3.port_a_address_width = 12, + ram_block3a_3.port_a_data_width = 1, + ram_block3a_3.port_a_first_address = 0, + ram_block3a_3.port_a_first_bit_number = 3, + ram_block3a_3.port_a_last_address = 4095, + ram_block3a_3.port_a_logical_ram_depth = 4096, + ram_block3a_3.port_a_logical_ram_width = 16, + ram_block3a_3.port_b_address_clear = "none", + ram_block3a_3.port_b_address_clock = "clock1", + ram_block3a_3.port_b_address_width = 12, + ram_block3a_3.port_b_data_out_clear = "none", + ram_block3a_3.port_b_data_out_clock = "none", + ram_block3a_3.port_b_data_width = 1, + ram_block3a_3.port_b_first_address = 0, + ram_block3a_3.port_b_first_bit_number = 3, + ram_block3a_3.port_b_last_address = 4095, + ram_block3a_3.port_b_logical_ram_depth = 4096, + ram_block3a_3.port_b_logical_ram_width = 16, + ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_3.ram_block_type = "auto", + ram_block3a_3.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_4 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[4]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_4portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_4.connectivity_checking = "OFF", + ram_block3a_4.logical_ram_name = "ALTSYNCRAM", + ram_block3a_4.mixed_port_feed_through_mode = "dont_care", + ram_block3a_4.operation_mode = "dual_port", + ram_block3a_4.port_a_address_width = 12, + ram_block3a_4.port_a_data_width = 1, + ram_block3a_4.port_a_first_address = 0, + ram_block3a_4.port_a_first_bit_number = 4, + ram_block3a_4.port_a_last_address = 4095, + ram_block3a_4.port_a_logical_ram_depth = 4096, + ram_block3a_4.port_a_logical_ram_width = 16, + ram_block3a_4.port_b_address_clear = "none", + ram_block3a_4.port_b_address_clock = "clock1", + ram_block3a_4.port_b_address_width = 12, + ram_block3a_4.port_b_data_out_clear = "none", + ram_block3a_4.port_b_data_out_clock = "none", + ram_block3a_4.port_b_data_width = 1, + ram_block3a_4.port_b_first_address = 0, + ram_block3a_4.port_b_first_bit_number = 4, + ram_block3a_4.port_b_last_address = 4095, + ram_block3a_4.port_b_logical_ram_depth = 4096, + ram_block3a_4.port_b_logical_ram_width = 16, + ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_4.ram_block_type = "auto", + ram_block3a_4.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_5 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[5]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_5portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_5.connectivity_checking = "OFF", + ram_block3a_5.logical_ram_name = "ALTSYNCRAM", + ram_block3a_5.mixed_port_feed_through_mode = "dont_care", + ram_block3a_5.operation_mode = "dual_port", + ram_block3a_5.port_a_address_width = 12, + ram_block3a_5.port_a_data_width = 1, + ram_block3a_5.port_a_first_address = 0, + ram_block3a_5.port_a_first_bit_number = 5, + ram_block3a_5.port_a_last_address = 4095, + ram_block3a_5.port_a_logical_ram_depth = 4096, + ram_block3a_5.port_a_logical_ram_width = 16, + ram_block3a_5.port_b_address_clear = "none", + ram_block3a_5.port_b_address_clock = "clock1", + ram_block3a_5.port_b_address_width = 12, + ram_block3a_5.port_b_data_out_clear = "none", + ram_block3a_5.port_b_data_out_clock = "none", + ram_block3a_5.port_b_data_width = 1, + ram_block3a_5.port_b_first_address = 0, + ram_block3a_5.port_b_first_bit_number = 5, + ram_block3a_5.port_b_last_address = 4095, + ram_block3a_5.port_b_logical_ram_depth = 4096, + ram_block3a_5.port_b_logical_ram_width = 16, + ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_5.ram_block_type = "auto", + ram_block3a_5.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_6 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[6]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_6portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_6.connectivity_checking = "OFF", + ram_block3a_6.logical_ram_name = "ALTSYNCRAM", + ram_block3a_6.mixed_port_feed_through_mode = "dont_care", + ram_block3a_6.operation_mode = "dual_port", + ram_block3a_6.port_a_address_width = 12, + ram_block3a_6.port_a_data_width = 1, + ram_block3a_6.port_a_first_address = 0, + ram_block3a_6.port_a_first_bit_number = 6, + ram_block3a_6.port_a_last_address = 4095, + ram_block3a_6.port_a_logical_ram_depth = 4096, + ram_block3a_6.port_a_logical_ram_width = 16, + ram_block3a_6.port_b_address_clear = "none", + ram_block3a_6.port_b_address_clock = "clock1", + ram_block3a_6.port_b_address_width = 12, + ram_block3a_6.port_b_data_out_clear = "none", + ram_block3a_6.port_b_data_out_clock = "none", + ram_block3a_6.port_b_data_width = 1, + ram_block3a_6.port_b_first_address = 0, + ram_block3a_6.port_b_first_bit_number = 6, + ram_block3a_6.port_b_last_address = 4095, + ram_block3a_6.port_b_logical_ram_depth = 4096, + ram_block3a_6.port_b_logical_ram_width = 16, + ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_6.ram_block_type = "auto", + ram_block3a_6.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_7 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[7]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_7portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_7.connectivity_checking = "OFF", + ram_block3a_7.logical_ram_name = "ALTSYNCRAM", + ram_block3a_7.mixed_port_feed_through_mode = "dont_care", + ram_block3a_7.operation_mode = "dual_port", + ram_block3a_7.port_a_address_width = 12, + ram_block3a_7.port_a_data_width = 1, + ram_block3a_7.port_a_first_address = 0, + ram_block3a_7.port_a_first_bit_number = 7, + ram_block3a_7.port_a_last_address = 4095, + ram_block3a_7.port_a_logical_ram_depth = 4096, + ram_block3a_7.port_a_logical_ram_width = 16, + ram_block3a_7.port_b_address_clear = "none", + ram_block3a_7.port_b_address_clock = "clock1", + ram_block3a_7.port_b_address_width = 12, + ram_block3a_7.port_b_data_out_clear = "none", + ram_block3a_7.port_b_data_out_clock = "none", + ram_block3a_7.port_b_data_width = 1, + ram_block3a_7.port_b_first_address = 0, + ram_block3a_7.port_b_first_bit_number = 7, + ram_block3a_7.port_b_last_address = 4095, + ram_block3a_7.port_b_logical_ram_depth = 4096, + ram_block3a_7.port_b_logical_ram_width = 16, + ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_7.ram_block_type = "auto", + ram_block3a_7.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_8 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[8]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_8portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_8.connectivity_checking = "OFF", + ram_block3a_8.logical_ram_name = "ALTSYNCRAM", + ram_block3a_8.mixed_port_feed_through_mode = "dont_care", + ram_block3a_8.operation_mode = "dual_port", + ram_block3a_8.port_a_address_width = 12, + ram_block3a_8.port_a_data_width = 1, + ram_block3a_8.port_a_first_address = 0, + ram_block3a_8.port_a_first_bit_number = 8, + ram_block3a_8.port_a_last_address = 4095, + ram_block3a_8.port_a_logical_ram_depth = 4096, + ram_block3a_8.port_a_logical_ram_width = 16, + ram_block3a_8.port_b_address_clear = "none", + ram_block3a_8.port_b_address_clock = "clock1", + ram_block3a_8.port_b_address_width = 12, + ram_block3a_8.port_b_data_out_clear = "none", + ram_block3a_8.port_b_data_out_clock = "none", + ram_block3a_8.port_b_data_width = 1, + ram_block3a_8.port_b_first_address = 0, + ram_block3a_8.port_b_first_bit_number = 8, + ram_block3a_8.port_b_last_address = 4095, + ram_block3a_8.port_b_logical_ram_depth = 4096, + ram_block3a_8.port_b_logical_ram_width = 16, + ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_8.ram_block_type = "auto", + ram_block3a_8.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_9 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[9]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_9portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_9.connectivity_checking = "OFF", + ram_block3a_9.logical_ram_name = "ALTSYNCRAM", + ram_block3a_9.mixed_port_feed_through_mode = "dont_care", + ram_block3a_9.operation_mode = "dual_port", + ram_block3a_9.port_a_address_width = 12, + ram_block3a_9.port_a_data_width = 1, + ram_block3a_9.port_a_first_address = 0, + ram_block3a_9.port_a_first_bit_number = 9, + ram_block3a_9.port_a_last_address = 4095, + ram_block3a_9.port_a_logical_ram_depth = 4096, + ram_block3a_9.port_a_logical_ram_width = 16, + ram_block3a_9.port_b_address_clear = "none", + ram_block3a_9.port_b_address_clock = "clock1", + ram_block3a_9.port_b_address_width = 12, + ram_block3a_9.port_b_data_out_clear = "none", + ram_block3a_9.port_b_data_out_clock = "none", + ram_block3a_9.port_b_data_width = 1, + ram_block3a_9.port_b_first_address = 0, + ram_block3a_9.port_b_first_bit_number = 9, + ram_block3a_9.port_b_last_address = 4095, + ram_block3a_9.port_b_logical_ram_depth = 4096, + ram_block3a_9.port_b_logical_ram_width = 16, + ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_9.ram_block_type = "auto", + ram_block3a_9.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_10 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[10]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_10portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_10.connectivity_checking = "OFF", + ram_block3a_10.logical_ram_name = "ALTSYNCRAM", + ram_block3a_10.mixed_port_feed_through_mode = "dont_care", + ram_block3a_10.operation_mode = "dual_port", + ram_block3a_10.port_a_address_width = 12, + ram_block3a_10.port_a_data_width = 1, + ram_block3a_10.port_a_first_address = 0, + ram_block3a_10.port_a_first_bit_number = 10, + ram_block3a_10.port_a_last_address = 4095, + ram_block3a_10.port_a_logical_ram_depth = 4096, + ram_block3a_10.port_a_logical_ram_width = 16, + ram_block3a_10.port_b_address_clear = "none", + ram_block3a_10.port_b_address_clock = "clock1", + ram_block3a_10.port_b_address_width = 12, + ram_block3a_10.port_b_data_out_clear = "none", + ram_block3a_10.port_b_data_out_clock = "none", + ram_block3a_10.port_b_data_width = 1, + ram_block3a_10.port_b_first_address = 0, + ram_block3a_10.port_b_first_bit_number = 10, + ram_block3a_10.port_b_last_address = 4095, + ram_block3a_10.port_b_logical_ram_depth = 4096, + ram_block3a_10.port_b_logical_ram_width = 16, + ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_10.ram_block_type = "auto", + ram_block3a_10.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_11 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[11]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_11portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_11.connectivity_checking = "OFF", + ram_block3a_11.logical_ram_name = "ALTSYNCRAM", + ram_block3a_11.mixed_port_feed_through_mode = "dont_care", + ram_block3a_11.operation_mode = "dual_port", + ram_block3a_11.port_a_address_width = 12, + ram_block3a_11.port_a_data_width = 1, + ram_block3a_11.port_a_first_address = 0, + ram_block3a_11.port_a_first_bit_number = 11, + ram_block3a_11.port_a_last_address = 4095, + ram_block3a_11.port_a_logical_ram_depth = 4096, + ram_block3a_11.port_a_logical_ram_width = 16, + ram_block3a_11.port_b_address_clear = "none", + ram_block3a_11.port_b_address_clock = "clock1", + ram_block3a_11.port_b_address_width = 12, + ram_block3a_11.port_b_data_out_clear = "none", + ram_block3a_11.port_b_data_out_clock = "none", + ram_block3a_11.port_b_data_width = 1, + ram_block3a_11.port_b_first_address = 0, + ram_block3a_11.port_b_first_bit_number = 11, + ram_block3a_11.port_b_last_address = 4095, + ram_block3a_11.port_b_logical_ram_depth = 4096, + ram_block3a_11.port_b_logical_ram_width = 16, + ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_11.ram_block_type = "auto", + ram_block3a_11.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_12 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[12]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_12portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_12.connectivity_checking = "OFF", + ram_block3a_12.logical_ram_name = "ALTSYNCRAM", + ram_block3a_12.mixed_port_feed_through_mode = "dont_care", + ram_block3a_12.operation_mode = "dual_port", + ram_block3a_12.port_a_address_width = 12, + ram_block3a_12.port_a_data_width = 1, + ram_block3a_12.port_a_first_address = 0, + ram_block3a_12.port_a_first_bit_number = 12, + ram_block3a_12.port_a_last_address = 4095, + ram_block3a_12.port_a_logical_ram_depth = 4096, + ram_block3a_12.port_a_logical_ram_width = 16, + ram_block3a_12.port_b_address_clear = "none", + ram_block3a_12.port_b_address_clock = "clock1", + ram_block3a_12.port_b_address_width = 12, + ram_block3a_12.port_b_data_out_clear = "none", + ram_block3a_12.port_b_data_out_clock = "none", + ram_block3a_12.port_b_data_width = 1, + ram_block3a_12.port_b_first_address = 0, + ram_block3a_12.port_b_first_bit_number = 12, + ram_block3a_12.port_b_last_address = 4095, + ram_block3a_12.port_b_logical_ram_depth = 4096, + ram_block3a_12.port_b_logical_ram_width = 16, + ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_12.ram_block_type = "auto", + ram_block3a_12.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_13 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[13]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_13portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_13.connectivity_checking = "OFF", + ram_block3a_13.logical_ram_name = "ALTSYNCRAM", + ram_block3a_13.mixed_port_feed_through_mode = "dont_care", + ram_block3a_13.operation_mode = "dual_port", + ram_block3a_13.port_a_address_width = 12, + ram_block3a_13.port_a_data_width = 1, + ram_block3a_13.port_a_first_address = 0, + ram_block3a_13.port_a_first_bit_number = 13, + ram_block3a_13.port_a_last_address = 4095, + ram_block3a_13.port_a_logical_ram_depth = 4096, + ram_block3a_13.port_a_logical_ram_width = 16, + ram_block3a_13.port_b_address_clear = "none", + ram_block3a_13.port_b_address_clock = "clock1", + ram_block3a_13.port_b_address_width = 12, + ram_block3a_13.port_b_data_out_clear = "none", + ram_block3a_13.port_b_data_out_clock = "none", + ram_block3a_13.port_b_data_width = 1, + ram_block3a_13.port_b_first_address = 0, + ram_block3a_13.port_b_first_bit_number = 13, + ram_block3a_13.port_b_last_address = 4095, + ram_block3a_13.port_b_logical_ram_depth = 4096, + ram_block3a_13.port_b_logical_ram_width = 16, + ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_13.ram_block_type = "auto", + ram_block3a_13.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_14 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[14]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_14portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_14.connectivity_checking = "OFF", + ram_block3a_14.logical_ram_name = "ALTSYNCRAM", + ram_block3a_14.mixed_port_feed_through_mode = "dont_care", + ram_block3a_14.operation_mode = "dual_port", + ram_block3a_14.port_a_address_width = 12, + ram_block3a_14.port_a_data_width = 1, + ram_block3a_14.port_a_first_address = 0, + ram_block3a_14.port_a_first_bit_number = 14, + ram_block3a_14.port_a_last_address = 4095, + ram_block3a_14.port_a_logical_ram_depth = 4096, + ram_block3a_14.port_a_logical_ram_width = 16, + ram_block3a_14.port_b_address_clear = "none", + ram_block3a_14.port_b_address_clock = "clock1", + ram_block3a_14.port_b_address_width = 12, + ram_block3a_14.port_b_data_out_clear = "none", + ram_block3a_14.port_b_data_out_clock = "none", + ram_block3a_14.port_b_data_width = 1, + ram_block3a_14.port_b_first_address = 0, + ram_block3a_14.port_b_first_bit_number = 14, + ram_block3a_14.port_b_last_address = 4095, + ram_block3a_14.port_b_logical_ram_depth = 4096, + ram_block3a_14.port_b_logical_ram_width = 16, + ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_14.ram_block_type = "auto", + ram_block3a_14.lpm_type = "cyclone_ram_block"; + cyclone_ram_block ram_block3a_15 + ( + .clk0(clock0), + .clk1(clock1), + .ena0(wren_a), + .ena1(clocken1), + .portaaddr({address_a_wire[11:0]}), + .portadatain({data_a[15]}), + .portadataout(), + .portawe(1'b1), + .portbaddr({address_b_wire[11:0]}), + .portbdataout(wire_ram_block3a_15portbdataout[0:0]), + .portbrewe(1'b1) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .clr0(1'b0), + .clr1(1'b0), + .portabyteenamasks(1'b1), + .portbbyteenamasks(1'b1), + .portbdatain(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + ram_block3a_15.connectivity_checking = "OFF", + ram_block3a_15.logical_ram_name = "ALTSYNCRAM", + ram_block3a_15.mixed_port_feed_through_mode = "dont_care", + ram_block3a_15.operation_mode = "dual_port", + ram_block3a_15.port_a_address_width = 12, + ram_block3a_15.port_a_data_width = 1, + ram_block3a_15.port_a_first_address = 0, + ram_block3a_15.port_a_first_bit_number = 15, + ram_block3a_15.port_a_last_address = 4095, + ram_block3a_15.port_a_logical_ram_depth = 4096, + ram_block3a_15.port_a_logical_ram_width = 16, + ram_block3a_15.port_b_address_clear = "none", + ram_block3a_15.port_b_address_clock = "clock1", + ram_block3a_15.port_b_address_width = 12, + ram_block3a_15.port_b_data_out_clear = "none", + ram_block3a_15.port_b_data_out_clock = "none", + ram_block3a_15.port_b_data_width = 1, + ram_block3a_15.port_b_first_address = 0, + ram_block3a_15.port_b_first_bit_number = 15, + ram_block3a_15.port_b_last_address = 4095, + ram_block3a_15.port_b_logical_ram_depth = 4096, + ram_block3a_15.port_b_logical_ram_width = 16, + ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", + ram_block3a_15.ram_block_type = "auto", + ram_block3a_15.lpm_type = "cyclone_ram_block"; + assign + address_a_wire = address_a, + address_b_wire = address_b, + q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; +endmodule //fifo_4k_altsyncram_8pl + + +//dffpipe DELAY=1 WIDTH=12 clock clrn d q +//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_dffpipe_bb3 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; + input clock; + input clrn; + input [11:0] d; + output [11:0] q; + + wire [11:0] wire_dffe4a_D; + reg [11:0] dffe4a; + wire ena; + wire prn; + wire sclr; + + // synopsys translate_off + initial + dffe4a[0:0] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[0:0] <= 1'b1; + else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; + else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; + // synopsys translate_off + initial + dffe4a[1:1] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[1:1] <= 1'b1; + else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; + else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; + // synopsys translate_off + initial + dffe4a[2:2] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[2:2] <= 1'b1; + else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; + else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; + // synopsys translate_off + initial + dffe4a[3:3] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[3:3] <= 1'b1; + else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; + else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; + // synopsys translate_off + initial + dffe4a[4:4] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[4:4] <= 1'b1; + else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; + else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; + // synopsys translate_off + initial + dffe4a[5:5] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[5:5] <= 1'b1; + else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; + else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; + // synopsys translate_off + initial + dffe4a[6:6] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[6:6] <= 1'b1; + else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; + else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; + // synopsys translate_off + initial + dffe4a[7:7] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[7:7] <= 1'b1; + else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; + else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; + // synopsys translate_off + initial + dffe4a[8:8] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[8:8] <= 1'b1; + else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; + else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; + // synopsys translate_off + initial + dffe4a[9:9] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[9:9] <= 1'b1; + else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; + else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; + // synopsys translate_off + initial + dffe4a[10:10] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[10:10] <= 1'b1; + else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; + else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; + // synopsys translate_off + initial + dffe4a[11:11] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe4a[11:11] <= 1'b1; + else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0; + else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11]; + assign + wire_dffe4a_D = (d & {12{(~ sclr)}}); + assign + ena = 1'b1, + prn = 1'b1, + q = dffe4a, + sclr = 1'b0; +endmodule //fifo_4k_dffpipe_bb3 + + +//dffpipe WIDTH=12 clock clrn d q +//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + + +//dffpipe WIDTH=12 clock clrn d q +//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_dffpipe_em2 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; + input clock; + input clrn; + input [11:0] d; + output [11:0] q; + + wire [11:0] wire_dffe6a_D; + reg [11:0] dffe6a; + wire ena; + wire prn; + wire sclr; + + // synopsys translate_off + initial + dffe6a[0:0] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[0:0] <= 1'b1; + else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; + else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; + // synopsys translate_off + initial + dffe6a[1:1] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[1:1] <= 1'b1; + else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; + else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; + // synopsys translate_off + initial + dffe6a[2:2] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[2:2] <= 1'b1; + else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; + else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; + // synopsys translate_off + initial + dffe6a[3:3] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[3:3] <= 1'b1; + else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; + else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; + // synopsys translate_off + initial + dffe6a[4:4] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[4:4] <= 1'b1; + else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; + else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; + // synopsys translate_off + initial + dffe6a[5:5] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[5:5] <= 1'b1; + else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; + else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; + // synopsys translate_off + initial + dffe6a[6:6] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[6:6] <= 1'b1; + else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; + else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; + // synopsys translate_off + initial + dffe6a[7:7] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[7:7] <= 1'b1; + else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; + else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; + // synopsys translate_off + initial + dffe6a[8:8] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[8:8] <= 1'b1; + else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; + else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; + // synopsys translate_off + initial + dffe6a[9:9] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[9:9] <= 1'b1; + else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; + else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; + // synopsys translate_off + initial + dffe6a[10:10] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[10:10] <= 1'b1; + else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; + else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; + // synopsys translate_off + initial + dffe6a[11:11] = 0; + // synopsys translate_on + always @ ( posedge clock or negedge prn or negedge clrn) + if (prn == 1'b0) dffe6a[11:11] <= 1'b1; + else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0; + else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11]; + assign + wire_dffe6a_D = (d & {12{(~ sclr)}}); + assign + ena = 1'b1, + prn = 1'b1, + q = dffe6a, + sclr = 1'b0; +endmodule //fifo_4k_dffpipe_em2 + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_alt_synch_pipe_em2 + ( + clock, + clrn, + d, + q) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; + input clock; + input clrn; + input [11:0] d; + output [11:0] q; + + wire [11:0] wire_dffpipe5_q; + + fifo_4k_dffpipe_em2 dffpipe5 + ( + .clock(clock), + .clrn(clrn), + .d(d), + .q(wire_dffpipe5_q)); + assign + q = wire_dffpipe5_q; +endmodule //fifo_4k_alt_synch_pipe_em2 + + +//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 12 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_add_sub_b18 + ( + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input [11:0] dataa; + input [11:0] datab; + output [11:0] result; + + wire [11:0] wire_add_sub_cella_combout; + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [0:0] wire_add_sub_cella_7cout; + wire [0:0] wire_add_sub_cella_8cout; + wire [0:0] wire_add_sub_cella_9cout; + wire [0:0] wire_add_sub_cella_10cout; + wire [11:0] wire_add_sub_cella_dataa; + wire [11:0] wire_add_sub_cella_datab; + + cyclone_lcell add_sub_cella_0 + ( + .cin(1'b1), + .combout(wire_add_sub_cella_combout[0:0]), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "69b2", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_1 + ( + .cin(wire_add_sub_cella_0cout[0:0]), + .combout(wire_add_sub_cella_combout[1:1]), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "69b2", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_2 + ( + .cin(wire_add_sub_cella_1cout[0:0]), + .combout(wire_add_sub_cella_combout[2:2]), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "69b2", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_3 + ( + .cin(wire_add_sub_cella_2cout[0:0]), + .combout(wire_add_sub_cella_combout[3:3]), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "69b2", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_4 + ( + .cin(wire_add_sub_cella_3cout[0:0]), + .combout(wire_add_sub_cella_combout[4:4]), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "69b2", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_5 + ( + .cin(wire_add_sub_cella_4cout[0:0]), + .combout(wire_add_sub_cella_combout[5:5]), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "69b2", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_6 + ( + .cin(wire_add_sub_cella_5cout[0:0]), + .combout(wire_add_sub_cella_combout[6:6]), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "69b2", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_7 + ( + .cin(wire_add_sub_cella_6cout[0:0]), + .combout(wire_add_sub_cella_combout[7:7]), + .cout(wire_add_sub_cella_7cout[0:0]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "69b2", + add_sub_cella_7.operation_mode = "arithmetic", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_8 + ( + .cin(wire_add_sub_cella_7cout[0:0]), + .combout(wire_add_sub_cella_combout[8:8]), + .cout(wire_add_sub_cella_8cout[0:0]), + .dataa(wire_add_sub_cella_dataa[8:8]), + .datab(wire_add_sub_cella_datab[8:8]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_8.cin_used = "true", + add_sub_cella_8.lut_mask = "69b2", + add_sub_cella_8.operation_mode = "arithmetic", + add_sub_cella_8.sum_lutc_input = "cin", + add_sub_cella_8.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_9 + ( + .cin(wire_add_sub_cella_8cout[0:0]), + .combout(wire_add_sub_cella_combout[9:9]), + .cout(wire_add_sub_cella_9cout[0:0]), + .dataa(wire_add_sub_cella_dataa[9:9]), + .datab(wire_add_sub_cella_datab[9:9]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_9.cin_used = "true", + add_sub_cella_9.lut_mask = "69b2", + add_sub_cella_9.operation_mode = "arithmetic", + add_sub_cella_9.sum_lutc_input = "cin", + add_sub_cella_9.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_10 + ( + .cin(wire_add_sub_cella_9cout[0:0]), + .combout(wire_add_sub_cella_combout[10:10]), + .cout(wire_add_sub_cella_10cout[0:0]), + .dataa(wire_add_sub_cella_dataa[10:10]), + .datab(wire_add_sub_cella_datab[10:10]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_10.cin_used = "true", + add_sub_cella_10.lut_mask = "69b2", + add_sub_cella_10.operation_mode = "arithmetic", + add_sub_cella_10.sum_lutc_input = "cin", + add_sub_cella_10.lpm_type = "cyclone_lcell"; + cyclone_lcell add_sub_cella_11 + ( + .cin(wire_add_sub_cella_10cout[0:0]), + .combout(wire_add_sub_cella_combout[11:11]), + .cout(), + .dataa(wire_add_sub_cella_dataa[11:11]), + .datab(wire_add_sub_cella_datab[11:11]), + .regout() + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_off + `endif + , + .aclr(1'b0), + .aload(1'b0), + .clk(1'b1), + .datac(1'b1), + .datad(1'b1), + .ena(1'b1), + .inverta(1'b0), + .regcascin(1'b0), + .sclr(1'b0), + .sload(1'b0) + `ifdef FORMAL_VERIFICATION + `else + // synopsys translate_on + `endif + // synopsys translate_off + , + .cin0(), + .cin1(), + .cout0(), + .cout1(), + .devclrn(), + .devpor() + // synopsys translate_on + ); + defparam + add_sub_cella_11.cin_used = "true", + add_sub_cella_11.lut_mask = "6969", + add_sub_cella_11.operation_mode = "normal", + add_sub_cella_11.sum_lutc_input = "cin", + add_sub_cella_11.lpm_type = "cyclone_lcell"; + assign + wire_add_sub_cella_dataa = dataa, + wire_add_sub_cella_datab = datab; + assign + result = wire_add_sub_cella_combout; +endmodule //fifo_4k_add_sub_b18 + + +//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + + +//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab +//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END + +//synthesis_resources = lut 104 M4K 16 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module fifo_4k_dcfifo_6cq + ( + aclr, + data, + q, + rdclk, + rdempty, + rdreq, + rdusedw, + wrclk, + wrfull, + wrreq, + wrusedw) /* synthesis synthesis_clearbox=1 */ + /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; + input aclr; + input [15:0] data; + output [15:0] q; + input rdclk; + output rdempty; + input rdreq; + output [11:0] rdusedw; + input wrclk; + output wrfull; + input wrreq; + output [11:0] wrusedw; + + wire [11:0] wire_rdptr_g_gray2bin_bin; + wire [11:0] wire_rs_dgwp_gray2bin_bin; + wire [11:0] wire_wrptr_g_gray2bin_bin; + wire [11:0] wire_ws_dgrp_gray2bin_bin; + wire [11:0] wire_rdptr_g_q; + wire [11:0] wire_rdptr_g1p_q; + wire [11:0] wire_wrptr_g1p_q; + wire [15:0] wire_fifo_ram_q_b; + reg [11:0] delayed_wrptr_g; + reg [11:0] wrptr_g; + wire [11:0] wire_rs_brp_q; + wire [11:0] wire_rs_bwp_q; + wire [11:0] wire_rs_dgwp_q; + wire [11:0] wire_ws_brp_q; + wire [11:0] wire_ws_bwp_q; + wire [11:0] wire_ws_dgrp_q; + wire [11:0] wire_rdusedw_sub_result; + wire [11:0] wire_wrusedw_sub_result; + reg wire_rdempty_eq_comp_aeb_int; + wire wire_rdempty_eq_comp_aeb; + wire [11:0] wire_rdempty_eq_comp_dataa; + wire [11:0] wire_rdempty_eq_comp_datab; + reg wire_wrfull_eq_comp_aeb_int; + wire wire_wrfull_eq_comp_aeb; + wire [11:0] wire_wrfull_eq_comp_dataa; + wire [11:0] wire_wrfull_eq_comp_datab; + wire int_rdempty; + wire int_wrfull; + wire valid_rdreq; + wire valid_wrreq; + + fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin + ( + .bin(wire_rdptr_g_gray2bin_bin), + .gray(wire_rdptr_g_q)); + fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin + ( + .bin(wire_rs_dgwp_gray2bin_bin), + .gray(wire_rs_dgwp_q)); + fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin + ( + .bin(wire_wrptr_g_gray2bin_bin), + .gray(wrptr_g)); + fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin + ( + .bin(wire_ws_dgrp_gray2bin_bin), + .gray(wire_ws_dgrp_q)); + fifo_4k_a_graycounter_826 rdptr_g + ( + .aclr(aclr), + .clock(rdclk), + .cnt_en(valid_rdreq), + .q(wire_rdptr_g_q)); + fifo_4k_a_graycounter_3r6 rdptr_g1p + ( + .aclr(aclr), + .clock(rdclk), + .cnt_en(valid_rdreq), + .q(wire_rdptr_g1p_q)); + fifo_4k_a_graycounter_3r6 wrptr_g1p + ( + .aclr(aclr), + .clock(wrclk), + .cnt_en(valid_wrreq), + .q(wire_wrptr_g1p_q)); + fifo_4k_altsyncram_8pl fifo_ram + ( + .address_a(wrptr_g), + .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))), + .clock0(wrclk), + .clock1(rdclk), + .clocken1((valid_rdreq | int_rdempty)), + .data_a(data), + .q_b(wire_fifo_ram_q_b), + .wren_a(valid_wrreq)); + // synopsys translate_off + initial + delayed_wrptr_g = 0; + // synopsys translate_on + always @ ( posedge wrclk or posedge aclr) + if (aclr == 1'b1) delayed_wrptr_g <= 12'b0; + else delayed_wrptr_g <= wrptr_g; + // synopsys translate_off + initial + wrptr_g = 0; + // synopsys translate_on + always @ ( posedge wrclk or posedge aclr) + if (aclr == 1'b1) wrptr_g <= 12'b0; + else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; + fifo_4k_dffpipe_bb3 rs_brp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(wire_rdptr_g_gray2bin_bin), + .q(wire_rs_brp_q)); + fifo_4k_dffpipe_bb3 rs_bwp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(wire_rs_dgwp_gray2bin_bin), + .q(wire_rs_bwp_q)); + fifo_4k_alt_synch_pipe_em2 rs_dgwp + ( + .clock(rdclk), + .clrn((~ aclr)), + .d(delayed_wrptr_g), + .q(wire_rs_dgwp_q)); + fifo_4k_dffpipe_bb3 ws_brp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_ws_dgrp_gray2bin_bin), + .q(wire_ws_brp_q)); + fifo_4k_dffpipe_bb3 ws_bwp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_wrptr_g_gray2bin_bin), + .q(wire_ws_bwp_q)); + fifo_4k_alt_synch_pipe_em2 ws_dgrp + ( + .clock(wrclk), + .clrn((~ aclr)), + .d(wire_rdptr_g_q), + .q(wire_ws_dgrp_q)); + fifo_4k_add_sub_b18 rdusedw_sub + ( + .dataa(wire_rs_bwp_q), + .datab(wire_rs_brp_q), + .result(wire_rdusedw_sub_result)); + fifo_4k_add_sub_b18 wrusedw_sub + ( + .dataa(wire_ws_bwp_q), + .datab(wire_ws_brp_q), + .result(wire_wrusedw_sub_result)); + always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) + if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) + begin + wire_rdempty_eq_comp_aeb_int = 1'b1; + end + else + begin + wire_rdempty_eq_comp_aeb_int = 1'b0; + end + assign + wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; + assign + wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, + wire_rdempty_eq_comp_datab = wire_rdptr_g_q; + always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) + if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) + begin + wire_wrfull_eq_comp_aeb_int = 1'b1; + end + else + begin + wire_wrfull_eq_comp_aeb_int = 1'b0; + end + assign + wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; + assign + wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, + wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; + assign + int_rdempty = wire_rdempty_eq_comp_aeb, + int_wrfull = wire_wrfull_eq_comp_aeb, + q = wire_fifo_ram_q_b, + rdempty = int_rdempty, + rdusedw = wire_rdusedw_sub_result, + valid_rdreq = rdreq, + valid_wrreq = wrreq, + wrfull = int_wrfull, + wrusedw = wire_wrusedw_sub_result; +endmodule //fifo_4k_dcfifo_6cq +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_4k ( + data, + wrreq, + rdreq, + rdclk, + wrclk, + aclr, + q, + rdempty, + rdusedw, + wrfull, + wrusedw)/* synthesis synthesis_clearbox = 1 */; + + input [15:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + + wire sub_wire0; + wire [11:0] sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire [11:0] sub_wire4; + wire rdempty = sub_wire0; + wire [11:0] wrusedw = sub_wire1[11:0]; + wire wrfull = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire [11:0] rdusedw = sub_wire4[11:0]; + + fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE diff --git a/usrp1/megacells/fifo_4k_18.v b/usrp1/megacells/fifo_4k_18.v new file mode 100755 index 000000000..ad76121bb --- /dev/null +++ b/usrp1/megacells/fifo_4k_18.v @@ -0,0 +1,186 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4k_18.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2007 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_4k_18 ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdusedw, + wrfull, + wrusedw); + + input aclr; + input [17:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [17:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + + wire sub_wire0; + wire [11:0] sub_wire1; + wire sub_wire2; + wire [17:0] sub_wire3; + wire [11:0] sub_wire4; + wire rdempty = sub_wire0; + wire [11:0] wrusedw = sub_wire1[11:0]; + wire wrfull = sub_wire2; + wire [17:0] q = sub_wire3[17:0]; + wire [11:0] rdusedw = sub_wire4[11:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4) + // synopsys translate_off + , + .rdfull (), + .wrempty () + // synopsys translate_on + ); + defparam + dcfifo_component.add_ram_output_register = "OFF", + dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone", + dcfifo_component.lpm_numwords = 4096, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 18, + dcfifo_component.lpm_widthu = 12, + dcfifo_component.overflow_checking = "OFF", + dcfifo_component.underflow_checking = "OFF", + dcfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "18" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "18" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0] +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/usrp1/megacells/fifo_4k_bb.v b/usrp1/megacells/fifo_4k_bb.v new file mode 100644 index 000000000..fc4ca9797 --- /dev/null +++ b/usrp1/megacells/fifo_4k_bb.v @@ -0,0 +1,131 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4k.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_4k ( + data, + wrreq, + rdreq, + rdclk, + wrclk, + aclr, + q, + rdempty, + rdusedw, + wrfull, + wrusedw)/* synthesis synthesis_clearbox = 1 */; + + input [15:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE diff --git a/usrp1/megacells/fifo_4kx16_dc.bsf b/usrp1/megacells/fifo_4kx16_dc.bsf new file mode 100755 index 000000000..b80add8de --- /dev/null +++ b/usrp1/megacells/fifo_4kx16_dc.bsf @@ -0,0 +1,117 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 184) + (text "fifo_4kx16_dc" (rect 41 1 134 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 168 25 180)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 16 160)(line_width 1)) + ) + (port + (pt 160 40) + (output) + (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8))) + (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8))) + (line (pt 160 40)(pt 144 40)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "wrusedw[11..0]" (rect 0 0 92 14)(font "Arial" (font_size 8))) + (text "wrusedw[11..0]" (rect 63 66 132 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 3)) + ) + (port + (pt 160 96) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (port + (pt 160 120) + (output) + (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) + (text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8))) + (line (pt 160 120)(pt 144 120)(line_width 1)) + ) + (port + (pt 160 136) + (output) + (text "rdusedw[11..0]" (rect 0 0 87 14)(font "Arial" (font_size 8))) + (text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8))) + (line (pt 160 136)(pt 144 136)(line_width 3)) + ) + (drawing + (text "(ack)" (rect 51 99 72 111)(font "Arial" )) + (text "16 bits x 4096 words" (rect 58 156 144 168)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 168)(line_width 1)) + (line (pt 144 168)(pt 16 168)(line_width 1)) + (line (pt 16 168)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 148)(pt 144 148)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/usrp1/megacells/fifo_4kx16_dc.cmp b/usrp1/megacells/fifo_4kx16_dc.cmp new file mode 100755 index 000000000..356de4d62 --- /dev/null +++ b/usrp1/megacells/fifo_4kx16_dc.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_4kx16_dc + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + wrfull : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) + ); +end component; diff --git a/usrp1/megacells/fifo_4kx16_dc.inc b/usrp1/megacells/fifo_4kx16_dc.inc new file mode 100755 index 000000000..c14c01836 --- /dev/null +++ b/usrp1/megacells/fifo_4kx16_dc.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_4kx16_dc +( + aclr, + data[15..0], + rdclk, + rdreq, + wrclk, + wrreq +) + +RETURNS ( + q[15..0], + rdempty, + rdusedw[11..0], + wrfull, + wrusedw[11..0] +); diff --git a/usrp1/megacells/fifo_4kx16_dc.v b/usrp1/megacells/fifo_4kx16_dc.v new file mode 100755 index 000000000..1f09000e3 --- /dev/null +++ b/usrp1/megacells/fifo_4kx16_dc.v @@ -0,0 +1,178 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4kx16_dc.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_4kx16_dc ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdusedw, + wrfull, + wrusedw); + + input aclr; + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + + wire sub_wire0; + wire [11:0] sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire [11:0] sub_wire4; + wire rdempty = sub_wire0; + wire [11:0] wrusedw = sub_wire1[11:0]; + wire wrfull = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire [11:0] rdusedw = sub_wire4[11:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4) + // synopsys translate_off + , + .wrempty (), + .rdfull () + // synopsys translate_on + ); + defparam + dcfifo_component.add_ram_output_register = "OFF", + dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone", + dcfifo_component.lpm_numwords = 4096, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 16, + dcfifo_component.lpm_widthu = 12, + dcfifo_component.overflow_checking = "OFF", + dcfifo_component.underflow_checking = "OFF", + dcfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE diff --git a/usrp1/megacells/fifo_4kx16_dc_bb.v b/usrp1/megacells/fifo_4kx16_dc_bb.v new file mode 100755 index 000000000..91c3c322f --- /dev/null +++ b/usrp1/megacells/fifo_4kx16_dc_bb.v @@ -0,0 +1,130 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4kx16_dc.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_4kx16_dc ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdusedw, + wrfull, + wrusedw); + + input aclr; + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE diff --git a/usrp1/megacells/fifo_4kx16_dc_inst.v b/usrp1/megacells/fifo_4kx16_dc_inst.v new file mode 100755 index 000000000..566f27a17 --- /dev/null +++ b/usrp1/megacells/fifo_4kx16_dc_inst.v @@ -0,0 +1,13 @@ +fifo_4kx16_dc fifo_4kx16_dc_inst ( + .aclr ( aclr_sig ), + .data ( data_sig ), + .rdclk ( rdclk_sig ), + .rdreq ( rdreq_sig ), + .wrclk ( wrclk_sig ), + .wrreq ( wrreq_sig ), + .q ( q_sig ), + .rdempty ( rdempty_sig ), + .rdusedw ( rdusedw_sig ), + .wrfull ( wrfull_sig ), + .wrusedw ( wrusedw_sig ) + ); diff --git a/usrp1/megacells/mylpm_addsub.bsf b/usrp1/megacells/mylpm_addsub.bsf new file mode 100755 index 000000000..e5c1ded7f --- /dev/null +++ b/usrp1/megacells/mylpm_addsub.bsf @@ -0,0 +1,80 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 112) + (text "mylpm_addsub" (rect 26 2 145 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 93 30 108)(font "Arial" )) + (port + (pt 0 56) + (input) + (text "dataa[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) + (text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "datab[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) + (text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 64 88)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "clock" (rect 0 0 34 16)(font "Arial" (font_size 8))) + (text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 1)) + ) + (port + (pt 0 32) + (input) + (text "add_sub" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 80 32)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "result[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8))) + (text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 96 72)(line_width 3)) + ) + (drawing + (text "A" (rect 66 48 75 64)(font "Arial" (font_size 8))) + (text "B" (rect 66 80 75 96)(font "Arial" (font_size 8))) + (text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8))) + (line (pt 64 48)(pt 96 56)(line_width 1)) + (line (pt 96 56)(pt 96 88)(line_width 1)) + (line (pt 96 88)(pt 64 96)(line_width 1)) + (line (pt 64 96)(pt 64 48)(line_width 1)) + (line (pt 80 32)(pt 80 52)(line_width 1)) + (line (pt 106 40)(pt 125 40)(line_width 1)) + (line (pt 64 66)(pt 70 72)(line_width 1)) + (line (pt 70 72)(pt 64 78)(line_width 1)) + ) +) diff --git a/usrp1/megacells/mylpm_addsub.cmp b/usrp1/megacells/mylpm_addsub.cmp new file mode 100755 index 000000000..311c54a5b --- /dev/null +++ b/usrp1/megacells/mylpm_addsub.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component mylpm_addsub + PORT + ( + add_sub : IN STD_LOGIC ; + dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + clock : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/usrp1/megacells/mylpm_addsub.inc b/usrp1/megacells/mylpm_addsub.inc new file mode 100755 index 000000000..d8b283f49 --- /dev/null +++ b/usrp1/megacells/mylpm_addsub.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION mylpm_addsub +( + add_sub, + dataa[15..0], + datab[15..0], + clock +) + +RETURNS ( + result[15..0] +); diff --git a/usrp1/megacells/mylpm_addsub.v b/usrp1/megacells/mylpm_addsub.v new file mode 100755 index 000000000..0566f7e57 --- /dev/null +++ b/usrp1/megacells/mylpm_addsub.v @@ -0,0 +1,102 @@ +// megafunction wizard: %LPM_ADD_SUB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_add_sub + +// ============================================================ +// File Name: mylpm_addsub.v +// Megafunction Name(s): +// lpm_add_sub +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +module mylpm_addsub ( + add_sub, + dataa, + datab, + clock, + result); + + input add_sub; + input [15:0] dataa; + input [15:0] datab; + input clock; + output [15:0] result; + + wire [15:0] sub_wire0; + wire [15:0] result = sub_wire0[15:0]; + + lpm_add_sub lpm_add_sub_component ( + .dataa (dataa), + .add_sub (add_sub), + .datab (datab), + .clock (clock), + .result (sub_wire0)); + defparam + lpm_add_sub_component.lpm_width = 16, + lpm_add_sub_component.lpm_direction = "UNUSED", + lpm_add_sub_component.lpm_type = "LPM_ADD_SUB", + lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO", + lpm_add_sub_component.lpm_pipeline = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "16" +// Retrieval info: PRIVATE: Function NUMERIC "2" +// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantA NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Overflow NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "1" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub +// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] +// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0] +// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0] +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0 +// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 +// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0 +// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/usrp1/megacells/mylpm_addsub_bb.v b/usrp1/megacells/mylpm_addsub_bb.v new file mode 100755 index 000000000..598d3da52 --- /dev/null +++ b/usrp1/megacells/mylpm_addsub_bb.v @@ -0,0 +1,35 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module mylpm_addsub ( + add_sub, + dataa, + datab, + clock, + result); + + input add_sub; + input [15:0] dataa; + input [15:0] datab; + input clock; + output [15:0] result; + +endmodule + diff --git a/usrp1/megacells/mylpm_addsub_inst.v b/usrp1/megacells/mylpm_addsub_inst.v new file mode 100755 index 000000000..dd732bd6d --- /dev/null +++ b/usrp1/megacells/mylpm_addsub_inst.v @@ -0,0 +1,7 @@ +mylpm_addsub mylpm_addsub_inst ( + .add_sub ( add_sub_sig ), + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .clock ( clock_sig ), + .result ( result_sig ) + ); diff --git a/usrp1/megacells/pll.v b/usrp1/megacells/pll.v new file mode 100644 index 000000000..dacd11f23 --- /dev/null +++ b/usrp1/megacells/pll.v @@ -0,0 +1,207 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [5:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0) + // synopsys translate_off +, + .fbin (), + .pllena (), + .clkswitch (), + .areset (), + .pfdena (), + .clkena (), + .extclkena (), + .scanclk (), + .scanaclr (), + .scandata (), + .scanread (), + .scanwrite (), + .extclk (), + .clkbad (), + .activeclock (), + .locked (), + .clkloss (), + .scandataout (), + .scandone (), + .sclkout1 (), + .sclkout0 (), + .enable0 (), + .enable1 () + // synopsys translate_on + +); + defparam + altpll_component.clk0_duty_cycle = 50, + altpll_component.lpm_type = "altpll", + altpll_component.clk0_multiply_by = 1, + altpll_component.inclk0_input_frequency = 20833, + altpll_component.clk0_divide_by = 1, + altpll_component.pll_type = "AUTO", + altpll_component.clk0_time_delay = "0", + altpll_component.intended_device_family = "Cyclone", + altpll_component.operation_mode = "NORMAL", + altpll_component.compensate_clock = "CLK0", + altpll_component.clk0_phase_shift = "-3000"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" +// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE diff --git a/usrp1/megacells/pll_bb.v b/usrp1/megacells/pll_bb.v new file mode 100644 index 000000000..debadaa25 --- /dev/null +++ b/usrp1/megacells/pll_bb.v @@ -0,0 +1,29 @@ +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module pll ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + diff --git a/usrp1/megacells/pll_inst.v b/usrp1/megacells/pll_inst.v new file mode 100644 index 000000000..97db58ba0 --- /dev/null +++ b/usrp1/megacells/pll_inst.v @@ -0,0 +1,4 @@ +pll pll_inst ( + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ) + ); diff --git a/usrp1/megacells/sub32.bsf b/usrp1/megacells/sub32.bsf new file mode 100755 index 000000000..753fdc738 --- /dev/null +++ b/usrp1/megacells/sub32.bsf @@ -0,0 +1,87 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2003 Altera Corporation +Any megafunction design, and related netlist (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only +to program PLD devices (but not masked PLD devices) from Altera. Any +other use of such megafunction design, netlist, support information, +device programming or simulation file, or any other related documentation +or information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to the +intellectual property, including patents, copyrights, trademarks, trade +secrets, or maskworks, embodied in any such megafunction design, netlist, +support information, device programming or simulation file, or any other +related documentation or information provided by Altera or a megafunction +partner, remains with Altera, the megafunction partner, or their respective +licensors. No other licenses, including any licenses needed under any third +party's intellectual property, are provided herein. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 128) + (text "sub32" (rect 58 2 109 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 109 31 124)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "dataa[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "dataa[31..0]" (rect 4 24 73 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 64 40)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "datab[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "datab[31..0]" (rect 4 56 73 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 4 40 35 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clken" (rect 4 80 35 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 74 96)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) + (text "aclr" (rect 4 96 25 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 85 112)(line_width 1)) + ) + (port + (pt 160 56) + (output) + (text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "result[31..0]" (rect 88 40 157 56)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 96 56)(line_width 3)) + ) + (drawing + (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8))) + (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8))) + (text "A-B" (rect 72 48 94 64)(font "Arial" (font_size 8))) + (line (pt 64 32)(pt 96 40)(line_width 1)) + (line (pt 96 40)(pt 96 72)(line_width 1)) + (line (pt 96 72)(pt 64 80)(line_width 1)) + (line (pt 64 80)(pt 64 32)(line_width 1)) + (line (pt 74 96)(pt 74 77)(line_width 1)) + (line (pt 85 112)(pt 85 74)(line_width 1)) + (line (pt 64 50)(pt 70 56)(line_width 1)) + (line (pt 70 56)(pt 64 62)(line_width 1)) + ) +) diff --git a/usrp1/megacells/sub32.cmp b/usrp1/megacells/sub32.cmp new file mode 100755 index 000000000..0d5b62ef9 --- /dev/null +++ b/usrp1/megacells/sub32.cmp @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +component sub32 + PORT + ( + dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + clock : IN STD_LOGIC ; + aclr : IN STD_LOGIC ; + clken : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/usrp1/megacells/sub32.inc b/usrp1/megacells/sub32.inc new file mode 100755 index 000000000..3c64e21c5 --- /dev/null +++ b/usrp1/megacells/sub32.inc @@ -0,0 +1,33 @@ +--Copyright (C) 1991-2003 Altera Corporation +--Any megafunction design, and related netlist (encrypted or decrypted), +--support information, device programming or simulation file, and any other +--associated documentation or information provided by Altera or a partner +--under Altera's Megafunction Partnership Program may be used only +--to program PLD devices (but not masked PLD devices) from Altera. Any +--other use of such megafunction design, netlist, support information, +--device programming or simulation file, or any other related documentation +--or information is prohibited for any other purpose, including, but not +--limited to modification, reverse engineering, de-compiling, or use with +--any other silicon devices, unless such use is explicitly licensed under +--a separate agreement with Altera or a megafunction partner. Title to the +--intellectual property, including patents, copyrights, trademarks, trade +--secrets, or maskworks, embodied in any such megafunction design, netlist, +--support information, device programming or simulation file, or any other +--related documentation or information provided by Altera or a megafunction +--partner, remains with Altera, the megafunction partner, or their respective +--licensors. No other licenses, including any licenses needed under any third +--party's intellectual property, are provided herein. + + +FUNCTION sub32 +( + dataa[31..0], + datab[31..0], + clock, + aclr, + clken +) + +RETURNS ( + result[31..0] +); diff --git a/usrp1/megacells/sub32.v b/usrp1/megacells/sub32.v new file mode 100755 index 000000000..dd825d91a --- /dev/null +++ b/usrp1/megacells/sub32.v @@ -0,0 +1,675 @@ +// megafunction wizard: %LPM_ADD_SUB%CBX% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_add_sub + +// ============================================================ +// File Name: sub32.v +// Megafunction Name(s): +// lpm_add_sub +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// ************************************************************ + + +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + + +//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result +//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END + +//synthesis_resources = lut 32 +module sub32_add_sub_cqa + ( + aclr, + clken, + clock, + dataa, + datab, + result) /* synthesis synthesis_clearbox=1 */; + input aclr; + input clken; + input clock; + input [31:0] dataa; + input [31:0] datab; + output [31:0] result; + + wire [0:0] wire_add_sub_cella_0cout; + wire [0:0] wire_add_sub_cella_1cout; + wire [0:0] wire_add_sub_cella_2cout; + wire [0:0] wire_add_sub_cella_3cout; + wire [0:0] wire_add_sub_cella_4cout; + wire [0:0] wire_add_sub_cella_5cout; + wire [0:0] wire_add_sub_cella_6cout; + wire [0:0] wire_add_sub_cella_7cout; + wire [0:0] wire_add_sub_cella_8cout; + wire [0:0] wire_add_sub_cella_9cout; + wire [0:0] wire_add_sub_cella_10cout; + wire [0:0] wire_add_sub_cella_11cout; + wire [0:0] wire_add_sub_cella_12cout; + wire [0:0] wire_add_sub_cella_13cout; + wire [0:0] wire_add_sub_cella_14cout; + wire [0:0] wire_add_sub_cella_15cout; + wire [0:0] wire_add_sub_cella_16cout; + wire [0:0] wire_add_sub_cella_17cout; + wire [0:0] wire_add_sub_cella_18cout; + wire [0:0] wire_add_sub_cella_19cout; + wire [0:0] wire_add_sub_cella_20cout; + wire [0:0] wire_add_sub_cella_21cout; + wire [0:0] wire_add_sub_cella_22cout; + wire [0:0] wire_add_sub_cella_23cout; + wire [0:0] wire_add_sub_cella_24cout; + wire [0:0] wire_add_sub_cella_25cout; + wire [0:0] wire_add_sub_cella_26cout; + wire [0:0] wire_add_sub_cella_27cout; + wire [0:0] wire_add_sub_cella_28cout; + wire [0:0] wire_add_sub_cella_29cout; + wire [0:0] wire_add_sub_cella_30cout; + wire [31:0] wire_add_sub_cella_dataa; + wire [31:0] wire_add_sub_cella_datab; + wire [31:0] wire_add_sub_cella_regout; + + stratix_lcell add_sub_cella_0 + ( + .aclr(aclr), + .cin(1'b1), + .clk(clock), + .cout(wire_add_sub_cella_0cout[0:0]), + .dataa(wire_add_sub_cella_dataa[0:0]), + .datab(wire_add_sub_cella_datab[0:0]), + .ena(clken), + .regout(wire_add_sub_cella_regout[0:0])); + defparam + add_sub_cella_0.cin_used = "true", + add_sub_cella_0.lut_mask = "69b2", + add_sub_cella_0.operation_mode = "arithmetic", + add_sub_cella_0.sum_lutc_input = "cin", + add_sub_cella_0.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_1 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_0cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_1cout[0:0]), + .dataa(wire_add_sub_cella_dataa[1:1]), + .datab(wire_add_sub_cella_datab[1:1]), + .ena(clken), + .regout(wire_add_sub_cella_regout[1:1])); + defparam + add_sub_cella_1.cin_used = "true", + add_sub_cella_1.lut_mask = "69b2", + add_sub_cella_1.operation_mode = "arithmetic", + add_sub_cella_1.sum_lutc_input = "cin", + add_sub_cella_1.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_2 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_1cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_2cout[0:0]), + .dataa(wire_add_sub_cella_dataa[2:2]), + .datab(wire_add_sub_cella_datab[2:2]), + .ena(clken), + .regout(wire_add_sub_cella_regout[2:2])); + defparam + add_sub_cella_2.cin_used = "true", + add_sub_cella_2.lut_mask = "69b2", + add_sub_cella_2.operation_mode = "arithmetic", + add_sub_cella_2.sum_lutc_input = "cin", + add_sub_cella_2.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_3 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_2cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_3cout[0:0]), + .dataa(wire_add_sub_cella_dataa[3:3]), + .datab(wire_add_sub_cella_datab[3:3]), + .ena(clken), + .regout(wire_add_sub_cella_regout[3:3])); + defparam + add_sub_cella_3.cin_used = "true", + add_sub_cella_3.lut_mask = "69b2", + add_sub_cella_3.operation_mode = "arithmetic", + add_sub_cella_3.sum_lutc_input = "cin", + add_sub_cella_3.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_4 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_3cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_4cout[0:0]), + .dataa(wire_add_sub_cella_dataa[4:4]), + .datab(wire_add_sub_cella_datab[4:4]), + .ena(clken), + .regout(wire_add_sub_cella_regout[4:4])); + defparam + add_sub_cella_4.cin_used = "true", + add_sub_cella_4.lut_mask = "69b2", + add_sub_cella_4.operation_mode = "arithmetic", + add_sub_cella_4.sum_lutc_input = "cin", + add_sub_cella_4.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_5 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_4cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_5cout[0:0]), + .dataa(wire_add_sub_cella_dataa[5:5]), + .datab(wire_add_sub_cella_datab[5:5]), + .ena(clken), + .regout(wire_add_sub_cella_regout[5:5])); + defparam + add_sub_cella_5.cin_used = "true", + add_sub_cella_5.lut_mask = "69b2", + add_sub_cella_5.operation_mode = "arithmetic", + add_sub_cella_5.sum_lutc_input = "cin", + add_sub_cella_5.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_6 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_5cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_6cout[0:0]), + .dataa(wire_add_sub_cella_dataa[6:6]), + .datab(wire_add_sub_cella_datab[6:6]), + .ena(clken), + .regout(wire_add_sub_cella_regout[6:6])); + defparam + add_sub_cella_6.cin_used = "true", + add_sub_cella_6.lut_mask = "69b2", + add_sub_cella_6.operation_mode = "arithmetic", + add_sub_cella_6.sum_lutc_input = "cin", + add_sub_cella_6.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_7 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_6cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_7cout[0:0]), + .dataa(wire_add_sub_cella_dataa[7:7]), + .datab(wire_add_sub_cella_datab[7:7]), + .ena(clken), + .regout(wire_add_sub_cella_regout[7:7])); + defparam + add_sub_cella_7.cin_used = "true", + add_sub_cella_7.lut_mask = "69b2", + add_sub_cella_7.operation_mode = "arithmetic", + add_sub_cella_7.sum_lutc_input = "cin", + add_sub_cella_7.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_8 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_7cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_8cout[0:0]), + .dataa(wire_add_sub_cella_dataa[8:8]), + .datab(wire_add_sub_cella_datab[8:8]), + .ena(clken), + .regout(wire_add_sub_cella_regout[8:8])); + defparam + add_sub_cella_8.cin_used = "true", + add_sub_cella_8.lut_mask = "69b2", + add_sub_cella_8.operation_mode = "arithmetic", + add_sub_cella_8.sum_lutc_input = "cin", + add_sub_cella_8.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_9 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_8cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_9cout[0:0]), + .dataa(wire_add_sub_cella_dataa[9:9]), + .datab(wire_add_sub_cella_datab[9:9]), + .ena(clken), + .regout(wire_add_sub_cella_regout[9:9])); + defparam + add_sub_cella_9.cin_used = "true", + add_sub_cella_9.lut_mask = "69b2", + add_sub_cella_9.operation_mode = "arithmetic", + add_sub_cella_9.sum_lutc_input = "cin", + add_sub_cella_9.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_10 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_9cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_10cout[0:0]), + .dataa(wire_add_sub_cella_dataa[10:10]), + .datab(wire_add_sub_cella_datab[10:10]), + .ena(clken), + .regout(wire_add_sub_cella_regout[10:10])); + defparam + add_sub_cella_10.cin_used = "true", + add_sub_cella_10.lut_mask = "69b2", + add_sub_cella_10.operation_mode = "arithmetic", + add_sub_cella_10.sum_lutc_input = "cin", + add_sub_cella_10.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_11 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_10cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_11cout[0:0]), + .dataa(wire_add_sub_cella_dataa[11:11]), + .datab(wire_add_sub_cella_datab[11:11]), + .ena(clken), + .regout(wire_add_sub_cella_regout[11:11])); + defparam + add_sub_cella_11.cin_used = "true", + add_sub_cella_11.lut_mask = "69b2", + add_sub_cella_11.operation_mode = "arithmetic", + add_sub_cella_11.sum_lutc_input = "cin", + add_sub_cella_11.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_12 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_11cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_12cout[0:0]), + .dataa(wire_add_sub_cella_dataa[12:12]), + .datab(wire_add_sub_cella_datab[12:12]), + .ena(clken), + .regout(wire_add_sub_cella_regout[12:12])); + defparam + add_sub_cella_12.cin_used = "true", + add_sub_cella_12.lut_mask = "69b2", + add_sub_cella_12.operation_mode = "arithmetic", + add_sub_cella_12.sum_lutc_input = "cin", + add_sub_cella_12.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_13 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_12cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_13cout[0:0]), + .dataa(wire_add_sub_cella_dataa[13:13]), + .datab(wire_add_sub_cella_datab[13:13]), + .ena(clken), + .regout(wire_add_sub_cella_regout[13:13])); + defparam + add_sub_cella_13.cin_used = "true", + add_sub_cella_13.lut_mask = "69b2", + add_sub_cella_13.operation_mode = "arithmetic", + add_sub_cella_13.sum_lutc_input = "cin", + add_sub_cella_13.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_14 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_13cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_14cout[0:0]), + .dataa(wire_add_sub_cella_dataa[14:14]), + .datab(wire_add_sub_cella_datab[14:14]), + .ena(clken), + .regout(wire_add_sub_cella_regout[14:14])); + defparam + add_sub_cella_14.cin_used = "true", + add_sub_cella_14.lut_mask = "69b2", + add_sub_cella_14.operation_mode = "arithmetic", + add_sub_cella_14.sum_lutc_input = "cin", + add_sub_cella_14.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_15 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_14cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_15cout[0:0]), + .dataa(wire_add_sub_cella_dataa[15:15]), + .datab(wire_add_sub_cella_datab[15:15]), + .ena(clken), + .regout(wire_add_sub_cella_regout[15:15])); + defparam + add_sub_cella_15.cin_used = "true", + add_sub_cella_15.lut_mask = "69b2", + add_sub_cella_15.operation_mode = "arithmetic", + add_sub_cella_15.sum_lutc_input = "cin", + add_sub_cella_15.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_16 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_15cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_16cout[0:0]), + .dataa(wire_add_sub_cella_dataa[16:16]), + .datab(wire_add_sub_cella_datab[16:16]), + .ena(clken), + .regout(wire_add_sub_cella_regout[16:16])); + defparam + add_sub_cella_16.cin_used = "true", + add_sub_cella_16.lut_mask = "69b2", + add_sub_cella_16.operation_mode = "arithmetic", + add_sub_cella_16.sum_lutc_input = "cin", + add_sub_cella_16.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_17 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_16cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_17cout[0:0]), + .dataa(wire_add_sub_cella_dataa[17:17]), + .datab(wire_add_sub_cella_datab[17:17]), + .ena(clken), + .regout(wire_add_sub_cella_regout[17:17])); + defparam + add_sub_cella_17.cin_used = "true", + add_sub_cella_17.lut_mask = "69b2", + add_sub_cella_17.operation_mode = "arithmetic", + add_sub_cella_17.sum_lutc_input = "cin", + add_sub_cella_17.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_18 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_17cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_18cout[0:0]), + .dataa(wire_add_sub_cella_dataa[18:18]), + .datab(wire_add_sub_cella_datab[18:18]), + .ena(clken), + .regout(wire_add_sub_cella_regout[18:18])); + defparam + add_sub_cella_18.cin_used = "true", + add_sub_cella_18.lut_mask = "69b2", + add_sub_cella_18.operation_mode = "arithmetic", + add_sub_cella_18.sum_lutc_input = "cin", + add_sub_cella_18.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_19 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_18cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_19cout[0:0]), + .dataa(wire_add_sub_cella_dataa[19:19]), + .datab(wire_add_sub_cella_datab[19:19]), + .ena(clken), + .regout(wire_add_sub_cella_regout[19:19])); + defparam + add_sub_cella_19.cin_used = "true", + add_sub_cella_19.lut_mask = "69b2", + add_sub_cella_19.operation_mode = "arithmetic", + add_sub_cella_19.sum_lutc_input = "cin", + add_sub_cella_19.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_20 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_19cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_20cout[0:0]), + .dataa(wire_add_sub_cella_dataa[20:20]), + .datab(wire_add_sub_cella_datab[20:20]), + .ena(clken), + .regout(wire_add_sub_cella_regout[20:20])); + defparam + add_sub_cella_20.cin_used = "true", + add_sub_cella_20.lut_mask = "69b2", + add_sub_cella_20.operation_mode = "arithmetic", + add_sub_cella_20.sum_lutc_input = "cin", + add_sub_cella_20.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_21 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_20cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_21cout[0:0]), + .dataa(wire_add_sub_cella_dataa[21:21]), + .datab(wire_add_sub_cella_datab[21:21]), + .ena(clken), + .regout(wire_add_sub_cella_regout[21:21])); + defparam + add_sub_cella_21.cin_used = "true", + add_sub_cella_21.lut_mask = "69b2", + add_sub_cella_21.operation_mode = "arithmetic", + add_sub_cella_21.sum_lutc_input = "cin", + add_sub_cella_21.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_22 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_21cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_22cout[0:0]), + .dataa(wire_add_sub_cella_dataa[22:22]), + .datab(wire_add_sub_cella_datab[22:22]), + .ena(clken), + .regout(wire_add_sub_cella_regout[22:22])); + defparam + add_sub_cella_22.cin_used = "true", + add_sub_cella_22.lut_mask = "69b2", + add_sub_cella_22.operation_mode = "arithmetic", + add_sub_cella_22.sum_lutc_input = "cin", + add_sub_cella_22.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_23 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_22cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_23cout[0:0]), + .dataa(wire_add_sub_cella_dataa[23:23]), + .datab(wire_add_sub_cella_datab[23:23]), + .ena(clken), + .regout(wire_add_sub_cella_regout[23:23])); + defparam + add_sub_cella_23.cin_used = "true", + add_sub_cella_23.lut_mask = "69b2", + add_sub_cella_23.operation_mode = "arithmetic", + add_sub_cella_23.sum_lutc_input = "cin", + add_sub_cella_23.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_24 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_23cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_24cout[0:0]), + .dataa(wire_add_sub_cella_dataa[24:24]), + .datab(wire_add_sub_cella_datab[24:24]), + .ena(clken), + .regout(wire_add_sub_cella_regout[24:24])); + defparam + add_sub_cella_24.cin_used = "true", + add_sub_cella_24.lut_mask = "69b2", + add_sub_cella_24.operation_mode = "arithmetic", + add_sub_cella_24.sum_lutc_input = "cin", + add_sub_cella_24.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_25 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_24cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_25cout[0:0]), + .dataa(wire_add_sub_cella_dataa[25:25]), + .datab(wire_add_sub_cella_datab[25:25]), + .ena(clken), + .regout(wire_add_sub_cella_regout[25:25])); + defparam + add_sub_cella_25.cin_used = "true", + add_sub_cella_25.lut_mask = "69b2", + add_sub_cella_25.operation_mode = "arithmetic", + add_sub_cella_25.sum_lutc_input = "cin", + add_sub_cella_25.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_26 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_25cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_26cout[0:0]), + .dataa(wire_add_sub_cella_dataa[26:26]), + .datab(wire_add_sub_cella_datab[26:26]), + .ena(clken), + .regout(wire_add_sub_cella_regout[26:26])); + defparam + add_sub_cella_26.cin_used = "true", + add_sub_cella_26.lut_mask = "69b2", + add_sub_cella_26.operation_mode = "arithmetic", + add_sub_cella_26.sum_lutc_input = "cin", + add_sub_cella_26.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_27 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_26cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_27cout[0:0]), + .dataa(wire_add_sub_cella_dataa[27:27]), + .datab(wire_add_sub_cella_datab[27:27]), + .ena(clken), + .regout(wire_add_sub_cella_regout[27:27])); + defparam + add_sub_cella_27.cin_used = "true", + add_sub_cella_27.lut_mask = "69b2", + add_sub_cella_27.operation_mode = "arithmetic", + add_sub_cella_27.sum_lutc_input = "cin", + add_sub_cella_27.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_28 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_27cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_28cout[0:0]), + .dataa(wire_add_sub_cella_dataa[28:28]), + .datab(wire_add_sub_cella_datab[28:28]), + .ena(clken), + .regout(wire_add_sub_cella_regout[28:28])); + defparam + add_sub_cella_28.cin_used = "true", + add_sub_cella_28.lut_mask = "69b2", + add_sub_cella_28.operation_mode = "arithmetic", + add_sub_cella_28.sum_lutc_input = "cin", + add_sub_cella_28.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_29 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_28cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_29cout[0:0]), + .dataa(wire_add_sub_cella_dataa[29:29]), + .datab(wire_add_sub_cella_datab[29:29]), + .ena(clken), + .regout(wire_add_sub_cella_regout[29:29])); + defparam + add_sub_cella_29.cin_used = "true", + add_sub_cella_29.lut_mask = "69b2", + add_sub_cella_29.operation_mode = "arithmetic", + add_sub_cella_29.sum_lutc_input = "cin", + add_sub_cella_29.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_30 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_29cout[0:0]), + .clk(clock), + .cout(wire_add_sub_cella_30cout[0:0]), + .dataa(wire_add_sub_cella_dataa[30:30]), + .datab(wire_add_sub_cella_datab[30:30]), + .ena(clken), + .regout(wire_add_sub_cella_regout[30:30])); + defparam + add_sub_cella_30.cin_used = "true", + add_sub_cella_30.lut_mask = "69b2", + add_sub_cella_30.operation_mode = "arithmetic", + add_sub_cella_30.sum_lutc_input = "cin", + add_sub_cella_30.lpm_type = "stratix_lcell"; + stratix_lcell add_sub_cella_31 + ( + .aclr(aclr), + .cin(wire_add_sub_cella_30cout[0:0]), + .clk(clock), + .dataa(wire_add_sub_cella_dataa[31:31]), + .datab(wire_add_sub_cella_datab[31:31]), + .ena(clken), + .regout(wire_add_sub_cella_regout[31:31])); + defparam + add_sub_cella_31.cin_used = "true", + add_sub_cella_31.lut_mask = "6969", + add_sub_cella_31.operation_mode = "normal", + add_sub_cella_31.sum_lutc_input = "cin", + add_sub_cella_31.lpm_type = "stratix_lcell"; + assign + wire_add_sub_cella_dataa = dataa, + wire_add_sub_cella_datab = datab; + assign + result = wire_add_sub_cella_regout; +endmodule //sub32_add_sub_cqa +//VALID FILE + + +module sub32 ( + dataa, + datab, + clock, + aclr, + clken, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] dataa; + input [31:0] datab; + input clock; + input aclr; + input clken; + output [31:0] result; + + wire [31:0] sub_wire0; + wire [31:0] result = sub_wire0[31:0]; + + sub32_add_sub_cqa sub32_add_sub_cqa_component ( + .dataa (dataa), + .datab (datab), + .clken (clken), + .aclr (aclr), + .clock (clock), + .result (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: nBit NUMERIC "32" +// Retrieval info: PRIVATE: Function NUMERIC "1" +// Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantA NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +// Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Overflow NUMERIC "0" +// Retrieval info: PRIVATE: Latency NUMERIC "1" +// Retrieval info: PRIVATE: aclr NUMERIC "1" +// Retrieval info: PRIVATE: clken NUMERIC "1" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] +// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0] +// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0] +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken +// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 +// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0 +// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all diff --git a/usrp1/megacells/sub32_bb.v b/usrp1/megacells/sub32_bb.v new file mode 100755 index 000000000..488ab51cf --- /dev/null +++ b/usrp1/megacells/sub32_bb.v @@ -0,0 +1,37 @@ +//Copyright (C) 1991-2003 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module sub32 ( + dataa, + datab, + clock, + aclr, + clken, + result)/* synthesis synthesis_clearbox = 1 */; + + input [31:0] dataa; + input [31:0] datab; + input clock; + input aclr; + input clken; + output [31:0] result; + +endmodule + diff --git a/usrp1/megacells/sub32_inst.v b/usrp1/megacells/sub32_inst.v new file mode 100755 index 000000000..1916fc524 --- /dev/null +++ b/usrp1/megacells/sub32_inst.v @@ -0,0 +1,8 @@ +sub32 sub32_inst ( + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .clock ( clock_sig ), + .aclr ( aclr_sig ), + .clken ( clken_sig ), + .result ( result_sig ) + ); diff --git a/usrp1/models/bustri.v b/usrp1/models/bustri.v new file mode 100644 index 000000000..6e5a0f74c --- /dev/null +++ b/usrp1/models/bustri.v @@ -0,0 +1,17 @@ + +// Model for tristate bus on altera +// FIXME do we really need to use a megacell for this? + +module bustri (data, + enabledt, + tridata); + + input [15:0] data; + input enabledt; + inout [15:0] tridata; + + assign tridata = enabledt ? data :16'bz; + +endmodule // bustri + + diff --git a/usrp1/models/fifo.v b/usrp1/models/fifo.v new file mode 100644 index 000000000..0ade49e9c --- /dev/null +++ b/usrp1/models/fifo.v @@ -0,0 +1,82 @@ +// Model of FIFO in Altera + +module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q, + rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); + + parameter width = 16; + parameter depth = 1024; + parameter addr_bits = 10; + + //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req + + input [width-1:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [width-1:0] q; + output rdfull; + output rdempty; + output reg [addr_bits-1:0] rdusedw; + output wrfull; + output wrempty; + output reg [addr_bits-1:0] wrusedw; + + reg [width-1:0] mem [0:depth-1]; + reg [addr_bits-1:0] rdptr; + reg [addr_bits-1:0] wrptr; + +`ifdef rd_req + reg [width-1:0] q; +`else + wire [width-1:0] q; +`endif + + integer i; + + always @( aclr) + begin + wrptr <= #1 0; + rdptr <= #1 0; + for(i=0;i=0;i=i-1) + bin_val[i] = bin_val[i+1] ^ gray_val[i]; + end +endmodule // gray2bin diff --git a/usrp1/sdr_lib/gen_cordic_consts.py b/usrp1/sdr_lib/gen_cordic_consts.py new file mode 100755 index 000000000..ab66cfe01 --- /dev/null +++ b/usrp1/sdr_lib/gen_cordic_consts.py @@ -0,0 +1,10 @@ +#!/usr/bin/env python + +import math + +zwidth = 16 + +for i in range(17): + c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth) + print "`define c%02d %d'd%d" % (i, zwidth, round (c)) + diff --git a/usrp1/sdr_lib/gen_sync.v b/usrp1/sdr_lib/gen_sync.v new file mode 100644 index 000000000..d6efdba98 --- /dev/null +++ b/usrp1/sdr_lib/gen_sync.v @@ -0,0 +1,43 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module gen_sync + ( input clock, + input reset, + input enable, + input [7:0] rate, + output wire sync ); + +// parameter width = 8; + + reg [7:0] counter; + assign sync = |(((rate+1)>>1)& counter); + + always @(posedge clock) + if(reset || ~enable) + counter <= #1 0; + else if(counter == rate) + counter <= #1 0; + else + counter <= #1 counter + 8'd1; + +endmodule // gen_sync + diff --git a/usrp1/sdr_lib/hb/acc.v b/usrp1/sdr_lib/hb/acc.v new file mode 100644 index 000000000..195d5ea94 --- /dev/null +++ b/usrp1/sdr_lib/hb/acc.v @@ -0,0 +1,22 @@ + + +module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, + input signed [30:0] addend, output reg signed [33:0] sum ); + + always @(posedge clock) + if(reset) + sum <= #1 34'd0; + //else if(clear & enable_in) + // sum <= #1 addend; + //else if(clear) + // sum <= #1 34'd0; + else if(clear) + sum <= #1 addend; + else if(enable_in) + sum <= #1 sum + addend; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // acc + diff --git a/usrp1/sdr_lib/hb/coeff_rom.v b/usrp1/sdr_lib/hb/coeff_rom.v new file mode 100644 index 000000000..7f8886b4e --- /dev/null +++ b/usrp1/sdr_lib/hb/coeff_rom.v @@ -0,0 +1,19 @@ + + +module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); + + always @(posedge clock) + case (addr) + 3'd0 : data <= #1 -16'd49; + 3'd1 : data <= #1 16'd165; + 3'd2 : data <= #1 -16'd412; + 3'd3 : data <= #1 16'd873; + 3'd4 : data <= #1 -16'd1681; + 3'd5 : data <= #1 16'd3135; + 3'd6 : data <= #1 -16'd6282; + 3'd7 : data <= #1 16'd20628; + endcase // case(addr) + +endmodule // coeff_rom + + diff --git a/usrp1/sdr_lib/hb/halfband_decim.v b/usrp1/sdr_lib/hb/halfband_decim.v new file mode 100644 index 000000000..dff4d902c --- /dev/null +++ b/usrp1/sdr_lib/hb/halfband_decim.v @@ -0,0 +1,163 @@ +/* -*- verilog -*- + * + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2005 Matt Ettus + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA + */ + +/* + * This implements a 31-tap halfband filter that decimates by two. + * The coefficients are symmetric, and with the exception of the middle tap, + * every other coefficient is zero. The middle section of taps looks like this: + * + * ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ... + * | + * middle tap -------+ + * + * See coeff_rom.v for the full set. The taps are scaled relative to 32768, + * thus the middle tap equals 1.0. Not counting the middle tap, there are 8 + * non-zero taps on each side, and they are symmetric. A naive implementation + * requires a mulitply for each non-zero tap. Because of symmetry, we can + * replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output + * sample, we need to perform 8 multiplications. Since the middle tap is 1.0, + * we just add the corresponding delay line value. + * + * About timing: We implement this with a single multiplier, so it takes + * 8 cycles to compute a single output. However, since we're decimating by two + * we can accept a new input value every 4 cycles. strobe_in is asserted when + * there's a new input sample available. Depending on the overall decimation + * rate, strobe_in may be asserted less frequently than once every 4 clocks. + * On the output side, we assert strobe_out when output contains a new sample. + * + * Implementation: Every time strobe_in is asserted we store the new data into + * the delay line. We split the delay line into two components, one for the + * even samples, and one for the odd samples. ram16_odd is the delay line for + * the odd samples. This ram is written on each odd assertion of strobe_in, and + * is read on each clock when we're computing the dot product. ram16_even is + * similar, although because it holds the even samples we must be able to read + * two samples from different addresses at the same time, while writing the incoming + * even samples. Thus it's "triple-ported". + */ + +module halfband_decim + (input clock, input reset, input enable, input strobe_in, output wire strobe_out, + input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl); + + reg [3:0] rd_addr1; + reg [3:0] rd_addr2; + reg [3:0] phase; + reg [3:0] base_addr; + + wire signed [15:0] mac_out,middle_data, sum, coeff; + wire signed [30:0] product; + wire signed [33:0] sum_even; + wire clear; + reg store_odd; + + always @(posedge clock) + if(reset) + store_odd <= #1 1'b0; + else + if(strobe_in) + store_odd <= #1 ~store_odd; + + wire start = strobe_in & store_odd; + always @(posedge clock) + if(reset) + base_addr <= #1 4'd0; + else if(start) + base_addr <= #1 base_addr + 4'd1; + + always @(posedge clock) + if(reset) + phase <= #1 4'd8; + else if (start) + phase <= #1 4'd0; + else if(phase != 4'd8) + phase <= #1 phase + 4'd1; + + reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD; + always @(posedge clock) + begin + start_d1 <= #1 start; + start_d2 <= #1 start_d1; + start_d3 <= #1 start_d2; + start_d4 <= #1 start_d3; + start_d5 <= #1 start_d4; + start_d6 <= #1 start_d5; + start_d7 <= #1 start_d6; + start_d8 <= #1 start_d7; + start_d9 <= #1 start_d8; + start_dA <= #1 start_d9; + start_dB <= #1 start_dA; + start_dC <= #1 start_dB; + start_dD <= #1 start_dC; + end // always @ (posedge clock) + + reg mult_en, mult_en_pre; + always @(posedge clock) + begin + mult_en_pre <= #1 phase!=8; + mult_en <= #1 mult_en_pre; + end + + assign clear = start_d4; // was dC + wire latch_result = start_d4; // was dC + assign strobe_out = start_d5; // was dD + wire acc_en; + + always @* + case(phase[2:0]) + 3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end + 3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end + 3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end + 3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end + 3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end + 3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end + 3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end + 3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end + default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end + endcase // case(phase) + + coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff)); + + ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), + .wr_addr(base_addr),.wr_data(data_in), + .rd_addr1(rd_addr1),.rd_addr2(rd_addr2), + .sum(sum)); + + ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items + .wr_addr(base_addr),.wr_data(data_in), + //.rd_addr(base_addr+4'd7),.rd_data(middle_data)); + .rd_addr(base_addr+4'd6),.rd_data(middle_data)); + + mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en)); + + acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(), + .clear(clear),.addend(product),.sum(sum_even)); + + wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!! + + always @(posedge clock) + if(reset) + data_out <= #1 16'd0; + else if(latch_result) + data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]); + + assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase}; + +endmodule // halfband_decim diff --git a/usrp1/sdr_lib/hb/halfband_interp.v b/usrp1/sdr_lib/hb/halfband_interp.v new file mode 100644 index 000000000..cdb11c1f6 --- /dev/null +++ b/usrp1/sdr_lib/hb/halfband_interp.v @@ -0,0 +1,121 @@ + + +module halfband_interp + (input clock, input reset, input enable, + input strobe_in, input strobe_out, + input [15:0] signal_in_i, input [15:0] signal_in_q, + output reg [15:0] signal_out_i, output reg [15:0] signal_out_q, + output wire [12:0] debug); + + wire [15:0] coeff_ram_out; + wire [15:0] data_ram_out_i; + wire [15:0] data_ram_out_q; + + wire [3:0] data_rd_addr; + reg [3:0] data_wr_addr; + reg [2:0] coeff_rd_addr; + + wire filt_done; + + wire [15:0] mac_out_i; + wire [15:0] mac_out_q; + reg [15:0] delayed_middle_i, delayed_middle_q; + wire [7:0] shift = 8'd9; + + reg stb_out_happened; + + wire [15:0] data_ram_out_i_b; + + always @(posedge clock) + if(strobe_in) + stb_out_happened <= #1 1'b0; + else if(strobe_out) + stb_out_happened <= #1 1'b1; + +assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr}; + + wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i; + wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q; + +/* always @(posedge clock) + if(reset) + begin + signal_out_i <= #1 16'd0; + signal_out_q <= #1 16'd0; + end + else if(strobe_in) + begin + signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff + signal_out_q <= #1 delayed_middle_q; + end + //else if(filt_done&stb_out_happened) + else if(stb_out_happened) + begin + signal_out_i <= #1 mac_out_i; + signal_out_q <= #1 mac_out_q; + end +*/ + + always @(posedge clock) + if(reset) + coeff_rd_addr <= #1 3'd0; + else if(coeff_rd_addr != 3'd0) + coeff_rd_addr <= #1 coeff_rd_addr + 3'd1; + else if(strobe_in) + coeff_rd_addr <= #1 3'd1; + + reg filt_done_d1; + always@(posedge clock) + filt_done_d1 <= #1 filt_done; + + always @(posedge clock) + if(reset) + data_wr_addr <= #1 4'd0; + //else if(strobe_in) + else if(filt_done & ~filt_done_d1) + data_wr_addr <= #1 data_wr_addr + 4'd1; + + always @(posedge clock) + if(coeff_rd_addr == 3'd7) + begin + delayed_middle_i <= #1 data_ram_out_i_b; + // delayed_middle_q <= #1 data_ram_out_q_b; + end + +// always @(posedge clock) +// if(reset) +// data_rd_addr <= #1 4'd0; +// else if(strobe_in) +// data_rd_addr <= #1 data_wr_addr + 4'd1; +// else if(!filt_done) +// data_rd_addr <= #1 data_rd_addr + 4'd1; +// else +// data_rd_addr <= #1 data_wr_addr; + + wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr}; + wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr}; +// always @(posedge clock) +// if(reset) +// filt_done <= #1 1'b1; +// else if(strobe_in) + // filt_done <= #1 1'b0; +// else if(coeff_rd_addr == 4'd0) +// filt_done <= #1 1'b1; + + assign filt_done = (coeff_rd_addr == 3'd0); + + coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) ); + + ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i), + .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i)); + + ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q), + .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q)); + + mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), + .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) ); + + mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), + .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) ); + +endmodule // halfband_interp diff --git a/usrp1/sdr_lib/hb/hbd_tb/HBD b/usrp1/sdr_lib/hb/hbd_tb/HBD new file mode 100644 index 000000000..574fbba91 --- /dev/null +++ b/usrp1/sdr_lib/hb/hbd_tb/HBD @@ -0,0 +1,80 @@ +*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +test_hbd.clock +test_hbd.reset +@420 +test_hbd.halfband_decim.middle_data[15:0] +@22 +test_hbd.halfband_decim.sum_even[33:0] +test_hbd.halfband_decim.base_addr[3:0] +@420 +test_hbd.i_in[15:0] +@24 +test_hbd.halfband_decim.phase[3:0] +test_hbd.halfband_decim.ram16_even.rd_addr1[3:0] +test_hbd.halfband_decim.ram16_even.rd_addr2[3:0] +test_hbd.halfband_decim.ram16_even.wr_addr[3:0] +test_hbd.halfband_decim.ram16_even.wr_data[15:0] +@28 +test_hbd.halfband_decim.ram16_even.write +@420 +test_hbd.halfband_decim.sum[15:0] +test_hbd.halfband_decim.product[30:0] +test_hbd.halfband_decim.dout[33:0] +test_hbd.halfband_decim.sum_even[33:0] +@22 +test_hbd.halfband_decim.acc.addend[30:0] +@28 +test_hbd.halfband_decim.acc.reset +@420 +test_hbd.halfband_decim.acc.sum[33:0] +test_hbd.halfband_decim.mult.x[15:0] +test_hbd.halfband_decim.mult.y[15:0] +@28 +test_hbd.halfband_decim.acc.clear +test_hbd.strobe_in +test_hbd.strobe_out +test_hbd.halfband_decim.acc_en +@420 +test_hbd.i_out[15:0] +@28 +test_hbd.halfband_decim.mult_en +test_hbd.halfband_decim.latch_result +@420 +test_hbd.halfband_decim.sum[15:0] +test_hbd.halfband_decim.sum_even[33:0] +test_hbd.halfband_decim.dout[33:0] +test_hbd.halfband_decim.data_out[15:0] +@22 +test_hbd.halfband_decim.data_out[15:0] +@28 +test_hbd.halfband_decim.dout[33:0] +@29 +test_hbd.halfband_decim.acc_en +@22 +test_hbd.halfband_decim.base_addr[3:0] +@28 +test_hbd.halfband_decim.clear +test_hbd.halfband_decim.latch_result +test_hbd.halfband_decim.mult_en +test_hbd.halfband_decim.mult_en_pre +@22 +test_hbd.halfband_decim.phase[3:0] +@28 +test_hbd.halfband_decim.start +test_hbd.halfband_decim.start_d1 +test_hbd.halfband_decim.start_d2 +test_hbd.halfband_decim.start_d3 +test_hbd.halfband_decim.start_d4 +test_hbd.halfband_decim.start_d5 +test_hbd.halfband_decim.start_d6 +test_hbd.halfband_decim.start_d7 +test_hbd.halfband_decim.start_d8 +test_hbd.halfband_decim.start_d9 +test_hbd.halfband_decim.start_dA +test_hbd.halfband_decim.start_dB +test_hbd.halfband_decim.start_dC +test_hbd.halfband_decim.start_dD +test_hbd.halfband_decim.store_odd +test_hbd.halfband_decim.strobe_in +test_hbd.halfband_decim.strobe_out diff --git a/usrp1/sdr_lib/hb/hbd_tb/really_golden b/usrp1/sdr_lib/hb/hbd_tb/really_golden new file mode 100644 index 000000000..2d24a9e14 --- /dev/null +++ b/usrp1/sdr_lib/hb/hbd_tb/really_golden @@ -0,0 +1,142 @@ +VCD info: dumpfile test_hbd.vcd opened for output. + x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8192 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 +- 4 + 18 +- 63 + 167 +- 367 + 737 +- 1539 + 5146 + 5146 +- 1539 + 737 +- 367 + 167 +- 63 + 18 +- 4 + 0 + 0 + 0 + 0 + 0 +- 4 + 14 +- 49 + 118 +- 249 + 488 + 7141 +12287 +17433 +15894 +16631 +16264 +16432 +16368 +16387 +16383 +16383 +16383 +16383 +16383 +16387 +16368 +16432 +16264 +16631 +15894 + 9241 + 4095 +- 1051 + 488 +- 249 + 118 +- 49 + 14 +- 4 + 0 + 0 + 0 + 0 + 0 +- 4 + 14 +- 49 + 118 +- 249 + 488 +- 1051 +12287 +17433 +15894 +16631 +16264 +16432 +16368 +16387 +16383 +16383 +16383 +16383 +16383 +16387 +16368 +16432 +16264 +16631 +15894 +17433 + 4095 +- 1051 + 488 +- 249 + 118 +- 49 + 14 +- 4 + 0 + 0 + 0 + 0 diff --git a/usrp1/sdr_lib/hb/hbd_tb/regression b/usrp1/sdr_lib/hb/hbd_tb/regression new file mode 100644 index 000000000..fc279c2f2 --- /dev/null +++ b/usrp1/sdr_lib/hb/hbd_tb/regression @@ -0,0 +1,95 @@ +echo "Baseline 1000" +iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden +diff golden really_golden + +echo +echo "Test 100" +iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 50" +iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 40" +iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 30" +iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 25" +iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 20" +iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 19" +iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 18" +iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 17" +iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 16" +iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 15" +iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 14" +iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 13" +iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 12" +iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 11" +iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 10" +iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 9" +iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 8" +iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 7" +iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 6" +iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 5" +iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 4" +iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 3" +iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden diff --git a/usrp1/sdr_lib/hb/hbd_tb/run_hbd b/usrp1/sdr_lib/hb/hbd_tb/run_hbd new file mode 100755 index 000000000..b8aec7574 --- /dev/null +++ b/usrp1/sdr_lib/hb/hbd_tb/run_hbd @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog -y .. -o test_hbd test_hbd.v +./test_hbd diff --git a/usrp1/sdr_lib/hb/hbd_tb/test_hbd.v b/usrp1/sdr_lib/hb/hbd_tb/test_hbd.v new file mode 100644 index 000000000..01ab5e7e0 --- /dev/null +++ b/usrp1/sdr_lib/hb/hbd_tb/test_hbd.v @@ -0,0 +1,75 @@ + + +module test_hbd(); + + reg clock; + initial clock = 1'b0; + always #5 clock <= ~clock; + + reg reset; + initial reset = 1'b1; + initial #1000 reset = 1'b0; + + initial $dumpfile("test_hbd.vcd"); + initial $dumpvars(0,test_hbd); + + reg [15:0] i_in, q_in; + wire [15:0] i_out, q_out; + + reg strobe_in; + wire strobe_out; + reg coeff_write; + reg [15:0] coeff_data; + reg [4:0] coeff_addr; + + halfband_decim halfband_decim + ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), + .data_in(i_in),.data_out(i_out) ); + + always @(posedge strobe_out) + if(i_out[15]) + $display("-%d",65536-i_out); + else + $display("%d",i_out); + + initial + begin + strobe_in = 1'b0; + @(negedge reset); + @(posedge clock); + while(1) + begin + strobe_in <= #1 1'b1; + @(posedge clock); + strobe_in <= #1 1'b0; + repeat (`RATE) + @(posedge clock); + end + end + + initial #10000000 $finish; // Just in case... + + initial + begin + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (41) @(posedge strobe_in); + i_in <= #1 16'd16384; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + repeat (7) @(posedge clock); + $finish; + end // initial begin +endmodule // test_hb diff --git a/usrp1/sdr_lib/hb/mac.v b/usrp1/sdr_lib/hb/mac.v new file mode 100644 index 000000000..5a270bc73 --- /dev/null +++ b/usrp1/sdr_lib/hb/mac.v @@ -0,0 +1,58 @@ + + +module mac (input clock, input reset, input enable, input clear, + input signed [15:0] x, input signed [15:0] y, + input [7:0] shift, output [15:0] z ); + + reg signed [30:0] product; + reg signed [39:0] z_int; + reg signed [15:0] z_shift; + + reg enable_d1; + always @(posedge clock) + enable_d1 <= #1 enable; + + always @(posedge clock) + if(reset | clear) + z_int <= #1 40'd0; + else if(enable_d1) + z_int <= #1 z_int + {{9{product[30]}},product}; + + always @(posedge clock) + product <= #1 x*y; + + always @* // FIXME full case? parallel case? + case(shift) + //8'd0 : z_shift <= z_int[39:24]; + //8'd1 : z_shift <= z_int[38:23]; + //8'd2 : z_shift <= z_int[37:22]; + //8'd3 : z_shift <= z_int[36:21]; + //8'd4 : z_shift <= z_int[35:20]; + //8'd5 : z_shift <= z_int[34:19]; + 8'd6 : z_shift <= z_int[33:18]; + 8'd7 : z_shift <= z_int[32:17]; + 8'd8 : z_shift <= z_int[31:16]; + 8'd9 : z_shift <= z_int[30:15]; + 8'd10 : z_shift <= z_int[29:14]; + 8'd11 : z_shift <= z_int[28:13]; + //8'd12 : z_shift <= z_int[27:12]; + //8'd13 : z_shift <= z_int[26:11]; + //8'd14 : z_shift <= z_int[25:10]; + //8'd15 : z_shift <= z_int[24:9]; + //8'd16 : z_shift <= z_int[23:8]; + //8'd17 : z_shift <= z_int[22:7]; + //8'd18 : z_shift <= z_int[21:6]; + //8'd19 : z_shift <= z_int[20:5]; + //8'd20 : z_shift <= z_int[19:4]; + //8'd21 : z_shift <= z_int[18:3]; + //8'd22 : z_shift <= z_int[17:2]; + //8'd23 : z_shift <= z_int[16:1]; + //8'd24 : z_shift <= z_int[15:0]; + default : z_shift <= z_int[15:0]; + endcase // case(shift) + + // FIXME do we need to saturate? + //assign z = z_shift; + assign z = z_int[15:0]; + +endmodule // mac diff --git a/usrp1/sdr_lib/hb/mult.v b/usrp1/sdr_lib/hb/mult.v new file mode 100644 index 000000000..a8d4cb1b7 --- /dev/null +++ b/usrp1/sdr_lib/hb/mult.v @@ -0,0 +1,16 @@ + + +module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, + input enable_in, output reg enable_out ); + + always @(posedge clock) + if(enable_in) + product <= #1 x*y; + else + product <= #1 31'd0; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // mult + diff --git a/usrp1/sdr_lib/hb/ram16_2port.v b/usrp1/sdr_lib/hb/ram16_2port.v new file mode 100644 index 000000000..e1761a926 --- /dev/null +++ b/usrp1/sdr_lib/hb/ram16_2port.v @@ -0,0 +1,22 @@ + + +module ram16_2port (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr1, output reg [15:0] rd_data1, + input [3:0] rd_addr2, output reg [15:0] rd_data2); + + reg [15:0] ram_array [0:31]; + + always @(posedge clock) + rd_data1 <= #1 ram_array[rd_addr1]; + + always @(posedge clock) + rd_data2 <= #1 ram_array[rd_addr2]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram16_2port + + diff --git a/usrp1/sdr_lib/hb/ram16_2sum.v b/usrp1/sdr_lib/hb/ram16_2sum.v new file mode 100644 index 000000000..559b06fd5 --- /dev/null +++ b/usrp1/sdr_lib/hb/ram16_2sum.v @@ -0,0 +1,27 @@ + + +module ram16_2sum (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr1, input [3:0] rd_addr2, + output reg [15:0] sum); + + reg signed [15:0] ram_array [0:15]; + reg signed [15:0] a,b; + wire signed [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + always @(posedge clock) + begin + a <= #1 ram_array[rd_addr1]; + b <= #1 ram_array[rd_addr2]; + end + + assign sum_int = {a[15],a} + {b[15],b}; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + +endmodule // ram16_2sum diff --git a/usrp1/sdr_lib/hb/ram32_2sum.v b/usrp1/sdr_lib/hb/ram32_2sum.v new file mode 100644 index 000000000..d1f55b7d0 --- /dev/null +++ b/usrp1/sdr_lib/hb/ram32_2sum.v @@ -0,0 +1,22 @@ + + +module ram32_2sum (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr1, input [4:0] rd_addr2, + output reg [15:0] sum); + + reg [15:0] ram_array [0:31]; + wire [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + + +endmodule // ram32_2sum + diff --git a/usrp1/sdr_lib/io_pins.v b/usrp1/sdr_lib/io_pins.v new file mode 100644 index 000000000..ad1b7b4a8 --- /dev/null +++ b/usrp1/sdr_lib/io_pins.v @@ -0,0 +1,52 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2005,2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +`include "../../firmware/include/fpga_regs_common.v" +`include "../../firmware/include/fpga_regs_standard.v" + +module io_pins + ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3, + input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3, + input clock, input rx_reset, input tx_reset, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe); + + reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe; + + bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0)); + bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1)); + bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe),.reg_val(reg_2)); + bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe),.reg_val(reg_3)); + + // Upper 16 bits are mask for lower 16 + always @(posedge clock) + if(serial_strobe) + case(serial_addr) + `FR_OE_0 : io_0_oe + <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_1 : io_1_oe + <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_2 : io_2_oe + <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_3 : io_3_oe + <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + endcase // case(serial_addr) + +endmodule // io_pins diff --git a/usrp1/sdr_lib/master_control.v b/usrp1/sdr_lib/master_control.v new file mode 100644 index 000000000..3bce55f23 --- /dev/null +++ b/usrp1/sdr_lib/master_control.v @@ -0,0 +1,163 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2005 Matt Ettus +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Clock, enable, and reset controls for whole system + +module master_control + ( input master_clk, input usbclk, + input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe, + output tx_bus_reset, output rx_bus_reset, + output wire tx_dsp_reset, output wire rx_dsp_reset, + output wire enable_tx, output wire enable_rx, + output wire [7:0] interp_rate, output wire [7:0] decim_rate, + output tx_sample_strobe, output strobe_interp, + output rx_sample_strobe, output strobe_decim, + input tx_empty, + input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3, + output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3 + ); + + // FIXME need a separate reset for all control settings + // Master Controls assignments + wire [7:0] master_controls; + setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls)); + assign enable_tx = master_controls[0]; + assign enable_rx = master_controls[1]; + assign tx_dsp_reset = master_controls[2]; + assign rx_dsp_reset = master_controls[3]; + // Unused - 4-7 + + // Strobe Generators + setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate)); + setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate)); + + strobe_gen da_strobe_gen + ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx), + .rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) ); + + strobe_gen tx_strobe_gen + ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx), + .rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) ); + + assign rx_sample_strobe = 1'b1; + + strobe_gen decim_strobe_gen + ( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx), + .rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) ); + + // Reset syncs for bus (usbclk) side + // The RX bus side reset isn't used, the TX bus side one may not be needed + reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2; + + always @(posedge usbclk) + begin + tx_reset_bus_sync1 <= #1 tx_dsp_reset; + rx_reset_bus_sync1 <= #1 rx_dsp_reset; + tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1; + rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1; + end + + assign tx_bus_reset = tx_reset_bus_sync2; + assign rx_bus_reset = rx_reset_bus_sync2; + + wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk; + wire txaclk,txbclk,rxaclk,rxbclk; + wire [3:0] debug_en, txcvr_ctrl; + + wire [31:0] txcvr_rxlines, txcvr_txlines; + + setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk)); + setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk)); + setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk)); + setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk)); + + setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en)); + + clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0])); + clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0])); + clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0])); + clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0])); + + reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg; + // Upper 16 bits are mask for lower 16 + always @(posedge master_clk) + if(serial_strobe) + case(serial_addr) + `FR_IO_0 : io_0_reg + <= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_IO_1 : io_1_reg + <= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_IO_2 : io_2_reg + <= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_IO_3 : io_3_reg + <= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + endcase // case(serial_addr) + + wire transmit_now; + wire atr_ctl; + wire [11:0] atr_tx_delay, atr_rx_delay; + wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3; + + setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0)); + setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0)); + setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0)); + + setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1)); + setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1)); + setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1)); + + setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2)); + setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2)); + setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2)); + + setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3)); + setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3)); + setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3)); + + //setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl)); + setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay)); + setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay)); + + assign atr_ctl = 1'b1; + + atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty), + .tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now)); + + wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0; + wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg); + + wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1; + wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg); + + wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2; + wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg); + + wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3; + wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg); + + assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0; + assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1; + assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2; + assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3; + + +endmodule // master_control diff --git a/usrp1/sdr_lib/master_control_multi.v b/usrp1/sdr_lib/master_control_multi.v new file mode 100644 index 000000000..cab96a79f --- /dev/null +++ b/usrp1/sdr_lib/master_control_multi.v @@ -0,0 +1,73 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +`include "config.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" +// Clock, enable, and reset controls for whole system +// Modified version to enable multi_usrp synchronisation + +module master_control_multi + ( input master_clk, input usbclk, + input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe, + input wire rx_slave_sync, + output tx_bus_reset, output rx_bus_reset, + output wire tx_dsp_reset, output wire rx_dsp_reset, + output wire enable_tx, output wire enable_rx, + output wire sync_rx, + output wire [7:0] interp_rate, output wire [7:0] decim_rate, + output tx_sample_strobe, output strobe_interp, + output rx_sample_strobe, output strobe_decim, + input tx_empty, + input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3, + output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3 + ); + + wire [15:0] reg_1_std; + + master_control master_control_standard + ( .master_clk(master_clk),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + .debug_0(debug_0),.debug_1(debug_1), + .debug_2(debug_2),.debug_3(debug_3), + .reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) ); + + // FIXME need a separate reset for all control settings + // Master/slave Controls assignments + wire [7:0] rx_master_slave_controls; + setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls)); + + assign sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync); + //sync if we are told by master_control or if we get a hardware slave sync + //TODO There can be a one sample difference between master and slave sync. + // Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger + // Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind) + //TODO make output pin not hardwired +assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]}; + + +endmodule // master_control diff --git a/usrp1/sdr_lib/phase_acc.v b/usrp1/sdr_lib/phase_acc.v new file mode 100755 index 000000000..f44853d36 --- /dev/null +++ b/usrp1/sdr_lib/phase_acc.v @@ -0,0 +1,52 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + + +// Basic Phase accumulator for DDS + + +module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase); + parameter FREQADDR = 0; + parameter PHASEADDR = 0; + parameter resolution = 32; + + input clk, reset, enable, strobe; + input [6:0] serial_addr; + input [31:0] serial_data; + input serial_strobe; + + output reg [resolution-1:0] phase; + wire [resolution-1:0] freq; + + setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq)); + + always @(posedge clk) + if(reset) + phase <= #1 32'b0; + else if(serial_strobe & (serial_addr == PHASEADDR)) + phase <= #1 serial_data; + else if(enable & strobe) + phase <= #1 phase + freq; + +endmodule // phase_acc + + diff --git a/usrp1/sdr_lib/ram.v b/usrp1/sdr_lib/ram.v new file mode 100644 index 000000000..fb64cdeae --- /dev/null +++ b/usrp1/sdr_lib/ram.v @@ -0,0 +1,16 @@ + + +module ram (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:31]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram diff --git a/usrp1/sdr_lib/ram16.v b/usrp1/sdr_lib/ram16.v new file mode 100644 index 000000000..0c93da2be --- /dev/null +++ b/usrp1/sdr_lib/ram16.v @@ -0,0 +1,17 @@ + + +module ram16 (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:15]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram16 + diff --git a/usrp1/sdr_lib/ram32.v b/usrp1/sdr_lib/ram32.v new file mode 100644 index 000000000..064e2735a --- /dev/null +++ b/usrp1/sdr_lib/ram32.v @@ -0,0 +1,17 @@ + + +module ram32 (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:31]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram32 + diff --git a/usrp1/sdr_lib/ram64.v b/usrp1/sdr_lib/ram64.v new file mode 100644 index 000000000..084545808 --- /dev/null +++ b/usrp1/sdr_lib/ram64.v @@ -0,0 +1,16 @@ + + +module ram64 (input clock, input write, + input [5:0] wr_addr, input [15:0] wr_data, + input [5:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:63]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram64 diff --git a/usrp1/sdr_lib/rssi.v b/usrp1/sdr_lib/rssi.v new file mode 100644 index 000000000..e45e2148c --- /dev/null +++ b/usrp1/sdr_lib/rssi.v @@ -0,0 +1,30 @@ + + +module rssi (input clock, input reset, input enable, + input [11:0] adc, output [15:0] rssi, output [15:0] over_count); + + wire over_hi = (adc == 12'h7FF); + wire over_lo = (adc == 12'h800); + wire over = over_hi | over_lo; + + reg [25:0] over_count_int; + always @(posedge clock) + if(reset | ~enable) + over_count_int <= #1 26'd0; + else + over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10]; + + assign over_count = over_count_int[25:10]; + + wire [11:0] abs_adc = adc[11] ? ~adc : adc; + + reg [25:0] rssi_int; + always @(posedge clock) + if(reset | ~enable) + rssi_int <= #1 26'd0; + else + rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10]; + + assign rssi = rssi_int[25:10]; + +endmodule // rssi diff --git a/usrp1/sdr_lib/rx_buffer.v b/usrp1/sdr_lib/rx_buffer.v new file mode 100644 index 000000000..d17294b98 --- /dev/null +++ b/usrp1/sdr_lib/rx_buffer.v @@ -0,0 +1,237 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Interface to Cypress FX2 bus +// A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each + +`include "../../firmware/include/fpga_regs_common.v" +`include "../../firmware/include/fpga_regs_standard.v" + +module rx_buffer + ( // Read/USB side + input usbclk, + input bus_reset, + output [15:0] usbdata, + input RD, + output reg have_pkt_rdy, + output reg rx_overrun, + input clear_status, + // Write/DSP side + input rxclk, + input reset, // DSP side reset (used here), do not reset registers + input rxstrobe, + input wire [3:0] channels, + input wire [15:0] ch_0, + input wire [15:0] ch_1, + input wire [15:0] ch_2, + input wire [15:0] ch_3, + input wire [15:0] ch_4, + input wire [15:0] ch_5, + input wire [15:0] ch_6, + input wire [15:0] ch_7, + // Settings, on rxclk also + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, + input reset_regs, //Only reset registers + output [31:0] debugbus + ); + + wire [15:0] fifodata, fifodata_8; + reg [15:0] fifodata_16; + + wire [11:0] rxfifolevel; + wire rx_full; + + wire bypass_hb, want_q; + wire [4:0] bitwidth; + wire [3:0] bitshift; + + setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({bypass_hb,want_q,bitwidth,bitshift})); + + // USB Read Side of FIFO + always @(negedge usbclk) + have_pkt_rdy <= (rxfifolevel >= 256); + + // 257 Bug Fix + reg [8:0] read_count; + always @(negedge usbclk) + if(bus_reset) + read_count <= 0; + else if(RD) + read_count <= read_count + 1; + else + read_count <= 0; + + // FIFO + wire ch0_in, ch0_out, iq_out; + assign ch0_in = (phase == 1); + + fifo_4k_18 rxfifo + ( // DSP Write Side + .data ( {ch0_in, phase[0], fifodata} ), + .wrreq (~rx_full & (phase != 0)), + .wrclk ( rxclk ), + .wrfull ( rx_full ), + .wrempty ( ), + .wrusedw ( ), + // USB Read Side + .q ( {ch0_out,iq_out,usbdata} ), + .rdreq ( RD & ~read_count[8] ), + .rdclk ( ~usbclk ), + .rdfull ( ), + .rdempty ( ), + .rdusedw ( rxfifolevel ), + // Async, shared + .aclr ( reset ) ); + + // DSP Write Side of FIFO + reg [15:0] ch_0_reg; + reg [15:0] ch_1_reg; + reg [15:0] ch_2_reg; + reg [15:0] ch_3_reg; + reg [15:0] ch_4_reg; + reg [15:0] ch_5_reg; + reg [15:0] ch_6_reg; + reg [15:0] ch_7_reg; + + always @(posedge rxclk) + if (rxstrobe) + begin + ch_0_reg <= ch_0; + ch_1_reg <= ch_1; + ch_2_reg <= ch_2; + ch_3_reg <= ch_3; + ch_4_reg <= ch_4; + ch_5_reg <= ch_5; + ch_6_reg <= ch_6; + ch_7_reg <= ch_7; + end + + reg [3:0] phase; + always @(posedge rxclk) + if(reset) + phase <= 4'd0; + else if(phase == 0) + begin + if(rxstrobe) + phase <= 4'd1; + end + else if(~rx_full) + if(phase == ((bitwidth == 5'd8) ? (channels>>1) : channels)) + phase <= 4'd0; + else + phase <= phase + 4'd1; + + assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16; + + assign fifodata_8 = {round_8(top),round_8(bottom)}; + reg [15:0] top,bottom; + + function [7:0] round_8; + input [15:0] in_val; + + round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]); + endfunction // round_8 + + always @* + case(phase) + 4'd1 : begin + bottom = ch_0_reg; + top = ch_1_reg; + end + 4'd2 : begin + bottom = ch_2_reg; + top = ch_3_reg; + end + 4'd3 : begin + bottom = ch_4_reg; + top = ch_5_reg; + end + 4'd4 : begin + bottom = ch_6_reg; + top = ch_7_reg; + end + default : begin + top = 16'hFFFF; + bottom = 16'hFFFF; + end + endcase // case(phase) + + always @* + case(phase) + 4'd1 : fifodata_16 = ch_0_reg; + 4'd2 : fifodata_16 = ch_1_reg; + 4'd3 : fifodata_16 = ch_2_reg; + 4'd4 : fifodata_16 = ch_3_reg; + 4'd5 : fifodata_16 = ch_4_reg; + 4'd6 : fifodata_16 = ch_5_reg; + 4'd7 : fifodata_16 = ch_6_reg; + 4'd8 : fifodata_16 = ch_7_reg; + default : fifodata_16 = 16'hFFFF; + endcase // case(phase) + + // Detect overrun + reg clear_status_dsp, rx_overrun_dsp; + always @(posedge rxclk) + clear_status_dsp <= clear_status; + + always @(negedge usbclk) + rx_overrun <= rx_overrun_dsp; + + always @(posedge rxclk) + if(reset) + rx_overrun_dsp <= 1'b0; + else if(rxstrobe & (phase != 0)) + rx_overrun_dsp <= 1'b1; + else if(clear_status_dsp) + rx_overrun_dsp <= 1'b0; + + // Debug bus + // + // 15:0 rxclk domain => TXA 15:0 + // 31:16 usbclk domain => RXA 15:0 + + assign debugbus[0] = reset; + assign debugbus[1] = reset_regs; + assign debugbus[2] = rxstrobe; + assign debugbus[6:3] = channels; + assign debugbus[7] = rx_full; + assign debugbus[11:8] = phase; + assign debugbus[12] = ch0_in; + assign debugbus[13] = clear_status_dsp; + assign debugbus[14] = rx_overrun_dsp; + assign debugbus[15] = rxclk; + + assign debugbus[16] = bus_reset; + assign debugbus[17] = RD; + assign debugbus[18] = have_pkt_rdy; + assign debugbus[19] = rx_overrun; + assign debugbus[20] = read_count[0]; + assign debugbus[21] = read_count[8]; + assign debugbus[22] = ch0_out; + assign debugbus[23] = iq_out; + assign debugbus[24] = clear_status; + assign debugbus[30:25] = 0; + assign debugbus[31] = usbclk; + +endmodule // rx_buffer + diff --git a/usrp1/sdr_lib/rx_chain.v b/usrp1/sdr_lib/rx_chain.v new file mode 100644 index 000000000..bc4336e41 --- /dev/null +++ b/usrp1/sdr_lib/rx_chain.v @@ -0,0 +1,106 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Following defines conditionally include RX path circuitry + +`include "config.vh" // resolved relative to project root + +module rx_chain + (input clock, + input reset, + input enable, + input wire [7:0] decim_rate, + input sample_strobe, + input decimator_strobe, + output wire hb_strobe, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out, + output wire [15:0] q_out, + output wire [15:0] debugdata,output wire [15:0] debugctrl + ); + + parameter FREQADDR = 0; + parameter PHASEADDR = 0; + + wire [31:0] phase; + wire [15:0] bb_i, bb_q; + wire [15:0] hb_in_i, hb_in_q; + + assign debugdata = hb_in_i; + +`ifdef RX_NCO_ON + phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc + (.clk(clock),.reset(reset),.enable(enable), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .strobe(sample_strobe),.phase(phase) ); + + cordic rx_cordic + ( .clock(clock),.reset(reset),.enable(enable), + .xi(i_in),.yi(q_in),.zi(phase[31:16]), + .xo(bb_i),.yo(bb_q),.zo() ); +`else + assign bb_i = i_in; + assign bb_q = q_in; + assign sample_strobe = 1; +`endif // !`ifdef RX_NCO_ON + +`ifdef RX_CIC_ON + cic_decim cic_decim_i_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_i),.signal_out(hb_in_i) ); +`else + assign hb_in_i = bb_i; + assign decimator_strobe = sample_strobe; +`endif + +`ifdef RX_HB_ON + halfband_decim hbd_i_0 + ( .clock(clock),.reset(reset),.enable(enable), + .strobe_in(decimator_strobe),.strobe_out(hb_strobe), + .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) ); +`else + assign i_out = hb_in_i; + assign hb_strobe = decimator_strobe; +`endif + +`ifdef RX_CIC_ON + cic_decim cic_decim_q_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_q),.signal_out(hb_in_q) ); +`else + assign hb_in_q = bb_q; +`endif + +`ifdef RX_HB_ON + halfband_decim hbd_q_0 + ( .clock(clock),.reset(reset),.enable(enable), + .strobe_in(decimator_strobe),.strobe_out(), + .data_in(hb_in_q),.data_out(q_out) ); +`else + assign q_out = hb_in_q; +`endif + + +endmodule // rx_chain diff --git a/usrp1/sdr_lib/rx_chain_dual.v b/usrp1/sdr_lib/rx_chain_dual.v new file mode 100644 index 000000000..d9d98f3fc --- /dev/null +++ b/usrp1/sdr_lib/rx_chain_dual.v @@ -0,0 +1,103 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module rx_chain_dual + (input clock, + input clock_2x, + input reset, + input enable, + input wire [7:0] decim_rate, + input sample_strobe, + input decimator_strobe, + input wire [31:0] freq0, + input wire [15:0] i_in0, + input wire [15:0] q_in0, + output wire [15:0] i_out0, + output wire [15:0] q_out0, + input wire [31:0] freq1, + input wire [15:0] i_in1, + input wire [15:0] q_in1, + output wire [15:0] i_out1, + output wire [15:0] q_out1 + ); + + wire [15:0] phase; + wire [15:0] bb_i, bb_q; + wire [15:0] i_in, q_in; + + wire [31:0] phase0; + wire [31:0] phase1; + reg [15:0] bb_i0, bb_q0; + reg [15:0] bb_i1, bb_q1; + + // We want to time-share the CORDIC by double-clocking it + + phase_acc rx_phase_acc_0 + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq0),.phase(phase0) ); + + phase_acc rx_phase_acc_1 + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq1),.phase(phase1) ); + + assign phase = clock ? phase0[31:16] : phase1[31:16]; + assign i_in = clock ? i_in0 : i_in1; + assign q_in = clock ? q_in0 : q_in1; + +// This appears reversed because of the number of CORDIC stages + always @(posedge clock_2x) + if(clock) + begin + bb_i1 <= #1 bb_i; + bb_q1 <= #1 bb_q; + end + else + begin + bb_i0 <= #1 bb_i; + bb_q0 <= #1 bb_q; + end + + cordic rx_cordic + ( .clock(clock_2x),.reset(reset),.enable(enable), + .xi(i_in),.yi(q_in),.zi(phase), + .xo(bb_i),.yo(bb_q),.zo() ); + + cic_decim cic_decim_i_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_i0),.signal_out(i_out0) ); + + cic_decim cic_decim_q_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_q0),.signal_out(q_out0) ); + + cic_decim cic_decim_i_1 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_i1),.signal_out(i_out1) ); + + cic_decim cic_decim_q_1 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), + .signal_in(bb_q1),.signal_out(q_out1) ); + +endmodule // rx_chain diff --git a/usrp1/sdr_lib/rx_dcoffset.v b/usrp1/sdr_lib/rx_dcoffset.v new file mode 100644 index 000000000..3be475ed6 --- /dev/null +++ b/usrp1/sdr_lib/rx_dcoffset.v @@ -0,0 +1,22 @@ + + +module rx_dcoffset (input clock, input enable, input reset, + input signed [15:0] adc_in, output signed [15:0] adc_out, + input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe); + parameter MYADDR = 0; + + reg signed [31:0] integrator; + wire signed [15:0] scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]); + assign adc_out = adc_in - scaled_integrator; + + // FIXME do we need signed? + //FIXME What do we do when clipping? + always @(posedge clock) + if(reset) + integrator <= #1 32'd0; + else if(serial_strobe & (MYADDR == serial_addr)) + integrator <= #1 {serial_data[15:0],16'd0}; + else if(enable) + integrator <= #1 integrator + adc_out; + +endmodule // rx_dcoffset diff --git a/usrp1/sdr_lib/serial_io.v b/usrp1/sdr_lib/serial_io.v new file mode 100644 index 000000000..62f92bed2 --- /dev/null +++ b/usrp1/sdr_lib/serial_io.v @@ -0,0 +1,118 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2004 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + + +// Serial Control Bus from Cypress chip + +module serial_io + ( input master_clk, + input serial_clock, + input serial_data_in, + input enable, + input reset, + inout wire serial_data_out, + output reg [6:0] serial_addr, + output reg [31:0] serial_data, + output wire serial_strobe, + input wire [31:0] readback_0, + input wire [31:0] readback_1, + input wire [31:0] readback_2, + input wire [31:0] readback_3, + input wire [31:0] readback_4, + input wire [31:0] readback_5, + input wire [31:0] readback_6, + input wire [31:0] readback_7 + ); + + reg is_read; + reg [7:0] ser_ctr; + reg write_done; + + assign serial_data_out = is_read ? serial_data[31] : 1'bz; + + always @(posedge serial_clock, posedge reset, negedge enable) + if(reset) + ser_ctr <= #1 8'd0; + else if(~enable) + ser_ctr <= #1 8'd0; + else if(ser_ctr == 39) + ser_ctr <= #1 8'd0; + else + ser_ctr <= #1 ser_ctr + 8'd1; + + always @(posedge serial_clock, posedge reset, negedge enable) + if(reset) + is_read <= #1 1'b0; + else if(~enable) + is_read <= #1 1'b0; + else if((ser_ctr == 7)&&(serial_addr[6]==1)) + is_read <= #1 1'b1; + + always @(posedge serial_clock, posedge reset) + if(reset) + begin + serial_addr <= #1 7'b0; + serial_data <= #1 32'b0; + write_done <= #1 1'b0; + end + else if(~enable) + begin + //serial_addr <= #1 7'b0; + //serial_data <= #1 32'b0; + write_done <= #1 1'b0; + end + else + begin + if(~is_read && (ser_ctr == 39)) + write_done <= #1 1'b1; + else + write_done <= #1 1'b0; + if(is_read & (ser_ctr==8)) + case (serial_addr) + 7'd1: serial_data <= #1 readback_0; + 7'd2: serial_data <= #1 readback_1; + 7'd3: serial_data <= #1 readback_2; + 7'd4: serial_data <= #1 readback_3; + 7'd5: serial_data <= #1 readback_4; + 7'd6: serial_data <= #1 readback_5; + 7'd7: serial_data <= #1 readback_6; + 7'd8: serial_data <= #1 readback_7; + default: serial_data <= #1 32'd0; + endcase // case(serial_addr) + else if(ser_ctr >= 8) + serial_data <= #1 {serial_data[30:0],serial_data_in}; + else if(ser_ctr < 8) + serial_addr <= #1 {serial_addr[5:0],serial_data_in}; + end // else: !if(~enable) + + reg enable_d1, enable_d2; + always @(posedge master_clk) + begin + enable_d1 <= #1 enable; + enable_d2 <= #1 enable_d1; + end + + assign serial_strobe = enable_d2 & ~enable_d1; + +endmodule // serial_io + + diff --git a/usrp1/sdr_lib/setting_reg.v b/usrp1/sdr_lib/setting_reg.v new file mode 100644 index 000000000..3d31a9efb --- /dev/null +++ b/usrp1/sdr_lib/setting_reg.v @@ -0,0 +1,23 @@ + + +module setting_reg + ( input clock, input reset, input strobe, input wire [6:0] addr, + input wire [31:0] in, output reg [31:0] out, output reg changed); + parameter my_addr = 0; + + always @(posedge clock) + if(reset) + begin + out <= #1 32'd0; + changed <= #1 1'b0; + end + else + if(strobe & (my_addr==addr)) + begin + out <= #1 in; + changed <= #1 1'b1; + end + else + changed <= #1 1'b0; + +endmodule // setting_reg diff --git a/usrp1/sdr_lib/setting_reg_masked.v b/usrp1/sdr_lib/setting_reg_masked.v new file mode 100644 index 000000000..72f7e21eb --- /dev/null +++ b/usrp1/sdr_lib/setting_reg_masked.v @@ -0,0 +1,26 @@ + + +module setting_reg_masked + ( input clock, input reset, input strobe, input wire [6:0] addr, + input wire [31:0] in, output reg [31:0] out, output reg changed); +/* upper 16 bits are mask, lower 16 bits are value + * Note that you get a 16 bit register, not a 32 bit one */ + + parameter my_addr = 0; + + always @(posedge clock) + if(reset) + begin + out <= #1 32'd0; + changed <= #1 1'b0; + end + else + if(strobe & (my_addr==addr)) + begin + out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] ); + changed <= #1 1'b1; + end + else + changed <= #1 1'b0; + +endmodule // setting_reg_masked diff --git a/usrp1/sdr_lib/sign_extend.v b/usrp1/sdr_lib/sign_extend.v new file mode 100644 index 000000000..eae67faf2 --- /dev/null +++ b/usrp1/sdr_lib/sign_extend.v @@ -0,0 +1,35 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// Sign extension "macro" +// bits_out should be greater than bits_in + +module sign_extend (in,out); + parameter bits_in=0; // FIXME Quartus insists on a default + parameter bits_out=0; + + input [bits_in-1:0] in; + output [bits_out-1:0] out; + + assign out = {{(bits_out-bits_in){in[bits_in-1]}},in}; + +endmodule diff --git a/usrp1/sdr_lib/strobe_gen.v b/usrp1/sdr_lib/strobe_gen.v new file mode 100644 index 000000000..ba1a8ab28 --- /dev/null +++ b/usrp1/sdr_lib/strobe_gen.v @@ -0,0 +1,46 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + + +module strobe_gen + ( input clock, + input reset, + input enable, + input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio + input strobe_in, + output wire strobe ); + +// parameter width = 8; + + reg [7:0] counter; + assign strobe = ~|counter && enable && strobe_in; + + always @(posedge clock) + if(reset | ~enable) + counter <= #1 8'd0; + else if(strobe_in) + if(counter == 0) + counter <= #1 rate; + else + counter <= #1 counter - 8'd1; + +endmodule // strobe_gen diff --git a/usrp1/sdr_lib/tx_buffer.v b/usrp1/sdr_lib/tx_buffer.v new file mode 100644 index 000000000..58642229d --- /dev/null +++ b/usrp1/sdr_lib/tx_buffer.v @@ -0,0 +1,170 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Interface to Cypress FX2 bus +// A packet is 512 Bytes. Each fifo line is 2 bytes +// Fifo has 1024 or 2048 lines + +module tx_buffer + ( // USB Side + input usbclk, + input bus_reset, // Used here for the 257-Hack to fix the FX2 bug + input [15:0] usbdata, + input wire WR, + output reg have_space, + output reg tx_underrun, + input clear_status, + + // DSP Side + input txclk, + input reset, // standard DSP-side reset + input wire [3:0] channels, + output reg [15:0] tx_i_0, + output reg [15:0] tx_q_0, + output reg [15:0] tx_i_1, + output reg [15:0] tx_q_1, + input txstrobe, + output wire tx_empty, + output [31:0] debugbus + ); + + wire [11:0] txfifolevel; + wire [15:0] fifodata; + wire rdreq; + reg [3:0] phase; + wire sop_f, iq_f; + reg sop; + + // USB Side of FIFO + reg [15:0] usbdata_reg; + reg wr_reg; + reg [8:0] write_count; + + always @(posedge usbclk) + have_space <= (txfifolevel < (4092-256)); // be extra conservative + + always @(posedge usbclk) + begin + wr_reg <= WR; + usbdata_reg <= usbdata; + end + + always @(posedge usbclk) + if(bus_reset) + write_count <= 0; + else if(wr_reg) + write_count <= write_count + 1; + else + write_count <= 0; + + always @(posedge usbclk) + sop <= WR & ~wr_reg; // Edge detect + + // FIFO + fifo_4k_18 txfifo + ( // USB Write Side + .data ( {sop,write_count[0],usbdata_reg} ), + .wrreq ( wr_reg & ~write_count[8] ), + .wrclk ( usbclk ), + .wrfull ( ), + .wrempty ( ), + .wrusedw ( txfifolevel ), + // DSP Read Side + .q ( {sop_f, iq_f, fifodata} ), + .rdreq ( rdreq ), + .rdclk ( txclk ), + .rdfull ( ), + .rdempty ( tx_empty ), + .rdusedw ( ), + // Async, shared + .aclr ( reset ) ); + + // DAC Side of FIFO + always @(posedge txclk) + if(reset) + begin + {tx_i_0,tx_q_0,tx_i_1,tx_q_1} <= 64'h0; + phase <= 4'd0; + end + else if(phase == channels) + begin + if(txstrobe) + phase <= 4'd0; + end + else + if(~tx_empty) + begin + case(phase) + 4'd0 : tx_i_0 <= fifodata; + 4'd1 : tx_q_0 <= fifodata; + 4'd2 : tx_i_1 <= fifodata; + 4'd3 : tx_q_1 <= fifodata; + endcase // case(phase) + phase <= phase + 4'd1; + end + + assign rdreq = ((phase != channels) & ~tx_empty); + + // Detect Underruns, cross clock domains + reg clear_status_dsp, tx_underrun_dsp; + always @(posedge txclk) + clear_status_dsp <= clear_status; + + always @(posedge usbclk) + tx_underrun <= tx_underrun_dsp; + + always @(posedge txclk) + if(reset) + tx_underrun_dsp <= 1'b0; + else if(txstrobe & (phase != channels)) + tx_underrun_dsp <= 1'b1; + else if(clear_status_dsp) + tx_underrun_dsp <= 1'b0; + + // TX debug bus + // + // 15:0 txclk domain => TXA [15:0] + // 31:16 usbclk domain => RXA [15:0] + + assign debugbus[0] = reset; + assign debugbus[1] = txstrobe; + assign debugbus[2] = rdreq; + assign debugbus[6:3] = phase; + assign debugbus[7] = tx_empty; + assign debugbus[8] = tx_underrun_dsp; + assign debugbus[9] = iq_f; + assign debugbus[10] = sop_f; + assign debugbus[14:11] = 0; + assign debugbus[15] = txclk; + + assign debugbus[16] = bus_reset; + assign debugbus[17] = WR; + assign debugbus[18] = wr_reg; + assign debugbus[19] = have_space; + assign debugbus[20] = write_count[8]; + assign debugbus[21] = write_count[0]; + assign debugbus[22] = sop; + assign debugbus[23] = tx_underrun; + assign debugbus[30:24] = 0; + assign debugbus[31] = usbclk; + +endmodule // tx_buffer + diff --git a/usrp1/sdr_lib/tx_chain.v b/usrp1/sdr_lib/tx_chain.v new file mode 100644 index 000000000..60f868475 --- /dev/null +++ b/usrp1/sdr_lib/tx_chain.v @@ -0,0 +1,65 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module tx_chain + (input clock, + input reset, + input enable, + input wire [7:0] interp_rate, + input sample_strobe, + input interpolator_strobe, + input wire [31:0] freq, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out, + output wire [15:0] q_out + ); + + wire [15:0] bb_i, bb_q; + + cic_interp cic_interp_i + ( .clock(clock),.reset(reset),.enable(enable), + .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe), + .signal_in(i_in),.signal_out(bb_i) ); + + cic_interp cic_interp_q + ( .clock(clock),.reset(reset),.enable(enable), + .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe), + .signal_in(q_in),.signal_out(bb_q) ); + +`define NOCORDIC_TX +`ifdef NOCORDIC_TX + assign i_out = bb_i; + assign q_out = bb_q; +`else + wire [31:0] phase; + + phase_acc phase_acc_tx + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq),.phase(phase) ); + + cordic tx_cordic_0 + ( .clock(clock),.reset(reset),.enable(sample_strobe), + .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), + .xo(i_out),.yo(q_out),.zo() ); +`endif + +endmodule // tx_chain diff --git a/usrp1/sdr_lib/tx_chain_hb.v b/usrp1/sdr_lib/tx_chain_hb.v new file mode 100644 index 000000000..5594348b4 --- /dev/null +++ b/usrp1/sdr_lib/tx_chain_hb.v @@ -0,0 +1,76 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module tx_chain_hb + (input clock, + input reset, + input enable, + input wire [7:0] interp_rate, + input sample_strobe, + input interpolator_strobe, + input hb_strobe, + input wire [31:0] freq, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out, + output wire [15:0] q_out, +output wire [15:0] debug, output [15:0] hb_i_out + ); +assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe}; + + wire [15:0] bb_i, bb_q; + wire [15:0] hb_i_out, hb_q_out; + + halfband_interp hb + (.clock(clock),.reset(reset),.enable(enable), + .strobe_in(interpolator_strobe),.strobe_out(hb_strobe), + .signal_in_i(i_in),.signal_in_q(q_in), + .signal_out_i(hb_i_out),.signal_out_q(hb_q_out), + .debug(debug[12:0])); + + cic_interp cic_interp_i + ( .clock(clock),.reset(reset),.enable(enable), + .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), + .signal_in(hb_i_out),.signal_out(bb_i) ); + + cic_interp cic_interp_q + ( .clock(clock),.reset(reset),.enable(enable), + .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), + .signal_in(hb_q_out),.signal_out(bb_q) ); + +`define NOCORDIC_TX +`ifdef NOCORDIC_TX + assign i_out = bb_i; + assign q_out = bb_q; +`else + wire [31:0] phase; + + phase_acc phase_acc_tx + (.clk(clock),.reset(reset),.enable(enable), + .strobe(sample_strobe),.freq(freq),.phase(phase) ); + + cordic tx_cordic_0 + ( .clock(clock),.reset(reset),.enable(sample_strobe), + .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), + .xo(i_out),.yo(q_out),.zo() ); +`endif + +endmodule // tx_chain diff --git a/usrp1/tb/.gitignore b/usrp1/tb/.gitignore new file mode 100644 index 000000000..6bc85aa2d --- /dev/null +++ b/usrp1/tb/.gitignore @@ -0,0 +1,3 @@ +/*.vcd +/*.out +/fullchip_tb diff --git a/usrp1/tb/cbus_tb.v b/usrp1/tb/cbus_tb.v new file mode 100644 index 000000000..53cc1272b --- /dev/null +++ b/usrp1/tb/cbus_tb.v @@ -0,0 +1,71 @@ +module cbus_tb; + +`define ch1in_freq 0 +`define ch2in_freq 1 +`define ch3in_freq 2 +`define ch4in_freq 3 +`define ch1out_freq 4 +`define ch2out_freq 5 +`define ch3out_freq 6 +`define ch4out_freq 7 +`define rates 8 +`define misc 9 + + task send_config_word; + input [7:0] addr; + input [31:0] data; + integer i; + + begin + #10 serenable = 1; + for(i=7;i>=0;i=i-1) + begin + #10 serdata = addr[i]; + #10 serclk = 0; + #10 serclk = 1; + #10 serclk = 0; + end + for(i=31;i>=0;i=i-1) + begin + #10 serdata = data[i]; + #10 serclk = 0; + #10 serclk = 1; + #10 serclk = 0; + end + #10 serenable = 0; + // #10 serclk = 1; + // #10 serclk = 0; + end + endtask // send_config_word + + initial $dumpfile("cbus_tb.vcd"); + initial $dumpvars(0,cbus_tb); + + initial reset = 1; + initial #500 reset = 0; + + reg serclk, serdata, serenable, reset; + wire SDO; + + control_bus control_bus + ( .serial_clock(serclk), + .serial_data_in(serdata), + .enable(serenable), + .reset(reset), + .serial_data_out(SDO) ); + + + initial + begin + #1000 send_config_word(8'd1,32'hDEAD_BEEF); + #1000 send_config_word(8'd3,32'hDDEE_FF01); + #1000 send_config_word(8'd19,32'hFFFF_FFFF); + #1000 send_config_word(8'd23,32'h1234_FEDC); + #1000 send_config_word(8'h80,32'h0); + #1000 send_config_word(8'h81,32'h0); + #1000 send_config_word(8'h82,32'h0); + #1000 reset = 1; + #1 $finish; + end + +endmodule // cbus_tb diff --git a/usrp1/tb/cordic_tb.v b/usrp1/tb/cordic_tb.v new file mode 100644 index 000000000..946fc776c --- /dev/null +++ b/usrp1/tb/cordic_tb.v @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + + +module cordic_tb(); + + cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo ); + + reg reset; + reg clk; + reg enable; + reg [15:0] xi, yi, zi; + + initial reset = 1'b1; + initial #1000 reset = 1'b0; + + initial clk = 1'b0; + always #50 clk <= ~clk; + + initial enable = 1'b1; + + initial zi = 16'b0; + + always @(posedge clk) + zi <= #1 zi + 16'd0; + + wire [15:0] xo,yo,zo; + + initial $dumpfile("cordic.vcd"); + initial $dumpvars(0,cordic_tb); + initial + begin +`include "sine.txt" + end + + wire [15:0] xiu = {~xi[15],xi[14:0]}; + wire [15:0] yiu = {~yi[15],yi[14:0]}; + wire [15:0] xou = {~xo[15],xo[14:0]}; + wire [15:0] you = {~yo[15],yo[14:0]}; + initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you); + +endmodule // cordic_tb diff --git a/usrp1/tb/decim_tb.v b/usrp1/tb/decim_tb.v new file mode 100644 index 000000000..d9a926125 --- /dev/null +++ b/usrp1/tb/decim_tb.v @@ -0,0 +1,108 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// testbench for fullchip + +module decim_tb(); + +`include "usrp_tasks.v" + + reg clk_120mhz; + reg usbclk; + reg reset; + + reg [11:0] adc1_data, adc2_data; + wire [13:0] dac1_data, dac2_data; + + wire [5:0] usbctl; + wire [5:0] usbrdy; + + wire [15:0] usbdata; + + reg WE, RD, OE; + + assign usbctl[0] = WE; + assign usbctl[1] = RD; + assign usbctl[2] = OE; + assign usbctl[5:3] = 0; + + reg tb_oe; + assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; + reg serload, serenable, serclk, serdata; + reg enable_tx, enable_rx; + reg [15:0] usbdatareg; + +/////////////////////////////////////////////// +// Simulation Control +initial +begin + $dumpfile("decim_tb.vcd"); + $dumpvars(0, fc_tb); +end + +initial #100000 $finish; + +/////////////////////////////////////////////// +// Monitors + +reg [7:0] counter_decim; +wire [7:0] decim_rate; +assign decim_rate = 32; +initial $monitor(dac1_data); + + always @(posedge clk_120mhz) + begin + if(reset | ~enable_tx) + counter_decim <= #1 0; + else if(counter_decim == 0) + counter_decim <= #1 decim_rate - 8'b1; + else + counter_decim <= #1 counter_decim - 8'b1; + end + +/////////////////////////////////////////////// +// Clock and reset + +initial clk_120mhz = 0; +initial usbclk = 0; +always #48 clk_120mhz = ~clk_120mhz; +always #120 usbclk = ~usbclk; + +initial reset = 1'b1; +initial #500 reset = 1'b0; + + +initial enable_tx = 1'b1; + + wire [31:0] decim_out, q_decim_out; + wire [31:0] decim_out; + wire [31:0] phase; + + cic_decim #(.bitwidth(32),.stages(4)) + decim_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), + .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); + + cic_decim #(.bitwidth(32),.stages(4)) + decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), + .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); + +endmodule diff --git a/usrp1/tb/fullchip_tb.v b/usrp1/tb/fullchip_tb.v new file mode 100755 index 000000000..2406fa777 --- /dev/null +++ b/usrp1/tb/fullchip_tb.v @@ -0,0 +1,174 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// testbench for fullchip + +`timescale 1ns/1ns + +module fullchip_tb(); + +`include "usrp_tasks.v" + +fullchip fullchip + ( + .clk_120mhz(clk_120mhz), + .reset(reset), + .enable_rx(enable_rx), + .enable_tx(enable_tx), + .SLD(serload), + .SEN(serenable), + .clear_status(), + .SDI(serdata), + .SCLK(serclk), + + .adc1_data(adc1_data), + .adc2_data(adc2_data), + .adc3_data(adc1_data), + .adc4_data(adc2_data), + + .dac1_data(dac1_data), + .dac2_data(dac2_data), + .dac3_data(),.dac4_data(), + + .adclk0(adclk),.adclk1(), + + .adc_oeb(),.adc_otr(4'b0), + + .clk_out(clk_out), + + .misc_pins(), + + // USB interface + .usbclk(usbclk),.usbctl(usbctl), + .usbrdy(usbrdy),.usbdata(usbdata) + ); + + reg clk_120mhz; + reg usbclk; + reg reset; + + reg [11:0] adc1_data, adc2_data; + wire [13:0] dac1_data, dac2_data; + + wire [5:0] usbctl; + wire [5:0] usbrdy; + + wire [15:0] usbdata; + + reg WE, RD, OE; + + assign usbctl[0] = WE; + assign usbctl[1] = RD; + assign usbctl[2] = OE; + assign usbctl[5:3] = 0; + + wire have_packet_rdy = usbrdy[1]; + + reg tb_oe; + initial tb_oe=1'b1; + + assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; + reg serload, serenable, serclk, serdata; + reg enable_tx, enable_rx; + reg [15:0] usbdatareg; + +/////////////////////////////////////////////// +// Simulation Control +initial +begin + $dumpfile("fullchip_tb.vcd"); + $dumpvars(0, fullchip_tb); +end + +//initial #1000000 $finish; + +/////////////////////////////////////////////// +// Monitors + +//initial $monitor(dac1_data); + +/////////////////////////////////////////////// +// Clock and reset + +initial clk_120mhz = 0; +initial usbclk = 0; +always #24 clk_120mhz = ~clk_120mhz; +always #60 usbclk = ~usbclk; + +initial reset = 1'b1; +initial #500 reset = 1'b0; + +///////////////////////////////////////////////// +// Run AD input + +always @(posedge adclk) adc1_data <= #1 12'd1234; +always @(posedge adclk) adc2_data <= #1 12'd1234; + +///////////////////////////////////////////////// +// USB interface + + initial + begin + initialize_usb; + #30000 @(posedge usbclk); + burst_usb_write(257); + + #30000 burst_usb_read(256); + #10000 $finish; + +// repeat(30) +// begin +// write_from_usb; +// read_from_usb; +// end +end + +///////////////////////////////////////////////// +// TX and RX enable + +initial enable_tx = 1'b0; +initial #40000 enable_tx = 1'b1; +initial enable_rx = 1'b0; +initial #40000 enable_rx = 1'b1; + +////////////////////////////////////////////////// +// Set up control bus + +initial +begin + #1000 send_config_word(`ch1in_freq,32'h0); // 1 MHz on 60 MHz clock + send_config_word(`ch2in_freq,32'h0); + send_config_word(`ch3in_freq,32'h0); + send_config_word(`ch4in_freq,32'h0); + send_config_word(`ch1out_freq,32'h01234567); + send_config_word(`ch2out_freq,32'h0); + send_config_word(`ch3out_freq,32'h0); + send_config_word(`ch4out_freq,32'h0); + send_config_word(`misc,32'h0); + send_config_word(`rates,{8'd2,8'd12,8'h0f,8'h07}); + // adc, ext, interp, decim +end + +///////////////////////////////////////////////////////// + +endmodule + diff --git a/usrp1/tb/interp_tb.v b/usrp1/tb/interp_tb.v new file mode 100755 index 000000000..830fceb31 --- /dev/null +++ b/usrp1/tb/interp_tb.v @@ -0,0 +1,108 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// testbench for fullchip + +module interp_tb(); + +`include "usrp_tasks.v" + + reg clk_120mhz; + reg usbclk; + reg reset; + + reg [11:0] adc1_data, adc2_data; + wire [13:0] dac1_data, dac2_data; + + wire [5:0] usbctl; + wire [5:0] usbrdy; + + wire [15:0] usbdata; + + reg WE, RD, OE; + + assign usbctl[0] = WE; + assign usbctl[1] = RD; + assign usbctl[2] = OE; + assign usbctl[5:3] = 0; + + reg tb_oe; + assign usbdata = tb_oe ? usbdatareg : 16'hxxxx; + reg serload, serenable, serclk, serdata; + reg enable_tx, enable_rx; + reg [15:0] usbdatareg; + +/////////////////////////////////////////////// +// Simulation Control +initial +begin + $dumpfile("interp_tb.vcd"); + $dumpvars(0, fc_tb); +end + +initial #100000 $finish; + +/////////////////////////////////////////////// +// Monitors + +reg [7:0] counter_interp; +wire [7:0] interp_rate; +assign interp_rate = 32; +initial $monitor(dac1_data); + + always @(posedge clk_120mhz) + begin + if(reset | ~enable_tx) + counter_interp <= #1 0; + else if(counter_interp == 0) + counter_interp <= #1 interp_rate - 8'b1; + else + counter_interp <= #1 counter_interp - 8'b1; + end + +/////////////////////////////////////////////// +// Clock and reset + +initial clk_120mhz = 0; +initial usbclk = 0; +always #48 clk_120mhz = ~clk_120mhz; +always #120 usbclk = ~usbclk; + +initial reset = 1'b1; +initial #500 reset = 1'b0; + + +initial enable_tx = 1'b1; + + wire [31:0] interp_out, q_interp_out; + wire [31:0] decim_out; + wire [31:0] phase; + + cic_interp #(.bitwidth(32),.stages(4)) + interp_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), + .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(interp_out)); + + cic_decim #(.bitwidth(32),.stages(4)) + decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx), + .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(decim_out)); + +endmodule diff --git a/usrp1/tb/justinterp_tb.v b/usrp1/tb/justinterp_tb.v new file mode 100644 index 000000000..f97696488 --- /dev/null +++ b/usrp1/tb/justinterp_tb.v @@ -0,0 +1,73 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +module cic_decim_tb; + +cic_decim #(.bitwidth(16),.stages(4)) + decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out); + + reg clock; + reg reset; + reg enable; + wire strobe; + reg [15:0] signal_in; + wire [15:0] signal_out; + + assign strobe_in = 1'b1; + reg strobe_out; + + always @(posedge clock) + while(1) + begin + @(posedge clock); + @(posedge clock); + @(posedge clock); + @(posedge clock); + strobe_out <= 1'b1; + @(posedge clock); + @(posedge clock); + @(posedge clock); + @(posedge clock); + strobe_out <= 1'b0; + end + + initial clock = 0; + always #50 clock = ~clock; + + initial reset = 1; + initial #1000 reset = 0; + + initial enable = 0; + initial #2000 enable = 1; + + initial signal_in = 16'h1; + initial #500000 signal_in = 16'h7fff; + initial #1000000 signal_in = 16'h8000; + initial #1500000 signal_in = 16'hffff; + + + initial $dumpfile("decim.vcd"); + initial $dumpvars(0,cic_decim_tb); + + initial #10000000 $finish; + +endmodule // cic_decim_tb diff --git a/usrp1/tb/makesine.pl b/usrp1/tb/makesine.pl new file mode 100755 index 000000000..9aebd6947 --- /dev/null +++ b/usrp1/tb/makesine.pl @@ -0,0 +1,14 @@ +#!/usr/bin/perl + +$angle = 0; +$angle_inc = 2*3.14159/87.2; +$amp = 1; +$amp_rate = 1.0035; +for($i=0;$i<3500;$i++) + { + printf("@(posedge clk);xi<= #1 16'h%x;yi<= #1 16'h%x;\n",65535&int($amp*cos($angle)),65535&int($amp*sin($angle))); + $angle += $angle_inc; + $amp *= $amp_rate; + } + +printf("\$finish;\n"); diff --git a/usrp1/tb/run_cordic b/usrp1/tb/run_cordic new file mode 100755 index 000000000..68144fc83 --- /dev/null +++ b/usrp1/tb/run_cordic @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog -y ../sdr_lib -o cordic_tb cordic_tb.v + diff --git a/usrp1/tb/run_fullchip b/usrp1/tb/run_fullchip new file mode 100755 index 000000000..eb81d7ff7 --- /dev/null +++ b/usrp1/tb/run_fullchip @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog -y ../toplevel/fullchip -y ../sdr_lib -y ../models -y . -o fullchip_tb fullchip_tb.v + diff --git a/usrp1/tb/usrp_tasks.v b/usrp1/tb/usrp_tasks.v new file mode 100755 index 000000000..93395f96a --- /dev/null +++ b/usrp1/tb/usrp_tasks.v @@ -0,0 +1,145 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Tasks + +///////////////////////////////////////////////// +// USB interface + +task initialize_usb; +begin + OE = 0;WE = 0;RD = 0; + usbdatareg <= 16'h0; +end +endtask + +task write_from_usb; +begin + tb_oe <= 1'b1; + @(posedge usbclk); + usbdatareg <= #1 $random % 65536; + WE <= #1 1'b1; + @(posedge usbclk) + WE <= #1 1'b0; + tb_oe <= #1 1'b0; +end +endtask + +task burst_usb_write; + input [31:0] repeat_count; + + begin + tb_oe <= 1'b1; + repeat(repeat_count) + begin + @(posedge usbclk) + usbdatareg <= #1 usbdatareg + 1; //$random % 65536; + WE <= #1 1'b1; + end + @(posedge usbclk) + WE <= #1 1'b0; + tb_oe <= 1'b0; + end +endtask // burst_usb_write + + +task read_from_usb; +begin + @(posedge usbclk); + RD <= #1 1'b1; + @(posedge usbclk); + RD <= #1 1'b0; + OE <= #1 1'b1; + @(posedge usbclk); + OE <= #1 1'b0; +end +endtask + +task burst_usb_read; + input [31:0] repeat_count; + begin + while (~have_packet_rdy) begin + @(posedge usbclk); + end + + @(posedge usbclk) + RD <= #1 1'b1; + repeat(repeat_count) + begin + @(posedge usbclk) + OE <= #1 1'b1; + end + RD <= #1 1'b0; + @(posedge usbclk); + OE <= #1 1'b0; + end +endtask // burst_usb_read + +///////////////////////////////////////////////// +// TX and RX enable + +////////////////////////////////////////////////// +// Set up control bus + +`define ch1in_freq 0 +`define ch2in_freq 1 +`define ch3in_freq 2 +`define ch4in_freq 3 +`define ch1out_freq 4 +`define ch2out_freq 5 +`define ch3out_freq 6 +`define ch4out_freq 7 +`define rates 8 +`define misc 9 + + task send_config_word; + input [7:0] addr; + input [31:0] data; + integer i; + + begin + #10 serenable = 1; + for(i=7;i>=0;i=i-1) + begin + #10 serdata = addr[i]; + #10 serclk = 0; + #10 serclk = 1; + #10 serclk = 0; + end + for(i=31;i>=0;i=i-1) + begin + #10 serdata = data[i]; + #10 serclk = 0; + #10 serclk = 1; + #10 serclk = 0; + end + #10 serenable = 0; + // #10 serload = 0; + // #10 serload = 1; + #10 serclk = 1; + #10 serclk = 0; + //#10 serload = 0; + end + endtask // send_config_word + + +///////////////////////////////////////////////////////// + diff --git a/usrp1/toplevel/include/common_config_1rxhb_1tx.vh b/usrp1/toplevel/include/common_config_1rxhb_1tx.vh new file mode 100644 index 000000000..fb2e915b1 --- /dev/null +++ b/usrp1/toplevel/include/common_config_1rxhb_1tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built + `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] + `define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* receive circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + + `define RX_SINGLE +//`define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/usrp1/toplevel/include/common_config_2rx_0tx.vh b/usrp1/toplevel/include/common_config_2rx_0tx.vh new file mode 100644 index 000000000..c97c5a32b --- /dev/null +++ b/usrp1/toplevel/include/common_config_2rx_0tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* receive circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE +`define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter +//`define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/usrp1/toplevel/include/common_config_2rxhb_0tx.vh b/usrp1/toplevel/include/common_config_2rxhb_0tx.vh new file mode 100644 index 000000000..459268b6a --- /dev/null +++ b/usrp1/toplevel/include/common_config_2rxhb_0tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* transmit circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE + `define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/usrp1/toplevel/include/common_config_2rxhb_2tx.vh b/usrp1/toplevel/include/common_config_2rxhb_2tx.vh new file mode 100644 index 000000000..ecf0fa03e --- /dev/null +++ b/usrp1/toplevel/include/common_config_2rxhb_2tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built + `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] +//`define TX_SINGLE + `define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* receive circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE + `define RX_DUAL +//`define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter + `define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/usrp1/toplevel/include/common_config_4rx_0tx.vh b/usrp1/toplevel/include/common_config_4rx_0tx.vh new file mode 100644 index 000000000..498419570 --- /dev/null +++ b/usrp1/toplevel/include/common_config_4rx_0tx.vh @@ -0,0 +1,61 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ------------------------------------------------------------ +// If TX_ON is not defined, there is *no* transmit circuitry built +// `define TX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD +// to respectively enable 1, 2 or 4 transmit channels. +// [Please note that only TX_SINGLE and TX_DUAL are currently valid] +//`define TX_SINGLE +//`define TX_DUAL +//`define TX_QUAD + +// ------------------------------------------------------------ +// Define TX_HB_ON to enable the transmit halfband filter +// [Not implemented] +//`define TX_HB_ON + +// ------------------------------------------------------------ +// IF RX_ON is not defined, there is *no* receive circuitry built + `define RX_ON + +// ------------------------------------------------------------ +// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD +// to respectively define 1, 2 or 4 receive channels. + +//`define RX_SINGLE +//`define RX_DUAL + `define RX_QUAD + +// ------------------------------------------------------------ +// Define RX_HB_ON to enable the receive halfband filter +//`define RX_HB_ON + +// ------------------------------------------------------------ +// Define RX_NCO_ON to enable the receive Numerical Controlled Osc + `define RX_NCO_ON + +// ------------------------------------------------------------ +// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter + `define RX_CIC_ON diff --git a/usrp1/toplevel/include/common_config_bottom.vh b/usrp1/toplevel/include/common_config_bottom.vh new file mode 100644 index 000000000..3129798a1 --- /dev/null +++ b/usrp1/toplevel/include/common_config_bottom.vh @@ -0,0 +1,104 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006,2007 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ==================================================================== +// This is the common tail for standard configuation +// ==================================================================== +// +// >>>> DO NOT EDIT BELOW HERE <<<< +// +// N.B., *all* the remainder of the code should be conditionalized +// only in terms of: +// +// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB, +// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB, +// RX_NCO_ON, RX_CIC_ON +// ==================================================================== + +`ifdef TX_ON + + `ifdef TX_SINGLE + `define TX_EN_0 + `define TX_CAP_NCHAN 3'd1 + `endif + + `ifdef TX_DUAL + `define TX_EN_0 + `define TX_EN_1 + `define TX_CAP_NCHAN 3'd2 + `endif + + `ifdef TX_QUAD + `define TX_EN_0 + `define TX_EN_1 + `define TX_EN_2 + `define TX_EN_3 + `define TX_CAP_NCHAN 3'd4 + `endif + + `ifdef TX_HB_ON + `define TX_CAP_HB 1 + `else + `define TX_CAP_HB 0 + `endif + +`else // !ifdef TX_ON + + `define TX_CAP_NCHAN 3'd0 + `define TX_CAP_HB 0 + +`endif // !ifdef TX_ON + +// -------------------------------------------------------------------- + +`ifdef RX_ON + + `ifdef RX_SINGLE + `define RX_EN_0 + `define RX_CAP_NCHAN 3'd1 + `endif + + `ifdef RX_DUAL + `define RX_EN_0 + `define RX_EN_1 + `define RX_CAP_NCHAN 3'd2 + `endif + + `ifdef RX_QUAD + `define RX_EN_0 + `define RX_EN_1 + `define RX_EN_2 + `define RX_EN_3 + `define RX_CAP_NCHAN 3'd4 + `endif + + `ifdef RX_HB_ON + `define RX_CAP_HB 1 + `else + `define RX_CAP_HB 0 + `endif + +`else // !ifdef RX_ON + + `define RX_CAP_NCHAN 3'd0 + `define RX_CAP_HB 0 + +`endif // !ifdef RX_ON diff --git a/usrp1/toplevel/mrfm/.gitignore b/usrp1/toplevel/mrfm/.gitignore new file mode 100644 index 000000000..fe06aad0d --- /dev/null +++ b/usrp1/toplevel/mrfm/.gitignore @@ -0,0 +1,17 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/*.summary +/a.out +/db diff --git a/usrp1/toplevel/mrfm/biquad_2stage.v b/usrp1/toplevel/mrfm/biquad_2stage.v new file mode 100644 index 000000000..9b769014d --- /dev/null +++ b/usrp1/toplevel/mrfm/biquad_2stage.v @@ -0,0 +1,131 @@ +`include "mrfm.vh" + +module biquad_2stage (input clock, input reset, input strobe_in, + input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, + input wire [15:0] sample_in, output reg [15:0] sample_out, output wire [63:0] debugbus); + + wire [3:0] coeff_addr, coeff_wr_addr; + wire [3:0] data_addr, data_wr_addr; + reg [3:0] cur_offset, data_addr_int, data_wr_addr_int; + + wire [15:0] coeff, coeff_wr_data, data, data_wr_data; + wire coeff_wr; + reg data_wr; + + wire [30:0] product; + wire [33:0] accum; + wire [15:0] scaled_accum; + + wire [7:0] shift; + reg [3:0] phase; + wire enable_mult, enable_acc, latch_out, select_input; + reg done, clear_acc; + + setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr)); + + setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(shift),.changed()); + + ram16 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data), + .rd_addr(coeff_addr),.rd_data(coeff)); + + ram16 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data), + .rd_addr(data_addr),.rd_data(data)); + + mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() ); + + acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), + .addend(product),.sum(accum) ); + + shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); + + assign data_wr_data = select_input ? sample_in : scaled_accum; + assign enable_mult = 1'b1; + + always @(posedge clock) + if(reset) + cur_offset <= #1 4'd0; + else if(latch_out) + cur_offset <= #1 cur_offset + 4'd1; + + assign data_addr = data_addr_int + cur_offset; + assign data_wr_addr = data_wr_addr_int + cur_offset; + + always @(posedge clock) + if(reset) + done <= #1 1'b0; + else if(latch_out) + done <= #1 1'b1; + else if(strobe_in) + done <= #1 1'b0; + + always @(posedge clock) + if(reset) + phase <= #1 4'd0; + else if(strobe_in) + phase <= #1 4'd0; + else if(!done) + phase <= #1 phase + 4'd1; + + assign coeff_addr = phase; + + always @(phase) + case(phase) + 4'd01 : data_addr_int = 4'd00; 4'd02 : data_addr_int = 4'd01; 4'd03 : data_addr_int = 4'd02; + 4'd04 : data_addr_int = 4'd03; 4'd05 : data_addr_int = 4'd04; + + 4'd07 : data_addr_int = 4'd03; 4'd08 : data_addr_int = 4'd04; 4'd09 : data_addr_int = 4'd05; + 4'd10 : data_addr_int = 4'd06; 4'd11 : data_addr_int = 4'd07; + default : data_addr_int = 4'd00; + endcase // case(phase) + + always @(phase) + case(phase) + 4'd0 : data_wr_addr_int = 4'd2; + 4'd8 : data_wr_addr_int = 4'd5; + 4'd14 : data_wr_addr_int = 4'd8; + default : data_wr_addr_int = 4'd0; + endcase // case(phase) + + always @(phase) + case(phase) + 4'd0, 4'd8, 4'd14 : data_wr = 1'b1; + default : data_wr = 1'b0; + endcase // case(phase) + + assign select_input = (phase == 4'd0); + + always @(phase) + case(phase) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd9, 4'd15 : clear_acc = 1'd1; + default : clear_acc = 1'b0; + endcase // case(phase) + + assign enable_acc = ~clear_acc; + assign latch_out = (phase == 4'd14); + + always @(posedge clock) + if(reset) + sample_out <= #1 16'd0; + else if(latch_out) + sample_out <= #1 scaled_accum; + + //////////////////////////////////////////////////////// + // Debug + + wire [3:0] debugmux; + + setting_reg #(`FR_MRFM_DEBUG) sr_debugmux(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(debugmux),.changed()); + + assign debugbus[15:0] = debugmux[0] ? {coeff_addr,data_addr,data_wr_addr,cur_offset} : {phase,data_addr_int,data_wr_addr_int,cur_offset}; + assign debugbus[31:16] = debugmux[1] ? scaled_accum : {clock, strobe_in, data_wr, enable_mult, enable_acc, clear_acc, latch_out,select_input,done, data_addr_int}; + assign debugbus[47:32] = debugmux[2] ? sample_out : coeff; + assign debugbus[63:48] = debugmux[3] ? sample_in : data; + +endmodule // biquad_2stage + diff --git a/usrp1/toplevel/mrfm/biquad_6stage.v b/usrp1/toplevel/mrfm/biquad_6stage.v new file mode 100644 index 000000000..2b0c511ce --- /dev/null +++ b/usrp1/toplevel/mrfm/biquad_6stage.v @@ -0,0 +1,137 @@ +`include "mrfm.vh" + +module mrfm_iir (input clock, input reset, input strobe_in, + input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, + input wire [15:0] sample_in, output reg [15:0] sample_out); + + wire [5:0] coeff_addr, coeff_wr_addr; + wire [4:0] data_addr, data_wr_addr; + reg [4:0] cur_offset, data_addr_int, data_wr_addr_int; + + wire [15:0] coeff, coeff_wr_data, data, data_wr_data; + wire coeff_wr; + reg data_wr; + + wire [30:0] product; + wire [33:0] accum; + wire [15:0] scaled_accum; + + wire [7:0] shift; + reg [5:0] phase; + wire enable_mult, enable_acc, latch_out, select_input; + reg done, clear_acc; + + setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr)); + + setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(shift),.changed()); + + ram64 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data), + .rd_addr(coeff_addr),.rd_data(coeff)); + + ram32 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data), + .rd_addr(data_addr),.rd_data(data)); + + mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() ); + + acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), + .addend(product),.sum(accum) ); + + shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); + + assign data_wr_data = select_input ? sample_in : scaled_accum; + assign enable_mult = 1'b1; + + always @(posedge clock) + if(reset) + cur_offset <= #1 5'd0; + else if(latch_out) + cur_offset <= #1 cur_offset + 5'd1; + + assign data_addr = data_addr_int + cur_offset; + assign data_wr_addr = data_wr_addr_int + cur_offset; + + always @(posedge clock) + if(reset) + done <= #1 1'b0; + else if(latch_out) + done <= #1 1'b1; + else if(strobe_in) + done <= #1 1'b0; + + always @(posedge clock) + if(reset) + phase <= #1 6'd0; + else if(strobe_in) + phase <= #1 6'd0; + else if(!done) + phase <= #1 phase + 6'd1; + + always @(phase) + case(phase) + 6'd0 : data_addr_int = 5'd0; + default : data_addr_int = 5'd0; + endcase // case(phase) + + assign coeff_addr = phase; + + always @(phase) + case(phase) + 6'd01 : data_addr_int = 5'd00; 6'd02 : data_addr_int = 5'd01; 6'd03 : data_addr_int = 5'd02; + 6'd04 : data_addr_int = 5'd03; 6'd05 : data_addr_int = 5'd04; + + 6'd07 : data_addr_int = 5'd03; 6'd08 : data_addr_int = 5'd04; 6'd09 : data_addr_int = 5'd05; + 6'd10 : data_addr_int = 5'd06; 6'd11 : data_addr_int = 5'd07; + + 6'd13 : data_addr_int = 5'd06; 6'd14 : data_addr_int = 5'd07; 6'd15 : data_addr_int = 5'd08; + 6'd16 : data_addr_int = 5'd09; 6'd17 : data_addr_int = 5'd10; + + 6'd19 : data_addr_int = 5'd09; 6'd20 : data_addr_int = 5'd10; 6'd21 : data_addr_int = 5'd11; + 6'd22 : data_addr_int = 5'd12; 6'd23 : data_addr_int = 5'd13; + + 6'd25 : data_addr_int = 5'd12; 6'd26 : data_addr_int = 5'd13; 6'd27 : data_addr_int = 5'd14; + 6'd28 : data_addr_int = 5'd15; 6'd29 : data_addr_int = 5'd16; + + 6'd31 : data_addr_int = 5'd15; 6'd32 : data_addr_int = 5'd16; 6'd33 : data_addr_int = 5'd17; + 6'd34 : data_addr_int = 5'd18; 6'd35 : data_addr_int = 5'd19; + + default : data_addr_int = 5'd00; + endcase // case(phase) + + always @(phase) + case(phase) + 6'd0 : data_wr_addr_int = 5'd2; + 6'd8 : data_wr_addr_int = 5'd5; + 6'd14 : data_wr_addr_int = 5'd8; + 6'd20 : data_wr_addr_int = 5'd11; + 6'd26 : data_wr_addr_int = 5'd14; + 6'd32 : data_wr_addr_int = 5'd17; + 6'd38 : data_wr_addr_int = 5'd20; + default : data_wr_addr_int = 5'd0; + endcase // case(phase) + + always @(phase) + case(phase) + 6'd0, 6'd8, 6'd14, 6'd20, 6'd26, 6'd32, 6'd38: data_wr = 1'b1; + default : data_wr = 1'b0; + endcase // case(phase) + + always @(phase) + case(phase) + 6'd0, 6'd1, 6'd2, 6'd3, 6'd9, 6'd15, 6'd21, 6'd27, 6'd33 : clear_acc = 1'd1; + default : clear_acc = 1'b0; + endcase // case(phase) + + assign enable_acc = ~clear_acc; + assign latch_out = (phase == 6'd38); + + always @(posedge clock) + if(reset) + sample_out <= #1 16'd0; + else if(latch_out) + sample_out <= #1 scaled_accum; + +endmodule // mrfm_iir diff --git a/usrp1/toplevel/mrfm/mrfm.csf b/usrp1/toplevel/mrfm/mrfm.csf new file mode 100644 index 000000000..2c30b996b --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm.csf @@ -0,0 +1,444 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; + OPTIMIZE_TIMING = "NORMAL COMPILATION"; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = OFF; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |mrfm; + ROUTING_BACK_ANNOTATION_MODE = OFF; + INC_PLC_MODE = OFF; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} +CHIP(mrfm) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; + AUTO_RESTART_CONFIGURATION = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + USER_START_UP_CLOCK = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_JTAG_BST_SUPPORT = OFF; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + USE_CONFIGURATION_DEVICE = OFF; + APEX20K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + STRATIX_UPDATE_MODE = STANDARD; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + COMPRESSION_MODE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + GENERATE_TTF_FILE = OFF; + GENERATE_RBF_FILE = ON; + GENERATE_HEX_FILE = OFF; + SECURITY_BIT = OFF; + ENABLE_VREFA_PIN = OFF; + ENABLE_VREFB_PIN = OFF; + GENERATE_SVF_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_JBC_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_HEXOUT_FILE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; + BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; + HEXOUT_FILE_START_ADDRESS = 0; + HEXOUT_FILE_COUNT_DIRECTION = UP; + RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; + STRATIX_DEVICE_IO_STANDARD = LVTTL; + CLOCK_SOURCE = INTERNAL; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CONFIGURATION_CLOCK_DIVISOR = 1; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + SCLK : LOCATION = Pin_101; + SDI : LOCATION = Pin_100; + SEN : LOCATION = Pin_98; + SLD : LOCATION = Pin_95; + adc1_data[0] : LOCATION = Pin_5; + adc1_data[10] : LOCATION = Pin_235; + adc1_data[11] : LOCATION = Pin_234; + adc1_data[1] : LOCATION = Pin_4; + adc1_data[2] : LOCATION = Pin_3; + adc1_data[3] : LOCATION = Pin_2; + adc1_data[4] : LOCATION = Pin_1; + adc1_data[4] : IO_STANDARD = LVTTL; + adc1_data[5] : LOCATION = Pin_240; + adc1_data[6] : LOCATION = Pin_239; + adc1_data[7] : LOCATION = Pin_238; + adc1_data[8] : LOCATION = Pin_237; + adc1_data[9] : LOCATION = Pin_236; + adc2_data[0] : LOCATION = Pin_20; + adc2_data[10] : LOCATION = Pin_8; + adc2_data[11] : LOCATION = Pin_7; + adc2_data[1] : LOCATION = Pin_19; + adc2_data[2] : LOCATION = Pin_18; + adc2_data[3] : LOCATION = Pin_17; + adc2_data[4] : LOCATION = Pin_16; + adc2_data[5] : LOCATION = Pin_15; + adc2_data[6] : LOCATION = Pin_14; + adc2_data[7] : LOCATION = Pin_13; + adc2_data[8] : LOCATION = Pin_12; + adc2_data[9] : LOCATION = Pin_11; + adc3_data[0] : LOCATION = Pin_200; + adc3_data[10] : LOCATION = Pin_184; + adc3_data[11] : LOCATION = Pin_183; + adc3_data[1] : LOCATION = Pin_197; + adc3_data[2] : LOCATION = Pin_196; + adc3_data[3] : LOCATION = Pin_195; + adc3_data[4] : LOCATION = Pin_194; + adc3_data[5] : LOCATION = Pin_193; + adc3_data[6] : LOCATION = Pin_188; + adc3_data[7] : LOCATION = Pin_187; + adc3_data[8] : LOCATION = Pin_186; + adc3_data[9] : LOCATION = Pin_185; + adc4_data[0] : LOCATION = Pin_222; + adc4_data[10] : LOCATION = Pin_203; + adc4_data[11] : LOCATION = Pin_202; + adc4_data[1] : LOCATION = Pin_219; + adc4_data[2] : LOCATION = Pin_217; + adc4_data[3] : LOCATION = Pin_216; + adc4_data[4] : LOCATION = Pin_215; + adc4_data[5] : LOCATION = Pin_214; + adc4_data[6] : LOCATION = Pin_213; + adc4_data[7] : LOCATION = Pin_208; + adc4_data[8] : LOCATION = Pin_207; + adc4_data[9] : LOCATION = Pin_206; + adc_oeb[0] : LOCATION = Pin_228; + adc_oeb[1] : LOCATION = Pin_21; + adc_oeb[2] : LOCATION = Pin_181; + adc_oeb[3] : LOCATION = Pin_218; + adc_otr[0] : LOCATION = Pin_233; + adc_otr[1] : LOCATION = Pin_6; + adc_otr[2] : LOCATION = Pin_182; + adc_otr[3] : LOCATION = Pin_201; + adclk0 : LOCATION = Pin_224; + adclk1 : LOCATION = Pin_226; + clk0 : LOCATION = Pin_28; + clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk0 : IO_STANDARD = LVTTL; + clk1 : LOCATION = Pin_29; + clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk1 : IO_STANDARD = LVTTL; + clk3 : LOCATION = Pin_152; + clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk3 : IO_STANDARD = LVTTL; + clk_120mhz : LOCATION = Pin_153; + clk_120mhz : IO_STANDARD = LVTTL; + clk_out : LOCATION = Pin_63; + clk_out : IO_STANDARD = LVTTL; + dac1_data[0] : LOCATION = Pin_165; + dac1_data[10] : LOCATION = Pin_177; + dac1_data[11] : LOCATION = Pin_178; + dac1_data[12] : LOCATION = Pin_179; + dac1_data[13] : LOCATION = Pin_180; + dac1_data[1] : LOCATION = Pin_166; + dac1_data[2] : LOCATION = Pin_167; + dac1_data[3] : LOCATION = Pin_168; + dac1_data[4] : LOCATION = Pin_169; + dac1_data[5] : LOCATION = Pin_170; + dac1_data[6] : LOCATION = Pin_173; + dac1_data[7] : LOCATION = Pin_174; + dac1_data[8] : LOCATION = Pin_175; + dac1_data[9] : LOCATION = Pin_176; + dac2_data[0] : LOCATION = Pin_159; + dac2_data[10] : LOCATION = Pin_163; + dac2_data[11] : LOCATION = Pin_139; + dac2_data[12] : LOCATION = Pin_164; + dac2_data[13] : LOCATION = Pin_138; + dac2_data[1] : LOCATION = Pin_158; + dac2_data[2] : LOCATION = Pin_160; + dac2_data[3] : LOCATION = Pin_156; + dac2_data[4] : LOCATION = Pin_161; + dac2_data[5] : LOCATION = Pin_144; + dac2_data[6] : LOCATION = Pin_162; + dac2_data[7] : LOCATION = Pin_141; + dac2_data[8] : LOCATION = Pin_143; + dac2_data[9] : LOCATION = Pin_140; + dac3_data[0] : LOCATION = Pin_122; + dac3_data[10] : LOCATION = Pin_134; + dac3_data[11] : LOCATION = Pin_135; + dac3_data[12] : LOCATION = Pin_136; + dac3_data[13] : LOCATION = Pin_137; + dac3_data[1] : LOCATION = Pin_123; + dac3_data[2] : LOCATION = Pin_124; + dac3_data[3] : LOCATION = Pin_125; + dac3_data[4] : LOCATION = Pin_126; + dac3_data[5] : LOCATION = Pin_127; + dac3_data[6] : LOCATION = Pin_128; + dac3_data[7] : LOCATION = Pin_131; + dac3_data[8] : LOCATION = Pin_132; + dac3_data[9] : LOCATION = Pin_133; + dac4_data[0] : LOCATION = Pin_104; + dac4_data[10] : LOCATION = Pin_118; + dac4_data[11] : LOCATION = Pin_119; + dac4_data[12] : LOCATION = Pin_120; + dac4_data[13] : LOCATION = Pin_121; + dac4_data[1] : LOCATION = Pin_105; + dac4_data[2] : LOCATION = Pin_106; + dac4_data[3] : LOCATION = Pin_107; + dac4_data[4] : LOCATION = Pin_108; + dac4_data[5] : LOCATION = Pin_113; + dac4_data[6] : LOCATION = Pin_114; + dac4_data[7] : LOCATION = Pin_115; + dac4_data[8] : LOCATION = Pin_116; + dac4_data[9] : LOCATION = Pin_117; + enable_rx : LOCATION = Pin_88; + enable_tx : LOCATION = Pin_93; + gndbus[0] : LOCATION = Pin_223; + gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[0] : IO_STANDARD = LVTTL; + gndbus[1] : LOCATION = Pin_225; + gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[1] : IO_STANDARD = LVTTL; + gndbus[2] : LOCATION = Pin_227; + gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[2] : IO_STANDARD = LVTTL; + gndbus[3] : LOCATION = Pin_62; + gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[3] : IO_STANDARD = LVTTL; + gndbus[4] : LOCATION = Pin_64; + gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[4] : IO_STANDARD = LVTTL; + misc_pins[0] : LOCATION = Pin_87; + misc_pins[0] : IO_STANDARD = LVTTL; + misc_pins[10] : LOCATION = Pin_76; + misc_pins[10] : IO_STANDARD = LVTTL; + misc_pins[11] : LOCATION = Pin_74; + misc_pins[11] : IO_STANDARD = LVTTL; + misc_pins[1] : LOCATION = Pin_86; + misc_pins[1] : IO_STANDARD = LVTTL; + misc_pins[2] : LOCATION = Pin_85; + misc_pins[2] : IO_STANDARD = LVTTL; + misc_pins[3] : LOCATION = Pin_84; + misc_pins[3] : IO_STANDARD = LVTTL; + misc_pins[4] : LOCATION = Pin_83; + misc_pins[4] : IO_STANDARD = LVTTL; + misc_pins[5] : LOCATION = Pin_82; + misc_pins[5] : IO_STANDARD = LVTTL; + misc_pins[6] : LOCATION = Pin_79; + misc_pins[6] : IO_STANDARD = LVTTL; + misc_pins[7] : LOCATION = Pin_78; + misc_pins[7] : IO_STANDARD = LVTTL; + misc_pins[8] : LOCATION = Pin_77; + misc_pins[8] : IO_STANDARD = LVTTL; + misc_pins[9] : LOCATION = Pin_75; + misc_pins[9] : IO_STANDARD = LVTTL; + reset : LOCATION = Pin_94; + usbclk : LOCATION = Pin_55; + usbctl[0] : LOCATION = Pin_56; + usbctl[1] : LOCATION = Pin_54; + usbctl[2] : LOCATION = Pin_53; + usbctl[3] : LOCATION = Pin_58; + usbctl[4] : LOCATION = Pin_57; + usbctl[5] : LOCATION = Pin_44; + usbdata[0] : LOCATION = Pin_73; + usbdata[10] : LOCATION = Pin_41; + usbdata[11] : LOCATION = Pin_39; + usbdata[12] : LOCATION = Pin_38; + usbdata[12] : IO_STANDARD = LVTTL; + usbdata[13] : LOCATION = Pin_37; + usbdata[14] : LOCATION = Pin_24; + usbdata[15] : LOCATION = Pin_23; + usbdata[1] : LOCATION = Pin_68; + usbdata[2] : LOCATION = Pin_67; + usbdata[3] : LOCATION = Pin_66; + usbdata[4] : LOCATION = Pin_65; + usbdata[5] : LOCATION = Pin_61; + usbdata[6] : LOCATION = Pin_60; + usbdata[7] : LOCATION = Pin_59; + usbdata[8] : LOCATION = Pin_43; + usbdata[9] : LOCATION = Pin_42; + usbrdy[0] : LOCATION = Pin_45; + usbrdy[1] : LOCATION = Pin_46; + usbrdy[2] : LOCATION = Pin_47; + usbrdy[3] : LOCATION = Pin_48; + usbrdy[4] : LOCATION = Pin_49; + usbrdy[5] : LOCATION = Pin_50; + clear_status : LOCATION = Pin_99; +} diff --git a/usrp1/toplevel/mrfm/mrfm.esf b/usrp1/toplevel/mrfm/mrfm.esf new file mode 100644 index 000000000..72b84e39e --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm.esf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = mrfm; +} diff --git a/usrp1/toplevel/mrfm/mrfm.psf b/usrp1/toplevel/mrfm/mrfm.psf new file mode 100644 index 000000000..678a7faa2 --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm.psf @@ -0,0 +1,312 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_DSP_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_TURBO_BIT = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_PARALLEL_EXPANDERS = ON; + AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; + AUTO_FAST_OUTPUT_REGISTERS = OFF; + AUTO_FAST_INPUT_REGISTERS = OFF; + AUTO_CASCADE_CHAINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; + PARALLEL_EXPANDER_CHAIN_LENGTH = 16; + CASCADE_CHAIN_LENGTH = 2; + STRATIX_CARRY_CHAIN_LENGTH = 70; + MERCURY_CARRY_CHAIN_LENGTH = 48; + FLEX10K_CARRY_CHAIN_LENGTH = 32; + FLEX6K_CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN_LENGTH = 48; + CARRY_OUT_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + AUTO_LCELL_INSERTION = ON; + ALLOW_XOR_GATE_USAGE = ON; + AUTO_PACKED_REGISTERS_STRATIX = NORMAL; + AUTO_PACKED_REGISTERS = OFF; + AUTO_PACKED_REG_CYCLONE = NORMAL; + FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; + FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; + MERCURY_OPTIMIZATION_TECHNIQUE = AREA; + APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; + MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; + STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; + CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; + FLEX10K_TECHNOLOGY_MAPPER = LUT; + FLEX6K_TECHNOLOGY_MAPPER = LUT; + MERCURY_TECHNOLOGY_MAPPER = LUT; + APEX20K_TECHNOLOGY_MAPPER = LUT; + MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; + STRATIX_TECHNOLOGY_MAPPER = LUT; + AUTO_IMPLEMENT_IN_ROM = OFF; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_CLOCK = ON; + USE_LPM_FOR_AHDL_OPERATORS = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + TURBO_BIT = ON; + MAX7000_IGNORE_SOFT_BUFFERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MAX7000_IGNORE_LCELL_BUFFERS = AUTO; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + DSP_BLOCK_BALANCING = AUTO; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(mrfm) +{ + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; + USER_LIBRARIES = "e:\usrp\fpga\megacells"; +} +THIRD_PARTY_EDA_TOOLS(mrfm) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} +CLOCK(clk_120mhz) +{ + FMAX_REQUIREMENT = "120.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(usbclk) +{ + FMAX_REQUIREMENT = "48.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(SCLK) +{ + FMAX_REQUIREMENT = "1.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk0) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk1) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} diff --git a/usrp1/toplevel/mrfm/mrfm.py b/usrp1/toplevel/mrfm/mrfm.py new file mode 100644 index 000000000..100db69eb --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm.py @@ -0,0 +1,129 @@ +#!/usr/bin/env python +# +# This is mrfm_fft_sos.py +# Modification of Matt's mrfm_fft.py that reads filter coefs from file +# +# Copyright 2004,2005 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru +from gnuradio import usrp + +class source_c(usrp.source_c): + def __init__(self,fpga_filename): + usrp.source_c.__init__(self,which=0, decim_rate=64, nchan=2, mux=0x32103210, mode=0, + fpga_filename=fpga_filename) + + self._write_9862(0,2,0x80) # Bypass ADC buffer, minimum gain + self._write_9862(0,3,0x80) # Bypass ADC buffer, minimum gain + + self._write_9862(0,8,0) # TX PWR Down + self._write_9862(0,10,0) # DAC offset + self._write_9862(0,11,0) # DAC offset + self._write_9862(0,14,0x80) # gain + self._write_9862(0,16,0xff) # pga + self._write_9862(0,18,0x0c) # TX IF + self._write_9862(0,19,0x01) # TX Digital + self._write_9862(0,20,0x00) # TX Mod + + # max/min values are +/-2, so scale is set to make 2 = 32767 + + self._write_fpga_reg(69,0x0e) # debug mux + self._write_fpga_reg(5,-1) + self._write_fpga_reg(7,-1) + self._write_oe(0,0xffff, 0xffff) + self._write_oe(1,0xffff, 0xffff) + self._write_fpga_reg(14,0xf) + + self.decim = None + + def set_coeffs(self,frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11): + def make_val(address,value): + return (address << 16) | (value & 0xffff) + + # gain, scale already included in a's and b's from file + + self._write_fpga_reg(67,make_val(1,b20)) + self._write_fpga_reg(67,make_val(2,b10)) + self._write_fpga_reg(67,make_val(3,b00)) + self._write_fpga_reg(67,make_val(4,a20)) + self._write_fpga_reg(67,make_val(5,a10)) + + self._write_fpga_reg(67,make_val(7,b21)) + self._write_fpga_reg(67,make_val(8,b11)) + self._write_fpga_reg(67,make_val(9,b01)) + self._write_fpga_reg(67,make_val(10,a21)) + self._write_fpga_reg(67,make_val(11,a11)) + + self._write_fpga_reg(68,frac_bits) # Shift + + print "Biquad 0 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b20,b10,b00,a20,a10) + print "Biquad 1 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b21,b11,b01,a21,a11) + + def set_decim_rate(self,rate=None): + i=2 + turn=1 + a=1 + b=1 + while (rate>1) and (i<257): + if (rate/i) * i == rate: + if turn == 1: + if a*i<257: + a = a * i + turn = 0 + elif b*i<257: + b = b * i + turn = 0 + else: + print "Failed to set DECIMATOR" + return self.decim + elif b*i<257: + b = b * i + turn = 1 + elif a*i<257: + a = a * i + turn = 1 + else: + print "Failed to set DECIMATOR" + return self.decim + rate=rate/i + continue + i = i + 1 + if rate > 1: + print "Failed to set DECIMATOR" + return self.decim + else: + self.decim = a*b + print "a = %d b = %d" % (a,b) + self._write_fpga_reg(64,(a-1)*256+(b-1)) # Set actual decimation + + def decim_rate(self): + return self.decim + + def set_center_freq(self,freq): + self._write_fpga_reg(65,int(-freq/64e6*65536*65536)) # set center freq + + def set_compensator(self,a11,a12,a21,a22,shift): + self._write_fpga_reg(70,a11) + self._write_fpga_reg(71,a12) + self._write_fpga_reg(72,a21) + self._write_fpga_reg(73,a22) + self._write_fpga_reg(74,shift) # comp shift + diff --git a/usrp1/toplevel/mrfm/mrfm.qpf b/usrp1/toplevel/mrfm/mrfm.qpf new file mode 100644 index 000000000..959140875 --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm.qpf @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2004 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.0" +DATE = "17:10:11 December 20, 2004" + + +# Active Revisions + +PROJECT_REVISION = "mrfm" diff --git a/usrp1/toplevel/mrfm/mrfm.qsf b/usrp1/toplevel/mrfm/mrfm.qsf new file mode 100644 index 000000000..ba1ae0223 --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm.qsf @@ -0,0 +1,411 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# mrfm_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" +set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2" + +# Pin & Location Assignments +# ========================== +set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" +set_location_assignment PIN_29 -to SCLK +set_location_assignment PIN_117 -to SDI +set_location_assignment PIN_28 -to usbclk +set_location_assignment PIN_107 -to usbctl[0] +set_location_assignment PIN_106 -to usbctl[1] +set_location_assignment PIN_105 -to usbctl[2] +set_location_assignment PIN_100 -to usbdata[0] +set_location_assignment PIN_84 -to usbdata[10] +set_location_assignment PIN_83 -to usbdata[11] +set_location_assignment PIN_82 -to usbdata[12] +set_location_assignment PIN_79 -to usbdata[13] +set_location_assignment PIN_78 -to usbdata[14] +set_location_assignment PIN_77 -to usbdata[15] +set_location_assignment PIN_99 -to usbdata[1] +set_location_assignment PIN_98 -to usbdata[2] +set_location_assignment PIN_95 -to usbdata[3] +set_location_assignment PIN_94 -to usbdata[4] +set_location_assignment PIN_93 -to usbdata[5] +set_location_assignment PIN_88 -to usbdata[6] +set_location_assignment PIN_87 -to usbdata[7] +set_location_assignment PIN_86 -to usbdata[8] +set_location_assignment PIN_85 -to usbdata[9] +set_location_assignment PIN_104 -to usbrdy[0] +set_location_assignment PIN_101 -to usbrdy[1] +set_location_assignment PIN_76 -to FX2_1 +set_location_assignment PIN_75 -to FX2_2 +set_location_assignment PIN_74 -to FX2_3 +set_location_assignment PIN_116 -to io_rx_a[0] +set_location_assignment PIN_115 -to io_rx_a[1] +set_location_assignment PIN_114 -to io_rx_a[2] +set_location_assignment PIN_113 -to io_rx_a[3] +set_location_assignment PIN_108 -to io_rx_a[4] +set_location_assignment PIN_195 -to io_rx_a[5] +set_location_assignment PIN_196 -to io_rx_a[6] +set_location_assignment PIN_197 -to io_rx_a[7] +set_location_assignment PIN_200 -to io_rx_a[8] +set_location_assignment PIN_201 -to io_rx_a[9] +set_location_assignment PIN_202 -to io_rx_a[10] +set_location_assignment PIN_203 -to io_rx_a[11] +set_location_assignment PIN_206 -to io_rx_a[12] +set_location_assignment PIN_207 -to io_rx_a[13] +set_location_assignment PIN_208 -to io_rx_a[14] +set_location_assignment PIN_214 -to io_rx_b[0] +set_location_assignment PIN_215 -to io_rx_b[1] +set_location_assignment PIN_216 -to io_rx_b[2] +set_location_assignment PIN_217 -to io_rx_b[3] +set_location_assignment PIN_218 -to io_rx_b[4] +set_location_assignment PIN_219 -to io_rx_b[5] +set_location_assignment PIN_222 -to io_rx_b[6] +set_location_assignment PIN_223 -to io_rx_b[7] +set_location_assignment PIN_224 -to io_rx_b[8] +set_location_assignment PIN_225 -to io_rx_b[9] +set_location_assignment PIN_226 -to io_rx_b[10] +set_location_assignment PIN_227 -to io_rx_b[11] +set_location_assignment PIN_228 -to io_rx_b[12] +set_location_assignment PIN_233 -to io_rx_b[13] +set_location_assignment PIN_234 -to io_rx_b[14] +set_location_assignment PIN_175 -to io_tx_a[0] +set_location_assignment PIN_176 -to io_tx_a[1] +set_location_assignment PIN_177 -to io_tx_a[2] +set_location_assignment PIN_178 -to io_tx_a[3] +set_location_assignment PIN_179 -to io_tx_a[4] +set_location_assignment PIN_180 -to io_tx_a[5] +set_location_assignment PIN_181 -to io_tx_a[6] +set_location_assignment PIN_182 -to io_tx_a[7] +set_location_assignment PIN_183 -to io_tx_a[8] +set_location_assignment PIN_184 -to io_tx_a[9] +set_location_assignment PIN_185 -to io_tx_a[10] +set_location_assignment PIN_186 -to io_tx_a[11] +set_location_assignment PIN_187 -to io_tx_a[12] +set_location_assignment PIN_188 -to io_tx_a[13] +set_location_assignment PIN_193 -to io_tx_a[14] +set_location_assignment PIN_73 -to io_tx_b[0] +set_location_assignment PIN_68 -to io_tx_b[1] +set_location_assignment PIN_67 -to io_tx_b[2] +set_location_assignment PIN_66 -to io_tx_b[3] +set_location_assignment PIN_65 -to io_tx_b[4] +set_location_assignment PIN_64 -to io_tx_b[5] +set_location_assignment PIN_63 -to io_tx_b[6] +set_location_assignment PIN_62 -to io_tx_b[7] +set_location_assignment PIN_61 -to io_tx_b[8] +set_location_assignment PIN_60 -to io_tx_b[9] +set_location_assignment PIN_59 -to io_tx_b[10] +set_location_assignment PIN_58 -to io_tx_b[11] +set_location_assignment PIN_57 -to io_tx_b[12] +set_location_assignment PIN_56 -to io_tx_b[13] +set_location_assignment PIN_55 -to io_tx_b[14] +set_location_assignment PIN_152 -to master_clk +set_location_assignment PIN_144 -to rx_a_a[0] +set_location_assignment PIN_143 -to rx_a_a[1] +set_location_assignment PIN_141 -to rx_a_a[2] +set_location_assignment PIN_140 -to rx_a_a[3] +set_location_assignment PIN_139 -to rx_a_a[4] +set_location_assignment PIN_138 -to rx_a_a[5] +set_location_assignment PIN_137 -to rx_a_a[6] +set_location_assignment PIN_136 -to rx_a_a[7] +set_location_assignment PIN_135 -to rx_a_a[8] +set_location_assignment PIN_134 -to rx_a_a[9] +set_location_assignment PIN_133 -to rx_a_a[10] +set_location_assignment PIN_132 -to rx_a_a[11] +set_location_assignment PIN_23 -to rx_a_b[0] +set_location_assignment PIN_21 -to rx_a_b[1] +set_location_assignment PIN_20 -to rx_a_b[2] +set_location_assignment PIN_19 -to rx_a_b[3] +set_location_assignment PIN_18 -to rx_a_b[4] +set_location_assignment PIN_17 -to rx_a_b[5] +set_location_assignment PIN_16 -to rx_a_b[6] +set_location_assignment PIN_15 -to rx_a_b[7] +set_location_assignment PIN_14 -to rx_a_b[8] +set_location_assignment PIN_13 -to rx_a_b[9] +set_location_assignment PIN_12 -to rx_a_b[10] +set_location_assignment PIN_11 -to rx_a_b[11] +set_location_assignment PIN_131 -to rx_b_a[0] +set_location_assignment PIN_128 -to rx_b_a[1] +set_location_assignment PIN_127 -to rx_b_a[2] +set_location_assignment PIN_126 -to rx_b_a[3] +set_location_assignment PIN_125 -to rx_b_a[4] +set_location_assignment PIN_124 -to rx_b_a[5] +set_location_assignment PIN_123 -to rx_b_a[6] +set_location_assignment PIN_122 -to rx_b_a[7] +set_location_assignment PIN_121 -to rx_b_a[8] +set_location_assignment PIN_120 -to rx_b_a[9] +set_location_assignment PIN_119 -to rx_b_a[10] +set_location_assignment PIN_118 -to rx_b_a[11] +set_location_assignment PIN_8 -to rx_b_b[0] +set_location_assignment PIN_7 -to rx_b_b[1] +set_location_assignment PIN_6 -to rx_b_b[2] +set_location_assignment PIN_5 -to rx_b_b[3] +set_location_assignment PIN_4 -to rx_b_b[4] +set_location_assignment PIN_3 -to rx_b_b[5] +set_location_assignment PIN_2 -to rx_b_b[6] +set_location_assignment PIN_240 -to rx_b_b[7] +set_location_assignment PIN_239 -to rx_b_b[8] +set_location_assignment PIN_238 -to rx_b_b[9] +set_location_assignment PIN_237 -to rx_b_b[10] +set_location_assignment PIN_236 -to rx_b_b[11] +set_location_assignment PIN_156 -to SDO +set_location_assignment PIN_153 -to SEN_FPGA +set_location_assignment PIN_159 -to tx_a[0] +set_location_assignment PIN_160 -to tx_a[1] +set_location_assignment PIN_161 -to tx_a[2] +set_location_assignment PIN_162 -to tx_a[3] +set_location_assignment PIN_163 -to tx_a[4] +set_location_assignment PIN_164 -to tx_a[5] +set_location_assignment PIN_165 -to tx_a[6] +set_location_assignment PIN_166 -to tx_a[7] +set_location_assignment PIN_167 -to tx_a[8] +set_location_assignment PIN_168 -to tx_a[9] +set_location_assignment PIN_169 -to tx_a[10] +set_location_assignment PIN_170 -to tx_a[11] +set_location_assignment PIN_173 -to tx_a[12] +set_location_assignment PIN_174 -to tx_a[13] +set_location_assignment PIN_38 -to tx_b[0] +set_location_assignment PIN_39 -to tx_b[1] +set_location_assignment PIN_41 -to tx_b[2] +set_location_assignment PIN_42 -to tx_b[3] +set_location_assignment PIN_43 -to tx_b[4] +set_location_assignment PIN_44 -to tx_b[5] +set_location_assignment PIN_45 -to tx_b[6] +set_location_assignment PIN_46 -to tx_b[7] +set_location_assignment PIN_47 -to tx_b[8] +set_location_assignment PIN_48 -to tx_b[9] +set_location_assignment PIN_49 -to tx_b[10] +set_location_assignment PIN_50 -to tx_b[11] +set_location_assignment PIN_53 -to tx_b[12] +set_location_assignment PIN_54 -to tx_b[13] +set_location_assignment PIN_158 -to TXSYNC_A +set_location_assignment PIN_37 -to TXSYNC_B +set_location_assignment PIN_235 -to io_rx_b[15] +set_location_assignment PIN_24 -to io_tx_b[15] +set_location_assignment PIN_213 -to io_rx_a[15] +set_location_assignment PIN_194 -to io_tx_a[15] +set_location_assignment PIN_1 -to MYSTERY_SIGNAL + +# Timing Assignments +# ================== +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name TOP_LEVEL_ENTITY mrfm +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name INC_PLC_MODE OFF +set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF +set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# Timing Analysis Assignments +# =========================== +set_global_assignment -name MAX_SCC_SIZE 50 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF + +# Simulator Assignments +# ===================== +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "1 ns" + +# Design Assistant Assignments +# ============================ +set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF +set_global_assignment -name ASSG_CAT OFF +set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF +set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF +set_global_assignment -name CLK_CAT OFF +set_global_assignment -name CLK_RULE_COMB_CLOCK OFF +set_global_assignment -name CLK_RULE_INV_CLOCK OFF +set_global_assignment -name CLK_RULE_GATING_SCHEME OFF +set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF +set_global_assignment -name CLK_RULE_MIX_EDGES OFF +set_global_assignment -name RESET_CAT OFF +set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name TIMING_CAT OFF +set_global_assignment -name TIMING_RULE_SHIFT_REG OFF +set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF +set_global_assignment -name NONSYNCHSTRUCT_CAT OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF +set_global_assignment -name SIGNALRACE_CAT OFF +set_global_assignment -name ACLK_CAT OFF +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF +set_global_assignment -name HCPY_CAT OFF +set_global_assignment -name HCPY_VREF_PINS OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name HUB_ENTITY_NAME SLD_HUB +set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST +set_global_assignment -name ENABLE_SIGNALTAP OFF + +# LogicLock Region Assignments +# ============================ +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF + +# ----------------- +# start CLOCK(SCLK) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK +set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK + +# end CLOCK(SCLK) +# --------------- + +# ----------------------- +# start CLOCK(master_clk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk +set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk + +# end CLOCK(master_clk) +# --------------------- + +# ------------------- +# start CLOCK(usbclk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk +set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk + +# end CLOCK(usbclk) +# ----------------- + +# ---------------------- +# start ENTITY(mrfm) + + # Timing Assignments + # ================== +set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK +set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk +set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk + +# end ENTITY(mrfm) +# -------------------- + + +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name VERILOG_FILE mrfm.vh +set_global_assignment -name VERILOG_FILE biquad_2stage.v +set_global_assignment -name VERILOG_FILE mrfm_compensator.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v +set_global_assignment -name VERILOG_FILE mrfm_proc.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v +set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v +set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v +set_global_assignment -name VERILOG_FILE mrfm.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" \ No newline at end of file diff --git a/usrp1/toplevel/mrfm/mrfm.v b/usrp1/toplevel/mrfm/mrfm.v new file mode 100644 index 000000000..7a0e38059 --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm.v @@ -0,0 +1,199 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Top level module for a full setup with DUCs and DDCs + +// Uncomment the following to include optional circuitry + +`include "mrfm.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module mrfm +(output MYSTERY_SIGNAL, + input master_clk, + input SCLK, + input SDI, + inout SDO, + input SEN_FPGA, + + input FX2_1, + output FX2_2, + output FX2_3, + + input wire [11:0] rx_a_a, + input wire [11:0] rx_b_a, + input wire [11:0] rx_a_b, + input wire [11:0] rx_b_b, + + output wire [13:0] tx_a, + output wire [13:0] tx_b, + + output wire TXSYNC_A, + output wire TXSYNC_B, + + // USB interface + input usbclk, + input wire [2:0] usbctl, + output wire [1:0] usbrdy, + inout [15:0] usbdata, // NB Careful, inout + + // These are the general purpose i/o's that go to the daughterboard slots + inout wire [15:0] io_tx_a, + inout wire [15:0] io_tx_b, + inout wire [15:0] io_rx_a, + inout wire [15:0] io_rx_b + ); + wire [15:0] debugdata,debugctrl; + assign MYSTERY_SIGNAL = 1'b0; + + wire clk64; + + wire WR = usbctl[0]; + wire RD = usbctl[1]; + wire OE = usbctl[2]; + + wire have_space, have_pkt_rdy; + assign usbrdy[0] = have_space; + assign usbrdy[1] = have_pkt_rdy; + + wire tx_underrun, rx_overrun; + wire clear_status = FX2_1; + assign FX2_2 = rx_overrun; + assign FX2_3 = tx_underrun; + + wire [15:0] usbdata_out; + + wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; + + wire tx_realsignals; + wire [3:0] rx_numchan; + + wire [15:0] tx_debugbus, rx_debugbus; + + wire enable_tx, enable_rx; + wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; + wire [7:0] settings; + + // Tri-state bus macro + bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); + + assign clk64 = master_clk; + + wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; + wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; + + wire serial_strobe; + wire [6:0] serial_addr; + wire [31:0] serial_data; + + ///////////////////////////////////////////////////////////////////////////////////////////////////// + + setting_reg #(`FR_TX_MUX) + sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + ////////////////////////////////////////////////////////////////////////////////////////////////////// + // Signal Processing Chain + + reg [15:0] adc0; + wire [15:0] dac0; + wire [15:0] i,q,ip,qp; + wire strobe_out; + wire sync_out; + + always @(posedge clk64) + adc0 <= #1 {rx_a_a[11],rx_a_a[11:0],3'b0}; + + wire [15:0] adc0_corr; + rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0_corr), + .serial_addr(7'd0),.serial_data(32'd0),.serial_strobe(1'b0)); + + //wire [63:0] filt_debug = 64'd0; + + mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .signal_in(adc0_corr),.signal_out(dac0),.sync_out(sync_out), + .i(i),.q(q),.ip(ip),.qp(qp),.strobe_out(strobe_out), + .debugbus( /* filt_debug */ )); + + wire txsync = 1'b0; + assign TXSYNC_A = txsync; + assign TXSYNC_B = txsync; + + assign tx_a = dac0[15:2]; + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Data Collection on RX Buffer + + assign rx_numchan[0] = 1'b0; + setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr), + .in(serial_data),.out(rx_numchan[3:1])); + + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(i),.ch_1(q), + .ch_2(ip),.ch_3(qp), + .ch_4(16'd0),.ch_5(16'd0), + .ch_6(16'd0),.ch_7(16'd0), + .rxclk(clk64),.rxstrobe(strobe_out), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .debugbus(rx_debugbus) ); + + ////////////////////////////////////////////////////////////////////////////// + // Control Functions + + wire [31:0] capabilities = 32'd2; + + serial_io serial_io + ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), + .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) ); + + wire [15:0] reg_0,reg_1,reg_2,reg_3; + master_control master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + .debug_0({15'd0,sync_out}), //filt_debug[63:48]), + .debug_1({15'd0,sync_out}), //filt_debug[47:32]), + .debug_2({15'd0,sync_out}), //filt_debug[31:16]), + .debug_3({15'd0,sync_out}), //filt_debug[15:0]), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + + io_pins io_pins + (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + +endmodule // mrfm + diff --git a/usrp1/toplevel/mrfm/mrfm.vh b/usrp1/toplevel/mrfm/mrfm.vh new file mode 100644 index 000000000..808342d8d --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm.vh @@ -0,0 +1,21 @@ + + +// MRFM Register defines + +`define FR_MRFM_DECIM 7'd64 +`define FR_MRFM_FREQ 7'd65 +`define FR_MRFM_PHASE 7'd66 +`define FR_MRFM_IIR_COEFF 7'd67 +`define FR_MRFM_IIR_SHIFT 7'd68 +`define FR_MRFM_DEBUG 7'd69 +`define FR_MRFM_COMP_A11 7'd70 +`define FR_MRFM_COMP_A12 7'd71 +`define FR_MRFM_COMP_A21 7'd72 +`define FR_MRFM_COMP_A22 7'd73 +`define FR_MRFM_COMP_SHIFT 7'd74 +`define FR_USER_11 7'd75 +`define FR_USER_12 7'd76 +`define FR_USER_13 7'd77 +`define FR_USER_14 7'd78 +`define FR_USER_15 7'd79 + diff --git a/usrp1/toplevel/mrfm/mrfm_compensator.v b/usrp1/toplevel/mrfm/mrfm_compensator.v new file mode 100644 index 000000000..f44b73b2f --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm_compensator.v @@ -0,0 +1,80 @@ + + +module mrfm_compensator (input clock, input reset, input strobe_in, + input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, + input [15:0] i_in, input [15:0] q_in, output reg [15:0] i_out, output reg [15:0] q_out); + + wire [15:0] a11,a12,a21,a22; + reg [15:0] i_in_reg, q_in_reg; + wire [30:0] product; + reg [3:0] phase; + wire [15:0] data,coeff; + wire [7:0] shift; + wire [33:0] accum; + wire [15:0] scaled_accum; + wire enable_acc; + + setting_reg #(`FR_MRFM_COMP_A11) sr_a11(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(a11),.changed()); + setting_reg #(`FR_MRFM_COMP_A12) sr_a12(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(a12),.changed()); + setting_reg #(`FR_MRFM_COMP_A21) sr_a21(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(a21),.changed()); + setting_reg #(`FR_MRFM_COMP_A22) sr_a22(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(a22),.changed()); + setting_reg #(`FR_MRFM_COMP_SHIFT) sr_cshift(.clock(clock),.reset(reset), + .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out(shift),.changed()); + + mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(1'b1),.enable_out() ); + acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), + .addend(product),.sum(accum) ); + shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); + + always @(posedge clock) + if(reset) + begin + i_in_reg <= #1 16'd0; + q_in_reg <= #1 16'd0; + end + else if(strobe_in) + begin + i_in_reg <= #1 i_in; + q_in_reg <= #1 q_in; + end + + always @(posedge clock) + if(reset) + phase <= #1 4'd0; + else if(strobe_in) + phase <= #1 4'd1; + else if(strobe_in != 4'd8) + phase <= #1 phase + 4'd1; + + assign data = ((phase == 4'd1)||(phase === 4'd4)) ? i_in_reg : + ((phase == 4'd2)||(phase == 4'd5)) ? q_in_reg : 16'd0; + + assign coeff = (phase == 4'd1) ? a11 : (phase == 4'd2) ? a12 : + (phase == 4'd4) ? a21 : (phase == 4'd5) ? a22 : 16'd0; + + assign clear_acc = (phase == 4'd0) || (phase == 4'd1) || (phase == 4'd4) || (phase==4'd8); + assign enable_acc = ~clear_acc; + + always @(posedge clock) + if(reset) + i_out <= #1 16'd0; + else if(phase == 4'd4) + i_out <= #1 scaled_accum; + + always @(posedge clock) + if(reset) + q_out <= #1 16'd0; + else if(phase == 4'd7) + q_out <= #1 scaled_accum; + + +endmodule // mrfm_compensator diff --git a/usrp1/toplevel/mrfm/mrfm_fft.py b/usrp1/toplevel/mrfm/mrfm_fft.py new file mode 100755 index 000000000..a4db0a53d --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm_fft.py @@ -0,0 +1,319 @@ +#!/usr/bin/env python +# +# This is mrfm_fft_sos.py +# Modification of Matt's mrfm_fft.py that reads filter coefs from file +# +# Copyright 2004,2005 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru +from gnuradio import usrp +from gnuradio import eng_notation +from gnuradio.eng_option import eng_option +from gnuradio.wxgui import stdgui, fftsink, waterfallsink, scopesink, form, slider +from optparse import OptionParser +import wx +import sys +import mrfm + + +def pick_subdevice(u): + """ + The user didn't specify a subdevice on the command line. + If there's a daughterboard on A, select A. + If there's a daughterboard on B, select B. + Otherwise, select A. + """ + if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a problem + return (0, 0) + if u.db[1][0].dbid() >= 0: + return (1, 0) + return (0, 0) + +def read_ints(filename): + try: + f = open(filename) + ints = [ int(i) for i in f.read().split() ] + f.close() + return ints + except: + return [] + +class app_flow_graph(stdgui.gui_flow_graph): + def __init__(self, frame, panel, vbox, argv): + stdgui.gui_flow_graph.__init__(self) + + self.frame = frame + self.panel = panel + + parser = OptionParser(option_class=eng_option) + parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, + help="select USRP Rx side A or B (default=first one with a daughterboard)") + parser.add_option("-d", "--decim", type="int", default=16, + help="set fgpa decimation rate to DECIM [default=%default]") + parser.add_option("-f", "--freq", type="eng_float", default=None, + help="set frequency to FREQ", metavar="FREQ") + parser.add_option("-g", "--gain", type="eng_float", default=None, + help="set gain in dB (default is midpoint)") + parser.add_option("-W", "--waterfall", action="store_true", default=False, + help="Enable waterfall display") + parser.add_option("-8", "--width-8", action="store_true", default=False, + help="Enable 8-bit samples across USB") + parser.add_option("-S", "--oscilloscope", action="store_true", default=False, + help="Enable oscilloscope display") + parser.add_option("-F", "--filename", default=None, + help="Name of file with filter coefficients") + parser.add_option("-C", "--cfilename", default=None, + help="Name of file with compensator coefficients") + parser.add_option("-B", "--bitstream", default="mrfm.rbf", + help="Name of FPGA Bitstream file (.rbf)") + parser.add_option("-n", "--frame-decim", type="int", default=20, + help="set oscope frame decimation factor to n [default=12]") + (options, args) = parser.parse_args() + if len(args) != 0: + parser.print_help() + sys.exit(1) + + self.show_debug_info = True + + # default filter coefs + b00 = b01 = 16384 + b10 = b20 = a10 = a20 = b11 = b21 = a11 = a21 = 0 + + ba = read_ints(options.filename) + if len(ba) >= 6: + b00 = ba[0]; b10 = ba[1]; b20 = ba[2]; a10 = ba[4]; a20 = ba[5] + if len(ba) >= 12: + b01 = ba[6]; b11 = ba[7]; b21 = ba[8]; a11 = ba[10]; a21=ba[11] + print b00, b10, b20, a10, a20, b01, b11, b21, a11, a21 + + # default compensator coefficients + c11 = c22 = 1 + c12 = c21 = cscale = 0 + + cs = read_ints(options.cfilename) + if len(cs) >= 5: + c11 = cs[0]; c12 = cs[1]; c21 = cs[2]; c22 = cs[3]; cscale = cs[4] + print c11, c12, c21, c22, cscale + + # build the graph + self.u = mrfm.source_c(options.bitstream) + + self.u.set_decim_rate(options.decim) + self.u.set_center_freq(options.freq) + + frac_bits = 14 + self.u.set_coeffs(frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11) + + self.u.set_compensator(c11,c12,c21,c22,cscale) + + if options.rx_subdev_spec is None: + options.rx_subdev_spec = pick_subdevice(self.u) + self.u.set_mux(usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec)) + + if options.width_8: + width = 8 + shift = 8 + format = self.u.make_format(width, shift) + print "format =", hex(format) + r = self.u.set_format(format) + print "set_format =", r + + # determine the daughterboard subdevice we're using + self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec) + + #input_rate = self.u.adc_freq() / self.u.decim_rate() + input_rate = self.u.adc_freq() / options.decim + + # fft_rate = 15 + fft_rate = 5 + + self.deint = gr.deinterleave(gr.sizeof_gr_complex) + self.connect(self.u,self.deint) + + if options.waterfall: + self.scope1=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, + fft_rate=fft_rate) + self.scope2=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, + fft_rate=fft_rate) + + elif options.oscilloscope: + self.scope1 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) # added option JPJ 4/21/2006 + self.scope2 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) + + else: + self.scope1 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, + fft_rate=fft_rate) + self.scope2 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, + fft_rate=fft_rate) + + # Show I, I' on top scope panel, Q, Q' on bottom + #self.fin = gr.complex_to_float() + #self.fout = gr.complex_to_float() + + #self.connect((self.deint,0), self.fin) + #self.connect((self.deint,1), self.fout) + + #self.ii = gr.float_to_complex() + #self.qq = gr.float_to_complex() + + #self.connect((self.fin,0), (self.ii,0)) + #self.connect((self.fout,0), (self.ii,1)) + #self.connect((self.fin,1), (self.qq,0)) + #self.connect((self.fout,1), (self.qq,1)) + + #self.connect(self.ii, self.scope1) + #self.connect(self.qq, self.scope2) + + self.connect ((self.deint,0),self.scope1) + self.connect ((self.deint,1),self.scope2) + + self._build_gui(vbox) + + # set initial values + + if options.gain is None: + # if no gain was specified, use the mid-point in dB + g = self.subdev.gain_range() + options.gain = float(g[0]+g[1])/2 + + if options.freq is None: + # if no freq was specified, use the mid-point + r = self.subdev.freq_range() + options.freq = float(r[0]+r[1])/2 + + self.set_gain(options.gain) + + if not(self.set_freq(options.freq)): + self._set_status_msg("Failed to set initial frequency") + + if self.show_debug_info: + self.myform['decim'].set_value(self.u.decim_rate()) + self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) + self.myform['dbname'].set_value(self.subdev.name()) + + + def _set_status_msg(self, msg): + self.frame.GetStatusBar().SetStatusText(msg, 0) + + def _build_gui(self, vbox): + + def _form_set_freq(kv): + return self.set_freq(kv['freq']) + + vbox.Add(self.scope1.win, 10, wx.EXPAND) + vbox.Add(self.scope2.win, 10, wx.EXPAND) + + # add control area at the bottom + self.myform = myform = form.form() + hbox = wx.BoxSizer(wx.HORIZONTAL) + hbox.Add((5,0), 0, 0) + myform['freq'] = form.float_field( + parent=self.panel, sizer=hbox, label="Center freq", weight=1, + callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) + + hbox.Add((5,0), 0, 0) + g = self.subdev.gain_range() + myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain", + weight=3, + min=int(g[0]), max=int(g[1]), + callback=self.set_gain) + + hbox.Add((5,0), 0, 0) + vbox.Add(hbox, 0, wx.EXPAND) + + self._build_subpanel(vbox) + + def _build_subpanel(self, vbox_arg): + # build a secondary information panel (sometimes hidden) + + # FIXME figure out how to have this be a subpanel that is always + # created, but has its visibility controlled by foo.Show(True/False) + + if not(self.show_debug_info): + return + + panel = self.panel + vbox = vbox_arg + myform = self.myform + + #panel = wx.Panel(self.panel, -1) + #vbox = wx.BoxSizer(wx.VERTICAL) + + hbox = wx.BoxSizer(wx.HORIZONTAL) + hbox.Add((5,0), 0) + myform['decim'] = form.static_float_field( + parent=panel, sizer=hbox, label="Decim") + + hbox.Add((5,0), 1) + myform['fs@usb'] = form.static_float_field( + parent=panel, sizer=hbox, label="Fs@USB") + + hbox.Add((5,0), 1) + myform['dbname'] = form.static_text_field( + parent=panel, sizer=hbox) + + hbox.Add((5,0), 1) + myform['baseband'] = form.static_float_field( + parent=panel, sizer=hbox, label="Analog BB") + + hbox.Add((5,0), 1) + myform['ddc'] = form.static_float_field( + parent=panel, sizer=hbox, label="DDC") + + hbox.Add((5,0), 0) + vbox.Add(hbox, 0, wx.EXPAND) + + + + def set_freq(self, target_freq): + """ + Set the center frequency we're interested in. + + @param target_freq: frequency in Hz + @rypte: bool + + Tuning is a two step process. First we ask the front-end to + tune as close to the desired frequency as it can. Then we use + the result of that operation and our target_frequency to + determine the value for the digital down converter. + """ + r = self.u.tune(0, self.subdev, target_freq) + + if r: + self.myform['freq'].set_value(target_freq) # update displayed value + if self.show_debug_info: + self.myform['baseband'].set_value(r.baseband_freq) + self.myform['ddc'].set_value(r.dxc_freq) + return True + + return False + + def set_gain(self, gain): + self.myform['gain'].set_value(gain) # update displayed value + self.subdev.set_gain(gain) + + +def main (): + app = stdgui.stdapp(app_flow_graph, "USRP FFT", nstatus=1) + app.MainLoop() + +if __name__ == '__main__': + main () diff --git a/usrp1/toplevel/mrfm/mrfm_proc.v b/usrp1/toplevel/mrfm/mrfm_proc.v new file mode 100644 index 000000000..80de9fc90 --- /dev/null +++ b/usrp1/toplevel/mrfm/mrfm_proc.v @@ -0,0 +1,96 @@ + +`include "mrfm.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module mrfm_proc (input clock, input reset, input enable, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, + input [15:0] signal_in, output wire [15:0] signal_out, output wire sync_out, + output wire [15:0] i, output wire [15:0] q, + output wire [15:0] ip, output wire [15:0] qp, + output wire strobe_out, output wire [63:0] debugbus); + + // Strobes + wire sample_strobe, strobe_0, strobe_1, strobe_2; + assign sample_strobe = 1'b1; + wire [7:0] rate_0, rate_1, rate_2; + + setting_reg #(`FR_MRFM_DECIM) sr_decim(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out({rate_2,rate_1,rate_0})); + + strobe_gen strobe_gen_0 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(sample_strobe),.strobe(strobe_0) ); + strobe_gen strobe_gen_1 + ( .clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_0),.strobe(strobe_1) ); + + wire [31:0] phase; + + assign sync_out = phase[31]; + wire [15:0] i_decim_0, i_decim_1, i_decim_2; + wire [15:0] q_decim_0, q_decim_1, q_decim_2; + + wire [15:0] i_interp_0, i_interp_1, i_interp_2; + wire [15:0] q_interp_0, q_interp_1, q_interp_2; + + wire [15:0] i_filt, q_filt, i_comp, q_comp; + + assign ip=i_comp; + assign qp=q_comp; + + phase_acc #(`FR_MRFM_FREQ,`FR_MRFM_PHASE,32) rx_phase_acc + (.clk(clock),.reset(reset),.enable(enable), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .strobe(sample_strobe),.phase(phase) ); + + cordic rx_cordic (.clock(clock),.reset(reset),.enable(enable), + .xi(signal_in),.yi(16'd0),.zi(phase[31:16]), + .xo(i_decim_0),.yo(q_decim_0),.zo() ); + + cic_decim cic_decim_i_0 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), + .signal_in(i_decim_0),.signal_out(i_decim_1)); + cic_decim cic_decim_i_1 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), + .signal_in(i_decim_1),.signal_out(i)); + + cic_decim cic_decim_q_0 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), + .signal_in(q_decim_0),.signal_out(q_decim_1)); + cic_decim cic_decim_q_1 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), + .signal_in(q_decim_1),.signal_out(q)); + + assign strobe_out = strobe_1; + + biquad_2stage iir_i (.clock(clock),.reset(reset),.strobe_in(strobe_1), + .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), + .sample_in(i),.sample_out(i_filt),.debugbus(debugbus)); + + biquad_2stage iir_q (.clock(clock),.reset(reset),.strobe_in(strobe_1), + .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), + .sample_in(q),.sample_out(q_filt),.debugbus()); + + mrfm_compensator compensator (.clock(clock),.reset(reset),.strobe_in(strobe_1), + .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), + .i_in(i_filt),.q_in(q_filt),.i_out(i_comp),.q_out(q_comp)); + + cic_interp cic_interp_i_0 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), + .signal_in(i_comp),.signal_out(i_interp_0)); + cic_interp cic_interp_i_1 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), + .signal_in(i_interp_0),.signal_out(i_interp_1)); + + cic_interp cic_interp_q_0 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), + .signal_in(q_comp),.signal_out(q_interp_0)); + cic_interp cic_interp_q_1 (.clock(clock),.reset(reset),.enable(enable), + .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), + .signal_in(q_interp_0),.signal_out(q_interp_1)); + + cordic tx_cordic (.clock(clock),.reset(reset),.enable(enable), + .xi(i_interp_1),.yi(q_interp_1),.zi(-phase[31:16]), + .xo(signal_out),.yo(),.zo() ); + +endmodule // mrfm_proc diff --git a/usrp1/toplevel/mrfm/shifter.v b/usrp1/toplevel/mrfm/shifter.v new file mode 100644 index 000000000..dd4d4b527 --- /dev/null +++ b/usrp1/toplevel/mrfm/shifter.v @@ -0,0 +1,106 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2005,2006 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module shifter(input wire [33:0] in, output wire [15:0] out, input wire [7:0] shift); + // Wish we could do assign out = in[15+shift:shift]; + + reg [15:0] quotient, remainder; + wire [15:0] out_unclipped; + reg [18:0] msbs; + wire in_range; + + always @* + case(shift) + 0 : quotient = in[15:0]; + 1 : quotient = in[16:1]; + 2 : quotient = in[17:2]; + 3 : quotient = in[18:3]; + 4 : quotient = in[19:4]; + 5 : quotient = in[20:5]; + 6 : quotient = in[21:6]; + 7 : quotient = in[22:7]; + 8 : quotient = in[23:8]; + 9 : quotient = in[24:9]; + 10 : quotient = in[25:10]; + 11 : quotient = in[26:11]; + 12 : quotient = in[27:12]; + 13 : quotient = in[28:13]; + 14 : quotient = in[29:14]; + 15 : quotient = in[30:15]; + 16 : quotient = in[31:16]; + 17 : quotient = in[32:17]; + 18 : quotient = in[33:18]; + default : quotient = in[15:0]; + endcase // case(shift) + + always @* + case(shift) + 0 : remainder = 16'b0; + 1 : remainder = {in[0],15'b0}; + 2 : remainder = {in[1:0],14'b0}; + 3 : remainder = {in[2:0],13'b0}; + 4 : remainder = {in[3:0],12'b0}; + 5 : remainder = {in[4:0],11'b0}; + 6 : remainder = {in[5:0],10'b0}; + 7 : remainder = {in[6:0],9'b0}; + 8 : remainder = {in[7:0],8'b0}; + 9 : remainder = {in[8:0],7'b0}; + 10 : remainder = {in[9:0],6'b0}; + 11 : remainder = {in[10:0],5'b0}; + 12 : remainder = {in[11:0],4'b0}; + 13 : remainder = {in[12:0],3'b0}; + 14 : remainder = {in[13:0],2'b0}; + 15 : remainder = {in[14:0],1'b0}; + 16 : remainder = in[15:0]; + 17 : remainder = in[16:1]; + 18 : remainder = in[17:2]; + default : remainder = 16'b0; + endcase // case(shift) + + always @* + case(shift) + 0 : msbs = in[33:15]; + 1 : msbs = {in[33],in[33:16]}; + 2 : msbs = {{2{in[33]}},in[33:17]}; + 3 : msbs = {{3{in[33]}},in[33:18]}; + 4 : msbs = {{4{in[33]}},in[33:19]}; + 5 : msbs = {{5{in[33]}},in[33:20]}; + 6 : msbs = {{6{in[33]}},in[33:21]}; + 7 : msbs = {{7{in[33]}},in[33:22]}; + 8 : msbs = {{8{in[33]}},in[33:23]}; + 9 : msbs = {{9{in[33]}},in[33:24]}; + 10 : msbs = {{10{in[33]}},in[33:25]}; + 11 : msbs = {{11{in[33]}},in[33:26]}; + 12 : msbs = {{12{in[33]}},in[33:27]}; + 13 : msbs = {{13{in[33]}},in[33:28]}; + 14 : msbs = {{14{in[33]}},in[33:29]}; + 15 : msbs = {{15{in[33]}},in[33:30]}; + 16 : msbs = {{16{in[33]}},in[33:31]}; + 17 : msbs = {{17{in[33]}},in[33:32]}; + 18 : msbs = {{18{in[33]}},in[33]}; + default : msbs = in[33:15]; + endcase // case(shift) + + assign in_range = &msbs | ~(|msbs); + assign out_unclipped = quotient + (in[33] & |remainder); + assign out = in_range ? out_unclipped : {in[33],{15{~in[33]}}}; + +endmodule // shifter diff --git a/usrp1/toplevel/sizetest/.gitignore b/usrp1/toplevel/sizetest/.gitignore new file mode 100644 index 000000000..201434ddc --- /dev/null +++ b/usrp1/toplevel/sizetest/.gitignore @@ -0,0 +1,15 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/db diff --git a/usrp1/toplevel/sizetest/sizetest.csf b/usrp1/toplevel/sizetest/sizetest.csf new file mode 100644 index 000000000..4b724e7f5 --- /dev/null +++ b/usrp1/toplevel/sizetest/sizetest.csf @@ -0,0 +1,160 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = OFF; + OPTIMIZE_TIMING = OFF; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = ON; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |sizetest; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +CHIP(sizetest) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} diff --git a/usrp1/toplevel/sizetest/sizetest.psf b/usrp1/toplevel/sizetest/sizetest.psf new file mode 100644 index 000000000..e4fc6aa27 --- /dev/null +++ b/usrp1/toplevel/sizetest/sizetest.psf @@ -0,0 +1,228 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + STRATIX_CARRY_CHAIN_LENGTH = 70; + AUTO_PACKED_REG_CYCLONE = "MINIMIZE AREA WITH CHAINS"; + CYCLONE_OPTIMIZATION_TECHNIQUE = SPEED; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_CLOCK = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + IGNORE_SOFT_BUFFERS = ON; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(sizetest) +{ + USER_LIBRARIES = "e:\fpga\megacells\"; + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "22:00:25 SEPTEMBER 28, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; +} +THIRD_PARTY_EDA_TOOLS(sizetest) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} diff --git a/usrp1/toplevel/sizetest/sizetest.quartus b/usrp1/toplevel/sizetest/sizetest.quartus new file mode 100644 index 000000000..d1eaf227a --- /dev/null +++ b/usrp1/toplevel/sizetest/sizetest.quartus @@ -0,0 +1,19 @@ +COMPILER_SETTINGS_LIST +{ + COMPILER_SETTINGS = sizetest; +} +SIMULATOR_SETTINGS_LIST +{ + SIMULATOR_SETTINGS = sizetest; +} +SOFTWARE_SETTINGS_LIST +{ + SOFTWARE_SETTINGS = Debug; + SOFTWARE_SETTINGS = Release; +} +FILES +{ + VERILOG_FILE = ..\..\sdr_lib\cordic_stage.v; + VERILOG_FILE = ..\..\sdr_lib\cordic.v; + VERILOG_FILE = sizetest.v; +} diff --git a/usrp1/toplevel/sizetest/sizetest.ssf b/usrp1/toplevel/sizetest/sizetest.ssf new file mode 100644 index 000000000..1aceab1f1 --- /dev/null +++ b/usrp1/toplevel/sizetest/sizetest.ssf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = sizetest; +} diff --git a/usrp1/toplevel/sizetest/sizetest.v b/usrp1/toplevel/sizetest/sizetest.v new file mode 100644 index 000000000..5a847b961 --- /dev/null +++ b/usrp1/toplevel/sizetest/sizetest.v @@ -0,0 +1,39 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +module sizetest(input clock, + input reset, + input enable, + input [15:0]xi, + input [15:0] yi, + input [15:0] zi, + output [15:0] xo, + output [15:0] yo, + output [15:0] zo +// input [15:0] constant + ); + +wire [16:0] zo; + +cordic_stage cordic_stage(clock, reset, enable, xi, yi, zi, 16'd16383, xo, yo, zo ); + +endmodule diff --git a/usrp1/toplevel/usrp_inband_usb/.gitignore b/usrp1/toplevel/usrp_inband_usb/.gitignore new file mode 100644 index 000000000..2cc25f0f2 --- /dev/null +++ b/usrp1/toplevel/usrp_inband_usb/.gitignore @@ -0,0 +1,16 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/*.summary +/db diff --git a/usrp1/toplevel/usrp_inband_usb/config.vh b/usrp1/toplevel/usrp_inband_usb/config.vh new file mode 100644 index 000000000..007a529e3 --- /dev/null +++ b/usrp1/toplevel/usrp_inband_usb/config.vh @@ -0,0 +1,53 @@ + // -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006,2007 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ==================================================================== +// User control over what parts get included +// +// >>>> EDIT ONLY THIS SECTION <<<< +// Uncomment only ONE configuration +// ==================================================================== + +// ==================================================================== +// FIXME drive configuration selection from the command line and/or gui +// ==================================================================== + +// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel + `include "../include/common_config_1rxhb_1tx.vh" + +// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels +// `include "../include/common_config_2rxhb_2tx.vh" + +// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_4rx_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels +//`include "../include/common_config_2rxhb_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_2rx_0tx.vh" + +// Add other "known to fit" configurations here... + +// ==================================================================== +// Now include the common footer +// ==================================================================== + `include "../include/common_config_bottom.vh" diff --git a/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.csf b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.csf new file mode 100644 index 000000000..c10cff92c --- /dev/null +++ b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.csf @@ -0,0 +1,444 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; + OPTIMIZE_TIMING = "NORMAL COMPILATION"; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = OFF; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |usrp_inband_usb; + ROUTING_BACK_ANNOTATION_MODE = OFF; + INC_PLC_MODE = OFF; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} +CHIP(usrp_inband_usb) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; + AUTO_RESTART_CONFIGURATION = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + USER_START_UP_CLOCK = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_JTAG_BST_SUPPORT = OFF; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + USE_CONFIGURATION_DEVICE = OFF; + APEX20K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + STRATIX_UPDATE_MODE = STANDARD; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + COMPRESSION_MODE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + GENERATE_TTF_FILE = OFF; + GENERATE_RBF_FILE = ON; + GENERATE_HEX_FILE = OFF; + SECURITY_BIT = OFF; + ENABLE_VREFA_PIN = OFF; + ENABLE_VREFB_PIN = OFF; + GENERATE_SVF_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_JBC_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_HEXOUT_FILE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; + BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; + HEXOUT_FILE_START_ADDRESS = 0; + HEXOUT_FILE_COUNT_DIRECTION = UP; + RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; + STRATIX_DEVICE_IO_STANDARD = LVTTL; + CLOCK_SOURCE = INTERNAL; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CONFIGURATION_CLOCK_DIVISOR = 1; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + SCLK : LOCATION = Pin_101; + SDI : LOCATION = Pin_100; + SEN : LOCATION = Pin_98; + SLD : LOCATION = Pin_95; + adc1_data[0] : LOCATION = Pin_5; + adc1_data[10] : LOCATION = Pin_235; + adc1_data[11] : LOCATION = Pin_234; + adc1_data[1] : LOCATION = Pin_4; + adc1_data[2] : LOCATION = Pin_3; + adc1_data[3] : LOCATION = Pin_2; + adc1_data[4] : LOCATION = Pin_1; + adc1_data[4] : IO_STANDARD = LVTTL; + adc1_data[5] : LOCATION = Pin_240; + adc1_data[6] : LOCATION = Pin_239; + adc1_data[7] : LOCATION = Pin_238; + adc1_data[8] : LOCATION = Pin_237; + adc1_data[9] : LOCATION = Pin_236; + adc2_data[0] : LOCATION = Pin_20; + adc2_data[10] : LOCATION = Pin_8; + adc2_data[11] : LOCATION = Pin_7; + adc2_data[1] : LOCATION = Pin_19; + adc2_data[2] : LOCATION = Pin_18; + adc2_data[3] : LOCATION = Pin_17; + adc2_data[4] : LOCATION = Pin_16; + adc2_data[5] : LOCATION = Pin_15; + adc2_data[6] : LOCATION = Pin_14; + adc2_data[7] : LOCATION = Pin_13; + adc2_data[8] : LOCATION = Pin_12; + adc2_data[9] : LOCATION = Pin_11; + adc3_data[0] : LOCATION = Pin_200; + adc3_data[10] : LOCATION = Pin_184; + adc3_data[11] : LOCATION = Pin_183; + adc3_data[1] : LOCATION = Pin_197; + adc3_data[2] : LOCATION = Pin_196; + adc3_data[3] : LOCATION = Pin_195; + adc3_data[4] : LOCATION = Pin_194; + adc3_data[5] : LOCATION = Pin_193; + adc3_data[6] : LOCATION = Pin_188; + adc3_data[7] : LOCATION = Pin_187; + adc3_data[8] : LOCATION = Pin_186; + adc3_data[9] : LOCATION = Pin_185; + adc4_data[0] : LOCATION = Pin_222; + adc4_data[10] : LOCATION = Pin_203; + adc4_data[11] : LOCATION = Pin_202; + adc4_data[1] : LOCATION = Pin_219; + adc4_data[2] : LOCATION = Pin_217; + adc4_data[3] : LOCATION = Pin_216; + adc4_data[4] : LOCATION = Pin_215; + adc4_data[5] : LOCATION = Pin_214; + adc4_data[6] : LOCATION = Pin_213; + adc4_data[7] : LOCATION = Pin_208; + adc4_data[8] : LOCATION = Pin_207; + adc4_data[9] : LOCATION = Pin_206; + adc_oeb[0] : LOCATION = Pin_228; + adc_oeb[1] : LOCATION = Pin_21; + adc_oeb[2] : LOCATION = Pin_181; + adc_oeb[3] : LOCATION = Pin_218; + adc_otr[0] : LOCATION = Pin_233; + adc_otr[1] : LOCATION = Pin_6; + adc_otr[2] : LOCATION = Pin_182; + adc_otr[3] : LOCATION = Pin_201; + adclk0 : LOCATION = Pin_224; + adclk1 : LOCATION = Pin_226; + clk0 : LOCATION = Pin_28; + clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk0 : IO_STANDARD = LVTTL; + clk1 : LOCATION = Pin_29; + clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk1 : IO_STANDARD = LVTTL; + clk3 : LOCATION = Pin_152; + clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk3 : IO_STANDARD = LVTTL; + clk_120mhz : LOCATION = Pin_153; + clk_120mhz : IO_STANDARD = LVTTL; + clk_out : LOCATION = Pin_63; + clk_out : IO_STANDARD = LVTTL; + dac1_data[0] : LOCATION = Pin_165; + dac1_data[10] : LOCATION = Pin_177; + dac1_data[11] : LOCATION = Pin_178; + dac1_data[12] : LOCATION = Pin_179; + dac1_data[13] : LOCATION = Pin_180; + dac1_data[1] : LOCATION = Pin_166; + dac1_data[2] : LOCATION = Pin_167; + dac1_data[3] : LOCATION = Pin_168; + dac1_data[4] : LOCATION = Pin_169; + dac1_data[5] : LOCATION = Pin_170; + dac1_data[6] : LOCATION = Pin_173; + dac1_data[7] : LOCATION = Pin_174; + dac1_data[8] : LOCATION = Pin_175; + dac1_data[9] : LOCATION = Pin_176; + dac2_data[0] : LOCATION = Pin_159; + dac2_data[10] : LOCATION = Pin_163; + dac2_data[11] : LOCATION = Pin_139; + dac2_data[12] : LOCATION = Pin_164; + dac2_data[13] : LOCATION = Pin_138; + dac2_data[1] : LOCATION = Pin_158; + dac2_data[2] : LOCATION = Pin_160; + dac2_data[3] : LOCATION = Pin_156; + dac2_data[4] : LOCATION = Pin_161; + dac2_data[5] : LOCATION = Pin_144; + dac2_data[6] : LOCATION = Pin_162; + dac2_data[7] : LOCATION = Pin_141; + dac2_data[8] : LOCATION = Pin_143; + dac2_data[9] : LOCATION = Pin_140; + dac3_data[0] : LOCATION = Pin_122; + dac3_data[10] : LOCATION = Pin_134; + dac3_data[11] : LOCATION = Pin_135; + dac3_data[12] : LOCATION = Pin_136; + dac3_data[13] : LOCATION = Pin_137; + dac3_data[1] : LOCATION = Pin_123; + dac3_data[2] : LOCATION = Pin_124; + dac3_data[3] : LOCATION = Pin_125; + dac3_data[4] : LOCATION = Pin_126; + dac3_data[5] : LOCATION = Pin_127; + dac3_data[6] : LOCATION = Pin_128; + dac3_data[7] : LOCATION = Pin_131; + dac3_data[8] : LOCATION = Pin_132; + dac3_data[9] : LOCATION = Pin_133; + dac4_data[0] : LOCATION = Pin_104; + dac4_data[10] : LOCATION = Pin_118; + dac4_data[11] : LOCATION = Pin_119; + dac4_data[12] : LOCATION = Pin_120; + dac4_data[13] : LOCATION = Pin_121; + dac4_data[1] : LOCATION = Pin_105; + dac4_data[2] : LOCATION = Pin_106; + dac4_data[3] : LOCATION = Pin_107; + dac4_data[4] : LOCATION = Pin_108; + dac4_data[5] : LOCATION = Pin_113; + dac4_data[6] : LOCATION = Pin_114; + dac4_data[7] : LOCATION = Pin_115; + dac4_data[8] : LOCATION = Pin_116; + dac4_data[9] : LOCATION = Pin_117; + enable_rx : LOCATION = Pin_88; + enable_tx : LOCATION = Pin_93; + gndbus[0] : LOCATION = Pin_223; + gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[0] : IO_STANDARD = LVTTL; + gndbus[1] : LOCATION = Pin_225; + gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[1] : IO_STANDARD = LVTTL; + gndbus[2] : LOCATION = Pin_227; + gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[2] : IO_STANDARD = LVTTL; + gndbus[3] : LOCATION = Pin_62; + gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[3] : IO_STANDARD = LVTTL; + gndbus[4] : LOCATION = Pin_64; + gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[4] : IO_STANDARD = LVTTL; + misc_pins[0] : LOCATION = Pin_87; + misc_pins[0] : IO_STANDARD = LVTTL; + misc_pins[10] : LOCATION = Pin_76; + misc_pins[10] : IO_STANDARD = LVTTL; + misc_pins[11] : LOCATION = Pin_74; + misc_pins[11] : IO_STANDARD = LVTTL; + misc_pins[1] : LOCATION = Pin_86; + misc_pins[1] : IO_STANDARD = LVTTL; + misc_pins[2] : LOCATION = Pin_85; + misc_pins[2] : IO_STANDARD = LVTTL; + misc_pins[3] : LOCATION = Pin_84; + misc_pins[3] : IO_STANDARD = LVTTL; + misc_pins[4] : LOCATION = Pin_83; + misc_pins[4] : IO_STANDARD = LVTTL; + misc_pins[5] : LOCATION = Pin_82; + misc_pins[5] : IO_STANDARD = LVTTL; + misc_pins[6] : LOCATION = Pin_79; + misc_pins[6] : IO_STANDARD = LVTTL; + misc_pins[7] : LOCATION = Pin_78; + misc_pins[7] : IO_STANDARD = LVTTL; + misc_pins[8] : LOCATION = Pin_77; + misc_pins[8] : IO_STANDARD = LVTTL; + misc_pins[9] : LOCATION = Pin_75; + misc_pins[9] : IO_STANDARD = LVTTL; + reset : LOCATION = Pin_94; + usbclk : LOCATION = Pin_55; + usbctl[0] : LOCATION = Pin_56; + usbctl[1] : LOCATION = Pin_54; + usbctl[2] : LOCATION = Pin_53; + usbctl[3] : LOCATION = Pin_58; + usbctl[4] : LOCATION = Pin_57; + usbctl[5] : LOCATION = Pin_44; + usbdata[0] : LOCATION = Pin_73; + usbdata[10] : LOCATION = Pin_41; + usbdata[11] : LOCATION = Pin_39; + usbdata[12] : LOCATION = Pin_38; + usbdata[12] : IO_STANDARD = LVTTL; + usbdata[13] : LOCATION = Pin_37; + usbdata[14] : LOCATION = Pin_24; + usbdata[15] : LOCATION = Pin_23; + usbdata[1] : LOCATION = Pin_68; + usbdata[2] : LOCATION = Pin_67; + usbdata[3] : LOCATION = Pin_66; + usbdata[4] : LOCATION = Pin_65; + usbdata[5] : LOCATION = Pin_61; + usbdata[6] : LOCATION = Pin_60; + usbdata[7] : LOCATION = Pin_59; + usbdata[8] : LOCATION = Pin_43; + usbdata[9] : LOCATION = Pin_42; + usbrdy[0] : LOCATION = Pin_45; + usbrdy[1] : LOCATION = Pin_46; + usbrdy[2] : LOCATION = Pin_47; + usbrdy[3] : LOCATION = Pin_48; + usbrdy[4] : LOCATION = Pin_49; + usbrdy[5] : LOCATION = Pin_50; + clear_status : LOCATION = Pin_99; +} diff --git a/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.esf b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.esf new file mode 100644 index 000000000..6079e9795 --- /dev/null +++ b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.esf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = usrp_inband_usb; +} diff --git a/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.psf b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.psf new file mode 100644 index 000000000..85276ecc4 --- /dev/null +++ b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.psf @@ -0,0 +1,312 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_DSP_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_TURBO_BIT = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_PARALLEL_EXPANDERS = ON; + AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; + AUTO_FAST_OUTPUT_REGISTERS = OFF; + AUTO_FAST_INPUT_REGISTERS = OFF; + AUTO_CASCADE_CHAINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; + PARALLEL_EXPANDER_CHAIN_LENGTH = 16; + CASCADE_CHAIN_LENGTH = 2; + STRATIX_CARRY_CHAIN_LENGTH = 70; + MERCURY_CARRY_CHAIN_LENGTH = 48; + FLEX10K_CARRY_CHAIN_LENGTH = 32; + FLEX6K_CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN_LENGTH = 48; + CARRY_OUT_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + AUTO_LCELL_INSERTION = ON; + ALLOW_XOR_GATE_USAGE = ON; + AUTO_PACKED_REGISTERS_STRATIX = NORMAL; + AUTO_PACKED_REGISTERS = OFF; + AUTO_PACKED_REG_CYCLONE = NORMAL; + FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; + FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; + MERCURY_OPTIMIZATION_TECHNIQUE = AREA; + APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; + MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; + STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; + CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; + FLEX10K_TECHNOLOGY_MAPPER = LUT; + FLEX6K_TECHNOLOGY_MAPPER = LUT; + MERCURY_TECHNOLOGY_MAPPER = LUT; + APEX20K_TECHNOLOGY_MAPPER = LUT; + MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; + STRATIX_TECHNOLOGY_MAPPER = LUT; + AUTO_IMPLEMENT_IN_ROM = OFF; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_CLOCK = ON; + USE_LPM_FOR_AHDL_OPERATORS = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + TURBO_BIT = ON; + MAX7000_IGNORE_SOFT_BUFFERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MAX7000_IGNORE_LCELL_BUFFERS = AUTO; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + DSP_BLOCK_BALANCING = AUTO; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(usrp_inband_usb) +{ + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; + USER_LIBRARIES = "e:\usrp\fpga\megacells"; +} +THIRD_PARTY_EDA_TOOLS(usrp_inband_usb) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} +CLOCK(clk_120mhz) +{ + FMAX_REQUIREMENT = "120.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(usbclk) +{ + FMAX_REQUIREMENT = "48.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(SCLK) +{ + FMAX_REQUIREMENT = "1.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk0) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk1) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} diff --git a/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qpf b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qpf new file mode 100644 index 000000000..f6220e320 --- /dev/null +++ b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qpf @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2004 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.0" +DATE = "17:10:11 December 20, 2004" + + +# Active Revisions + +PROJECT_REVISION = "usrp_inband_usb" diff --git a/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qsf new file mode 100644 index 000000000..ae0807f6f --- /dev/null +++ b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -0,0 +1,423 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# usrp_inband_usb_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" +set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP2" + +# Pin & Location Assignments +# ========================== +set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" +set_location_assignment PIN_29 -to SCLK +set_location_assignment PIN_117 -to SDI +set_location_assignment PIN_28 -to usbclk +set_location_assignment PIN_107 -to usbctl[0] +set_location_assignment PIN_106 -to usbctl[1] +set_location_assignment PIN_105 -to usbctl[2] +set_location_assignment PIN_100 -to usbdata[0] +set_location_assignment PIN_84 -to usbdata[10] +set_location_assignment PIN_83 -to usbdata[11] +set_location_assignment PIN_82 -to usbdata[12] +set_location_assignment PIN_79 -to usbdata[13] +set_location_assignment PIN_78 -to usbdata[14] +set_location_assignment PIN_77 -to usbdata[15] +set_location_assignment PIN_99 -to usbdata[1] +set_location_assignment PIN_98 -to usbdata[2] +set_location_assignment PIN_95 -to usbdata[3] +set_location_assignment PIN_94 -to usbdata[4] +set_location_assignment PIN_93 -to usbdata[5] +set_location_assignment PIN_88 -to usbdata[6] +set_location_assignment PIN_87 -to usbdata[7] +set_location_assignment PIN_86 -to usbdata[8] +set_location_assignment PIN_85 -to usbdata[9] +set_location_assignment PIN_104 -to usbrdy[0] +set_location_assignment PIN_101 -to usbrdy[1] +set_location_assignment PIN_76 -to FX2_1 +set_location_assignment PIN_75 -to FX2_2 +set_location_assignment PIN_74 -to FX2_3 +set_location_assignment PIN_116 -to io_rx_a[0] +set_location_assignment PIN_115 -to io_rx_a[1] +set_location_assignment PIN_114 -to io_rx_a[2] +set_location_assignment PIN_113 -to io_rx_a[3] +set_location_assignment PIN_108 -to io_rx_a[4] +set_location_assignment PIN_195 -to io_rx_a[5] +set_location_assignment PIN_196 -to io_rx_a[6] +set_location_assignment PIN_197 -to io_rx_a[7] +set_location_assignment PIN_200 -to io_rx_a[8] +set_location_assignment PIN_201 -to io_rx_a[9] +set_location_assignment PIN_202 -to io_rx_a[10] +set_location_assignment PIN_203 -to io_rx_a[11] +set_location_assignment PIN_206 -to io_rx_a[12] +set_location_assignment PIN_207 -to io_rx_a[13] +set_location_assignment PIN_208 -to io_rx_a[14] +set_location_assignment PIN_214 -to io_rx_b[0] +set_location_assignment PIN_215 -to io_rx_b[1] +set_location_assignment PIN_216 -to io_rx_b[2] +set_location_assignment PIN_217 -to io_rx_b[3] +set_location_assignment PIN_218 -to io_rx_b[4] +set_location_assignment PIN_219 -to io_rx_b[5] +set_location_assignment PIN_222 -to io_rx_b[6] +set_location_assignment PIN_223 -to io_rx_b[7] +set_location_assignment PIN_224 -to io_rx_b[8] +set_location_assignment PIN_225 -to io_rx_b[9] +set_location_assignment PIN_226 -to io_rx_b[10] +set_location_assignment PIN_227 -to io_rx_b[11] +set_location_assignment PIN_228 -to io_rx_b[12] +set_location_assignment PIN_233 -to io_rx_b[13] +set_location_assignment PIN_234 -to io_rx_b[14] +set_location_assignment PIN_175 -to io_tx_a[0] +set_location_assignment PIN_176 -to io_tx_a[1] +set_location_assignment PIN_177 -to io_tx_a[2] +set_location_assignment PIN_178 -to io_tx_a[3] +set_location_assignment PIN_179 -to io_tx_a[4] +set_location_assignment PIN_180 -to io_tx_a[5] +set_location_assignment PIN_181 -to io_tx_a[6] +set_location_assignment PIN_182 -to io_tx_a[7] +set_location_assignment PIN_183 -to io_tx_a[8] +set_location_assignment PIN_184 -to io_tx_a[9] +set_location_assignment PIN_185 -to io_tx_a[10] +set_location_assignment PIN_186 -to io_tx_a[11] +set_location_assignment PIN_187 -to io_tx_a[12] +set_location_assignment PIN_188 -to io_tx_a[13] +set_location_assignment PIN_193 -to io_tx_a[14] +set_location_assignment PIN_73 -to io_tx_b[0] +set_location_assignment PIN_68 -to io_tx_b[1] +set_location_assignment PIN_67 -to io_tx_b[2] +set_location_assignment PIN_66 -to io_tx_b[3] +set_location_assignment PIN_65 -to io_tx_b[4] +set_location_assignment PIN_64 -to io_tx_b[5] +set_location_assignment PIN_63 -to io_tx_b[6] +set_location_assignment PIN_62 -to io_tx_b[7] +set_location_assignment PIN_61 -to io_tx_b[8] +set_location_assignment PIN_60 -to io_tx_b[9] +set_location_assignment PIN_59 -to io_tx_b[10] +set_location_assignment PIN_58 -to io_tx_b[11] +set_location_assignment PIN_57 -to io_tx_b[12] +set_location_assignment PIN_56 -to io_tx_b[13] +set_location_assignment PIN_55 -to io_tx_b[14] +set_location_assignment PIN_152 -to master_clk +set_location_assignment PIN_144 -to rx_a_a[0] +set_location_assignment PIN_143 -to rx_a_a[1] +set_location_assignment PIN_141 -to rx_a_a[2] +set_location_assignment PIN_140 -to rx_a_a[3] +set_location_assignment PIN_139 -to rx_a_a[4] +set_location_assignment PIN_138 -to rx_a_a[5] +set_location_assignment PIN_137 -to rx_a_a[6] +set_location_assignment PIN_136 -to rx_a_a[7] +set_location_assignment PIN_135 -to rx_a_a[8] +set_location_assignment PIN_134 -to rx_a_a[9] +set_location_assignment PIN_133 -to rx_a_a[10] +set_location_assignment PIN_132 -to rx_a_a[11] +set_location_assignment PIN_23 -to rx_a_b[0] +set_location_assignment PIN_21 -to rx_a_b[1] +set_location_assignment PIN_20 -to rx_a_b[2] +set_location_assignment PIN_19 -to rx_a_b[3] +set_location_assignment PIN_18 -to rx_a_b[4] +set_location_assignment PIN_17 -to rx_a_b[5] +set_location_assignment PIN_16 -to rx_a_b[6] +set_location_assignment PIN_15 -to rx_a_b[7] +set_location_assignment PIN_14 -to rx_a_b[8] +set_location_assignment PIN_13 -to rx_a_b[9] +set_location_assignment PIN_12 -to rx_a_b[10] +set_location_assignment PIN_11 -to rx_a_b[11] +set_location_assignment PIN_131 -to rx_b_a[0] +set_location_assignment PIN_128 -to rx_b_a[1] +set_location_assignment PIN_127 -to rx_b_a[2] +set_location_assignment PIN_126 -to rx_b_a[3] +set_location_assignment PIN_125 -to rx_b_a[4] +set_location_assignment PIN_124 -to rx_b_a[5] +set_location_assignment PIN_123 -to rx_b_a[6] +set_location_assignment PIN_122 -to rx_b_a[7] +set_location_assignment PIN_121 -to rx_b_a[8] +set_location_assignment PIN_120 -to rx_b_a[9] +set_location_assignment PIN_119 -to rx_b_a[10] +set_location_assignment PIN_118 -to rx_b_a[11] +set_location_assignment PIN_8 -to rx_b_b[0] +set_location_assignment PIN_7 -to rx_b_b[1] +set_location_assignment PIN_6 -to rx_b_b[2] +set_location_assignment PIN_5 -to rx_b_b[3] +set_location_assignment PIN_4 -to rx_b_b[4] +set_location_assignment PIN_3 -to rx_b_b[5] +set_location_assignment PIN_2 -to rx_b_b[6] +set_location_assignment PIN_240 -to rx_b_b[7] +set_location_assignment PIN_239 -to rx_b_b[8] +set_location_assignment PIN_238 -to rx_b_b[9] +set_location_assignment PIN_237 -to rx_b_b[10] +set_location_assignment PIN_236 -to rx_b_b[11] +set_location_assignment PIN_156 -to SDO +set_location_assignment PIN_153 -to SEN_FPGA +set_location_assignment PIN_159 -to tx_a[0] +set_location_assignment PIN_160 -to tx_a[1] +set_location_assignment PIN_161 -to tx_a[2] +set_location_assignment PIN_162 -to tx_a[3] +set_location_assignment PIN_163 -to tx_a[4] +set_location_assignment PIN_164 -to tx_a[5] +set_location_assignment PIN_165 -to tx_a[6] +set_location_assignment PIN_166 -to tx_a[7] +set_location_assignment PIN_167 -to tx_a[8] +set_location_assignment PIN_168 -to tx_a[9] +set_location_assignment PIN_169 -to tx_a[10] +set_location_assignment PIN_170 -to tx_a[11] +set_location_assignment PIN_173 -to tx_a[12] +set_location_assignment PIN_174 -to tx_a[13] +set_location_assignment PIN_38 -to tx_b[0] +set_location_assignment PIN_39 -to tx_b[1] +set_location_assignment PIN_41 -to tx_b[2] +set_location_assignment PIN_42 -to tx_b[3] +set_location_assignment PIN_43 -to tx_b[4] +set_location_assignment PIN_44 -to tx_b[5] +set_location_assignment PIN_45 -to tx_b[6] +set_location_assignment PIN_46 -to tx_b[7] +set_location_assignment PIN_47 -to tx_b[8] +set_location_assignment PIN_48 -to tx_b[9] +set_location_assignment PIN_49 -to tx_b[10] +set_location_assignment PIN_50 -to tx_b[11] +set_location_assignment PIN_53 -to tx_b[12] +set_location_assignment PIN_54 -to tx_b[13] +set_location_assignment PIN_158 -to TXSYNC_A +set_location_assignment PIN_37 -to TXSYNC_B +set_location_assignment PIN_235 -to io_rx_b[15] +set_location_assignment PIN_24 -to io_tx_b[15] +set_location_assignment PIN_213 -to io_rx_a[15] +set_location_assignment PIN_194 -to io_tx_a[15] +set_location_assignment PIN_1 -to MYSTERY_SIGNAL + +# Timing Assignments +# ================== +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name TOP_LEVEL_ENTITY usrp_inband_usb +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name INC_PLC_MODE OFF +set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF +set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# Timing Analysis Assignments +# =========================== +set_global_assignment -name MAX_SCC_SIZE 50 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF + +# Simulator Assignments +# ===================== +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "1 ns" + +# Design Assistant Assignments +# ============================ +set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF +set_global_assignment -name ASSG_CAT OFF +set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF +set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF +set_global_assignment -name CLK_CAT OFF +set_global_assignment -name CLK_RULE_COMB_CLOCK OFF +set_global_assignment -name CLK_RULE_INV_CLOCK OFF +set_global_assignment -name CLK_RULE_GATING_SCHEME OFF +set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF +set_global_assignment -name CLK_RULE_MIX_EDGES OFF +set_global_assignment -name RESET_CAT OFF +set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name TIMING_CAT OFF +set_global_assignment -name TIMING_RULE_SHIFT_REG OFF +set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF +set_global_assignment -name NONSYNCHSTRUCT_CAT OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF +set_global_assignment -name SIGNALRACE_CAT OFF +set_global_assignment -name ACLK_CAT OFF +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF +set_global_assignment -name HCPY_CAT OFF +set_global_assignment -name HCPY_VREF_PINS OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name HUB_ENTITY_NAME SLD_HUB +set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST +set_global_assignment -name ENABLE_SIGNALTAP OFF + +# LogicLock Region Assignments +# ============================ +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF + +# ----------------- +# start CLOCK(SCLK) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK +set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK + +# end CLOCK(SCLK) +# --------------- + +# ----------------------- +# start CLOCK(master_clk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk +set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk + +# end CLOCK(master_clk) +# --------------------- + +# ------------------- +# start CLOCK(usbclk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk +set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk + +# end CLOCK(usbclk) +# ----------------- + +# ---------------------- +# start ENTITY(usrp_inband_usb) + + # Timing Assignments + # ================== +set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK +set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk +set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk + +# end ENTITY(usrp_inband_usb) +# -------------------- + + +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4kx16_dc.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v +set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v +set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v +set_global_assignment -name VERILOG_FILE usrp_inband_usb.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v +set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file diff --git a/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v new file mode 100644 index 000000000..79f0dfa4a --- /dev/null +++ b/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v @@ -0,0 +1,428 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2004 Matt Ettus +// Copyright 2007 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// +`define TX_IN_BAND +`define RX_IN_BAND + +`include "config.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module usrp_inband_usb +(output MYSTERY_SIGNAL, + input master_clk, + input SCLK, + input SDI, + inout SDO, + input SEN_FPGA, + + input FX2_1, + output FX2_2, + output FX2_3, + + input wire [11:0] rx_a_a, + input wire [11:0] rx_b_a, + input wire [11:0] rx_a_b, + input wire [11:0] rx_b_b, + + output wire [13:0] tx_a, + output wire [13:0] tx_b, + + output wire TXSYNC_A, + output wire TXSYNC_B, + + // USB interface + input usbclk, + input wire [2:0] usbctl, + output wire [1:0] usbrdy, + inout [15:0] usbdata, // NB Careful, inout + + // These are the general purpose i/o's that go to the daughterboard slots + inout wire [15:0] io_tx_a, + inout wire [15:0] io_tx_b, + inout wire [15:0] io_rx_a, + inout wire [15:0] io_rx_b + ); + wire [15:0] debugdata,debugctrl; + assign MYSTERY_SIGNAL = 1'b0; + + wire clk64,clk128; + + wire WR = usbctl[0]; + wire RD = usbctl[1]; + wire OE = usbctl[2]; + + wire have_space, have_pkt_rdy; + assign usbrdy[0] = have_space; + assign usbrdy[1] = have_pkt_rdy; + + wire rx_overrun; + wire clear_status = FX2_1; + assign FX2_2 = rx_overrun; + assign FX2_3 = (tx_underrun == 0); + + wire [15:0] usbdata_out; + + wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; + + wire tx_realsignals; + wire [3:0] rx_numchan; + wire [2:0] tx_numchan; + + wire [7:0] interp_rate, decim_rate; + wire [15:0] tx_debugbus, rx_debugbus; + + wire enable_tx, enable_rx; + wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; + wire [7:0] settings; + + // Tri-state bus macro + bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); + + wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; + wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; + + // TX + wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; + wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; + + wire strobe_interp, tx_sample_strobe; + wire tx_empty; + + wire serial_strobe; + wire [6:0] serial_addr; + wire [31:0] serial_data; + + reg [15:0] debug_counter; + reg [15:0] loopback_i_0,loopback_q_0; + + + //Connection RX inband <-> TX inband + wire rx_WR; + wire [15:0] rx_databus; + wire rx_WR_done; + wire rx_WR_enabled; + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Transmit Side +`ifdef TX_ON + assign bb_tx_i0 = ch0tx; + assign bb_tx_q0 = ch1tx; + assign bb_tx_i1 = ch2tx; + assign bb_tx_q1 = ch3tx; + +wire [1:0] tx_underrun; + +`ifdef TX_IN_BAND + tx_buffer_inband tx_buffer + ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), + .usbdata(usbdata),.WR(WR),.have_space(have_space), + .tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}), + .tx_i_0(ch0tx),.tx_q_0(ch1tx), + .tx_i_1(ch2tx),.tx_q_1(ch3tx), + .tx_i_2(),.tx_q_2(), + .tx_i_3(),.tx_q_3(), + .txclk(clk64),.txstrobe(strobe_interp), + .clear_status(clear_status), + .tx_empty(tx_empty), + .rx_WR(rx_WR), + .rx_databus(rx_databus), + .rx_WR_done(rx_WR_done), + .rx_WR_enabled(rx_WR_enabled), + .reg_addr(reg_addr), + .reg_data_out(reg_data_out), + .reg_data_in(reg_data_in), + .reg_io_enable(reg_io_enable), + .debugbus(rx_debugbus), + .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), + .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait), + .stop(stop), .stop_time(stop_time)); + + `ifdef TX_DUAL + defparam tx_buffer.NUM_CHAN=2; + `endif + +`else + tx_buffer tx_buffer + ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), + .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), + .channels({tx_numchan,1'b0}), + .tx_i_0(ch0tx),.tx_q_0(ch1tx), + .tx_i_1(ch2tx),.tx_q_1(ch3tx), + .tx_i_2(),.tx_q_2(), + .tx_i_3(),.tx_q_3(), + .txclk(clk64),.txstrobe(strobe_interp), + .clear_status(clear_status), + .tx_empty(tx_empty)); +`endif + + `ifdef TX_EN_0 + tx_chain tx_chain_0 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); + `else + assign i_out_0=16'd0; + assign q_out_0=16'd0; + `endif + + `ifdef TX_EN_1 + tx_chain tx_chain_1 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); + `else + assign i_out_1=16'd0; + assign q_out_1=16'd0; + `endif + + setting_reg #(`FR_TX_MUX) + sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; + + wire txsync = tx_sample_strobe; + assign TXSYNC_A = txsync; + assign TXSYNC_B = txsync; + + assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; + assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; +`endif // `ifdef TX_ON + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Receive Side +`ifdef RX_ON + wire rx_sample_strobe,strobe_decim,hb_strobe; + wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, + bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; + + wire loopback = settings[0]; + wire counter = settings[1]; + + always @(posedge clk64) + if(rx_dsp_reset) + debug_counter <= #1 16'd0; + else if(~enable_rx) + debug_counter <= #1 16'd0; + else if(hb_strobe) + debug_counter <=#1 debug_counter + 16'd2; + + always @(posedge clk64) + if(strobe_interp) + begin + loopback_i_0 <= #1 ch0tx; + loopback_q_0 <= #1 ch1tx; + end + + assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; + assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; + assign ch2rx = bb_rx_i1; + assign ch3rx = bb_rx_q1; + assign ch4rx = bb_rx_i2; + assign ch5rx = bb_rx_q2; + assign ch6rx = bb_rx_i3; + assign ch7rx = bb_rx_q3; + + wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; + wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; + adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), + .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3), + .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), + .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), + .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), + .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan)); + `ifdef RX_IN_BAND + rx_buffer_inband rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), + .reset_regs(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(ch0rx),.ch_1(ch1rx), + .ch_2(ch2rx),.ch_3(ch3rx), + .ch_4(ch4rx),.ch_5(ch5rx), + .ch_6(ch6rx),.ch_7(ch7rx), + .rxclk(clk64),.rxstrobe(hb_strobe), + .clear_status(clear_status), + .rx_WR(rx_WR), + .rx_databus(rx_databus), + .rx_WR_done(rx_WR_done), + .rx_WR_enabled(rx_WR_enabled), + .debugbus(tx_debugbus), + .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3), + .tx_underrun(tx_underrun)); + + `ifdef RX_DUAL + defparam rx_buffer.NUM_CHAN=2; + `endif + + `else + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), + .reset_regs(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(ch0rx),.ch_1(ch1rx), + .ch_2(ch2rx),.ch_3(ch3rx), + .ch_4(ch4rx),.ch_5(ch5rx), + .ch_6(ch6rx),.ch_7(ch7rx), + .rxclk(clk64),.rxstrobe(hb_strobe), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + `endif + + `ifdef RX_EN_0 + rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); + `else + assign bb_rx_i0=16'd0; + assign bb_rx_q0=16'd0; + `endif + + `ifdef RX_EN_1 + rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); + `else + assign bb_rx_i1=16'd0; + assign bb_rx_q1=16'd0; + `endif + + `ifdef RX_EN_2 + rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); + `else + assign bb_rx_i2=16'd0; + assign bb_rx_q2=16'd0; + `endif + + `ifdef RX_EN_3 + rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); + `else + assign bb_rx_i3=16'd0; + assign bb_rx_q3=16'd0; + `endif + +`endif // `ifdef RX_ON + + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Control Functions + + wire [31:0] capabilities; + assign capabilities[7] = `TX_CAP_HB; + assign capabilities[6:4] = `TX_CAP_NCHAN; + assign capabilities[3] = `RX_CAP_HB; + assign capabilities[2:0] = `RX_CAP_NCHAN; + + serial_io serial_io + ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), + .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), + .serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db), + .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), + .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) + ); + + wire [6:0] reg_addr; + wire [31:0] reg_data_out; + wire [31:0] reg_data_in; + wire [1:0] reg_io_enable; + wire [31:0] rssi_threshhold; + wire [31:0] rssi_wait; + wire [6:0] addr_wr; + wire [31:0] data_wr; + wire strobe_wr; + wire [6:0] addr_db; + wire [31:0] data_db; + wire strobe_db; + assign serial_strobe = strobe_db | strobe_wr; + assign serial_addr = (strobe_db)? (addr_db) : (addr_wr); + assign serial_data = (strobe_db)? (data_db) : (data_wr); + //assign serial_strobe = strobe_wr; + //assign serial_data = data_wr; + //assign serial_addr = addr_wr; + + register_io register_control + (.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in), + .dataout(reg_data_out), .addr_wr(addr_wr), .data_wr(data_wr), .strobe_wr(strobe_wr), + .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), + .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .debug_en(debug_en), .misc(settings), + .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + + //implementing freeze mode + reg [15:0] timestop; + wire stop; + wire [15:0] stop_time; + assign clk64 = (timestop == 0) ? master_clk : 0; + always @(posedge master_clk) + if (timestop[15:0] != 0) + timestop <= timestop - 16'd1; + else if (stop) + timestop <= stop_time; + + + wire [15:0] reg_0,reg_1,reg_2,reg_3; + master_control master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + //.debug_0(rx_a_a),.debug_1(ddc0_in_i), + .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + + io_pins io_pins + (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Misc Settings + setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); + +endmodule // usrp_inband_usb diff --git a/usrp1/toplevel/usrp_multi/.gitignore b/usrp1/toplevel/usrp_multi/.gitignore new file mode 100644 index 000000000..2cc25f0f2 --- /dev/null +++ b/usrp1/toplevel/usrp_multi/.gitignore @@ -0,0 +1,16 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/*.summary +/db diff --git a/usrp1/toplevel/usrp_multi/config.vh b/usrp1/toplevel/usrp_multi/config.vh new file mode 100644 index 000000000..07011bd48 --- /dev/null +++ b/usrp1/toplevel/usrp_multi/config.vh @@ -0,0 +1,62 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006,2007 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ==================================================================== +// User control over what parts get included +// +// >>>> EDIT ONLY THIS SECTION <<<< +// Uncomment only ONE configuration +// ==================================================================== + +// ==================================================================== +// FIXME drive configuration selection from the command line and/or gui +// ==================================================================== + +`define MULTI_ON // enable multi usrp configuration + +// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel +//`include "../include/common_config_1rxhb_1tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 2 transmit channels +`include "../include/common_config_2rxhb_2tx.vh" + +// Uncomment this for multi with 4 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_4rx_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels +//`include "../include/common_config_2rxhb_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_2rx_0tx.vh" + + +// Add other "known to fit" configurations here... + +// ==================================================================== +// Now include the common footer +// ==================================================================== + +`ifdef MULTI_ON + `define COUNTER_32BIT_ON +`endif + +`include "../include/common_config_bottom.vh" diff --git a/usrp1/toplevel/usrp_multi/usrp_multi.csf b/usrp1/toplevel/usrp_multi/usrp_multi.csf new file mode 100644 index 000000000..2f5df2bca --- /dev/null +++ b/usrp1/toplevel/usrp_multi/usrp_multi.csf @@ -0,0 +1,444 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; + OPTIMIZE_TIMING = "NORMAL COMPILATION"; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = OFF; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |usrp_multi; + ROUTING_BACK_ANNOTATION_MODE = OFF; + INC_PLC_MODE = OFF; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} +CHIP(usrp_multi) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; + AUTO_RESTART_CONFIGURATION = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + USER_START_UP_CLOCK = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_JTAG_BST_SUPPORT = OFF; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + USE_CONFIGURATION_DEVICE = OFF; + APEX20K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + STRATIX_UPDATE_MODE = STANDARD; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + COMPRESSION_MODE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + GENERATE_TTF_FILE = OFF; + GENERATE_RBF_FILE = ON; + GENERATE_HEX_FILE = OFF; + SECURITY_BIT = OFF; + ENABLE_VREFA_PIN = OFF; + ENABLE_VREFB_PIN = OFF; + GENERATE_SVF_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_JBC_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_HEXOUT_FILE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; + BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; + HEXOUT_FILE_START_ADDRESS = 0; + HEXOUT_FILE_COUNT_DIRECTION = UP; + RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; + STRATIX_DEVICE_IO_STANDARD = LVTTL; + CLOCK_SOURCE = INTERNAL; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CONFIGURATION_CLOCK_DIVISOR = 1; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + SCLK : LOCATION = Pin_101; + SDI : LOCATION = Pin_100; + SEN : LOCATION = Pin_98; + SLD : LOCATION = Pin_95; + adc1_data[0] : LOCATION = Pin_5; + adc1_data[10] : LOCATION = Pin_235; + adc1_data[11] : LOCATION = Pin_234; + adc1_data[1] : LOCATION = Pin_4; + adc1_data[2] : LOCATION = Pin_3; + adc1_data[3] : LOCATION = Pin_2; + adc1_data[4] : LOCATION = Pin_1; + adc1_data[4] : IO_STANDARD = LVTTL; + adc1_data[5] : LOCATION = Pin_240; + adc1_data[6] : LOCATION = Pin_239; + adc1_data[7] : LOCATION = Pin_238; + adc1_data[8] : LOCATION = Pin_237; + adc1_data[9] : LOCATION = Pin_236; + adc2_data[0] : LOCATION = Pin_20; + adc2_data[10] : LOCATION = Pin_8; + adc2_data[11] : LOCATION = Pin_7; + adc2_data[1] : LOCATION = Pin_19; + adc2_data[2] : LOCATION = Pin_18; + adc2_data[3] : LOCATION = Pin_17; + adc2_data[4] : LOCATION = Pin_16; + adc2_data[5] : LOCATION = Pin_15; + adc2_data[6] : LOCATION = Pin_14; + adc2_data[7] : LOCATION = Pin_13; + adc2_data[8] : LOCATION = Pin_12; + adc2_data[9] : LOCATION = Pin_11; + adc3_data[0] : LOCATION = Pin_200; + adc3_data[10] : LOCATION = Pin_184; + adc3_data[11] : LOCATION = Pin_183; + adc3_data[1] : LOCATION = Pin_197; + adc3_data[2] : LOCATION = Pin_196; + adc3_data[3] : LOCATION = Pin_195; + adc3_data[4] : LOCATION = Pin_194; + adc3_data[5] : LOCATION = Pin_193; + adc3_data[6] : LOCATION = Pin_188; + adc3_data[7] : LOCATION = Pin_187; + adc3_data[8] : LOCATION = Pin_186; + adc3_data[9] : LOCATION = Pin_185; + adc4_data[0] : LOCATION = Pin_222; + adc4_data[10] : LOCATION = Pin_203; + adc4_data[11] : LOCATION = Pin_202; + adc4_data[1] : LOCATION = Pin_219; + adc4_data[2] : LOCATION = Pin_217; + adc4_data[3] : LOCATION = Pin_216; + adc4_data[4] : LOCATION = Pin_215; + adc4_data[5] : LOCATION = Pin_214; + adc4_data[6] : LOCATION = Pin_213; + adc4_data[7] : LOCATION = Pin_208; + adc4_data[8] : LOCATION = Pin_207; + adc4_data[9] : LOCATION = Pin_206; + adc_oeb[0] : LOCATION = Pin_228; + adc_oeb[1] : LOCATION = Pin_21; + adc_oeb[2] : LOCATION = Pin_181; + adc_oeb[3] : LOCATION = Pin_218; + adc_otr[0] : LOCATION = Pin_233; + adc_otr[1] : LOCATION = Pin_6; + adc_otr[2] : LOCATION = Pin_182; + adc_otr[3] : LOCATION = Pin_201; + adclk0 : LOCATION = Pin_224; + adclk1 : LOCATION = Pin_226; + clk0 : LOCATION = Pin_28; + clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk0 : IO_STANDARD = LVTTL; + clk1 : LOCATION = Pin_29; + clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk1 : IO_STANDARD = LVTTL; + clk3 : LOCATION = Pin_152; + clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk3 : IO_STANDARD = LVTTL; + clk_120mhz : LOCATION = Pin_153; + clk_120mhz : IO_STANDARD = LVTTL; + clk_out : LOCATION = Pin_63; + clk_out : IO_STANDARD = LVTTL; + dac1_data[0] : LOCATION = Pin_165; + dac1_data[10] : LOCATION = Pin_177; + dac1_data[11] : LOCATION = Pin_178; + dac1_data[12] : LOCATION = Pin_179; + dac1_data[13] : LOCATION = Pin_180; + dac1_data[1] : LOCATION = Pin_166; + dac1_data[2] : LOCATION = Pin_167; + dac1_data[3] : LOCATION = Pin_168; + dac1_data[4] : LOCATION = Pin_169; + dac1_data[5] : LOCATION = Pin_170; + dac1_data[6] : LOCATION = Pin_173; + dac1_data[7] : LOCATION = Pin_174; + dac1_data[8] : LOCATION = Pin_175; + dac1_data[9] : LOCATION = Pin_176; + dac2_data[0] : LOCATION = Pin_159; + dac2_data[10] : LOCATION = Pin_163; + dac2_data[11] : LOCATION = Pin_139; + dac2_data[12] : LOCATION = Pin_164; + dac2_data[13] : LOCATION = Pin_138; + dac2_data[1] : LOCATION = Pin_158; + dac2_data[2] : LOCATION = Pin_160; + dac2_data[3] : LOCATION = Pin_156; + dac2_data[4] : LOCATION = Pin_161; + dac2_data[5] : LOCATION = Pin_144; + dac2_data[6] : LOCATION = Pin_162; + dac2_data[7] : LOCATION = Pin_141; + dac2_data[8] : LOCATION = Pin_143; + dac2_data[9] : LOCATION = Pin_140; + dac3_data[0] : LOCATION = Pin_122; + dac3_data[10] : LOCATION = Pin_134; + dac3_data[11] : LOCATION = Pin_135; + dac3_data[12] : LOCATION = Pin_136; + dac3_data[13] : LOCATION = Pin_137; + dac3_data[1] : LOCATION = Pin_123; + dac3_data[2] : LOCATION = Pin_124; + dac3_data[3] : LOCATION = Pin_125; + dac3_data[4] : LOCATION = Pin_126; + dac3_data[5] : LOCATION = Pin_127; + dac3_data[6] : LOCATION = Pin_128; + dac3_data[7] : LOCATION = Pin_131; + dac3_data[8] : LOCATION = Pin_132; + dac3_data[9] : LOCATION = Pin_133; + dac4_data[0] : LOCATION = Pin_104; + dac4_data[10] : LOCATION = Pin_118; + dac4_data[11] : LOCATION = Pin_119; + dac4_data[12] : LOCATION = Pin_120; + dac4_data[13] : LOCATION = Pin_121; + dac4_data[1] : LOCATION = Pin_105; + dac4_data[2] : LOCATION = Pin_106; + dac4_data[3] : LOCATION = Pin_107; + dac4_data[4] : LOCATION = Pin_108; + dac4_data[5] : LOCATION = Pin_113; + dac4_data[6] : LOCATION = Pin_114; + dac4_data[7] : LOCATION = Pin_115; + dac4_data[8] : LOCATION = Pin_116; + dac4_data[9] : LOCATION = Pin_117; + enable_rx : LOCATION = Pin_88; + enable_tx : LOCATION = Pin_93; + gndbus[0] : LOCATION = Pin_223; + gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[0] : IO_STANDARD = LVTTL; + gndbus[1] : LOCATION = Pin_225; + gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[1] : IO_STANDARD = LVTTL; + gndbus[2] : LOCATION = Pin_227; + gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[2] : IO_STANDARD = LVTTL; + gndbus[3] : LOCATION = Pin_62; + gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[3] : IO_STANDARD = LVTTL; + gndbus[4] : LOCATION = Pin_64; + gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[4] : IO_STANDARD = LVTTL; + misc_pins[0] : LOCATION = Pin_87; + misc_pins[0] : IO_STANDARD = LVTTL; + misc_pins[10] : LOCATION = Pin_76; + misc_pins[10] : IO_STANDARD = LVTTL; + misc_pins[11] : LOCATION = Pin_74; + misc_pins[11] : IO_STANDARD = LVTTL; + misc_pins[1] : LOCATION = Pin_86; + misc_pins[1] : IO_STANDARD = LVTTL; + misc_pins[2] : LOCATION = Pin_85; + misc_pins[2] : IO_STANDARD = LVTTL; + misc_pins[3] : LOCATION = Pin_84; + misc_pins[3] : IO_STANDARD = LVTTL; + misc_pins[4] : LOCATION = Pin_83; + misc_pins[4] : IO_STANDARD = LVTTL; + misc_pins[5] : LOCATION = Pin_82; + misc_pins[5] : IO_STANDARD = LVTTL; + misc_pins[6] : LOCATION = Pin_79; + misc_pins[6] : IO_STANDARD = LVTTL; + misc_pins[7] : LOCATION = Pin_78; + misc_pins[7] : IO_STANDARD = LVTTL; + misc_pins[8] : LOCATION = Pin_77; + misc_pins[8] : IO_STANDARD = LVTTL; + misc_pins[9] : LOCATION = Pin_75; + misc_pins[9] : IO_STANDARD = LVTTL; + reset : LOCATION = Pin_94; + usbclk : LOCATION = Pin_55; + usbctl[0] : LOCATION = Pin_56; + usbctl[1] : LOCATION = Pin_54; + usbctl[2] : LOCATION = Pin_53; + usbctl[3] : LOCATION = Pin_58; + usbctl[4] : LOCATION = Pin_57; + usbctl[5] : LOCATION = Pin_44; + usbdata[0] : LOCATION = Pin_73; + usbdata[10] : LOCATION = Pin_41; + usbdata[11] : LOCATION = Pin_39; + usbdata[12] : LOCATION = Pin_38; + usbdata[12] : IO_STANDARD = LVTTL; + usbdata[13] : LOCATION = Pin_37; + usbdata[14] : LOCATION = Pin_24; + usbdata[15] : LOCATION = Pin_23; + usbdata[1] : LOCATION = Pin_68; + usbdata[2] : LOCATION = Pin_67; + usbdata[3] : LOCATION = Pin_66; + usbdata[4] : LOCATION = Pin_65; + usbdata[5] : LOCATION = Pin_61; + usbdata[6] : LOCATION = Pin_60; + usbdata[7] : LOCATION = Pin_59; + usbdata[8] : LOCATION = Pin_43; + usbdata[9] : LOCATION = Pin_42; + usbrdy[0] : LOCATION = Pin_45; + usbrdy[1] : LOCATION = Pin_46; + usbrdy[2] : LOCATION = Pin_47; + usbrdy[3] : LOCATION = Pin_48; + usbrdy[4] : LOCATION = Pin_49; + usbrdy[5] : LOCATION = Pin_50; + clear_status : LOCATION = Pin_99; +} diff --git a/usrp1/toplevel/usrp_multi/usrp_multi.esf b/usrp1/toplevel/usrp_multi/usrp_multi.esf new file mode 100644 index 000000000..df45f676b --- /dev/null +++ b/usrp1/toplevel/usrp_multi/usrp_multi.esf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = usrp_multi; +} diff --git a/usrp1/toplevel/usrp_multi/usrp_multi.psf b/usrp1/toplevel/usrp_multi/usrp_multi.psf new file mode 100644 index 000000000..68c2d12f9 --- /dev/null +++ b/usrp1/toplevel/usrp_multi/usrp_multi.psf @@ -0,0 +1,312 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_DSP_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_TURBO_BIT = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_PARALLEL_EXPANDERS = ON; + AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; + AUTO_FAST_OUTPUT_REGISTERS = OFF; + AUTO_FAST_INPUT_REGISTERS = OFF; + AUTO_CASCADE_CHAINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; + PARALLEL_EXPANDER_CHAIN_LENGTH = 16; + CASCADE_CHAIN_LENGTH = 2; + STRATIX_CARRY_CHAIN_LENGTH = 70; + MERCURY_CARRY_CHAIN_LENGTH = 48; + FLEX10K_CARRY_CHAIN_LENGTH = 32; + FLEX6K_CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN_LENGTH = 48; + CARRY_OUT_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + AUTO_LCELL_INSERTION = ON; + ALLOW_XOR_GATE_USAGE = ON; + AUTO_PACKED_REGISTERS_STRATIX = NORMAL; + AUTO_PACKED_REGISTERS = OFF; + AUTO_PACKED_REG_CYCLONE = NORMAL; + FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; + FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; + MERCURY_OPTIMIZATION_TECHNIQUE = AREA; + APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; + MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; + STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; + CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; + FLEX10K_TECHNOLOGY_MAPPER = LUT; + FLEX6K_TECHNOLOGY_MAPPER = LUT; + MERCURY_TECHNOLOGY_MAPPER = LUT; + APEX20K_TECHNOLOGY_MAPPER = LUT; + MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; + STRATIX_TECHNOLOGY_MAPPER = LUT; + AUTO_IMPLEMENT_IN_ROM = OFF; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_CLOCK = ON; + USE_LPM_FOR_AHDL_OPERATORS = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + TURBO_BIT = ON; + MAX7000_IGNORE_SOFT_BUFFERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MAX7000_IGNORE_LCELL_BUFFERS = AUTO; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + DSP_BLOCK_BALANCING = AUTO; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(usrp_multi) +{ + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; + USER_LIBRARIES = "e:\usrp\fpga\megacells"; +} +THIRD_PARTY_EDA_TOOLS(usrp_multi) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} +CLOCK(clk_120mhz) +{ + FMAX_REQUIREMENT = "120.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(usbclk) +{ + FMAX_REQUIREMENT = "48.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(SCLK) +{ + FMAX_REQUIREMENT = "1.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk0) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk1) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} diff --git a/usrp1/toplevel/usrp_multi/usrp_multi.qpf b/usrp1/toplevel/usrp_multi/usrp_multi.qpf new file mode 100644 index 000000000..1524de1bb --- /dev/null +++ b/usrp1/toplevel/usrp_multi/usrp_multi.qpf @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2004 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.0" +DATE = "17:10:11 December 20, 2004" + + +# Active Revisions + +PROJECT_REVISION = "usrp_multi" diff --git a/usrp1/toplevel/usrp_multi/usrp_multi.qsf b/usrp1/toplevel/usrp_multi/usrp_multi.qsf new file mode 100644 index 000000000..9f0efbd83 --- /dev/null +++ b/usrp1/toplevel/usrp_multi/usrp_multi.qsf @@ -0,0 +1,408 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# usrp_multi_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" +set_global_assignment -name LAST_QUARTUS_VERSION 6.1 + +# Pin & Location Assignments +# ========================== +set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" +set_location_assignment PIN_29 -to SCLK +set_location_assignment PIN_117 -to SDI +set_location_assignment PIN_28 -to usbclk +set_location_assignment PIN_107 -to usbctl[0] +set_location_assignment PIN_106 -to usbctl[1] +set_location_assignment PIN_105 -to usbctl[2] +set_location_assignment PIN_100 -to usbdata[0] +set_location_assignment PIN_84 -to usbdata[10] +set_location_assignment PIN_83 -to usbdata[11] +set_location_assignment PIN_82 -to usbdata[12] +set_location_assignment PIN_79 -to usbdata[13] +set_location_assignment PIN_78 -to usbdata[14] +set_location_assignment PIN_77 -to usbdata[15] +set_location_assignment PIN_99 -to usbdata[1] +set_location_assignment PIN_98 -to usbdata[2] +set_location_assignment PIN_95 -to usbdata[3] +set_location_assignment PIN_94 -to usbdata[4] +set_location_assignment PIN_93 -to usbdata[5] +set_location_assignment PIN_88 -to usbdata[6] +set_location_assignment PIN_87 -to usbdata[7] +set_location_assignment PIN_86 -to usbdata[8] +set_location_assignment PIN_85 -to usbdata[9] +set_location_assignment PIN_104 -to usbrdy[0] +set_location_assignment PIN_101 -to usbrdy[1] +set_location_assignment PIN_76 -to FX2_1 +set_location_assignment PIN_75 -to FX2_2 +set_location_assignment PIN_74 -to FX2_3 +set_location_assignment PIN_116 -to io_rx_a[0] +set_location_assignment PIN_115 -to io_rx_a[1] +set_location_assignment PIN_114 -to io_rx_a[2] +set_location_assignment PIN_113 -to io_rx_a[3] +set_location_assignment PIN_108 -to io_rx_a[4] +set_location_assignment PIN_195 -to io_rx_a[5] +set_location_assignment PIN_196 -to io_rx_a[6] +set_location_assignment PIN_197 -to io_rx_a[7] +set_location_assignment PIN_200 -to io_rx_a[8] +set_location_assignment PIN_201 -to io_rx_a[9] +set_location_assignment PIN_202 -to io_rx_a[10] +set_location_assignment PIN_203 -to io_rx_a[11] +set_location_assignment PIN_206 -to io_rx_a[12] +set_location_assignment PIN_207 -to io_rx_a[13] +set_location_assignment PIN_208 -to io_rx_a[14] +set_location_assignment PIN_214 -to io_rx_b[0] +set_location_assignment PIN_215 -to io_rx_b[1] +set_location_assignment PIN_216 -to io_rx_b[2] +set_location_assignment PIN_217 -to io_rx_b[3] +set_location_assignment PIN_218 -to io_rx_b[4] +set_location_assignment PIN_219 -to io_rx_b[5] +set_location_assignment PIN_222 -to io_rx_b[6] +set_location_assignment PIN_223 -to io_rx_b[7] +set_location_assignment PIN_224 -to io_rx_b[8] +set_location_assignment PIN_225 -to io_rx_b[9] +set_location_assignment PIN_226 -to io_rx_b[10] +set_location_assignment PIN_227 -to io_rx_b[11] +set_location_assignment PIN_228 -to io_rx_b[12] +set_location_assignment PIN_233 -to io_rx_b[13] +set_location_assignment PIN_234 -to io_rx_b[14] +set_location_assignment PIN_175 -to io_tx_a[0] +set_location_assignment PIN_176 -to io_tx_a[1] +set_location_assignment PIN_177 -to io_tx_a[2] +set_location_assignment PIN_178 -to io_tx_a[3] +set_location_assignment PIN_179 -to io_tx_a[4] +set_location_assignment PIN_180 -to io_tx_a[5] +set_location_assignment PIN_181 -to io_tx_a[6] +set_location_assignment PIN_182 -to io_tx_a[7] +set_location_assignment PIN_183 -to io_tx_a[8] +set_location_assignment PIN_184 -to io_tx_a[9] +set_location_assignment PIN_185 -to io_tx_a[10] +set_location_assignment PIN_186 -to io_tx_a[11] +set_location_assignment PIN_187 -to io_tx_a[12] +set_location_assignment PIN_188 -to io_tx_a[13] +set_location_assignment PIN_193 -to io_tx_a[14] +set_location_assignment PIN_73 -to io_tx_b[0] +set_location_assignment PIN_68 -to io_tx_b[1] +set_location_assignment PIN_67 -to io_tx_b[2] +set_location_assignment PIN_66 -to io_tx_b[3] +set_location_assignment PIN_65 -to io_tx_b[4] +set_location_assignment PIN_64 -to io_tx_b[5] +set_location_assignment PIN_63 -to io_tx_b[6] +set_location_assignment PIN_62 -to io_tx_b[7] +set_location_assignment PIN_61 -to io_tx_b[8] +set_location_assignment PIN_60 -to io_tx_b[9] +set_location_assignment PIN_59 -to io_tx_b[10] +set_location_assignment PIN_58 -to io_tx_b[11] +set_location_assignment PIN_57 -to io_tx_b[12] +set_location_assignment PIN_56 -to io_tx_b[13] +set_location_assignment PIN_55 -to io_tx_b[14] +set_location_assignment PIN_152 -to master_clk +set_location_assignment PIN_144 -to rx_a_a[0] +set_location_assignment PIN_143 -to rx_a_a[1] +set_location_assignment PIN_141 -to rx_a_a[2] +set_location_assignment PIN_140 -to rx_a_a[3] +set_location_assignment PIN_139 -to rx_a_a[4] +set_location_assignment PIN_138 -to rx_a_a[5] +set_location_assignment PIN_137 -to rx_a_a[6] +set_location_assignment PIN_136 -to rx_a_a[7] +set_location_assignment PIN_135 -to rx_a_a[8] +set_location_assignment PIN_134 -to rx_a_a[9] +set_location_assignment PIN_133 -to rx_a_a[10] +set_location_assignment PIN_132 -to rx_a_a[11] +set_location_assignment PIN_23 -to rx_a_b[0] +set_location_assignment PIN_21 -to rx_a_b[1] +set_location_assignment PIN_20 -to rx_a_b[2] +set_location_assignment PIN_19 -to rx_a_b[3] +set_location_assignment PIN_18 -to rx_a_b[4] +set_location_assignment PIN_17 -to rx_a_b[5] +set_location_assignment PIN_16 -to rx_a_b[6] +set_location_assignment PIN_15 -to rx_a_b[7] +set_location_assignment PIN_14 -to rx_a_b[8] +set_location_assignment PIN_13 -to rx_a_b[9] +set_location_assignment PIN_12 -to rx_a_b[10] +set_location_assignment PIN_11 -to rx_a_b[11] +set_location_assignment PIN_131 -to rx_b_a[0] +set_location_assignment PIN_128 -to rx_b_a[1] +set_location_assignment PIN_127 -to rx_b_a[2] +set_location_assignment PIN_126 -to rx_b_a[3] +set_location_assignment PIN_125 -to rx_b_a[4] +set_location_assignment PIN_124 -to rx_b_a[5] +set_location_assignment PIN_123 -to rx_b_a[6] +set_location_assignment PIN_122 -to rx_b_a[7] +set_location_assignment PIN_121 -to rx_b_a[8] +set_location_assignment PIN_120 -to rx_b_a[9] +set_location_assignment PIN_119 -to rx_b_a[10] +set_location_assignment PIN_118 -to rx_b_a[11] +set_location_assignment PIN_8 -to rx_b_b[0] +set_location_assignment PIN_7 -to rx_b_b[1] +set_location_assignment PIN_6 -to rx_b_b[2] +set_location_assignment PIN_5 -to rx_b_b[3] +set_location_assignment PIN_4 -to rx_b_b[4] +set_location_assignment PIN_3 -to rx_b_b[5] +set_location_assignment PIN_2 -to rx_b_b[6] +set_location_assignment PIN_240 -to rx_b_b[7] +set_location_assignment PIN_239 -to rx_b_b[8] +set_location_assignment PIN_238 -to rx_b_b[9] +set_location_assignment PIN_237 -to rx_b_b[10] +set_location_assignment PIN_236 -to rx_b_b[11] +set_location_assignment PIN_156 -to SDO +set_location_assignment PIN_153 -to SEN_FPGA +set_location_assignment PIN_159 -to tx_a[0] +set_location_assignment PIN_160 -to tx_a[1] +set_location_assignment PIN_161 -to tx_a[2] +set_location_assignment PIN_162 -to tx_a[3] +set_location_assignment PIN_163 -to tx_a[4] +set_location_assignment PIN_164 -to tx_a[5] +set_location_assignment PIN_165 -to tx_a[6] +set_location_assignment PIN_166 -to tx_a[7] +set_location_assignment PIN_167 -to tx_a[8] +set_location_assignment PIN_168 -to tx_a[9] +set_location_assignment PIN_169 -to tx_a[10] +set_location_assignment PIN_170 -to tx_a[11] +set_location_assignment PIN_173 -to tx_a[12] +set_location_assignment PIN_174 -to tx_a[13] +set_location_assignment PIN_38 -to tx_b[0] +set_location_assignment PIN_39 -to tx_b[1] +set_location_assignment PIN_41 -to tx_b[2] +set_location_assignment PIN_42 -to tx_b[3] +set_location_assignment PIN_43 -to tx_b[4] +set_location_assignment PIN_44 -to tx_b[5] +set_location_assignment PIN_45 -to tx_b[6] +set_location_assignment PIN_46 -to tx_b[7] +set_location_assignment PIN_47 -to tx_b[8] +set_location_assignment PIN_48 -to tx_b[9] +set_location_assignment PIN_49 -to tx_b[10] +set_location_assignment PIN_50 -to tx_b[11] +set_location_assignment PIN_53 -to tx_b[12] +set_location_assignment PIN_54 -to tx_b[13] +set_location_assignment PIN_158 -to TXSYNC_A +set_location_assignment PIN_37 -to TXSYNC_B +set_location_assignment PIN_235 -to io_rx_b[15] +set_location_assignment PIN_24 -to io_tx_b[15] +set_location_assignment PIN_213 -to io_rx_a[15] +set_location_assignment PIN_194 -to io_tx_a[15] +set_location_assignment PIN_1 -to MYSTERY_SIGNAL + +# Timing Assignments +# ================== +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name TOP_LEVEL_ENTITY usrp_multi +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name USER_LIBRARIES "H:\\usrp-for2.7\\fpga\\megacells" +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name INC_PLC_MODE OFF +set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF +set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# Timing Analysis Assignments +# =========================== +set_global_assignment -name MAX_SCC_SIZE 50 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF + +# Simulator Assignments +# ===================== +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "1 ns" + +# Design Assistant Assignments +# ============================ +set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF +set_global_assignment -name ASSG_CAT OFF +set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF +set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF +set_global_assignment -name CLK_CAT OFF +set_global_assignment -name CLK_RULE_COMB_CLOCK OFF +set_global_assignment -name CLK_RULE_INV_CLOCK OFF +set_global_assignment -name CLK_RULE_GATING_SCHEME OFF +set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF +set_global_assignment -name CLK_RULE_MIX_EDGES OFF +set_global_assignment -name RESET_CAT OFF +set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name TIMING_CAT OFF +set_global_assignment -name TIMING_RULE_SHIFT_REG OFF +set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF +set_global_assignment -name NONSYNCHSTRUCT_CAT OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF +set_global_assignment -name SIGNALRACE_CAT OFF +set_global_assignment -name ACLK_CAT OFF +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF +set_global_assignment -name HCPY_CAT OFF +set_global_assignment -name HCPY_VREF_PINS OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name HUB_ENTITY_NAME SLD_HUB +set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST +set_global_assignment -name ENABLE_SIGNALTAP OFF + +# LogicLock Region Assignments +# ============================ +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF + +# ----------------- +# start CLOCK(SCLK) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK +set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK + +# end CLOCK(SCLK) +# --------------- + +# ----------------------- +# start CLOCK(master_clk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk +set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk + +# end CLOCK(master_clk) +# --------------------- + +# ------------------- +# start CLOCK(usbclk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk +set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk + +# end CLOCK(usbclk) +# ----------------- + +# ---------------------- +# start ENTITY(usrp_multi) + + # Timing Assignments + # ================== +set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK +set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk +set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk + +# end ENTITY(usrp_multi) +# -------------------- + + +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg_masked.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control_multi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v +set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v +set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v +set_global_assignment -name VERILOG_FILE usrp_multi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file diff --git a/usrp1/toplevel/usrp_multi/usrp_multi.v b/usrp1/toplevel/usrp_multi/usrp_multi.v new file mode 100644 index 000000000..ce484fc1c --- /dev/null +++ b/usrp1/toplevel/usrp_multi/usrp_multi.v @@ -0,0 +1,379 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2004,2005,2006 Matt Ettus +// Copyright (C) 2006 Martin Dudok van Heel +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Top level module for a full setup with DUCs and DDCs + +// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins +// for debugging info. NB, This can kill the m'board and/or d'board if you +// have anything except basic d'boards installed. + +// Uncomment the following to include optional circuitry + +`include "config.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module usrp_multi +(output MYSTERY_SIGNAL, + input master_clk, + input SCLK, + input SDI, + inout SDO, + input SEN_FPGA, + + input FX2_1, + output FX2_2, + output FX2_3, + + input wire [11:0] rx_a_a, + input wire [11:0] rx_b_a, + input wire [11:0] rx_a_b, + input wire [11:0] rx_b_b, + + output wire [13:0] tx_a, + output wire [13:0] tx_b, + + output wire TXSYNC_A, + output wire TXSYNC_B, + + // USB interface + input usbclk, + input wire [2:0] usbctl, + output wire [1:0] usbrdy, + inout [15:0] usbdata, // NB Careful, inout + + // These are the general purpose i/o's that go to the daughterboard slots + inout wire [15:0] io_tx_a, + inout wire [15:0] io_tx_b, + inout wire [15:0] io_rx_a, + inout wire [15:0] io_rx_b + ); + wire [15:0] debugdata,debugctrl; + assign MYSTERY_SIGNAL = 1'b0; + + wire clk64,clk128; + + wire WR = usbctl[0]; + wire RD = usbctl[1]; + wire OE = usbctl[2]; + + wire have_space, have_pkt_rdy; + assign usbrdy[0] = have_space; + assign usbrdy[1] = have_pkt_rdy; + + wire tx_underrun, rx_overrun; + wire clear_status = FX2_1; + assign FX2_2 = rx_overrun; + assign FX2_3 = tx_underrun; + + wire [15:0] usbdata_out; + + wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; + + wire tx_realsignals; + wire [3:0] rx_numchan; + wire [2:0] tx_numchan; + + wire [7:0] interp_rate, decim_rate; + wire [15:0] tx_debugbus, rx_debugbus; + + wire enable_tx, enable_rx; + wire reset_data; +`ifdef MULTI_ON + wire sync_rx; + assign reset_data = sync_rx; +`else + assign reset_data = 1'b0; +`endif // `ifdef MULTI_ON + + wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; + wire [7:0] settings; + + // Tri-state bus macro + bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); + + assign clk64 = master_clk; + + wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; + wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; + + // TX + wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; + wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; + + wire strobe_interp, tx_sample_strobe; + wire tx_empty; + + wire serial_strobe; + wire [6:0] serial_addr; + wire [31:0] serial_data; + + reg [15:0] debug_counter; +`ifdef COUNTER_32BIT_ON + reg [31:0] sample_counter_32bit; +`endif // `ifdef COUNTER_32BIT_ON + reg [15:0] loopback_i_0,loopback_q_0; + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Transmit Side +`ifdef TX_ON + assign bb_tx_i0 = ch0tx; + assign bb_tx_q0 = ch1tx; + assign bb_tx_i1 = ch2tx; + assign bb_tx_q1 = ch3tx; + + tx_buffer tx_buffer + ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), + .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), + .channels({tx_numchan,1'b0}), + .tx_i_0(ch0tx),.tx_q_0(ch1tx), + .tx_i_1(ch2tx),.tx_q_1(ch3tx), + .tx_i_2(),.tx_q_2(), + .tx_i_3(),.tx_q_3(), + .txclk(clk64),.txstrobe(strobe_interp), + .clear_status(clear_status), + .tx_empty(tx_empty), + .debugbus(tx_debugbus) ); + + tx_chain tx_chain_0 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); + + tx_chain tx_chain_1 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); + + setting_reg #(`FR_TX_MUX) + sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; + + wire txsync = tx_sample_strobe; + assign TXSYNC_A = txsync; + assign TXSYNC_B = txsync; + + assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; + assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; +`endif // `ifdef TX_ON + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Receive Side +`ifdef RX_ON + wire rx_sample_strobe,strobe_decim,hb_strobe; + wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, + bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; + + wire loopback = settings[0]; + wire counter = settings[1]; +`ifdef COUNTER_32BIT_ON + wire counter_32bit = settings[2]; + + always @(posedge clk64) + if(rx_dsp_reset) + sample_counter_32bit <= #1 32'd0; + else if(~enable_rx | reset_data) + sample_counter_32bit <=#1 32'd0; + else if(hb_strobe) + sample_counter_32bit <=#1 sample_counter_32bit + 32'd1; +`endif // `ifdef COUNTER_32BIT_ON + + always @(posedge clk64) + if(rx_dsp_reset) + debug_counter <= #1 16'd0; + else if(~enable_rx) + debug_counter <= #1 16'd0; + else if(hb_strobe) + debug_counter <=#1 debug_counter + 16'd2; + + always @(posedge clk64) + if(strobe_interp) + begin + loopback_i_0 <= #1 ch0tx; + loopback_q_0 <= #1 ch1tx; + end + +`ifdef COUNTER_32BIT_ON + assign ch0rx = counter_32bit?sample_counter_32bit[31:16]:counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; + assign ch1rx = counter_32bit?sample_counter_32bit[15:0]:counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; + assign ch2rx = bb_rx_i1; + assign ch3rx = bb_rx_q1; + assign ch4rx = counter_32bit?bb_rx_i0:bb_rx_i2; + assign ch5rx = counter_32bit?bb_rx_q0:bb_rx_q2;// If using counter replicate channels here to be able to get rx_i0 when using counter + //This means if you use 4 channels that channel 3 will be replaced by channel 0 + // and channel 0 will output the 32 bit counter. + assign ch6rx = bb_rx_i3; + assign ch7rx = bb_rx_q3; +`else + assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; + assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; + assign ch2rx = bb_rx_i1; + assign ch3rx = bb_rx_q1; + assign ch4rx = bb_rx_i2; + assign ch5rx = bb_rx_q2; + assign ch6rx = bb_rx_i3; + assign ch7rx = bb_rx_q3; +`endif // `ifdef COUNTER_32BIT_ON + + + wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; + adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), + .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), + .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), + .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), + .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); + + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset | reset_data), + .reset_regs(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(ch0rx),.ch_1(ch1rx), + .ch_2(ch2rx),.ch_3(ch3rx), + .ch_4(ch4rx),.ch_5(ch5rx), + .ch_6(ch6rx),.ch_7(ch7rx), + .rxclk(clk64),.rxstrobe(hb_strobe), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .debugbus(rx_debugbus) ); + + `ifdef RX_EN_0 + rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 + ( .clock(clk64),.reset(reset_data),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); + `else + assign bb_rx_i0=16'd0; + assign bb_rx_q0=16'd0; + `endif + + `ifdef RX_EN_1 + rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 + ( .clock(clk64),.reset(reset_data),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); + `else + assign bb_rx_i1=16'd0; + assign bb_rx_q1=16'd0; + `endif + + `ifdef RX_EN_2 + rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 + ( .clock(clk64),.reset(reset_data),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); + `else + assign bb_rx_i2=16'd0; + assign bb_rx_q2=16'd0; + `endif + + `ifdef RX_EN_3 + rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 + ( .clock(clk64),.reset(reset_data),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); + assign bb_rx_i3=16'd0; + assign bb_rx_q3=16'd0; + `endif + +`endif // `ifdef RX_ON + + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Control Functions + + wire [31:0] capabilities; + assign capabilities[7] = `TX_CAP_HB; + assign capabilities[6:4] = `TX_CAP_NCHAN; + assign capabilities[3] = `RX_CAP_HB; + assign capabilities[2:0] = `RX_CAP_NCHAN; + + + serial_io serial_io + ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), + .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) ); + + wire [15:0] reg_0,reg_1,reg_2,reg_3; + +`ifdef MULTI_ON + + master_control_multi master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .rx_slave_sync(io_rx_a[`bitnoFR_RX_SYNC_INPUT_IOPIN]), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .sync_rx(sync_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + //.debug_0(rx_a_a),.debug_1(ddc0_in_i), + .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + +`else //`ifdef MULTI_ON + + master_control master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + //.debug_0(rx_a_a),.debug_1(ddc0_in_i), + .debug_0(rx_debugbus),.debug_1(ddc0_in_i), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + +`endif //`ifdef MULTI_ON + + io_pins io_pins + (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Misc Settings + setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); + +endmodule // usrp_multi diff --git a/usrp1/toplevel/usrp_std/.gitignore b/usrp1/toplevel/usrp_std/.gitignore new file mode 100644 index 000000000..31d6ea9ef --- /dev/null +++ b/usrp1/toplevel/usrp_std/.gitignore @@ -0,0 +1,17 @@ +/*.qws +/*.eqn +/*.done +/*.htm +/*.rpt +/*.ini +/*.fsf +/*.jam +/*.jbc +/*.pin +/*.pof +/*.sof +/*.rbf +/*.ttf +/*.summary +/prev* +/db diff --git a/usrp1/toplevel/usrp_std/config.vh b/usrp1/toplevel/usrp_std/config.vh new file mode 100644 index 000000000..f1f8ec40e --- /dev/null +++ b/usrp1/toplevel/usrp_std/config.vh @@ -0,0 +1,53 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2006,2007 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// ==================================================================== +// User control over what parts get included +// +// >>>> EDIT ONLY THIS SECTION <<<< +// Uncomment only ONE configuration +// ==================================================================== + +// ==================================================================== +// FIXME drive configuration selection from the command line and/or gui +// ==================================================================== + +// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel +//`include "../include/common_config_1rxhb_1tx.vh" + +// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels + `include "../include/common_config_2rxhb_2tx.vh" + +// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_4rx_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels +//`include "../include/common_config_2rxhb_0tx.vh" + +// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels +//`include "../include/common_config_2rx_0tx.vh" + +// Add other "known to fit" configurations here... + +// ==================================================================== +// Now include the common footer +// ==================================================================== + `include "../include/common_config_bottom.vh" diff --git a/usrp1/toplevel/usrp_std/usrp_std.csf b/usrp1/toplevel/usrp_std/usrp_std.csf new file mode 100644 index 000000000..627197caf --- /dev/null +++ b/usrp1/toplevel/usrp_std/usrp_std.csf @@ -0,0 +1,444 @@ +COMPILER_SETTINGS +{ + IO_PLACEMENT_OPTIMIZATION = OFF; + ENABLE_DRC_SETTINGS = OFF; + PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; + PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; + PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; + DRC_FANOUT_EXCEEDING = 30; + DRC_REPORT_FANOUT_EXCEEDING = OFF; + DRC_TOP_FANOUT = 50; + DRC_REPORT_TOP_FANOUT = OFF; + RUN_DRC_DURING_COMPILATION = OFF; + ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; + ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; + ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; + ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; + SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; + MERGE_HEX_FILE = OFF; + TRUE_WYSIWYG_FLOW = OFF; + SEED = 1; + FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; + FAMILY = Cyclone; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; + DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; + DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; + DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; + DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; + DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; + DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; + DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; + DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; + DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; + STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; + PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; + STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; + FAST_FIT_COMPILATION = OFF; + SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; + OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; + OPTIMIZE_TIMING = "NORMAL COMPILATION"; + OPTIMIZE_HOLD_TIMING = OFF; + COMPILATION_LEVEL = FULL; + SAVE_DISK_SPACE = OFF; + SPEED_DISK_USAGE_TRADEOFF = NORMAL; + LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; + SIGNALPROBE_ALLOW_OVERUSE = OFF; + FOCUS_ENTITY_NAME = |usrp_std; + ROUTING_BACK_ANNOTATION_MODE = OFF; + INC_PLC_MODE = OFF; + FIT_ONLY_ONE_ATTEMPT = OFF; +} +DEFAULT_DEVICE_OPTIONS +{ + GENERATE_CONFIG_HEXOUT_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_JBC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_SVF_FILE = OFF; + RESERVE_PIN = "AS INPUT TRI-STATED"; + RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; + HEXOUT_FILE_COUNT_DIRECTION = UP; + HEXOUT_FILE_START_ADDRESS = 0; + GENERATE_HEX_FILE = OFF; + GENERATE_RBF_FILE = OFF; + GENERATE_TTF_FILE = OFF; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + APEX20K_CONFIGURATION_DEVICE = AUTO; + USE_CONFIGURATION_DEVICE = ON; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + AUTO_RESTART_CONFIGURATION = OFF; + ENABLE_VREFB_PIN = OFF; + ENABLE_VREFA_PIN = OFF; + SECURITY_BIT = OFF; + USER_START_UP_CLOCK = OFF; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_UPDATE_MODE = STANDARD; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + ENABLE_JTAG_BST_SUPPORT = OFF; + CONFIGURATION_CLOCK_DIVISOR = 1; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CLOCK_SOURCE = INTERNAL; + COMPRESSION_MODE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; +} +AUTO_SLD_HUB_ENTITY +{ + AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; + HUB_INSTANCE_NAME = SLD_HUB_INST; + HUB_ENTITY_NAME = SLD_HUB; +} +SIGNALTAP_LOGIC_ANALYZER_SETTINGS +{ + ENABLE_SIGNALTAP = Off; + AUTO_ENABLE_SMART_COMPILE = On; +} +CHIP(usrp_std) +{ + DEVICE = EP1C12Q240C8; + DEVICE_FILTER_PACKAGE = "ANY QFP"; + DEVICE_FILTER_PIN_COUNT = 240; + DEVICE_FILTER_SPEED_GRADE = ANY; + AUTO_RESTART_CONFIGURATION = OFF; + RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; + USER_START_UP_CLOCK = OFF; + ENABLE_DEVICE_WIDE_RESET = OFF; + ENABLE_DEVICE_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + ENABLE_JTAG_BST_SUPPORT = OFF; + MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; + APEX20K_JTAG_USER_CODE = FFFFFFFF; + MERCURY_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_JTAG_USER_CODE = 7F; + MAX7000_JTAG_USER_CODE = FFFFFFFF; + MAX7000S_JTAG_USER_CODE = FFFF; + STRATIX_JTAG_USER_CODE = FFFFFFFF; + APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; + USE_CONFIGURATION_DEVICE = OFF; + APEX20K_CONFIGURATION_DEVICE = AUTO; + MERCURY_CONFIGURATION_DEVICE = AUTO; + FLEX6K_CONFIGURATION_DEVICE = AUTO; + FLEX10K_CONFIGURATION_DEVICE = AUTO; + EXCALIBUR_CONFIGURATION_DEVICE = AUTO; + STRATIX_CONFIGURATION_DEVICE = AUTO; + CYCLONE_CONFIGURATION_DEVICE = AUTO; + STRATIX_UPDATE_MODE = STANDARD; + APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; + AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; + DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; + COMPRESSION_MODE = OFF; + ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; + FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; + EPROM_USE_CHECKSUM_AS_USERCODE = OFF; + USE_CHECKSUM_AS_USERCODE = OFF; + MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; + GENERATE_TTF_FILE = OFF; + GENERATE_RBF_FILE = ON; + GENERATE_HEX_FILE = OFF; + SECURITY_BIT = OFF; + ENABLE_VREFA_PIN = OFF; + ENABLE_VREFB_PIN = OFF; + GENERATE_SVF_FILE = OFF; + GENERATE_ISC_FILE = OFF; + GENERATE_JAM_FILE = OFF; + GENERATE_JBC_FILE = OFF; + GENERATE_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_SVF_FILE = OFF; + GENERATE_CONFIG_ISC_FILE = OFF; + GENERATE_CONFIG_JAM_FILE = OFF; + GENERATE_CONFIG_JBC_FILE = OFF; + GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; + GENERATE_CONFIG_HEXOUT_FILE = OFF; + ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; + BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; + HEXOUT_FILE_START_ADDRESS = 0; + HEXOUT_FILE_COUNT_DIRECTION = UP; + RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; + STRATIX_DEVICE_IO_STANDARD = LVTTL; + CLOCK_SOURCE = INTERNAL; + CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; + CONFIGURATION_CLOCK_DIVISOR = 1; + RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; + RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; + SCLK : LOCATION = Pin_101; + SDI : LOCATION = Pin_100; + SEN : LOCATION = Pin_98; + SLD : LOCATION = Pin_95; + adc1_data[0] : LOCATION = Pin_5; + adc1_data[10] : LOCATION = Pin_235; + adc1_data[11] : LOCATION = Pin_234; + adc1_data[1] : LOCATION = Pin_4; + adc1_data[2] : LOCATION = Pin_3; + adc1_data[3] : LOCATION = Pin_2; + adc1_data[4] : LOCATION = Pin_1; + adc1_data[4] : IO_STANDARD = LVTTL; + adc1_data[5] : LOCATION = Pin_240; + adc1_data[6] : LOCATION = Pin_239; + adc1_data[7] : LOCATION = Pin_238; + adc1_data[8] : LOCATION = Pin_237; + adc1_data[9] : LOCATION = Pin_236; + adc2_data[0] : LOCATION = Pin_20; + adc2_data[10] : LOCATION = Pin_8; + adc2_data[11] : LOCATION = Pin_7; + adc2_data[1] : LOCATION = Pin_19; + adc2_data[2] : LOCATION = Pin_18; + adc2_data[3] : LOCATION = Pin_17; + adc2_data[4] : LOCATION = Pin_16; + adc2_data[5] : LOCATION = Pin_15; + adc2_data[6] : LOCATION = Pin_14; + adc2_data[7] : LOCATION = Pin_13; + adc2_data[8] : LOCATION = Pin_12; + adc2_data[9] : LOCATION = Pin_11; + adc3_data[0] : LOCATION = Pin_200; + adc3_data[10] : LOCATION = Pin_184; + adc3_data[11] : LOCATION = Pin_183; + adc3_data[1] : LOCATION = Pin_197; + adc3_data[2] : LOCATION = Pin_196; + adc3_data[3] : LOCATION = Pin_195; + adc3_data[4] : LOCATION = Pin_194; + adc3_data[5] : LOCATION = Pin_193; + adc3_data[6] : LOCATION = Pin_188; + adc3_data[7] : LOCATION = Pin_187; + adc3_data[8] : LOCATION = Pin_186; + adc3_data[9] : LOCATION = Pin_185; + adc4_data[0] : LOCATION = Pin_222; + adc4_data[10] : LOCATION = Pin_203; + adc4_data[11] : LOCATION = Pin_202; + adc4_data[1] : LOCATION = Pin_219; + adc4_data[2] : LOCATION = Pin_217; + adc4_data[3] : LOCATION = Pin_216; + adc4_data[4] : LOCATION = Pin_215; + adc4_data[5] : LOCATION = Pin_214; + adc4_data[6] : LOCATION = Pin_213; + adc4_data[7] : LOCATION = Pin_208; + adc4_data[8] : LOCATION = Pin_207; + adc4_data[9] : LOCATION = Pin_206; + adc_oeb[0] : LOCATION = Pin_228; + adc_oeb[1] : LOCATION = Pin_21; + adc_oeb[2] : LOCATION = Pin_181; + adc_oeb[3] : LOCATION = Pin_218; + adc_otr[0] : LOCATION = Pin_233; + adc_otr[1] : LOCATION = Pin_6; + adc_otr[2] : LOCATION = Pin_182; + adc_otr[3] : LOCATION = Pin_201; + adclk0 : LOCATION = Pin_224; + adclk1 : LOCATION = Pin_226; + clk0 : LOCATION = Pin_28; + clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk0 : IO_STANDARD = LVTTL; + clk1 : LOCATION = Pin_29; + clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk1 : IO_STANDARD = LVTTL; + clk3 : LOCATION = Pin_152; + clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; + clk3 : IO_STANDARD = LVTTL; + clk_120mhz : LOCATION = Pin_153; + clk_120mhz : IO_STANDARD = LVTTL; + clk_out : LOCATION = Pin_63; + clk_out : IO_STANDARD = LVTTL; + dac1_data[0] : LOCATION = Pin_165; + dac1_data[10] : LOCATION = Pin_177; + dac1_data[11] : LOCATION = Pin_178; + dac1_data[12] : LOCATION = Pin_179; + dac1_data[13] : LOCATION = Pin_180; + dac1_data[1] : LOCATION = Pin_166; + dac1_data[2] : LOCATION = Pin_167; + dac1_data[3] : LOCATION = Pin_168; + dac1_data[4] : LOCATION = Pin_169; + dac1_data[5] : LOCATION = Pin_170; + dac1_data[6] : LOCATION = Pin_173; + dac1_data[7] : LOCATION = Pin_174; + dac1_data[8] : LOCATION = Pin_175; + dac1_data[9] : LOCATION = Pin_176; + dac2_data[0] : LOCATION = Pin_159; + dac2_data[10] : LOCATION = Pin_163; + dac2_data[11] : LOCATION = Pin_139; + dac2_data[12] : LOCATION = Pin_164; + dac2_data[13] : LOCATION = Pin_138; + dac2_data[1] : LOCATION = Pin_158; + dac2_data[2] : LOCATION = Pin_160; + dac2_data[3] : LOCATION = Pin_156; + dac2_data[4] : LOCATION = Pin_161; + dac2_data[5] : LOCATION = Pin_144; + dac2_data[6] : LOCATION = Pin_162; + dac2_data[7] : LOCATION = Pin_141; + dac2_data[8] : LOCATION = Pin_143; + dac2_data[9] : LOCATION = Pin_140; + dac3_data[0] : LOCATION = Pin_122; + dac3_data[10] : LOCATION = Pin_134; + dac3_data[11] : LOCATION = Pin_135; + dac3_data[12] : LOCATION = Pin_136; + dac3_data[13] : LOCATION = Pin_137; + dac3_data[1] : LOCATION = Pin_123; + dac3_data[2] : LOCATION = Pin_124; + dac3_data[3] : LOCATION = Pin_125; + dac3_data[4] : LOCATION = Pin_126; + dac3_data[5] : LOCATION = Pin_127; + dac3_data[6] : LOCATION = Pin_128; + dac3_data[7] : LOCATION = Pin_131; + dac3_data[8] : LOCATION = Pin_132; + dac3_data[9] : LOCATION = Pin_133; + dac4_data[0] : LOCATION = Pin_104; + dac4_data[10] : LOCATION = Pin_118; + dac4_data[11] : LOCATION = Pin_119; + dac4_data[12] : LOCATION = Pin_120; + dac4_data[13] : LOCATION = Pin_121; + dac4_data[1] : LOCATION = Pin_105; + dac4_data[2] : LOCATION = Pin_106; + dac4_data[3] : LOCATION = Pin_107; + dac4_data[4] : LOCATION = Pin_108; + dac4_data[5] : LOCATION = Pin_113; + dac4_data[6] : LOCATION = Pin_114; + dac4_data[7] : LOCATION = Pin_115; + dac4_data[8] : LOCATION = Pin_116; + dac4_data[9] : LOCATION = Pin_117; + enable_rx : LOCATION = Pin_88; + enable_tx : LOCATION = Pin_93; + gndbus[0] : LOCATION = Pin_223; + gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[0] : IO_STANDARD = LVTTL; + gndbus[1] : LOCATION = Pin_225; + gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[1] : IO_STANDARD = LVTTL; + gndbus[2] : LOCATION = Pin_227; + gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[2] : IO_STANDARD = LVTTL; + gndbus[3] : LOCATION = Pin_62; + gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[3] : IO_STANDARD = LVTTL; + gndbus[4] : LOCATION = Pin_64; + gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; + gndbus[4] : IO_STANDARD = LVTTL; + misc_pins[0] : LOCATION = Pin_87; + misc_pins[0] : IO_STANDARD = LVTTL; + misc_pins[10] : LOCATION = Pin_76; + misc_pins[10] : IO_STANDARD = LVTTL; + misc_pins[11] : LOCATION = Pin_74; + misc_pins[11] : IO_STANDARD = LVTTL; + misc_pins[1] : LOCATION = Pin_86; + misc_pins[1] : IO_STANDARD = LVTTL; + misc_pins[2] : LOCATION = Pin_85; + misc_pins[2] : IO_STANDARD = LVTTL; + misc_pins[3] : LOCATION = Pin_84; + misc_pins[3] : IO_STANDARD = LVTTL; + misc_pins[4] : LOCATION = Pin_83; + misc_pins[4] : IO_STANDARD = LVTTL; + misc_pins[5] : LOCATION = Pin_82; + misc_pins[5] : IO_STANDARD = LVTTL; + misc_pins[6] : LOCATION = Pin_79; + misc_pins[6] : IO_STANDARD = LVTTL; + misc_pins[7] : LOCATION = Pin_78; + misc_pins[7] : IO_STANDARD = LVTTL; + misc_pins[8] : LOCATION = Pin_77; + misc_pins[8] : IO_STANDARD = LVTTL; + misc_pins[9] : LOCATION = Pin_75; + misc_pins[9] : IO_STANDARD = LVTTL; + reset : LOCATION = Pin_94; + usbclk : LOCATION = Pin_55; + usbctl[0] : LOCATION = Pin_56; + usbctl[1] : LOCATION = Pin_54; + usbctl[2] : LOCATION = Pin_53; + usbctl[3] : LOCATION = Pin_58; + usbctl[4] : LOCATION = Pin_57; + usbctl[5] : LOCATION = Pin_44; + usbdata[0] : LOCATION = Pin_73; + usbdata[10] : LOCATION = Pin_41; + usbdata[11] : LOCATION = Pin_39; + usbdata[12] : LOCATION = Pin_38; + usbdata[12] : IO_STANDARD = LVTTL; + usbdata[13] : LOCATION = Pin_37; + usbdata[14] : LOCATION = Pin_24; + usbdata[15] : LOCATION = Pin_23; + usbdata[1] : LOCATION = Pin_68; + usbdata[2] : LOCATION = Pin_67; + usbdata[3] : LOCATION = Pin_66; + usbdata[4] : LOCATION = Pin_65; + usbdata[5] : LOCATION = Pin_61; + usbdata[6] : LOCATION = Pin_60; + usbdata[7] : LOCATION = Pin_59; + usbdata[8] : LOCATION = Pin_43; + usbdata[9] : LOCATION = Pin_42; + usbrdy[0] : LOCATION = Pin_45; + usbrdy[1] : LOCATION = Pin_46; + usbrdy[2] : LOCATION = Pin_47; + usbrdy[3] : LOCATION = Pin_48; + usbrdy[4] : LOCATION = Pin_49; + usbrdy[5] : LOCATION = Pin_50; + clear_status : LOCATION = Pin_99; +} diff --git a/usrp1/toplevel/usrp_std/usrp_std.esf b/usrp1/toplevel/usrp_std/usrp_std.esf new file mode 100644 index 000000000..b88c15994 --- /dev/null +++ b/usrp1/toplevel/usrp_std/usrp_std.esf @@ -0,0 +1,14 @@ +SIMULATOR_SETTINGS +{ + ESTIMATE_POWER_CONSUMPTION = OFF; + GLITCH_INTERVAL = 1NS; + GLITCH_DETECTION = OFF; + SIMULATION_COVERAGE = ON; + CHECK_OUTPUTS = OFF; + SETUP_HOLD_DETECTION = OFF; + POWER_ESTIMATION_START_TIME = "0 NS"; + ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; + SIMULATION_MODE = TIMING; + START_TIME = 0NS; + USE_COMPILER_SETTINGS = usrp_std; +} diff --git a/usrp1/toplevel/usrp_std/usrp_std.psf b/usrp1/toplevel/usrp_std/usrp_std.psf new file mode 100644 index 000000000..506c81b6a --- /dev/null +++ b/usrp1/toplevel/usrp_std/usrp_std.psf @@ -0,0 +1,312 @@ +DEFAULT_DESIGN_ASSISTANT_SETTINGS +{ + HCPY_ALOAD_SIGNALS = OFF; + HCPY_VREF_PINS = OFF; + HCPY_CAT = OFF; + HCPY_ILLEGAL_HC_DEV_PKG = OFF; + ACLK_RULE_IMSZER_ADOMAIN = OFF; + ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; + ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; + ACLK_CAT = OFF; + SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; + SIGNALRACE_CAT = OFF; + NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; + NONSYNCHSTRUCT_RULE_SRLATCH = OFF; + NONSYNCHSTRUCT_RULE_DLATCH = OFF; + NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; + NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; + NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; + NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; + NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; + NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; + NONSYNCHSTRUCT_CAT = OFF; + NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; + TIMING_RULE_COIN_CLKEDGE = OFF; + TIMING_RULE_SHIFT_REG = OFF; + TIMING_RULE_HIGH_FANOUTS = OFF; + TIMING_CAT = OFF; + RESET_RULE_ALL = OFF; + RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; + RESET_RULE_REG_ASNYCH = OFF; + RESET_RULE_COMB_ASYNCH_RESET = OFF; + RESET_RULE_IMSYNCH_EXRESET = OFF; + RESET_RULE_UNSYNCH_EXRESET = OFF; + RESET_RULE_INPINS_RESETNET = OFF; + RESET_CAT = OFF; + CLK_RULE_ALL = OFF; + CLK_RULE_MIX_EDGES = OFF; + CLK_RULE_CLKNET_CLKSPINES = OFF; + CLK_RULE_INPINS_CLKNET = OFF; + CLK_RULE_GATING_SCHEME = OFF; + CLK_RULE_INV_CLOCK = OFF; + CLK_RULE_COMB_CLOCK = OFF; + CLK_CAT = OFF; + HCPY_EXCEED_USER_IO_USAGE = OFF; + HCPY_EXCEED_RAM_USAGE = OFF; + NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; + SIGNALRACE_RULE_TRISTATE = OFF; + ASSG_RULE_MISSING_TIMING = OFF; + ASSG_RULE_MISSING_FMAX = OFF; + ASSG_CAT = OFF; +} +SYNTHESIS_FITTING_SETTINGS +{ + AUTO_SHIFT_REGISTER_RECOGNITION = ON; + AUTO_DSP_RECOGNITION = ON; + AUTO_RAM_RECOGNITION = ON; + REMOVE_DUPLICATE_LOGIC = ON; + AUTO_TURBO_BIT = ON; + AUTO_MERGE_PLLS = ON; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_PARALLEL_EXPANDERS = ON; + AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; + AUTO_FAST_OUTPUT_REGISTERS = OFF; + AUTO_FAST_INPUT_REGISTERS = OFF; + AUTO_CASCADE_CHAINS = ON; + AUTO_CARRY_CHAINS = ON; + AUTO_DELAY_CHAINS = ON; + MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; + PARALLEL_EXPANDER_CHAIN_LENGTH = 16; + CASCADE_CHAIN_LENGTH = 2; + STRATIX_CARRY_CHAIN_LENGTH = 70; + MERCURY_CARRY_CHAIN_LENGTH = 48; + FLEX10K_CARRY_CHAIN_LENGTH = 32; + FLEX6K_CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN_LENGTH = 48; + CARRY_OUT_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + AUTO_LCELL_INSERTION = ON; + ALLOW_XOR_GATE_USAGE = ON; + AUTO_PACKED_REGISTERS_STRATIX = NORMAL; + AUTO_PACKED_REGISTERS = OFF; + AUTO_PACKED_REG_CYCLONE = NORMAL; + FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; + FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; + MERCURY_OPTIMIZATION_TECHNIQUE = AREA; + APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; + MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; + STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; + CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; + FLEX10K_TECHNOLOGY_MAPPER = LUT; + FLEX6K_TECHNOLOGY_MAPPER = LUT; + MERCURY_TECHNOLOGY_MAPPER = LUT; + APEX20K_TECHNOLOGY_MAPPER = LUT; + MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; + STRATIX_TECHNOLOGY_MAPPER = LUT; + AUTO_IMPLEMENT_IN_ROM = OFF; + AUTO_GLOBAL_MEMORY_CONTROLS = OFF; + AUTO_GLOBAL_REGISTER_CONTROLS = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_CLOCK = ON; + USE_LPM_FOR_AHDL_OPERATORS = ON; + LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; + ENABLE_BUS_HOLD_CIRCUITRY = OFF; + WEAK_PULL_UP_RESISTOR = OFF; + TURBO_BIT = ON; + MAX7000_IGNORE_SOFT_BUFFERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MAX7000_IGNORE_LCELL_BUFFERS = AUTO; + IGNORE_LCELL_BUFFERS = OFF; + IGNORE_ROW_GLOBAL_BUFFERS = OFF; + IGNORE_GLOBAL_BUFFERS = OFF; + IGNORE_CASCADE_BUFFERS = OFF; + IGNORE_CARRY_BUFFERS = OFF; + REMOVE_DUPLICATE_REGISTERS = ON; + REMOVE_REDUNDANT_LOGIC_CELLS = OFF; + ALLOW_POWER_UP_DONT_CARE = ON; + PCI_IO = OFF; + NOT_GATE_PUSH_BACK = ON; + SLOW_SLEW_RATE = OFF; + DSP_BLOCK_BALANCING = AUTO; + STATE_MACHINE_PROCESSING = AUTO; +} +DEFAULT_HARDCOPY_SETTINGS +{ + HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; +} +DEFAULT_TIMING_REQUIREMENTS +{ + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + RUN_ALL_TIMING_ANALYSES = ON; + IGNORE_CLOCK_SETTINGS = OFF; + DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_READ_DURING_WRITE_PATHS = ON; + CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; + DO_MIN_ANALYSIS = ON; + DO_MIN_TIMING = OFF; + NUMBER_OF_PATHS_TO_REPORT = 200; + NUMBER_OF_DESTINATION_TO_REPORT = 10; + NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; + MAX_SCC_SIZE = 50; +} +HDL_SETTINGS +{ + VERILOG_INPUT_VERSION = VERILOG_2001; + ENABLE_IP_DEBUG = OFF; + VHDL_INPUT_VERSION = VHDL93; + VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; +} +PROJECT_INFO(usrp_std) +{ + ORIGINAL_QUARTUS_VERSION = 3.0; + PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; + LAST_QUARTUS_VERSION = 3.0; + SHOW_REGISTRATION_MESSAGE = ON; + USER_LIBRARIES = "e:\usrp\fpga\megacells"; +} +THIRD_PARTY_EDA_TOOLS(usrp_std) +{ + EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = ""; + EDA_SIMULATION_TOOL = ""; + EDA_TIMING_ANALYSIS_TOOL = ""; + EDA_BOARD_DESIGN_TOOL = ""; + EDA_FORMAL_VERIFICATION_TOOL = ""; + EDA_RESYNTHESIS_TOOL = ""; +} +EDA_TOOL_SETTINGS(eda_design_synthesis) +{ + EDA_INPUT_GND_NAME = GND; + EDA_INPUT_VCC_NAME = VCC; + EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_INPUT_DATA_FORMAT = EDIF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_simulation) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_timing_analysis) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + EDA_LAUNCH_CMD_LINE_TOOL = OFF; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_board_design) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_formal_verification) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + RESYNTHESIS_RETIMING = FULL; +} +EDA_TOOL_SETTINGS(eda_palace) +{ + EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; + EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; + EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; + EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; + EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; + EDA_FLATTEN_BUSES = OFF; + EDA_MAP_ILLEGAL_CHARACTERS = OFF; + EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; + EDA_RUN_TOOL_AUTOMATICALLY = OFF; + EDA_OUTPUT_DATA_FORMAT = NONE; + RESYNTHESIS_RETIMING = FULL; + RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; + RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; + USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; +} +CLOCK(clk_120mhz) +{ + FMAX_REQUIREMENT = "120.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(usbclk) +{ + FMAX_REQUIREMENT = "48.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(SCLK) +{ + FMAX_REQUIREMENT = "1.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk0) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} +CLOCK(adclk1) +{ + FMAX_REQUIREMENT = "60.0 MHz"; + INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; + DUTY_CYCLE = 50; + DIVIDE_BASE_CLOCK_PERIOD_BY = 1; + MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; + INVERT_BASE_CLOCK = OFF; +} diff --git a/usrp1/toplevel/usrp_std/usrp_std.qpf b/usrp1/toplevel/usrp_std/usrp_std.qpf new file mode 100644 index 000000000..e8b27505c --- /dev/null +++ b/usrp1/toplevel/usrp_std/usrp_std.qpf @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2004 Altera Corporation +# Any megafunction design, and related netlist (encrypted or decrypted), +# support information, device programming or simulation file, and any other +# associated documentation or information provided by Altera or a partner +# under Altera's Megafunction Partnership Program may be used only +# to program PLD devices (but not masked PLD devices) from Altera. Any +# other use of such megafunction design, netlist, support information, +# device programming or simulation file, or any other related documentation +# or information is prohibited for any other purpose, including, but not +# limited to modification, reverse engineering, de-compiling, or use with +# any other silicon devices, unless such use is explicitly licensed under +# a separate agreement with Altera or a megafunction partner. Title to the +# intellectual property, including patents, copyrights, trademarks, trade +# secrets, or maskworks, embodied in any such megafunction design, netlist, +# support information, device programming or simulation file, or any other +# related documentation or information provided by Altera or a megafunction +# partner, remains with Altera, the megafunction partner, or their respective +# licensors. No other licenses, including any licenses needed under any third +# party's intellectual property, are provided herein. + + + +QUARTUS_VERSION = "4.0" +DATE = "17:10:11 December 20, 2004" + + +# Active Revisions + +PROJECT_REVISION = "usrp_std" diff --git a/usrp1/toplevel/usrp_std/usrp_std.qsf b/usrp1/toplevel/usrp_std/usrp_std.qsf new file mode 100644 index 000000000..e0bac4893 --- /dev/null +++ b/usrp1/toplevel/usrp_std/usrp_std.qsf @@ -0,0 +1,409 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# usrp_std_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" +set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1" + +# Pin & Location Assignments +# ========================== +set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" +set_location_assignment PIN_29 -to SCLK +set_location_assignment PIN_117 -to SDI +set_location_assignment PIN_28 -to usbclk +set_location_assignment PIN_107 -to usbctl[0] +set_location_assignment PIN_106 -to usbctl[1] +set_location_assignment PIN_105 -to usbctl[2] +set_location_assignment PIN_100 -to usbdata[0] +set_location_assignment PIN_84 -to usbdata[10] +set_location_assignment PIN_83 -to usbdata[11] +set_location_assignment PIN_82 -to usbdata[12] +set_location_assignment PIN_79 -to usbdata[13] +set_location_assignment PIN_78 -to usbdata[14] +set_location_assignment PIN_77 -to usbdata[15] +set_location_assignment PIN_99 -to usbdata[1] +set_location_assignment PIN_98 -to usbdata[2] +set_location_assignment PIN_95 -to usbdata[3] +set_location_assignment PIN_94 -to usbdata[4] +set_location_assignment PIN_93 -to usbdata[5] +set_location_assignment PIN_88 -to usbdata[6] +set_location_assignment PIN_87 -to usbdata[7] +set_location_assignment PIN_86 -to usbdata[8] +set_location_assignment PIN_85 -to usbdata[9] +set_location_assignment PIN_104 -to usbrdy[0] +set_location_assignment PIN_101 -to usbrdy[1] +set_location_assignment PIN_76 -to FX2_1 +set_location_assignment PIN_75 -to FX2_2 +set_location_assignment PIN_74 -to FX2_3 +set_location_assignment PIN_116 -to io_rx_a[0] +set_location_assignment PIN_115 -to io_rx_a[1] +set_location_assignment PIN_114 -to io_rx_a[2] +set_location_assignment PIN_113 -to io_rx_a[3] +set_location_assignment PIN_108 -to io_rx_a[4] +set_location_assignment PIN_195 -to io_rx_a[5] +set_location_assignment PIN_196 -to io_rx_a[6] +set_location_assignment PIN_197 -to io_rx_a[7] +set_location_assignment PIN_200 -to io_rx_a[8] +set_location_assignment PIN_201 -to io_rx_a[9] +set_location_assignment PIN_202 -to io_rx_a[10] +set_location_assignment PIN_203 -to io_rx_a[11] +set_location_assignment PIN_206 -to io_rx_a[12] +set_location_assignment PIN_207 -to io_rx_a[13] +set_location_assignment PIN_208 -to io_rx_a[14] +set_location_assignment PIN_214 -to io_rx_b[0] +set_location_assignment PIN_215 -to io_rx_b[1] +set_location_assignment PIN_216 -to io_rx_b[2] +set_location_assignment PIN_217 -to io_rx_b[3] +set_location_assignment PIN_218 -to io_rx_b[4] +set_location_assignment PIN_219 -to io_rx_b[5] +set_location_assignment PIN_222 -to io_rx_b[6] +set_location_assignment PIN_223 -to io_rx_b[7] +set_location_assignment PIN_224 -to io_rx_b[8] +set_location_assignment PIN_225 -to io_rx_b[9] +set_location_assignment PIN_226 -to io_rx_b[10] +set_location_assignment PIN_227 -to io_rx_b[11] +set_location_assignment PIN_228 -to io_rx_b[12] +set_location_assignment PIN_233 -to io_rx_b[13] +set_location_assignment PIN_234 -to io_rx_b[14] +set_location_assignment PIN_175 -to io_tx_a[0] +set_location_assignment PIN_176 -to io_tx_a[1] +set_location_assignment PIN_177 -to io_tx_a[2] +set_location_assignment PIN_178 -to io_tx_a[3] +set_location_assignment PIN_179 -to io_tx_a[4] +set_location_assignment PIN_180 -to io_tx_a[5] +set_location_assignment PIN_181 -to io_tx_a[6] +set_location_assignment PIN_182 -to io_tx_a[7] +set_location_assignment PIN_183 -to io_tx_a[8] +set_location_assignment PIN_184 -to io_tx_a[9] +set_location_assignment PIN_185 -to io_tx_a[10] +set_location_assignment PIN_186 -to io_tx_a[11] +set_location_assignment PIN_187 -to io_tx_a[12] +set_location_assignment PIN_188 -to io_tx_a[13] +set_location_assignment PIN_193 -to io_tx_a[14] +set_location_assignment PIN_73 -to io_tx_b[0] +set_location_assignment PIN_68 -to io_tx_b[1] +set_location_assignment PIN_67 -to io_tx_b[2] +set_location_assignment PIN_66 -to io_tx_b[3] +set_location_assignment PIN_65 -to io_tx_b[4] +set_location_assignment PIN_64 -to io_tx_b[5] +set_location_assignment PIN_63 -to io_tx_b[6] +set_location_assignment PIN_62 -to io_tx_b[7] +set_location_assignment PIN_61 -to io_tx_b[8] +set_location_assignment PIN_60 -to io_tx_b[9] +set_location_assignment PIN_59 -to io_tx_b[10] +set_location_assignment PIN_58 -to io_tx_b[11] +set_location_assignment PIN_57 -to io_tx_b[12] +set_location_assignment PIN_56 -to io_tx_b[13] +set_location_assignment PIN_55 -to io_tx_b[14] +set_location_assignment PIN_152 -to master_clk +set_location_assignment PIN_144 -to rx_a_a[0] +set_location_assignment PIN_143 -to rx_a_a[1] +set_location_assignment PIN_141 -to rx_a_a[2] +set_location_assignment PIN_140 -to rx_a_a[3] +set_location_assignment PIN_139 -to rx_a_a[4] +set_location_assignment PIN_138 -to rx_a_a[5] +set_location_assignment PIN_137 -to rx_a_a[6] +set_location_assignment PIN_136 -to rx_a_a[7] +set_location_assignment PIN_135 -to rx_a_a[8] +set_location_assignment PIN_134 -to rx_a_a[9] +set_location_assignment PIN_133 -to rx_a_a[10] +set_location_assignment PIN_132 -to rx_a_a[11] +set_location_assignment PIN_23 -to rx_a_b[0] +set_location_assignment PIN_21 -to rx_a_b[1] +set_location_assignment PIN_20 -to rx_a_b[2] +set_location_assignment PIN_19 -to rx_a_b[3] +set_location_assignment PIN_18 -to rx_a_b[4] +set_location_assignment PIN_17 -to rx_a_b[5] +set_location_assignment PIN_16 -to rx_a_b[6] +set_location_assignment PIN_15 -to rx_a_b[7] +set_location_assignment PIN_14 -to rx_a_b[8] +set_location_assignment PIN_13 -to rx_a_b[9] +set_location_assignment PIN_12 -to rx_a_b[10] +set_location_assignment PIN_11 -to rx_a_b[11] +set_location_assignment PIN_131 -to rx_b_a[0] +set_location_assignment PIN_128 -to rx_b_a[1] +set_location_assignment PIN_127 -to rx_b_a[2] +set_location_assignment PIN_126 -to rx_b_a[3] +set_location_assignment PIN_125 -to rx_b_a[4] +set_location_assignment PIN_124 -to rx_b_a[5] +set_location_assignment PIN_123 -to rx_b_a[6] +set_location_assignment PIN_122 -to rx_b_a[7] +set_location_assignment PIN_121 -to rx_b_a[8] +set_location_assignment PIN_120 -to rx_b_a[9] +set_location_assignment PIN_119 -to rx_b_a[10] +set_location_assignment PIN_118 -to rx_b_a[11] +set_location_assignment PIN_8 -to rx_b_b[0] +set_location_assignment PIN_7 -to rx_b_b[1] +set_location_assignment PIN_6 -to rx_b_b[2] +set_location_assignment PIN_5 -to rx_b_b[3] +set_location_assignment PIN_4 -to rx_b_b[4] +set_location_assignment PIN_3 -to rx_b_b[5] +set_location_assignment PIN_2 -to rx_b_b[6] +set_location_assignment PIN_240 -to rx_b_b[7] +set_location_assignment PIN_239 -to rx_b_b[8] +set_location_assignment PIN_238 -to rx_b_b[9] +set_location_assignment PIN_237 -to rx_b_b[10] +set_location_assignment PIN_236 -to rx_b_b[11] +set_location_assignment PIN_156 -to SDO +set_location_assignment PIN_153 -to SEN_FPGA +set_location_assignment PIN_159 -to tx_a[0] +set_location_assignment PIN_160 -to tx_a[1] +set_location_assignment PIN_161 -to tx_a[2] +set_location_assignment PIN_162 -to tx_a[3] +set_location_assignment PIN_163 -to tx_a[4] +set_location_assignment PIN_164 -to tx_a[5] +set_location_assignment PIN_165 -to tx_a[6] +set_location_assignment PIN_166 -to tx_a[7] +set_location_assignment PIN_167 -to tx_a[8] +set_location_assignment PIN_168 -to tx_a[9] +set_location_assignment PIN_169 -to tx_a[10] +set_location_assignment PIN_170 -to tx_a[11] +set_location_assignment PIN_173 -to tx_a[12] +set_location_assignment PIN_174 -to tx_a[13] +set_location_assignment PIN_38 -to tx_b[0] +set_location_assignment PIN_39 -to tx_b[1] +set_location_assignment PIN_41 -to tx_b[2] +set_location_assignment PIN_42 -to tx_b[3] +set_location_assignment PIN_43 -to tx_b[4] +set_location_assignment PIN_44 -to tx_b[5] +set_location_assignment PIN_45 -to tx_b[6] +set_location_assignment PIN_46 -to tx_b[7] +set_location_assignment PIN_47 -to tx_b[8] +set_location_assignment PIN_48 -to tx_b[9] +set_location_assignment PIN_49 -to tx_b[10] +set_location_assignment PIN_50 -to tx_b[11] +set_location_assignment PIN_53 -to tx_b[12] +set_location_assignment PIN_54 -to tx_b[13] +set_location_assignment PIN_158 -to TXSYNC_A +set_location_assignment PIN_37 -to TXSYNC_B +set_location_assignment PIN_235 -to io_rx_b[15] +set_location_assignment PIN_24 -to io_tx_b[15] +set_location_assignment PIN_213 -to io_rx_a[15] +set_location_assignment PIN_194 -to io_tx_a[15] +set_location_assignment PIN_1 -to MYSTERY_SIGNAL + +# Timing Assignments +# ================== +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name TOP_LEVEL_ENTITY usrp_std +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" +set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name INC_PLC_MODE OFF +set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF +set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + +# Timing Analysis Assignments +# =========================== +set_global_assignment -name MAX_SCC_SIZE 50 + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF + +# Simulator Assignments +# ===================== +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "1 ns" + +# Design Assistant Assignments +# ============================ +set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF +set_global_assignment -name ASSG_CAT OFF +set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF +set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF +set_global_assignment -name CLK_CAT OFF +set_global_assignment -name CLK_RULE_COMB_CLOCK OFF +set_global_assignment -name CLK_RULE_INV_CLOCK OFF +set_global_assignment -name CLK_RULE_GATING_SCHEME OFF +set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF +set_global_assignment -name CLK_RULE_MIX_EDGES OFF +set_global_assignment -name RESET_CAT OFF +set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF +set_global_assignment -name TIMING_CAT OFF +set_global_assignment -name TIMING_RULE_SHIFT_REG OFF +set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF +set_global_assignment -name NONSYNCHSTRUCT_CAT OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF +set_global_assignment -name SIGNALRACE_CAT OFF +set_global_assignment -name ACLK_CAT OFF +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF +set_global_assignment -name HCPY_CAT OFF +set_global_assignment -name HCPY_VREF_PINS OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name HUB_ENTITY_NAME SLD_HUB +set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST +set_global_assignment -name ENABLE_SIGNALTAP OFF + +# LogicLock Region Assignments +# ============================ +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF + +# ----------------- +# start CLOCK(SCLK) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK +set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK + +# end CLOCK(SCLK) +# --------------- + +# ----------------------- +# start CLOCK(master_clk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk +set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk + +# end CLOCK(master_clk) +# --------------------- + +# ------------------- +# start CLOCK(usbclk) + + # Timing Assignments + # ================== +set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk +set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk +set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk + +# end CLOCK(usbclk) +# ----------------- + +# ---------------------- +# start ENTITY(usrp_std) + + # Timing Assignments + # ================== +set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK +set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk +set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk + +# end ENTITY(usrp_std) +# -------------------- + +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v +set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v +set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v +set_global_assignment -name VERILOG_FILE usrp_std.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file diff --git a/usrp1/toplevel/usrp_std/usrp_std.v b/usrp1/toplevel/usrp_std/usrp_std.v new file mode 100644 index 000000000..8b29a9c21 --- /dev/null +++ b/usrp1/toplevel/usrp_std/usrp_std.v @@ -0,0 +1,333 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003,2004 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Top level module for a full setup with DUCs and DDCs + +// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins +// for debugging info. NB, This can kill the m'board and/or d'board if you +// have anything except basic d'boards installed. + +// Uncomment the following to include optional circuitry + +`include "config.vh" +`include "../../../firmware/include/fpga_regs_common.v" +`include "../../../firmware/include/fpga_regs_standard.v" + +module usrp_std +(output MYSTERY_SIGNAL, + input master_clk, + input SCLK, + input SDI, + inout SDO, + input SEN_FPGA, + + input FX2_1, + output FX2_2, + output FX2_3, + + input wire [11:0] rx_a_a, + input wire [11:0] rx_b_a, + input wire [11:0] rx_a_b, + input wire [11:0] rx_b_b, + + output wire [13:0] tx_a, + output wire [13:0] tx_b, + + output wire TXSYNC_A, + output wire TXSYNC_B, + + // USB interface + input usbclk, + input wire [2:0] usbctl, + output wire [1:0] usbrdy, + inout [15:0] usbdata, // NB Careful, inout + + // These are the general purpose i/o's that go to the daughterboard slots + inout wire [15:0] io_tx_a, + inout wire [15:0] io_tx_b, + inout wire [15:0] io_rx_a, + inout wire [15:0] io_rx_b + ); + wire [15:0] debugdata,debugctrl; + assign MYSTERY_SIGNAL = 1'b0; + + wire clk64,clk128; + + wire WR = usbctl[0]; + wire RD = usbctl[1]; + wire OE = usbctl[2]; + + wire have_space, have_pkt_rdy; + assign usbrdy[0] = have_space; + assign usbrdy[1] = have_pkt_rdy; + + wire tx_underrun, rx_overrun; + wire clear_status = FX2_1; + assign FX2_2 = rx_overrun; + assign FX2_3 = tx_underrun; + + wire [15:0] usbdata_out; + + wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; + + wire tx_realsignals; + wire [3:0] rx_numchan; + wire [2:0] tx_numchan; + + wire [7:0] interp_rate, decim_rate; + wire [31:0] tx_debugbus, rx_debugbus; + + wire enable_tx, enable_rx; + wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; + wire [7:0] settings; + + // Tri-state bus macro + bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); + + assign clk64 = master_clk; + + wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; + wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; + + // TX + wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; + wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; + + wire strobe_interp, tx_sample_strobe; + wire tx_empty; + + wire serial_strobe; + wire [6:0] serial_addr; + wire [31:0] serial_data; + + reg [15:0] debug_counter; + reg [15:0] loopback_i_0,loopback_q_0; + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Transmit Side +`ifdef TX_ON + assign bb_tx_i0 = ch0tx; + assign bb_tx_q0 = ch1tx; + assign bb_tx_i1 = ch2tx; + assign bb_tx_q1 = ch3tx; + + tx_buffer tx_buffer + ( .usbclk(usbclk), .bus_reset(tx_bus_reset), + .usbdata(usbdata),.WR(WR), .have_space(have_space), + .tx_underrun(tx_underrun), .clear_status(clear_status), + .txclk(clk64), .reset(tx_dsp_reset), + .channels({tx_numchan,1'b0}), + .tx_i_0(ch0tx),.tx_q_0(ch1tx), + .tx_i_1(ch2tx),.tx_q_1(ch3tx), + .txstrobe(strobe_interp), + .tx_empty(tx_empty), + .debugbus(tx_debugbus) ); + + `ifdef TX_EN_0 + tx_chain tx_chain_0 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); + `else + assign i_out_0=16'd0; + assign q_out_0=16'd0; + `endif + + `ifdef TX_EN_1 + tx_chain tx_chain_1 + ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), + .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), + .interpolator_strobe(strobe_interp),.freq(), + .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); + `else + assign i_out_1=16'd0; + assign q_out_1=16'd0; + `endif + + setting_reg #(`FR_TX_MUX) + sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), + .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); + + wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; + wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; + + wire txsync = tx_sample_strobe; + assign TXSYNC_A = txsync; + assign TXSYNC_B = txsync; + + assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; + assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; +`endif // `ifdef TX_ON + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Receive Side +`ifdef RX_ON + wire rx_sample_strobe,strobe_decim,hb_strobe; + wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, + bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; + + wire loopback = settings[0]; + wire counter = settings[1]; + + always @(posedge clk64) + if(rx_dsp_reset) + debug_counter <= #1 16'd0; + else if(~enable_rx) + debug_counter <= #1 16'd0; + else if(hb_strobe) + debug_counter <=#1 debug_counter + 16'd2; + + always @(posedge clk64) + if(strobe_interp) + begin + loopback_i_0 <= #1 ch0tx; + loopback_q_0 <= #1 ch1tx; + end + + assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; + assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; + assign ch2rx = bb_rx_i1; + assign ch3rx = bb_rx_q1; + assign ch4rx = bb_rx_i2; + assign ch5rx = bb_rx_q2; + assign ch6rx = bb_rx_i3; + assign ch7rx = bb_rx_q3; + + wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; + wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; + + adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), + .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3), + .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), + .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), + .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), + .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); + + rx_buffer rx_buffer + ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), + .reset_regs(rx_dsp_reset), + .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), + .channels(rx_numchan), + .ch_0(ch0rx),.ch_1(ch1rx), + .ch_2(ch2rx),.ch_3(ch3rx), + .ch_4(ch4rx),.ch_5(ch5rx), + .ch_6(ch6rx),.ch_7(ch7rx), + .rxclk(clk64),.rxstrobe(hb_strobe), + .clear_status(clear_status), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .debugbus(rx_debugbus) ); + + `ifdef RX_EN_0 + rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); + `else + assign bb_rx_i0=16'd0; + assign bb_rx_q0=16'd0; + `endif + + `ifdef RX_EN_1 + rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); + `else + assign bb_rx_i1=16'd0; + assign bb_rx_q1=16'd0; + `endif + + `ifdef RX_EN_2 + rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); + `else + assign bb_rx_i2=16'd0; + assign bb_rx_q2=16'd0; + `endif + + `ifdef RX_EN_3 + rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 + ( .clock(clk64),.reset(1'b0),.enable(enable_rx), + .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); + `else + assign bb_rx_i3=16'd0; + assign bb_rx_q3=16'd0; + `endif + +`endif // `ifdef RX_ON + + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Control Functions + + wire [31:0] capabilities; + assign capabilities[7] = `TX_CAP_HB; + assign capabilities[6:4] = `TX_CAP_NCHAN; + assign capabilities[3] = `RX_CAP_HB; + assign capabilities[2:0] = `RX_CAP_NCHAN; + + + serial_io serial_io + ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), + .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), + .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) + ); + + wire [15:0] reg_0,reg_1,reg_2,reg_3; + master_control master_control + ( .master_clk(clk64),.usbclk(usbclk), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), + .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), + .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), + .enable_tx(enable_tx),.enable_rx(enable_rx), + .interp_rate(interp_rate),.decim_rate(decim_rate), + .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), + .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), + .tx_empty(tx_empty), + //.debug_0(rx_a_a),.debug_1(ddc0_in_i), + .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]), + .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); + + io_pins io_pins + (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), + .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), + .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Misc Settings + setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); + +endmodule // usrp_std -- cgit v1.2.3 From 7bf8a6df381a667134b55701993c6770d32bc76b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Jan 2010 11:56:55 -0800 Subject: Moved usrp2 fpga files into usrp2 subdir. --- boot_cpld/.gitignore | 38 - boot_cpld/_impact.cmd | 34 - boot_cpld/boot_cpld.ipf | Bin 2967 -> 0 bytes boot_cpld/boot_cpld.ise | Bin 227573 -> 0 bytes boot_cpld/boot_cpld.lfp | 5 - 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usrp2/top/u2_rev3_iad/dsp_core_rx.v create mode 100644 usrp2/top/u2_rev3_iad/dsp_core_tb.sav create mode 100644 usrp2/top/u2_rev3_iad/dsp_core_tb.v create mode 100644 usrp2/top/u2_rev3_iad/impulse.v create mode 100755 usrp2/top/u2_rev3_iad/wave.sh create mode 100755 usrp2/top/u2plus/u2plus.ucf create mode 100644 usrp2/top/u2plus/u2plus.v diff --git a/boot_cpld/.gitignore b/boot_cpld/.gitignore deleted file mode 100644 index 45cf9a86b..000000000 --- a/boot_cpld/.gitignore +++ /dev/null @@ -1,38 +0,0 @@ -/*_xdb -/*.restore -/*.xrpt -/*.zip -/xst -/_ngo -/_xmsgs -/*.log -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.ipf_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*.cel -/_pace.ucf -/*.lock -/*.tfi -/templates diff --git a/boot_cpld/_impact.cmd b/boot_cpld/_impact.cmd deleted file mode 100755 index 4af86cb02..000000000 --- a/boot_cpld/_impact.cmd +++ /dev/null @@ -1,34 +0,0 @@ -loadProjectFile -file "C:\cygwin\home\matt\usrp2\fpga\boot_cpld/boot_cpld.ipf" -setMode -ss -setMode -sm -setMode -hw140 -setMode -spi -setMode -acecf -setMode -acempm -setMode -pff -setMode -bs -setMode -bs -setMode -bs -setMode -bs -setCable -port auto -Identify -identifyMPM -assignFile -p 1 -file "C:/cygwin/home/matt/usrp2/fpga/boot_cpld/boot_cpld.jed" -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Program -p 1 -e -v -defaultVersion 0 -Identify -identifyMPM -Identify -identifyMPM -Identify -identifyMPM -Identify -identifyMPM -Identify -identifyMPM -setMode -bs -deleteDevice -position 1 diff --git a/boot_cpld/boot_cpld.ipf b/boot_cpld/boot_cpld.ipf deleted file mode 100755 index 8acb6821e..000000000 Binary files a/boot_cpld/boot_cpld.ipf and /dev/null differ diff --git a/boot_cpld/boot_cpld.ise b/boot_cpld/boot_cpld.ise deleted file mode 100755 index 7252d3768..000000000 Binary files a/boot_cpld/boot_cpld.ise and /dev/null differ diff --git a/boot_cpld/boot_cpld.lfp b/boot_cpld/boot_cpld.lfp deleted file mode 100755 index 0f0c8f2e2..000000000 --- a/boot_cpld/boot_cpld.lfp +++ /dev/null @@ -1,5 +0,0 @@ -# begin LFP file C:\cygwin\home\matt\u2f\boot_cpld\boot_cpld.lfp -designfile boot_cpld.v -parttype xc9572xl-vq44-10 -bus_delimiter 0; -set_busdelim_onsave 1; diff --git a/boot_cpld/boot_cpld.ucf b/boot_cpld/boot_cpld.ucf deleted file mode 100755 index 789bb1d96..000000000 --- a/boot_cpld/boot_cpld.ucf +++ /dev/null @@ -1,34 +0,0 @@ -NET "CLK_25MHZ" LOC = "P5" ; -NET "CLK_25MHZ_EN" LOC = "P6" ; -NET "LED<0>" LOC = "P12" ; -NET "LED<1>" LOC = "P8" ; -NET "LED<2>" LOC = "P7" ; -NET "DEBUG<0>" LOC = "P1" ; -NET "DEBUG<1>" LOC = "P2" ; -NET "DEBUG<2>" LOC = "P3" ; -NET "DEBUG<3>" LOC = "P29" ; -NET "DEBUG<4>" LOC = "P30" ; -NET "DEBUG<5>" LOC = "P31" ; -NET "DEBUG<6>" LOC = "P32" ; -NET "DEBUG<7>" LOC = "P33" ; -NET "DEBUG<8>" LOC = "P34" ; -NET "POR" LOC = "P42" ; -NET "SD_nCS" LOC = "P20" ; -NET "SD_Din" LOC = "P21" ; -NET "SD_CLK" LOC = "P22" ; -NET "SD_Dout" LOC = "P23" ; -NET "SD_DAT1" LOC = "P27" ; -NET "SD_DAT2" LOC = "P28" ; -NET "SD_prot" LOC = "P19" ; -NET "SD_det" LOC = "P36" ; -NET "CFG_INIT_B" LOC = "P38" ; -NET "CFG_Din" LOC = "P37" ; -NET "CFG_CCLK" LOC = "P41" ; -NET "CFG_DONE" LOC = "P40" ; -NET "CFG_PROG_B" LOC = "P39" ; -NET "CPLD_CLK" LOC = "P13" ; -NET "START" LOC = "P14" ; -NET "MODE" LOC = "P18" ; -NET "DONE" LOC = "P16" ; -NET "detached" LOC = "P43" ; -NET "CPLD_misc" LOC = "P44" ; diff --git a/boot_cpld/boot_cpld.v b/boot_cpld/boot_cpld.v deleted file mode 100755 index 2ffc6daed..000000000 --- a/boot_cpld/boot_cpld.v +++ /dev/null @@ -1,95 +0,0 @@ -`timescale 1ns / 1ps -// //////////////////////////////////////////////////////////////////////////////// -// Boot CPLD design, only for u2_rev2 -// //////////////////////////////////////////////////////////////////////////////// - -module boot_cpld - (input CLK_25MHZ, - output CLK_25MHZ_EN, - output [2:0] LED, - output [8:0] DEBUG, - input POR, - - // To SD Card - output SD_nCS, - output SD_Din, - output SD_CLK, - input SD_Dout, - input SD_DAT1, // Unused - input SD_DAT2, // Unused - input SD_prot, // Write Protect - input SD_det, // Card Detect - - // To FPGA Config Interface - input CFG_INIT_B, - output CFG_Din, // Also used in Data interface - output CFG_CCLK, - input CFG_DONE, - output CFG_PROG_B, - - // To FPGA data interface - output CPLD_CLK, - input START, - input MODE, - input DONE, - output detached, - input CPLD_misc // Unused for now - ); - - assign CLK_25MHZ_EN = 1'b1; - - assign LED[0] = ~CFG_DONE; - assign LED[1] = CFG_INIT_B; - assign LED[2] = ~CFG_PROG_B; - - wire en_outs; - wire [3:0] set_sel = 4'd0; - - assign CPLD_CLK = CFG_CCLK; - assign DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, - START, MODE, DONE, CPLD_misc}; - - // Handle cutover to FPGA control of SD - wire fpga_takeover = ~CPLD_misc; - wire SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int; - - assign SD_CLK = fpga_takeover ? START : SD_CLK_int; - assign SD_nCS = fpga_takeover ? MODE : SD_nCS_int; - assign SD_Din = fpga_takeover ? DONE : SD_Din_int; - assign CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int; - - spi_boot #(.width_set_sel_g(4), // How many sets (16) - .width_bit_cnt_g(6), // Block length (12 is faster, 6 is minimum) - .width_img_cnt_g(2), // How many images per set - .num_bits_per_img_g(20), // Image size, 20 = 1MB - .sd_init_g(1), // SD-specific initialization - .mmc_compat_clk_div_g(0),// No MMC support - .width_mmc_clk_div_g(0), // No MMC support - .reset_level_g(0)) // Active low reset - - spi_boot(.clk_i(CLK_25MHZ), - .reset_i(POR), - - // To SD Card - .spi_clk_o(SD_CLK_int), - .spi_cs_n_o(SD_nCS_int), - .spi_data_in_i(SD_Dout), - .spi_data_out_o(SD_Din_int), - .spi_en_outs_o(en_outs), - - // Data Port - .start_i(START), - .mode_i(MODE), // 0->conf mode, 1->data mode - .detached_o(detached), - .dat_done_i(DONE), - .set_sel_i(set_sel), - - // To FPGA - .config_n_o(CFG_PROG_B), - .cfg_init_n_i(CFG_INIT_B), - .cfg_done_i(CFG_DONE), - .cfg_clk_o(CFG_CCLK), - .cfg_dat_o(CFG_Din_int) - ); - -endmodule // boot_cpld diff --git a/control_lib/.gitignore b/control_lib/.gitignore deleted file mode 100644 index 025385cff..000000000 --- a/control_lib/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -/a.out -/*.vcd -/*.lxt -/*.sav -/*.log diff --git a/control_lib/CRC16_D16.v b/control_lib/CRC16_D16.v deleted file mode 100644 index 7e2816af1..000000000 --- a/control_lib/CRC16_D16.v +++ /dev/null @@ -1,89 +0,0 @@ -/////////////////////////////////////////////////////////////////////// -// File: CRC16_D16.v -// Date: Sun Jun 17 06:42:55 2007 -// -// Copyright (C) 1999-2003 Easics NV. -// This source file may be used and distributed without restriction -// provided that this copyright statement is not removed from the file -// and that any derivative work contains the original copyright notice -// and the associated disclaimer. -// -// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS -// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -// Purpose: Verilog module containing a synthesizable CRC function -// * polynomial: (0 5 12 16) -// * data width: 16 -// -// Info: tools@easics.be -// http://www.easics.com -/////////////////////////////////////////////////////////////////////// - - -module CRC16_D16 - (input [15:0] Data, - input [15:0] CRC, - output [15:0] NewCRC); - - assign NewCRC = nextCRC16_D16(Data,CRC); - - // polynomial: (0 5 12 16) - // data width: 16 - // convention: the first serial data bit is D[15] - function [15:0] nextCRC16_D16; - - input [15:0] Data; - input [15:0] CRC; - - reg [15:0] D; - reg [15:0] C; - reg [15:0] NewCRC; - - begin - - D = Data; - C = CRC; - - NewCRC[0] = D[12] ^ D[11] ^ D[8] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ - C[8] ^ C[11] ^ C[12]; - NewCRC[1] = D[13] ^ D[12] ^ D[9] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ - C[9] ^ C[12] ^ C[13]; - NewCRC[2] = D[14] ^ D[13] ^ D[10] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ - C[10] ^ C[13] ^ C[14]; - NewCRC[3] = D[15] ^ D[14] ^ D[11] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ - C[11] ^ C[14] ^ C[15]; - NewCRC[4] = D[15] ^ D[12] ^ D[8] ^ D[4] ^ C[4] ^ C[8] ^ C[12] ^ - C[15]; - NewCRC[5] = D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ D[4] ^ - D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ - C[13]; - NewCRC[6] = D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[5] ^ - D[1] ^ C[1] ^ C[5] ^ C[6] ^ C[9] ^ C[10] ^ C[12] ^ - C[13] ^ C[14]; - NewCRC[7] = D[15] ^ D[14] ^ D[13] ^ D[11] ^ D[10] ^ D[7] ^ D[6] ^ - D[2] ^ C[2] ^ C[6] ^ C[7] ^ C[10] ^ C[11] ^ C[13] ^ - C[14] ^ C[15]; - NewCRC[8] = D[15] ^ D[14] ^ D[12] ^ D[11] ^ D[8] ^ D[7] ^ D[3] ^ - C[3] ^ C[7] ^ C[8] ^ C[11] ^ C[12] ^ C[14] ^ C[15]; - NewCRC[9] = D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[8] ^ D[4] ^ C[4] ^ - C[8] ^ C[9] ^ C[12] ^ C[13] ^ C[15]; - NewCRC[10] = D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[5] ^ C[5] ^ C[9] ^ - C[10] ^ C[13] ^ C[14]; - NewCRC[11] = D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[6] ^ C[6] ^ C[10] ^ - C[11] ^ C[14] ^ C[15]; - NewCRC[12] = D[15] ^ D[8] ^ D[7] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ C[7] ^ - C[8] ^ C[15]; - NewCRC[13] = D[9] ^ D[8] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ C[8] ^ C[9]; - NewCRC[14] = D[10] ^ D[9] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ C[9] ^ C[10]; - NewCRC[15] = D[11] ^ D[10] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ C[10] ^ - C[11]; - - nextCRC16_D16 = NewCRC; - - end - - endfunction - -endmodule - diff --git a/control_lib/SYSCTRL.sav b/control_lib/SYSCTRL.sav deleted file mode 100644 index 43bfef10e..000000000 --- a/control_lib/SYSCTRL.sav +++ /dev/null @@ -1,24 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -system_control_tb.aux_clk -@29 -system_control_tb.clk_fpga -@28 -system_control_tb.dsp_clk -system_control_tb.dsp_rst -system_control_tb.proc_rst -system_control_tb.rl_done -system_control_tb.rl_rst -system_control_tb.wb_clk -system_control_tb.wb_rst -system_control_tb.system_control.POR -@22 -system_control_tb.system_control.POR_ctr[3:0] -@28 -system_control_tb.clock_ready -system_control_tb.system_control.half_clk -system_control_tb.system_control.fin_ret_half -system_control_tb.system_control.fin_ret_aux -system_control_tb.system_control.gate_dsp_clk diff --git a/control_lib/WB_SIM.sav b/control_lib/WB_SIM.sav deleted file mode 100644 index 467cd35ef..000000000 --- a/control_lib/WB_SIM.sav +++ /dev/null @@ -1,47 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -wb_sim.wb_rst -wb_sim.wb_clk -@23 -wb_sim.rom_data[47:0] -@22 -wb_sim.rom_addr[15:0] -@28 -wb_sim.start -wb_sim.wb_ack -@22 -wb_sim.wb_adr[15:0] -@28 -wb_sim.wb_cyc -@22 -wb_sim.wb_dat[31:0] -wb_sim.wb_sel[3:0] -@28 -wb_sim.wb_stb -wb_sim.wb_we -@22 -wb_sim.port_output[31:0] -@28 -wb_sim.system_control.POR -wb_sim.system_control.aux_clk -wb_sim.system_control.clk_fpga -@29 -wb_sim.system_control.done -@28 -wb_sim.system_control.dsp_clk -wb_sim.system_control.fin_del1 -wb_sim.system_control.fin_del2 -wb_sim.system_control.fin_del3 -wb_sim.system_control.fin_ret_aux -@29 -wb_sim.system_control.fin_ret_fpga -@28 -wb_sim.system_control.finished -wb_sim.system_control.reset_out -wb_sim.system_control.start -wb_sim.system_control.started -wb_sim.system_control.wb_clk_o -wb_sim.system_control.wb_rst_o -wb_sim.system_control.wb_rst_o_alt diff --git a/control_lib/atr_controller.v b/control_lib/atr_controller.v deleted file mode 100644 index fed2791f9..000000000 --- a/control_lib/atr_controller.v +++ /dev/null @@ -1,57 +0,0 @@ - -// Automatic transmit/receive switching of control pins to daughterboards -// Store everything in registers for now, but could use a RAM for more -// complex state machines in the future - -module atr_controller - (input clk_i, input rst_i, - input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input run_rx, input run_tx, input [31:0] master_time, - output [31:0] ctrl_lines); - - reg [3:0] state; - reg [31:0] atr_ram [0:15]; // DP distributed RAM - - // WB Interface - always @(posedge clk_i) - if(we_i & stb_i & cyc_i) - begin - if(sel_i[3]) - atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24]; - if(sel_i[2]) - atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16]; - if(sel_i[1]) - atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; - if(sel_i[0]) - atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; - end // if (we_i & stb_i & cyc_i) - - always @(posedge clk_i) - dat_o <= atr_ram[adr_i[5:2]]; - - always @(posedge clk_i) - ack_o <= stb_i & cyc_i & ~ack_o; - - // Control side of DP RAM - assign ctrl_lines = atr_ram[state]; - - // Put a more complex state machine with time delays and multiple states here - // if daughterboard requires more complex sequencing - localparam ATR_IDLE = 4'd0; - localparam ATR_TX = 4'd1; - localparam ATR_RX = 4'd2; - localparam ATR_FULL_DUPLEX = 4'd3; - - always @(posedge clk_i) - if(rst_i) - state <= ATR_IDLE; - else - case ({run_rx,run_tx}) - 2'b00 : state <= ATR_IDLE; - 2'b01 : state <= ATR_TX; - 2'b10 : state <= ATR_RX; - 2'b11 : state <= ATR_FULL_DUPLEX; - endcase // case({run_rx,run_tx}) - -endmodule // atr_controller diff --git a/control_lib/bin2gray.v b/control_lib/bin2gray.v deleted file mode 100644 index 513402163..000000000 --- a/control_lib/bin2gray.v +++ /dev/null @@ -1,10 +0,0 @@ - - -module bin2gray - #(parameter WIDTH=8) - (input [WIDTH-1:0] bin, - output [WIDTH-1:0] gray); - - assign gray = (bin >> 1) ^ bin; - -endmodule // bin2gray diff --git a/control_lib/bootrom.mem b/control_lib/bootrom.mem deleted file mode 100644 index d688b4342..000000000 --- a/control_lib/bootrom.mem +++ /dev/null @@ -1,26 +0,0 @@ -00000C000F03 -101400000000 - // SPI: Set Divider to div by 2 -// Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds -1018_0000_0001 // SPI: Choose AD9510 -1010_0000_3418 // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word -1000_0000_0010 // SPI: AD9510 A:0 D:10 Set up AD9510 SPI -1010_0000_3518 // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word -ffff_ffff_ffff // terminate -#// First 16 bits are address, last 32 are data -#// First 4 bits of address select which slave -// 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on -// 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels -// 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) -// 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal -// 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current -// 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On -// 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) -// 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 -// 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det -// 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... -// 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care -// 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 -// 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 - // default : addr_data = {13'h5A,8'h01}; // Register Update -// @ 55 // Jump to new address 8'h55 diff --git a/control_lib/clock_bootstrap_rom.v b/control_lib/clock_bootstrap_rom.v deleted file mode 100644 index 46563db65..000000000 --- a/control_lib/clock_bootstrap_rom.v +++ /dev/null @@ -1,34 +0,0 @@ - - -module clock_bootstrap_rom(input [15:0] addr, output [47:0] data); - - reg [47:0] rom [0:15]; - - //initial - // $readmemh("bootrom.mem", rom); - - assign data = rom[addr]; - - initial - begin - // First 16 bits are address, last 32 are data - // First 4 bits of address select which slave - rom[0] = 48'h0000_0C00_0F03; // Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds - rom[1] = 48'h1014_0000_0000; // SPI: Set Divider to div by 2 - rom[2] = 48'h1018_0000_0001; // SPI: Choose AD9510 - rom[3] = 48'h1010_0000_3418; // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word - rom[4] = 48'h1000_0000_0010; // SPI: AD9510 A:0 D:10 Set up AD9510 SPI - rom[5] = 48'h1010_0000_3518; // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word - rom[6] = 48'hffff_ffff_ffff; // terminate - rom[7] = 48'hffff_ffff_ffff; // terminate - rom[8] = 48'hffff_ffff_ffff; // terminate - rom[9] = 48'hffff_ffff_ffff; // terminate - rom[10] = 48'hffff_ffff_ffff; // terminate - rom[11] = 48'hffff_ffff_ffff; // terminate - rom[12] = 48'hffff_ffff_ffff; // terminate - rom[13] = 48'hffff_ffff_ffff; // terminate - rom[14] = 48'hffff_ffff_ffff; // terminate - rom[15] = 48'hffff_ffff_ffff; // terminate - end // initial begin - -endmodule // clock_bootstrap_rom diff --git a/control_lib/clock_control.v b/control_lib/clock_control.v deleted file mode 100644 index 1bbe6bd75..000000000 --- a/control_lib/clock_control.v +++ /dev/null @@ -1,115 +0,0 @@ - - -// AD9510 Register Map (from datasheet Rev. A) - -/* INSTRUCTION word format (16 bits) - * 15 Read = 1, Write = 0 - * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream - * 12:0 Address - */ - -/* ADDR Contents Value (hex) - * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate - * 04 A Counter - * 05-06 B Counter - * 07-0A PLL Control - * 0B-0C R Divider - * 0D PLL Control - * 34-3A Fine Delay - * 3C-3F LVPECL Outs - * 40-43 LVDS/CMOS Outs - * 45 Clock select, power down - * 48-57 Dividers - * 58 Func and Sync - * 5A Update regs - */ - - -module clock_control - (input reset, - input aux_clk, // 25MHz, for before fpga clock is active - input clk_fpga, // real 100 MHz FPGA clock - output [1:0] clk_en, // controls source of reference clock - output [1:0] clk_sel, // controls source of reference clock - input clk_func, // FIXME needs to be some kind of out SYNC or reset to 9510 - input clk_status, // Monitor PLL or SYNC status - - output sen, // Enable for the AD9510 - output sclk, // FIXME these need to be shared - input sdi, - output sdo - ); - - wire read = 1'b0; // Always write for now - wire [1:0] w = 2'b00; // Always send 1 byte at a time - - assign clk_sel = 2'b00; // Both outputs from External Ref (SMA) - assign clk_en = 2'b11; // Both outputs enabled - - reg [20:0] addr_data; - - reg [5:0] entry; - reg start; - reg [7:0] counter; - reg [23:0] command; - - always @* - case(entry) - 6'd00 : addr_data = {13'h00,8'h10}; // Serial setup - 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on - 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels - 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) - 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal - 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current - 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On - 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) - 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 - 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det - 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... - 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care - 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 - 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 - default : addr_data = {13'h5A,8'h01}; // Register Update - endcase // case(entry) - - wire [5:0] lastentry = 6'd15; - wire done = (counter == 8'd49); - - always @(posedge aux_clk) - if(reset) - begin - entry <= #1 6'd0; - start <= #1 1'b1; - end - else if(start) - start <= #1 1'b0; - else if(done && (entry - // reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1]; - - // Port 1 - always @(posedge clk) - if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]]; - - always @(posedge clk) - if(we1_i & en1_i & sel1_i[3]) - ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[2]) - ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[1]) - ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8]; - always @(posedge clk) - if(we1_i & en1_i & sel1_i[0]) - ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0]; - - // Port 2 - always @(posedge clk) - if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]]; - always @(posedge clk) - if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]]; - - always @(posedge clk) - if(we2_i & en2_i & sel2_i[3]) - ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[2]) - ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[1]) - ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8]; - always @(posedge clk) - if(we2_i & en2_i & sel2_i[0]) - ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0]; - -endmodule // dpram32 - - diff --git a/control_lib/fifo_tb.v b/control_lib/fifo_tb.v deleted file mode 100644 index 616fe4ee7..000000000 --- a/control_lib/fifo_tb.v +++ /dev/null @@ -1,151 +0,0 @@ -module fifo_tb(); - - reg clk, rst; - wire short_full, short_empty, long_full, long_empty; - wire casc2_full, casc2_empty; - reg read, write; - - wire [7:0] short_do, long_do; - wire [7:0] casc2_do; - reg [7:0] di; - - reg clear = 0; - - shortfifo #(.WIDTH(8)) shortfifo - (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear), - .read(read),.write(write),.full(short_full),.empty(short_empty)); - - longfifo #(.WIDTH(8), .SIZE(4)) longfifo - (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear), - .read(read),.write(write),.full(long_full),.empty(long_empty)); - - cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2 - (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear), - .read(read),.write(write),.full(casc2_full),.empty(casc2_empty)); - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #50 clk = ~clk; - - initial di = 8'hAE; - initial read = 0; - initial write = 0; - - always @(posedge clk) - if(write) - di <= di + 1; - - always @(posedge clk) - begin - if(short_full != long_full) - $display("Error: FULL mismatch"); - if(short_empty != long_empty) - $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)"); - if(read & (short_do != long_do)) - $display("Error: DATA mismatch"); - end - - initial $dumpfile("fifo_tb.vcd"); - initial $dumpvars(0,fifo_tb); - - initial - begin - @(negedge rst); - @(posedge clk); - repeat (10) - @(posedge clk); - write <= 1; - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - - repeat(10) - begin - write <= 1; - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end // repeat (10) - - write <= 1; - repeat (4) - @(posedge clk); - write <= 0; - @(posedge clk); - read <= 1; - repeat (4) - @(posedge clk); - read <= 0; - @(posedge clk); - - - write <= 1; - repeat (4) - @(posedge clk); - write <= 0; - @(posedge clk); - repeat (4) - begin - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - end - - write <= 1; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - repeat (5) - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - read <= 0; - @(posedge clk); - - write <= 1; - repeat (16) - @(posedge clk); - write <= 0; - @(posedge clk); - - read <= 1; - repeat (16) - @(posedge clk); - read <= 0; - @(posedge clk); - - repeat (10) - @(posedge clk); - $finish; - end -endmodule // longfifo_tb diff --git a/control_lib/gray2bin.v b/control_lib/gray2bin.v deleted file mode 100644 index 5df40bd52..000000000 --- a/control_lib/gray2bin.v +++ /dev/null @@ -1,13 +0,0 @@ - - -module gray2bin - #(parameter WIDTH=8) - (input [WIDTH-1:0] gray, - output reg [WIDTH-1:0] bin); - - integer i; - always @(gray) - for(i = 0;i>i); - -endmodule // gray2bin diff --git a/control_lib/gray_send.v b/control_lib/gray_send.v deleted file mode 100644 index 7fc07d40c..000000000 --- a/control_lib/gray_send.v +++ /dev/null @@ -1,29 +0,0 @@ - - - -module gray_send - #(parameter WIDTH = 8) - (input clk_in, input [WIDTH-1:0] addr_in, - input clk_out, output reg [WIDTH-1:0] addr_out); - - reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1; - wire [WIDTH-1:0] gray, bin; - - bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) ); - - always @(posedge clk_in) - gray_clkin <= gray; - - always @(posedge clk_out) - gray_clkout <= gray_clkin; - - always @(posedge clk_out) - gray_clkout_d1 <= gray_clkout; - - gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) ); - - // FIXME we may not need the next register, but it may help timing - always @(posedge clk_out) - addr_out <= bin; - -endmodule // gray_send diff --git a/control_lib/icache.v b/control_lib/icache.v deleted file mode 100644 index bd21f47cc..000000000 --- a/control_lib/icache.v +++ /dev/null @@ -1,135 +0,0 @@ - -module icache - #(parameter AWIDTH=14, - parameter CWIDTH=6) - - (input wb_clk_i, - input wb_rst_i, - input [AWIDTH-1:0] iwb_adr_i, - input iwb_stb_i, - output [31:0] iwb_dat_o, - output iwb_ack_o, - input [31:0] iram_dat_i, - output [AWIDTH-1:0] iram_adr_o, - output iram_en_o, - input flush); - - localparam TAGWIDTH = AWIDTH-CWIDTH-2; - reg stb_d1, ack_d1, miss_d1; - reg [AWIDTH-1:0] held_addr; - reg [31:0] idata [0:(1< clear $end -$var wire 1 ? clk $end -$var wire 36 @ datain [35:0] $end -$var wire 36 A dataout [35:0] $end -$var wire 1 $ dst_rdy_i $end -$var wire 1 ! dst_rdy_o $end -$var wire 1 B read $end -$var wire 1 C reset $end -$var wire 1 D src_rdy_i $end -$var wire 1 % src_rdy_o $end -$var wire 1 E write $end -$var reg 4 F a [3:0] $end -$var reg 1 G empty $end -$var reg 1 H full $end -$var reg 5 I occupied [4:0] $end -$var reg 5 J space [4:0] $end -$scope begin gen_srl16[0] $end -$scope module srl16e $end -$var wire 1 K A0 $end -$var wire 1 L A1 $end -$var wire 1 M A2 $end -$var wire 1 N A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 O D $end -$var wire 1 P Q $end -$var reg 16 Q data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[1] $end -$scope module srl16e $end -$var wire 1 R A0 $end -$var wire 1 S A1 $end -$var wire 1 T A2 $end -$var wire 1 U A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 V D $end -$var wire 1 W Q $end -$var reg 16 X data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[2] $end -$scope module srl16e $end -$var wire 1 Y A0 $end -$var wire 1 Z A1 $end -$var wire 1 [ A2 $end -$var wire 1 \ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ] D $end -$var wire 1 ^ Q $end -$var reg 16 _ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[3] $end -$scope module srl16e $end -$var wire 1 ` A0 $end -$var wire 1 a A1 $end -$var wire 1 b A2 $end -$var wire 1 c A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 d D $end -$var wire 1 e Q $end -$var reg 16 f data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[4] $end -$scope module srl16e $end -$var wire 1 g A0 $end -$var wire 1 h A1 $end -$var wire 1 i A2 $end -$var wire 1 j A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 k D $end -$var wire 1 l Q $end -$var reg 16 m data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[5] $end -$scope module srl16e $end -$var wire 1 n A0 $end -$var wire 1 o A1 $end -$var wire 1 p A2 $end -$var wire 1 q A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 r D $end -$var wire 1 s Q $end -$var reg 16 t data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[6] $end -$scope module srl16e $end -$var wire 1 u A0 $end -$var wire 1 v A1 $end -$var wire 1 w A2 $end -$var wire 1 x A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 y D $end -$var wire 1 z Q $end -$var reg 16 { data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[7] $end -$scope module srl16e $end -$var wire 1 | A0 $end -$var wire 1 } A1 $end -$var wire 1 ~ A2 $end -$var wire 1 !" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 "" D $end -$var wire 1 #" Q $end -$var reg 16 $" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[8] $end -$scope module srl16e $end -$var wire 1 %" A0 $end -$var wire 1 &" A1 $end -$var wire 1 '" A2 $end -$var wire 1 (" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 )" D $end -$var wire 1 *" Q $end -$var reg 16 +" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[9] $end -$scope module srl16e $end -$var wire 1 ," A0 $end -$var wire 1 -" A1 $end -$var wire 1 ." A2 $end -$var wire 1 /" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 0" D $end -$var wire 1 1" Q $end -$var reg 16 2" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[10] $end -$scope module srl16e $end -$var wire 1 3" A0 $end -$var wire 1 4" A1 $end -$var wire 1 5" A2 $end -$var wire 1 6" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 7" D $end -$var wire 1 8" Q $end -$var reg 16 9" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[11] $end -$scope module srl16e $end -$var wire 1 :" A0 $end -$var wire 1 ;" A1 $end -$var wire 1 <" A2 $end -$var wire 1 =" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 >" D $end -$var wire 1 ?" Q $end -$var reg 16 @" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[12] $end -$scope module srl16e $end -$var wire 1 A" A0 $end -$var wire 1 B" A1 $end -$var wire 1 C" A2 $end -$var wire 1 D" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 E" D $end -$var wire 1 F" Q $end -$var reg 16 G" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[13] $end -$scope module srl16e $end -$var wire 1 H" A0 $end -$var wire 1 I" A1 $end -$var wire 1 J" A2 $end -$var wire 1 K" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 L" D $end -$var wire 1 M" Q $end -$var reg 16 N" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[14] $end -$scope module srl16e $end -$var wire 1 O" A0 $end -$var wire 1 P" A1 $end -$var wire 1 Q" A2 $end -$var wire 1 R" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 S" D $end -$var wire 1 T" Q $end -$var reg 16 U" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[15] $end -$scope module srl16e $end -$var wire 1 V" A0 $end -$var wire 1 W" A1 $end -$var wire 1 X" A2 $end -$var wire 1 Y" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 Z" D $end -$var wire 1 [" Q $end -$var reg 16 \" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[16] $end -$scope module srl16e $end -$var wire 1 ]" A0 $end -$var wire 1 ^" A1 $end -$var wire 1 _" A2 $end -$var wire 1 `" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 a" D $end -$var wire 1 b" Q $end -$var reg 16 c" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[17] $end -$scope module srl16e $end -$var wire 1 d" A0 $end -$var wire 1 e" A1 $end -$var wire 1 f" A2 $end -$var wire 1 g" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 h" D $end -$var wire 1 i" Q $end -$var reg 16 j" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[18] $end -$scope module srl16e $end -$var wire 1 k" A0 $end -$var wire 1 l" A1 $end -$var wire 1 m" A2 $end -$var wire 1 n" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 o" D $end -$var wire 1 p" Q $end -$var reg 16 q" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[19] $end -$scope module srl16e $end -$var wire 1 r" A0 $end -$var wire 1 s" A1 $end -$var wire 1 t" A2 $end -$var wire 1 u" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 v" D $end -$var wire 1 w" Q $end -$var reg 16 x" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[20] $end -$scope module srl16e $end -$var wire 1 y" A0 $end -$var wire 1 z" A1 $end -$var wire 1 {" A2 $end -$var wire 1 |" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 }" D $end -$var wire 1 ~" Q $end -$var reg 16 !# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[21] $end -$scope module srl16e $end -$var wire 1 "# A0 $end -$var wire 1 ## A1 $end -$var wire 1 $# A2 $end -$var wire 1 %# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 &# D $end -$var wire 1 '# Q $end -$var reg 16 (# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[22] $end -$scope module srl16e $end -$var wire 1 )# A0 $end -$var wire 1 *# A1 $end -$var wire 1 +# A2 $end -$var wire 1 ,# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 -# D $end -$var wire 1 .# Q $end -$var reg 16 /# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[23] $end -$scope module srl16e $end -$var wire 1 0# A0 $end -$var wire 1 1# A1 $end -$var wire 1 2# A2 $end -$var wire 1 3# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 4# D $end -$var wire 1 5# Q $end -$var reg 16 6# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[24] $end -$scope module srl16e $end -$var wire 1 7# A0 $end -$var wire 1 8# A1 $end -$var wire 1 9# A2 $end -$var wire 1 :# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ;# D $end -$var wire 1 <# Q $end -$var reg 16 =# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[25] $end -$scope module srl16e $end -$var wire 1 ># A0 $end -$var wire 1 ?# A1 $end -$var wire 1 @# A2 $end -$var wire 1 A# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 B# D $end -$var wire 1 C# Q $end -$var reg 16 D# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[26] $end -$scope module srl16e $end -$var wire 1 E# A0 $end -$var wire 1 F# A1 $end -$var wire 1 G# A2 $end -$var wire 1 H# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 I# D $end -$var wire 1 J# Q $end -$var reg 16 K# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[27] $end -$scope module srl16e $end -$var wire 1 L# A0 $end -$var wire 1 M# A1 $end -$var wire 1 N# A2 $end -$var wire 1 O# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 P# D $end -$var wire 1 Q# Q $end -$var reg 16 R# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[28] $end -$scope module srl16e $end -$var wire 1 S# A0 $end -$var wire 1 T# A1 $end -$var wire 1 U# A2 $end -$var wire 1 V# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 W# D $end -$var wire 1 X# Q $end -$var reg 16 Y# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[29] $end -$scope module srl16e $end -$var wire 1 Z# A0 $end -$var wire 1 [# A1 $end -$var wire 1 \# A2 $end -$var wire 1 ]# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ^# D $end -$var wire 1 _# Q $end -$var reg 16 `# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[30] $end -$scope module srl16e $end -$var wire 1 a# A0 $end -$var wire 1 b# A1 $end -$var wire 1 c# A2 $end -$var wire 1 d# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 e# D $end -$var wire 1 f# Q $end -$var reg 16 g# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[31] $end -$scope module srl16e $end -$var wire 1 h# A0 $end -$var wire 1 i# A1 $end -$var wire 1 j# A2 $end -$var wire 1 k# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 l# D $end -$var wire 1 m# Q $end -$var reg 16 n# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[32] $end -$scope module srl16e $end -$var wire 1 o# A0 $end -$var wire 1 p# A1 $end -$var wire 1 q# A2 $end -$var wire 1 r# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 s# D $end -$var wire 1 t# Q $end -$var reg 16 u# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[33] $end -$scope module srl16e $end -$var wire 1 v# A0 $end -$var wire 1 w# A1 $end -$var wire 1 x# A2 $end -$var wire 1 y# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 z# D $end -$var wire 1 {# Q $end -$var reg 16 |# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[34] $end -$scope module srl16e $end -$var wire 1 }# A0 $end -$var wire 1 ~# A1 $end -$var wire 1 !$ A2 $end -$var wire 1 "$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 #$ D $end -$var wire 1 $$ Q $end -$var reg 16 %$ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[35] $end -$scope module srl16e $end -$var wire 1 &$ A0 $end -$var wire 1 '$ A1 $end -$var wire 1 ($ A2 $end -$var wire 1 )$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 *$ D $end -$var wire 1 +$ Q $end -$var reg 16 ,$ data [15:0] $end -$upscope $end -$upscope $end -$upscope $end -$scope module fifo36_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 -$ f19_dataout [18:0] $end -$var wire 1 ' f19_dst_rdy_i $end -$var wire 1 ( f19_src_rdy_o $end -$var wire 1 .$ f19_xfer $end -$var wire 36 /$ f36_datain [35:0] $end -$var wire 1 $ f36_dst_rdy_o $end -$var wire 1 0$ f36_eof $end -$var wire 1 1$ f36_occ $end -$var wire 1 2$ f36_sof $end -$var wire 1 % f36_src_rdy_i $end -$var wire 1 3$ f36_xfer $end -$var wire 1 4$ half_line $end -$var wire 1 C reset $end -$var reg 1 5$ phase $end -$upscope $end -$scope module fifo19_to_ll8 $end -$var wire 1 6$ advance $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 7$ f19_data [18:0] $end -$var wire 1 ' f19_dst_rdy_o $end -$var wire 1 8$ f19_eof $end -$var wire 1 9$ f19_occ $end -$var wire 1 :$ f19_sof $end -$var wire 1 ( f19_src_rdy_i $end -$var wire 1 ;$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 <$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 =$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 >$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var reg 8 ?$ ll_data [7:0] $end -$var reg 1 @$ state $end -$upscope $end -$scope module ll8_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 A$ f19_data [18:0] $end -$var wire 1 * f19_dst_rdy_i $end -$var wire 1 + f19_src_rdy_o $end -$var wire 8 B$ ll_data [7:0] $end -$var wire 1 C$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 D$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 E$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 F$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var wire 1 G$ xfer_out $end -$var reg 8 H$ dat0 [7:0] $end -$var reg 8 I$ dat1 [7:0] $end -$var reg 1 J$ f19_eof $end -$var reg 1 K$ f19_occ $end -$var reg 1 L$ f19_sof $end -$var reg 2 M$ state [1:0] $end -$upscope $end -$scope module fifo19_to_fifo36 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 N$ f19_datain [18:0] $end -$var wire 1 * f19_dst_rdy_o $end -$var wire 1 O$ f19_eof $end -$var wire 1 P$ f19_occ $end -$var wire 1 Q$ f19_sof $end -$var wire 1 + f19_src_rdy_i $end -$var wire 36 R$ f36_dataout [35:0] $end -$var wire 1 S$ f36_dst_rdy_i $end -$var wire 1 - f36_src_rdy_o $end -$var wire 1 C reset $end -$var wire 1 T$ xfer_out $end -$var reg 16 U$ dat0 [15:0] $end -$var reg 16 V$ dat1 [15:0] $end -$var reg 1 W$ f36_eof $end -$var reg 1 X$ f36_occ $end -$var reg 1 Y$ f36_sof $end -$var reg 2 Z$ state [1:0] $end -$upscope $end -$scope task PutPacketInFIFO36 $end -$var reg 32 [$ data_len [31:0] $end -$var reg 32 \$ data_start [31:0] $end -$upscope $end -$scope task ReadFromFIFO36 $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx \$ -bx [$ -bx Z$ -xY$ -xX$ -xW$ -bx V$ -bx U$ -0T$ -0S$ -b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$ -xQ$ -xP$ -xO$ -bx N$ -bx M$ -xL$ -xK$ -xJ$ -bx I$ -bx H$ -xG$ -xF$ -xE$ -xD$ -xC$ -bx B$ -bx A$ -x@$ -bx ?$ -x>$ -x=$ -x<$ -x;$ -x:$ -x9$ -x8$ -bx 7$ -x6$ -x5$ -x4$ -x3$ -x2$ -x1$ -x0$ -bx /$ -x.$ -bx -$ -b0 ,$ -x+$ -0*$ -x)$ -x($ -x'$ -x&$ -b0 %$ -x$$ -0#$ -x"$ -x!$ -x~# -x}# -b0 |# -x{# -0z# -xy# -xx# -xw# -xv# -b0 u# -xt# -0s# -xr# -xq# -xp# -xo# -b0 n# -xm# -0l# -xk# -xj# -xi# -xh# -b0 g# -xf# -0e# -xd# -xc# -xb# -xa# -b0 `# -x_# -0^# -x]# -x\# -x[# -xZ# -b0 Y# -xX# -0W# -xV# -xU# -xT# -xS# -b0 R# -xQ# -0P# -xO# -xN# -xM# -xL# -b0 K# -xJ# -0I# -xH# -xG# -xF# -xE# -b0 D# -xC# -0B# -xA# -x@# -x?# -x># -b0 =# -x<# -0;# -x:# -x9# -x8# -x7# -b0 6# -x5# -04# -x3# -x2# -x1# -x0# -b0 /# -x.# -0-# -x,# -x+# -x*# -x)# -b0 (# -x'# -0&# -x%# -x$# -x## -x"# -b0 !# -x~" -0}" -x|" -x{" -xz" -xy" -b0 x" -xw" -0v" -xu" -xt" -xs" -xr" -b0 q" -xp" -0o" -xn" -xm" -xl" -xk" -b0 j" -xi" -0h" -xg" -xf" -xe" -xd" -b0 c" -xb" -0a" -x`" -x_" -x^" -x]" -b0 \" -x[" -0Z" -xY" -xX" -xW" -xV" -b0 U" -xT" -0S" -xR" -xQ" -xP" -xO" -b0 N" -xM" -0L" -xK" -xJ" -xI" -xH" -b0 G" -xF" -0E" -xD" -xC" -xB" -xA" -b0 @" -x?" -0>" -x=" -x<" -x;" -x:" -b0 9" -x8" -07" -x6" -x5" -x4" -x3" -b0 2" -x1" -00" -x/" -x." -x-" -x," -b0 +" -x*" -0)" -x(" -x'" -x&" -x%" -b0 $" -x#" -0"" -x!" -x~ -x} -x| -b0 { -xz -0y -xx -xw -xv -xu -b0 t -xs -0r -xq -xp -xo -xn -b0 m -xl -0k -xj -xi -xh -xg -b0 f -xe -0d -xc -xb -xa -x` -b0 _ -x^ -0] -x\ -x[ -xZ -xY -b0 X -xW -0V -xU -xT -xS -xR -b0 Q -xP -0O -xN -xM -xL -xK -bx J -bx I -xH -xG -bx F -0E -0D -1C -xB -bx A -b0 @ -0? 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-#14200000000000000 -04 -0? -#14250000000000000 -1.$ -1' -b11110110 ?$ -b11110110 . -b11110110 B$ -0G$ -1T$ -1@$ -b1 M$ -0+ -b11100110 H$ -b1110011010110101 ) -b1110011010110101 A$ -b1110011010110101 N$ -b10 Z$ -1- -b1010010110110101 V$ -b11100101111101011010010110110101 , -b11100101111101011010010110110101 R$ -14 -1? -#14300000000000000 -04 -0? -#14350000000000000 -0.$ -03$ -0B -0' -0$ -0T$ -1G$ -b10100110 ?$ -b10100110 . -b10100110 B$ -b1010011010110110 & -b1010011010110110 -$ -b1010011010110110 7$ -b0 Z$ -0- -b11110110 I$ -b1110011011110110 ) -b1110011011110110 A$ -b1110011011110110 N$ -b10 M$ -1+ -0@$ -15$ -14 -1? -#14400000000000000 -04 -0? -#14450000000000000 -13$ -1B -1.$ -1$ -1' -b10110110 ?$ -b10110110 . -b10110110 B$ -0G$ -1@$ -b1 M$ -0+ -b10100110 H$ -b1010011011110110 ) -b1010011011110110 A$ -b1010011011110110 N$ -b1 Z$ -b1110011011110110 U$ -b11100110111101101010010110110101 , -b11100110111101101010010110110101 R$ -14 -1? -#14500000000000000 -04 -0? -#14550000000000000 -0.$ -03$ -0B -0' -0$ -1G$ -b11100111 ?$ -b11100111 . -b11100111 B$ -b1110011111110111 & -b1110011111110111 -$ -b1110011111110111 7$ -1K -1P -0L -1R -0S -1W -1Y -0Z -1^ -1` -0a -0e -1g -0h -1n -0o -1u -0v -1| -0} -1%" -1*" -0&" -1," -0-" -11" -13" -04" -18" -1:" -0;" -0?" -1A" -0B" -1H" -0I" -1O" -0P" -1V" -0W" -1]" -1b" -0^" -1d" -0e" -1i" -1k" -0l" -1p" -1r" -0s" -0w" -1y" -0z" -1"# -0## -1)# -0*# -10# -01# -17# -1<# -08# -1># -0?# -1C# -1E# -0F# -1J# -1L# -0M# -0Q# -1S# -0T# -1Z# -0[# -1a# -0b# -1h# -0i# -1o# -0p# -1v# -0w# -0{# -b11100111111101111010011110110111 # -b11100111111101111010011110110111 A -b11100111111101111010011110110111 /$ -1}# -0~# -1&$ -0'$ -b10110110 I$ -b1010011010110110 ) -b1010011010110110 A$ -b1010011010110110 N$ -b10 M$ -1+ -0@$ -05$ -b10 I -b1110 J -b1 F -14 -1? -#14600000000000000 -04 -0? -#14650000000000000 -1.$ -1' -b11110111 ?$ -b11110111 . -b11110111 B$ -0G$ -1T$ -1@$ -b1 M$ -0+ -b11100111 H$ -b1110011110110110 ) -b1110011110110110 A$ -b1110011110110110 N$ -b10 Z$ -1- -b1010011010110110 V$ -b11100110111101101010011010110110 , -b11100110111101101010011010110110 R$ -14 -1? -#14700000000000000 -04 -0? -#14750000000000000 -0.$ -03$ -0B -0' -0$ -0T$ -1G$ -b10100111 ?$ -b10100111 . -b10100111 B$ -b1010011110110111 & -b1010011110110111 -$ -b1010011110110111 7$ -b0 Z$ -0- -b11110111 I$ -b1110011111110111 ) -b1110011111110111 A$ -b1110011111110111 N$ -b10 M$ -1+ -0@$ -15$ -14 -1? -#14800000000000000 -04 -0? -#14850000000000000 -13$ -1B -1.$ -1$ -1' -b10110111 ?$ -b10110111 . -b10110111 B$ -0G$ -1@$ -b1 M$ -0+ -b10100111 H$ -b1010011111110111 ) -b1010011111110111 A$ -b1010011111110111 N$ -b1 Z$ -b1110011111110111 U$ -b11100111111101111010011010110110 , -b11100111111101111010011010110110 R$ -14 -1? -#14900000000000000 -04 -0? -#14950000000000000 -0.$ -03$ -0B -0' -0$ -10$ -1G$ -b11101000 ?$ -b11101000 . -b11101000 B$ -b1110100011111000 & -b1110100011111000 -$ -b1110100011111000 7$ -0K -0P -0R -0W -0Y -0^ -0` -1e -0g -0n -0u -0| -0%" -0*" -0," -01" -03" -08" -0:" -1?" -0A" -0H" -0O" -0V" -0]" -0b" -0d" -0i" -0k" -0p" -0r" -1w" -0y" -0"# -0)# -00# -07# -0<# -0># -0C# -0E# -0J# -0L# -1Q# -0S# -0Z# -0a# -0h# -0o# -0v# -1{# -b1011101000111110001010100010111000 # -b1011101000111110001010100010111000 A -b1011101000111110001010100010111000 /$ -0}# -0&$ -b10110111 I$ -b1010011110110111 ) -b1010011110110111 A$ -b1010011110110111 N$ -b10 M$ -1+ -0@$ -05$ -b1 I -b1111 J -b0 F -14 -1? -#15000000000000000 -04 -0? -#15050000000000000 -1.$ -1' -b11111000 ?$ -b11111000 . -b11111000 B$ -0G$ -1T$ -1@$ -b1 M$ -0+ -b11101000 H$ -b1110100010110111 ) -b1110100010110111 A$ -b1110100010110111 N$ -b10 Z$ -1- -b1010011110110111 V$ -b11100111111101111010011110110111 , -b11100111111101111010011110110111 R$ -14 -1? -#15100000000000000 -04 -0? -#15150000000000000 -0.$ -03$ -0B -0' -18$ -0$ -0T$ -1G$ -b10101000 ?$ -b10101000 . -b10101000 B$ -b101010100010111000 & -b101010100010111000 -$ -b101010100010111000 7$ -b0 Z$ -0- -b11111000 I$ -b1110100011111000 ) -b1110100011111000 A$ -b1110100011111000 N$ -b10 M$ -1+ -0@$ -15$ -14 -1? -#15200000000000000 -04 -0? -#15250000000000000 -1D$ -13$ -1B -00 -1.$ -1$ -1<$ -1' -b10111000 ?$ -b10111000 . -b10111000 B$ -0G$ -1@$ -b1 M$ -0+ -b10101000 H$ -b1010100011111000 ) -b1010100011111000 A$ -b1010100011111000 N$ -b1 Z$ -b1110100011111000 U$ -b11101000111110001010011110110111 , -b11101000111110001010011110110111 R$ -14 -1? -#15300000000000000 -04 -0? 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-#18100000000000000 -04 -0? -#18150000000000000 -14 -1? -#18200000000000000 -04 -0? -#18250000000000000 -14 -1? -#18300000000000000 -04 -0? -#18350000000000000 -14 -1? -#18400000000000000 -04 -0? -#18450000000000000 -14 -1? -#18500000000000000 -04 -0? -#18550000000000000 -14 -1? -#18600000000000000 -04 -0? -#18650000000000000 -14 -1? -#18700000000000000 -04 -0? -#18750000000000000 -14 -1? -#18800000000000000 -04 -0? -#18850000000000000 -14 -1? -#18900000000000000 -04 -0? -#18950000000000000 -14 -1? -#19000000000000000 -04 -0? -#19050000000000000 -14 -1? -#19100000000000000 -04 -0? -#19150000000000000 -14 -1? -#19200000000000000 -04 -0? -#19250000000000000 -14 -1? -#19300000000000000 -04 -0? -#19350000000000000 -14 -1? -#19400000000000000 -04 -0? -#19450000000000000 -14 -1? -#19500000000000000 -04 -0? -#19550000000000000 -14 -1? -#19600000000000000 -04 -0? -#19650000000000000 -14 -1? -#19700000000000000 -04 -0? -#19750000000000000 -14 -1? -#19800000000000000 -04 -0? -#19850000000000000 -14 -1? -#19900000000000000 -04 -0? -#19950000000000000 -14 -1? -#20000000000000000 -04 -0? diff --git a/control_lib/newfifo/fifo_short.v b/control_lib/newfifo/fifo_short.v deleted file mode 100644 index 53a7603c7..000000000 --- a/control_lib/newfifo/fifo_short.v +++ /dev/null @@ -1,95 +0,0 @@ - -module fifo_short - #(parameter WIDTH=32) - (input clk, input reset, input clear, - input [WIDTH-1:0] datain, - input src_rdy_i, - output dst_rdy_o, - output [WIDTH-1:0] dataout, - output src_rdy_o, - input dst_rdy_i, - - output reg [4:0] space, - output reg [4:0] occupied); - - reg full, empty; - wire write = src_rdy_i & dst_rdy_o; - wire read = dst_rdy_i & src_rdy_o; - - assign dst_rdy_o = ~full; - assign src_rdy_o = ~empty; - - reg [3:0] a; - genvar i; - - generate - for (i=0;i 00 = all 4 bytes - 01 = 1 byte - 10 = 2 bytes - 11 = 3 bytes - -fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]} - OCC same as buffer interface - -fifo19 --> {OCC,EOP,SOP,DATA[15:0]} - Doesn't fit well into BRAM, dist RAM ok - OCC = 1 means last word is half full - = 0 means last word is full - -fifo18 --> {EOP,SOP,DATA[15:0]} - No half-word capability? Should we drop sop instead? - -Control Wires - Data into FIFO - SRC_RDY_i Upstream has data for me - DST_RDY_o I have space - Transfer occurs if SRC_RDI_i && DST_RDY_o - -Control Wires - Data out of FIFO - SRC_RDY_o I have data for downstream - DST_RDY_i Downstream has space - Transfer occurs if SRC_RDI_o && DST_RDY_i - diff --git a/control_lib/newfifo/fifo_tb.v b/control_lib/newfifo/fifo_tb.v deleted file mode 100644 index f561df7fa..000000000 --- a/control_lib/newfifo/fifo_tb.v +++ /dev/null @@ -1,158 +0,0 @@ -module fifo_new_tb(); - - reg clk = 0; - reg rst = 1; - reg clear = 0; - initial #1000 rst = 0; - always #50 clk = ~clk; - - reg [31:0] f36_data = 0; - reg [1:0] f36_occ = 0; - reg f36_sof = 0, f36_eof = 0; - - wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; - reg src_rdy_f36i = 0; - wire dst_rdy_f36i; - - wire [35:0] f36_out, f36_out2; - wire src_rdy_f36o; - reg dst_rdy_f36o = 0; - - //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36 - //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 - - wire i1_sr, i1_dr; - wire i2_sr, i2_dr; - wire i3_sr, i3_dr; - reg i4_dr = 0; - wire i4_sr; - - wire [35:0] i1, i4; - wire [18:0] i2, i3; - - wire [7:0] ll_data; - wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n; - - fifo_short #(.WIDTH(36)) fifo_short1 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), - .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) ); - - fifo36_to_fifo19 fifo36_to_fifo19 - (.clk(clk),.reset(rst),.clear(clear), - .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr), - .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) ); - - fifo19_to_ll8 fifo19_to_ll8 - (.clk(clk),.reset(rst),.clear(clear), - .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr), - .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n)); - - ll8_to_fifo19 ll8_to_fifo19 - (.clk(clk),.reset(rst),.clear(clear), - .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n), - .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) ); - - fifo19_to_fifo36 fifo19_to_fifo36 - (.clk(clk),.reset(rst),.clear(clear), - .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr), - .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) ); - - task ReadFromFIFO36; - begin - $display("Read from FIFO36"); - #1 i4_dr <= 1; - while(1) - begin - while(~i4_sr) - @(posedge clk); - $display("Read: %h",i4); - @(posedge clk); - end - end - endtask // ReadFromFIFO36 - - reg [15:0] count; - task PutPacketInFIFO36; - input [31:0] data_start; - input [31:0] data_len; - begin - count <= 4; - src_rdy_f36i <= 1; - f36_data <= data_start; - f36_sof <= 1; - f36_eof <= 0; - f36_occ <= 0; - - $display("Put Packet in FIFO36"); - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - $display("PPI_FIFO36: Entered First Line"); - f36_sof <= 0; - while(count+4 < data_len) - begin - f36_data <= f36_data + 32'h01010101; - count <= count + 4; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - $display("PPI_FIFO36: Entered New Line"); - end - f36_data <= f36_data + 32'h01010101; - f36_eof <= 1; - if(count + 4 == data_len) - f36_occ <= 0; - else if(count + 3 == data_len) - f36_occ <= 3; - else if(count + 2 == data_len) - f36_occ <= 2; - else - f36_occ <= 1; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - f36_occ <= 0; - f36_eof <= 0; - f36_data <= 0; - src_rdy_f36i <= 0; - $display("PPI_FIFO36: Entered Last Line"); - end - endtask // PutPacketInFIFO36 - - initial $dumpfile("fifo_new_tb.vcd"); - initial $dumpvars(0,fifo_new_tb); - - initial - begin - @(negedge rst); - //#10000; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - ReadFromFIFO36; - end - - initial - begin - @(negedge rst); - @(posedge clk); - @(posedge clk); - PutPacketInFIFO36(32'hA0B0C0D0,12); - @(posedge clk); - @(posedge clk); - #10000; - @(posedge clk); - PutPacketInFIFO36(32'hE0F0A0B0,36); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end - - initial #20000 $finish; -endmodule // longfifo_tb diff --git a/control_lib/newfifo/ll8_shortfifo.v b/control_lib/newfifo/ll8_shortfifo.v deleted file mode 100644 index 39ada9a4f..000000000 --- a/control_lib/newfifo/ll8_shortfifo.v +++ /dev/null @@ -1,13 +0,0 @@ - - -module ll8_shortfifo - (input clk, input reset, input clear, - input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o, - output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i); - - fifo_short #(.WIDTH(11)) fifo_short - (.clk(clk), .reset(reset), .clear(clear), - .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - -endmodule // ll8_shortfifo diff --git a/control_lib/newfifo/ll8_to_fifo19.v b/control_lib/newfifo/ll8_to_fifo19.v deleted file mode 100644 index c65be5136..000000000 --- a/control_lib/newfifo/ll8_to_fifo19.v +++ /dev/null @@ -1,77 +0,0 @@ - -module ll8_to_fifo19 - (input clk, input reset, input clear, - input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, - - output [18:0] f19_data, - output f19_src_rdy_o, - input f19_dst_rdy_i ); - - // Why anybody would use active low in an FPGA is beyond me... - wire ll_sof = ~ll_sof_n; - wire ll_eof = ~ll_eof_n; - wire ll_src_rdy = ~ll_src_rdy_n; - wire ll_dst_rdy; - assign ll_dst_rdy_n = ~ll_dst_rdy; - - wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i; - // wire xfer_in = ll_src_rdy & ll_dst_rdy; Not needed - - reg f19_sof, f19_eof, f19_occ; - - reg [1:0] state; - reg [7:0] dat0, dat1; - - always @(posedge clk) - if(ll_src_rdy & ((state==0)|xfer_out)) - f19_sof <= ll_sof; - - always @(posedge clk) - if(ll_src_rdy & ((state != 2)|xfer_out)) - f19_eof <= ll_eof; - - always @(posedge clk) - if(ll_eof) - f19_occ <= ~state[0]; - else - f19_occ <= 0; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(ll_src_rdy) - case(state) - 0 : - if(ll_eof) - state <= 2; - else - state <= 1; - 1 : - state <= 2; - 2 : - if(xfer_out) - state <= 1; - endcase // case(state) - else - if(xfer_out) - state <= 0; - - always @(posedge clk) - if(ll_src_rdy & (state==1)) - dat1 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & ((state==0) | xfer_out)) - dat0 <= ll_data; - - assign ll_dst_rdy = xfer_out | (state != 2); - assign f19_data = {f19_occ,f19_eof,f19_sof,dat0,dat1}; - assign f19_src_rdy_o = (state == 2); - -endmodule // ll8_to_fifo19 - diff --git a/control_lib/newfifo/ll8_to_fifo36.v b/control_lib/newfifo/ll8_to_fifo36.v deleted file mode 100644 index 108daa903..000000000 --- a/control_lib/newfifo/ll8_to_fifo36.v +++ /dev/null @@ -1,97 +0,0 @@ - -module ll8_to_fifo36 - (input clk, input reset, input clear, - input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, - - output [35:0] f36_data, - output f36_src_rdy_o, - input f36_dst_rdy_i ); - - wire f36_write = f36_src_rdy_o & f36_dst_rdy_i; - - // Why anybody would use active low in an FPGA is beyond me... - wire ll_sof = ~ll_sof_n; - wire ll_eof = ~ll_eof_n; - wire ll_src_rdy = ~ll_src_rdy_n; - wire ll_dst_rdy; - assign ll_dst_rdy_n = ~ll_dst_rdy; - - reg f36_sof, f36_eof; - reg [1:0] f36_occ; - - - reg [2:0] state; - reg [7:0] dat0, dat1, dat2, dat3; - - always @(posedge clk) - if(ll_src_rdy & ((state==0)|f36_write)) - f36_sof <= ll_sof; - - always @(posedge clk) - if(ll_src_rdy & ((state !=4)|f36_write)) - f36_eof <= ll_eof; - - always @(posedge clk) - if(ll_eof) - f36_occ <= state[1:0] + 1; - else - f36_occ <= 0; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(ll_src_rdy) - case(state) - 0 : - if(ll_eof) - state <= 4; - else - state <= 1; - 1 : - if(ll_eof) - state <= 4; - else - state <= 2; - 2 : - if(ll_eof) - state <= 4; - else - state <= 3; - 3 : state <= 4; - 4 : - if(f36_dst_rdy_i) - if(ll_eof) - state <= 4; - else - state <= 1; - endcase // case(state) - else - if(f36_write) - state <= 0; - - always @(posedge clk) - if(ll_src_rdy & (state==3)) - dat3 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & (state==2)) - dat2 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & (state==1)) - dat1 <= ll_data; - - always @(posedge clk) - if(ll_src_rdy & ((state==0) | f36_write)) - dat0 <= ll_data; - - assign ll_dst_rdy = f36_dst_rdy_i | (state != 4); - assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess - assign f36_src_rdy_o = (state == 4); - -endmodule // ll8_to_fifo36 diff --git a/control_lib/nsgpio.v b/control_lib/nsgpio.v deleted file mode 100644 index 937ea7020..000000000 --- a/control_lib/nsgpio.v +++ /dev/null @@ -1,107 +0,0 @@ -// Modified from code originally by Richard Herveille, his copyright is below - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple General Purpose IO core //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - - -module nsgpio - (input clk_i, input rst_i, - input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0] dat_i, - output reg [31:0] dat_o, output reg ack_o, - input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, - inout [31:0] gpio - ); - - reg [63:0] ctrl; - reg [31:0] line; - reg [31:0] lgpio; // LatchedGPIO pins - reg [31:0] ddr; - - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - begin - ctrl <= 64'h0; - line <= 0; - end - else if (wb_wr) - case( adr_i[3:2] ) - 2'b00 : - line <= dat_i; - 2'b01 : - ddr[31:0] <= dat_i; - 2'b10 : - ctrl[63:32] <= dat_i; - 2'b11 : - ctrl[31:0] <= dat_i; - endcase // case( adr_i[3:2] ) - - always @(posedge clk_i) - case (adr_i[3:2]) - 2'b00 : - dat_o <= lgpio; - 2'b01 : - dat_o <= ddr; - 2'b10 : - dat_o <= ctrl[63:32]; - 2'b11 : - dat_o <= ctrl[31:0]; - endcase // case(adr_i[3:2]) - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - ack_o <= 1'b0; - else - ack_o <= wb_acc & !ack_o; - - // latch GPIO input pins - always @(posedge clk_i) - lgpio <= gpio; - - // assign GPIO outputs - integer n; - reg [31:0] igpio; // temporary internal signal - - always @(ctrl or line or debug_1 or debug_0 or atr) - for(n=0;n<32;n=n+1) - igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : - (ctrl[2*n] ? atr[n] : line[n]) ) - : 1'bz; - - assign gpio = igpio; - -endmodule - diff --git a/control_lib/oneshot_2clk.v b/control_lib/oneshot_2clk.v deleted file mode 100644 index 72f16a4b3..000000000 --- a/control_lib/oneshot_2clk.v +++ /dev/null @@ -1,35 +0,0 @@ - -// Retime a single bit from one clock domain to another -// Guarantees that no matter what the relative clock rates, if the in signal is high for at least -// one clock cycle in the clk_in domain, then the out signal will be high for at least one -// clock cycle in the clk_out domain. If the in signal goes high again before the process is done -// the behavior is undefined. No other guarantees. Designed for passing reset into a new -// clock domain. - -module oneshot_2clk - (input clk_in, - input in, - input clk_out, - output reg out); - - reg del_in = 0; - reg sendit = 0, gotit = 0; - reg sendit_d = 0, gotit_d = 0; - - always @(posedge clk_in) del_in <= in; - - always @(posedge clk_in) - if(in & ~del_in) // we have a positive edge - sendit <= 1; - else if(gotit) - sendit <= 0; - - always @(posedge clk_out) sendit_d <= sendit; - always @(posedge clk_out) out <= sendit_d; - - always @(posedge clk_in) gotit_d <= out; - always @(posedge clk_in) gotit <= gotit_d; - -endmodule // oneshot_2clk - - diff --git a/control_lib/pic.v b/control_lib/pic.v deleted file mode 100644 index 9b9944d4a..000000000 --- a/control_lib/pic.v +++ /dev/null @@ -1,183 +0,0 @@ - -// Heavily modified by M. Ettus, 2009, little original code remains -// Modified by M. Ettus, 2008 for 32 bit width - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple Programmable Interrupt Controller //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -// -// This is a simple Programmable Interrupt Controller. -// The number of interrupts is depending on the databus size. -// There's one interrupt input per databit (i.e. 16 interrupts for a 16 -// bit databus). -// All attached devices share the same CPU priority level. -// -// -// -// Registers: -// -// 0x00: EdgeEnable Register -// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source -// '0' = level triggered interrupt source -// 0x01: PolarityRegister -// bits 7:0 R/W Polarity '1' = high level / rising edge -// '0' = low level / falling edge -// 0x02: MaskRegister -// bits 7:0 R/W Mask '1' = interrupt masked (disabled) -// '0' = interrupt not masked (enabled) -// 0x03: PendingRegister -// bits 7:0 R/W Pending '1' = interrupt pending -// '0' = no interrupt pending -// -// A CPU interrupt is generated when an interrupt is pending and its -// MASK bit is cleared. -// -// -// -// HOWTO: -// -// Clearing pending interrupts: -// Writing a '1' to a bit in the interrupt pending register clears the -// interrupt. Make sure to clear the interrupt at the source before -// writing to the interrupt pending register. Otherwise the interrupt -// will be set again. -// -// Priority based interrupts: -// Upon reception of an interrupt, check the interrupt register and -// determine the highest priority interrupt. Mask all interrupts from the -// current level to the lowest level. This negates the interrupt line, and -// makes sure only interrupts with a higher level are triggered. After -// completion of the interrupt service routine, clear the interrupt source, -// the interrupt bit in the pending register, and restore the MASK register -// to it's previous state. -// -// Addapt the core for fewer interrupt sources: -// If less than 8 interrupt sources are required, than the 'is' parameter -// can be set to the amount of required interrupts. Interrupts are mapped -// starting at the LSBs. So only the 'is' LSBs per register are valid. All -// other bits (i.e. the 8-'is' MSBs) are set to zero '0'. -// Codesize is approximately linear to the amount of interrupts. I.e. using -// 4 instead of 8 interrupt sources reduces the size by approx. half. -// - - -module pic - (input clk_i, input rst_i, input cyc_i, input stb_i, - input [2:0] adr_i, - input we_i, - input [31:0] dat_i, - output reg [31:0] dat_o, - output reg ack_o, - output reg int_o, - input [31:0] irq - ); - - reg [31:0] pol, edgen, pending, mask; // register bank - reg [31:0] lirq, dirq; // latched irqs, delayed latched irqs - - // latch interrupt inputs - always @(posedge clk_i) - lirq <= irq; - - // generate delayed latched irqs - always @(posedge clk_i) - dirq <= lirq; - - // generate actual triggers - function trigger; - input edgen, pol, lirq, dirq; - reg edge_irq, level_irq; - begin - edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq); - level_irq = pol ? lirq : ~lirq; - trigger = edgen ? edge_irq : level_irq; - end - endfunction - - reg [31:0] irq_event; - integer n; - always @(posedge clk_i) - for(n = 0; n < 32; n = n+1) - irq_event[n] <= trigger(edgen[n], pol[n], lirq[n], dirq[n]); - - // generate wishbone register bank writes - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i) - if (rst_i) - begin - pol <= 0; // clear polarity register - edgen <= 0; // clear edge enable register - mask <= 0; // mask all interrupts - end - else if(wb_wr) // wishbone write cycle?? - case (adr_i) // synopsys full_case parallel_case - 3'd0 : edgen <= dat_i; // EDGE-ENABLE register - 3'd1 : pol <= dat_i; // POLARITY register - 3'd2 : mask <= dat_i; // MASK register - 3'd3 : ; // PENDING register is a special case (see below) - 3'd4 : ; // Priority encoded live (pending & ~mask) - endcase - - // pending register is a special case - always @(posedge clk_i) - if (rst_i) - pending <= 0; // clear all pending interrupts - else if ( wb_wr & (adr_i == 3'd3) ) - pending <= (pending & ~dat_i) | irq_event; - else - pending <= pending | irq_event; - - wire [31:0] live_enc; - priority_enc priority_enc ( .in(pending & ~mask), .out(live_enc) ); - - always @(posedge clk_i) - case (adr_i) // synopsys full_case parallel_case - 3'd0 : dat_o <= edgen; - 3'd1 : dat_o <= pol; - 3'd2 : dat_o <= mask; - 3'd3 : dat_o <= pending; - 3'd4 : dat_o <= live_enc; - endcase - - always @(posedge clk_i) - ack_o <= wb_acc & !ack_o; - - always @(posedge clk_i) - if(rst_i) - int_o <= 0; - else - int_o <= |(pending & ~mask); - -endmodule diff --git a/control_lib/priority_enc.v b/control_lib/priority_enc.v deleted file mode 100644 index 916192445..000000000 --- a/control_lib/priority_enc.v +++ /dev/null @@ -1,44 +0,0 @@ - -module priority_enc - (input [31:0] in, - output reg [31:0] out); - - always @* - casex(in) - 32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 31; - 32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 30; - 32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 29; - 32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 28; - 32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 27; - 32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 26; - 32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 25; - 32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 24; - 32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 23; - 32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 22; - 32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 21; - 32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 20; - 32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : out <= 19; - 32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : out <= 18; - 32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : out <= 17; - 32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : out <= 16; - 32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : out <= 15; - 32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : out <= 14; - 32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : out <= 13; - 32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : out <= 12; - 32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : out <= 11; - 32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : out <= 10; - 32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : out <= 9; - 32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : out <= 8; - 32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : out <= 7; - 32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : out <= 6; - 32'b0000_0000_0000_0000_0000_0000_001x_xxxx : out <= 5; - 32'b0000_0000_0000_0000_0000_0000_0001_xxxx : out <= 4; - 32'b0000_0000_0000_0000_0000_0000_0000_1xxx : out <= 3; - 32'b0000_0000_0000_0000_0000_0000_0000_01xx : out <= 2; - 32'b0000_0000_0000_0000_0000_0000_0000_001x : out <= 1; - 32'b0000_0000_0000_0000_0000_0000_0000_0001 : out <= 0; - 32'b0000_0000_0000_0000_0000_0000_0000_0000 : out <= 32'hFFFF_FFFF; - default : out <= 32'hFFFF_FFFF; - endcase // casex (in) - -endmodule // priority_enc diff --git a/control_lib/ram_2port.v b/control_lib/ram_2port.v deleted file mode 100644 index 6c8332b9c..000000000 --- a/control_lib/ram_2port.v +++ /dev/null @@ -1,42 +0,0 @@ - - -module ram_2port - #(parameter DWIDTH=32, - parameter AWIDTH=9) - (input clka, - input ena, - input wea, - input [AWIDTH-1:0] addra, - input [DWIDTH-1:0] dia, - output reg [DWIDTH-1:0] doa, - - input clkb, - input enb, - input web, - input [AWIDTH-1:0] addrb, - input [DWIDTH-1:0] dib, - output reg [DWIDTH-1:0] dob); - - reg [DWIDTH-1:0] ram [(1<>1)); - wire latch_dat = (clk_ctr == (clk_div - 8'd2)); - wire send_clk_lo = (clk_ctr == (clk_div - 8'd1)); - - wire send_bit = (bit_ready && (bit_ctr != 0)); - assign ready = (bit_ctr == 0); - - always @(posedge clk) - if(rst) - clk_ctr <= 0; - else if(bit_done) - clk_ctr <= 0; - else if(bit_busy) - clk_ctr <= clk_ctr + 1; - else if(send_bit) - clk_ctr <= 1; - - always @(posedge clk) - if(rst) - sd_clk <= 0; - else if(send_clk_hi) - sd_clk <= 1; - else if(send_clk_lo) - sd_clk <= 0; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else if(bit_done) - if(bit_ctr == 4'd8) - bit_ctr <= 0; - else - bit_ctr <= bit_ctr + 1; - else if(bit_ready & go) - bit_ctr <= 1; - - reg [7:0] shift_reg; - always @(posedge clk) - if(go) - shift_reg <= send_dat; - else if(latch_dat) - shift_reg <= {shift_reg[6:0],sd_miso}; - - assign sd_mosi = shift_reg[7]; - assign rcv_dat = shift_reg; - -endmodule // sd_spi diff --git a/control_lib/sd_spi_tb.v b/control_lib/sd_spi_tb.v deleted file mode 100644 index e30a5bdf6..000000000 --- a/control_lib/sd_spi_tb.v +++ /dev/null @@ -1,40 +0,0 @@ - - -module sd_spi_tb; - - reg clk = 0; - always #5 clk = ~clk; - reg rst = 1; - initial #32 rst = 0; - - wire sd_clk, sd_mosi, sd_miso; - wire [7:0] clk_div = 12; - wire [7:0] send_dat = 23; - wire [7:0] rcv_dat; - - wire ready; - reg go = 0; - initial - begin - repeat (100) - @(posedge clk); - go <= 1; - @(posedge clk); - go <= 0; - end - - sd_spi dut(.clk(clk),.rst(rst), - .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat), - .go(go),.ready(ready) ); - - initial - begin - $dumpfile("sd_spi_tb.vcd"); - $dumpvars(0,sd_spi_tb); - end - - initial - #10000 $finish(); - -endmodule // sd_spi_tb diff --git a/control_lib/sd_spi_wb.v b/control_lib/sd_spi_wb.v deleted file mode 100644 index 7a6258b56..000000000 --- a/control_lib/sd_spi_wb.v +++ /dev/null @@ -1,76 +0,0 @@ - -// Wishbone module for spi communications with an SD Card -// The programming interface is simple -- -// Write the desired clock divider to address 1 (should be 1 or higher) -// Status is in address 0. A 1 indicates the last transaction is done and it is safe to -// send another -// Writing a byte to address 2 sends that byte over SPI. When it is done, -// status (addr 0) goes high again, and the received byte can be read from address 3. - -module sd_spi_wb - (input clk, - input rst, - - // SD Card interface - output sd_clk, - output sd_csn, - output sd_mosi, - input sd_miso, - - input wb_cyc_i, - input wb_stb_i, - input wb_we_i, - input [1:0] wb_adr_i, - input [7:0] wb_dat_i, - output reg [7:0] wb_dat_o, - output reg wb_ack_o); - - localparam ADDR_STATUS = 0; - localparam ADDR_CLKDIV = 1; - localparam ADDR_WRITE = 2; - localparam ADDR_READ = 3; - - wire [7:0] status, rcv_dat; - reg [7:0] clkdiv; - wire ready; - reg ack_d1; - - reg cs_reg; - assign sd_csn = ~cs_reg; // FIXME - - always @(posedge clk) - if(rst) ack_d1 <= 0; - else ack_d1 <= wb_ack_o; - - always @(posedge clk) - if(rst) wb_ack_o <= 0; - else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1; - - always @(posedge clk) - case(wb_adr_i) - ADDR_STATUS : wb_dat_o <= {7'd0,ready}; - ADDR_CLKDIV : wb_dat_o <= clkdiv; - ADDR_READ : wb_dat_o <= rcv_dat; - default : wb_dat_o <= 0; - endcase // case(wb_adr_i) - - always @(posedge clk) - if(rst) - begin - clkdiv <= 200; - cs_reg <= 0; - end - else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o) - case(wb_adr_i) - ADDR_STATUS : cs_reg <= wb_dat_i; - ADDR_CLKDIV : clkdiv <= wb_dat_i; - endcase // case(wb_adr_i) - - wire go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE); - - sd_spi sd_spi(.clk(clk),.rst(rst), - .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat), - .go(go),.ready(ready) ); - -endmodule // sd_spi_wb diff --git a/control_lib/setting_reg.v b/control_lib/setting_reg.v deleted file mode 100644 index ccbaa3d2e..000000000 --- a/control_lib/setting_reg.v +++ /dev/null @@ -1,23 +0,0 @@ - - -module setting_reg - #(parameter my_addr = 0) - (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); - - always @(posedge clk) - if(rst) - begin - out <= 32'd0; - changed <= 1'b0; - end - else - if(strobe & (my_addr==addr)) - begin - out <= in; - changed <= 1'b1; - end - else - changed <= 1'b0; - -endmodule // setting_reg diff --git a/control_lib/settings_bus.v b/control_lib/settings_bus.v deleted file mode 100644 index d01a30ab4..000000000 --- a/control_lib/settings_bus.v +++ /dev/null @@ -1,49 +0,0 @@ - -// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock - -module settings_bus - #(parameter AWIDTH=16, parameter DWIDTH=32) - (input wb_clk, - input wb_rst, - input [AWIDTH-1:0] wb_adr_i, - input [DWIDTH-1:0] wb_dat_i, - input wb_stb_i, - input wb_we_i, - output reg wb_ack_o, - input sys_clk, - output strobe, - output reg [7:0] addr, - output reg [31:0] data); - - reg stb_int, stb_int_d1; - - always @(posedge wb_clk) - if(wb_rst) - begin - stb_int <= 1'b0; - addr <= 8'd0; - data <= 32'd0; - end - else if(wb_we_i & wb_stb_i) - begin - stb_int <= 1'b1; - addr <= wb_adr_i[9:2]; - data <= wb_dat_i; - end - else - stb_int <= 1'b0; - - always @(posedge wb_clk) - if(wb_rst) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - - always @(posedge wb_clk) - stb_int_d1 <= stb_int; - - //assign strobe = stb_int & ~stb_int_d1; - assign strobe = stb_int & wb_ack_o; - -endmodule // settings_bus - diff --git a/control_lib/shortfifo.v b/control_lib/shortfifo.v deleted file mode 100644 index d8ce1428e..000000000 --- a/control_lib/shortfifo.v +++ /dev/null @@ -1,87 +0,0 @@ - -module shortfifo - #(parameter WIDTH=32) - (input clk, input rst, - input [WIDTH-1:0] datain, - output [WIDTH-1:0] dataout, - input read, - input write, - input clear, - output reg full, - output reg empty, - output reg [4:0] space, - output reg [4:0] occupied); - - reg [3:0] a; - genvar i; - - generate - for (i=0;i>1); - wire stop_now = (bit_ctr == 10) && shift_now; - wire go_now = (bit_ctr == 0) && neg_trans; - - always @(posedge clk) - if(rst) - sr <= 0; - else if(shift_now) - sr <= {rx_d2,sr[7:1]}; - - always @(posedge clk) - if(rst) - baud_ctr <= 0; - else - if(go_now) - baud_ctr <= 1; - else if(stop_now) - baud_ctr <= 0; - else if(baud_ctr >= clkdiv) - baud_ctr <= 1; - else if(baud_ctr != 0) - baud_ctr <= baud_ctr + 1; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else - if(go_now) - bit_ctr <= 1; - else if(stop_now) - bit_ctr <= 0; - else if(baud_ctr == clkdiv) - bit_ctr <= bit_ctr + 1; - - wire full; - wire write = ~full & rx_d2 & stop_now; - - medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo - (.clk(clk),.rst(rst), - .datain(sr),.write(write),.full(full), - .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty), - .clear(0),.space(),.occupied(fifo_level) ); - -endmodule // simple_uart_rx diff --git a/control_lib/simple_uart_tx.v b/control_lib/simple_uart_tx.v deleted file mode 100644 index e11a347ed..000000000 --- a/control_lib/simple_uart_tx.v +++ /dev/null @@ -1,60 +0,0 @@ - -module simple_uart_tx - #(parameter DEPTH=0) - (input clk, input rst, - input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output fifo_full, - input [15:0] clkdiv, output baudclk, output reg tx); - - reg [15:0] baud_ctr; - reg [3:0] bit_ctr; - - wire read, empty; - wire [7:0] char_to_send; - - medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo - (.clk(clk),.rst(rst), - .datain(fifo_in),.write(fifo_write),.full(fifo_full), - .dataout(char_to_send),.read(read),.empty(empty), - .clear(0),.space(fifo_level),.occupied() ); - - always @(posedge clk) - if(rst) - baud_ctr <= 0; - else if (baud_ctr >= clkdiv) - baud_ctr <= 0; - else - baud_ctr <= baud_ctr + 1; - - always @(posedge clk) - if(rst) - bit_ctr <= 0; - else if(baud_ctr == clkdiv) - if(bit_ctr == 9) - bit_ctr <= 0; - else if(bit_ctr != 0) - bit_ctr <= bit_ctr + 1; - else if(~empty) - bit_ctr <= 1; - - always @(posedge clk) - if(rst) - tx <= 1; - else - case(bit_ctr) - 0 : tx <= 1; - 1 : tx <= 0; - 2 : tx <= char_to_send[0]; - 3 : tx <= char_to_send[1]; - 4 : tx <= char_to_send[2]; - 5 : tx <= char_to_send[3]; - 6 : tx <= char_to_send[4]; - 7 : tx <= char_to_send[5]; - 8 : tx <= char_to_send[6]; - 9 : tx <= char_to_send[7]; - default : tx <= 1; - endcase // case(bit_ctr) - - assign read = (bit_ctr == 9) && (baud_ctr == clkdiv); - assign baudclk = (baud_ctr == 1); // Only for debug purposes - -endmodule // simple_uart_tx diff --git a/control_lib/spi.v b/control_lib/spi.v deleted file mode 100644 index a80c488e9..000000000 --- a/control_lib/spi.v +++ /dev/null @@ -1,84 +0,0 @@ - - -// AD9510 Register Map (from datasheet Rev. A) - -/* INSTRUCTION word format (16 bits) - * 15 Read = 1, Write = 0 - * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream - * 12:0 Address - */ - -/* ADDR Contents Value (hex) - * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate - * 04 A Counter - * 05-06 B Counter - * 07-0A PLL Control - * 0B-0C R Divider - * 0D PLL Control - * 34-3A Fine Delay - * 3C-3F LVPECL Outs - * 40-43 LVDS/CMOS Outs - * 45 Clock select, power down - * 48-57 Dividers - * 58 Func and Sync - * 5A Update regs - */ - - -module spi - (input reset, - input clk, - - // SPI signals - output sen, - output sclk, - input sdi, - output sdo, - - // Interfaces - input read_1, - input write_1, - input [15:0] command_1, - input [15:0] wdata_1, - output [15:0] rdata_1, - output reg done_1, - input msb_first_1, - input [5:0] command_width_1, - input [5:0] data_width_1, - input [7:0] clkdiv_1 - - ); - - reg [15:0] command, wdata, rdata; - reg done; - - always @(posedge clk) - if(reset) - done_1 <= #1 1'b0; - - always @(posedge clk) - if(reset) - begin - counter <= #1 7'd0; - command <= #1 20'd0; - end - else if(start) - begin - counter <= #1 7'd1; - command <= #1 {read,w,addr_data}; - end - else if( |counter && ~done ) - begin - counter <= #1 counter + 7'd1; - if(~counter[0]) - command <= {command[22:0],1'b0}; - end - - wire done = (counter == 8'd49); - - assign sen = (done | counter == 8'd0); // CSB is high when we're not doing anything - assign sclk = ~counter[0]; - assign sdo = command[23]; - - -endmodule // clock_control diff --git a/control_lib/srl.v b/control_lib/srl.v deleted file mode 100644 index fa28c7669..000000000 --- a/control_lib/srl.v +++ /dev/null @@ -1,21 +0,0 @@ - -module srl - #(parameter WIDTH=18) - (input clk, - input write, - input [WIDTH-1:0] in, - input [3:0] addr, - output [WIDTH-1:0] out); - - genvar i; - generate - for (i=0;i 5) - clock_present <= 1; - else - ; - else - if(abs_diff<3) - clock_present <= 0; - else - rd_counter <= rd_counter + 1; - -endmodule // ss_rcvr diff --git a/control_lib/system_control.v b/control_lib/system_control.v deleted file mode 100644 index 5d89f13db..000000000 --- a/control_lib/system_control.v +++ /dev/null @@ -1,47 +0,0 @@ -// System bootup order: -// 0 - Internal POR to reset this block. Maybe control it from CPLD in the future? -// 1 - Everything in reset -// 2 - Take RAM Loader out of reset -// 3 - When RAM Loader done, take processor and wishbone out of reset - -module system_control - (input wb_clk_i, - output reg ram_loader_rst_o, - output reg wb_rst_o, - input ram_loader_done_i - ); - - reg POR = 1'b1; - reg [3:0] POR_ctr; - - initial POR_ctr = 4'd0; - always @(posedge wb_clk_i) - if(POR_ctr == 4'd15) - POR <= 1'b0; - else - POR_ctr <= POR_ctr + 4'd1; - - always @(posedge POR or posedge wb_clk_i) - if(POR) - ram_loader_rst_o <= 1'b1; - else - ram_loader_rst_o <= #1 1'b0; - - // Main system reset - reg delayed_rst; - - always @(posedge POR or posedge wb_clk_i) - if(POR) - begin - wb_rst_o <= 1'b1; - delayed_rst <= 1'b1; - end - else if(ram_loader_done_i) - begin - delayed_rst <= 1'b0; - wb_rst_o <= delayed_rst; - end - -endmodule // system_control - - diff --git a/control_lib/system_control_tb.v b/control_lib/system_control_tb.v deleted file mode 100644 index a8eff4811..000000000 --- a/control_lib/system_control_tb.v +++ /dev/null @@ -1,57 +0,0 @@ - - -module system_control_tb(); - - reg aux_clk, clk_fpga; - wire wb_clk, dsp_clk; - wire wb_rst, dsp_rst, rl_rst, proc_rst; - - reg rl_done, clock_ready; - - initial aux_clk = 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'b0; - - initial clock_ready = 1'b0; - initial - begin - @(negedge proc_rst); - #1003 clock_ready <= 1'b1; - end - - always #7 clk_fpga = ~clk_fpga; - - initial begin - $dumpfile("system_control_tb.vcd"); - $dumpvars(0,system_control_tb); - end - - initial #10000 $finish; - - initial - begin - @(negedge rl_rst); - rl_done <= 1'b0; - #1325 rl_done <= 1'b1; - end - - initial - begin - @(negedge proc_rst); - clock_ready <= 1'b0; - #327 clock_ready <= 1'b1; - end - - system_control - system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga), - .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk), - .ram_loader_rst_o(rl_rst), - .processor_rst_o(proc_rst), - .wb_rst_o(wb_rst), - .dsp_rst_o(dsp_rst), - .ram_loader_done_i(rl_done), - .clock_ready_i(clock_ready), - .debug_o()); - -endmodule // system_control_tb diff --git a/control_lib/traffic_cop.v b/control_lib/traffic_cop.v deleted file mode 100644 index e7579656a..000000000 --- a/control_lib/traffic_cop.v +++ /dev/null @@ -1,25 +0,0 @@ - -module traffic_cop(); - - -endmodule // traffic_cop - - - -/* - - Traffic Cop to control buffer pool - - Inputs - - Commands - - Basic Operations - - Outputs - - - - - - */ diff --git a/control_lib/wb_1master.v b/control_lib/wb_1master.v deleted file mode 100644 index fb313efae..000000000 --- a/control_lib/wb_1master.v +++ /dev/null @@ -1,464 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Connection Bus Top Level //// -//// //// -//// //// -//// Original Author: Johny Chi //// -//// chisuhua@yahoo.com.cn //// -//// Modified By Matt Ettus, matt@ettus.com //// -//// //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// Up to 8 slaves share a Wishbone Bus connection to 1 master - - module wb_1master - #(parameter decode_w = 8, // address decode width - parameter s0_addr = 8'h0, // slave 0 address - parameter s0_mask = 8'h0, // slave 0 don't cares - parameter s1_addr = 8'h0, // slave 1 address - parameter s1_mask = 8'h0, // slave 1 don't cares - parameter s2_addr = 8'h0, // slave 2 address - parameter s2_mask = 8'h0, // slave 2 don't cares - parameter s3_addr = 8'h0, // slave 3 address - parameter s3_mask = 8'h0, // slave 3 don't cares - parameter s4_addr = 8'h0, // slave 4 address - parameter s4_mask = 8'h0, // slave 4 don't cares - parameter s5_addr = 8'h0, // slave 5 address - parameter s5_mask = 8'h0, // slave 5 don't cares - parameter s6_addr = 8'h0, // slave 6 address - parameter s6_mask = 8'h0, // slave 6 don't cares - parameter s7_addr = 8'h0, // slave 7 address - parameter s7_mask = 8'h0, // slave 7 don't cares - parameter s8_addr = 8'h0, // slave 8 address - parameter s8_mask = 8'h0, // slave 8 don't cares - parameter s9_addr = 8'h0, // slave 9 address - parameter s9_mask = 8'h0, // slave 9 don't cares - parameter sa_addr = 8'h0, // slave a address - parameter sa_mask = 8'h0, // slave a don't cares - parameter sb_addr = 8'h0, // slave b address - parameter sb_mask = 8'h0, // slave b don't cares - parameter sc_addr = 8'h0, // slave c address - parameter sc_mask = 8'h0, // slave c don't cares - parameter sd_addr = 8'h0, // slave d address - parameter sd_mask = 8'h0, // slave d don't cares - parameter se_addr = 8'h0, // slave e address - parameter se_mask = 8'h0, // slave e don't cares - parameter sf_addr = 8'h0, // slave f address - parameter sf_mask = 8'h0, // slave f don't cares - - parameter dw = 32, // Data bus Width - parameter aw = 32, // Address bus Width - parameter sw = 4) // Number of Select Lines - - (input clk_i, - input rst_i, - - // Master Interface - input [dw-1:0] m0_dat_i, - output [dw-1:0] m0_dat_o, - input [aw-1:0] m0_adr_i, - input [sw-1:0] m0_sel_i, - input m0_we_i, - input m0_cyc_i, - input m0_stb_i, - output m0_ack_o, - output m0_err_o, - output m0_rty_o, - - // Slave Interfaces - input [dw-1:0] s0_dat_i, - output [dw-1:0] s0_dat_o, - output [aw-1:0] s0_adr_o, - output [sw-1:0] s0_sel_o, - output s0_we_o, - output s0_cyc_o, - output s0_stb_o, - input s0_ack_i, - input s0_err_i, - input s0_rty_i, - - input [dw-1:0] s1_dat_i, - output [dw-1:0] s1_dat_o, - output [aw-1:0] s1_adr_o, - output [sw-1:0] s1_sel_o, - output s1_we_o, - output s1_cyc_o, - output s1_stb_o, - input s1_ack_i, - input s1_err_i, - input s1_rty_i, - - input [dw-1:0] s2_dat_i, - output [dw-1:0] s2_dat_o, - output [aw-1:0] s2_adr_o, - output [sw-1:0] s2_sel_o, - output s2_we_o, - output s2_cyc_o, - output s2_stb_o, - input s2_ack_i, - input s2_err_i, - input s2_rty_i, - - input [dw-1:0] s3_dat_i, - output [dw-1:0] s3_dat_o, - output [aw-1:0] s3_adr_o, - output [sw-1:0] s3_sel_o, - output s3_we_o, - output s3_cyc_o, - output s3_stb_o, - input s3_ack_i, - input s3_err_i, - input s3_rty_i, - - input [dw-1:0] s4_dat_i, - output [dw-1:0] s4_dat_o, - output [aw-1:0] s4_adr_o, - output [sw-1:0] s4_sel_o, - output s4_we_o, - output s4_cyc_o, - output s4_stb_o, - input s4_ack_i, - input s4_err_i, - input s4_rty_i, - - input [dw-1:0] s5_dat_i, - output [dw-1:0] s5_dat_o, - output [aw-1:0] s5_adr_o, - output [sw-1:0] s5_sel_o, - output s5_we_o, - output s5_cyc_o, - output s5_stb_o, - input s5_ack_i, - input s5_err_i, - input s5_rty_i, - - input [dw-1:0] s6_dat_i, - output [dw-1:0] s6_dat_o, - output [aw-1:0] s6_adr_o, - output [sw-1:0] s6_sel_o, - output s6_we_o, - output s6_cyc_o, - output s6_stb_o, - input s6_ack_i, - input s6_err_i, - input s6_rty_i, - - input [dw-1:0] s7_dat_i, - output [dw-1:0] s7_dat_o, - output [aw-1:0] s7_adr_o, - output [sw-1:0] s7_sel_o, - output s7_we_o, - output s7_cyc_o, - output s7_stb_o, - input s7_ack_i, - input s7_err_i, - input s7_rty_i, - - input [dw-1:0] s8_dat_i, - output [dw-1:0] s8_dat_o, - output [aw-1:0] s8_adr_o, - output [sw-1:0] s8_sel_o, - output s8_we_o, - output s8_cyc_o, - output s8_stb_o, - input s8_ack_i, - input s8_err_i, - input s8_rty_i, - - input [dw-1:0] s9_dat_i, - output [dw-1:0] s9_dat_o, - output [aw-1:0] s9_adr_o, - output [sw-1:0] s9_sel_o, - output s9_we_o, - output s9_cyc_o, - output s9_stb_o, - input s9_ack_i, - input s9_err_i, - input s9_rty_i, - - input [dw-1:0] sa_dat_i, - output [dw-1:0] sa_dat_o, - output [aw-1:0] sa_adr_o, - output [sw-1:0] sa_sel_o, - output sa_we_o, - output sa_cyc_o, - output sa_stb_o, - input sa_ack_i, - input sa_err_i, - input sa_rty_i, - - input [dw-1:0] sb_dat_i, - output [dw-1:0] sb_dat_o, - output [aw-1:0] sb_adr_o, - output [sw-1:0] sb_sel_o, - output sb_we_o, - output sb_cyc_o, - output sb_stb_o, - input sb_ack_i, - input sb_err_i, - input sb_rty_i, - - input [dw-1:0] sc_dat_i, - output [dw-1:0] sc_dat_o, - output [aw-1:0] sc_adr_o, - output [sw-1:0] sc_sel_o, - output sc_we_o, - output sc_cyc_o, - output sc_stb_o, - input sc_ack_i, - input sc_err_i, - input sc_rty_i, - - input [dw-1:0] sd_dat_i, - output [dw-1:0] sd_dat_o, - output [aw-1:0] sd_adr_o, - output [sw-1:0] sd_sel_o, - output sd_we_o, - output sd_cyc_o, - output sd_stb_o, - input sd_ack_i, - input sd_err_i, - input sd_rty_i, - - input [dw-1:0] se_dat_i, - output [dw-1:0] se_dat_o, - output [aw-1:0] se_adr_o, - output [sw-1:0] se_sel_o, - output se_we_o, - output se_cyc_o, - output se_stb_o, - input se_ack_i, - input se_err_i, - input se_rty_i, - - input [dw-1:0] sf_dat_i, - output [dw-1:0] sf_dat_o, - output [aw-1:0] sf_adr_o, - output [sw-1:0] sf_sel_o, - output sf_we_o, - output sf_cyc_o, - output sf_stb_o, - input sf_ack_i, - input sf_err_i, - input sf_rty_i - ); - - // //////////////////////////////////////////////////////////////// - // - // Local wires - // - - wire [15:0] ssel_dec; - reg [dw-1:0] i_dat_s; // internal share bus , slave data to master - - // Master output Interface - assign m0_dat_o = i_dat_s; - - always @* - case(ssel_dec) - 1 : i_dat_s <= s0_dat_i; - 2 : i_dat_s <= s1_dat_i; - 4 : i_dat_s <= s2_dat_i; - 8 : i_dat_s <= s3_dat_i; - 16 : i_dat_s <= s4_dat_i; - 32 : i_dat_s <= s5_dat_i; - 64 : i_dat_s <= s6_dat_i; - 128 : i_dat_s <= s7_dat_i; - 256 : i_dat_s <= s8_dat_i; - 512 : i_dat_s <= s9_dat_i; - 1024 : i_dat_s <= sa_dat_i; - 2048 : i_dat_s <= sb_dat_i; - 4096 : i_dat_s <= sc_dat_i; - 8192 : i_dat_s <= sd_dat_i; - 16384 : i_dat_s <= se_dat_i; - 32768 : i_dat_s <= sf_dat_i; - default : i_dat_s <= s0_dat_i; - endcase // case(ssel_dec) - - assign {m0_ack_o, m0_err_o, m0_rty_o} - = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i | - s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i , - s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i | - s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i , - s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i | - s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i }; - - // Slave output interfaces - assign s0_adr_o = m0_adr_i; - assign s0_sel_o = m0_sel_i; - assign s0_dat_o = m0_dat_i; - assign s0_we_o = m0_we_i; - assign s0_cyc_o = m0_cyc_i; - assign s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0]; - - assign s1_adr_o = m0_adr_i; - assign s1_sel_o = m0_sel_i; - assign s1_dat_o = m0_dat_i; - assign s1_we_o = m0_we_i; - assign s1_cyc_o = m0_cyc_i; - assign s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1]; - - assign s2_adr_o = m0_adr_i; - assign s2_sel_o = m0_sel_i; - assign s2_dat_o = m0_dat_i; - assign s2_we_o = m0_we_i; - assign s2_cyc_o = m0_cyc_i; - assign s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2]; - - assign s3_adr_o = m0_adr_i; - assign s3_sel_o = m0_sel_i; - assign s3_dat_o = m0_dat_i; - assign s3_we_o = m0_we_i; - assign s3_cyc_o = m0_cyc_i; - assign s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3]; - - assign s4_adr_o = m0_adr_i; - assign s4_sel_o = m0_sel_i; - assign s4_dat_o = m0_dat_i; - assign s4_we_o = m0_we_i; - assign s4_cyc_o = m0_cyc_i; - assign s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4]; - - assign s5_adr_o = m0_adr_i; - assign s5_sel_o = m0_sel_i; - assign s5_dat_o = m0_dat_i; - assign s5_we_o = m0_we_i; - assign s5_cyc_o = m0_cyc_i; - assign s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5]; - - assign s6_adr_o = m0_adr_i; - assign s6_sel_o = m0_sel_i; - assign s6_dat_o = m0_dat_i; - assign s6_we_o = m0_we_i; - assign s6_cyc_o = m0_cyc_i; - assign s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6]; - - assign s7_adr_o = m0_adr_i; - assign s7_sel_o = m0_sel_i; - assign s7_dat_o = m0_dat_i; - assign s7_we_o = m0_we_i; - assign s7_cyc_o = m0_cyc_i; - assign s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7]; - - assign s8_adr_o = m0_adr_i; - assign s8_sel_o = m0_sel_i; - assign s8_dat_o = m0_dat_i; - assign s8_we_o = m0_we_i; - assign s8_cyc_o = m0_cyc_i; - assign s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8]; - - assign s9_adr_o = m0_adr_i; - assign s9_sel_o = m0_sel_i; - assign s9_dat_o = m0_dat_i; - assign s9_we_o = m0_we_i; - assign s9_cyc_o = m0_cyc_i; - assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9]; - - assign sa_adr_o = m0_adr_i; - assign sa_sel_o = m0_sel_i; - assign sa_dat_o = m0_dat_i; - assign sa_we_o = m0_we_i; - assign sa_cyc_o = m0_cyc_i; - assign sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10]; - - assign sb_adr_o = m0_adr_i; - assign sb_sel_o = m0_sel_i; - assign sb_dat_o = m0_dat_i; - assign sb_we_o = m0_we_i; - assign sb_cyc_o = m0_cyc_i; - assign sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11]; - - assign sc_adr_o = m0_adr_i; - assign sc_sel_o = m0_sel_i; - assign sc_dat_o = m0_dat_i; - assign sc_we_o = m0_we_i; - assign sc_cyc_o = m0_cyc_i; - assign sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12]; - - assign sd_adr_o = m0_adr_i; - assign sd_sel_o = m0_sel_i; - assign sd_dat_o = m0_dat_i; - assign sd_we_o = m0_we_i; - assign sd_cyc_o = m0_cyc_i; - assign sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13]; - - assign se_adr_o = m0_adr_i; - assign se_sel_o = m0_sel_i; - assign se_dat_o = m0_dat_i; - assign se_we_o = m0_we_i; - assign se_cyc_o = m0_cyc_i; - assign se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14]; - - assign sf_adr_o = m0_adr_i; - assign sf_sel_o = m0_sel_i; - assign sf_dat_o = m0_dat_i; - assign sf_we_o = m0_we_i; - assign sf_cyc_o = m0_cyc_i; - assign sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15]; - - // Address decode logic - // WARNING -- must make sure these are mutually exclusive! - - - assign ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask); - assign ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask); - assign ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask); - assign ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask); - assign ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask); - assign ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask); - assign ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask); - assign ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask); - assign ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask); - assign ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask); - assign ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask); - assign ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask); - assign ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask); - assign ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask); - assign ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask); - assign ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask); - -/* - assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr); - assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr); - assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr); - assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr); - assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr); - assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr); - assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr); - assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr); - assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr); - assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr); - assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr); - assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr); - assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr); - assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr); - assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr); - assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr); - */ -endmodule // wb_1master diff --git a/control_lib/wb_bridge_16_32.v b/control_lib/wb_bridge_16_32.v deleted file mode 100644 index 405e25c3c..000000000 --- a/control_lib/wb_bridge_16_32.v +++ /dev/null @@ -1,36 +0,0 @@ - - -module wb_bridge_16_32 - #(parameter AWIDTH=16) - (input wb_clk, input wb_rst, - input A_cyc_i, input A_stb_i, input A_we_i, input [3:0] A_sel_i, - input [AWIDTH-1:0] A_adr_i, input [31:0] A_dat_i, output [31:0] A_dat_o, output A_ack_o, - output B_cyc_o, output B_stb_o, output B_we_o, output [1:0] B_sel_o, - output [AWIDTH-1:0] B_adr_o, output [15:0] B_dat_o, input [15:0] B_dat_i, input B_ack_i - ); - - reg [15:0] holding; - reg phase; - - assign B_adr_o = {A_adr_i[AWIDTH-1:2],phase,1'b0}; - assign B_cyc_o = A_cyc_i; - assign B_stb_o = A_stb_i; - assign B_we_o = A_we_i; - - assign B_dat_o = ~phase ? A_dat_i[15:0] : A_dat_i[31:16]; - assign B_sel_o = ~phase ? A_sel_i[1:0] : A_sel_i[3:2]; - - assign A_dat_o = {B_dat_i,holding}; - assign A_ack_o = phase & B_ack_i; - - always @(posedge wb_clk) - if(wb_rst) - phase <= 0; - else if(B_ack_i) - phase <= ~phase; - - always @(posedge wb_clk) - if(~phase & B_ack_i) - holding <= B_dat_i; - -endmodule // wb_bridge_16_32 diff --git a/control_lib/wb_bus_writer.v b/control_lib/wb_bus_writer.v deleted file mode 100644 index fc148a0ff..000000000 --- a/control_lib/wb_bus_writer.v +++ /dev/null @@ -1,57 +0,0 @@ - -// wb_bus_writer -// -// WB Bus Master device to send a sequence of single-word transactions -// based on a list in a RAM or ROM (FASM interface) -// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]} -// continues until it gets an all-1s entry - -module wb_bus_writer (input start, - output done, - output reg [15:0] rom_addr, - input [47:0] rom_data, - // WB Master Interface, don't need wb_dat_i - input wb_clk_i, - input wb_rst_i, - output [31:0] wb_dat_o, - input wb_ack_i, - output [15:0] wb_adr_o, - output wb_cyc_o, - output [3:0] wb_sel_o, - output wb_stb_o, - output wb_we_o - ); - -`define IDLE 0 -`define READ 1 - - reg [3:0] state; - - assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s - - always @(posedge wb_clk_i) - if(wb_rst_i) - begin - rom_addr <= #1 0; - state <= #1 0; - end - else if(start) - begin - rom_addr <= #1 0; - state <= #1 `READ; - end - else if((state == `READ) && wb_ack_i) - if(done) - state <= #1 `IDLE; - else - rom_addr <= #1 rom_addr + 1; - - assign wb_dat_o = rom_data[31:0]; - assign wb_adr_o = rom_data[47:32]; - assign wb_sel_o = 4'b1111; // All writes are the full 32 bits - - assign wb_cyc_o = !done & (state != `IDLE); - assign wb_stb_o = !done & (state != `IDLE); - assign wb_we_o = !done & (state != `IDLE); - -endmodule // wb_bus_writer diff --git a/control_lib/wb_output_pins32.v b/control_lib/wb_output_pins32.v deleted file mode 100644 index 1517f2066..000000000 --- a/control_lib/wb_output_pins32.v +++ /dev/null @@ -1,49 +0,0 @@ - - -// Simple 32-bit Wishbone compatible slave output port -// with 8-bit granularity, modeled after the one in the spec -// Allows for readback -// Assumes a 32-bit wishbone bus -// Lowest order bits get sel[0] -// - -module wb_output_pins32 - (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o, - wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i, - port_output); - - input wb_rst_i; - input wb_clk_i; - input wire [31:0] wb_dat_i; - output wire [31:0] wb_dat_o; - input wb_we_i; - input wire [3:0] wb_sel_i; - input wb_stb_i; - output wb_ack_o; - input wb_cyc_i; - - output wire [31:0] port_output; - - reg [31:0] internal_reg; - - always @(posedge wb_clk_i) - if(wb_rst_i) - internal_reg <= #1 32'b0; - else - begin - if(wb_stb_i & wb_we_i & wb_sel_i[0]) - internal_reg[7:0] <= #1 wb_dat_i[7:0]; - if(wb_stb_i & wb_we_i & wb_sel_i[1]) - internal_reg[15:8] <= #1 wb_dat_i[15:8]; - if(wb_stb_i & wb_we_i & wb_sel_i[2]) - internal_reg[23:16] <= #1 wb_dat_i[23:16]; - if(wb_stb_i & wb_we_i & wb_sel_i[3]) - internal_reg[31:24] <= #1 wb_dat_i[31:24]; - end // else: !if(wb_rst_i) - - assign wb_dat_o = internal_reg; - assign port_output = internal_reg; - assign wb_ack_o = wb_stb_i; - -endmodule // wb_output_pins32 - diff --git a/control_lib/wb_ram_block.v b/control_lib/wb_ram_block.v deleted file mode 100644 index 044d34ca4..000000000 --- a/control_lib/wb_ram_block.v +++ /dev/null @@ -1,36 +0,0 @@ - - -// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency -// These have to be a multiple of 512 lines (2K) long - -module wb_ram_block - #(parameter AWIDTH=9) - (input clk_i, - input stb_i, - input we_i, - input [AWIDTH-1:0] adr_i, - input [31:0] dat_i, - output reg [31:0] dat_o, - output ack_o); - - reg [31:0] distram [0:1<<(AWIDTH-1)]; - - always @(posedge clk_i) - begin - if(stb_i & we_i) - distram[adr_i] <= dat_i; - dat_o <= distram[adr_i]; - end - - reg stb_d1, ack_d1; - always @(posedge clk_i) - stb_d1 <= stb_i; - - always @(posedge clk_i) - ack_d1 <= ack_o; - - assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1)); -endmodule // wb_ram_block - - - diff --git a/control_lib/wb_ram_dist.v b/control_lib/wb_ram_dist.v deleted file mode 100644 index cffc2f423..000000000 --- a/control_lib/wb_ram_dist.v +++ /dev/null @@ -1,33 +0,0 @@ - - -module wb_ram_dist - #(parameter AWIDTH=8) - (input clk_i, - input stb_i, - input we_i, - input [AWIDTH-1:0] adr_i, - input [31:0] dat_i, - input [3:0] sel_i, - output [31:0] dat_o, - output ack_o); - - reg [31:0] distram [0:1<<(AWIDTH-1)]; - - always @(posedge clk_i) - begin - if(stb_i & we_i & sel_i[3]) - distram[adr_i][31:24] <= dat_i[31:24]; - if(stb_i & we_i & sel_i[2]) - distram[adr_i][24:16] <= dat_i[24:16]; - if(stb_i & we_i & sel_i[1]) - distram[adr_i][15:8] <= dat_i[15:8]; - if(stb_i & we_i & sel_i[0]) - distram[adr_i][7:0] <= dat_i[7:0]; - end // always @ (posedge clk_i) - - assign dat_o = distram[adr_i]; - assign ack_o = stb_i; - -endmodule // wb_ram_dist - - diff --git a/control_lib/wb_readback_mux.v b/control_lib/wb_readback_mux.v deleted file mode 100644 index 3922b03e3..000000000 --- a/control_lib/wb_readback_mux.v +++ /dev/null @@ -1,60 +0,0 @@ - - -// Note -- clocks must be synchronous (derived from the same source) -// Assumes alt_clk is running at a multiple of wb_clk - -module wb_readback_mux - (input wb_clk_i, - input wb_rst_i, - input wb_stb_i, - input [15:0] wb_adr_i, - output reg [31:0] wb_dat_o, - output reg wb_ack_o, - - input [31:0] word00, - input [31:0] word01, - input [31:0] word02, - input [31:0] word03, - input [31:0] word04, - input [31:0] word05, - input [31:0] word06, - input [31:0] word07, - input [31:0] word08, - input [31:0] word09, - input [31:0] word10, - input [31:0] word11, - input [31:0] word12, - input [31:0] word13, - input [31:0] word14, - input [31:0] word15 - ); - - always @(posedge wb_clk_i) - if(wb_rst_i) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - - always @(posedge wb_clk_i) - case(wb_adr_i[5:2]) - 0 : wb_dat_o <= word00; - 1 : wb_dat_o <= word01; - 2 : wb_dat_o <= word02; - 3 : wb_dat_o <= word03; - 4 : wb_dat_o <= word04; - 5 : wb_dat_o <= word05; - 6 : wb_dat_o <= word06; - 7 : wb_dat_o <= word07; - 8 : wb_dat_o <= word08; - 9 : wb_dat_o <= word09; - 10: wb_dat_o <= word10; - 11: wb_dat_o <= word11; - 12: wb_dat_o <= word12; - 13: wb_dat_o <= word13; - 14: wb_dat_o <= word14; - 15: wb_dat_o <= word15; - endcase // case(addr_reg[3:0]) - -endmodule // wb_readback_mux - - diff --git a/control_lib/wb_regfile_2clock.v b/control_lib/wb_regfile_2clock.v deleted file mode 100644 index e248e5161..000000000 --- a/control_lib/wb_regfile_2clock.v +++ /dev/null @@ -1,107 +0,0 @@ - -module wb_regfile_2clock - (input wb_clk_i, - input wb_rst_i, - input wb_stb_i, - input wb_we_i, - input [15:0] wb_adr_i, - input [3:0] wb_sel_i, - input [31:0] wb_dat_i, - output [31:0] wb_dat_o, - output wb_ack_o, - input alt_clk, - input alt_rst, - - output reg [31:0] reg00, - output reg [31:0] reg01, - output reg [31:0] reg02, - output reg [31:0] reg03, - output reg [31:0] reg04, - output reg [31:0] reg05, - output reg [31:0] reg06, - output reg [31:0] reg07 - ); - - reg [15:0] addr_reg; - reg [3:0] sel_reg; - reg [31:0] dat_reg; - reg wr_ret1, wr_ret2, we_reg, stb_reg; - - always @(posedge wb_clk_i) - if(wb_rst_i) - begin - addr_reg <= 0; - sel_reg <= 0; - dat_reg <= 0; - end - else if(wb_stb_i & wb_we_i) - begin - addr_reg <= wb_adr_i; - sel_reg <= wb_sel_i; - dat_reg <= wb_dat_i; - end - - always @(posedge wb_clk_i) - if(wb_rst_i) - {we_reg,stb_reg} <= 2'b0; - else - {we_reg,stb_reg} <= {wb_we_i,wb_stb_i}; - - assign wb_ack_o = stb_reg; - - always @(posedge alt_clk) - if(alt_rst) - {wr_ret2, wr_ret1} <= 2'b0; - else - {wr_ret2, wr_ret1} <= {wr_ret1, we_reg & stb_reg}; - - always @(posedge alt_clk) - if(alt_rst) - begin - reg00 <= 0; - reg01 <= 0; - reg02 <= 0; - reg03 <= 0; - reg04 <= 0; - reg05 <= 0; - reg06 <= 0; - reg07 <= 0; - end // if (alt_rst) - else if(wr_ret2) - case(addr_reg[4:2]) - 3'd0: reg00 <= { {sel_reg[3] ? dat_reg[31:24] : reg00[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg00[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg00[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg00[7:0]}}; - 3'd1: reg01 <= { {sel_reg[3] ? dat_reg[31:24] : reg01[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg01[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg01[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg01[7:0]}}; - 3'd2: reg02 <= { {sel_reg[3] ? dat_reg[31:24] : reg02[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg02[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg02[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg02[7:0]}}; - 3'd3: reg03 <= { {sel_reg[3] ? dat_reg[31:24] : reg03[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg03[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg03[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg03[7:0]}}; - 3'd4: reg04 <= { {sel_reg[3] ? dat_reg[31:24] : reg04[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg04[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg04[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg04[7:0]}}; - 3'd5: reg05 <= { {sel_reg[3] ? dat_reg[31:24] : reg05[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg05[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg05[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg05[7:0]}}; - 3'd6: reg06 <= { {sel_reg[3] ? dat_reg[31:24] : reg06[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg06[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg06[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg06[7:0]}}; - 3'd7: reg07 <= { {sel_reg[3] ? dat_reg[31:24] : reg07[31:24]}, - {sel_reg[2] ? dat_reg[23:16] : reg07[23:16]}, - {sel_reg[1] ? dat_reg[15:8] : reg07[15:8]}, - {sel_reg[0] ? dat_reg[7:0] : reg07[7:0]}}; - endcase // case(addr_reg[2:0]) - -endmodule // wb_regfile_2clock - diff --git a/control_lib/wb_semaphore.v b/control_lib/wb_semaphore.v deleted file mode 100644 index a9208e6a1..000000000 --- a/control_lib/wb_semaphore.v +++ /dev/null @@ -1,42 +0,0 @@ - -// up to 8 semaphores - -// After a read operation, the semaphore is always locked -// If it was already locked before the read (meaning someone else holds the lock) -// then a 1 is returned -// If it was not already locked (meaning the reader now holds the lock) -// then a 0 is returned - -// A write operation clears the lock - -module wb_semaphore - #(parameter count=8, DBUS_WIDTH=32) - (input wb_clk_i, - input wb_rst_i, - input [DBUS_WIDTH-1:0] wb_dat_i, - input [2:0] wb_adr_i, - input wb_cyc_i, - input wb_stb_i, - input wb_we_i, - output wb_ack_o, - output [DBUS_WIDTH-1:0] wb_dat_o); - - reg [count-1:0] locked; - - always @(posedge clock) - if(wb_rst_i) - locked <= {count{1'b0}}; - else if(wb_stb_i) - if(wb_we_i) - locked[adr_i] <= 1'b0; - else - locked[adr_i] <= 1'b1; - - assign wb_dat_o[DBUS_WIDTH-1:1] = {(DBUS_WIDTH-1){1'b0}}; - assign wb_dat_o[0] = locked[adr_i]; - assign wb_ack_o = wb_stb_i; - - -endmodule // wb_semaphore - - diff --git a/control_lib/wb_sim.v b/control_lib/wb_sim.v deleted file mode 100644 index b324e1457..000000000 --- a/control_lib/wb_sim.v +++ /dev/null @@ -1,79 +0,0 @@ - - -module wb_sim(); - - wire wb_clk, wb_rst; - wire start; - - reg POR, aux_clk, clk_fpga; - - initial POR = 1'b1; - initial #103 POR = 1'b0; - - initial aux_clk = 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #7 clk_fpga = ~clk_fpga; - - initial begin - $dumpfile("wb_sim.vcd"); - $dumpvars(0,wb_sim); - end - - initial #10000 $finish; - - wire [15:0] rom_addr; - wire [47:0] rom_data; - wire [31:0] wb_dat; - wire [15:0] wb_adr; - wire wb_cyc,wb_stb,wb_we,wb_ack; - wire [3:0] wb_sel; - - wire [31:0] port_output; - - - system_control system_control(.dsp_clk(dsp_clk), - .reset_out(reset_out), - .wb_clk_o(wb_clk), - .wb_rst_o(wb_rst), - .wb_rst_o_alt(wb_rst_o_alt), - .start (start), - .aux_clk(aux_clk), - .clk_fpga(clk_fpga), - .POR (POR), - .done (done)); - - clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data)); - - wb_bus_writer bus_writer(.rom_addr (rom_addr[15:0]), - .wb_dat_o (wb_dat[31:0]), - .wb_adr_o (wb_adr[15:0]), - .wb_cyc_o (wb_cyc), - .wb_sel_o (wb_sel[3:0]), - .wb_stb_o (wb_stb), - .wb_we_o (wb_we), - .start (start), - .done (done), - .rom_data (rom_data[47:0]), - .wb_clk_i (wb_clk), - .wb_rst_i (wb_rst), - .wb_ack_i (wb_ack)); - - wb_output_pins32 output_pins(.wb_dat_o(), - .wb_ack_o(wb_ack), - .port_output(port_output[31:0]), - .wb_rst_i(wb_rst), - .wb_clk_i(wb_clk), - .wb_dat_i(wb_dat[31:0]), - .wb_we_i(wb_we), - .wb_sel_i(wb_sel[3:0]), - .wb_stb_i(wb_stb), - .wb_cyc_i(wb_cyc)); - - - - -endmodule // wb_sim - diff --git a/coregen/.gitignore b/coregen/.gitignore deleted file mode 100644 index 956cab52b..000000000 --- a/coregen/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/xlnx_auto* -/*log -/tmp diff --git a/coregen/coregen.cgp b/coregen/coregen.cgp deleted file mode 100644 index 810d64dac..000000000 --- a/coregen/coregen.cgp +++ /dev/null @@ -1,20 +0,0 @@ -# Date: Thu Sep 3 17:40:48 2009 -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/matt/coregen/tmp - diff --git a/coregen/fifo_generator_release_notes.txt b/coregen/fifo_generator_release_notes.txt deleted file mode 100644 index 554ec87f4..000000000 --- a/coregen/fifo_generator_release_notes.txt +++ /dev/null @@ -1,160 +0,0 @@ -COPYRIGHT (c) 2006, 2007 XILINX, INC. -ALL RIGHTS RESERVED - -Core name : FIFO Generator -Version : v4.1 -Release Date : August 8, 2007 -File : fifo_generator_release_notes.txt - -Revision History -Date By Version Change Description -======================================================================== -09/2006 Xilinx, Inc. 3.2 Initial creation. -02/2007 Xilinx, Inc. 3.3 Revised for v3.3. -02/2007 Xilinx, Inc. 3.3 Revised for v3.3 rev 1. -08/2007 Xilinx, Inc. 3.4 Revised for v4.1. -======================================================================== - -INTRODUCTION -RELEASE NOTES - 1. General Core Design - 1.1 Enhancements - 1.2 Resolved Issues - 1.3 Outstanding Issues - 2. General Simulation - 2.1 Enhancements - 2.2 Resolved Issues - 2.3 Outstanding Issues - 3. Documentation - 3.1 Enhancements - 3.2 Resolved Issues - 3.3 Outstanding Issues -OTHER GENERAL INFORMATION -TECHNICAL SUPPORT - -======================================================================== - -INTRODUCTION -============ -Thank you using the FIFO Generator core from Xilinx! -In order to obtain the latest core updates and documentation, -please visit the Intellectual Property page located at: -http://www.xilinx.com/ipcenter/index.htm -This document contains the release notes for FIFO Generator v4.1 -which includes enhancements, resolved issues and outstanding known -issues. For release notes and known issues for CORE Generator 9.2i IP -Update 1 and FIFO Generator v4.1 please see Answer Record 25222. - -RELEASE NOTES -============= -This section lists any enhancements, resolved issues and outstanding -known issues. - - -1. General Core Design - 1.1 Enhancements - 1.1.1 Error Correction Checking (ECC) feature support for - Virtex-5 block RAM FIFO configurations - - 1.1.2 Full range data count widths now supported for non-symmetric - aspect ratio configurations - - 1.1.3 Option to define asynchronous reset value for full condition - flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM, - distributed RAM and shift RAM-based FIFO configurations only - - 1.1.4 Support added for use embedded output registers in block RAM - FIFO configurations (Virtex-4 and Virtex-5 only) - - 1.2 Resolved Issues - 1.2.1 Coregen GUI - For built-in FIFOs, GUI reports incorrect - number of built-in FIFO primitives used. - Change request: 4433738 - - 1.2.2 Programmable full flag is always asserted even when FIFO is - empty due to incorrect threshold setting. - Change request: 435835 - - 1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol - .. , these pins should be connected to the same signal" occur - during MAP when targeting Virtex-4 and Virtex-5. - Change request: 338260 - - 1.2.4 Write Data Count and Read Data Count overestimate the number - of words written or read when core is configured with this - combination of options: First-Word-Fall-Through(FWFT), - accurate data count using extra logic, non-symmetric port - aspect ratio. - Change request: 436886 - - 1.2.5 SBITERR and DBITERR outputs are not driven in behavior - models. - Change request: 433637 - - 1.2.6 Maximum programmable empty threshold negate value is - incorrect. - Change request: 433921 - - 1.2.7 Programmable full flag behavior is incorrect when the - core is configured with this combination of options: - FWFT, non-symmetric port aspect ratio, single or - multiple programmable full threshold input port. - Change request: 435874 - - 1.2.8 Programmable empty flag stuck high when the core is - configured with this combination of options: block or - distributed RAM FIFO, single or multiple programmable - empty threshold input port. - Change request: 443569 - - 1.3 Outstanding Issues - 1.3.1 "WARNING:Ngdbuild:452 - logical net - 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during - NgdBuild although programmable empty or full is not selected. - Warnings can be safely ignored. - Change request: 431975 - -2. General Simulation - 2.1 Enhancements - None at this time. - - 2.2 Resolved Issues - None at this time. - - 2.3 Outstanding Issues - 2.3.1 Ncelab warnings during Verilog structural and timing simulations - in ncsim for Virtex5 Block RAM FIFOs. - The simulations will be successful, but there will be warnings - similar to the following in the log file: "memory index out of - declared bounds" in simprims_ver_virtex5_source.v or - unisims_ver_virtex5_source.v. Cadence does not want to fix this - issue. These warning messages can safely be ignored. - Change request: 423374, 423375 - -3. Documentation - 3.1 Enhancements - 3.1.1 Added clarification on FIFO flag latency. - - 3.1.1 Added clarification on actual FIFO depth. - - 3.2 Resolved Issues - None at this time. - - 3.3 Outstanding Issues - None at this time. - - -TECHNICAL SUPPORT -================= -The fastest method for obtaining specific technical support for the -FIFO Generator core is through the http://support.xilinx.com/ -website. Questions are routed to a team of engineers with specific -expertise in using the FIFO Generator core. Xilinx will provide -technical support for use of this product as described in the FIFO -Generator Datasheet. Xilinx cannot guarantee timing, functionality, -or support of this product for designs that do not follow these -guidelines. - - - - diff --git a/coregen/fifo_generator_ug175.pdf b/coregen/fifo_generator_ug175.pdf deleted file mode 100644 index 2c3e3c200..000000000 Binary files a/coregen/fifo_generator_ug175.pdf and /dev/null differ diff --git a/coregen/fifo_xlnx_16x19_2clk.ngc b/coregen/fifo_xlnx_16x19_2clk.ngc deleted file mode 100644 index b12d34d7c..000000000 --- a/coregen/fifo_xlnx_16x19_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$3f24g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/coregen/fifo_xlnx_16x19_2clk.v b/coregen/fifo_xlnx_16x19_2clk.v deleted file mode 100644 index 1d633384b..000000000 --- a/coregen/fifo_xlnx_16x19_2clk.v +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating -// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_16x19_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [18 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [18 : 0] dout; -output empty; -output full; -output [4 : 0] rd_data_count; -output [4 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(5), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(19), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(19), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(2), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(15), - .C_PROG_FULL_THRESH_NEGATE_VAL(14), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(5), - .C_RD_DEPTH(16), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(4), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(5), - .C_WR_DEPTH(16), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(4), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/coregen/fifo_xlnx_16x19_2clk.veo b/coregen/fifo_xlnx_16x19_2clk.veo deleted file mode 100644 index 2e9af1efa..000000000 --- a/coregen/fifo_xlnx_16x19_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_16x19_2clk YourInstanceName ( - .din(din), // Bus [18 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [18 : 0] - .empty(empty), - .full(full), - .rd_data_count(rd_data_count), // Bus [4 : 0] - .wr_data_count(wr_data_count)); // Bus [4 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating -// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/coregen/fifo_xlnx_16x19_2clk.xco b/coregen/fifo_xlnx_16x19_2clk.xco deleted file mode 100644 index d0f638026..000000000 --- a/coregen/fifo_xlnx_16x19_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Fri Sep 11 04:33:27 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_16x19_2clk -CSET data_count=false -CSET data_count_width=5 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=15 -CSET full_threshold_negate_value=14 -CSET input_data_width=19 -CSET input_depth=16 -CSET output_data_width=19 -CSET output_depth=16 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=5 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=5 -# END Parameters -GENERATE -# CRC: 60b85dda - diff --git a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index ef33fff67..000000000 --- a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - -
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- - - diff --git a/coregen/fifo_xlnx_16x19_2clk_flist.txt b/coregen/fifo_xlnx_16x19_2clk_flist.txt deleted file mode 100644 index 5e1a6ed35..000000000 --- a/coregen/fifo_xlnx_16x19_2clk_flist.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Output products list for -fifo_xlnx_16x19_2clk.ngc -fifo_xlnx_16x19_2clk.v -fifo_xlnx_16x19_2clk.veo -fifo_xlnx_16x19_2clk.xco -fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_16x19_2clk_flist.txt -fifo_xlnx_16x19_2clk_xmdf.tcl diff --git a/coregen/fifo_xlnx_16x19_2clk_readme.txt b/coregen/fifo_xlnx_16x19_2clk_readme.txt deleted file mode 100644 index 1b5976555..000000000 --- a/coregen/fifo_xlnx_16x19_2clk_readme.txt +++ /dev/null @@ -1,39 +0,0 @@ -The following files were generated for 'fifo_xlnx_16x19_2clk' in directory -/home/matt/gnuradio.git/usrp2/fpga/coregen/: - -fifo_xlnx_16x19_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_16x19_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_16x19_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_16x19_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_16x19_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_16x19_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_16x19_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl deleted file mode 100644 index 8d633e9c2..000000000 --- a/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_16x19_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_16x19_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x19_2clk -} -# ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x19_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/fifo_xlnx_2Kx36_2clk.asy b/coregen/fifo_xlnx_2Kx36_2clk.asy deleted file mode 100644 index a87aa2f84..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk.asy +++ /dev/null @@ -1,49 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 fifo_xlnx_2Kx36_2clk -RECTANGLE Normal 32 32 544 672 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName din[35:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName wr_en -PINATTR Polarity IN -LINE Normal 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName wr_clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 0 240 LEFT 36 -PINATTR PinName rd_en -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName rd_clk -PINATTR Polarity IN -LINE Normal 144 704 144 672 -PIN 144 704 BOTTOM 36 -PINATTR PinName rst -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName dout[35:0] -PINATTR Polarity OUT -LINE Normal 576 208 544 208 -PIN 576 208 RIGHT 36 -PINATTR PinName full -PINATTR Polarity OUT -LINE Wide 576 368 544 368 -PIN 576 368 RIGHT 36 -PINATTR PinName wr_data_count[11:0] -PINATTR Polarity OUT -LINE Normal 576 432 544 432 -PIN 576 432 RIGHT 36 -PINATTR PinName empty -PINATTR Polarity OUT -LINE Wide 576 592 544 592 -PIN 576 592 RIGHT 36 -PINATTR PinName rd_data_count[11:0] -PINATTR Polarity OUT - diff --git a/coregen/fifo_xlnx_2Kx36_2clk.ngc b/coregen/fifo_xlnx_2Kx36_2clk.ngc deleted file mode 100644 index 684eb74f4..000000000 --- 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\ No newline at end of file diff --git a/coregen/fifo_xlnx_2Kx36_2clk.sym b/coregen/fifo_xlnx_2Kx36_2clk.sym deleted file mode 100644 index 5d56b5c98..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk.sym +++ /dev/null @@ -1,74 +0,0 @@ -VERSION 5 -BEGIN SYMBOL fifo_xlnx_2Kx36_2clk -SYMBOLTYPE BLOCK -TIMESTAMP 2009 9 3 17 25 13 -SYMPIN 0 80 Input din[35:0] -SYMPIN 0 144 Input wr_en -SYMPIN 0 176 Input wr_clk -SYMPIN 0 240 Input rd_en -SYMPIN 0 272 Input rd_clk -SYMPIN 144 704 Input rst -SYMPIN 576 80 Output dout[35:0] -SYMPIN 576 208 Output full -SYMPIN 576 368 Output wr_data_count[11:0] -SYMPIN 576 432 Output empty -SYMPIN 576 592 Output rd_data_count[11:0] -BEGIN DISPLAY 32 32 TEXT fifo_xlnx_2Kx36_2clk - FONT 40 "Arial" -END DISPLAY -RECTANGLE N 32 32 544 672 -BEGIN LINE W 0 80 32 80 -END LINE -BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 144 32 144 -BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 176 32 176 -BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 240 32 240 -BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 272 32 272 -BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 144 704 144 672 -BEGIN DISPLAY 144 668 PIN rst ATTR PinName - ALIGNMENT BCENTER - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 80 544 80 -END LINE -BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -LINE N 576 208 544 208 -BEGIN DISPLAY 540 208 PIN full ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 368 544 368 -END LINE -BEGIN DISPLAY 540 368 PIN wr_data_count[11:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -LINE N 576 432 544 432 -BEGIN DISPLAY 540 432 PIN empty ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 592 544 592 -END LINE -BEGIN DISPLAY 540 592 PIN rd_data_count[11:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -END SYMBOL diff --git a/coregen/fifo_xlnx_2Kx36_2clk.v b/coregen/fifo_xlnx_2Kx36_2clk.v deleted file mode 100644 index 0762b3ae9..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk.v +++ /dev/null @@ -1,173 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating -// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_2Kx36_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [35 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [35 : 0] dout; -output empty; -output full; -output [11 : 0] rd_data_count; -output [11 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(12), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("2kx18"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(2047), - .C_PROG_FULL_THRESH_NEGATE_VAL(2046), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(12), - .C_RD_DEPTH(2048), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(11), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(12), - .C_WR_DEPTH(2048), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(11), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box" - -endmodule - diff --git a/coregen/fifo_xlnx_2Kx36_2clk.veo b/coregen/fifo_xlnx_2Kx36_2clk.veo deleted file mode 100644 index af9191555..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_2Kx36_2clk YourInstanceName ( - .din(din), // Bus [35 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [35 : 0] - .empty(empty), - .full(full), - .rd_data_count(rd_data_count), // Bus [11 : 0] - .wr_data_count(wr_data_count)); // Bus [11 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating -// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/coregen/fifo_xlnx_2Kx36_2clk.vhd b/coregen/fifo_xlnx_2Kx36_2clk.vhd deleted file mode 100644 index 53033dc97..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk.vhd +++ /dev/null @@ -1,156 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating --- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synthesis translate_off -Library XilinxCoreLib; --- synthesis translate_on -ENTITY fifo_xlnx_2Kx36_2clk IS - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(11 downto 0); - wr_data_count: OUT std_logic_VECTOR(11 downto 0)); -END fifo_xlnx_2Kx36_2clk; - -ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS --- synthesis translate_off -component wrapped_fifo_xlnx_2Kx36_2clk - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(11 downto 0); - wr_data_count: OUT std_logic_VECTOR(11 downto 0)); -end component; - --- Configuration specification - for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) - generic map( - c_has_int_clk => 0, - c_rd_freq => 1, - c_wr_response_latency => 1, - c_has_srst => 0, - c_has_rd_data_count => 1, - c_din_width => 36, - c_has_wr_data_count => 1, - c_full_flags_rst_val => 1, - c_implementation_type => 2, - c_family => "spartan3", - c_use_embedded_reg => 0, - c_has_wr_rst => 0, - c_wr_freq => 1, - c_use_dout_rst => 1, - c_underflow_low => 0, - c_has_meminit_file => 0, - c_has_overflow => 0, - c_preload_latency => 0, - c_dout_width => 36, - c_msgon_val => 1, - c_rd_depth => 2048, - c_default_value => "BlankString", - c_mif_file_name => "BlankString", - c_has_underflow => 0, - c_has_rd_rst => 0, - c_has_almost_full => 0, - c_has_rst => 1, - c_data_count_width => 12, - c_has_wr_ack => 0, - c_use_ecc => 0, - c_wr_ack_low => 0, - c_common_clock => 0, - c_rd_pntr_width => 11, - c_use_fwft_data_count => 1, - c_has_almost_empty => 0, - c_rd_data_count_width => 12, - c_enable_rlocs => 0, - c_wr_pntr_width => 11, - c_overflow_low => 0, - c_prog_empty_type => 0, - c_optimization_mode => 0, - c_wr_data_count_width => 12, - c_preload_regs => 1, - c_dout_rst_val => "0", - c_has_data_count => 0, - c_prog_full_thresh_negate_val => 2046, - c_wr_depth => 2048, - c_prog_empty_thresh_negate_val => 5, - c_prog_empty_thresh_assert_val => 4, - c_has_valid => 0, - c_init_wr_pntr_val => 0, - c_prog_full_thresh_assert_val => 2047, - c_use_fifo16_flags => 0, - c_has_backup => 0, - c_valid_low => 0, - c_prim_fifo_type => "2kx18", - c_count_type => 0, - c_prog_full_type => 0, - c_memory_type => 1); --- synthesis translate_on -BEGIN --- synthesis translate_off -U0 : wrapped_fifo_xlnx_2Kx36_2clk - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- synthesis translate_on - -END fifo_xlnx_2Kx36_2clk_a; - diff --git a/coregen/fifo_xlnx_2Kx36_2clk.vho b/coregen/fifo_xlnx_2Kx36_2clk.vho deleted file mode 100644 index 5165b0bc4..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk.vho +++ /dev/null @@ -1,76 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- The following code must appear in the VHDL architecture header: - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -component fifo_xlnx_2Kx36_2clk - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(11 downto 0); - wr_data_count: OUT std_logic_VECTOR(11 downto 0)); -end component; - --- Synplicity black box declaration -attribute syn_black_box : boolean; -attribute syn_black_box of fifo_xlnx_2Kx36_2clk: component is true; - --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : fifo_xlnx_2Kx36_2clk - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- INST_TAG_END ------ End INSTANTIATION Template ------------ - --- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating --- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - diff --git a/coregen/fifo_xlnx_2Kx36_2clk.xco b/coregen/fifo_xlnx_2Kx36_2clk.xco deleted file mode 100644 index e25ad38da..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Thu Sep 3 17:25:43 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = VHDL -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = True -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_2Kx36_2clk -CSET data_count=false -CSET data_count_width=12 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=2047 -CSET full_threshold_negate_value=2046 -CSET input_data_width=36 -CSET input_depth=2048 -CSET output_data_width=36 -CSET output_depth=2048 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=12 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=12 -# END Parameters -GENERATE -# CRC: 2ae9f6ef - diff --git a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index 5108be2c5..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,106 +0,0 @@ - - - - - - -
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- - - diff --git a/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/coregen/fifo_xlnx_2Kx36_2clk_flist.txt deleted file mode 100644 index 670d84713..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk_flist.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Output products list for -fifo_xlnx_2Kx36_2clk.asy -fifo_xlnx_2Kx36_2clk.ngc -fifo_xlnx_2Kx36_2clk.sym -fifo_xlnx_2Kx36_2clk.v -fifo_xlnx_2Kx36_2clk.veo -fifo_xlnx_2Kx36_2clk.vhd -fifo_xlnx_2Kx36_2clk.vho -fifo_xlnx_2Kx36_2clk.xco -fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_2Kx36_2clk_flist.txt -fifo_xlnx_2Kx36_2clk_xmdf.tcl diff --git a/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/coregen/fifo_xlnx_2Kx36_2clk_readme.txt deleted file mode 100644 index 1879503a9..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk_readme.txt +++ /dev/null @@ -1,55 +0,0 @@ -The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory -/home/matt/gnuradio.git/usrp2/fpga/coregen/: - -fifo_xlnx_2Kx36_2clk.asy: - Graphical symbol information file. Used by the ISE tools and some - third party tools to create a symbol representing the core. - -fifo_xlnx_2Kx36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_2Kx36_2clk.sym: - Please see the core data sheet. - -fifo_xlnx_2Kx36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_2Kx36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_2Kx36_2clk.vhd: - VHDL wrapper file provided to support functional simulation. This - file contains simulation model customization data that is passed to - a parameterized simulation model for the core. - -fifo_xlnx_2Kx36_2clk.vho: - VHO template file containing code that can be used as a model for - instantiating a CORE Generator module in a VHDL design. - -fifo_xlnx_2Kx36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_2Kx36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_2Kx36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_2Kx36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl deleted file mode 100644 index cac25efd2..000000000 --- a/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl +++ /dev/null @@ -1,84 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_2Kx36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_2Kx36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_2Kx36_2clk -} -# ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.sym -utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vho -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_2Kx36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/fifo_xlnx_512x36_2clk.asy b/coregen/fifo_xlnx_512x36_2clk.asy deleted file mode 100644 index ecc80b648..000000000 --- a/coregen/fifo_xlnx_512x36_2clk.asy +++ /dev/null @@ -1,49 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk -RECTANGLE Normal 32 32 544 672 -LINE Wide 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName din[35:0] -PINATTR Polarity IN -LINE Normal 0 144 32 144 -PIN 0 144 LEFT 36 -PINATTR PinName wr_en -PINATTR Polarity IN -LINE Normal 0 176 32 176 -PIN 0 176 LEFT 36 -PINATTR PinName wr_clk -PINATTR Polarity IN -LINE Normal 0 240 32 240 -PIN 0 240 LEFT 36 -PINATTR PinName rd_en -PINATTR Polarity IN -LINE Normal 0 272 32 272 -PIN 0 272 LEFT 36 -PINATTR PinName rd_clk -PINATTR Polarity IN -LINE Normal 144 704 144 672 -PIN 144 704 BOTTOM 36 -PINATTR PinName rst -PINATTR Polarity IN -LINE Wide 576 80 544 80 -PIN 576 80 RIGHT 36 -PINATTR PinName dout[35:0] -PINATTR Polarity OUT -LINE Normal 576 208 544 208 -PIN 576 208 RIGHT 36 -PINATTR PinName full -PINATTR Polarity OUT -LINE Wide 576 368 544 368 -PIN 576 368 RIGHT 36 -PINATTR PinName wr_data_count[8:0] -PINATTR Polarity OUT -LINE Normal 576 432 544 432 -PIN 576 432 RIGHT 36 -PINATTR PinName empty -PINATTR Polarity OUT -LINE Wide 576 592 544 592 -PIN 576 592 RIGHT 36 -PINATTR PinName rd_data_count[8:0] -PINATTR Polarity OUT - diff --git a/coregen/fifo_xlnx_512x36_2clk.ngc b/coregen/fifo_xlnx_512x36_2clk.ngc deleted file mode 100644 index 55486485a..000000000 --- a/coregen/fifo_xlnx_512x36_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$4g64g<,[o}e~g`n;"2*413&;$>"9 > %17?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/coregen/fifo_xlnx_512x36_2clk.sym b/coregen/fifo_xlnx_512x36_2clk.sym deleted file mode 100644 index 13e8af33d..000000000 --- a/coregen/fifo_xlnx_512x36_2clk.sym +++ /dev/null @@ -1,74 +0,0 @@ -VERSION 5 -BEGIN SYMBOL fifo_xlnx_512x36_2clk -SYMBOLTYPE BLOCK -TIMESTAMP 2008 7 28 22 45 53 -SYMPIN 0 80 Input din[35:0] -SYMPIN 0 144 Input wr_en -SYMPIN 0 176 Input wr_clk -SYMPIN 0 240 Input rd_en -SYMPIN 0 272 Input rd_clk -SYMPIN 144 704 Input rst -SYMPIN 576 80 Output dout[35:0] -SYMPIN 576 208 Output full -SYMPIN 576 368 Output wr_data_count[8:0] -SYMPIN 576 432 Output empty -SYMPIN 576 592 Output rd_data_count[8:0] -BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk - FONT 40 "Arial" -END DISPLAY -RECTANGLE N 32 32 544 672 -BEGIN LINE W 0 80 32 80 -END LINE -BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 144 32 144 -BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 176 32 176 -BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 240 32 240 -BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 0 272 32 272 -BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName - FONT 24 "Arial" -END DISPLAY -LINE N 144 704 144 672 -BEGIN DISPLAY 144 668 PIN rst ATTR PinName - ALIGNMENT BCENTER - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 80 544 80 -END LINE -BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -LINE N 576 208 544 208 -BEGIN DISPLAY 540 208 PIN full ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 368 544 368 -END LINE -BEGIN DISPLAY 540 368 PIN wr_data_count[8:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -LINE N 576 432 544 432 -BEGIN DISPLAY 540 432 PIN empty ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -BEGIN LINE W 576 592 544 592 -END LINE -BEGIN DISPLAY 540 592 PIN rd_data_count[8:0] ATTR PinName - ALIGNMENT RIGHT - FONT 24 "Arial" -END DISPLAY -END SYMBOL diff --git a/coregen/fifo_xlnx_512x36_2clk.v b/coregen/fifo_xlnx_512x36_2clk.v deleted file mode 100644 index 905069743..000000000 --- a/coregen/fifo_xlnx_512x36_2clk.v +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating -// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_512x36_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [35 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [35 : 0] dout; -output empty; -output full; -output [9 : 0] rd_data_count; -output [9 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(10), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(511), - .C_PROG_FULL_THRESH_NEGATE_VAL(510), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(10), - .C_RD_DEPTH(512), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(9), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(10), - .C_WR_DEPTH(512), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(9), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/coregen/fifo_xlnx_512x36_2clk.veo b/coregen/fifo_xlnx_512x36_2clk.veo deleted file mode 100644 index 6699ee73b..000000000 --- a/coregen/fifo_xlnx_512x36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_512x36_2clk YourInstanceName ( - .din(din), // Bus [35 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [35 : 0] - .empty(empty), - .full(full), - .rd_data_count(rd_data_count), // Bus [9 : 0] - .wr_data_count(wr_data_count)); // Bus [9 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating -// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/coregen/fifo_xlnx_512x36_2clk.vhd b/coregen/fifo_xlnx_512x36_2clk.vhd deleted file mode 100644 index d9c2dd307..000000000 --- a/coregen/fifo_xlnx_512x36_2clk.vhd +++ /dev/null @@ -1,156 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating --- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synthesis translate_off -Library XilinxCoreLib; --- synthesis translate_on -ENTITY fifo_xlnx_512x36_2clk IS - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(8 downto 0); - wr_data_count: OUT std_logic_VECTOR(8 downto 0)); -END fifo_xlnx_512x36_2clk; - -ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS --- synthesis translate_off -component wrapped_fifo_xlnx_512x36_2clk - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(8 downto 0); - wr_data_count: OUT std_logic_VECTOR(8 downto 0)); -end component; - --- Configuration specification - for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) - generic map( - c_has_int_clk => 0, - c_rd_freq => 1, - c_wr_response_latency => 1, - c_has_srst => 0, - c_has_rd_data_count => 1, - c_din_width => 36, - c_has_wr_data_count => 1, - c_full_flags_rst_val => 1, - c_implementation_type => 2, - c_family => "spartan3", - c_use_embedded_reg => 0, - c_has_wr_rst => 0, - c_wr_freq => 1, - c_use_dout_rst => 0, - c_underflow_low => 0, - c_has_meminit_file => 0, - c_has_overflow => 0, - c_preload_latency => 0, - c_dout_width => 36, - c_msgon_val => 1, - c_rd_depth => 512, - c_default_value => "BlankString", - c_mif_file_name => "BlankString", - c_has_underflow => 0, - c_has_rd_rst => 0, - c_has_almost_full => 0, - c_has_rst => 1, - c_data_count_width => 9, - c_has_wr_ack => 0, - c_use_ecc => 0, - c_wr_ack_low => 0, - c_common_clock => 0, - c_rd_pntr_width => 9, - c_use_fwft_data_count => 0, - c_has_almost_empty => 0, - c_rd_data_count_width => 9, - c_enable_rlocs => 0, - c_wr_pntr_width => 9, - c_overflow_low => 0, - c_prog_empty_type => 0, - c_optimization_mode => 0, - c_wr_data_count_width => 9, - c_preload_regs => 1, - c_dout_rst_val => "0", - c_has_data_count => 0, - c_prog_full_thresh_negate_val => 510, - c_wr_depth => 512, - c_prog_empty_thresh_negate_val => 5, - c_prog_empty_thresh_assert_val => 4, - c_has_valid => 0, - c_init_wr_pntr_val => 0, - c_prog_full_thresh_assert_val => 511, - c_use_fifo16_flags => 0, - c_has_backup => 0, - c_valid_low => 0, - c_prim_fifo_type => "512x36", - c_count_type => 0, - c_prog_full_type => 0, - c_memory_type => 1); --- synthesis translate_on -BEGIN --- synthesis translate_off -U0 : wrapped_fifo_xlnx_512x36_2clk - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- synthesis translate_on - -END fifo_xlnx_512x36_2clk_a; - diff --git a/coregen/fifo_xlnx_512x36_2clk.vho b/coregen/fifo_xlnx_512x36_2clk.vho deleted file mode 100644 index 70eac27a5..000000000 --- a/coregen/fifo_xlnx_512x36_2clk.vho +++ /dev/null @@ -1,76 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- The following code must appear in the VHDL architecture header: - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -component fifo_xlnx_512x36_2clk - port ( - din: IN std_logic_VECTOR(35 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(35 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(8 downto 0); - wr_data_count: OUT std_logic_VECTOR(8 downto 0)); -end component; - --- Synplicity black box declaration -attribute syn_black_box : boolean; -attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true; - --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : fifo_xlnx_512x36_2clk - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- INST_TAG_END ------ End INSTANTIATION Template ------------ - --- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating --- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - diff --git a/coregen/fifo_xlnx_512x36_2clk.xco b/coregen/fifo_xlnx_512x36_2clk.xco deleted file mode 100644 index 5934ef285..000000000 --- a/coregen/fifo_xlnx_512x36_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Thu Sep 3 17:24:24 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_512x36_2clk -CSET data_count=false -CSET data_count_width=10 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=511 -CSET full_threshold_negate_value=510 -CSET input_data_width=36 -CSET input_depth=512 -CSET output_data_width=36 -CSET output_depth=512 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=10 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=10 -# END Parameters -GENERATE -# CRC: b7f2a9ba - diff --git a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index d110a0158..000000000 --- a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,109 +0,0 @@ - - - - - - -
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- - - diff --git a/coregen/fifo_xlnx_512x36_2clk_flist.txt b/coregen/fifo_xlnx_512x36_2clk_flist.txt deleted file mode 100644 index b0975be2d..000000000 --- a/coregen/fifo_xlnx_512x36_2clk_flist.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Output products list for -fifo_xlnx_512x36_2clk.ngc -fifo_xlnx_512x36_2clk.v -fifo_xlnx_512x36_2clk.veo -fifo_xlnx_512x36_2clk.xco -fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_512x36_2clk_flist.txt -fifo_xlnx_512x36_2clk_xmdf.tcl diff --git a/coregen/fifo_xlnx_512x36_2clk_readme.txt b/coregen/fifo_xlnx_512x36_2clk_readme.txt deleted file mode 100644 index a250a74f5..000000000 --- a/coregen/fifo_xlnx_512x36_2clk_readme.txt +++ /dev/null @@ -1,39 +0,0 @@ -The following files were generated for 'fifo_xlnx_512x36_2clk' in directory -/home/matt/gnuradio.git/usrp2/fpga/coregen/: - -fifo_xlnx_512x36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_512x36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_512x36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_512x36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_512x36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_512x36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_512x36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl deleted file mode 100644 index 8a0c0e3ff..000000000 --- a/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_512x36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_512x36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk -} -# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/fifo_xlnx_64x36_2clk.ngc b/coregen/fifo_xlnx_64x36_2clk.ngc deleted file mode 100644 index e8c55a1af..000000000 --- a/coregen/fifo_xlnx_64x36_2clk.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$4;14g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/coregen/fifo_xlnx_64x36_2clk.v b/coregen/fifo_xlnx_64x36_2clk.v deleted file mode 100644 index e84237689..000000000 --- a/coregen/fifo_xlnx_64x36_2clk.v +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating -// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module fifo_xlnx_64x36_2clk( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [35 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [35 : 0] dout; -output empty; -output full; -output [6 : 0] rd_data_count; -output [6 : 0] wr_data_count; - -// synthesis translate_off - - FIFO_GENERATOR_V4_3 #( - .C_COMMON_CLOCK(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(7), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(36), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(36), - .C_ENABLE_RLOCS(0), - .C_FAMILY("spartan3"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(1), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(1), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(2), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(2), - .C_MIF_FILE_NAME("BlankString"), - .C_MSGON_VAL(1), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(0), - .C_PRELOAD_REGS(1), - .C_PRIM_FIFO_TYPE("512x36"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(63), - .C_PROG_FULL_THRESH_NEGATE_VAL(62), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(7), - .C_RD_DEPTH(64), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(6), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(1), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(7), - .C_WR_DEPTH(64), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(6), - .C_WR_RESPONSE_LATENCY(1)) - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .INT_CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .SRST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK(), - .SBITERR(), - .DBITERR()); - - -// synthesis translate_on - -endmodule - diff --git a/coregen/fifo_xlnx_64x36_2clk.veo b/coregen/fifo_xlnx_64x36_2clk.veo deleted file mode 100644 index 9c761370c..000000000 --- a/coregen/fifo_xlnx_64x36_2clk.veo +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -fifo_xlnx_64x36_2clk YourInstanceName ( - .din(din), // Bus [35 : 0] - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .dout(dout), // Bus [35 : 0] - .empty(empty), - .full(full), - .rd_data_count(rd_data_count), // Bus [6 : 0] - .wr_data_count(wr_data_count)); // Bus [6 : 0] - -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating -// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - diff --git a/coregen/fifo_xlnx_64x36_2clk.xco b/coregen/fifo_xlnx_64x36_2clk.xco deleted file mode 100644 index c6e9aae27..000000000 --- a/coregen/fifo_xlnx_64x36_2clk.xco +++ /dev/null @@ -1,82 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Thu Sep 3 17:22:56 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = Verilog -SET device = xc3s2000 -SET devicefamily = spartan3 -SET flowvendor = Other -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.3 -# END Select -# BEGIN Parameters -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=fifo_xlnx_64x36_2clk -CSET data_count=false -CSET data_count_width=7 -CSET disable_timing_violations=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_negate_value=5 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=63 -CSET full_threshold_negate_value=62 -CSET input_data_width=36 -CSET input_depth=64 -CSET output_data_width=36 -CSET output_depth=64 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=true -CSET read_data_count_width=7 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=true -CSET valid_flag=false -CSET valid_sense=Active_High -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=true -CSET write_data_count_width=7 -# END Parameters -GENERATE -# CRC: 2bb925ae - diff --git a/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso b/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso deleted file mode 100644 index f1a6f7899..000000000 --- a/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso +++ /dev/null @@ -1,3 +0,0 @@ -blkmemdp_v6_2 -blk_mem_gen_v2_6 -fifo_generator_v4_3 diff --git a/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index a23402f56..000000000 --- a/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,104 +0,0 @@ - - - - - - -
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- - - -
- - - diff --git a/coregen/fifo_xlnx_64x36_2clk_flist.txt b/coregen/fifo_xlnx_64x36_2clk_flist.txt deleted file mode 100644 index 44e31eb6c..000000000 --- a/coregen/fifo_xlnx_64x36_2clk_flist.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Output products list for -fifo_xlnx_64x36_2clk.ngc -fifo_xlnx_64x36_2clk.v -fifo_xlnx_64x36_2clk.veo -fifo_xlnx_64x36_2clk.xco -fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -fifo_xlnx_64x36_2clk_flist.txt -fifo_xlnx_64x36_2clk_xmdf.tcl diff --git a/coregen/fifo_xlnx_64x36_2clk_readme.txt b/coregen/fifo_xlnx_64x36_2clk_readme.txt deleted file mode 100644 index 7734c0087..000000000 --- a/coregen/fifo_xlnx_64x36_2clk_readme.txt +++ /dev/null @@ -1,39 +0,0 @@ -The following files were generated for 'fifo_xlnx_64x36_2clk' in directory -/home/matt/gnuradio.git/usrp2/fpga/coregen/: - -fifo_xlnx_64x36_2clk.ngc: - Binary Xilinx implementation netlist file containing the information - required to implement the module in a Xilinx (R) FPGA. - -fifo_xlnx_64x36_2clk.v: - Verilog wrapper file provided to support functional simulation. - This file contains simulation model customization data that is - passed to a parameterized simulation model for the core. - -fifo_xlnx_64x36_2clk.veo: - VEO template file containing code that can be used as a model for - instantiating a CORE Generator module in a Verilog design. - -fifo_xlnx_64x36_2clk.xco: - CORE Generator input file containing the parameters used to - regenerate a core. - -fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: - Please see the core data sheet. - -fifo_xlnx_64x36_2clk_flist.txt: - Text file listing all of the output files produced when a customized - core was generated in the CORE Generator. - -fifo_xlnx_64x36_2clk_readme.txt: - Text file indicating the files generated and how they are used. - -fifo_xlnx_64x36_2clk_xmdf.tcl: - ISE Project Navigator interface file. ISE uses this file to determine - how the files output by CORE Generator for the core can be integrated - into your ISE project. - - -Please see the Xilinx CORE Generator online help for further details on -generated files and how to use them. - diff --git a/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl b/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl deleted file mode 100644 index ff5dfd3c2..000000000 --- a/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# The package naming convention is _xmdf -package provide fifo_xlnx_64x36_2clk_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::fifo_xlnx_64x36_2clk_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_64x36_2clk -} -# ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.ngc -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_64x36_2clk -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/extram/.gitignore b/extram/.gitignore deleted file mode 100644 index 7fc71ccb6..000000000 --- a/extram/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/a.out diff --git a/extram/extram_interface.v b/extram/extram_interface.v deleted file mode 100644 index 7554592ba..000000000 --- a/extram/extram_interface.v +++ /dev/null @@ -1,53 +0,0 @@ - -// Temporary buffer pool storage, mostly useful for pre-generated data streams or -// for making more space to juggle packets in case of eth frames coming out of order - -module extram_interface - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - // Buffer pool interfaces - input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o, - input rd_sop_i, input rd_eop_i, - output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o, - input wr_ready_i, input wr_full_i, - - // RAM Interface - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - input RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn ); - - // Command format -- - // Read/_Write , start address[17:0] - wire [18:0] cmd_in; - wire cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd; - wire empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd; - - // Dummy logic - assign RAM_OEn = 1; - - setting_reg #(.my_addr(0)) - sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(cmd_in),.changed(cmd_stb)); - - reg cmd_stb_d1; - always @(posedge clk) cmd_stb_d1 <= cmd_stb; - assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1; - assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1; - - shortfifo #(.WIDTH(19)) wr_cmd_fifo - (.clk(clk),.rst(rst),.clear(1'b0), - .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd), - .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) ); - - shortfifo #(.WIDTH(19)) rd_cmd_fifo - (.clk(clk),.rst(rst),.clear(1'b0), - .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd), - .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) ); - -endmodule // extram_interface diff --git a/extram/extram_wb.v b/extram/extram_wb.v deleted file mode 100644 index c8428783a..000000000 --- a/extram/extram_wb.v +++ /dev/null @@ -1,146 +0,0 @@ - -module extram_wb - #(parameter PAGE_SIZE = 10, - parameter ADDR_WIDTH = 16) - (input clk, input rst, - input wb_clk, input wb_rst, - input cyc_i, input stb_i, - input [ADDR_WIDTH-1:0] adr_i, - input we_i, - input [31:0] dat_i, - output reg [31:0] dat_o, - output reg ack_o, - - inout [17:0] RAM_D, - output [PAGE_SIZE-2:0] RAM_A, - output RAM_CE1n, output RAM_CENn, - output RAM_CLK, output RAM_WEn, - output RAM_OEn, output RAM_LDn ); - - wire read_acc = stb_i & cyc_i & ~we_i; - wire write_acc = stb_i & cyc_i & we_i; - wire acc = stb_i & cyc_i; - - assign RAM_CLK = ~wb_clk; // 50 MHz for now, eventually should be 200 MHz - assign RAM_LDn = 0; // No burst for now - assign RAM_CENn = 0; // Use CE1n as our main CE - - reg [PAGE_SIZE-2:1] RAM_addr_reg; - always @(posedge wb_clk) - if(acc) - RAM_addr_reg[PAGE_SIZE-2:1] <= adr_i[PAGE_SIZE-1:2]; - assign RAM_A[PAGE_SIZE-2:1] = RAM_addr_reg; - - reg [31:0] ram_out; - always @(posedge wb_clk) - if(write_acc) - ram_out <= dat_i; - - // RAM access state machine - localparam RAM_idle = 0; - localparam RAM_read_1 = 1; - localparam RAM_read_2 = 2; - localparam RAM_read_3 = 3; - localparam RAM_read_4 = 4; - localparam RAM_write_1 = 6; - localparam RAM_write_2 = 7; - localparam RAM_write_3 = 8; - localparam RAM_write_4 = 9; - - reg myOE = 0; - reg RAM_OE = 0; - reg RAM_WE = 0; - reg RAM_EN = 0; - reg RAM_A0_reg; - reg [3:0] RAM_state; - - always @(posedge wb_clk) - if(wb_rst) - begin - RAM_state <= RAM_idle; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - else - case(RAM_state) - RAM_idle : - if(read_acc & ~ack_o) - begin - RAM_state <= RAM_read_1; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 0; - end - else if(write_acc & ~ack_o) - begin - RAM_state <= RAM_write_1; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 0; - end - else - begin - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_read_1 : - begin - RAM_state <= RAM_read_2; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 1; - end - RAM_read_2 : - begin - RAM_state <= RAM_read_3; - myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_read_3 : - begin - RAM_state <= RAM_read_4; - myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_read_4 : - begin - RAM_state <= RAM_idle; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_write_1 : - begin - RAM_state <= RAM_write_2; - myOE <= 1; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1; - end - RAM_write_2 : - begin - RAM_state <= RAM_write_3; - myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_write_3 : - begin - RAM_state <= RAM_write_4; - myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_write_4 : - begin - RAM_state <= RAM_idle; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - default : RAM_state <= RAM_idle; - endcase // case(RAM_state) - - assign RAM_A[0] = RAM_A0_reg; - assign RAM_WEn = ~RAM_WE; // ((RAM_state==RAM_write_1)||(RAM_state==RAM_write_2)); - assign RAM_OEn = ~RAM_OE; - assign RAM_CE1n = ~RAM_EN; // Active low (RAM_state != RAM_idle); - - assign RAM_D[17:16] = 2'bzz; - assign RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_2)?ram_out[15:0]:ram_out[31:16]) - : 16'bzzzz_zzzz_zzzz_zzzz; - - always @(posedge wb_clk) - if(RAM_state == RAM_read_3) - dat_o[15:0] <= RAM_D[15:0]; - else - dat_o[31:16] <= RAM_D[15:0]; - - always @(posedge wb_clk) - if(wb_rst) - ack_o <= 0; - else if((RAM_state == RAM_write_4)||(RAM_state == RAM_read_4)) - ack_o <= 1; - else - ack_o <= 0; - -endmodule // extram_wb diff --git a/extram/wb_zbt16_b.v b/extram/wb_zbt16_b.v deleted file mode 100644 index d93e21c99..000000000 --- a/extram/wb_zbt16_b.v +++ /dev/null @@ -1,63 +0,0 @@ - -module wb_zbt16_b - (input clk, - input rst, - // Wishbone bus A, highest priority, with prefetch - input [19:0] wb_adr_i, - input [15:0] wb_dat_i, - output reg [15:0] wb_dat_o, - input [ 1:0] wb_sel_i, - input wb_cyc_i, - input wb_stb_i, - output reg wb_ack_o, - input wb_we_i, - // Memory connection - output sram_clk, - output [18:0] sram_a, - inout [15:0] sram_d, - output sram_we, - output [ 1:0] sram_bw, - output sram_adv, - output sram_ce, - output sram_oe, - output sram_mode, - output sram_zz - ); - - assign sram_clk = ~clk; - //assign sram_oe = 1'b0; - assign sram_ce = 1'b0; - assign sram_adv = 1'b0; - assign sram_mode = 1'b0; - assign sram_zz = 1'b0; - assign sram_bw = 2'b0; - - // need to drive wb_dat_o, wb_ack_o, - // sram_a, sram_d, sram_we - wire myOE; - assign sram_d = myOE ? wb_dat_i : 16'bzzzz; - assign sram_a = wb_adr_i[19:1]; - - reg read_d1, read_d2, read_d3, write_d1, write_d2, write_d3; - wire acc = wb_cyc_i & wb_stb_i; - wire read_acc = wb_cyc_i & wb_stb_i & ~wb_we_i & ~read_d1 & ~read_d2 & ~read_d3; - wire write_acc = wb_cyc_i & wb_stb_i & wb_we_i & ~write_d1 & ~write_d2 & ~write_d3; - - assign sram_we = ~write_acc; - assign sram_oe = ~(read_d2 | read_d3); - assign myOE = write_d1 | write_d2; - wire latch_now = read_d2; - - always @(posedge clk) - if(latch_now) - wb_dat_o <= sram_d; - - always @(posedge clk) wb_ack_o <= read_d2 | write_d2; - always @(posedge clk) read_d1 <= read_acc; - always @(posedge clk) read_d2 <= read_d1; - always @(posedge clk) read_d3 <= read_d2; - always @(posedge clk) write_d1 <= write_acc; - always @(posedge clk) write_d2 <= write_d1; - always @(posedge clk) write_d3 <= write_d2; -endmodule // wb_zbt16_b - diff --git a/models/BUFG.v b/models/BUFG.v deleted file mode 100644 index a935c6285..000000000 --- a/models/BUFG.v +++ /dev/null @@ -1,33 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5 2005/03/14 22:32:51 yanx Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 8.1i (I.13) -// \ \ Description : Xilinx Functional Simulation Library Component -// / / Global Clock Buffer -// /___/ /\ Filename : BUFG.v -// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// End Revision - -`timescale 100 ps / 10 ps - - -module BUFG (O, I); - - output O; - - input I; - - buf B1 (O, I); - - -endmodule - diff --git a/models/CY7C1356C/cy1356.inp b/models/CY7C1356C/cy1356.inp deleted file mode 100644 index a55ffac39..000000000 --- a/models/CY7C1356C/cy1356.inp +++ /dev/null @@ -1,140 +0,0 @@ -/*Address inputs only 0=LOW - "Data is in HEX, four bytes (LSB,MSB)" 1=HIGH - ZZZZZZZZZZZZZZZZ=Tri-state G-WRITE = Global Write - XXXXXXXXXXXXXXXX= Don't care B-WRITE = Byte Write - YYYY=unknown BG-WRITE = BURST GLOBAL WRITE - BB-WRITE = BURST BYTE WRITE - -*/ -// CE3# BW2# ADV/LD# -// CEN# CE2 WE# -// Add IN OUT CE1# BW1# -0000000000000000_XXXXXXXXXXXXXXXX_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 -0000000000000001_XXXXXXXXXXXXXXXX_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 -0000000000000010_0000000000000000_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 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-//************************************************************************ -//************************************************************************ -//** This model is the property of Cypress Semiconductor Corp and is ** -//** protected by the US copyright laws, any unauthorized copying and ** -//** distribution is prohibited. Cypress reserves the right to change ** -//** any of the functional specifications without any prior notice. ** -//** Cypress is not liable for any damages which may result from the ** -//** use of this functional model. ** -//** ** -//** File Name : CY7C1356 ** -//** ** -//** Revision : 1.0 - 08/03/2004 ** -//** ** -//** The timings are to be selected by the user depending upon the ** -//** frequency of operation from the datasheet. ** -//** ** -//** Model : CY7C1356C - NoBL Pipelined SRAM ** -//** Queries : MPD Applications ** -//** Website: www.cypress.com/support ** -//************************************************************************ -//************************************************************************ - -`timescale 1ns / 10ps - -// NOTE : Any setup/hold errors will force input signal to x state -// or if results indeterminant (write addr) core is reset x - -// define fixed values - -`define wordsize (18 -1) // -`define no_words (1048576 -1) // 1M x 18 RAM - -module cy1356 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); - -inout [`wordsize:0] d; -input clk, // clock input (R) - we_b, // byte write enable(L) - adv_lb, // burst(H)/load(L) address - ce1b, // chip enable(L) - ce2, // chip enable(H) - ce3b, // chip enable(L) - oeb, // async output enable(L)(read) - cenb, // clock enable(L) - mode; // interleave(H)/linear(L) burst -input [1:0] bws; // byte write select(L) -input [18:0] a; // address bus - -// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK *** -// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT *** - - -//********************************************************************** -// Timings for 225MHz -//********************************************************************** -`ifdef sb225 - `define teohz #2.8 - `define teolz #0 - `define tchz #2.8 - `define tclz #1.25 - - `define tco #2.8 - `define tdoh #1.25 - `define tas 1.4 - `define tah 0.4 -`endif -//*********************************************************************** -// Timings for 200MHz -//********************************************************************** -`ifdef sb200 - `define teohz #3.2 - `define teolz #0 - `define tchz #3.2 - `define tclz #1.5 - - `define tco #3.2 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 -`endif -//*********************************************************************** - -//********************************************************************** -// This model is configured for 166 MHz Operation (CY7C1356-166). -//********************************************************************** -`ifdef sb166 - `define teohz #3.5 - `define teolz #0 - `define tchz #3.5 - `define tclz #1.5 - - `define tco #3.5 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 -`endif - -reg notifier; // error support reg's -reg noti1_0; -reg noti1_1; -reg noti1_2; -reg noti1_3; -reg noti1_4; -reg noti1_5; -reg noti1_6; -reg noti2; - - -wire chipen; // combined chip enable (high for an active chip) - -reg chipen_d; // _d = delayed -reg chipen_o; // _o = operational = delayed sig or _d sig - -wire writestate; // holds 1 if any of writebus is low -reg writestate_d; -reg writestate_o; - -wire loadcyc; // holds 1 for load cycles (setup and hold checks) -wire writecyc; // holds 1 for write cycles (setup and hold checks) -wire [1:0] bws; // holds the bws values - -wire [1:0] writebusb; // holds the "internal" bws bus based on we_b -reg [1:0] writebusb_d; -reg [1:0] writebusb_o; - -wire [2:0] operation; // holds chipen, adv_ld and writestate -reg [2:0] operation_d; -reg [2:0] operation_o; - -wire [18:0] a; // address input bus -reg [18:0] a_d; -reg [18:0] a_o; - -reg [`wordsize:0] do; // data output reg -reg [`wordsize:0] di; // data input bus -reg [`wordsize:0] dd; // data delayed bus - -wire tristate; // tristate output (on a bytewise basis) when asserted -reg cetri; // register set by chip disable which sets the tristate -reg oetri; // register set by oe which sets the tristate -reg enable; // register to make the ram enabled when equal to 1 -reg [18:0] addreg; // register to hold the input address -reg [`wordsize:0] pipereg; // register for the output data - -reg [`wordsize:0] mem [0:`no_words]; // RAM array - -reg [`wordsize:0] writeword; // temporary holding register for the write data -reg burstinit; // register to hold a[0] for burst type -reg [18:0] i; // temporary register used to write to all mem locs. -reg writetri; // tristate -reg lw, bw; // pipelined write functions -reg we_bl; - - -wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 18'bz ; // data bus - -assign chipen = (adv_lb == 1 ) ? chipen_d : - ~ce1b & ce2 & ~ce3b ; - -assign writestate = ~& writebusb; - -assign operation = {chipen, adv_lb, writestate}; - -assign writebusb[1:0] = ( we_b ==0 & adv_lb ==0) ? bws[1:0]: - ( we_b ==1 & adv_lb ==0) ? 2'b11 : - ( we_bl ==0 & adv_lb ==1) ? bws[1:0]: - ( we_bl ==1 & adv_lb ==1) ? 2'b11 : - 2'bxx ; - -assign loadcyc = chipen & !cenb; - -assign writecyc = writestate_d & enable & ~cenb & chipen; // check - -assign tristate = cetri | writetri | oetri; - -pullup (mode); - -// formers for notices/errors etc -// -//$display("NOTICE : xxx :"); -//$display("WARNING : xxx :"); -//$display("ERROR *** : xxx :"); - - -// initialize the output to be tri-state, ram to be disabled - -initial - begin -// signals - - writetri = 0; - cetri = 1; - enable = 0; - lw = 0; - bw = 0; - -// error signals - - notifier = 0; - noti1_0 = 0; - noti1_1 = 0; - noti1_2 = 0; - noti1_3 = 0; - noti1_4 = 0; - noti1_5 = 0; - noti1_6 = 0; - noti2 = 0; - -end - - - -// asynchronous OE - -always @(oeb) -begin - if (oeb == 1) - oetri <= `teohz 1; - else - oetri <= `teolz 0; -end - -// *** SETUP / HOLD VIOLATIONS *** - -always @(noti2) -begin -$display("NOTICE : 020 : Data bus corruption"); - force d =18'bx; - #1; - release d; -end - -always @(noti1_0) -begin -$display("NOTICE : 010 : Byte write corruption"); - force bws = 2'bx; - #1; - release bws; -end - -always @(noti1_1) -begin -$display("NOTICE : 011 : Byte enable corruption"); - force we_b = 1'bx; - #1; - release we_b; -end - -always @(noti1_2) -begin -$display("NOTICE : 012 : CE1B corruption"); - force ce1b =1'bx; - #1; - release ce1b; -end - -always @(noti1_3) -begin -$display("NOTICE : 013 : CE2 corruption"); - force ce2 =1'bx; - #1; - release ce2; -end - -always @(noti1_4) -begin -$display("NOTICE : 014 : CE3B corruption"); - force ce3b =1'bx; - #1; - release ce3b; -end - -always @(noti1_5) -begin -$display("NOTICE : 015 : CENB corruption"); - force cenb =1'bx; - #1; - release cenb; -end - -always @(noti1_6) -begin -$display("NOTICE : 016 : ADV_LB corruption"); - force adv_lb = 1'bx; - #1; - release adv_lb; -end - -// synchronous functions from clk edge - -always @(posedge clk) -if (!cenb) -begin -#0.01; - // latch conditions on adv_lb - - if (adv_lb) - we_bl <= we_bl; - else - we_bl <= we_b; - - chipen_d <= chipen; - - - chipen_o <= chipen; - writestate_o <= writestate; - writestate_d <= writestate_o; - writebusb_o <= writebusb; - writebusb_d <= writebusb_o; - operation_o <= operation; - a_o <= a; - a_d <= a_o; - di = d; - - // execute previously pipelined fns - - if (lw) begin - loadwrite; - lw =0; - end - - if (bw) begin - burstwrite; - bw =0; - end - - // decode input/piplined state - - casex (operation_o) - 3'b0?? : turnoff; - 3'b101 : setlw; - 3'b111 : setbw; - 3'b100 : loadread; - 3'b110 : burstread; - default : unknown; // output unknown values and display an error message - endcase - - do <= `tco pipereg; - -end - -// *** task section *** - -task read; -begin - if (enable) cetri <= `tclz 0; - writetri <= `tchz 0; - do <= `tdoh 18'hx; - pipereg = mem[addreg]; -end -endtask - -task write; -begin - if (enable) cetri <= `tclz 0; - writeword = mem[addreg]; // set up a word to hold the data for the current location - /* overwrite the current word for the bytes being written to */ - if (!writebusb_d[1]) writeword[17:9] = di[17:9]; - if (!writebusb_d[0]) writeword[8:0] = di[8:0]; - writeword = writeword & writeword; //convert z to x states - mem[addreg] = writeword; // store the new word into the memory location - //writetri <= `tchz 1; // tristate the outputs -end -endtask - -task setlw; -begin - lw =1; - writetri <= `tchz 1; // tristate the outputs -end -endtask - -task setbw; -begin - bw =1; - writetri <= `tchz 1; // tristate the outputs -end -endtask - -task loadread; -begin - burstinit = a_o[0]; - addreg = a_o; - enable = 1; - read; -end -endtask - -task loadwrite; -begin - burstinit = a_d[0]; - addreg = a_d; - enable = 1; - write; -end -endtask - -task burstread; -begin - burst; - read; -end -endtask - -task burstwrite; -begin - burst; - write; -end -endtask - -task unknown; -begin - do = 18'bx; - // $display ("Unknown function: Operation = %b\n", operation); -end -endtask - -task turnoff; -begin - enable = 0; - cetri <= `tchz 1; - pipereg = 18'h0; -end -endtask - -task burst; -begin - if (burstinit == 0 || mode == 0) - begin - case (addreg[1:0]) - 2'b00: addreg[1:0] = 2'b01; - 2'b01: addreg[1:0] = 2'b10; - 2'b10: addreg[1:0] = 2'b11; - 2'b11: addreg[1:0] = 2'b00; - default: addreg[1:0] = 2'bxx; - endcase - end - else - begin - case (addreg[1:0]) - 2'b00: addreg[1:0] = 2'b11; - 2'b01: addreg[1:0] = 2'b00; - 2'b10: addreg[1:0] = 2'b01; - 2'b11: addreg[1:0] = 2'b10; - default: addreg[1:0] = 2'bxx; - endcase - end -end -endtask - -// IO checks - -specify -// specify the setup and hold checks - -// notifier will wipe memory as result is indeterminent - -$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier); - -// noti1 should make ip = 'bx; - -$setuphold(posedge clk, bws, `tas, `tah, noti1_0); - -$setuphold(posedge clk, we_b, `tas, `tah, noti1_1); -$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2); -$setuphold(posedge clk, ce2, `tas, `tah, noti1_3); -$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4); - -// noti2 should make d = 18'hxxxxx; - -$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2); - -// add extra tests here. - -$setuphold(posedge clk, cenb, `tas, `tah, noti1_5); -$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6); - -endspecify - -endmodule - - diff --git a/models/CY7C1356C/readme.txt b/models/CY7C1356C/readme.txt deleted file mode 100644 index 3578c80dc..000000000 --- a/models/CY7C1356C/readme.txt +++ /dev/null @@ -1,33 +0,0 @@ -*************************** -Cypress Semiconductor -MPD Applications -Verilog model for NoBL SRAM CY7C1356 -Created: August 04, 2004 -Rev: 1.0 -*************************** - -This is the verilog model for the CY7C1356 along with the testbench and test vectors. - -Contact support@cypress.com if you have any questions. - -This directory has 4 files. including this readme. - -1)cy7c1356c.v -> Verilog model for CY7C1356c - -2)cy1356.inp -> Test Vector File used for testing the verilog model - -3)testbench.v -> Test bench used for testing the verilog model - - -COMPILING METHOD : ------------------- - - verilog +define+
- - Ex: - verilog +define+sb133 CY7C1356c.v testbench.v - -VERIFIED WITH: --------------- - -VERILOG-XL 2.2 \ No newline at end of file diff --git a/models/CY7C1356C/testbench.v b/models/CY7C1356C/testbench.v deleted file mode 100644 index 5dde89e6c..000000000 --- a/models/CY7C1356C/testbench.v +++ /dev/null @@ -1,189 +0,0 @@ -`timescale 1ns / 10ps - - -// -// CY7C1356 -// Simulatiom of Verilog model -// -// - -// -// test bench for US vector input -// -// - -// define speed 166MHz - -`define tx10 #6 -`define tx08 #4.8 -`define tx05 #3 -`define tx04 #2.4 -`define tx02 #1.2 - -/* -`define tx10 #4.0 // period -`define tx08 #3.2 //0.8 period -`define tx05 #2.0 //0.5 period 250MHZ -`define tx04 #1.6 //0.4 period -`define tx02 #0.8 //0.2 period - -`define tx10 #4.4 // period -`define tx08 #3.52 //0.8 period -`define tx05 #2.2 //0.5 period 225MHZ -`define tx04 #1.76 //0.4 period -`define tx02 #0.88 //0.2 period - -`define tx10 #5 // period -`define tx08 #4 //0.8 period -`define tx05 #2.5 //0.5 period 200MHZ -`define tx04 #2.0 //0.4 period -`define tx02 #1.0 //0.2 period -*/ - - -module rw_test; - -`define num_vectors 126 -`define impi {a[15:0],io[15:0],tsti[15:0],cenb,ce1b,ce2,ce3b,bweb,bwb,adv_lb} - - -reg [57:1] lsim_vectors [1:`num_vectors]; - - -reg clk; -reg adv_lb; -reg ce1b; //cs1b -reg ce2; //cs2 -reg ce3b; //cs3b -reg [1:0] bwb; -reg bweb; -reg oeb; -reg ftb; -reg mode; //lbob -reg cenb; //zz -reg tp42; //sclk -reg tp39; //se -reg tp38; //tm -reg [19:0] a; -reg [17:0] io; -reg [17:0] tsti; -reg vddq; -reg vssqr; -reg iosel; - - -wire [17:0] d = iosel ? io[17:0] : 18'bz; - -reg noti3; -reg strb,j; -integer vector,i; - - - -cy1356 testram ( d, clk, a, bwb, bweb, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); - -initial -begin - $dumpfile("dumpfile.dump"); - $dumpvars(0,rw_test); -end - -initial -begin -io = 18'bz; -ftb = 1; -oeb = 0; -a[19:16] = 4'h0; -mode = 0; -strb = 0; -tp38 = 0; -tp39 = 0; -tp42 = 0; -`tx02; -forever `tx05 strb = ~strb; -end - -initial -begin -clk = 0; -forever `tx05 clk =~clk; -end - -initial - begin - - $readmemb("cy1356.inp", lsim_vectors); //load input vector file - - `impi = lsim_vectors[1]; //apply 1st test vector - - for (vector = 2; vector <= `num_vectors; vector = vector + 1) - @(posedge strb) - begin - - `impi = lsim_vectors[vector]; - - - - io[16:13] = io[07:04]; - io[12:09] = io[07:04]; - io[07:04] = io[03:00]; - io[03:00] = io[03:00]; - - io[17] = io[16] ^^ io[15] ^^ io[14] ^^ io[13] ^^ io[11] ^^ io[11] ^^ io[10] ^^ io[9]; - io[8] = io[7] ^^ io[6] ^^ io[5] ^^ io[4] ^^ io[3] ^^ io[2] ^^ io[1] ^^ io[0]; - - tsti[16:13] = tsti[07:04]; - tsti[12:09] = tsti[07:04]; - tsti[07:04] = tsti[03:00]; - tsti[03:00] = tsti[03:00]; - - tsti[17] = tsti[16] ^^ tsti[15] ^^ tsti[14] ^^ tsti[13] ^^ tsti[11] ^^ tsti[11] ^^ tsti[10] ^^ tsti[9]; - tsti[8] = tsti[7] ^^ tsti[6] ^^ tsti[5] ^^ tsti[4] ^^ tsti[3] ^^ tsti[2] ^^ tsti[1] ^^ tsti[0]; - - if (io === 18'hxxxxx) - iosel = `tx05 0; - else - iosel = `tx05 1; - - end - #15 $finish; // This prevents simulation beyond end of test patterns - end - -always@(posedge clk) -begin - - if (io !== 18'hxxxxx) //input cycle - begin - $display("NOTICE : 001 : line = %d OK",vector -1); - end - else //do the test - begin - if (d == tsti) - begin - $display("NOTICE : 002 : line = %d OK",vector -1); - end - else - begin - j =0; - for (i =0;i< 18; i=i+1) - begin - if(tsti[i] !== 1'bx) - begin - if (d[i] !== tsti[i]) j = 1; - end - else - j = 0; - end - if (j) - $display("ERROR *** : 003 : line = %d data = %b test = %b",vector -1,d,tsti); - else - $display("NOTICE : 003 : line = %d OK",vector -1); - end - end -end - -endmodule - - - - diff --git a/models/FIFO_GENERATOR_V4_3.v b/models/FIFO_GENERATOR_V4_3.v deleted file mode 100644 index bcb9af8a7..000000000 --- a/models/FIFO_GENERATOR_V4_3.v +++ /dev/null @@ -1,3494 +0,0 @@ -/* - * $RDCfile: $ $Revision: 1.1.2.15 $ $Date: 2007/07/25 15:58:33 $ - ******************************************************************************* - * - * FIFO Generator v3.3 - Verilog Behavioral Model - * - ******************************************************************************* - * - * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. - * This text/file contains proprietary, confidential - * information of Xilinx, Inc., is distributed under - * license from Xilinx, Inc., and may be used, copied - * and/or disclosed only pursuant to the terms of a valid - * license agreement with Xilinx, Inc. Xilinx hereby - * grants you a license to use this text/file solely for - * design, simulation, implementation and creation of - * design files limited to Xilinx devices or technologies. - * Use with non-Xilinx devices or technologies is expressly - * prohibited and immediately terminates your license unless - * covered by a separate agreement. - * - * Xilinx is providing theis design, code, or information - * "as-is" solely for use in developing programs and - * solutions for Xilinx devices, with no obligation on the - * part of Xilinx to provide support. By providing this design, - * code, or information as one possible implementation of - * this feature, application or standard. Xilinx is making no - * representation that this implementation is free from any - * claims of infringement. You are responsible for obtaining - * any rights you may require for your implementation. - * Xilinx expressly disclaims any warranty whatsoever with - * respect to the adequacy of the implementation, including - * but not limited to any warranties or representations that this - * implementation is free from claims of infringement, implied - * warranties of merchantability or fitness for a particular - * purpose. - * - * Xilinx products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * This copyright and support notice must be retained as part - * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. - * All rights reserved. - * - ******************************************************************************* - * - * Filename: fifo_generator_v4_3_bhv.v - * - * Description: - * The verilog behavioral model for the FIFO generator core. - * - ******************************************************************************* - */ - -`timescale 1ps/1ps - -/******************************************************************************* - * Declaration of top-level module - ******************************************************************************/ -module FIFO_GENERATOR_V4_3 -( - BACKUP, - BACKUP_MARKER, - CLK, - DIN, - PROG_EMPTY_THRESH, - PROG_EMPTY_THRESH_ASSERT, - PROG_EMPTY_THRESH_NEGATE, - PROG_FULL_THRESH, - PROG_FULL_THRESH_ASSERT, - PROG_FULL_THRESH_NEGATE, - RD_CLK, - RD_EN, - RD_RST, - RST, - SRST, - WR_CLK, - WR_EN, - WR_RST, - INT_CLK, - - ALMOST_EMPTY, - ALMOST_FULL, - DATA_COUNT, - DOUT, - EMPTY, - FULL, - OVERFLOW, - PROG_EMPTY, - PROG_FULL, - RD_DATA_COUNT, - UNDERFLOW, - VALID, - WR_ACK, - WR_DATA_COUNT, - SBITERR, - DBITERR - ); - - /**************************************************************************** - * Definition of Ports - * - * - ***************************************************************************** - * Definition of Parameters - * - * - *****************************************************************************/ - - /**************************************************************************** - * Declare user parameters and their defaults - *****************************************************************************/ - parameter C_COMMON_CLOCK = 0; - parameter C_COUNT_TYPE = 0; - parameter C_DATA_COUNT_WIDTH = 2; - parameter C_DEFAULT_VALUE = ""; - parameter C_DIN_WIDTH = 8; - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_ENABLE_RLOCS = 0; - - parameter C_FAMILY = "virtex2"; - //Not allowed in Verilog model - - parameter C_HAS_ALMOST_EMPTY = 0; - parameter C_HAS_ALMOST_FULL = 0; - parameter C_HAS_BACKUP = 0; - parameter C_HAS_DATA_COUNT = 0; - parameter C_HAS_MEMINIT_FILE = 0; - parameter C_HAS_OVERFLOW = 0; - parameter C_HAS_RD_DATA_COUNT = 0; - parameter C_HAS_RD_RST = 0; - parameter C_HAS_RST = 0; - parameter C_HAS_SRST = 0; - parameter C_HAS_UNDERFLOW = 0; - parameter C_HAS_VALID = 0; - parameter C_HAS_WR_ACK = 0; - parameter C_HAS_WR_DATA_COUNT = 0; - parameter C_HAS_WR_RST = 0; - parameter C_IMPLEMENTATION_TYPE = 0; - parameter C_INIT_WR_PNTR_VAL = 0; - parameter C_MEMORY_TYPE = 1; - parameter C_MIF_FILE_NAME = ""; - parameter C_OPTIMIZATION_MODE = 0; - parameter C_OVERFLOW_LOW = 0; - parameter C_PRELOAD_LATENCY = 1; - parameter C_PRELOAD_REGS = 0; - parameter C_PRIM_FIFO_TYPE = 512; - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; - parameter C_PROG_EMPTY_TYPE = 0; - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; - parameter C_PROG_FULL_TYPE = 0; - parameter C_RD_DATA_COUNT_WIDTH = 2; - parameter C_RD_DEPTH = 256; - parameter C_RD_FREQ = 1; - parameter C_RD_PNTR_WIDTH = 8; - parameter C_UNDERFLOW_LOW = 0; - parameter C_USE_FIFO16_FLAGS = 0; - parameter C_VALID_LOW = 0; - parameter C_WR_ACK_LOW = 0; - parameter C_WR_DATA_COUNT_WIDTH = 2; - parameter C_WR_DEPTH = 256; - parameter C_WR_FREQ = 1; - parameter C_WR_PNTR_WIDTH = 8; - parameter C_WR_RESPONSE_LATENCY = 1; - parameter C_USE_ECC = 0; - parameter C_FULL_FLAGS_RST_VAL = 1; - parameter C_HAS_INT_CLK = 0; - parameter C_USE_EMBEDDED_REG = 0; - parameter C_USE_FWFT_DATA_COUNT = 0; - - //There are 2 Verilog behavioral models - // 0 = Synchronous FIFO/ShiftRam FIFO - // 1 = Asynchronous FIFO - parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : - (C_IMPLEMENTATION_TYPE==1 ? 0 : - (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); - - - /****************************************************************************** - * Declare Input and Output Ports - *****************************************************************************/ - input CLK; - input BACKUP; - input BACKUP_MARKER; - input [C_DIN_WIDTH-1:0] DIN; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; - input RD_CLK; - input RD_EN; - input RD_RST; - input RST; - input SRST; - input WR_CLK; - input WR_EN; - input WR_RST; - input INT_CLK; - - output ALMOST_EMPTY; - output ALMOST_FULL; - output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; - output [C_DOUT_WIDTH-1:0] DOUT; - output EMPTY; - output FULL; - output OVERFLOW; - output PROG_EMPTY; - output PROG_FULL; - output VALID; - output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; - output UNDERFLOW; - output WR_ACK; - output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; - output SBITERR; - output DBITERR; - - - wire ALMOST_EMPTY; - wire ALMOST_FULL; - wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; - wire [C_DOUT_WIDTH-1:0] DOUT; - wire EMPTY; - wire FULL; - wire OVERFLOW; - wire PROG_EMPTY; - wire PROG_FULL; - wire VALID; - wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; - wire UNDERFLOW; - wire WR_ACK; - wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; - - - wire RD_CLK_P0_IN; - wire RST_P0_IN; - wire RD_EN_FIFO_IN; - wire RD_EN_P0_IN; - - wire ALMOST_EMPTY_FIFO_OUT; - wire ALMOST_FULL_FIFO_OUT; - wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; - wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; - wire EMPTY_FIFO_OUT; - wire FULL_FIFO_OUT; - wire OVERFLOW_FIFO_OUT; - wire PROG_EMPTY_FIFO_OUT; - wire PROG_FULL_FIFO_OUT; - wire VALID_FIFO_OUT; - wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; - wire UNDERFLOW_FIFO_OUT; - wire WR_ACK_FIFO_OUT; - wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; - - - //*************************************************************************** - // Internal Signals - // The core uses either the internal_ wires or the preload0_ wires depending - // on whether the core uses Preload0 or not. - // When using preload0, the internal signals connect the internal core to - // the preload logic, and the external core's interfaces are tied to the - // preload0 signals from the preload logic. - //*************************************************************************** - wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; - wire VALID_P0_OUT; - wire EMPTY_P0_OUT; - wire ALMOSTEMPTY_P0_OUT; - reg EMPTY_P0_OUT_Q; - reg ALMOSTEMPTY_P0_OUT_Q; - wire UNDERFLOW_P0_OUT; - wire RDEN_P0_OUT; - wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; - wire EMPTY_P0_IN; - - assign SBITERR = 1'b0; - assign DBITERR = 1'b0; - -// choose the base FIFO implementation for simulation -generate -case (C_VERILOG_IMPL) -0 : begin : block1 - fifo_generator_v4_3_bhv_ver_ss - #( - C_COMMON_CLOCK, - C_COUNT_TYPE, - C_DATA_COUNT_WIDTH, - C_DEFAULT_VALUE, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_ENABLE_RLOCS, - C_FAMILY,//Not allowed in Verilog model - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_BACKUP, - C_HAS_DATA_COUNT, - C_HAS_MEMINIT_FILE, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RD_RST, - C_HAS_RST, - C_HAS_SRST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_HAS_WR_RST, - C_IMPLEMENTATION_TYPE, - C_INIT_WR_PNTR_VAL, - C_MEMORY_TYPE, - C_MIF_FILE_NAME, - C_OPTIMIZATION_MODE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_WR_RESPONSE_LATENCY, - C_FULL_FLAGS_RST_VAL, - C_USE_EMBEDDED_REG - ) - gen_ss - ( - .CLK (CLK), - .RST (RST), - .SRST (SRST), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .DATA_COUNT (DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) - ); -end -1 : begin : block1 - fifo_generator_v4_3_bhv_ver_as - #( - C_COMMON_CLOCK, - C_COUNT_TYPE, - C_DATA_COUNT_WIDTH, - C_DEFAULT_VALUE, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_ENABLE_RLOCS, - C_FAMILY,//Not allowed in Verilog model - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_BACKUP, - C_HAS_DATA_COUNT, - C_HAS_MEMINIT_FILE, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RD_RST, - C_HAS_RST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_HAS_WR_RST, - C_IMPLEMENTATION_TYPE, - C_INIT_WR_PNTR_VAL, - C_MEMORY_TYPE, - C_MIF_FILE_NAME, - C_OPTIMIZATION_MODE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_WR_RESPONSE_LATENCY, - C_FULL_FLAGS_RST_VAL, - C_USE_FWFT_DATA_COUNT, - C_USE_EMBEDDED_REG - ) - gen_as - ( - .WR_CLK (WR_CLK), - .RD_CLK (RD_CLK), - .RST (RST), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), - .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) - ); -end - -default : begin : block1 - fifo_generator_v4_3_bhv_ver_as - #( - C_COMMON_CLOCK, - C_COUNT_TYPE, - C_DATA_COUNT_WIDTH, - C_DEFAULT_VALUE, - C_DIN_WIDTH, - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_ENABLE_RLOCS, - C_FAMILY,//Not allowed in Verilog model - C_HAS_ALMOST_EMPTY, - C_HAS_ALMOST_FULL, - C_HAS_BACKUP, - C_HAS_DATA_COUNT, - C_HAS_MEMINIT_FILE, - C_HAS_OVERFLOW, - C_HAS_RD_DATA_COUNT, - C_HAS_RD_RST, - C_HAS_RST, - C_HAS_UNDERFLOW, - C_HAS_VALID, - C_HAS_WR_ACK, - C_HAS_WR_DATA_COUNT, - C_HAS_WR_RST, - C_IMPLEMENTATION_TYPE, - C_INIT_WR_PNTR_VAL, - C_MEMORY_TYPE, - C_MIF_FILE_NAME, - C_OPTIMIZATION_MODE, - C_OVERFLOW_LOW, - C_PRELOAD_LATENCY, - C_PRELOAD_REGS, - C_PROG_EMPTY_THRESH_ASSERT_VAL, - C_PROG_EMPTY_THRESH_NEGATE_VAL, - C_PROG_EMPTY_TYPE, - C_PROG_FULL_THRESH_ASSERT_VAL, - C_PROG_FULL_THRESH_NEGATE_VAL, - C_PROG_FULL_TYPE, - C_RD_DATA_COUNT_WIDTH, - C_RD_DEPTH, - C_RD_PNTR_WIDTH, - C_UNDERFLOW_LOW, - C_VALID_LOW, - C_WR_ACK_LOW, - C_WR_DATA_COUNT_WIDTH, - C_WR_DEPTH, - C_WR_PNTR_WIDTH, - C_WR_RESPONSE_LATENCY, - C_FULL_FLAGS_RST_VAL, - C_USE_FWFT_DATA_COUNT, - C_USE_EMBEDDED_REG - ) - gen_as - ( - .WR_CLK (WR_CLK), - .RD_CLK (RD_CLK), - .RST (RST), - .DIN (DIN), - .WR_EN (WR_EN), - .RD_EN (RD_EN_FIFO_IN), - .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), - .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), - .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), - .PROG_FULL_THRESH (PROG_FULL_THRESH), - .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), - .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), - .DOUT (DOUT_FIFO_OUT), - .FULL (FULL_FIFO_OUT), - .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), - .WR_ACK (WR_ACK_FIFO_OUT), - .OVERFLOW (OVERFLOW_FIFO_OUT), - .EMPTY (EMPTY_FIFO_OUT), - .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), - .VALID (VALID_FIFO_OUT), - .UNDERFLOW (UNDERFLOW_FIFO_OUT), - .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), - .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), - .PROG_FULL (PROG_FULL_FIFO_OUT), - .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) - ); -end - -endcase -endgenerate - - -//************************************************************************** -// Connect Internal Signals -// (Signals labeled internal_*) -// In the normal case, these signals tie directly to the FIFO's inputs and -// outputs. -// In the case of Preload Latency 0 or 1, there are intermediate -// signals between the internal FIFO and the preload logic. -//************************************************************************** - -generate -if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) - begin : block2 - -fifo_generator_v4_3_bhv_ver_preload0 - #( - C_DOUT_RST_VAL, - C_DOUT_WIDTH, - C_HAS_RST, - C_VALID_LOW, - C_UNDERFLOW_LOW - ) - fgpl0 -( - .RD_CLK (RD_CLK_P0_IN), - .RD_RST (RST_P0_IN), - .RD_EN (RD_EN_P0_IN), - .FIFOEMPTY (EMPTY_P0_IN), - .FIFODATA (DATA_P0_IN), - .USERDATA (DATA_P0_OUT), - .USERVALID (VALID_P0_OUT), - .USEREMPTY (EMPTY_P0_OUT), - .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), - .USERUNDERFLOW (UNDERFLOW_P0_OUT), - .RAMVALID (RAMVALID_P0_OUT), - .FIFORDEN (RDEN_P0_OUT) - ); - - assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); - assign RST_P0_IN = RST; - assign RD_EN_P0_IN = RD_EN; - - assign RD_EN_FIFO_IN = RDEN_P0_OUT; - - assign DOUT = DATA_P0_OUT; - assign DATA_P0_IN = DOUT_FIFO_OUT; - assign VALID = VALID_P0_OUT ; - assign EMPTY = EMPTY_P0_OUT; - assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; - assign EMPTY_P0_IN = EMPTY_FIFO_OUT; - assign UNDERFLOW = UNDERFLOW_P0_OUT ; - - always @ (posedge RD_CLK or posedge RST) - begin - if (RST) - begin - EMPTY_P0_OUT_Q <= 1; - ALMOSTEMPTY_P0_OUT_Q <= 1; - end - else - begin - EMPTY_P0_OUT_Q <= EMPTY_P0_OUT; - ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT; - end - end - - end -else - begin : block2 - - assign RD_CLK_P0_IN = 0; - assign RST_P0_IN = 0; - assign RD_EN_P0_IN = 0; - - assign RD_EN_FIFO_IN = RD_EN; - - assign DOUT = DOUT_FIFO_OUT; - assign DATA_P0_IN = 0; - assign VALID = VALID_FIFO_OUT; - assign EMPTY = EMPTY_FIFO_OUT; - assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; - assign EMPTY_P0_IN = 0; - assign UNDERFLOW = UNDERFLOW_FIFO_OUT; - - end -endgenerate - - -//Connect Data Count Signals -generate -if (C_USE_FWFT_DATA_COUNT==1) begin : block3 - assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); -end -else begin : block3 - assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; -end -endgenerate - -generate -if (C_USE_FWFT_DATA_COUNT==1) begin : block4 - assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; -end -else begin : block4 - assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; -end -endgenerate - - - assign FULL = FULL_FIFO_OUT; - assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; - assign WR_ACK = WR_ACK_FIFO_OUT; - assign OVERFLOW = OVERFLOW_FIFO_OUT; - assign PROG_FULL = PROG_FULL_FIFO_OUT; - assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; - assign DATA_COUNT = DATA_COUNT_FIFO_OUT; - - - // if an asynchronous FIFO has been selected, display a message that the FIFO - // will not be cycle-accurate in simulation - initial begin - //if (C_IMPLEMENTATION_TYPE == 1) begin //bug in v3.1 - if (C_IMPLEMENTATION_TYPE == 2) begin //fixed in v3.2 (IP2_Im) - $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); - end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin - $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); - $finish; - end - - end - -endmodule //fifo_generator_v4_3_bhv_ver - - - - - - -/******************************************************************************* - * Declaration of asynchronous FIFO Module - ******************************************************************************/ -module fifo_generator_v4_3_bhv_ver_as - ( - WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, - PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, - PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, - DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID, - UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY - ); - - /***************************************************************************** - * Declare user parameters and their defaults - *****************************************************************************/ - parameter C_COMMON_CLOCK = 0; - parameter C_COUNT_TYPE = 0; - parameter C_DATA_COUNT_WIDTH = 2; - parameter C_DEFAULT_VALUE = ""; - parameter C_DIN_WIDTH = 8; - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_ENABLE_RLOCS = 0; - parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model - parameter C_HAS_ALMOST_EMPTY = 0; - parameter C_HAS_ALMOST_FULL = 0; - parameter C_HAS_BACKUP = 0; - parameter C_HAS_DATA_COUNT = 0; - parameter C_HAS_MEMINIT_FILE = 0; - parameter C_HAS_OVERFLOW = 0; - parameter C_HAS_RD_DATA_COUNT = 0; - parameter C_HAS_RD_RST = 0; - parameter C_HAS_RST = 0; - parameter C_HAS_UNDERFLOW = 0; - parameter C_HAS_VALID = 0; - parameter C_HAS_WR_ACK = 0; - parameter C_HAS_WR_DATA_COUNT = 0; - parameter C_HAS_WR_RST = 0; - parameter C_IMPLEMENTATION_TYPE = 0; - parameter C_INIT_WR_PNTR_VAL = 0; - parameter C_MEMORY_TYPE = 1; - parameter C_MIF_FILE_NAME = ""; - parameter C_OPTIMIZATION_MODE = 0; - parameter C_OVERFLOW_LOW = 0; - parameter C_PRELOAD_LATENCY = 1; - parameter C_PRELOAD_REGS = 0; - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; - parameter C_PROG_EMPTY_TYPE = 0; - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; - parameter C_PROG_FULL_TYPE = 0; - parameter C_RD_DATA_COUNT_WIDTH = 2; - parameter C_RD_DEPTH = 256; - parameter C_RD_PNTR_WIDTH = 8; - parameter C_UNDERFLOW_LOW = 0; - parameter C_VALID_LOW = 0; - parameter C_WR_ACK_LOW = 0; - parameter C_WR_DATA_COUNT_WIDTH = 2; - parameter C_WR_DEPTH = 256; - parameter C_WR_PNTR_WIDTH = 8; - parameter C_WR_RESPONSE_LATENCY = 1; - parameter C_FULL_FLAGS_RST_VAL = 1; - parameter C_USE_FWFT_DATA_COUNT = 0; - parameter C_USE_EMBEDDED_REG = 0; - - /***************************************************************************** - * Declare Input and Output Ports - *****************************************************************************/ - input [C_DIN_WIDTH-1:0] DIN; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; - input RD_CLK; - input RD_EN; - input RST; - input WR_CLK; - input WR_EN; - output ALMOST_EMPTY; - output ALMOST_FULL; - output [C_DOUT_WIDTH-1:0] DOUT; - output EMPTY; - output FULL; - output OVERFLOW; - output PROG_EMPTY; - output PROG_FULL; - output VALID; - output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; - output UNDERFLOW; - output WR_ACK; - output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; - - /******************************************************************************* - * Input and output register declarations - ******************************************************************************/ - /******************************************************************************* - * Parameters used as constants - ******************************************************************************/ - //When RST is present, set FULL reset value to '1'. - //If core has no RST, make sure FULL powers-on as '0'. - parameter C_DEPTH_RATIO_WR = - (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; - parameter C_DEPTH_RATIO_RD = - (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; - parameter C_FIFO_WR_DEPTH = - (C_COMMON_CLOCK) ? - C_WR_DEPTH : C_WR_DEPTH - 1; - parameter C_FIFO_RD_DEPTH = - (C_COMMON_CLOCK) ? - C_RD_DEPTH : C_RD_DEPTH - 1; - - - // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD - // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 - // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) - // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 - // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 - parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); - // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD - // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC - // -----------------|------------------|-----------------|--------------- - // 1 | 8 | C_RD_PNTR_WIDTH | 2 - // 1 | 4 | C_RD_PNTR_WIDTH | 2 - // 1 | 2 | C_RD_PNTR_WIDTH | 2 - // 1 | 1 | C_WR_PNTR_WIDTH | 2 - // 2 | 1 | C_WR_PNTR_WIDTH | 4 - // 4 | 1 | C_WR_PNTR_WIDTH | 8 - // 8 | 1 | C_WR_PNTR_WIDTH | 16 - parameter EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR)? - 2:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); - - - //Memory which will be used to simulate a FIFO - reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; - reg [31:0] num_wr_bits; - reg [31:0] num_rd_bits; - reg [31:0] next_num_wr_bits; - reg [31:0] next_num_rd_bits; - reg [31:0] wr_ptr; - reg [31:0] rd_ptr; - reg [31:0] wr_ptr_rdclk; - reg [31:0] wr_ptr_rdclk_next; - reg [31:0] rd_ptr_wrclk; - reg [31:0] rd_ptr_wrclk_next; - wire [31:0] num_read_words = num_rd_bits/C_DOUT_WIDTH; - wire [31:0] num_read_words_dc_i; - wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; - wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); - wire [31:0] num_read_words_pe = - num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); - wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; - wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized - = num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; - wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft - = num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; - wire [31:0] num_write_words = num_wr_bits/C_DIN_WIDTH; - wire [31:0] num_write_words_dc_i; - wire [31:0] num_write_words_dc = 1+(num_wr_bits-1)/C_DIN_WIDTH;//roof of num_wr_bits/C_DIN_WIDTH - wire [31:0] num_write_words_fwft_dc = - (num_wr_bits/C_DIN_WIDTH*C_DEPTH_RATIO_RD+2*C_DEPTH_RATIO_WR)/C_DEPTH_RATIO_RD; - wire [31:0] num_write_words_pf = - num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); - wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; - wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized - = num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; - wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft - = num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; - wire [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; - wire [31:0] log2_reads_per_write = log2_val(reads_per_write); - wire [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; - wire [31:0] log2_writes_per_read = log2_val(writes_per_read); - - /******************************************************************************* - * Internal Registers and wires - ******************************************************************************/ - wire wr_ack_i; - wire overflow_i; - wire underflow_i; - wire valid_i; - wire valid_out; - reg valid_d1; - /******************************************************************************* - * Internal registers and wires for internal reset logics - ******************************************************************************/ - reg rd_rst_asreg =0; - reg rd_rst_asreg_d1 =0; - reg rd_rst_asreg_d2 =0; - reg rd_rst_reg =0; - reg rd_rst_d1 =0; - reg wr_rst_asreg =0; - reg wr_rst_asreg_d1 =0; - reg wr_rst_asreg_d2 =0; - reg wr_rst_reg =0; - reg wr_rst_d1 =0; - wire rd_rst_comb; - wire rd_rst_i; - wire wr_rst_comb; - wire wr_rst_i; - - - - //Special ideal FIFO signals - reg [C_DOUT_WIDTH-1:0] ideal_dout; - wire [C_DOUT_WIDTH-1:0] ideal_dout_out; - reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; - reg ideal_wr_ack; - reg ideal_valid; - reg ideal_overflow; - reg ideal_underflow; - reg ideal_full; - reg ideal_empty; - reg ideal_almost_full; - reg ideal_almost_empty; - reg ideal_prog_full; - reg ideal_prog_empty; - - //MSBs of the counts - reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; - reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; - - //user specified value for reseting the size of the fifo - reg [C_DOUT_WIDTH-1:0] dout_reset_val; - - //temporary registers for WR_RESPONSE_LATENCY feature - - integer tmp_wr_listsize; - integer tmp_rd_listsize; - - //Signal for registered version of prog full and empty - reg prog_full_d; - reg prog_empty_d; - - //Threshold values for Programmable Flags - integer prog_empty_actual_thresh_assert; - integer prog_empty_actual_thresh_negate; - integer prog_full_actual_thresh_assert; - integer prog_full_actual_thresh_negate; - - - /**************************************************************************** - * Function Declarations - ***************************************************************************/ - - task write_fifo; - begin - memory[wr_ptr] <= DIN; - if (wr_ptr == 0) begin - wr_ptr <= C_WR_DEPTH - 1; - end else begin - wr_ptr <= wr_ptr - 1; - end - end - endtask // write_fifo - - task read_fifo; - integer i; - reg [C_DOUT_WIDTH-1:0] tmp_dout; - reg [C_DIN_WIDTH-1:0] memory_read; - reg [31:0] tmp_rd_ptr; - reg [31:0] rd_ptr_high; - reg [31:0] rd_ptr_low; - begin - // output is wider than input - if (reads_per_write == 0) begin - tmp_dout = 0; - tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); - for (i = writes_per_read - 1; i >= 0; i = i - 1) begin - tmp_dout = tmp_dout << C_DIN_WIDTH; - tmp_dout = tmp_dout | memory[tmp_rd_ptr]; - if (tmp_rd_ptr == 0) begin - tmp_rd_ptr = C_WR_DEPTH - 1; - end else begin - tmp_rd_ptr = tmp_rd_ptr - 1; - end - end - - // output is symmetric - end else if (reads_per_write == 1) begin - tmp_dout = memory[rd_ptr]; - - // input is wider than output - end else begin - rd_ptr_high = rd_ptr >> log2_reads_per_write; - rd_ptr_low = rd_ptr & (reads_per_write - 1); - memory_read = memory[rd_ptr_high]; - tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); - end - ideal_dout <= tmp_dout; - if (rd_ptr == 0) begin - rd_ptr <= C_RD_DEPTH - 1; - end else begin - rd_ptr <= rd_ptr - 1; - end - end - endtask - - /**************************************************************************** - * log2_val - * Returns the 'log2' value for the input value for the supported ratios - ***************************************************************************/ - function [31:0] log2_val; - input [31:0] binary_val; - - begin - if (binary_val == 8) begin - log2_val = 3; - end else if (binary_val == 4) begin - log2_val = 2; - end else begin - log2_val = 1; - end - end - endfunction - - /************************************************************************* - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***********************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - - /************************************************************************* - * Initialize Signals for clean power-on simulation - *************************************************************************/ - initial - begin - num_wr_bits = 0; - num_rd_bits = 0; - next_num_wr_bits = 0; - next_num_rd_bits = 0; - rd_ptr = C_RD_DEPTH - 1; - wr_ptr = C_WR_DEPTH - 1; - rd_ptr_wrclk = rd_ptr; - wr_ptr_rdclk = wr_ptr; - dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); - ideal_dout = dout_reset_val; - ideal_wr_ack = 1'b0; - ideal_valid = 1'b0; - ideal_overflow = 1'b0; - ideal_underflow = 1'b0; - //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) - //ideal_full = C_FULL_RESET_VAL; //was in v3.1 - ideal_full = 1'b0; //v3.2 - ideal_empty = 1'b1; - //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) - //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 - ideal_almost_full = 1'b0; //v3.2 - ideal_almost_empty = 1'b1; - ideal_wr_count = 0; - ideal_rd_count = 0; - //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) - //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 - ideal_prog_full = 1'b0; //v3.2 - ideal_prog_empty = 1'b1; - //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) - //Therefore, prog_full_d has to start-up at '0' too - //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 - prog_full_d = 1'b0; //v3.2 - prog_empty_d = 1'b1; - end - - - - /************************************************************************* - * Assign Internal ideal signals to output ports - *************************************************************************/ - assign ideal_dout_out= (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - ideal_dout_d1: ideal_dout; - assign DOUT = ideal_dout_out; - assign FULL = ideal_full; - assign EMPTY = ideal_empty; - assign ALMOST_FULL = ideal_almost_full; - assign ALMOST_EMPTY = ideal_almost_empty; - assign num_write_words_sized_i=C_USE_FWFT_DATA_COUNT? - num_write_words_sized_fwft:num_write_words_sized; - assign num_read_words_sized_i=C_USE_FWFT_DATA_COUNT? - num_read_words_sized_fwft:num_read_words_sized; - assign num_write_words_dc_i = C_USE_FWFT_DATA_COUNT? - num_write_words_fwft_dc: num_write_words_dc; - assign num_read_words_dc_i = C_USE_FWFT_DATA_COUNT? - num_read_words_fwft_dc: num_read_words_dc; - assign WR_DATA_COUNT = ideal_wr_count; - assign RD_DATA_COUNT = ideal_rd_count; - assign PROG_FULL = ideal_prog_full; - assign PROG_EMPTY = ideal_prog_empty; - - //Handshaking signals can be active low, depending on _LOW parameters - assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; - assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; - assign valid_out = (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - valid_d1: valid_i; - assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; - assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; - - assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; - assign wr_ack_i = (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : - (WR_EN & !FULL); - assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; - assign overflow_i = (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : - (WR_EN & FULL); - - /******************************************************************************* - * Internal reset logics - ******************************************************************************/ - assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; - assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; - assign wr_rst_i = C_HAS_RST ? wr_rst_reg : 0; - assign rd_rst_i = C_HAS_RST ? rd_rst_reg : 0; - - - always @(posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i == 1'b1) begin - valid_d1 <= 1'b0; - end else begin - valid_d1 <= valid_i; - end - end - always @(posedge RD_CLK or posedge rd_rst_i) begin - if (rd_rst_i == 1'b1) begin - ideal_dout_d1 <= dout_reset_val; - end else begin - ideal_dout_d1 <= ideal_dout; - end - end - - always @(posedge WR_CLK or posedge RST) begin - if (RST == 1'b1) begin - wr_rst_asreg <= 1'b1; - end else begin - if (wr_rst_asreg_d1 == 1'b1) begin - wr_rst_asreg <= 1'b0; - end else begin - wr_rst_asreg <= wr_rst_asreg; - end - end - end - - always @(posedge WR_CLK) begin - wr_rst_asreg_d1 <= wr_rst_asreg; - wr_rst_asreg_d2 <= wr_rst_asreg_d1; - end - - always @(posedge WR_CLK or posedge wr_rst_comb) begin - if (wr_rst_comb == 1'b1) begin - wr_rst_reg <= 1'b1; - end else begin - wr_rst_reg <= 1'b0; - end - end - - always @(posedge WR_CLK or posedge wr_rst_i) begin - if (wr_rst_i == 1'b1) begin - wr_rst_d1 <= 1'b1; - end else begin - wr_rst_d1 <= wr_rst_i; - end - end - always @(posedge RD_CLK or posedge RST) begin - if (RST == 1'b1) begin - rd_rst_asreg <= 1'b1; - end else begin - if (rd_rst_asreg_d1 == 1'b1) begin - rd_rst_asreg <= 1'b0; - end else begin - rd_rst_asreg <= rd_rst_asreg; - end - end - end - - always @(posedge RD_CLK) begin - rd_rst_asreg_d1 <= rd_rst_asreg; - rd_rst_asreg_d2 <= rd_rst_asreg_d1; - end - - always @(posedge RD_CLK or posedge rd_rst_comb) begin - if (rd_rst_comb == 1'b1) begin - rd_rst_reg <= 1'b1; - end else begin - rd_rst_reg <= 1'b0; - end - end - - //Generate overflow and underflow flags seperately - //because they don't support async rst - always @(posedge WR_CLK) begin - ideal_overflow <= WR_EN & ideal_full; - end - always @(posedge RD_CLK) begin - ideal_underflow <= ideal_empty & RD_EN; - end - - /******************************************************************************* - * Write and Read Logics - ******************************************************************************/ - always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w - - /****** Reset fifo (case 1)***************************************/ - if (wr_rst_i == 1'b1) begin - num_wr_bits <= 0; - next_num_wr_bits <= 0; - wr_ptr <= C_WR_DEPTH - 1; - rd_ptr_wrclk <= C_RD_DEPTH - 1; - ideal_wr_ack <= 0; - ideal_full <= C_FULL_FLAGS_RST_VAL; - ideal_almost_full <= C_FULL_FLAGS_RST_VAL; - ideal_wr_count <= 0; - - ideal_prog_full <= C_FULL_FLAGS_RST_VAL; - prog_full_d <= C_FULL_FLAGS_RST_VAL; - - end else begin //wr_rst_i==0 - - //Determine the current number of words in the FIFO - tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : - num_wr_bits/C_DIN_WIDTH; - rd_ptr_wrclk_next = rd_ptr; - if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin - next_num_wr_bits = num_wr_bits - - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - - rd_ptr_wrclk_next); - end else begin - next_num_wr_bits = num_wr_bits - - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); - end - - //If this is a write, handle the write by adding the value - // to the linked list, and updating all outputs appropriately - if (WR_EN == 1'b1) begin - if (ideal_full == 1'b1) begin - - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD - >= C_FIFO_WR_DEPTH) begin - //write unsuccessful - do not change contents - - //Do not acknowledge the write - ideal_wr_ack <= 0; - //Reminder that FIFO is still full - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - //If the FIFO is one from full, but reporting full - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-1) begin - //No change to FIFO - - //Write not successful - ideal_wr_ack <= 0; - //With DEPTH-1 words in the FIFO, it is almost_full - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - - //If the FIFO is completely empty, but it is - // reporting FULL for some reason (like reset) - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= - C_FIFO_WR_DEPTH-2) begin - //No change to FIFO - - //Write not successful - ideal_wr_ack <= 0; - //FIFO is really not close to full, so change flag status. - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - ideal_wr_count <= num_write_words_sized_i; - end //(tmp_wr_listsize == 0) - - end else begin - - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= - C_FIFO_WR_DEPTH) begin - //write unsuccessful - do not change contents - - //Do not acknowledge the write - ideal_wr_ack <= 0; - //Reminder that FIFO is still full - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - //If the FIFO is one from full - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-1) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= 1; - //This write is CAUSING the FIFO to go full - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - //If the FIFO is 2 from full - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == - C_FIFO_WR_DEPTH-2) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= 1; - //Still 2 from full - ideal_full <= 1'b0; - //2 from full, and writing, so set almost_full - ideal_almost_full <= 1'b1; - - ideal_wr_count <= num_write_words_sized_i; - - //If the FIFO is not close to being full - end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < - C_FIFO_WR_DEPTH-2) begin - //Add value on DIN port to FIFO - write_fifo; - next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; - //Write successful, so issue acknowledge - // and no error - ideal_wr_ack <= 1; - //Not even close to full. - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - ideal_wr_count <= num_write_words_sized_i; - - end - - end - - end else begin //(WR_EN == 1'b1) - - //If user did not attempt a write, then do not - // give ack or err - ideal_wr_ack <= 0; - - //Implied statements: - //ideal_empty <= ideal_empty; - //ideal_almost_empty <= ideal_almost_empty; - - //Check for full - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) - ideal_full <= 1'b1; - else - ideal_full <= 1'b0; - - //Check for almost_full - if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) - ideal_almost_full <= 1'b1; - else - ideal_almost_full <= 1'b0; - - ideal_wr_count <= num_write_words_sized_i; - end - - /********************************************************* - * Programmable FULL flags - *********************************************************/ - //Single Programmable Full Constant Threshold - if (C_PROG_FULL_TYPE==1) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; - prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; - end else begin - prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; - prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; - end - - //Two Programmable Full Constant Thresholds - end else if (C_PROG_FULL_TYPE==2) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; - prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; - end else begin - prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; - prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; - end - - //Single Programmable Full Threshold Input - end else if (C_PROG_FULL_TYPE==3) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; - prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; - end else begin - prog_full_actual_thresh_assert = PROG_FULL_THRESH; - prog_full_actual_thresh_negate = PROG_FULL_THRESH; - end - - //Two Programmable Full Threshold Inputs - end else if (C_PROG_FULL_TYPE==4) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; - prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; - end else begin - prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; - prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; - end - end //C_PROG_FULL_TYPE - - if (num_write_words_pf==0) begin - prog_full_d <= 1'b0; - end else begin - if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) - == prog_full_actual_thresh_assert-1) && WR_EN) begin - prog_full_d <= 1'b1; - end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) - >= prog_full_actual_thresh_assert) begin - prog_full_d <= 1'b1; - end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) - < prog_full_actual_thresh_negate) begin - prog_full_d <= 1'b0; - end - end - - if (wr_rst_d1==1 && wr_rst_i==0) begin - ideal_prog_full <= 0; - end else begin - ideal_prog_full <= prog_full_d; - end - num_wr_bits <= next_num_wr_bits; - rd_ptr_wrclk <= rd_ptr; - - end //wr_rst_i==0 - end // write always - - always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r - - /****** Reset fifo (case 1)***************************************/ - if (rd_rst_i) begin - num_rd_bits <= 0; - next_num_rd_bits <= 0; - rd_ptr <= C_RD_DEPTH -1; - wr_ptr_rdclk <= C_WR_DEPTH -1; - ideal_dout <= dout_reset_val; - ideal_valid <= 1'b0; - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - ideal_rd_count <= 0; - - ideal_prog_empty <= 1'b1; - prog_empty_d <= 1; - - - end else begin //rd_rst_i==0 - - //Determine the current number of words in the FIFO - tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : - num_rd_bits/C_DOUT_WIDTH; - wr_ptr_rdclk_next = wr_ptr; - - if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin - next_num_rd_bits = num_rd_bits + - C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - - wr_ptr_rdclk_next); - end else begin - next_num_rd_bits = num_rd_bits + - C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); - end - - /*****************************************************************/ - // Read Operation - Read Latency 1 - /*****************************************************************/ - if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin - - if (RD_EN == 1'b1) begin - - if (ideal_empty == 1'b1) begin - - //If the FIFO is completely empty, and is reporting empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Reminder that FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - end // if (tmp_rd_listsize <= 0) - - //If the FIFO is one from empty, but it is reporting empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Note that FIFO is no longer empty, but is almost empty (has one word left) - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == 1) - - //If the FIFO is two from empty, and is reporting empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Fifo has two words, so is neither empty or almost empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == 2) - - //If the FIFO is not close to empty, but is reporting that it is - // Treat the FIFO as empty this time, but unset EMPTY flags. - if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - end // else: if(ideal_empty == 1'b1) - - else //if (ideal_empty == 1'b0) - begin - - //If the FIFO is completely full, and we are successfully reading from it - if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Not close to empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) - - //If the FIFO is not close to being empty - else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Not close to empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - - //If the FIFO is two from empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Fifo is not yet empty. It is going almost_empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == 2) - - //If the FIFO is one from empty - else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) - begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Note that FIFO is GOING empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize == 1) - - - //If the FIFO is completely empty - else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Reminder that FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize <= 0) - - end // if (ideal_empty == 1'b0) - - end //(RD_EN == 1'b1) - - else //if (RD_EN == 1'b0) - begin - //If user did not attempt a read, do not give an ack or err - ideal_valid <= 1'b0; - - //Check for empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - ideal_empty <= 1'b1; - else - ideal_empty <= 1'b0; - - //Check for almost_empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) - ideal_almost_empty <= 1'b1; - else - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // else: !if(RD_EN == 1'b1) - - /*****************************************************************/ - // Read Operation - Read Latency 0 - /*****************************************************************/ - end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - if (RD_EN == 1'b1) begin - - if (ideal_empty == 1'b1) begin - - //If the FIFO is completely empty, and is reporting empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Reminder that FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is one from empty, but it is reporting empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Note that FIFO is no longer empty, but is almost empty (has one word left) - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is two from empty, and is reporting empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Fifo has two words, so is neither empty or almost empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is not close to empty, but is reporting that it is - // Treat the FIFO as empty this time, but unset EMPTY flags. - end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && - (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) - - end else begin - - //If the FIFO is completely full, and we are successfully reading from it - if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Not close to empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is not close to being empty - end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && - (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Not close to empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is two from empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Fifo is not yet empty. It is going almost_empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is one from empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin - //Read the value from the FIFO - read_fifo; - next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; - - //Acknowledge the read from the FIFO, no error - ideal_valid <= 1'b1; - //Note that FIFO is GOING empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - //If the FIFO is completely empty - end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin - //Do not change the contents of the FIFO - - //Do not acknowledge the read from empty FIFO - ideal_valid <= 1'b0; - //Reminder that FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - ideal_rd_count <= num_read_words_sized_i; - - end // if (tmp_rd_listsize <= 0) - - end // if (ideal_empty == 1'b0) - - end else begin//(RD_EN == 1'b0) - - - //If user did not attempt a read, do not give an ack or err - ideal_valid <= 1'b0; - - //Check for empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) - ideal_empty <= 1'b1; - else - ideal_empty <= 1'b0; - - //Check for almost_empty - if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) - ideal_almost_empty <= 1'b1; - else - ideal_almost_empty <= 1'b0; - - ideal_rd_count <= num_read_words_sized_i; - - end // else: !if(RD_EN == 1'b1) - end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) - - - /********************************************************* - * Programmable EMPTY flags - *********************************************************/ - //Determine the Assert and Negate thresholds for Programmable Empty - // (Subtract 2 read-sized words when using Preload 0) - - //Single Programmable Empty Constant Threshold - if (C_PROG_EMPTY_TYPE==1) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; - prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; - end - else begin - prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; - prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; - end - - //Two Programmable Empty Constant Thresholds - end else if (C_PROG_EMPTY_TYPE==2) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; - prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; - end - else begin - prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; - prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; - end - - //Single Programmable Empty Constant Threshold - end else if (C_PROG_EMPTY_TYPE==3) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; - prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; - end - else begin - prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; - prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; - - end - //Two Programmable Empty Constant Thresholds - end else if (C_PROG_EMPTY_TYPE==4) begin - if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin - prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; - prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; - end - else begin - prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; - prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; - end - end - - if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) - && RD_EN) begin - prog_empty_d <= 1'b1; - end else if (num_read_words_pe/C_DEPTH_RATIO_WR - <= prog_empty_actual_thresh_assert) begin - prog_empty_d <= 1'b1; - end else if (num_read_words_pe/C_DEPTH_RATIO_WR - > prog_empty_actual_thresh_negate) begin - prog_empty_d <= 1'b0; - end - - - ideal_prog_empty <= prog_empty_d; - num_rd_bits <= next_num_rd_bits; - wr_ptr_rdclk <= wr_ptr; - end //rd_rst_i==0 - end //always - -endmodule // fifo_generator_v4_3_bhv_ver_as - - -/******************************************************************************* - * Declaration of top-level module - ******************************************************************************/ -module fifo_generator_v4_3_bhv_ver_ss - ( - CLK, RST, SRST, DIN, WR_EN, RD_EN, - PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, - PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, - DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, - ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, - PROG_FULL, PROG_EMPTY - ); - -/****************************************************************************** - * Declare user parameters and their defaults - *****************************************************************************/ - parameter C_COMMON_CLOCK = 0; - parameter C_COUNT_TYPE = 0; - parameter C_DATA_COUNT_WIDTH = 2; - parameter C_DEFAULT_VALUE = ""; - parameter C_DIN_WIDTH = 8; - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_ENABLE_RLOCS = 0; - parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model - parameter C_HAS_ALMOST_EMPTY = 0; - parameter C_HAS_ALMOST_FULL = 0; - parameter C_HAS_BACKUP = 0; - parameter C_HAS_DATA_COUNT = 0; - parameter C_HAS_MEMINIT_FILE = 0; - parameter C_HAS_OVERFLOW = 0; - parameter C_HAS_RD_DATA_COUNT = 0; - parameter C_HAS_RD_RST = 0; - parameter C_HAS_RST = 0; - parameter C_HAS_SRST = 0; - parameter C_HAS_UNDERFLOW = 0; - parameter C_HAS_VALID = 0; - parameter C_HAS_WR_ACK = 0; - parameter C_HAS_WR_DATA_COUNT = 0; - parameter C_HAS_WR_RST = 0; - parameter C_IMPLEMENTATION_TYPE = 0; - parameter C_INIT_WR_PNTR_VAL = 0; - parameter C_MEMORY_TYPE = 1; - parameter C_MIF_FILE_NAME = ""; - parameter C_OPTIMIZATION_MODE = 0; - parameter C_OVERFLOW_LOW = 0; - parameter C_PRELOAD_LATENCY = 1; - parameter C_PRELOAD_REGS = 0; - parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; - parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; - parameter C_PROG_EMPTY_TYPE = 0; - parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; - parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; - parameter C_PROG_FULL_TYPE = 0; - parameter C_RD_DATA_COUNT_WIDTH = 2; - parameter C_RD_DEPTH = 256; - parameter C_RD_PNTR_WIDTH = 8; - parameter C_UNDERFLOW_LOW = 0; - parameter C_VALID_LOW = 0; - parameter C_WR_ACK_LOW = 0; - parameter C_WR_DATA_COUNT_WIDTH = 2; - parameter C_WR_DEPTH = 256; - parameter C_WR_PNTR_WIDTH = 8; - parameter C_WR_RESPONSE_LATENCY = 1; - parameter C_FULL_FLAGS_RST_VAL = 1; - parameter C_USE_EMBEDDED_REG = 0; - - -/****************************************************************************** - * Declare Input and Output Ports - *****************************************************************************/ - input CLK; - input [C_DIN_WIDTH-1:0] DIN; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; - input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; - input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; - input RD_EN; - input RST; - input SRST; - input WR_EN; - output ALMOST_EMPTY; - output ALMOST_FULL; - output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; - output [C_DOUT_WIDTH-1:0] DOUT; - output EMPTY; - output FULL; - output OVERFLOW; - output PROG_EMPTY; - output PROG_FULL; - output VALID; - output UNDERFLOW; - output WR_ACK; - -/******************************************************************************* - * Input and output register declarations - ******************************************************************************/ -/******************************************************************************* - * Parameters used as constants - ******************************************************************************/ - //When RST is present, set FULL reset value to '1'. - //If core has no RST, make sure FULL powers-on as '0'. - //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not - //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. - // Therefore, during SRST, all the FULL flags reset to 0. - parameter C_HAS_FAST_FIFO = 0; - parameter C_FIFO_WR_DEPTH = (C_COMMON_CLOCK) ? C_WR_DEPTH : C_WR_DEPTH - 1; - parameter C_FIFO_RD_DEPTH = (C_COMMON_CLOCK) ? C_RD_DEPTH : C_RD_DEPTH - 1; - - /**************************************************************************** - * Internal Registers and wires - ***************************************************************************/ - wire wr_ack_i; - wire overflow_i; - wire underflow_i; - wire valid_i; - wire valid_out; - reg valid_d1; - wire srst_i; - /******************************************************************************* - * Internal registers and wires for internal reset logics - ******************************************************************************/ - reg rst_asreg =0; - reg rst_asreg_d1 =0; - reg rst_asreg_d2 =0; - reg rst_reg =0; - reg rst_d1 =0; - wire rst_comb; - wire rst_i; - - - //Memory which will be used to simulate a FIFO - reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; - reg [31:0] num_bits; - reg [31:0] wr_ptr; - reg [31:0] rd_ptr; - wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; - reg [31:0] num_read_words_q; - wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; - reg [31:0] num_write_words_q; - //Removed power_on_timer in v3.2 (IP2_Im). For all reset types (Async, Sync, or no reset), the power-on values of the flags in the core are modified so that the core is ready to use from the very first clock cycle. - //reg [3:0] power_on_timer; - - //Special ideal FIFO signals - reg [C_DOUT_WIDTH-1:0] ideal_dout; - reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; - wire [C_DOUT_WIDTH-1:0] ideal_dout_out; - reg ideal_wr_ack; - reg ideal_valid; - reg ideal_overflow; - reg ideal_underflow; - reg ideal_full; - reg ideal_empty; - reg ideal_almost_full; - reg ideal_almost_empty; - reg ideal_prog_full; - reg ideal_prog_empty; - - - //MSBs of the counts - wire [C_DATA_COUNT_WIDTH-1:0] ideal_d_count; - - //user specified value for reseting the size of the fifo - reg [C_DOUT_WIDTH-1:0] dout_reset_val; - - - //temporary registers for WR_RESPONSE_LATENCY feature - reg ideal_wr_ack_q; - reg ideal_overflow_q; - - reg prog_full_d; - reg prog_empty_d; - - //Delayed version of RST - reg rst_q; - reg rst_qq; - - /**************************************************************************** - * Function Declarations - ***************************************************************************/ - task write_fifo; - begin - memory[wr_ptr] <= DIN; - if (wr_ptr == 0) begin - wr_ptr <= C_WR_DEPTH - 1; - end else begin - wr_ptr <= wr_ptr - 1; - end - end - endtask // write_fifo - - task read_fifo; - begin - ideal_dout <= memory[rd_ptr]; - if (rd_ptr == 0) begin - rd_ptr <= C_RD_DEPTH - 1; - end else begin - rd_ptr <= rd_ptr - 1; - end - end - endtask - - /**************************************************************************** - * log2_val - * Returns the 'log2' value for the input value for the supported ratios - ***************************************************************************/ - function [31:0] log2_val; - input [31:0] binary_val; - - begin - if (binary_val == 8) begin - log2_val = 3; - end else if (binary_val == 4) begin - log2_val = 2; - end else begin - log2_val = 1; - end - end - endfunction - - /**************************************************************************** - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***************************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - - /***************************************************************************** - * Initialize Signals - ****************************************************************************/ - initial begin - num_bits = 0; - num_read_words_q = 0; - num_write_words_q = 0; - rd_ptr = C_RD_DEPTH -1; - wr_ptr = C_WR_DEPTH -1; - dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); - ideal_dout = dout_reset_val; - ideal_wr_ack = 1'b0; - ideal_valid = 1'b0; - valid_d1 = 1'b0; - ideal_overflow = 1'b0; - ideal_underflow = 1'b0; - //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) - //ideal_full = C_FULL_RESET_VAL; //was in v3.1 - ideal_full = 1'b0; //v3.2 - ideal_empty = 1'b1; - //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) - //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 - ideal_almost_full = 1'b0; - ideal_almost_empty = 1'b1; - //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) - //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 - ideal_prog_full = 1'b0; //v3.2 - ideal_prog_empty = 1'b1; - - //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) - //Therefore, prog_full_d is also changed - //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 - prog_full_d = 1'b0; //v3.2 - prog_empty_d = 1'b1; - - //Removed in v3.2 - //power_on_timer = C_HAS_RST ? 4'h3 : 4'h0; - - //Added these initial values in v3.2 to make it consistent with the synchronization flop stages in the core. - rst_q = 1'b0; - rst_qq = 1'b0; - end - - - /***************************************************************************** - * Assign Internal ideal signals to output ports - ****************************************************************************/ - assign ideal_dout_out= (C_USE_EMBEDDED_REG==1 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - ideal_dout_d1: ideal_dout; - assign DOUT = ideal_dout_out; - //was in v3.1 - //assign FULL = (power_on_timer) ? C_FULL_RESET_VAL : ideal_full; - //v3.2 - assign FULL = ideal_full; - - assign EMPTY = ideal_empty; - //was in v3.1 - //assign ALMOST_FULL = (power_on_timer) ? C_ALMOST_FULL_RESET_VAL : ideal_almost_full; - //v3.2 - assign ALMOST_FULL = ideal_almost_full; - - assign ALMOST_EMPTY = ideal_almost_empty; - - assign ideal_d_count = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; - assign DATA_COUNT = ideal_d_count; - - //was in v3.1 - //assign PROG_FULL = (power_on_timer) ? C_PROG_FULL_RESET_VAL : ideal_prog_full; - //v3.2 - assign PROG_FULL = ideal_prog_full; - - assign PROG_EMPTY = ideal_prog_empty; - - //Handshaking signals can be active low, depending on _LOW parameters - assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; - assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; - assign valid_out = (C_PRELOAD_LATENCY==2 && - (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? - valid_d1: valid_i; - assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; - assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; - - assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; - assign wr_ack_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_wr_ack_q : - (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : - (WR_EN & !FULL); - assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; - assign overflow_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_overflow_q : - (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : - (WR_EN & FULL); - - assign srst_i = C_HAS_SRST ? SRST : 0; - - /******************************************************************************* - * Internal reset logics - ******************************************************************************/ - assign rst_comb = !rst_asreg_d2 && rst_asreg; - assign rst_i = C_HAS_RST ? rst_reg : 0; - - always @(posedge CLK or posedge rst_i) begin - if (rst_i == 1'b1) begin - valid_d1 <= 1'b0; - end else begin - if (srst_i) begin - valid_d1 <= 1'b0; - end else begin - valid_d1 <= valid_i; - end - end - end - always @(posedge CLK or posedge rst_i) begin - if (rst_i == 1'b1) begin - ideal_dout_d1 <= dout_reset_val; - end else begin - if (srst_i) begin - ideal_dout_d1 <= dout_reset_val; - end else begin - ideal_dout_d1 <= ideal_dout; - end - end - end - - always @(posedge CLK or posedge RST) begin - if (RST == 1'b1) begin - rst_asreg <= 1'b1; - end else begin - if (rst_asreg_d1 == 1'b1) begin - rst_asreg <= 1'b0; - end else begin - rst_asreg <= rst_asreg; - end - end - end - - always @(posedge CLK) begin - rst_asreg_d1 <= rst_asreg; - rst_asreg_d2 <= rst_asreg_d1; - end - - always @(posedge CLK or posedge rst_comb) begin - if (rst_comb == 1'b1) begin - rst_reg <= 1'b1; - end else begin - rst_reg <= 1'b0; - end - end - - - /******************************************************************************* - * Write and Read Logics - ******************************************************************************/ - - always @(posedge CLK or posedge rst_i) - begin : gen_wr_ack_resp - - //Register reset - rst_q <= rst_i; - rst_qq <= rst_q; - - //Register output signals to achieve desired WR_RESPONSE latency - if (C_WR_RESPONSE_LATENCY == 2) begin - if (rst_i == 1) begin - ideal_wr_ack_q <= 0; - ideal_overflow_q <= 0; - end else begin - ideal_wr_ack_q <= ideal_wr_ack; - ideal_overflow_q <= ideal_overflow; - end - end - - //Removed in v3.2 - /* - if (rst_i == 1) begin - power_on_timer <= 0; - end else if (power_on_timer > 0) begin - power_on_timer <= power_on_timer -1; - end else begin - power_on_timer <= 0; - end - */ - end // block: gen_wr_ack_resp - - // block memory has a synchronous reset - always @(posedge CLK) begin : gen_fifo_blkmemdout - //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. - //if (rst_i || rst_q || rst_qq) begin //was in v3.1 - if (rst_i || rst_q || srst_i) begin //v3.2 - /******Initialize Read Domain Signals************************************/ - if (C_MEMORY_TYPE == 1) begin - ideal_dout <= dout_reset_val; - end - //v3.2 - //end else begin - //if (C_MEMORY_TYPE == 1 && power_on_timer >= 2) begin //was in v3.1 - // if (C_MEMORY_TYPE == 1) begin //v3.2 - // ideal_dout <= dout_reset_val; - // end - end - end - - always @(posedge CLK or posedge rst_i) begin : gen_fifo - - /****** Reset fifo - Asynchronous Reset*************************************/ - //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. - //if (rst_i || rst_q || rst_qq) begin //was in v3.1 - //if (rst_i || rst_q) begin //v3.2 - if (rst_i ) begin //v3.2 - /******Initialize Generic FIFO constructs********************************/ - num_bits <= 0; - wr_ptr <= C_WR_DEPTH - 1; - rd_ptr <= C_RD_DEPTH - 1; - num_read_words_q <= 0; - num_write_words_q <= 0; - - - /******Initialize Write Domain Signals***********************************/ - ideal_wr_ack <= 0; - ideal_full <= C_FULL_FLAGS_RST_VAL; - ideal_almost_full <= C_FULL_FLAGS_RST_VAL; - - /******Initialize Read Domain Signals************************************/ - if (C_MEMORY_TYPE != 1) begin - ideal_dout <= dout_reset_val; - end - ideal_valid <= 1'b0; - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - end else begin - if (srst_i) begin - // SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. - if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin - /******Initialize Generic FIFO constructs********************************/ - num_bits <= 0; - wr_ptr <= C_WR_DEPTH - 1; - rd_ptr <= C_RD_DEPTH - 1; - num_read_words_q <= 0; - num_write_words_q <= 0; - - /******Initialize Write Domain Signals***********************************/ - ideal_wr_ack <= 0; - ideal_full <= 0; //'0' - ideal_almost_full <= 0; //'0' - - /******Initialize Read Domain Signals************************************/ - //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the above always block. - if (C_MEMORY_TYPE == 2) begin - ideal_dout <= dout_reset_val; - end - ideal_valid <= 1'b0; - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - end - - end else begin //normal operating conditions - /**********************************************************************/ - // Synchronous FIFO Condition #1 : Writing and not reading - /**********************************************************************/ - if (WR_EN & ~RD_EN) begin - - /*********************************/ - //If the FIFO is full, do NOT perform the write, - // update flags accordingly - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - ideal_wr_ack <= 0; - - //still full - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - //write unsuccessful - do not change contents - - // no read attempted - ideal_valid <= 1'b0; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - - /*********************************/ - //If the FIFO is reporting FULL - // (Startup condition) - /*********************************/ - end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin - ideal_wr_ack <= 0; - - //still full - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //write unsuccessful - do not change contents - - // no read attempted - ideal_valid <= 1'b0; - - //FIFO EMPTY in this state can not be determined - //ideal_empty <= 1'b0; - //ideal_almost_empty <= 1'b0; - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - //good write - ideal_wr_ack <= 1; - - //FIFO is one from FULL and going FULL - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= 1'b0; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is 2 from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin - //good write - ideal_wr_ack <= 1; - - //2 from full, and writing, so set almost_full - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - //Add input data - write_fifo; - - //no read attempted - ideal_valid <= 1'b0; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //good write - ideal_wr_ack <= 1; - - //Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= 1'b0; - - //Leaving ALMOST_EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - end else if (num_read_words == 0) begin - // good write - ideal_wr_ack <= 1; - - //Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= 1'b0; - - //Leaving EMPTY (still ALMOST_EMPTY) - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - num_bits <= num_bits + C_DIN_WIDTH; - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - // good write - ideal_wr_ack <= 1; - - //Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Add input data - write_fifo; - - // no read attempted - ideal_valid <= 1'b0; - - //Not near EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - num_bits <= num_bits + C_DIN_WIDTH; - - end // average case - - - /**********************************************************************/ - // Synchronous FIFO Condition #2 : Reading and not writing - /**********************************************************************/ - end else if (~WR_EN & RD_EN) begin - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin - //no write attemped - ideal_wr_ack <= 0; - - //FIFO is not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read will fail - ideal_valid <= 1'b0; - - //FIFO is still empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - //No read - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //no write attempted - ideal_wr_ack <= 0; - - //FIFO is not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read successful - ideal_valid <= 1'b1; - - //This read will make FIFO go empty - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - //Get the data from the FIFO - read_fifo; - num_bits <= num_bits - C_DIN_WIDTH; - - - /*********************************/ - //If the FIFO is 2 from EMPTY - /*********************************/ - end else if (num_read_words == 2) begin - - //no write attempted - ideal_wr_ack <= 0; - - //FIFO is not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read successful - ideal_valid <= 1'b1; - - //FIFO is going ALMOST_EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - //Get the data from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //no write attempted - ideal_wr_ack <= 0; - - //FIFO is leaving ALMOST FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - - /*********************************/ - // FIFO is FULL - /*********************************/ - end else if (num_write_words >= C_FIFO_WR_DEPTH) - begin - //no write attempted - ideal_wr_ack <= 0; - - //FIFO is leaving FULL, but is still ALMOST_FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - //no write attemped - ideal_wr_ack <= 0; - - //Not near empty - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - - end // average read - - - /**********************************************************************/ - // Synchronous FIFO Condition #3 : Reading and writing - /**********************************************************************/ - end else if (WR_EN & RD_EN) begin - - /*********************************/ - // FIFO is FULL - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - - ideal_wr_ack <= 0; - - //Read will be successful, so FIFO will leave FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits - C_DOUT_WIDTH; - - - /*********************************/ - // FIFO is reporting FULL, but it is empty - // (This is a special case, when coming out of RST - /*********************************/ - end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin - - ideal_wr_ack <= 0; - - //Read will be successful, so FIFO will leave FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //Read unsuccessful - ideal_valid <= 1'b0; - - //Report empty condition - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - //Do not read from empty FIFO - // Read from the FIFO - - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //Write successful - ideal_wr_ack <= 1; - - //FIFO will remain ALMOST_FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= 1'b1; - - //Not near empty - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - - //Write successful - ideal_wr_ack <= 1; - - // Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= 1'b1; - - //FIFO will stay ALMOST_EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - end else if (num_read_words == 0) begin - - //Write successful - ideal_wr_ack <= 1; - - // Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read will fail - ideal_valid <= 1'b0; - - //FIFO will leave EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - // No read - num_bits <= num_bits + C_DIN_WIDTH; - - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - - //Write successful - ideal_wr_ack <= 1; - - // Not near FULL - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - // put the data into the FIFO - write_fifo; - - //Read successful - ideal_valid <= 1'b1; - - // Not near EMPTY - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //Read from the FIFO - read_fifo; - num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; - - end // average case - - /**********************************************************************/ - // Synchronous FIFO Condition #4 : Not reading or writing - /*** - *******************************************************************/ - end else begin - - /*********************************/ - // FIFO is FULL - /*********************************/ - if (num_write_words >= C_FIFO_WR_DEPTH) begin - - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b1; - ideal_almost_full <= 1'b1; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //No change to memory - - /*********************************/ - //If the FIFO is one from full - /*********************************/ - end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin - - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b0; - ideal_almost_full <= 1'b1; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //No change to memory - - /*********************************/ - //If the FIFO is ALMOST EMPTY - /*********************************/ - end else if (num_read_words == 1) begin - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b1; - - //No change to memory - - end // almost empty - - - /*********************************/ - //If the FIFO is EMPTY - /*********************************/ - else if (num_read_words == 0) - begin - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b1; - ideal_almost_empty <= 1'b1; - - //No change to memory - - /*********************************/ - //If the FIFO is not near EMPTY or FULL - /*********************************/ - end else begin - - //No write - ideal_wr_ack <= 0; - ideal_full <= 1'b0; - ideal_almost_full <= 1'b0; - - //No read - ideal_valid <= 1'b0; - ideal_empty <= 1'b0; - ideal_almost_empty <= 1'b0; - - //No change to memory - - end // average case - - end // neither reading or writing - - num_read_words_q <= num_read_words; - num_write_words_q <= num_write_words; - - end //normal operating conditions - end - - end // block: gen_fifo - - //Generate overflow and underflow flags seperately - //because they don't support async rst - always @(posedge CLK) begin - ideal_overflow <= WR_EN & ideal_full; - ideal_underflow <= ideal_empty & RD_EN; - end - - always @(posedge CLK or posedge rst_i) begin : gen_fifo_p - - /****** Reset fifo - Async Reset****************************************/ - //The latency of de-assertion of the flags is reduced by 1 to be consistent with the core. - //if (rst_i || rst_q) begin //was in v3.1 - if (rst_i) begin //v3.2 - ideal_prog_full <= C_FULL_FLAGS_RST_VAL; - ideal_prog_empty <= 1'b1; - prog_full_d <= C_FULL_FLAGS_RST_VAL; - prog_empty_d <= 1'b1; - - end else begin - if (srst_i) begin - //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. - if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin - ideal_prog_full <= 1'b0; - ideal_prog_empty <= 1'b1; - prog_full_d <= 1'b0; - prog_empty_d <= 1'b1; - end - end else begin - - /***************************************************************** - * Programmable FULL flags - ****************************************************************/ - //Single constant threshold - if (C_PROG_FULL_TYPE == 1) begin - if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) - && WR_EN && !RD_EN) begin - prog_full_d <= 1'b1; - end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) - && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin //v3.2 - prog_full_d <= 1'b0; - end - - //Dual constant thresholds - end else if (C_PROG_FULL_TYPE == 2) begin - if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) - && WR_EN && !RD_EN) begin - prog_full_d <= 1'b1; - end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) - && RD_EN && !WR_EN) begin - prog_full_d <= 1'b0; - end - - //Single input threshold - end else if (C_PROG_FULL_TYPE == 3) begin - if ((num_write_words == PROG_FULL_THRESH-1) - && WR_EN && !RD_EN) begin - prog_full_d <= 1'b1; - end else if ((num_write_words == PROG_FULL_THRESH) - && !WR_EN && RD_EN) begin - prog_full_d <= 1'b0; - end else if (num_write_words >= PROG_FULL_THRESH) begin - prog_full_d <= 1'b1; - end else if (num_write_words < PROG_FULL_THRESH) begin - prog_full_d <= 1'b0; - end - - //Dual input thresholds - end else begin - if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) - && WR_EN && !RD_EN) begin - prog_full_d <= 1'b1; - end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) - && !WR_EN && RD_EN)begin - prog_full_d <= 1'b0; - end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin - prog_full_d <= 1'b1; - end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin - prog_full_d <= 1'b0; - end - end - - /***************************************************************** - * Programmable EMPTY flags - ****************************************************************/ - //Single constant threshold - if (C_PROG_EMPTY_TYPE == 1) begin - if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= 1'b1; - end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) - && WR_EN && !RD_EN) begin - prog_empty_d <= 1'b0; - end - //Dual constant thresholds - end else if (C_PROG_EMPTY_TYPE == 2) begin - if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= 1'b1; - end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) - && !RD_EN && WR_EN) begin - prog_empty_d <= 1'b0; - end - - //Single input threshold - end else if (C_PROG_EMPTY_TYPE == 3) begin - if ((num_read_words == PROG_EMPTY_THRESH+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= 1'b1; - end else if ((num_read_words == PROG_EMPTY_THRESH) - && !RD_EN && WR_EN) begin - prog_empty_d <= 1'b0; - end else if (num_read_words <= PROG_EMPTY_THRESH) begin - prog_empty_d <= 1'b1; - end else if (num_read_words > PROG_EMPTY_THRESH)begin - prog_empty_d <= 1'b0; - end - - //Dual input thresholds - end else begin - if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin - prog_empty_d <= 1'b1; - end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) - && RD_EN && !WR_EN) begin - prog_empty_d <= 1'b1; - end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin - prog_empty_d <= 1'b0; - end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) - && !RD_EN && WR_EN) begin - prog_empty_d <= 1'b0; - end - end - - ideal_prog_empty <= prog_empty_d; - if (rst_q && !rst_i) begin - ideal_prog_full <= 1'b0; - end else begin - ideal_prog_full <= prog_full_d; - end - - end //if (srst_i) begin - end //if (rst_i) begin - end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p -endmodule // fifo_generator_v4_3_bhv_ver_ss - - -module fifo_generator_v4_3_bhv_ver_preload0 - ( - RD_CLK, - RD_RST, - RD_EN, - FIFOEMPTY, - FIFODATA, - USERDATA, - USERVALID, - USERUNDERFLOW, - USEREMPTY, - USERALMOSTEMPTY, - RAMVALID, - FIFORDEN - ); - - - parameter C_DOUT_RST_VAL = ""; - parameter C_DOUT_WIDTH = 8; - parameter C_HAS_RST = 0; - parameter C_USERVALID_LOW = 0; - parameter C_USERUNDERFLOW_LOW = 0; - - - input RD_CLK; - input RD_RST; - input RD_EN; - input FIFOEMPTY; - input [C_DOUT_WIDTH-1:0] FIFODATA; - output [C_DOUT_WIDTH-1:0] USERDATA; - output USERVALID; - output USERUNDERFLOW; - output USEREMPTY; - output USERALMOSTEMPTY; - output RAMVALID; - output FIFORDEN; - - wire RD_CLK; - wire RD_RST; - wire RD_EN; - wire FIFOEMPTY; - wire [C_DOUT_WIDTH-1:0] FIFODATA; - reg [C_DOUT_WIDTH-1:0] USERDATA; - wire USERVALID; - wire USERUNDERFLOW; - wire USEREMPTY; - wire USERALMOSTEMPTY; - wire RAMVALID; - wire FIFORDEN; - - wire preloadstage1; - wire preloadstage2; - reg ram_valid_i; - reg read_data_valid_i; - wire ram_regout_en; - wire ram_rd_en; - reg empty_i = 1'b1; - reg empty_q = 1'b1; - reg rd_en_q = 1'b0; //Fix for CR:236270 in v3.2 //prasanna - reg almost_empty_i = 1'b1; - reg almost_empty_q = 1'b1; - wire rd_rst_i; - - -/************************************************************************* -* FUNCTIONS -*************************************************************************/ - - /************************************************************************* - * hexstr_conv - * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) - ***********************************************************************/ - function [C_DOUT_WIDTH-1:0] hexstr_conv; - input [(C_DOUT_WIDTH*8)-1:0] def_data; - - integer index,i,j; - reg [3:0] bin; - - begin - index = 0; - hexstr_conv = 'b0; - for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) - begin - case (def_data[7:0]) - 8'b00000000 : - begin - bin = 4'b0000; - i = -1; - end - 8'b00110000 : bin = 4'b0000; - 8'b00110001 : bin = 4'b0001; - 8'b00110010 : bin = 4'b0010; - 8'b00110011 : bin = 4'b0011; - 8'b00110100 : bin = 4'b0100; - 8'b00110101 : bin = 4'b0101; - 8'b00110110 : bin = 4'b0110; - 8'b00110111 : bin = 4'b0111; - 8'b00111000 : bin = 4'b1000; - 8'b00111001 : bin = 4'b1001; - 8'b01000001 : bin = 4'b1010; - 8'b01000010 : bin = 4'b1011; - 8'b01000011 : bin = 4'b1100; - 8'b01000100 : bin = 4'b1101; - 8'b01000101 : bin = 4'b1110; - 8'b01000110 : bin = 4'b1111; - 8'b01100001 : bin = 4'b1010; - 8'b01100010 : bin = 4'b1011; - 8'b01100011 : bin = 4'b1100; - 8'b01100100 : bin = 4'b1101; - 8'b01100101 : bin = 4'b1110; - 8'b01100110 : bin = 4'b1111; - default : - begin - bin = 4'bx; - end - endcase - for( j=0; j<4; j=j+1) - begin - if ((index*4)+j < C_DOUT_WIDTH) - begin - hexstr_conv[(index*4)+j] = bin[j]; - end - end - index = index + 1; - def_data = def_data >> 8; - end - end - endfunction - -initial - begin - ram_valid_i = 1'b0; - read_data_valid_i = 1'b0; - USERDATA = hexstr_conv(C_DOUT_RST_VAL); - end - - - //****************************************************************************** - // connect up optional reset - //****************************************************************************** - assign rd_rst_i = C_HAS_RST ? RD_RST : 0; - - - //****************************************************************************** - // preloadstage2 indicates that stage2 needs to be updated. This is true - // whenever read_data_valid is false, and RAM_valid is true. - //****************************************************************************** - assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); - - //****************************************************************************** - // preloadstage1 indicates that stage1 needs to be updated. This is true - // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is - // false (indicating that Stage1 needs updating), or preloadstage2 is active - // (indicating that Stage2 is going to update, so Stage1, therefore, must - // also be updated to keep it valid. - //****************************************************************************** - assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); - - //****************************************************************************** - // Calculate RAM_REGOUT_EN - // The output registers are controlled by the ram_regout_en signal. - // These registers should be updated either when the output in Stage2 is - // invalid (preloadstage2), OR when the user is reading, in which case the - // Stage2 value will go invalid unless it is replenished. - //****************************************************************************** - assign ram_regout_en = preloadstage2; - - //****************************************************************************** - // Calculate RAM_RD_EN - // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to - // update the value in Stage1. - // One case when this happens is when preloadstage1=true, which indicates - // that the data in Stage1 or Stage2 is invalid, and needs to automatically - // be updated. - // The other case is when the user is reading from the FIFO, which guarantees - // that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is - // replinished by data from the memory. So, as long as the RAM has data in it, - // a read of the RAM should occur. - //****************************************************************************** - assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; - - //****************************************************************************** - // Calculate RAMVALID_P0_OUT - // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. - // - // If the RAM is being read from on this clock cycle (ram_rd_en=1), then - // RAMVALID_P0_OUT is certainly going to be true. - // If the RAM is not being read from, but the output registers are being - // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, - // therefore causing RAMVALID_P0_OUT to be false. - // Otherwise, RAMVALID_P0_OUT will remain unchanged. - //****************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin // PROCESS regout_valid - if (rd_rst_i) // asynchronous reset (active high) - ram_valid_i <= 1'b0; - else - begin - if (ram_rd_en == 1'b1) - ram_valid_i <= 1'b1; - else - if (ram_regout_en == 1'b1) - ram_valid_i <= 1'b0; - else - ram_valid_i <= ram_valid_i; - end //rd_rst_i - end //always - - //****************************************************************************** - // Calculate READ_DATA_VALID - // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. - // Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1, - // such that the data in Stage1 is propogated into Stage2. - //****************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) - read_data_valid_i <= 1'b0; - else - read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN); - end //always - - - //***************************************************************************** - // Calculate EMPTY - // Defined as the inverse of READ_DATA_VALID - // - // Description: - // - // If read_data_valid_i indicates that the output is not valid, - // and there is no valid data on the output of the ram to preload it - // with, then we will report empty. - // - // If there is no valid data on the output of the ram and we are - // reading, then the FIFO will go empty. - // - //***************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) // asynchronous reset (active high) - begin - empty_i <= 1'b1; - empty_q <= 1'b1; - end - else // rising clock edge - begin - empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); - empty_q <= empty_i; - end - end //always - - //Fix for CR:236270 //prasanna - //Register RD_EN from user to calculate USERUNDERFLOW. - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) // asynchronous reset (active high) - begin - rd_en_q <= 1'b0; - end - else // rising clock edge - begin - rd_en_q <= RD_EN; - end - end //always - - - //***************************************************************************** - // Calculate user_almost_empty - // user_almost_empty is defined such that, unless more words are written - // to the FIFO, the next read will cause the FIFO to go EMPTY. - // - // In most cases, whenever the output registers are updated (due to a user - // read or a preload condition), then user_almost_empty will update to - // whatever RAM_EMPTY is. - // - // The exception is when the output is valid, the user is not reading, and - // Stage1 is not empty. In this condition, Stage1 will be preloaded from the - // memory, so we need to make sure user_almost_empty deasserts properly under - // this condition. - //***************************************************************************** - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) // asynchronous reset (active high) - begin - almost_empty_i <= 1'b1; - almost_empty_q <= 1'b1; - end - else // rising clock edge - begin - if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) - begin - almost_empty_i <= FIFOEMPTY; - end - almost_empty_q <= empty_i; - end - end //always - - - assign USEREMPTY = empty_i; - assign USERALMOSTEMPTY = almost_empty_i; - assign FIFORDEN = ram_rd_en; - assign RAMVALID = ram_valid_i; - assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; - //assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & RD_EN) : empty_q & RD_EN; //Bug in v3.1 (CR:236270) - assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //Fix for CR:236270 in v3.2 //prasanna - - always @ (posedge RD_CLK or posedge rd_rst_i) - begin - if (rd_rst_i) // asynchronous reset (active high) - USERDATA <= hexstr_conv(C_DOUT_RST_VAL); - else // rising clock edge - if (ram_regout_en) - USERDATA <= FIFODATA; - end //always - - - - - -endmodule diff --git a/models/M24LC024B.v b/models/M24LC024B.v deleted file mode 100644 index 45e04b450..000000000 --- a/models/M24LC024B.v +++ /dev/null @@ -1,459 +0,0 @@ -// Modified 11/14/07 to simulate the 24lc024, which responds to the address pins - -// ******************************************************************************************************* -// ** ** -// ** M24LC024B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** -// ** ** -// ******************************************************************************************************* -// ** ** -// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING ** -// ** ALL RIGHTS RESERVED ** -// ** ** -// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR ** -// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS ** -// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN ** -// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. ** -// ** ** -// ******************************************************************************************************* -// ** Revision : 1.1 ** -// ** Modified Date : 07/19/2004 ** -// ** Revision History: ** -// ** ** -// ** 02/01/2003: Initial design ** -// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. ** -// ** ** -// ******************************************************************************************************* -// ** TABLE OF CONTENTS ** -// ******************************************************************************************************* -// **---------------------------------------------------------------------------------------------------** -// ** DECLARATIONS ** -// **---------------------------------------------------------------------------------------------------** -// **---------------------------------------------------------------------------------------------------** -// ** INITIALIZATION ** -// **---------------------------------------------------------------------------------------------------** -// **---------------------------------------------------------------------------------------------------** -// ** CORE LOGIC ** -// **---------------------------------------------------------------------------------------------------** -// ** 1.01: START Bit Detection ** -// ** 1.02: STOP Bit Detection ** -// ** 1.03: Input Shift Register ** -// ** 1.04: Input Bit Counter ** -// ** 1.05: Control Byte Register ** -// ** 1.06: Byte Address Register ** -// ** 1.07: Write Data Buffer ** -// ** 1.08: Acknowledge Generator ** -// ** 1.09: Acknowledge Detect ** -// ** 1.10: Write Cycle Timer ** -// ** 1.11: Write Cycle Processor ** -// ** 1.12: Read Data Multiplexor ** -// ** 1.13: Read Data Processor ** -// ** 1.14: SDA Data I/O Buffer ** -// ** ** -// **---------------------------------------------------------------------------------------------------** -// ** DEBUG LOGIC ** -// **---------------------------------------------------------------------------------------------------** -// ** 2.01: Memory Data Bytes ** -// ** 2.02: Write Data Buffer ** -// ** ** -// **---------------------------------------------------------------------------------------------------** -// ** TIMING CHECKS ** -// **---------------------------------------------------------------------------------------------------** -// ** ** -// ******************************************************************************************************* - - -`timescale 1ns/10ps - -module M24LC024B (A0, A1, A2, WP, SDA, SCL, RESET); - - input A0; // unconnected pin - input A1; // unconnected pin - input A2; // unconnected pin - - input WP; // write protect pin - - inout SDA; // serial data I/O - input SCL; // serial data clock - - input RESET; // system reset - - -// ******************************************************************************************************* -// ** DECLARATIONS ** -// ******************************************************************************************************* - - reg SDA_DO; // serial data - output - reg SDA_OE; // serial data - output enable - - wire SDA_DriveEnable; // serial data output enable - reg SDA_DriveEnableDlyd; // serial data output enable - delayed - - reg [03:00] BitCounter; // serial bit counter - - reg START_Rcvd; // START bit received flag - reg STOP_Rcvd; // STOP bit received flag - reg CTRL_Rcvd; // control byte received flag - reg ADDR_Rcvd; // byte address received flag - reg MACK_Rcvd; // master acknowledge received flag - - reg WrCycle; // memory write cycle - reg RdCycle; // memory read cycle - - reg [07:00] ShiftRegister; // input data shift register - - reg [07:00] ControlByte; // control byte register - wire RdWrBit; // read/write control bit - - reg [07:00] StartAddress; // memory access starting address - reg [02:00] PageAddress; // memory page address - - reg [07:00] WrDataByte [0:7]; // memory write data buffer - wire [07:00] RdDataByte; // memory read data - - reg [15:00] WrCounter; // write buffer counter - - reg [02:00] WrPointer; // write buffer pointer - reg [07:00] RdPointer; // read address pointer - - reg WriteActive; // memory write cycle active - - reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array - - integer LoopIndex; // iterative loop index - - integer tAA; // timing parameter - integer tWC; // timing parameter - - -// ******************************************************************************************************* -// ** INITIALIZATION ** -// ******************************************************************************************************* - - initial tAA = 900; // SCL to SDA output delay - initial tWC = 5000000; // memory write cycle time - //initial tWC = 50000; // shortened memory write cycle time to speed up sims - - initial begin - SDA_DO = 0; - SDA_OE = 0; - end - - initial begin - START_Rcvd = 0; - STOP_Rcvd = 0; - CTRL_Rcvd = 0; - ADDR_Rcvd = 0; - MACK_Rcvd = 0; - end - - initial begin - BitCounter = 0; - ControlByte = 0; - end - - initial begin - WrCycle = 0; - RdCycle = 0; - - WriteActive = 0; - end - - -// ******************************************************************************************************* -// ** CORE LOGIC ** -// ******************************************************************************************************* -// ------------------------------------------------------------------------------------------------------- -// 1.01: START Bit Detection -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SDA) begin - if (SCL == 1) begin - START_Rcvd <= 1; - STOP_Rcvd <= 0; - CTRL_Rcvd <= 0; - ADDR_Rcvd <= 0; - MACK_Rcvd <= 0; - - WrCycle <= #1 0; - RdCycle <= #1 0; - - BitCounter <= 0; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.02: STOP Bit Detection -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SDA) begin - if (SCL == 1) begin - START_Rcvd <= 0; - STOP_Rcvd <= 1; - CTRL_Rcvd <= 0; - ADDR_Rcvd <= 0; - MACK_Rcvd <= 0; - - WrCycle <= #1 0; - RdCycle <= #1 0; - - BitCounter <= 10; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.03: Input Shift Register -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - ShiftRegister[00] <= SDA; - ShiftRegister[01] <= ShiftRegister[00]; - ShiftRegister[02] <= ShiftRegister[01]; - ShiftRegister[03] <= ShiftRegister[02]; - ShiftRegister[04] <= ShiftRegister[03]; - ShiftRegister[05] <= ShiftRegister[04]; - ShiftRegister[06] <= ShiftRegister[05]; - ShiftRegister[07] <= ShiftRegister[06]; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.04: Input Bit Counter -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - if (BitCounter < 10) BitCounter <= BitCounter + 1; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.05: Control Byte Register -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (START_Rcvd & (BitCounter == 8)) begin - if (!WriteActive & (ShiftRegister[07:04] == 4'b1010) - & (ShiftRegister[3:1] == {A2,A1,A0})) begin - if (ShiftRegister[00] == 0) WrCycle <= 1; - if (ShiftRegister[00] == 1) RdCycle <= 1; - - ControlByte <= ShiftRegister[07:00]; - - CTRL_Rcvd <= 1; - end - - START_Rcvd <= 0; - end - end - - assign RdWrBit = ControlByte[00]; - -// ------------------------------------------------------------------------------------------------------- -// 1.06: Byte Address Register -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (CTRL_Rcvd & (BitCounter == 8)) begin - if (RdWrBit == 0) begin - StartAddress <= ShiftRegister[07:00]; - RdPointer <= ShiftRegister[07:00]; - - ADDR_Rcvd <= 1; - end - - WrCounter <= 0; - WrPointer <= 0; - - CTRL_Rcvd <= 0; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.07: Write Data Buffer -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (ADDR_Rcvd & (BitCounter == 8)) begin - if ((WP == 0) & (RdWrBit == 0)) begin - WrDataByte[WrPointer] <= ShiftRegister[07:00]; - - WrCounter <= WrCounter + 1; - WrPointer <= WrPointer + 1; - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.08: Acknowledge Generator -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (!WriteActive) begin - if (BitCounter == 8) begin - if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin - SDA_DO <= 0; - SDA_OE <= 1; - end - end - if (BitCounter == 9) begin - BitCounter <= 0; - - if (!RdCycle) begin - SDA_DO <= 0; - SDA_OE <= 0; - end - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.09: Acknowledge Detect -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - if (RdCycle & (BitCounter == 8)) begin - if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1; - end - end - - always @(negedge SCL) MACK_Rcvd <= 0; - -// ------------------------------------------------------------------------------------------------------- -// 1.10: Write Cycle Timer -// ------------------------------------------------------------------------------------------------------- - - always @(posedge STOP_Rcvd) begin - if (WrCycle & (WP == 0) & (WrCounter > 0)) begin - WriteActive = 1; - #(tWC); - WriteActive = 0; - end - end - - always @(posedge STOP_Rcvd) begin - #(1.0); - STOP_Rcvd = 0; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.11: Write Cycle Processor -// ------------------------------------------------------------------------------------------------------- - - always @(posedge WriteActive) begin - for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin - PageAddress = StartAddress[02:00] + LoopIndex; - - MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]]; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.12: Read Data Multiplexor -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (BitCounter == 8) begin - if (WrCycle & ADDR_Rcvd) begin - RdPointer <= StartAddress + WrPointer + 1; - end - if (RdCycle) begin - RdPointer <= RdPointer + 1; - end - end - end - - assign RdDataByte = MemoryBlock[RdPointer[07:00]]; - -// ------------------------------------------------------------------------------------------------------- -// 1.13: Read Data Processor -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (RdCycle) begin - if (BitCounter == 8) begin - SDA_DO <= 0; - SDA_OE <= 0; - end - else if (BitCounter == 9) begin - SDA_DO <= RdDataByte[07]; - - if (MACK_Rcvd) SDA_OE <= 1; - end - else begin - SDA_DO <= RdDataByte[7-BitCounter]; - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.14: SDA Data I/O Buffer -// ------------------------------------------------------------------------------------------------------- - - bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd); - - assign SDA_DriveEnable = !SDA_DO & SDA_OE; - always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable; - - -// ******************************************************************************************************* -// ** DEBUG LOGIC ** -// ******************************************************************************************************* -// ------------------------------------------------------------------------------------------------------- -// 2.01: Memory Data Bytes -// ------------------------------------------------------------------------------------------------------- - - wire [07:00] MemoryByte00 = MemoryBlock[00]; - wire [07:00] MemoryByte01 = MemoryBlock[01]; - wire [07:00] MemoryByte02 = MemoryBlock[02]; - wire [07:00] MemoryByte03 = MemoryBlock[03]; - wire [07:00] MemoryByte04 = MemoryBlock[04]; - wire [07:00] MemoryByte05 = MemoryBlock[05]; - wire [07:00] MemoryByte06 = MemoryBlock[06]; - wire [07:00] MemoryByte07 = MemoryBlock[07]; - - wire [07:00] MemoryByte08 = MemoryBlock[08]; - wire [07:00] MemoryByte09 = MemoryBlock[09]; - wire [07:00] MemoryByte0A = MemoryBlock[10]; - wire [07:00] MemoryByte0B = MemoryBlock[11]; - wire [07:00] MemoryByte0C = MemoryBlock[12]; - wire [07:00] MemoryByte0D = MemoryBlock[13]; - wire [07:00] MemoryByte0E = MemoryBlock[14]; - wire [07:00] MemoryByte0F = MemoryBlock[15]; - -// ------------------------------------------------------------------------------------------------------- -// 2.02: Write Data Buffer -// ------------------------------------------------------------------------------------------------------- - - wire [07:00] WriteData_0 = WrDataByte[00]; - wire [07:00] WriteData_1 = WrDataByte[01]; - wire [07:00] WriteData_2 = WrDataByte[02]; - wire [07:00] WriteData_3 = WrDataByte[03]; - wire [07:00] WriteData_4 = WrDataByte[04]; - wire [07:00] WriteData_5 = WrDataByte[05]; - wire [07:00] WriteData_6 = WrDataByte[06]; - wire [07:00] WriteData_7 = WrDataByte[07]; - - -// ******************************************************************************************************* -// ** TIMING CHECKS ** -// ******************************************************************************************************* - - wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0); - - specify - specparam - tHI = 600, // SCL pulse width - high - tLO = 1300, // SCL pulse width - low - tSU_STA = 600, // SCL to SDA setup time - tHD_STA = 600, // SCL to SDA hold time - tSU_DAT = 100, // SDA to SCL setup time - tSU_STO = 600; // SCL to SDA setup time - - $width (posedge SCL, tHI); - $width (negedge SCL, tLO); - - $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA); - $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT); - $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO); - - $hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA); - endspecify - -endmodule diff --git a/models/M24LC02B.v b/models/M24LC02B.v deleted file mode 100644 index 4d9e2c6e2..000000000 --- a/models/M24LC02B.v +++ /dev/null @@ -1,455 +0,0 @@ -// ******************************************************************************************************* -// ** ** -// ** M24LC02B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** -// ** ** -// ******************************************************************************************************* -// ** ** -// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING ** -// ** ALL RIGHTS RESERVED ** -// ** ** -// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR ** -// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS ** -// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN ** -// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. ** -// ** ** -// ******************************************************************************************************* -// ** Revision : 1.1 ** -// ** Modified Date : 07/19/2004 ** -// ** Revision History: ** -// ** ** -// ** 02/01/2003: Initial design ** -// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. ** -// ** ** -// ******************************************************************************************************* -// ** TABLE OF CONTENTS ** -// ******************************************************************************************************* -// **---------------------------------------------------------------------------------------------------** -// ** DECLARATIONS ** -// **---------------------------------------------------------------------------------------------------** -// **---------------------------------------------------------------------------------------------------** -// ** INITIALIZATION ** -// **---------------------------------------------------------------------------------------------------** -// **---------------------------------------------------------------------------------------------------** -// ** CORE LOGIC ** -// **---------------------------------------------------------------------------------------------------** -// ** 1.01: START Bit Detection ** -// ** 1.02: STOP Bit Detection ** -// ** 1.03: Input Shift Register ** -// ** 1.04: Input Bit Counter ** -// ** 1.05: Control Byte Register ** -// ** 1.06: Byte Address Register ** -// ** 1.07: Write Data Buffer ** -// ** 1.08: Acknowledge Generator ** -// ** 1.09: Acknowledge Detect ** -// ** 1.10: Write Cycle Timer ** -// ** 1.11: Write Cycle Processor ** -// ** 1.12: Read Data Multiplexor ** -// ** 1.13: Read Data Processor ** -// ** 1.14: SDA Data I/O Buffer ** -// ** ** -// **---------------------------------------------------------------------------------------------------** -// ** DEBUG LOGIC ** -// **---------------------------------------------------------------------------------------------------** -// ** 2.01: Memory Data Bytes ** -// ** 2.02: Write Data Buffer ** -// ** ** -// **---------------------------------------------------------------------------------------------------** -// ** TIMING CHECKS ** -// **---------------------------------------------------------------------------------------------------** -// ** ** -// ******************************************************************************************************* - - -`timescale 1ns/10ps - -module M24LC02B (A0, A1, A2, WP, SDA, SCL, RESET); - - input A0; // unconnected pin - input A1; // unconnected pin - input A2; // unconnected pin - - input WP; // write protect pin - - inout SDA; // serial data I/O - input SCL; // serial data clock - - input RESET; // system reset - - -// ******************************************************************************************************* -// ** DECLARATIONS ** -// ******************************************************************************************************* - - reg SDA_DO; // serial data - output - reg SDA_OE; // serial data - output enable - - wire SDA_DriveEnable; // serial data output enable - reg SDA_DriveEnableDlyd; // serial data output enable - delayed - - reg [03:00] BitCounter; // serial bit counter - - reg START_Rcvd; // START bit received flag - reg STOP_Rcvd; // STOP bit received flag - reg CTRL_Rcvd; // control byte received flag - reg ADDR_Rcvd; // byte address received flag - reg MACK_Rcvd; // master acknowledge received flag - - reg WrCycle; // memory write cycle - reg RdCycle; // memory read cycle - - reg [07:00] ShiftRegister; // input data shift register - - reg [07:00] ControlByte; // control byte register - wire RdWrBit; // read/write control bit - - reg [07:00] StartAddress; // memory access starting address - reg [02:00] PageAddress; // memory page address - - reg [07:00] WrDataByte [0:7]; // memory write data buffer - wire [07:00] RdDataByte; // memory read data - - reg [15:00] WrCounter; // write buffer counter - - reg [02:00] WrPointer; // write buffer pointer - reg [07:00] RdPointer; // read address pointer - - reg WriteActive; // memory write cycle active - - reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array - - integer LoopIndex; // iterative loop index - - integer tAA; // timing parameter - integer tWC; // timing parameter - - -// ******************************************************************************************************* -// ** INITIALIZATION ** -// ******************************************************************************************************* - - initial tAA = 900; // SCL to SDA output delay - initial tWC = 5000000; // memory write cycle time - - initial begin - SDA_DO = 0; - SDA_OE = 0; - end - - initial begin - START_Rcvd = 0; - STOP_Rcvd = 0; - CTRL_Rcvd = 0; - ADDR_Rcvd = 0; - MACK_Rcvd = 0; - end - - initial begin - BitCounter = 0; - ControlByte = 0; - end - - initial begin - WrCycle = 0; - RdCycle = 0; - - WriteActive = 0; - end - - -// ******************************************************************************************************* -// ** CORE LOGIC ** -// ******************************************************************************************************* -// ------------------------------------------------------------------------------------------------------- -// 1.01: START Bit Detection -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SDA) begin - if (SCL == 1) begin - START_Rcvd <= 1; - STOP_Rcvd <= 0; - CTRL_Rcvd <= 0; - ADDR_Rcvd <= 0; - MACK_Rcvd <= 0; - - WrCycle <= #1 0; - RdCycle <= #1 0; - - BitCounter <= 0; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.02: STOP Bit Detection -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SDA) begin - if (SCL == 1) begin - START_Rcvd <= 0; - STOP_Rcvd <= 1; - CTRL_Rcvd <= 0; - ADDR_Rcvd <= 0; - MACK_Rcvd <= 0; - - WrCycle <= #1 0; - RdCycle <= #1 0; - - BitCounter <= 10; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.03: Input Shift Register -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - ShiftRegister[00] <= SDA; - ShiftRegister[01] <= ShiftRegister[00]; - ShiftRegister[02] <= ShiftRegister[01]; - ShiftRegister[03] <= ShiftRegister[02]; - ShiftRegister[04] <= ShiftRegister[03]; - ShiftRegister[05] <= ShiftRegister[04]; - ShiftRegister[06] <= ShiftRegister[05]; - ShiftRegister[07] <= ShiftRegister[06]; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.04: Input Bit Counter -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - if (BitCounter < 10) BitCounter <= BitCounter + 1; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.05: Control Byte Register -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (START_Rcvd & (BitCounter == 8)) begin - if (!WriteActive & (ShiftRegister[07:04] == 4'b1010)) begin - if (ShiftRegister[00] == 0) WrCycle <= 1; - if (ShiftRegister[00] == 1) RdCycle <= 1; - - ControlByte <= ShiftRegister[07:00]; - - CTRL_Rcvd <= 1; - end - - START_Rcvd <= 0; - end - end - - assign RdWrBit = ControlByte[00]; - -// ------------------------------------------------------------------------------------------------------- -// 1.06: Byte Address Register -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (CTRL_Rcvd & (BitCounter == 8)) begin - if (RdWrBit == 0) begin - StartAddress <= ShiftRegister[07:00]; - RdPointer <= ShiftRegister[07:00]; - - ADDR_Rcvd <= 1; - end - - WrCounter <= 0; - WrPointer <= 0; - - CTRL_Rcvd <= 0; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.07: Write Data Buffer -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (ADDR_Rcvd & (BitCounter == 8)) begin - if ((WP == 0) & (RdWrBit == 0)) begin - WrDataByte[WrPointer] <= ShiftRegister[07:00]; - - WrCounter <= WrCounter + 1; - WrPointer <= WrPointer + 1; - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.08: Acknowledge Generator -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (!WriteActive) begin - if (BitCounter == 8) begin - if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin - SDA_DO <= 0; - SDA_OE <= 1; - end - end - if (BitCounter == 9) begin - BitCounter <= 0; - - if (!RdCycle) begin - SDA_DO <= 0; - SDA_OE <= 0; - end - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.09: Acknowledge Detect -// ------------------------------------------------------------------------------------------------------- - - always @(posedge SCL) begin - if (RdCycle & (BitCounter == 8)) begin - if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1; - end - end - - always @(negedge SCL) MACK_Rcvd <= 0; - -// ------------------------------------------------------------------------------------------------------- -// 1.10: Write Cycle Timer -// ------------------------------------------------------------------------------------------------------- - - always @(posedge STOP_Rcvd) begin - if (WrCycle & (WP == 0) & (WrCounter > 0)) begin - WriteActive = 1; - #(tWC); - WriteActive = 0; - end - end - - always @(posedge STOP_Rcvd) begin - #(1.0); - STOP_Rcvd = 0; - end - -// ------------------------------------------------------------------------------------------------------- -// 1.11: Write Cycle Processor -// ------------------------------------------------------------------------------------------------------- - - always @(posedge WriteActive) begin - for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin - PageAddress = StartAddress[02:00] + LoopIndex; - - MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]]; - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.12: Read Data Multiplexor -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (BitCounter == 8) begin - if (WrCycle & ADDR_Rcvd) begin - RdPointer <= StartAddress + WrPointer + 1; - end - if (RdCycle) begin - RdPointer <= RdPointer + 1; - end - end - end - - assign RdDataByte = MemoryBlock[RdPointer[07:00]]; - -// ------------------------------------------------------------------------------------------------------- -// 1.13: Read Data Processor -// ------------------------------------------------------------------------------------------------------- - - always @(negedge SCL) begin - if (RdCycle) begin - if (BitCounter == 8) begin - SDA_DO <= 0; - SDA_OE <= 0; - end - else if (BitCounter == 9) begin - SDA_DO <= RdDataByte[07]; - - if (MACK_Rcvd) SDA_OE <= 1; - end - else begin - SDA_DO <= RdDataByte[7-BitCounter]; - end - end - end - -// ------------------------------------------------------------------------------------------------------- -// 1.14: SDA Data I/O Buffer -// ------------------------------------------------------------------------------------------------------- - - bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd); - - assign SDA_DriveEnable = !SDA_DO & SDA_OE; - always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable; - - -// ******************************************************************************************************* -// ** DEBUG LOGIC ** -// ******************************************************************************************************* -// ------------------------------------------------------------------------------------------------------- -// 2.01: Memory Data Bytes -// ------------------------------------------------------------------------------------------------------- - - wire [07:00] MemoryByte00 = MemoryBlock[00]; - wire [07:00] MemoryByte01 = MemoryBlock[01]; - wire [07:00] MemoryByte02 = MemoryBlock[02]; - wire [07:00] MemoryByte03 = MemoryBlock[03]; - wire [07:00] MemoryByte04 = MemoryBlock[04]; - wire [07:00] MemoryByte05 = MemoryBlock[05]; - wire [07:00] MemoryByte06 = MemoryBlock[06]; - wire [07:00] MemoryByte07 = MemoryBlock[07]; - - wire [07:00] MemoryByte08 = MemoryBlock[08]; - wire [07:00] MemoryByte09 = MemoryBlock[09]; - wire [07:00] MemoryByte0A = MemoryBlock[10]; - wire [07:00] MemoryByte0B = MemoryBlock[11]; - wire [07:00] MemoryByte0C = MemoryBlock[12]; - wire [07:00] MemoryByte0D = MemoryBlock[13]; - wire [07:00] MemoryByte0E = MemoryBlock[14]; - wire [07:00] MemoryByte0F = MemoryBlock[15]; - -// ------------------------------------------------------------------------------------------------------- -// 2.02: Write Data Buffer -// ------------------------------------------------------------------------------------------------------- - - wire [07:00] WriteData_0 = WrDataByte[00]; - wire [07:00] WriteData_1 = WrDataByte[01]; - wire [07:00] WriteData_2 = WrDataByte[02]; - wire [07:00] WriteData_3 = WrDataByte[03]; - wire [07:00] WriteData_4 = WrDataByte[04]; - wire [07:00] WriteData_5 = WrDataByte[05]; - wire [07:00] WriteData_6 = WrDataByte[06]; - wire [07:00] WriteData_7 = WrDataByte[07]; - - -// ******************************************************************************************************* -// ** TIMING CHECKS ** -// ******************************************************************************************************* - - wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0); - - specify - specparam - tHI = 600, // SCL pulse width - high - tLO = 1300, // SCL pulse width - low - tSU_STA = 600, // SCL to SDA setup time - tHD_STA = 600, // SCL to SDA hold time - tSU_DAT = 100, // SDA to SCL setup time - tSU_STO = 600; // SCL to SDA setup time - - $width (posedge SCL, tHI); - $width (negedge SCL, tLO); - - $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA); - $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT); - $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO); - - $hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA); - endspecify - -endmodule diff --git a/models/MULT18X18S.v b/models/MULT18X18S.v deleted file mode 100644 index 5d39eeaa6..000000000 --- a/models/MULT18X18S.v +++ /dev/null @@ -1,20 +0,0 @@ - -// Model of the Xilinx mult18x18s for signed 18x18 bit multiplies, -// As in the Spartan 3 series - -module MULT18X18S - (output reg signed [35:0] P, - input signed [17:0] A, - input signed [17:0] B, - input C, // Clock - input CE, // Clock Enable - input R // Synchronous Reset - ); - - always @(posedge C) - if(R) - P <= 36'sd0; - else if(CE) - P <= A * B; - -endmodule // MULT18X18S diff --git a/models/RAMB16_S36_S36.v b/models/RAMB16_S36_S36.v deleted file mode 100644 index f1a92c7ce..000000000 --- a/models/RAMB16_S36_S36.v +++ /dev/null @@ -1,2194 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2005 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Functional Simulation Library Component -// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM -// /___/ /\ Filename : RAMB16_S36_S36.v -// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// End Revision - -`ifdef legacy_model - -`timescale 1 ps / 1 ps - -module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); - - parameter INIT_A = 36'h0; - parameter INIT_B = 36'h0; - parameter SRVAL_A = 36'h0; - parameter SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - localparam SETUP_ALL = 1000; - localparam SETUP_READ_FIRST = 3000; - - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - output [31:0] DOA; - output [3:0] DOPA; - reg [31:0] doa_out; - reg [3:0] dopa_out; - wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31; - wire dopa0_out, dopa1_out, dopa2_out, dopa3_out; - - input [8:0] ADDRA; - input [31:0] DIA; - input [3:0] DIPA; - input ENA, CLKA, WEA, SSRA; - - output [31:0] DOB; - output [3:0] DOPB; - reg [31:0] dob_out; - reg [3:0] dopb_out; - wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; - wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; - - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB, CLKB, WEB, SSRB; - - reg [18431:0] mem; - reg [8:0] count; - reg [1:0] wr_mode_a, wr_mode_b; - - reg [5:0] dmi, dbi; - reg [5:0] pmi, pbi; - - wire [8:0] addra_int; - reg [8:0] addra_reg; - wire [31:0] dia_int; - wire [3:0] dipa_int; - wire ena_int, clka_int, wea_int, ssra_int; - reg ena_reg, wea_reg, ssra_reg; - wire [8:0] addrb_int; - reg [8:0] addrb_reg; - wire [31:0] dib_int; - wire [3:0] dipb_int; - wire enb_int, clkb_int, web_int, ssrb_int; - reg display_flag; - reg enb_reg, web_reg, ssrb_reg; - - time time_clka, time_clkb; - time time_clka_clkb; - time time_clkb_clka; - - reg setup_all_a_b; - reg setup_all_b_a; - reg setup_zero; - reg setup_rf_a_b; - reg setup_rf_b_a; - reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; - reg memory_collision, memory_collision_a_b, memory_collision_b_a; - reg address_collision, address_collision_a_b, address_collision_b_a; - reg change_clka; - reg change_clkb; - - wire [14:0] data_addra_int; - wire [14:0] data_addra_reg; - wire [14:0] data_addrb_int; - wire [14:0] data_addrb_reg; - wire [15:0] parity_addra_int; - wire [15:0] parity_addra_reg; - wire [15:0] parity_addrb_int; - wire [15:0] parity_addrb_reg; - - tri0 GSR = glbl.GSR; - - always @(GSR) - if (GSR) begin - assign doa_out = INIT_A[31:0]; - assign dopa_out = INIT_A[35:32]; - assign dob_out = INIT_B[31:0]; - assign dopb_out = INIT_B[35:32]; - end - else begin - deassign doa_out; - deassign dopa_out; - deassign dob_out; - deassign dopb_out; - end - - buf b_doa_out0 (doa_out0, doa_out[0]); - buf b_doa_out1 (doa_out1, doa_out[1]); - buf b_doa_out2 (doa_out2, doa_out[2]); - buf b_doa_out3 (doa_out3, doa_out[3]); - buf b_doa_out4 (doa_out4, doa_out[4]); - buf b_doa_out5 (doa_out5, doa_out[5]); - buf b_doa_out6 (doa_out6, doa_out[6]); - buf b_doa_out7 (doa_out7, doa_out[7]); - buf b_doa_out8 (doa_out8, doa_out[8]); - buf b_doa_out9 (doa_out9, doa_out[9]); - buf b_doa_out10 (doa_out10, doa_out[10]); - buf b_doa_out11 (doa_out11, doa_out[11]); - buf b_doa_out12 (doa_out12, doa_out[12]); - buf b_doa_out13 (doa_out13, doa_out[13]); - buf b_doa_out14 (doa_out14, doa_out[14]); - buf b_doa_out15 (doa_out15, doa_out[15]); - buf b_doa_out16 (doa_out16, doa_out[16]); - buf b_doa_out17 (doa_out17, doa_out[17]); - buf b_doa_out18 (doa_out18, doa_out[18]); - buf b_doa_out19 (doa_out19, doa_out[19]); - buf b_doa_out20 (doa_out20, doa_out[20]); - buf b_doa_out21 (doa_out21, doa_out[21]); - buf b_doa_out22 (doa_out22, doa_out[22]); - buf b_doa_out23 (doa_out23, doa_out[23]); - buf b_doa_out24 (doa_out24, doa_out[24]); - buf b_doa_out25 (doa_out25, doa_out[25]); - buf b_doa_out26 (doa_out26, doa_out[26]); - buf b_doa_out27 (doa_out27, doa_out[27]); - buf b_doa_out28 (doa_out28, doa_out[28]); - buf b_doa_out29 (doa_out29, doa_out[29]); - buf b_doa_out30 (doa_out30, doa_out[30]); - buf b_doa_out31 (doa_out31, doa_out[31]); - buf b_dopa_out0 (dopa_out0, dopa_out[0]); - buf b_dopa_out1 (dopa_out1, dopa_out[1]); - buf b_dopa_out2 (dopa_out2, dopa_out[2]); - buf b_dopa_out3 (dopa_out3, dopa_out[3]); - buf b_dob_out0 (dob_out0, dob_out[0]); - buf b_dob_out1 (dob_out1, dob_out[1]); - buf b_dob_out2 (dob_out2, dob_out[2]); - buf b_dob_out3 (dob_out3, dob_out[3]); - buf b_dob_out4 (dob_out4, dob_out[4]); - buf b_dob_out5 (dob_out5, dob_out[5]); - buf b_dob_out6 (dob_out6, dob_out[6]); - buf b_dob_out7 (dob_out7, dob_out[7]); - buf b_dob_out8 (dob_out8, dob_out[8]); - buf b_dob_out9 (dob_out9, dob_out[9]); - buf b_dob_out10 (dob_out10, dob_out[10]); - buf b_dob_out11 (dob_out11, dob_out[11]); - buf b_dob_out12 (dob_out12, dob_out[12]); - buf b_dob_out13 (dob_out13, dob_out[13]); - buf b_dob_out14 (dob_out14, dob_out[14]); - buf b_dob_out15 (dob_out15, dob_out[15]); - buf b_dob_out16 (dob_out16, dob_out[16]); - buf b_dob_out17 (dob_out17, dob_out[17]); - buf b_dob_out18 (dob_out18, dob_out[18]); - buf b_dob_out19 (dob_out19, dob_out[19]); - buf b_dob_out20 (dob_out20, dob_out[20]); - buf b_dob_out21 (dob_out21, dob_out[21]); - buf b_dob_out22 (dob_out22, dob_out[22]); - buf b_dob_out23 (dob_out23, dob_out[23]); - buf b_dob_out24 (dob_out24, dob_out[24]); - buf b_dob_out25 (dob_out25, dob_out[25]); - buf b_dob_out26 (dob_out26, dob_out[26]); - buf b_dob_out27 (dob_out27, dob_out[27]); - buf b_dob_out28 (dob_out28, dob_out[28]); - buf b_dob_out29 (dob_out29, dob_out[29]); - buf b_dob_out30 (dob_out30, dob_out[30]); - buf b_dob_out31 (dob_out31, dob_out[31]); - buf b_dopb_out0 (dopb_out0, dopb_out[0]); - buf b_dopb_out1 (dopb_out1, dopb_out[1]); - buf b_dopb_out2 (dopb_out2, dopb_out[2]); - buf b_dopb_out3 (dopb_out3, dopb_out[3]); - - buf b_doa0 (DOA[0], doa_out0); - buf b_doa1 (DOA[1], doa_out1); - buf b_doa2 (DOA[2], doa_out2); - buf b_doa3 (DOA[3], doa_out3); - buf b_doa4 (DOA[4], doa_out4); - buf b_doa5 (DOA[5], doa_out5); - buf b_doa6 (DOA[6], doa_out6); - buf b_doa7 (DOA[7], doa_out7); - buf b_doa8 (DOA[8], doa_out8); - buf b_doa9 (DOA[9], doa_out9); - buf b_doa10 (DOA[10], doa_out10); - buf b_doa11 (DOA[11], doa_out11); - buf b_doa12 (DOA[12], doa_out12); - buf b_doa13 (DOA[13], doa_out13); - buf b_doa14 (DOA[14], doa_out14); - buf b_doa15 (DOA[15], doa_out15); - buf b_doa16 (DOA[16], doa_out16); - buf b_doa17 (DOA[17], doa_out17); - buf b_doa18 (DOA[18], doa_out18); - buf b_doa19 (DOA[19], doa_out19); - buf b_doa20 (DOA[20], doa_out20); - buf b_doa21 (DOA[21], doa_out21); - buf b_doa22 (DOA[22], doa_out22); - buf b_doa23 (DOA[23], doa_out23); - buf b_doa24 (DOA[24], doa_out24); - buf b_doa25 (DOA[25], doa_out25); - buf b_doa26 (DOA[26], doa_out26); - buf b_doa27 (DOA[27], doa_out27); - buf b_doa28 (DOA[28], doa_out28); - buf b_doa29 (DOA[29], doa_out29); - buf b_doa30 (DOA[30], doa_out30); - buf b_doa31 (DOA[31], doa_out31); - buf b_dopa0 (DOPA[0], dopa_out0); - buf b_dopa1 (DOPA[1], dopa_out1); - buf b_dopa2 (DOPA[2], dopa_out2); - buf b_dopa3 (DOPA[3], dopa_out3); - buf b_dob0 (DOB[0], dob_out0); - buf b_dob1 (DOB[1], dob_out1); - buf b_dob2 (DOB[2], dob_out2); - buf b_dob3 (DOB[3], dob_out3); - buf b_dob4 (DOB[4], dob_out4); - buf b_dob5 (DOB[5], dob_out5); - buf b_dob6 (DOB[6], dob_out6); - buf b_dob7 (DOB[7], dob_out7); - buf b_dob8 (DOB[8], dob_out8); - buf b_dob9 (DOB[9], dob_out9); - buf b_dob10 (DOB[10], dob_out10); - buf b_dob11 (DOB[11], dob_out11); - buf b_dob12 (DOB[12], dob_out12); - buf b_dob13 (DOB[13], dob_out13); - buf b_dob14 (DOB[14], dob_out14); - buf b_dob15 (DOB[15], dob_out15); - buf b_dob16 (DOB[16], dob_out16); - buf b_dob17 (DOB[17], dob_out17); - buf b_dob18 (DOB[18], dob_out18); - buf b_dob19 (DOB[19], dob_out19); - buf b_dob20 (DOB[20], dob_out20); - buf b_dob21 (DOB[21], dob_out21); - buf b_dob22 (DOB[22], dob_out22); - buf b_dob23 (DOB[23], dob_out23); - buf b_dob24 (DOB[24], dob_out24); - buf b_dob25 (DOB[25], dob_out25); - buf b_dob26 (DOB[26], dob_out26); - buf b_dob27 (DOB[27], dob_out27); - buf b_dob28 (DOB[28], dob_out28); - buf b_dob29 (DOB[29], dob_out29); - buf b_dob30 (DOB[30], dob_out30); - buf b_dob31 (DOB[31], dob_out31); - buf b_dopb0 (DOPB[0], dopb_out0); - buf b_dopb1 (DOPB[1], dopb_out1); - buf b_dopb2 (DOPB[2], dopb_out2); - buf b_dopb3 (DOPB[3], dopb_out3); - - buf b_addra_0 (addra_int[0], ADDRA[0]); - buf b_addra_1 (addra_int[1], ADDRA[1]); - buf b_addra_2 (addra_int[2], ADDRA[2]); - buf b_addra_3 (addra_int[3], ADDRA[3]); - buf b_addra_4 (addra_int[4], ADDRA[4]); - buf b_addra_5 (addra_int[5], ADDRA[5]); - buf b_addra_6 (addra_int[6], ADDRA[6]); - buf b_addra_7 (addra_int[7], ADDRA[7]); - buf b_addra_8 (addra_int[8], ADDRA[8]); - buf b_dia_0 (dia_int[0], DIA[0]); - buf b_dia_1 (dia_int[1], DIA[1]); - buf b_dia_2 (dia_int[2], DIA[2]); - buf b_dia_3 (dia_int[3], DIA[3]); - buf b_dia_4 (dia_int[4], DIA[4]); - buf b_dia_5 (dia_int[5], DIA[5]); - buf b_dia_6 (dia_int[6], DIA[6]); - buf b_dia_7 (dia_int[7], DIA[7]); - buf b_dia_8 (dia_int[8], DIA[8]); - buf b_dia_9 (dia_int[9], DIA[9]); - buf b_dia_10 (dia_int[10], DIA[10]); - buf b_dia_11 (dia_int[11], DIA[11]); - buf b_dia_12 (dia_int[12], DIA[12]); - buf b_dia_13 (dia_int[13], DIA[13]); - buf b_dia_14 (dia_int[14], DIA[14]); - buf b_dia_15 (dia_int[15], DIA[15]); - buf b_dia_16 (dia_int[16], DIA[16]); - buf b_dia_17 (dia_int[17], DIA[17]); - buf b_dia_18 (dia_int[18], DIA[18]); - buf b_dia_19 (dia_int[19], DIA[19]); - buf b_dia_20 (dia_int[20], DIA[20]); - buf b_dia_21 (dia_int[21], DIA[21]); - buf b_dia_22 (dia_int[22], DIA[22]); - buf b_dia_23 (dia_int[23], DIA[23]); - buf b_dia_24 (dia_int[24], DIA[24]); - buf b_dia_25 (dia_int[25], DIA[25]); - buf b_dia_26 (dia_int[26], DIA[26]); - buf b_dia_27 (dia_int[27], DIA[27]); - buf b_dia_28 (dia_int[28], DIA[28]); - buf b_dia_29 (dia_int[29], DIA[29]); - buf b_dia_30 (dia_int[30], DIA[30]); - buf b_dia_31 (dia_int[31], DIA[31]); - buf b_dipa_0 (dipa_int[0], DIPA[0]); - buf b_dipa_1 (dipa_int[1], DIPA[1]); - buf b_dipa_2 (dipa_int[2], DIPA[2]); - buf b_dipa_3 (dipa_int[3], DIPA[3]); - buf b_ena (ena_int, ENA); - buf b_clka (clka_int, CLKA); - buf b_ssra (ssra_int, SSRA); - buf b_wea (wea_int, WEA); - buf b_addrb_0 (addrb_int[0], ADDRB[0]); - buf b_addrb_1 (addrb_int[1], ADDRB[1]); - buf b_addrb_2 (addrb_int[2], ADDRB[2]); - buf b_addrb_3 (addrb_int[3], ADDRB[3]); - buf b_addrb_4 (addrb_int[4], ADDRB[4]); - buf b_addrb_5 (addrb_int[5], ADDRB[5]); - buf b_addrb_6 (addrb_int[6], ADDRB[6]); - buf b_addrb_7 (addrb_int[7], ADDRB[7]); - buf b_addrb_8 (addrb_int[8], ADDRB[8]); - buf b_dib_0 (dib_int[0], DIB[0]); - buf b_dib_1 (dib_int[1], DIB[1]); - buf b_dib_2 (dib_int[2], DIB[2]); - buf b_dib_3 (dib_int[3], DIB[3]); - buf b_dib_4 (dib_int[4], DIB[4]); - buf b_dib_5 (dib_int[5], DIB[5]); - buf b_dib_6 (dib_int[6], DIB[6]); - buf b_dib_7 (dib_int[7], DIB[7]); - buf b_dib_8 (dib_int[8], DIB[8]); - buf b_dib_9 (dib_int[9], DIB[9]); - buf b_dib_10 (dib_int[10], DIB[10]); - buf b_dib_11 (dib_int[11], DIB[11]); - buf b_dib_12 (dib_int[12], DIB[12]); - buf b_dib_13 (dib_int[13], DIB[13]); - buf b_dib_14 (dib_int[14], DIB[14]); - buf b_dib_15 (dib_int[15], DIB[15]); - buf b_dib_16 (dib_int[16], DIB[16]); - buf b_dib_17 (dib_int[17], DIB[17]); - buf b_dib_18 (dib_int[18], DIB[18]); - buf b_dib_19 (dib_int[19], DIB[19]); - buf b_dib_20 (dib_int[20], DIB[20]); - buf b_dib_21 (dib_int[21], DIB[21]); - buf b_dib_22 (dib_int[22], DIB[22]); - buf b_dib_23 (dib_int[23], DIB[23]); - buf b_dib_24 (dib_int[24], DIB[24]); - buf b_dib_25 (dib_int[25], DIB[25]); - buf b_dib_26 (dib_int[26], DIB[26]); - buf b_dib_27 (dib_int[27], DIB[27]); - buf b_dib_28 (dib_int[28], DIB[28]); - buf b_dib_29 (dib_int[29], DIB[29]); - buf b_dib_30 (dib_int[30], DIB[30]); - buf b_dib_31 (dib_int[31], DIB[31]); - buf b_dipb_0 (dipb_int[0], DIPB[0]); - buf b_dipb_1 (dipb_int[1], DIPB[1]); - buf b_dipb_2 (dipb_int[2], DIPB[2]); - buf b_dipb_3 (dipb_int[3], DIPB[3]); - buf b_enb (enb_int, ENB); - buf b_clkb (clkb_int, CLKB); - buf b_ssrb (ssrb_int, SSRB); - buf b_web (web_int, WEB); - - initial begin - for (count = 0; count < 256; count = count + 1) begin - mem[count] <= INIT_00[count]; - mem[256 * 1 + count] <= INIT_01[count]; - mem[256 * 2 + count] <= INIT_02[count]; - mem[256 * 3 + count] <= INIT_03[count]; - mem[256 * 4 + count] <= INIT_04[count]; - mem[256 * 5 + count] <= INIT_05[count]; - mem[256 * 6 + count] <= INIT_06[count]; - mem[256 * 7 + count] <= INIT_07[count]; - mem[256 * 8 + count] <= INIT_08[count]; - mem[256 * 9 + count] <= INIT_09[count]; - mem[256 * 10 + count] <= INIT_0A[count]; - mem[256 * 11 + count] <= INIT_0B[count]; - mem[256 * 12 + count] <= INIT_0C[count]; - mem[256 * 13 + count] <= INIT_0D[count]; - mem[256 * 14 + count] <= INIT_0E[count]; - mem[256 * 15 + count] <= INIT_0F[count]; - mem[256 * 16 + count] <= INIT_10[count]; - mem[256 * 17 + count] <= INIT_11[count]; - mem[256 * 18 + count] <= INIT_12[count]; - mem[256 * 19 + count] <= INIT_13[count]; - mem[256 * 20 + count] <= INIT_14[count]; - mem[256 * 21 + count] <= INIT_15[count]; - mem[256 * 22 + count] <= INIT_16[count]; - mem[256 * 23 + count] <= INIT_17[count]; - mem[256 * 24 + count] <= INIT_18[count]; - mem[256 * 25 + count] <= INIT_19[count]; - mem[256 * 26 + count] <= INIT_1A[count]; - mem[256 * 27 + count] <= INIT_1B[count]; - mem[256 * 28 + count] <= INIT_1C[count]; - mem[256 * 29 + count] <= INIT_1D[count]; - mem[256 * 30 + count] <= INIT_1E[count]; - mem[256 * 31 + count] <= INIT_1F[count]; - mem[256 * 32 + count] <= INIT_20[count]; - mem[256 * 33 + count] <= INIT_21[count]; - mem[256 * 34 + count] <= INIT_22[count]; - mem[256 * 35 + count] <= INIT_23[count]; - mem[256 * 36 + count] <= INIT_24[count]; - mem[256 * 37 + count] <= INIT_25[count]; - mem[256 * 38 + count] <= INIT_26[count]; - mem[256 * 39 + count] <= INIT_27[count]; - mem[256 * 40 + count] <= INIT_28[count]; - mem[256 * 41 + count] <= INIT_29[count]; - mem[256 * 42 + count] <= INIT_2A[count]; - mem[256 * 43 + count] <= INIT_2B[count]; - mem[256 * 44 + count] <= INIT_2C[count]; - mem[256 * 45 + count] <= INIT_2D[count]; - mem[256 * 46 + count] <= INIT_2E[count]; - mem[256 * 47 + count] <= INIT_2F[count]; - mem[256 * 48 + count] <= INIT_30[count]; - mem[256 * 49 + count] <= INIT_31[count]; - mem[256 * 50 + count] <= INIT_32[count]; - mem[256 * 51 + count] <= INIT_33[count]; - mem[256 * 52 + count] <= INIT_34[count]; - mem[256 * 53 + count] <= INIT_35[count]; - mem[256 * 54 + count] <= INIT_36[count]; - mem[256 * 55 + count] <= INIT_37[count]; - mem[256 * 56 + count] <= INIT_38[count]; - mem[256 * 57 + count] <= INIT_39[count]; - mem[256 * 58 + count] <= INIT_3A[count]; - mem[256 * 59 + count] <= INIT_3B[count]; - mem[256 * 60 + count] <= INIT_3C[count]; - mem[256 * 61 + count] <= INIT_3D[count]; - mem[256 * 62 + count] <= INIT_3E[count]; - mem[256 * 63 + count] <= INIT_3F[count]; - mem[256 * 64 + count] <= INITP_00[count]; - mem[256 * 65 + count] <= INITP_01[count]; - mem[256 * 66 + count] <= INITP_02[count]; - mem[256 * 67 + count] <= INITP_03[count]; - mem[256 * 68 + count] <= INITP_04[count]; - mem[256 * 69 + count] <= INITP_05[count]; - mem[256 * 70 + count] <= INITP_06[count]; - mem[256 * 71 + count] <= INITP_07[count]; - end - address_collision <= 0; - address_collision_a_b <= 0; - address_collision_b_a <= 0; - change_clka <= 0; - change_clkb <= 0; - data_collision <= 0; - data_collision_a_b <= 0; - data_collision_b_a <= 0; - memory_collision <= 0; - memory_collision_a_b <= 0; - memory_collision_b_a <= 0; - setup_all_a_b <= 0; - setup_all_b_a <= 0; - setup_zero <= 0; - setup_rf_a_b <= 0; - setup_rf_b_a <= 0; - end - - assign data_addra_int = addra_int * 32; - assign data_addra_reg = addra_reg * 32; - assign data_addrb_int = addrb_int * 32; - assign data_addrb_reg = addrb_reg * 32; - assign parity_addra_int = 16384 + addra_int * 4; - assign parity_addra_reg = 16384 + addra_reg * 4; - assign parity_addrb_int = 16384 + addrb_int * 4; - assign parity_addrb_reg = 16384 + addrb_reg * 4; - - - initial begin - - display_flag = 1; - - case (SIM_COLLISION_CHECK) - - "NONE" : begin - assign setup_all_a_b = 1'b0; - assign setup_all_b_a = 1'b0; - assign setup_zero = 1'b0; - assign setup_rf_a_b = 1'b0; - assign setup_rf_b_a = 1'b0; - assign display_flag = 0; - end - "WARNING_ONLY" : begin - assign data_collision = 2'b00; - assign data_collision_a_b = 2'b00; - assign data_collision_b_a = 2'b00; - assign memory_collision = 1'b0; - assign memory_collision_a_b = 1'b0; - assign memory_collision_b_a = 1'b0; - end - "GENERATE_X_ONLY" : begin - assign display_flag = 0; - end - "ALL" : ; - default : begin - $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); - $finish; - end - - endcase // case(SIM_COLLISION_CHECK) - - end // initial begin - - - always @(posedge clka_int) begin - time_clka = $time; - #0 time_clkb_clka = time_clka - time_clkb; - change_clka = ~change_clka; - end - - always @(posedge clkb_int) begin - time_clkb = $time; - #0 time_clka_clkb = time_clkb - time_clka; - change_clkb = ~change_clkb; - end - - always @(change_clkb) begin - if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) - setup_all_a_b = 1; - if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) - setup_rf_a_b = 1; - end - - always @(change_clka) begin - if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) - setup_all_b_a = 1; - if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) - setup_rf_b_a = 1; - end - - always @(change_clkb or change_clka) begin - if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) - setup_zero = 1; - end - - always @(posedge setup_zero) begin - if ((ena_int == 1) && (wea_int == 1) && - (enb_int == 1) && (web_int == 1) && - (data_addra_int[14:5] == data_addrb_int[14:5])) - memory_collision <= 1; - end - - always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin - if ((ena_reg == 1) && (wea_reg == 1) && - (enb_int == 1) && (web_int == 1) && - (data_addra_reg[14:5] == data_addrb_int[14:5])) - memory_collision_a_b <= 1; - end - - always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin - if ((ena_int == 1) && (wea_int == 1) && - (enb_reg == 1) && (web_reg == 1) && - (data_addra_int[14:5] == data_addrb_reg[14:5])) - memory_collision_b_a <= 1; - end - - always @(posedge setup_all_a_b) begin - if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin - if ((ena_reg == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) - 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end -// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end - 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - endcase - end - end - setup_all_a_b <= 0; - end - - - always @(posedge setup_all_b_a) begin - if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin - if ((ena_int == 1) && (enb_reg == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) - 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end - 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end - 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - endcase - end - end - setup_all_b_a <= 0; - end - - - always @(posedge setup_zero) begin - if (data_addra_int[14:5] == data_addrb_int[14:5]) begin - if ((ena_int == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_int}) - 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end - 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end - 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end - endcase - end - end - setup_zero <= 0; - end - - task display_ra_wb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); - end - endtask - - task display_wa_rb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); - end - endtask - - task display_wa_wb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); - end - endtask - - - always @(posedge setup_rf_a_b) begin - if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin - if ((ena_reg == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) -// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end - 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end -// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end -// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - endcase - end - end - setup_rf_a_b <= 0; - end - - - always @(posedge setup_rf_b_a) begin - if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin - if ((ena_int == 1) && (enb_reg == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) -// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end -// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end - endcase - end - end - setup_rf_b_a <= 0; - end - - - always @(posedge clka_int) begin - addra_reg <= addra_int; - ena_reg <= ena_int; - ssra_reg <= ssra_int; - wea_reg <= wea_int; - end - - always @(posedge clkb_int) begin - addrb_reg <= addrb_int; - enb_reg <= enb_int; - ssrb_reg <= ssrb_int; - web_reg <= web_int; - end - - // Data - always @(posedge memory_collision) begin - for (dmi = 0; dmi < 32; dmi = dmi + 1) begin - mem[data_addra_int + dmi] <= 1'bX; - end - memory_collision <= 0; - end - - always @(posedge memory_collision_a_b) begin - for (dmi = 0; dmi < 32; dmi = dmi + 1) begin - mem[data_addra_reg + dmi] <= 1'bX; - end - memory_collision_a_b <= 0; - end - - always @(posedge memory_collision_b_a) begin - for (dmi = 0; dmi < 32; dmi = dmi + 1) begin - mem[data_addra_int + dmi] <= 1'bX; - end - memory_collision_b_a <= 0; - end - - always @(posedge data_collision[1]) begin - if (ssra_int == 0) begin - doa_out <= 32'bX; - end - data_collision[1] <= 0; - end - - always @(posedge data_collision[0]) begin - if (ssrb_int == 0) begin - dob_out <= 32'bX; - end - data_collision[0] <= 0; - end - - always @(posedge data_collision_a_b[1]) begin - if (ssra_reg == 0) begin - doa_out <= 32'bX; - end - data_collision_a_b[1] <= 0; - end - - always @(posedge data_collision_a_b[0]) begin - if (ssrb_int == 0) begin - dob_out <= 32'bX; - end - data_collision_a_b[0] <= 0; - end - - always @(posedge data_collision_b_a[1]) begin - if (ssra_int == 0) begin - doa_out <= 32'bX; - end - data_collision_b_a[1] <= 0; - end - - always @(posedge data_collision_b_a[0]) begin - if (ssrb_reg == 0) begin - dob_out <= 32'bX; - end - data_collision_b_a[0] <= 0; - end - - - // Parity - always @(posedge memory_collision) begin - for (pmi = 0; pmi < 4; pmi = pmi + 1) begin - mem[parity_addra_int + pmi] <= 1'bX; - end - end - - always @(posedge memory_collision_a_b) begin - for (pmi = 0; pmi < 4; pmi = pmi + 1) begin - mem[parity_addra_reg + pmi] <= 1'bX; - end - end - - always @(posedge memory_collision_b_a) begin - for (pmi = 0; pmi < 4; pmi = pmi + 1) begin - mem[parity_addra_int + pmi] <= 1'bX; - end - end - - always @(posedge data_collision[1]) begin - if (ssra_int == 0) begin - dopa_out <= 4'bX; - end - end - - always @(posedge data_collision[0]) begin - if (ssrb_int == 0) begin - dopb_out <= 4'bX; - end - end - - always @(posedge data_collision_a_b[1]) begin - if (ssra_reg == 0) begin - dopa_out <= 4'bX; - end - end - - always @(posedge data_collision_a_b[0]) begin - if (ssrb_int == 0) begin - dopb_out <= 4'bX; - end - end - - always @(posedge data_collision_b_a[1]) begin - if (ssra_int == 0) begin - dopa_out <= 4'bX; - end - end - - always @(posedge data_collision_b_a[0]) begin - if (ssrb_reg == 0) begin - dopb_out <= 4'bX; - end - end - - - initial begin - case (WRITE_MODE_A) - "WRITE_FIRST" : wr_mode_a <= 2'b00; - "READ_FIRST" : wr_mode_a <= 2'b01; - "NO_CHANGE" : wr_mode_a <= 2'b10; - default : begin - $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); - $finish; - end - endcase - end - - initial begin - case (WRITE_MODE_B) - "WRITE_FIRST" : wr_mode_b <= 2'b00; - "READ_FIRST" : wr_mode_b <= 2'b01; - "NO_CHANGE" : wr_mode_b <= 2'b10; - default : begin - $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); - $finish; - end - endcase - end - - // Port A - always @(posedge clka_int) begin - if (ena_int == 1'b1) begin - if (ssra_int == 1'b1) begin - doa_out[0] <= SRVAL_A[0]; - doa_out[1] <= SRVAL_A[1]; - doa_out[2] <= SRVAL_A[2]; - doa_out[3] <= SRVAL_A[3]; - doa_out[4] <= SRVAL_A[4]; - doa_out[5] <= SRVAL_A[5]; - doa_out[6] <= SRVAL_A[6]; - doa_out[7] <= SRVAL_A[7]; - doa_out[8] <= SRVAL_A[8]; - doa_out[9] <= SRVAL_A[9]; - doa_out[10] <= SRVAL_A[10]; - doa_out[11] <= SRVAL_A[11]; - doa_out[12] <= SRVAL_A[12]; - doa_out[13] <= SRVAL_A[13]; - doa_out[14] <= SRVAL_A[14]; - doa_out[15] <= SRVAL_A[15]; - doa_out[16] <= SRVAL_A[16]; - doa_out[17] <= SRVAL_A[17]; - doa_out[18] <= SRVAL_A[18]; - doa_out[19] <= SRVAL_A[19]; - doa_out[20] <= SRVAL_A[20]; - doa_out[21] <= SRVAL_A[21]; - doa_out[22] <= SRVAL_A[22]; - doa_out[23] <= SRVAL_A[23]; - doa_out[24] <= SRVAL_A[24]; - doa_out[25] <= SRVAL_A[25]; - doa_out[26] <= SRVAL_A[26]; - doa_out[27] <= SRVAL_A[27]; - doa_out[28] <= SRVAL_A[28]; - doa_out[29] <= SRVAL_A[29]; - doa_out[30] <= SRVAL_A[30]; - doa_out[31] <= SRVAL_A[31]; - dopa_out[0] <= SRVAL_A[32]; - dopa_out[1] <= SRVAL_A[33]; - dopa_out[2] <= SRVAL_A[34]; - dopa_out[3] <= SRVAL_A[35]; - end - else begin - if (wea_int == 1'b1) begin - if (wr_mode_a == 2'b00) begin - doa_out <= dia_int; - dopa_out <= dipa_int; - end - else if (wr_mode_a == 2'b01) begin - doa_out[0] <= mem[data_addra_int + 0]; - doa_out[1] <= mem[data_addra_int + 1]; - doa_out[2] <= mem[data_addra_int + 2]; - doa_out[3] <= mem[data_addra_int + 3]; - doa_out[4] <= mem[data_addra_int + 4]; - doa_out[5] <= mem[data_addra_int + 5]; - doa_out[6] <= mem[data_addra_int + 6]; - doa_out[7] <= mem[data_addra_int + 7]; - doa_out[8] <= mem[data_addra_int + 8]; - doa_out[9] <= mem[data_addra_int + 9]; - doa_out[10] <= mem[data_addra_int + 10]; - doa_out[11] <= mem[data_addra_int + 11]; - doa_out[12] <= mem[data_addra_int + 12]; - doa_out[13] <= mem[data_addra_int + 13]; - doa_out[14] <= mem[data_addra_int + 14]; - doa_out[15] <= mem[data_addra_int + 15]; - doa_out[16] <= mem[data_addra_int + 16]; - doa_out[17] <= mem[data_addra_int + 17]; - doa_out[18] <= mem[data_addra_int + 18]; - doa_out[19] <= mem[data_addra_int + 19]; - doa_out[20] <= mem[data_addra_int + 20]; - doa_out[21] <= mem[data_addra_int + 21]; - doa_out[22] <= mem[data_addra_int + 22]; - doa_out[23] <= mem[data_addra_int + 23]; - doa_out[24] <= mem[data_addra_int + 24]; - doa_out[25] <= mem[data_addra_int + 25]; - doa_out[26] <= mem[data_addra_int + 26]; - doa_out[27] <= mem[data_addra_int + 27]; - doa_out[28] <= mem[data_addra_int + 28]; - doa_out[29] <= mem[data_addra_int + 29]; - doa_out[30] <= mem[data_addra_int + 30]; - doa_out[31] <= mem[data_addra_int + 31]; - dopa_out[0] <= mem[parity_addra_int + 0]; - dopa_out[1] <= mem[parity_addra_int + 1]; - dopa_out[2] <= mem[parity_addra_int + 2]; - dopa_out[3] <= mem[parity_addra_int + 3]; - end - end - else begin - doa_out[0] <= mem[data_addra_int + 0]; - doa_out[1] <= mem[data_addra_int + 1]; - doa_out[2] <= mem[data_addra_int + 2]; - doa_out[3] <= mem[data_addra_int + 3]; - doa_out[4] <= mem[data_addra_int + 4]; - doa_out[5] <= mem[data_addra_int + 5]; - doa_out[6] <= mem[data_addra_int + 6]; - doa_out[7] <= mem[data_addra_int + 7]; - doa_out[8] <= mem[data_addra_int + 8]; - doa_out[9] <= mem[data_addra_int + 9]; - doa_out[10] <= mem[data_addra_int + 10]; - doa_out[11] <= mem[data_addra_int + 11]; - doa_out[12] <= mem[data_addra_int + 12]; - doa_out[13] <= mem[data_addra_int + 13]; - doa_out[14] <= mem[data_addra_int + 14]; - doa_out[15] <= mem[data_addra_int + 15]; - doa_out[16] <= mem[data_addra_int + 16]; - doa_out[17] <= mem[data_addra_int + 17]; - doa_out[18] <= mem[data_addra_int + 18]; - doa_out[19] <= mem[data_addra_int + 19]; - doa_out[20] <= mem[data_addra_int + 20]; - doa_out[21] <= mem[data_addra_int + 21]; - doa_out[22] <= mem[data_addra_int + 22]; - doa_out[23] <= mem[data_addra_int + 23]; - doa_out[24] <= mem[data_addra_int + 24]; - doa_out[25] <= mem[data_addra_int + 25]; - doa_out[26] <= mem[data_addra_int + 26]; - doa_out[27] <= mem[data_addra_int + 27]; - doa_out[28] <= mem[data_addra_int + 28]; - doa_out[29] <= mem[data_addra_int + 29]; - doa_out[30] <= mem[data_addra_int + 30]; - doa_out[31] <= mem[data_addra_int + 31]; - dopa_out[0] <= mem[parity_addra_int + 0]; - dopa_out[1] <= mem[parity_addra_int + 1]; - dopa_out[2] <= mem[parity_addra_int + 2]; - dopa_out[3] <= mem[parity_addra_int + 3]; - end - end - end - end - - always @(posedge clka_int) begin - if (ena_int == 1'b1 && wea_int == 1'b1) begin - mem[data_addra_int + 0] <= dia_int[0]; - mem[data_addra_int + 1] <= dia_int[1]; - mem[data_addra_int + 2] <= dia_int[2]; - mem[data_addra_int + 3] <= dia_int[3]; - mem[data_addra_int + 4] <= dia_int[4]; - mem[data_addra_int + 5] <= dia_int[5]; - mem[data_addra_int + 6] <= dia_int[6]; - mem[data_addra_int + 7] <= dia_int[7]; - mem[data_addra_int + 8] <= dia_int[8]; - mem[data_addra_int + 9] <= dia_int[9]; - mem[data_addra_int + 10] <= dia_int[10]; - mem[data_addra_int + 11] <= dia_int[11]; - mem[data_addra_int + 12] <= dia_int[12]; - mem[data_addra_int + 13] <= dia_int[13]; - mem[data_addra_int + 14] <= dia_int[14]; - mem[data_addra_int + 15] <= dia_int[15]; - mem[data_addra_int + 16] <= dia_int[16]; - mem[data_addra_int + 17] <= dia_int[17]; - mem[data_addra_int + 18] <= dia_int[18]; - mem[data_addra_int + 19] <= dia_int[19]; - mem[data_addra_int + 20] <= dia_int[20]; - mem[data_addra_int + 21] <= dia_int[21]; - mem[data_addra_int + 22] <= dia_int[22]; - mem[data_addra_int + 23] <= dia_int[23]; - mem[data_addra_int + 24] <= dia_int[24]; - mem[data_addra_int + 25] <= dia_int[25]; - mem[data_addra_int + 26] <= dia_int[26]; - mem[data_addra_int + 27] <= dia_int[27]; - mem[data_addra_int + 28] <= dia_int[28]; - mem[data_addra_int + 29] <= dia_int[29]; - mem[data_addra_int + 30] <= dia_int[30]; - mem[data_addra_int + 31] <= dia_int[31]; - mem[parity_addra_int + 0] <= dipa_int[0]; - mem[parity_addra_int + 1] <= dipa_int[1]; - mem[parity_addra_int + 2] <= dipa_int[2]; - mem[parity_addra_int + 3] <= dipa_int[3]; - end - end - - // Port B - always @(posedge clkb_int) begin - if (enb_int == 1'b1) begin - if (ssrb_int == 1'b1) begin - dob_out[0] <= SRVAL_B[0]; - dob_out[1] <= SRVAL_B[1]; - dob_out[2] <= SRVAL_B[2]; - dob_out[3] <= SRVAL_B[3]; - dob_out[4] <= SRVAL_B[4]; - dob_out[5] <= SRVAL_B[5]; - dob_out[6] <= SRVAL_B[6]; - dob_out[7] <= SRVAL_B[7]; - dob_out[8] <= SRVAL_B[8]; - dob_out[9] <= SRVAL_B[9]; - dob_out[10] <= SRVAL_B[10]; - dob_out[11] <= SRVAL_B[11]; - dob_out[12] <= SRVAL_B[12]; - dob_out[13] <= SRVAL_B[13]; - dob_out[14] <= SRVAL_B[14]; - dob_out[15] <= SRVAL_B[15]; - dob_out[16] <= SRVAL_B[16]; - dob_out[17] <= SRVAL_B[17]; - dob_out[18] <= SRVAL_B[18]; - dob_out[19] <= SRVAL_B[19]; - dob_out[20] <= SRVAL_B[20]; - dob_out[21] <= SRVAL_B[21]; - dob_out[22] <= SRVAL_B[22]; - dob_out[23] <= SRVAL_B[23]; - dob_out[24] <= SRVAL_B[24]; - dob_out[25] <= SRVAL_B[25]; - dob_out[26] <= SRVAL_B[26]; - dob_out[27] <= SRVAL_B[27]; - dob_out[28] <= SRVAL_B[28]; - dob_out[29] <= SRVAL_B[29]; - dob_out[30] <= SRVAL_B[30]; - dob_out[31] <= SRVAL_B[31]; - dopb_out[0] <= SRVAL_B[32]; - dopb_out[1] <= SRVAL_B[33]; - dopb_out[2] <= SRVAL_B[34]; - dopb_out[3] <= SRVAL_B[35]; - end - else begin - if (web_int == 1'b1) begin - if (wr_mode_b == 2'b00) begin - dob_out <= dib_int; - dopb_out <= dipb_int; - end - else if (wr_mode_b == 2'b01) begin - dob_out[0] <= mem[data_addrb_int + 0]; - dob_out[1] <= mem[data_addrb_int + 1]; - dob_out[2] <= mem[data_addrb_int + 2]; - dob_out[3] <= mem[data_addrb_int + 3]; - dob_out[4] <= mem[data_addrb_int + 4]; - dob_out[5] <= mem[data_addrb_int + 5]; - dob_out[6] <= mem[data_addrb_int + 6]; - dob_out[7] <= mem[data_addrb_int + 7]; - dob_out[8] <= mem[data_addrb_int + 8]; - dob_out[9] <= mem[data_addrb_int + 9]; - dob_out[10] <= mem[data_addrb_int + 10]; - dob_out[11] <= mem[data_addrb_int + 11]; - dob_out[12] <= mem[data_addrb_int + 12]; - dob_out[13] <= mem[data_addrb_int + 13]; - dob_out[14] <= mem[data_addrb_int + 14]; - dob_out[15] <= mem[data_addrb_int + 15]; - dob_out[16] <= mem[data_addrb_int + 16]; - dob_out[17] <= mem[data_addrb_int + 17]; - dob_out[18] <= mem[data_addrb_int + 18]; - dob_out[19] <= mem[data_addrb_int + 19]; - dob_out[20] <= mem[data_addrb_int + 20]; - dob_out[21] <= mem[data_addrb_int + 21]; - dob_out[22] <= mem[data_addrb_int + 22]; - dob_out[23] <= mem[data_addrb_int + 23]; - dob_out[24] <= mem[data_addrb_int + 24]; - dob_out[25] <= mem[data_addrb_int + 25]; - dob_out[26] <= mem[data_addrb_int + 26]; - dob_out[27] <= mem[data_addrb_int + 27]; - dob_out[28] <= mem[data_addrb_int + 28]; - dob_out[29] <= mem[data_addrb_int + 29]; - dob_out[30] <= mem[data_addrb_int + 30]; - dob_out[31] <= mem[data_addrb_int + 31]; - dopb_out[0] <= mem[parity_addrb_int + 0]; - dopb_out[1] <= mem[parity_addrb_int + 1]; - dopb_out[2] <= mem[parity_addrb_int + 2]; - dopb_out[3] <= mem[parity_addrb_int + 3]; - end - end - else begin - dob_out[0] <= mem[data_addrb_int + 0]; - dob_out[1] <= mem[data_addrb_int + 1]; - dob_out[2] <= mem[data_addrb_int + 2]; - dob_out[3] <= mem[data_addrb_int + 3]; - dob_out[4] <= mem[data_addrb_int + 4]; - dob_out[5] <= mem[data_addrb_int + 5]; - dob_out[6] <= mem[data_addrb_int + 6]; - dob_out[7] <= mem[data_addrb_int + 7]; - dob_out[8] <= mem[data_addrb_int + 8]; - dob_out[9] <= mem[data_addrb_int + 9]; - dob_out[10] <= mem[data_addrb_int + 10]; - dob_out[11] <= mem[data_addrb_int + 11]; - dob_out[12] <= mem[data_addrb_int + 12]; - dob_out[13] <= mem[data_addrb_int + 13]; - dob_out[14] <= mem[data_addrb_int + 14]; - dob_out[15] <= mem[data_addrb_int + 15]; - dob_out[16] <= mem[data_addrb_int + 16]; - dob_out[17] <= mem[data_addrb_int + 17]; - dob_out[18] <= mem[data_addrb_int + 18]; - dob_out[19] <= mem[data_addrb_int + 19]; - dob_out[20] <= mem[data_addrb_int + 20]; - dob_out[21] <= mem[data_addrb_int + 21]; - dob_out[22] <= mem[data_addrb_int + 22]; - dob_out[23] <= mem[data_addrb_int + 23]; - dob_out[24] <= mem[data_addrb_int + 24]; - dob_out[25] <= mem[data_addrb_int + 25]; - dob_out[26] <= mem[data_addrb_int + 26]; - dob_out[27] <= mem[data_addrb_int + 27]; - dob_out[28] <= mem[data_addrb_int + 28]; - dob_out[29] <= mem[data_addrb_int + 29]; - dob_out[30] <= mem[data_addrb_int + 30]; - dob_out[31] <= mem[data_addrb_int + 31]; - dopb_out[0] <= mem[parity_addrb_int + 0]; - dopb_out[1] <= mem[parity_addrb_int + 1]; - dopb_out[2] <= mem[parity_addrb_int + 2]; - dopb_out[3] <= mem[parity_addrb_int + 3]; - end - end - end - end - - always @(posedge clkb_int) begin - if (enb_int == 1'b1 && web_int == 1'b1) begin - mem[data_addrb_int + 0] <= dib_int[0]; - mem[data_addrb_int + 1] <= dib_int[1]; - mem[data_addrb_int + 2] <= dib_int[2]; - mem[data_addrb_int + 3] <= dib_int[3]; - mem[data_addrb_int + 4] <= dib_int[4]; - mem[data_addrb_int + 5] <= dib_int[5]; - mem[data_addrb_int + 6] <= dib_int[6]; - mem[data_addrb_int + 7] <= dib_int[7]; - mem[data_addrb_int + 8] <= dib_int[8]; - mem[data_addrb_int + 9] <= dib_int[9]; - mem[data_addrb_int + 10] <= dib_int[10]; - mem[data_addrb_int + 11] <= dib_int[11]; - mem[data_addrb_int + 12] <= dib_int[12]; - mem[data_addrb_int + 13] <= dib_int[13]; - mem[data_addrb_int + 14] <= dib_int[14]; - mem[data_addrb_int + 15] <= dib_int[15]; - mem[data_addrb_int + 16] <= dib_int[16]; - mem[data_addrb_int + 17] <= dib_int[17]; - mem[data_addrb_int + 18] <= dib_int[18]; - mem[data_addrb_int + 19] <= dib_int[19]; - mem[data_addrb_int + 20] <= dib_int[20]; - mem[data_addrb_int + 21] <= dib_int[21]; - mem[data_addrb_int + 22] <= dib_int[22]; - mem[data_addrb_int + 23] <= dib_int[23]; - mem[data_addrb_int + 24] <= dib_int[24]; - mem[data_addrb_int + 25] <= dib_int[25]; - mem[data_addrb_int + 26] <= dib_int[26]; - mem[data_addrb_int + 27] <= dib_int[27]; - mem[data_addrb_int + 28] <= dib_int[28]; - mem[data_addrb_int + 29] <= dib_int[29]; - mem[data_addrb_int + 30] <= dib_int[30]; - mem[data_addrb_int + 31] <= dib_int[31]; - mem[parity_addrb_int + 0] <= dipb_int[0]; - mem[parity_addrb_int + 1] <= dipb_int[1]; - mem[parity_addrb_int + 2] <= dipb_int[2]; - mem[parity_addrb_int + 3] <= dipb_int[3]; - end - end - - specify - (CLKA *> DOA) = (100, 100); - (CLKA *> DOPA) = (100, 100); - (CLKB *> DOB) = (100, 100); - (CLKB *> DOPB) = (100, 100); - endspecify - -endmodule - -`else - -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2005 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 10.1 -// \ \ Description : Xilinx Timing Simulation Library Component -// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM -// /___/ /\ Filename : RAMB16_S36_S36.v -// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// 03/10/05 - Initialized outputs. -// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). -// End Revision - -`timescale 1 ps/1 ps - -module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); - - parameter INIT_A = 36'h0; - parameter INIT_B = 36'h0; - parameter SRVAL_A = 36'h0; - parameter SRVAL_B = 36'h0; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - parameter SIM_COLLISION_CHECK = "ALL"; - localparam SETUP_ALL = 1000; - localparam SETUP_READ_FIRST = 3000; - - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - output [31:0] DOA; - output [3:0] DOPA; - output [31:0] DOB; - output [3:0] DOPB; - - input [8:0] ADDRA; - input [31:0] DIA; - input [3:0] DIPA; - input ENA, CLKA, WEA, SSRA; - input [8:0] ADDRB; - input [31:0] DIB; - input [3:0] DIPB; - input ENB, CLKB, WEB, SSRB; - - reg [31:0] doa_out = INIT_A[31:0]; - reg [3:0] dopa_out = INIT_A[35:32]; - reg [31:0] dob_out = INIT_B[31:0]; - reg [3:0] dopb_out = INIT_B[35:32]; - - reg [31:0] mem [511:0]; - reg [3:0] memp [511:0]; - - reg [8:0] count, countp; - reg [1:0] wr_mode_a, wr_mode_b; - - reg [5:0] dmi, dbi; - reg [5:0] pmi, pbi; - - wire [8:0] addra_int; - reg [8:0] addra_reg; - wire [31:0] dia_int; - wire [3:0] dipa_int; - wire ena_int, clka_int, wea_int, ssra_int; - reg ena_reg, wea_reg, ssra_reg; - wire [8:0] addrb_int; - reg [8:0] addrb_reg; - wire [31:0] dib_int; - wire [3:0] dipb_int; - wire enb_int, clkb_int, web_int, ssrb_int; - reg display_flag, output_flag; - reg enb_reg, web_reg, ssrb_reg; - - time time_clka, time_clkb; - time time_clka_clkb; - time time_clkb_clka; - - reg setup_all_a_b; - reg setup_all_b_a; - reg setup_zero; - reg setup_rf_a_b; - reg setup_rf_b_a; - reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; - reg memory_collision, memory_collision_a_b, memory_collision_b_a; - reg change_clka; - reg change_clkb; - - wire [14:0] data_addra_int; - wire [14:0] data_addra_reg; - wire [14:0] data_addrb_int; - wire [14:0] data_addrb_reg; - - wire dia_enable = ena_int && wea_int; - wire dib_enable = enb_int && web_int; - - tri0 GSR = glbl.GSR; - wire gsr_int; - - buf b_gsr (gsr_int, GSR); - - buf b_doa [31:0] (DOA, doa_out); - buf b_dopa [3:0] (DOPA, dopa_out); - buf b_addra [8:0] (addra_int, ADDRA); - buf b_dia [31:0] (dia_int, DIA); - buf b_dipa [3:0] (dipa_int, DIPA); - buf b_ena (ena_int, ENA); - buf b_clka (clka_int, CLKA); - buf b_ssra (ssra_int, SSRA); - buf b_wea (wea_int, WEA); - - buf b_dob [31:0] (DOB, dob_out); - buf b_dopb [3:0] (DOPB, dopb_out); - buf b_addrb [8:0] (addrb_int, ADDRB); - buf b_dib [31:0] (dib_int, DIB); - buf b_dipb [3:0] (dipb_int, DIPB); - buf b_enb (enb_int, ENB); - buf b_clkb (clkb_int, CLKB); - buf b_ssrb (ssrb_int, SSRB); - buf b_web (web_int, WEB); - - - always @(gsr_int) - if (gsr_int) begin - assign {dopa_out, doa_out} = INIT_A; - assign {dopb_out, dob_out} = INIT_B; - end - else begin - deassign doa_out; - deassign dopa_out; - deassign dob_out; - deassign dopb_out; - end - - - initial begin - - for (count = 0; count < 8; count = count + 1) begin - mem[count] = INIT_00[(count * 32) +: 32]; - mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; - mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; - mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; - mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; - mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; - mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; - mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; - mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; - mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; - mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; - mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; - mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; - mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; - mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; - mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; - mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; - mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; - mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; - mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; - mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; - mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; - mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; - mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; - mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; - mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; - mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; - mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; - mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; - mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; - mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; - mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; - mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; - mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; - mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; - mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; - mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; - mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; - mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; - mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; - mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; - mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; - mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; - mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; - mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; - mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; - mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; - mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; - mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; - mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; - mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; - mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; - mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; - mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; - mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; - mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; - mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; - mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; - mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; - mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; - mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; - mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; - mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; - mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; - end - -// initiate parity start - for (countp = 0; countp < 64; countp = countp + 1) begin - memp[countp] = INITP_00[(countp * 4) +: 4]; - memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; - memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; - memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; - memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; - memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; - memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; - memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; - end -// initiate parity end - - change_clka <= 0; - change_clkb <= 0; - data_collision <= 0; - data_collision_a_b <= 0; - data_collision_b_a <= 0; - memory_collision <= 0; - memory_collision_a_b <= 0; - memory_collision_b_a <= 0; - setup_all_a_b <= 0; - setup_all_b_a <= 0; - setup_zero <= 0; - setup_rf_a_b <= 0; - setup_rf_b_a <= 0; - end - - assign data_addra_int = addra_int * 32; - assign data_addra_reg = addra_reg * 32; - assign data_addrb_int = addrb_int * 32; - assign data_addrb_reg = addrb_reg * 32; - - - initial begin - - display_flag = 1; - output_flag = 1; - - case (SIM_COLLISION_CHECK) - - "NONE" : begin - output_flag = 0; - display_flag = 0; - end - "WARNING_ONLY" : output_flag = 0; - "GENERATE_X_ONLY" : display_flag = 0; - "ALL" : ; - - default : begin - $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); - $finish; - end - - endcase // case(SIM_COLLISION_CHECK) - - end // initial begin - - - always @(posedge clka_int) begin - if ((output_flag || display_flag)) begin - time_clka = $time; - #0 time_clkb_clka = time_clka - time_clkb; - change_clka = ~change_clka; - end - end - - always @(posedge clkb_int) begin - if ((output_flag || display_flag)) begin - time_clkb = $time; - #0 time_clka_clkb = time_clkb - time_clka; - change_clkb = ~change_clkb; - end - end - - always @(change_clkb) begin - if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) - setup_all_a_b = 1; - if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) - setup_rf_a_b = 1; - end - - always @(change_clka) begin - if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) - setup_all_b_a = 1; - if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) - setup_rf_b_a = 1; - end - - always @(change_clkb or change_clka) begin - if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) - setup_zero = 1; - end - - always @(posedge setup_zero) begin - if ((ena_int == 1) && (wea_int == 1) && - (enb_int == 1) && (web_int == 1) && - (data_addra_int[14:5] == data_addrb_int[14:5])) - memory_collision <= 1; - end - - always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin - if ((ena_reg == 1) && (wea_reg == 1) && - (enb_int == 1) && (web_int == 1) && - (data_addra_reg[14:5] == data_addrb_int[14:5])) - memory_collision_a_b <= 1; - end - - always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin - if ((ena_int == 1) && (wea_int == 1) && - (enb_reg == 1) && (web_reg == 1) && - (data_addra_int[14:5] == data_addrb_reg[14:5])) - memory_collision_b_a <= 1; - end - - always @(posedge setup_all_a_b) begin - if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin - if ((ena_reg == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) - 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end -// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end - 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end -// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end - 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - endcase - end - end - setup_all_a_b <= 0; - end - - - always @(posedge setup_all_b_a) begin - if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin - if ((ena_int == 1) && (enb_reg == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) - 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end - 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end - 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end - endcase - end - end - setup_all_b_a <= 0; - end - - - always @(posedge setup_zero) begin - if (data_addra_int[14:5] == data_addrb_int[14:5]) begin - if ((ena_int == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_int}) - 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end - 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end - 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end - 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end - 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end - 6'b101011 : begin display_wa_wb; end - 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end -// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end - 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end - 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end -// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end - 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end - 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end - endcase - end - end - setup_zero <= 0; - end - - task display_ra_wb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); - end - endtask - - task display_wa_rb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); - end - endtask - - task display_wa_wb; - begin - if (display_flag) - $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); - end - endtask - - - always @(posedge setup_rf_a_b) begin - if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin - if ((ena_reg == 1) && (enb_int == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) -// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end - 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end - 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end -// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end -// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end -// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end - 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end -// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end -// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end - endcase - end - end - setup_rf_a_b <= 0; - end - - - always @(posedge setup_rf_b_a) begin - if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin - if ((ena_int == 1) && (enb_reg == 1)) begin - case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) -// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end -// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end - 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end -// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end -// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end - 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end -// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end -// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end -// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end - endcase - end - end - setup_rf_b_a <= 0; - end - - - always @(posedge clka_int) begin - if ((output_flag || display_flag)) begin - addra_reg <= addra_int; - ena_reg <= ena_int; - ssra_reg <= ssra_int; - wea_reg <= wea_int; - end - end - - always @(posedge clkb_int) begin - if ((output_flag || display_flag)) begin - addrb_reg <= addrb_int; - enb_reg <= enb_int; - ssrb_reg <= ssrb_int; - web_reg <= web_int; - end - end - - - // Data - always @(posedge memory_collision) begin - if ((output_flag || display_flag)) begin - mem[addra_int] <= 32'bx; - memory_collision <= 0; - end - - end - - always @(posedge memory_collision_a_b) begin - if ((output_flag || display_flag)) begin - mem[addra_reg] <= 32'bx; - memory_collision_a_b <= 0; - end - end - - always @(posedge memory_collision_b_a) begin - if ((output_flag || display_flag)) begin - mem[addra_int] <= 32'bx; - memory_collision_b_a <= 0; - end - end - - always @(posedge data_collision[1]) begin - if (ssra_int == 0 && output_flag) begin - doa_out <= #100 32'bX; - end - data_collision[1] <= 0; - end - - always @(posedge data_collision[0]) begin - if (ssrb_int == 0 && output_flag) begin - dob_out <= #100 32'bX; - end - data_collision[0] <= 0; - end - - always @(posedge data_collision_a_b[1]) begin - if (ssra_reg == 0 && output_flag) begin - doa_out <= #100 32'bX; - end - data_collision_a_b[1] <= 0; - end - - always @(posedge data_collision_a_b[0]) begin - if (ssrb_int == 0 && output_flag) begin - dob_out <= #100 32'bX; - end - data_collision_a_b[0] <= 0; - end - - always @(posedge data_collision_b_a[1]) begin - if (ssra_int == 0 && output_flag) begin - doa_out <= #100 32'bX; - end - data_collision_b_a[1] <= 0; - end - - always @(posedge data_collision_b_a[0]) begin - if (ssrb_reg == 0 && output_flag) begin - dob_out <= #100 32'bX; - end - data_collision_b_a[0] <= 0; - end - -// x parity start - always @(posedge memory_collision) begin - if ((output_flag || display_flag)) - memp[addra_int] <= 4'bx; - end - - always @(posedge memory_collision_a_b) begin - if ((output_flag || display_flag)) - memp[addra_reg] <= 4'bx; - end - - always @(posedge memory_collision_b_a) begin - if ((output_flag || display_flag)) - memp[addra_int] <= 4'bx; - end - - always @(posedge data_collision[1]) begin - if (ssra_int == 0 && output_flag) begin - dopa_out <= #100 4'bX; - end - end - - always @(posedge data_collision_a_b[1]) begin - if (ssra_reg == 0 && output_flag) begin - dopa_out <= #100 4'bX; - end - end - - - always @(posedge data_collision_b_a[1]) begin - if (ssra_int == 0 && output_flag) begin - dopa_out <= #100 4'bX; - end - end - - always @(posedge data_collision[0]) begin - if (ssrb_int == 0 && output_flag) begin - dopb_out <= #100 4'bx; - end - end - - always @(posedge data_collision_a_b[0]) begin - if (ssrb_int == 0 && output_flag) begin - dopb_out <= #100 4'bx; - end - end - - always @(posedge data_collision_b_a[0]) begin - if (ssrb_reg == 0 && output_flag) begin - dopb_out <= #100 4'bx; - end - end -// x parity end - - initial begin - case (WRITE_MODE_A) - "WRITE_FIRST" : wr_mode_a <= 2'b00; - "READ_FIRST" : wr_mode_a <= 2'b01; - "NO_CHANGE" : wr_mode_a <= 2'b10; - default : begin - $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); - $finish; - end - endcase - end - - initial begin - case (WRITE_MODE_B) - "WRITE_FIRST" : wr_mode_b <= 2'b00; - "READ_FIRST" : wr_mode_b <= 2'b01; - "NO_CHANGE" : wr_mode_b <= 2'b10; - default : begin - $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); - $finish; - end - endcase - end - - - // Port A - always @(posedge clka_int) begin - - if (ena_int == 1'b1) begin - - if (ssra_int == 1'b1) begin - {dopa_out, doa_out} <= #100 SRVAL_A; - end - else begin - if (wea_int == 1'b1) begin - if (wr_mode_a == 2'b00) begin - doa_out <= #100 dia_int; - dopa_out <= #100 dipa_int; - end - else if (wr_mode_a == 2'b01) begin - - doa_out <= #100 mem[addra_int]; - dopa_out <= #100 memp[addra_int]; - - end - end - else begin - - doa_out <= #100 mem[addra_int]; - dopa_out <= #100 memp[addra_int]; - - end - end - - // memory - if (wea_int == 1'b1) begin - mem[addra_int] <= dia_int; - memp[addra_int] <= dipa_int; - end - - end - end - - - // Port B - always @(posedge clkb_int) begin - - if (enb_int == 1'b1) begin - - if (ssrb_int == 1'b1) begin - {dopb_out, dob_out} <= #100 SRVAL_B; - end - else begin - if (web_int == 1'b1) begin - if (wr_mode_b == 2'b00) begin - dob_out <= #100 dib_int; - dopb_out <= #100 dipb_int; - end - else if (wr_mode_b == 2'b01) begin - dob_out <= #100 mem[addrb_int]; - dopb_out <= #100 memp[addrb_int]; - end - end - else begin - dob_out <= #100 mem[addrb_int]; - dopb_out <= #100 memp[addrb_int]; - end - end - - // memory - if (web_int == 1'b1) begin - mem[addrb_int] <= dib_int; - memp[addrb_int] <= dipb_int; - end - - end - end - - -endmodule - -`endif diff --git a/models/SRL16E.v b/models/SRL16E.v deleted file mode 100644 index e71a419ac..000000000 --- a/models/SRL16E.v +++ /dev/null @@ -1,53 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 8.1i (I.13) -// \ \ Description : Xilinx Functional Simulation Library Component -// / / 16-Bit Shift Register Look-Up-Table with Clock Enable -// /___/ /\ Filename : SRL16E.v -// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// End Revision - -`timescale 1 ps / 1 ps - - -module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D); - - parameter INIT = 16'h0000; - - output Q; - - input A0, A1, A2, A3, CE, CLK, D; - - reg [15:0] data; - - - assign Q = data[{A3, A2, A1, A0}]; - - initial - begin - assign data = INIT; - while (CLK === 1'b1 || CLK===1'bX) - #10; - deassign data; - end - - always @(posedge CLK) - begin - if (CE == 1'b1) begin - {data[15:0]} <= #100 {data[14:0], D}; - end - end - - -endmodule - diff --git a/models/SRLC16E.v b/models/SRLC16E.v deleted file mode 100644 index a68bbe9e9..000000000 --- a/models/SRLC16E.v +++ /dev/null @@ -1,61 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16E.v,v 1.6.158.1 2007/03/09 18:13:20 patrickp Exp $ -/////////////////////////////////////////////////////////////////////////////// -// Copyright (c) 1995/2004 Xilinx, Inc. -// All Right Reserved. -/////////////////////////////////////////////////////////////////////////////// -// ____ ____ -// / /\/ / -// /___/ \ / Vendor : Xilinx -// \ \ \/ Version : 8.1i (I.13) -// \ \ Description : Xilinx Functional Simulation Library Component -// / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable -// /___/ /\ Filename : SRLC16E.v -// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 -// \___\/\___\ -// -// Revision: -// 03/23/04 - Initial version. -// End Revision - -`timescale 1 ps / 1 ps - - -module SRLC16E (Q, Q15, A0, A1, A2, A3, CE, CLK, D); - - parameter INIT = 16'h0000; - - output Q, Q15; - - input A0, A1, A2, A3, CE, CLK, D; - - reg [15:0] data; - wire [3:0] addr; - wire q_int; - - buf b_a3 (addr[3], A3); - buf b_a2 (addr[2], A2); - buf b_a1 (addr[1], A1); - buf b_a0 (addr[0], A0); - - buf b_q_int (q_int, data[addr]); - buf b_q (Q, q_int); - buf b_q15_int (q15_int, data[15]); - buf b_q15 (Q15, q15_int); - - initial - begin - assign data = INIT; - while (CLK === 1'b1 || CLK===1'bX) - #10; - deassign data; - end - - always @(posedge CLK) begin - if (CE == 1'b1) begin - {data[15:0]} <= #100 {data[14:0], D}; - end - end - - -endmodule - diff --git a/models/adc_model.v b/models/adc_model.v deleted file mode 100644 index e5a3ee0d8..000000000 --- a/models/adc_model.v +++ /dev/null @@ -1,48 +0,0 @@ - -module adc_model - (input clk, input rst, - output [13:0] adc_a, - output adc_ovf_a, - input adc_on_a, - input adc_oe_a, - output [13:0] adc_b, - output adc_ovf_b, - input adc_on_b, - input adc_oe_b - ); - - math_real math ( ) ; - - reg [13:0] adc_a_int = 0; - reg [13:0] adc_b_int = 0; - - assign adc_a = adc_oe_a ? adc_a_int : 14'bz; - assign adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz; - assign adc_b = adc_oe_b ? adc_b_int : 14'bz; - assign adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz; - - real phase = 0; - real freq = 330000/100000000; - - real scale = 8190; // math.pow(2,13)-2; - always @(posedge clk) - if(rst) - begin - adc_a_int <= 0; - adc_b_int <= 0; - end - else - begin - if(adc_on_a) - //adc_a_int <= $rtoi(math.round(math.sin(phase*math.MATH_2_PI)*scale)) ; - adc_a_int <= adc_a_int + 3; - if(adc_on_b) - adc_b_int <= adc_b_int - 7; - //adc_b_int <= $rtoi(math.round(math.cos(phase*math.MATH_2_PI)*scale)) ; - if(phase > 1) - phase <= phase + freq - 1; - else - phase <= phase + freq; - end - -endmodule // adc_model diff --git a/models/cpld_model.v b/models/cpld_model.v deleted file mode 100644 index c886433ae..000000000 --- a/models/cpld_model.v +++ /dev/null @@ -1,96 +0,0 @@ - -module cpld_model - (input aux_clk, input start, input mode, input done, - output dout, output reg sclk, output detached); - - reg [7:0] rom[0:65535]; - - reg [15:0] addr; - reg [7:0] data; - assign dout = data[7]; - - reg [2:0] state, bitcnt; - - localparam IDLE = 3'd0; - localparam READ = 3'd1; - localparam BIT1 = 3'd2; - localparam BIT2 = 3'd3; - localparam DONE = 3'd4; - localparam DETACHED = 3'd5; - localparam ERROR = 3'd7; - - integer i; - reg [1023:0] ROMFile; - - initial begin - for (i=0;i<65536;i=i+1) begin - rom[i] <= 32'h0; - end - if ( !$value$plusargs( "rom=%s", ROMFile ) ) - begin - $display( "Using default ROM file, 'flash.rom'" ); - ROMFile = "flash.rom"; - end - else - $display( "Using %s as ROM file.", ROMFile); - - #1 $readmemh( ROMFile,rom ); - end - - initial addr = 16'd0; - initial data = 8'd0; - initial state = IDLE; - initial bitcnt = 3'd0; - initial sclk = 1'b0; - - always @(posedge aux_clk) - case(state) - IDLE : - if(start) - if(~mode) - state <= READ; - else - state <= ERROR; - READ : - if(done) - state <= DONE; - else - begin - data <= rom[addr]; - addr <= addr + 1; - bitcnt <= 3'd0; - if(addr==16'hFFFF) - state <= ERROR; - else - state <= BIT1; - end // else: !if(start) - BIT1 : - begin - sclk <= 1'b1; - state <= BIT2; - end - BIT2 : - begin - sclk <= 1'b0; - data <= {data[6:0],1'b0}; - bitcnt <= bitcnt + 1; - if(bitcnt==7) - state <= READ; - else - state <=BIT1; - end - DONE : - begin - if(start) - state <= ERROR; - else - state <= DETACHED; - end - DETACHED : - if(start) - state <= ERROR; - endcase // case(state) - - assign detached = (state == DETACHED) || (state == IDLE); - -endmodule // cpld_model diff --git a/models/math_real.v b/models/math_real.v deleted file mode 100644 index e30f68ee7..000000000 --- a/models/math_real.v +++ /dev/null @@ -1,495 +0,0 @@ -/* - * This is a general recreation of the VHDL ieee.math_real package. - */ - -module math_real ; - // Constants for use below and for general reference - // TODO: Bring it out to 12 (or more???) places beyond the decimal? - localparam MATH_E = 2.7182818284; - localparam MATH_1_OVER_E = 0.3678794411; - localparam MATH_PI = 3.1415926536; - localparam MATH_2_PI = 6.2831853071; - localparam MATH_1_OVER_PI = 0.3183098861; - localparam MATH_PI_OVER_2 = 1.5707963267; - localparam MATH_PI_OVER_3 = 1.0471975511; - localparam MATH_PI_OVER_4 = 0.7853981633; - localparam MATH_3_PI_OVER_2 = 4.7123889803; - localparam MATH_LOG_OF_2 = 0.6931471805; - localparam MATH_LOG_OF_10 = 2.3025850929; - localparam MATH_LOG2_OF_E = 1.4426950408; - localparam MATH_LOG10_OF_E = 0.4342944819; - localparam MATH_SQRT_2 = 1.4142135623; - localparam MATH_1_OVER_SQRT_2= 0.7071067811; - localparam MATH_SQRT_PI = 1.7724538509; - localparam MATH_DEG_TO_RAD = 0.0174532925; - localparam MATH_RAD_TO_DEG = 57.2957795130; - - // The number of iterations to do for the Taylor series approximations - localparam EXPLOG_ITERATIONS = 19; - localparam COS_ITERATIONS = 8; - - /* Conversion Routines */ - - // Return the sign of a particular number. - function real sign ; - input real x ; - begin - sign = x < 0.0 ? 1.0 : 0.0 ; - end - endfunction - - // Return the trunc function of a number - function real trunc ; - input real x ; - begin - trunc = x - mod(x,1.0) ; - end - endfunction - - // Return the ceiling function of a number. - function real ceil ; - input real x ; - real retval ; - begin - retval = mod(x,1.0) ; - if( retval != 0.0 && x > 0.0 ) retval = x+1.0 ; - else retval = x ; - ceil = trunc(retval) ; - end - endfunction - - // Return the floor function of a number - function real floor ; - input real x ; - real retval ; - begin - retval = mod(x,1.0) ; - if( retval != 0.0 && x < 0.0 ) retval = x - 1.0 ; - else retval = x ; - floor = trunc(retval) ; - end - endfunction - - // Return the round function of a number - function real round ; - input real x ; - real retval ; - begin - retval = x > 0.0 ? x + 0.5 : x - 0.5 ; - round = trunc(retval) ; - end - endfunction - - // Return the fractional remainder of (x mod m) - function real mod ; - input real x ; - input real m ; - real retval ; - begin - retval = x ; - if( retval > m ) begin - while( retval > m ) begin - retval = retval - m ; - end - end - else begin - while( retval < -m ) begin - retval = retval + m ; - end - end - mod = retval ; - end - endfunction - - // Return the max between two real numbers - function real realmax ; - input real x ; - input real y ; - begin - realmax = x > y ? x : y ; - end - endfunction - - // Return the min between two real numbers - function real realmin ; - input real x ; - input real y ; - begin - realmin = x > y ? y : x ; - end - endfunction - - /* Random Numbers */ - - // Generate Gaussian distributed variables - function real gaussian ; - input real mean ; - input real var ; - real u1, u2, v1, v2, s ; - begin - s = 1.0 ; - while( s >= 1.0 ) begin - // Two random numbers between 0 and 1 - u1 = $random/4294967296.0 + 0.5 ; - u2 = $random/4294967296.0 + 0.5 ; - // Adjust to be between -1,1 - v1 = 2*u1-1.0 ; - v2 = 2*u2-1.0 ; - // Polar mag squared - s = (v1*v1 + v2*v2) ; - end - gaussian = mean + sqrt((-2.0*log(s))/s) * v1 * sqrt(var) ; - // gaussian2 = mean + sqrt(-2*log(s)/s)*v2 * sqrt(var) ; - end - endfunction - - /* Roots and Log Functions */ - - // Return the square root of a number - function real sqrt ; - input real x ; - real retval ; - begin - sqrt = (x == 0.0) ? 0.0 : powr(x,0.5) ; - end - endfunction - - // Return the cube root of a number - function real cbrt ; - input real x ; - real retval ; - begin - cbrt = (x == 0.0) ? 0.0 : powr(x,1.0/3.0) ; - end - endfunction - - // Return the absolute value of a real value - function real abs ; - input real x ; - begin - abs = (x > 0.0) ? x : -x ; - end - endfunction - - // Return a real value raised to an integer power - function real pow ; - input real b ; - input integer x ; - integer absx ; - real retval ; - begin - retval = 1.0 ; - absx = abs(x) ; - repeat(absx) begin - retval = b*retval ; - end - pow = x < 0 ? (1.0/retval) : retval ; - end - endfunction - - // Return a real value raised to a real power - function real powr ; - input real b ; - input real x ; - begin - powr = exp(x*log(b)) ; - end - endfunction - - // Return the evaluation of e^x where e is the natural logarithm base - // NOTE: This is the Taylor series expansion of e^x - function real exp ; - input real x ; - real retval ; - integer i ; - real nm1_fact ; - real powm1 ; - begin - nm1_fact = 1.0 ; - powm1 = 1.0 ; - retval = 1.0 ; - for( i = 1 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin - powm1 = x*powm1 ; - nm1_fact = nm1_fact * i ; - retval = retval + powm1/nm1_fact ; - end - exp = retval ; - end - endfunction - - // Return the evaluation log(x) - function real log ; - input real x ; - integer i ; - real whole ; - real xm1oxp1 ; - real retval ; - real newx ; - begin - retval = 0.0 ; - whole = 0.0 ; - newx = x ; - while( newx > MATH_E ) begin - whole = whole + 1.0 ; - newx = newx / MATH_E ; - end - xm1oxp1 = (newx-1.0)/(newx+1.0) ; - for( i = 0 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin - retval = retval + pow(xm1oxp1,2*i+1)/(2.0*i+1.0) ; - end - log = whole+2.0*retval ; - end - endfunction - - // Return the evaluation ln(x) (same as log(x)) - function real ln ; - input real x ; - begin - ln = log(x) ; - end - endfunction - - // Return the evaluation log_2(x) - function real log2 ; - input real x ; - begin - log2 = log(x)/MATH_LOG_OF_2 ; - end - endfunction - - function real log10 ; - input real x ; - begin - log10 = log(x)/MATH_LOG_OF_10 ; - end - endfunction - - function real log_base ; - input real x ; - input real b ; - begin - log_base = log(x)/log(b) ; - end - endfunction - - /* Trigonometric Functions */ - - // Internal function to reduce a value to be between [-pi:pi] - function real reduce ; - input real x ; - real retval ; - begin - retval = x ; - while( abs(retval) > MATH_PI ) begin - retval = retval > MATH_PI ? - (retval - MATH_2_PI) : - (retval + MATH_2_PI) ; - end - reduce = retval ; - end - endfunction - - // Return the cos of a number in radians - function real cos ; - input real x ; - integer i ; - integer sign ; - real newx ; - real retval ; - real xsqnm1 ; - real twonm1fact ; - begin - newx = reduce(x) ; - xsqnm1 = 1.0 ; - twonm1fact = 1.0 ; - retval = 1.0 ; - for( i = 1 ; i < COS_ITERATIONS ; i = i + 1 ) begin - sign = -2*(i % 2)+1 ; - xsqnm1 = xsqnm1*newx*newx ; - twonm1fact = twonm1fact * (2.0*i) * (2.0*i-1.0) ; - retval = retval + sign*(xsqnm1/twonm1fact) ; - end - cos = retval ; - end - endfunction - - // Return the sin of a number in radians - function real sin ; - input real x ; - begin - sin = cos(x - MATH_PI_OVER_2) ; - end - endfunction - - // Return the tan of a number in radians - function real tan ; - input real x ; - begin - tan = sin(x) / cos(x) ; - end - endfunction - - // Return the arcsin in radians of a number - function real arcsin ; - input real x ; - begin - arcsin = 2.0*arctan(x/(1.0+sqrt(1.0-x*x))) ; - end - endfunction - - // Return the arccos in radians of a number - function real arccos ; - input real x ; - begin - arccos = MATH_PI_OVER_2-arcsin(x) ; - end - endfunction - - // Return the arctan in radians of a number - // TODO: Make sure this REALLY does work as it is supposed to! - function real arctan ; - input real x ; - real retval ; - real y ; - real newx ; - real twoiotwoip1 ; - integer i ; - integer mult ; - begin - retval = 1.0 ; - twoiotwoip1 = 1.0 ; - mult = 1 ; - newx = abs(x) ; - while( newx > 1.0 ) begin - mult = mult*2 ; - newx = newx/(1.0+sqrt(1.0+newx*newx)) ; - end - y = 1.0 ; - for( i = 1 ; i < 2*COS_ITERATIONS ; i = i + 1 ) begin - y = y*((newx*newx)/(1+newx*newx)) ; - twoiotwoip1 = twoiotwoip1 * (2.0*i)/(2.0*i+1.0) ; - retval = retval + twoiotwoip1*y ; - end - retval = retval * (newx/(1+newx*newx)) ; - retval = retval * mult ; - - arctan = (x > 0.0) ? retval : -retval ; - end - endfunction - - // Return the arctan in radians of a ratio x/y - // TODO: Test to make sure this works as it is supposed to! - function real arctan_xy ; - input real x ; - input real y ; - real retval ; - begin - retval = 0.0 ; - if( x < 0.0 ) retval = MATH_PI - arctan(-abs(y)/x) ; - else if( x > 0.0 ) retval = arctan(abs(y)/x) ; - else if( x == 0.0 ) retval = MATH_PI_OVER_2 ; - arctan_xy = (y < 0.0) ? -retval : retval ; - end - endfunction - - /* Hyperbolic Functions */ - - // Return the sinh of a number - function real sinh ; - input real x ; - begin - sinh = (exp(x) - exp(-x))/2.0 ; - end - endfunction - - // Return the cosh of a number - function real cosh ; - input real x ; - begin - cosh = (exp(x) + exp(-x))/2.0 ; - end - endfunction - - // Return the tanh of a number - function real tanh ; - input real x ; - real e2x ; - begin - e2x = exp(2.0*x) ; - tanh = (e2x+1.0)/(e2x-1.0) ; - end - endfunction - - // Return the arcsinh of a number - function real arcsinh ; - input real x ; - begin - arcsinh = log(x+sqrt(x*x+1.0)) ; - end - endfunction - - // Return the arccosh of a number - function real arccosh ; - input real x ; - begin - arccosh = ln(x+sqrt(x*x-1.0)) ; - end - endfunction - - // Return the arctanh of a number - function real arctanh ; - input real x ; - begin - arctanh = 0.5*ln((1.0+x)/(1.0-x)) ; - end - endfunction - /* - initial begin - $display( "cos(MATH_PI_OVER_3): %f", cos(MATH_PI_OVER_3) ) ; - $display( "sin(MATH_PI_OVER_3): %f", sin(MATH_PI_OVER_3) ) ; - $display( "sign(-10): %f", sign(-10) ) ; - $display( "realmax(MATH_PI,MATH_E): %f", realmax(MATH_PI,MATH_E) ) ; - $display( "realmin(MATH_PI,MATH_E): %f", realmin(MATH_PI,MATH_E) ) ; - $display( "mod(MATH_PI,MATH_E): %f", mod(MATH_PI,MATH_E) ) ; - $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ; - $display( "ceil(4.0): %f", ceil(4.0) ) ; - $display( "ceil(3.99999999999999): %f", ceil(3.99999999999999) ) ; - $display( "pow(MATH_PI,2): %f", pow(MATH_PI,2) ) ; - $display( "gaussian(1.0,1.0): %f", gaussian(1.0,1.0) ) ; - $display( "round(MATH_PI): %f", round(MATH_PI) ) ; - $display( "trunc(-MATH_PI): %f", trunc(-MATH_PI) ) ; - $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ; - $display( "floor(MATH_PI): %f", floor(MATH_PI) ) ; - $display( "round(e): %f", round(MATH_E)) ; - $display( "ceil(-e): %f", ceil(-MATH_E)) ; - $display( "exp(MATH_PI): %f", exp(MATH_PI) ) ; - $display( "log2(MATH_PI): %f", log2(MATH_PI) ) ; - $display( "log_base(pow(2,32),2): %f", log_base(pow(2,32),2) ) ; - $display( "ln(0.1): %f", log(0.1) ) ; - $display( "cbrt(7): %f", cbrt(7) ) ; - $display( "cos(MATH_2_PI): %f", cos(20*MATH_2_PI) ) ; - $display( "sin(-MATH_2_PI): %f", sin(-50*MATH_2_PI) ) ; - $display( "sinh(MATH_E): %f", sinh(MATH_E) ) ; - $display( "cosh(MATH_2_PI): %f", cosh(MATH_2_PI) ) ; - $display( "arctan_xy(-4,3): %f", arctan_xy(-4,3) ) ; - $display( "arctan(MATH_PI): %f", arctan(MATH_PI) ) ; - $display( "arctan(-MATH_E/2): %f", arctan(-MATH_E/2) ) ; - $display( "arctan(MATH_PI_OVER_2): %f", arctan(MATH_PI_OVER_2) ) ; - $display( "arctan(1/7) = %f", arctan(1.0/7.0) ) ; - $display( "arctan(3/79) = %f", arctan(3.0/79.0) ) ; - $display( "pi/4 ?= %f", 5*arctan(1.0/7.0)+2*arctan(3.0/79.0) ) ; - $display( "arcsin(1.0): %f", arcsin(1.0) ) ; - $display( "cos(pi/2): %f", cos(MATH_PI_OVER_2)) ; - $display( "arccos(cos(pi/2)): %f", arccos(cos(MATH_PI_OVER_2)) ) ; - $display( "cos(0): %f", cos(0) ) ; - $display( "cos(MATH_PI_OVER_4): %f", cos(MATH_PI_OVER_4) ) ; - $display( "cos(MATH_PI_OVER_2): %f", cos(MATH_PI_OVER_2) ) ; - $display( "cos(3*MATH_PI_OVER_4): %f", cos(3*MATH_PI_OVER_4) ) ; - $display( "cos(MATH_PI): %f", cos(MATH_PI) ) ; - $display( "cos(5*MATH_PI_OVER_4): %f", cos(5*MATH_PI_OVER_4) ) ; - $display( "cos(6*MATH_PI_OVER_4): %f", cos(6*MATH_PI_OVER_4) ) ; - $display( "cos(7*MATH_PI_OVER_4): %f", cos(7*MATH_PI_OVER_4) ) ; - $display( "cos(8*MATH_PI_OVER_4): %f", cos(8*MATH_PI_OVER_4) ) ; - end*/ - -endmodule diff --git a/models/miim_model.v b/models/miim_model.v deleted file mode 100644 index 936d99a80..000000000 --- a/models/miim_model.v +++ /dev/null @@ -1,14 +0,0 @@ - -// Skeleton PHY interface simulator - -module miim_model(input mdc_i, - inout mdio, - input phy_resetn_i, - input phy_clk_i, - output phy_intn_o, - output [2:0] speed_o); - - assign phy_intn_o = 1; // No interrupts - assign speed_o = 3'b100; // 1G mode - -endmodule // miim_model diff --git a/models/phy_sim.v b/models/phy_sim.v deleted file mode 100644 index b3de19b04..000000000 --- a/models/phy_sim.v +++ /dev/null @@ -1,113 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Phy_sim.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// -//// //// -//// Author(s): //// -//// - Jon Gao (gaojon@yahoo.com) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: Phy_sim.v,v $ -// Revision 1.3 2006/11/17 17:53:07 maverickist -// no message -// -// Revision 1.2 2006/01/19 14:07:50 maverickist -// verification is complete. -// -// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator -// no message -// - -`timescale 1ns/100ps - -module phy_sim( - input Gtx_clk, // Used only in GMII mode - output Rx_clk, - output Tx_clk, // Used only in MII mode - input Tx_er, - input Tx_en, - input [7:0] Txd, - output Rx_er, - output Rx_dv, - output [7:0] Rxd, - output Crs, - output Col, - input [2:0] Speed, - input Done -); - -////////////////////////////////////////////////////////////////////// -// this file used to simulate Phy. -// generate clk and loop the Tx data to Rx data -// full duplex mode can be verified on loop mode. -////////////////////////////////////////////////////////////////////// -////////////////////////////////////////////////////////////////////// -// internal signals -////////////////////////////////////////////////////////////////////// -reg Clk_25m; // Used for 100 Mbps mode -reg Clk_2_5m; // Used for 10 Mbps mode - -//wire Rx_clk; -//wire Tx_clk; // Used only in MII mode - - initial - begin - #10; - while ( !Done ) - begin - #20 Clk_25m = 0; - #20 Clk_25m = 1; - end - end - - initial - begin - #10; - while ( !Done ) - begin - #200 Clk_2_5m = 0; - #200 Clk_2_5m = 1; - end - end - - assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; - assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; - - assign Rx_dv = Tx_en; - assign Rxd = Txd; - assign Rx_er = Tx_er; - assign Crs = Tx_en; - assign Col = 0; - -endmodule diff --git a/models/serdes_model.v b/models/serdes_model.v deleted file mode 100644 index f10e55554..000000000 --- a/models/serdes_model.v +++ /dev/null @@ -1,34 +0,0 @@ - -module serdes_model - (input ser_tx_clk, - input ser_tkmsb, - input ser_tklsb, - input [15:0] ser_t, - - output ser_rx_clk, - output ser_rkmsb, - output ser_rklsb, - output [15:0] ser_r, - - input even, - input error); - - wire [15:0] ser_r_odd; - wire ser_rklsb_odd, ser_rkmsb_odd; - - reg [7:0] hold_dat; - reg hold_k; - - always @(posedge ser_tx_clk) hold_k <= ser_tklsb; - always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8]; - assign ser_rklsb_odd = hold_k; - assign ser_rkmsb_odd = ser_tklsb; - assign ser_r_odd = {ser_t[7:0], hold_dat}; - - // Set outputs - assign ser_rx_clk = ser_tx_clk; - assign ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd; - assign ser_rklsb = even ? ser_tklsb : ser_rklsb_odd; - assign ser_r = error ^ (even ? ser_t : ser_r_odd); - -endmodule // serdes_model diff --git a/models/uart_rx.v b/models/uart_rx.v deleted file mode 100644 index f698a50fe..000000000 --- a/models/uart_rx.v +++ /dev/null @@ -1,48 +0,0 @@ - - -// Simple printout of characters from the UART -// Only does 8N1, requires the baud clock - -module uart_rx (input baudclk, input rxd); - reg [8:0] sr = 9'b0; - reg [3:0] baud_ctr = 4'b0; - - /* - wire byteclk = baud_ctr[3]; - reg rxd_d1 = 0; - always @(posedge baudclk) - rxd_d1 <= rxd; - - always @(posedge baudclk) - if(rxd_d1 != rxd) - baud_ctr <= 0; - else - baud_ctr <= baud_ctr + 1; -*/ - - wire byteclk = baudclk; - - always @(posedge byteclk) - sr <= { rxd, sr[8:1] }; - - reg [3:0] state = 0; - always @(posedge byteclk) - case(state) - 0 : - if(~sr[8] & sr[7]) // found start bit - state <= 1; - 1, 2, 3, 4, 5, 6, 7, 8 : - state <= state + 1; - 9 : - begin - state <= 0; - $write("%c",sr[7:0]); - if(~sr[8]) - $display("Error, no stop bit\n"); - end - default : - state <= 0; - endcase // case(state) - -endmodule // uart_rx - diff --git a/models/xlnx_glbl.v b/models/xlnx_glbl.v deleted file mode 100644 index 662a60e35..000000000 --- a/models/xlnx_glbl.v +++ /dev/null @@ -1,29 +0,0 @@ -module xlnx_glbl -( - GSR, - GTS -); - - //-------------------------------------------------------------------------- - // Parameters - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // IO declarations - //-------------------------------------------------------------------------- - - output GSR; - output GTS; - - //-------------------------------------------------------------------------- - // Local declarations - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // Internal declarations - //-------------------------------------------------------------------------- - - assign GSR = 0; - assign GTS = 0; - -endmodule diff --git a/opencores/8b10b/.gitignore b/opencores/8b10b/.gitignore deleted file mode 100644 index 548539d61..000000000 --- a/opencores/8b10b/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/dump.vcd -/a.out diff --git a/opencores/8b10b/8b10b_a.mem b/opencores/8b10b/8b10b_a.mem deleted file mode 100644 index 1761d74f6..000000000 --- a/opencores/8b10b/8b10b_a.mem +++ /dev/null @@ -1,268 +0,0 @@ -000000000100111010001100010110 -000000001011101010010001010110 -000000010101101010001001010110 -000000011110001101111000101001 -000000100110101010000101010110 -000000101101001101110100101001 -000000110011001101101100101001 -000000111111000101100011101001 -000001000111001010000011010110 -000001001100101101110010101001 -000001010010101101101010101001 -000001011110100101111010001001 -000001100001101101100110101001 -000001101101100101110110001001 -000001110011100101101110001001 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-111111100001111100011000001110 -111110111111010100000010101110 -111111011110110100000100101110 -111111101101110100001000101110 -111111110011110100010000101110 diff --git a/opencores/8b10b/README b/opencores/8b10b/README deleted file mode 100644 index 7bce294ac..000000000 --- a/opencores/8b10b/README +++ /dev/null @@ -1,4 +0,0 @@ -These files are not actually from OpenCores. They are from -Chuck Benz. See http://asics.chuckbenz.com - - diff --git a/opencores/8b10b/decode_8b10b.v b/opencores/8b10b/decode_8b10b.v deleted file mode 100644 index 0b2a8ac59..000000000 --- a/opencores/8b10b/decode_8b10b.v +++ /dev/null @@ -1,165 +0,0 @@ -// Chuck Benz, Hollis, NH Copyright (c)2002 -// -// The information and description contained herein is the -// property of Chuck Benz. -// -// Permission is granted for any reuse of this information -// and description as long as this copyright notice is -// preserved. Modifications may be made as long as this -// notice is preserved. - -// per Widmer and Franaszek - -module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ; - input [9:0] datain ; - input dispin ; - output [8:0] dataout ; - output dispout ; - output code_err ; - output disp_err ; - - wire ai = datain[0] ; - wire bi = datain[1] ; - wire ci = datain[2] ; - wire di = datain[3] ; - wire ei = datain[4] ; - wire ii = datain[5] ; - wire fi = datain[6] ; - wire gi = datain[7] ; - wire hi = datain[8] ; - wire ji = datain[9] ; - - wire aeqb = (ai & bi) | (!ai & !bi) ; - wire ceqd = (ci & di) | (!ci & !di) ; - wire p22 = (ai & bi & !ci & !di) | - (ci & di & !ai & !bi) | - ( !aeqb & !ceqd) ; - wire p13 = ( !aeqb & !ci & !di) | - ( !ceqd & !ai & !bi) ; - wire p31 = ( !aeqb & ci & di) | - ( !ceqd & ai & bi) ; - - wire p40 = ai & bi & ci & di ; - wire p04 = !ai & !bi & !ci & !di ; - - wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31. - wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits - wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits - - wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 | - (ei & ii & di)) & (ei | ii | di)) ; - - // The 5B/6B decoding special cases where ABCDE != abcde - - wire p22bceeqi = p22 & bi & ci & (ei == ii) ; - wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ; - wire p13in = p13 & !ii ; - wire p31i = p31 & ii ; - wire p13dei = p13 & di & ei & ii ; - wire p22aceeqi = p22 & ai & ci & (ei == ii) ; - wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ; - wire p13en = p13 & !ei ; - wire anbnenin = !ai & !bi & !ei & !ii ; - wire abei = ai & bi & ei & ii ; - wire cdei = ci & di & ei & ii ; - wire cndnenin = !ci & !di & !ei & !ii ; - - // non-zero disparity cases: - wire p22enin = p22 & !ei & !ii ; - wire p22ei = p22 & ei & ii ; - //wire p13in = p12 & !ii ; - //wire p31i = p31 & ii ; - wire p31dnenin = p31 & !di & !ei & !ii ; - //wire p13dei = p13 & di & ei & ii ; - wire p31e = p31 & ei ; - - wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi | - p13en | abei | cndnenin ; - wire compb = p22bceeqi | p31i | p13dei | p22aceeqi | - p13en | abei | cndnenin ; - wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi | - p13en | anbnenin | cndnenin ; - wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi | - p13en | abei | cndnenin ; - wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi | - p13en | anbnenin | cndnenin ; - - wire ao = ai ^ compa ; - wire bo = bi ^ compb ; - wire co = ci ^ compc ; - wire do = di ^ compd ; - wire eo = ei ^ compe ; - - wire feqg = (fi & gi) | (!fi & !gi) ; - wire heqj = (hi & ji) | (!hi & !ji) ; - wire fghj22 = (fi & gi & !hi & !ji) | - (!fi & !gi & hi & ji) | - ( !feqg & !heqj) ; - wire fghjp13 = ( !feqg & !hi & !ji) | - ( !heqj & !fi & !gi) ; - wire fghjp31 = ( (!feqg) & hi & ji) | - ( !heqj & fi & gi) ; - - wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ; - - wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) | - (p13 & !ei & ii & gi & hi & ji) | - (p31 & ei & !ii & !gi & !hi & !ji)) ; - - wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1 - ((dispin & ci & di & !ei & !ii) | ko | - (dispin & !ci & di & !ei & !ii))) | - (!fi & gi & hi & // 0111 cases, where disp6b is 0 - (( !dispin & !ci & !di & ei & ii) | ko | - ( !dispin & ci & !di & ei & ii))) ; - - wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ; - // k28 with positive disp into fghi - .1, .2, .5, and .6 special cases - wire k28p = ! (ci | di | ei | ii) ; - wire fo = (ji & !fi & (hi | !gi | k28p)) | - (fi & !ji & (!hi | gi | !k28p)) | - (k28p & gi & hi) | - (!k28p & !gi & !hi) ; - wire go = (ji & !fi & (hi | !gi | !k28p)) | - (fi & !ji & (!hi | gi |k28p)) | - (!k28p & gi & hi) | - (k28p & !gi & !hi) ; - wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) | - (fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) | - (!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ; - - wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ; - wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ; - wire disp4p = fghjp31 ; - wire disp4n = fghjp13 ; - - assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) | - (p13 & !ei & !ii) | (p31 & ei & ii) | - (ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) | - (ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) | - (!p31 & ei & !ii & !gi & !hi & !ji) | - (!p13 & !ei & ii & gi & hi & ji) | - (((ei & ii & !gi & !hi & !ji) | - (!ei & !ii & gi & hi & ji)) & - ! ((ci & di & ei) | (!ci & !di & !ei))) | - (disp6p & disp4p) | (disp6n & disp4n) | - (ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) | - (!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) | - (fi & gi & !hi & !ji & disp6p) | - (!fi & !gi & hi & ji & disp6n) | - (ci & di & ei & ii & !fi & !gi & !hi) | - (!ci & !di & !ei & !ii & fi & gi & hi) ; - - assign dataout = {ko, ho, go, fo, eo, do, co, bo, ao} ; - - // my disp err fires for any legal codes that violate disparity, may fire for illegal codes - assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) | - (dispin & !disp6n & fi & gi) | - (dispin & ai & bi & ci) | - (dispin & !disp6n & disp4p) | - (!dispin & !disp6p & !fi & !gi) | - (!dispin & !ai & !bi & !ci) | - (!dispin & !disp6p & disp4n) | - (disp6p & disp4p) | (disp6n & disp4n)) ; - -endmodule diff --git a/opencores/8b10b/encode_8b10b.v b/opencores/8b10b/encode_8b10b.v deleted file mode 100644 index c1f09b9ce..000000000 --- a/opencores/8b10b/encode_8b10b.v +++ /dev/null @@ -1,120 +0,0 @@ -// Chuck Benz, Hollis, NH Copyright (c)2002 -// -// The information and description contained herein is the -// property of Chuck Benz. -// -// Permission is granted for any reuse of this information -// and description as long as this copyright notice is -// preserved. Modifications may be made as long as this -// notice is preserved. - -// per Widmer and Franaszek - -module encode_8b10b (datain, dispin, dataout, dispout) ; - input [8:0] datain ; - input dispin ; // 0 = neg disp; 1 = pos disp - output [9:0] dataout ; - output dispout ; - - - wire ai = datain[0] ; - wire bi = datain[1] ; - wire ci = datain[2] ; - wire di = datain[3] ; - wire ei = datain[4] ; - wire fi = datain[5] ; - wire gi = datain[6] ; - wire hi = datain[7] ; - wire ki = datain[8] ; - - wire aeqb = (ai & bi) | (!ai & !bi) ; - wire ceqd = (ci & di) | (!ci & !di) ; - wire l22 = (ai & bi & !ci & !di) | - (ci & di & !ai & !bi) | - ( !aeqb & !ceqd) ; - wire l40 = ai & bi & ci & di ; - wire l04 = !ai & !bi & !ci & !di ; - wire l13 = ( !aeqb & !ci & !di) | - ( !ceqd & !ai & !bi) ; - wire l31 = ( !aeqb & ci & di) | - ( !ceqd & ai & bi) ; - - // The 5B/6B encoding - - wire ao = ai ; - wire bo = (bi & !l40) | l04 ; - wire co = l04 | ci | (ei & di & !ci & !bi & !ai) ; - wire do = di & ! (ai & bi & ci) ; - wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ; - wire io = (l22 & !ei) | - (ei & !di & !ci & !(ai&bi)) | // D16, D17, D18 - (ei & l40) | - (ki & ei & di & ci & !bi & !ai) | // K.28 - (ei & !di & ci & !bi & !ai) ; - - // pds16 indicates cases where d-1 is assumed + to get our encoded value - wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ; - // nds16 indicates cases where d-1 is assumed - to get our encoded value - wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ; - - // ndos6 is pds16 cases where d-1 is + yields - disp out - all of them - wire ndos6 = pd1s6 ; - // pdos6 is nds16 cases where d-1 is - yields + disp out - all but one - wire pdos6 = ki | (ei & !l22 & !l13) ; - - - // some Dx.7 and all Kx.7 cases result in run length of 5 case unless - // an alternate coding is used (referred to as Dx.A7, normal is Dx.P7) - // specifically, D11, D13, D14, D17, D18, D19. - wire alt7 = fi & gi & hi & (ki | - (dispin ? (!ei & di & l31) : (ei & !di & l13))) ; - - - wire fo = fi & ! alt7 ; - wire go = gi | (!fi & !gi & !hi) ; - wire ho = hi ; - wire jo = (!hi & (gi ^ fi)) | alt7 ; - - // nd1s4 is cases where d-1 is assumed - to get our encoded value - wire nd1s4 = fi & gi ; - // pd1s4 is cases where d-1 is assumed + to get our encoded value - wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ; - - // ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some - wire ndos4 = (!fi & !gi) ; - // pdos4 is nd1s4 cases where d-1 is - yields + disp out - wire pdos4 = fi & gi & hi ; - - // only legal K codes are K28.0->.7, K23/27/29/30.7 - // K28.0->7 is ei=di=ci=1,bi=ai=0 - // K23 is 10111 - // K27 is 11011 - // K29 is 11101 - // K30 is 11110 - so K23/27/29/30 are ei & l31 - wire illegalk = ki & - (ai | bi | !ci | !di | !ei) & // not K28.0->7 - (!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7 - - // now determine whether to do the complementing - // complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set - wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ; - - // disparity out of 5b6b is disp in with pdso6 and ndso6 - // pds16 indicates cases where d-1 is assumed + to get our encoded value - // ndos6 is cases where d-1 is + yields - disp out - // nds16 indicates cases where d-1 is assumed - to get our encoded value - // pdos6 is cases where d-1 is - yields + disp out - // disp toggles in all ndis16 cases, and all but that 1 nds16 case - - wire disp6 = dispin ^ (ndos6 | pdos6) ; - - wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ; - assign dispout = disp6 ^ (ndos4 | pdos4) ; - - assign dataout = {(jo ^ compls4), (ho ^ compls4), - (go ^ compls4), (fo ^ compls4), - (io ^ compls6), (eo ^ compls6), - (do ^ compls6), (co ^ compls6), - (bo ^ compls6), (ao ^ compls6)} ; - -endmodule diff --git a/opencores/8b10b/validate_8b10b.v b/opencores/8b10b/validate_8b10b.v deleted file mode 100644 index 926b1081d..000000000 --- a/opencores/8b10b/validate_8b10b.v +++ /dev/null @@ -1,168 +0,0 @@ -// Chuck Benz, Hollis, NH Copyright (c)2002 -// -// The information and description contained herein is the -// property of Chuck Benz. -// -// Permission is granted for any reuse of this information -// and description as long as this copyright notice is -// preserved. Modifications may be made as long as this -// notice is preserved. - -// 11-OCT-2002: updated with clearer messages, and checking decodeout - -`timescale 1ns / 1ns -module test_8b10b ; - reg [29:0] code8b10b [0:267] ; - reg [8:0] testin ; - reg dispin ; - reg [10:0] i ; - wire [9:0] testout ; - wire dispout, decodedisp, decodeerr, disperr ; - wire [8:0] decodeout ; - // My data file is 30 columns. Column 1 becomes [29], 2 becomes [28], etc.. - // code[0] is last Column (30) - // First column, [29] is K indication - // columns 2:9, [28:21], are data byte, aka 'm' and 'n' of Dm.n - // columns 10:19, [20:11] are 10b symbol if starting disparity was negative, 0 - // columns 20:29, [10:1] are 10b symbol if starting disparity was positive, 1 - // column 30, [0], is a 1 if symbol results in a disparity flip - // 0 for a balanced symbol (5 '1's, 5 '0's). - - wire [29:0] code = code8b10b[i] ; - wire [9:0] expect_0_disp = {code[11], code[12], code[13], code[14], code[15], - code[16], code[17], code[18], code[19], code[20]} ; - wire [9:0] expect_1_disp = {code[1], code[2], code[3], code[4], code[5], - code[6], code[7], code[8], code[9], code[10]} ; - - reg [1023:0] legal ; // mark every used 10b symbol as legal, leave rest marked as not - reg [2047:0] okdisp ; // now mark every used combination of symbol and starting disparity - reg [8:0] mapcode [1023:0] ; - reg [10:0] codedisp0, codedisp1 ; - reg [9:0] decodein ; - reg decdispin ; - integer errors ; - - encode_8b10b DUTE (testin, dispin, testout, dispout) ; - decode_8b10b DUTD (decodein, decdispin, decodeout, decodedisp, decodeerr, disperr) ; - - always @ (code) testin = code[29:21] ; - - initial begin - errors = 0 ; - $readmemb ("8b10b_a.mem", code8b10b) ; - //$vcdpluson ; - $dumpvars (0); - $display ("\n\nFirst, test by trying all 268 (256 Dx.y and 12 Kx.y)") ; - $display ("valid inputs, with both + and - starting disparity."); - $display ("We check that the encoder output and ending disparity is correct."); - $display ("We also check that the decoder matches."); - for (i = 0 ; i < 268 ; i = i + 1) begin - // testin = code[29:21] ; - dispin = 0 ; - #1 - decodein = testout ; - decdispin = dispin ; - #1 -// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ; - if (testout != expect_0_disp) - $display ("bad code0 %b %b %b %b %b", dispin, testin, dispout, testout, expect_0_disp) ; - if (dispout != (dispin ^ code[0])) - $display ("bad disp0 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ; - if (0 != (9'b1_1111_1111 & (testin ^ decodeout))) - $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if (decodedisp != dispout) - $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if ((testout != expect_0_disp) | decodeerr | - (dispout != (dispin ^ code[0])) | (decodedisp != dispout)) - errors = errors + 1 ; - - dispin = 1 ; - #1 - decodein = testout ; - decdispin = dispin ; - #1 -// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2, DUTD.fghjp31, DUTD.feqg, DUTD.heqj, DUTD.fghj22, DUTD.fi, DUTD.gi, DUTD.hi, DUTD.ji, DUTD.dispout}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ; - if (testout != expect_1_disp) - $display ("bad code1 %b %b %b %b %b", dispin, testin, dispout, testout, expect_1_disp) ; - if (dispout != (dispin ^ code[0])) - $display ("bad disp1 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ; - if (0 != (9'b1_1111_1111 & (testin ^ decodeout))) - $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if (decodedisp != dispout) - $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; - if ((testout != expect_1_disp) | decodeerr | - (dispout != (dispin ^ code[0])) | (decodedisp != dispout)) - errors = errors + 1 ; - end - $display ("%d errors in that testing.\n", errors) ; - - // Now, having verified all legal codes, lets run some illegal codes - // at the decoder... how to figure illegal codes ? 2048 possible cases, - // lets mark the OK ones... - legal = 0 ; - okdisp = 0 ; - for (i = 0 ; i < 268 ; i = i + 1) begin - #1 -// $display ("i=%d: %b %b %d %d %x %x", i, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp) ; - legal[expect_0_disp] = 1 ; - legal[expect_1_disp] = 1 ; - codedisp0 = expect_0_disp ; - codedisp1 = {1'b1, expect_1_disp} ; - okdisp[codedisp0] = 1 ; - okdisp[codedisp1] = 1 ; - mapcode[expect_0_disp] = code[29:21] ; - mapcode[expect_1_disp] = code[29:21] ; - end - - $display ("Now lets test all (legal and illegal) codes into the decoder."); - $display ("checking all possible decode inputs") ; - for (i = 0 ; i < 1024 ; i = i + 1) begin - decodein = i ; - decdispin = 0 ; - codedisp1 = 1024 | i ; - #1 - if (((legal[i] == 0) & (decodeerr != 1)) | - (legal[i] & (mapcode[i] != decodeout)) | - (legal[i] & (disperr != !okdisp[i]))) - $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", - decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i]) ; - if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ; - if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ; - if (legal[i] & (disperr != 1) & !okdisp[i]) $display ("ERR: disp err should be asserted") ; - else if (legal[i] & (disperr != 0) & okdisp[i]) - $display ("ERR: disp err should not be asserted") ; - - if (((legal[i] == 0) & (decodeerr != 1)) | - (legal[i] & !disperr & !okdisp[i]) | - (legal[i] & (mapcode[i] != decodeout)) | - (legal[i] & disperr & okdisp[i])) - errors = errors + 1 ; - - decdispin = 1 ; - #1 - if (((legal[i] == 0) & (decodeerr != 1)) | - (legal[i] & (mapcode[i] != decodeout)) | - (legal[i] & (disperr != !okdisp[i|1024]))) - $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", - decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i|1024]) ; - if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ; - if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ; - if (legal[i] & (disperr != 1) & !okdisp[i|1024]) $display ("ERR: disp err should be asserted") ; - else if (legal[i] & (disperr != 0) & okdisp[i|1024]) - $display ("ERR: disp err should not be asserted") ; - if (((legal[i] == 0) & (decodeerr != 1)) | - (legal[i] & !disperr & !okdisp[i|1024]) | - (legal[i] & (mapcode[i] != decodeout)) | - (legal[i] & disperr & okdisp[i|1024])) - errors = errors + 1 ; - end // for (i = 0 ; i < 1024 ; i = i + 1) - - $display ("\nDone testing decoder.\n") ; - $display ("Total error count: %d", errors); - if (errors == 0) $display ("Congratulations!\n"); - $finish ; - end // initial begin - -endmodule diff --git a/opencores/README b/opencores/README deleted file mode 100644 index d63b7cbdb..000000000 --- a/opencores/README +++ /dev/null @@ -1,11 +0,0 @@ -All the subdirectories of this directory contain code from the OpenCores -project, checked out directly from the OpenCores CVS server. You can update -any directory to the latest OpenCores code by doing "cvs up" in that. -This is not recommended unless you know what you are doing. - - -Each directory contains its own copyright and licensing information. We -believe that we have the right to distribute all of these files in the form -in which we provide them. If this is not the case, please notify Matt Ettus, -matt@ettus.com. - diff --git a/opencores/aemb/CVS/.gitignore b/opencores/aemb/CVS/.gitignore deleted file mode 100644 index b693d7c72..000000000 --- a/opencores/aemb/CVS/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/Entries.Log diff --git a/opencores/aemb/CVS/Entries b/opencores/aemb/CVS/Entries deleted file mode 100644 index 093a9a86a..000000000 --- a/opencores/aemb/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -D/rtl//// -D/sim//// -D/sw//// -D/doc//// diff --git a/opencores/aemb/CVS/Repository b/opencores/aemb/CVS/Repository deleted file mode 100644 index 967f2cedf..000000000 --- a/opencores/aemb/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb diff --git a/opencores/aemb/CVS/Root b/opencores/aemb/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/aemb/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/aemb/CVS/Template b/opencores/aemb/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/aemb/doc/CVS/Entries b/opencores/aemb/doc/CVS/Entries deleted file mode 100644 index 16bb46ac6..000000000 --- a/opencores/aemb/doc/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/aeMB_datasheet.pdf/1.3/Tue Jan 15 18:38:57 2008/-kb/ -D diff --git a/opencores/aemb/doc/CVS/Repository b/opencores/aemb/doc/CVS/Repository deleted file mode 100644 index 41df302a9..000000000 --- a/opencores/aemb/doc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/doc diff --git a/opencores/aemb/doc/CVS/Root b/opencores/aemb/doc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/aemb/doc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/aemb/doc/CVS/Template b/opencores/aemb/doc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/aemb/doc/aeMB_datasheet.pdf b/opencores/aemb/doc/aeMB_datasheet.pdf deleted file mode 100644 index 5b26ac319..000000000 Binary files a/opencores/aemb/doc/aeMB_datasheet.pdf and /dev/null differ diff --git a/opencores/aemb/rtl/CVS/Entries b/opencores/aemb/rtl/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/opencores/aemb/rtl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/opencores/aemb/rtl/CVS/Repository b/opencores/aemb/rtl/CVS/Repository deleted file mode 100644 index e2c1eab77..000000000 --- a/opencores/aemb/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/rtl diff --git a/opencores/aemb/rtl/CVS/Root b/opencores/aemb/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/aemb/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/aemb/rtl/CVS/Template b/opencores/aemb/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/aemb/rtl/verilog/.gitignore b/opencores/aemb/rtl/verilog/.gitignore deleted file mode 100644 index 6b09f5cc9..000000000 --- a/opencores/aemb/rtl/verilog/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/aeMB2* diff --git a/opencores/aemb/rtl/verilog/CVS/Entries b/opencores/aemb/rtl/verilog/CVS/Entries deleted file mode 100644 index f17d70235..000000000 --- a/opencores/aemb/rtl/verilog/CVS/Entries +++ /dev/null @@ -1,38 +0,0 @@ -/aeMB2_aslu.v/1.10/Tue May 20 18:13:50 2008// -/aeMB2_bpcu.v/1.5/Tue May 20 18:13:50 2008// -/aeMB2_brcc.v/1.3/Tue May 20 18:13:50 2008// -/aeMB2_bsft.v/1.3/Tue May 20 18:13:50 2008// -/aeMB2_ctrl.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_dparam.v/1.1/Tue May 20 18:13:51 2008// -/aeMB2_dwbif.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_edk32.v/1.8/Tue May 20 18:13:51 2008// -/aeMB2_edk62.v/1.8/Tue May 20 18:13:51 2008// -/aeMB2_exec.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_gprf.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_iche.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_idmx.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_intu.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_iwbif.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_memif.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_mult.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_ofid.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_opmx.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_pipe.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_regf.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_regs.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_sfrf.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_sim.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_sparam.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_spsram.v/1.1/Tue May 20 18:13:51 2008// -/aeMB2_sysc.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_tpsram.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_xslif.v/1.7/Tue May 20 18:13:52 2008// -/aeMB_bpcu.v/1.4/Thu Sep 11 02:11:12 2008// -/aeMB_core.v/1.9/Thu Sep 11 02:11:12 2008// -/aeMB_ctrl.v/1.10/Thu Sep 11 02:11:12 2008// -/aeMB_edk32.v/1.14/Thu Sep 11 02:11:12 2008// -/aeMB_ibuf.v/1.10/Thu Sep 11 02:11:12 2008// -/aeMB_regf.v/1.3/Thu Sep 11 02:11:12 2008// -/aeMB_sim.v/1.2/Thu Jan 22 05:50:30 2009// -/aeMB_xecu.v/1.12/Thu Sep 11 02:11:12 2008// -D diff --git a/opencores/aemb/rtl/verilog/CVS/Repository b/opencores/aemb/rtl/verilog/CVS/Repository deleted file mode 100644 index a9de19556..000000000 --- a/opencores/aemb/rtl/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/rtl/verilog diff --git a/opencores/aemb/rtl/verilog/CVS/Root b/opencores/aemb/rtl/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/aemb/rtl/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/aemb/rtl/verilog/CVS/Template b/opencores/aemb/rtl/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/opencores/aemb/rtl/verilog/aeMB_bpcu.v deleted file mode 100644 index a7c686e7e..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_bpcu.v +++ /dev/null @@ -1,184 +0,0 @@ -// $Id: aeMB_bpcu.v,v 1.4 2007/11/14 22:14:34 sybreon Exp $ -// -// AEMB BRANCH PROGRAMME COUNTER UNIT -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see . -// -// $Log: aeMB_bpcu.v,v $ -// Revision 1.4 2007/11/14 22:14:34 sybreon -// Changed interrupt handling system (reported by M. Ettus). -// -// Revision 1.3 2007/11/10 16:39:38 sybreon -// Upgraded license to LGPLv3. -// Significant performance optimisations. -// -// Revision 1.2 2007/11/02 19:20:58 sybreon -// Added better (beta) interrupt support. -// Changed MSR_IE to disabled at reset as per MB docs. -// -// Revision 1.1 2007/11/02 03:25:39 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// - -module aeMB_bpcu (/*AUTOARG*/ - // Outputs - iwb_adr_o, rPC, rPCLNK, rBRA, rDLY, - // Inputs - rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, gclk, grst, gena - ); - parameter IW = 24; - - // INST WISHBONE - output [IW-1:2] iwb_adr_o; - - // INTERNAL - output [31:2] rPC, rPCLNK; - output rBRA; - output rDLY; - //output [1:0] rATOM; - //output [1:0] xATOM; - - input [1:0] rMXALT; - input [5:0] rOPC; - input [4:0] rRD, rRA; - input [31:0] rRESULT; // ALU - input [31:0] rDWBDI; // RAM - input [31:0] rREGA; - //input [1:0] rXCE; - - // SYSTEM - input gclk, grst, gena; - - // --- BRANCH CONTROL -------------------------------------------- - // Controls the branch and delay flags - - wire fRTD = (rOPC == 6'o55); - wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57); - wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56); - - wire [31:0] wREGA; - assign wREGA = (rMXALT == 2'o2) ? rDWBDI : - (rMXALT == 2'o1) ? rRESULT : - rREGA; - - wire wBEQ = (wREGA == 32'd0); - wire wBNE = ~wBEQ; - wire wBLT = wREGA[31]; - wire wBLE = wBLT | wBEQ; - wire wBGE = ~wBLT; - wire wBGT = ~wBLE; - - reg xXCC; - always @(/*AUTOSENSE*/rRD or wBEQ or wBGE or wBGT or wBLE or wBLT - or wBNE) - case (rRD[2:0]) - 3'o0: xXCC <= wBEQ; - 3'o1: xXCC <= wBNE; - 3'o2: xXCC <= wBLT; - 3'o3: xXCC <= wBLE; - 3'o4: xXCC <= wBGT; - 3'o5: xXCC <= wBGE; - default: xXCC <= 1'bX; - endcase // case (rRD[2:0]) - - reg rBRA, xBRA; - reg rDLY, xDLY; - wire fSKIP = rBRA & !rDLY; - - always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD - or xXCC) - //if (rBRA | |rXCE) begin - if (rBRA) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xBRA <= 1'h0; - xDLY <= 1'h0; - // End of automatics - end else begin - xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD; - xBRA <= (fRTD | fBRU) ? 1'b1 : - (fBCC) ? xXCC : - 1'b0; - end - - // --- PC PIPELINE ------------------------------------------------ - // PC and related changes - - reg [31:2] rIPC, xIPC; - reg [31:2] rPC, xPC; - reg [31:2] rPCLNK, xPCLNK; - - assign iwb_adr_o = rIPC[IW-1:2]; - - always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin - //xPCLNK <= (^rATOM) ? rPC : rPC; - xPCLNK <= rPC; - //xPC <= (^rATOM) ? rIPC : rRESULT[31:2]; - xPC <= rIPC; - //xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); - /* - case (rXCE) - 2'o1: xIPC <= 30'h2; - 2'o2: xIPC <= 30'h4; - 2'o3: xIPC <= 30'h6; - default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); - endcase // case (rXCE) - */ - xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); - end - - // --- ATOMIC CONTROL --------------------------------------------- - // This is used to indicate 'safe' instruction borders. - - wire wIMM = (rOPC == 6'o54) & !fSKIP; - wire wRTD = (rOPC == 6'o55) & !fSKIP; - wire wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP; - wire wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP; - - wire fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA); - reg [1:0] rATOM, xATOM; - - always @(/*AUTOSENSE*/fATOM or rATOM) - xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)}; - - - // --- SYNC PIPELINE ---------------------------------------------- - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rATOM <= 2'h0; - rBRA <= 1'h0; - rDLY <= 1'h0; - rIPC <= 30'h0; - rPC <= 30'h0; - rPCLNK <= 30'h0; - // End of automatics - end else if (gena) begin - rIPC <= #1 xIPC; - rBRA <= #1 xBRA; - rPC <= #1 xPC; - rPCLNK <= #1 xPCLNK; - rDLY <= #1 xDLY; - rATOM <= #1 xATOM; - end - -endmodule // aeMB_bpcu diff --git a/opencores/aemb/rtl/verilog/aeMB_core.v b/opencores/aemb/rtl/verilog/aeMB_core.v deleted file mode 100644 index 20ce9852e..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_core.v +++ /dev/null @@ -1,137 +0,0 @@ -// $Id: aeMB_core.v,v 1.9 2007/11/23 14:06:41 sybreon Exp $ -// -// AEMB 32'bit RISC MICROPROCESSOR CORE -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see . -// -// HISTORY -// $Log: aeMB_core.v,v $ -// Revision 1.9 2007/11/23 14:06:41 sybreon -// Old version deprecated. -// -// Revision 1.8 2007/10/22 19:12:59 sybreon -// Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. -// -// Revision 1.7 2007/05/30 18:44:30 sybreon -// Added interrupt support. -// -// Revision 1.6 2007/05/17 09:08:21 sybreon -// Removed asynchronous reset signal. -// -// Revision 1.5 2007/04/27 00:23:55 sybreon -// Added code documentation. -// Improved size & speed of rtl/verilog/aeMB_aslu.v -// -// Revision 1.4 2007/04/25 22:15:04 sybreon -// Added support for 8-bit and 16-bit data types. -// -// Revision 1.3 2007/04/11 04:30:43 sybreon -// Added pipeline stalling from incomplete bus cycles. -// Separated sync and async portions of code. -// -// Revision 1.2 2007/04/04 06:13:23 sybreon -// Removed unused signals -// -// Revision 1.1 2007/03/09 17:52:17 sybreon -// initial import -// - - -module aeMB_core (/*AUTOARG*/ - // Outputs - iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, - fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, - // Inputs - sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, - fsl_ack_i, dwb_dat_i, dwb_ack_i - ); - // Instruction WB address space - parameter ISIZ = 32; - // Data WB address space - parameter DSIZ = 32; - // Multiplier - parameter MUL = 1; - // Barrel Shifter - parameter BSF = 1; - - /*AUTOOUTPUT*/ - // Beginning of automatic outputs (from unused autoinst outputs) - output [DSIZ-1:2] dwb_adr_o; // From edk32 of aeMB_edk32.v - output [31:0] dwb_dat_o; // From edk32 of aeMB_edk32.v - output [3:0] dwb_sel_o; // From edk32 of aeMB_edk32.v - output dwb_stb_o; // From edk32 of aeMB_edk32.v - output dwb_wre_o; // From edk32 of aeMB_edk32.v - output [6:2] fsl_adr_o; // From edk32 of aeMB_edk32.v - output [31:0] fsl_dat_o; // From edk32 of aeMB_edk32.v - output fsl_stb_o; // From edk32 of aeMB_edk32.v - output [1:0] fsl_tag_o; // From edk32 of aeMB_edk32.v - output fsl_wre_o; // From edk32 of aeMB_edk32.v - output [ISIZ-1:2] iwb_adr_o; // From edk32 of aeMB_edk32.v - output iwb_stb_o; // From edk32 of aeMB_edk32.v - // End of automatics - /*AUTOINPUT*/ - // Beginning of automatic inputs (from unused autoinst inputs) - input dwb_ack_i; // To edk32 of aeMB_edk32.v - input [31:0] dwb_dat_i; // To edk32 of aeMB_edk32.v - input fsl_ack_i; // To edk32 of aeMB_edk32.v - input [31:0] fsl_dat_i; // To edk32 of aeMB_edk32.v - input iwb_ack_i; // To edk32 of aeMB_edk32.v - input [31:0] iwb_dat_i; // To edk32 of aeMB_edk32.v - input sys_clk_i; // To edk32 of aeMB_edk32.v - input sys_int_i; // To edk32 of aeMB_edk32.v - input sys_rst_i; // To edk32 of aeMB_edk32.v - // End of automatics - /*AUTOWIRE*/ - - // INSTANTIATIONS ///////////////////////////////////////////////////////////////// - - /* - aeMB_edk32 AUTO_TEMPLATE ( - .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), - .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), - ); - */ - - aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF) - edk32 (/*AUTOINST*/ - // Outputs - .dwb_adr_o (dwb_adr_o[DSIZ-1:2]), // Templated - .dwb_dat_o (dwb_dat_o[31:0]), - .dwb_sel_o (dwb_sel_o[3:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_wre_o (dwb_wre_o), - .fsl_adr_o (fsl_adr_o[6:2]), - .fsl_dat_o (fsl_dat_o[31:0]), - .fsl_stb_o (fsl_stb_o), - .fsl_tag_o (fsl_tag_o[1:0]), - .fsl_wre_o (fsl_wre_o), - .iwb_adr_o (iwb_adr_o[ISIZ-1:2]), // Templated - .iwb_stb_o (iwb_stb_o), - // Inputs - .dwb_ack_i (dwb_ack_i), - .dwb_dat_i (dwb_dat_i[31:0]), - .fsl_ack_i (fsl_ack_i), - .fsl_dat_i (fsl_dat_i[31:0]), - .iwb_ack_i (iwb_ack_i), - .iwb_dat_i (iwb_dat_i[31:0]), - .sys_int_i (sys_int_i), - .sys_clk_i (sys_clk_i), - .sys_rst_i (sys_rst_i)); - - -endmodule // aeMB_core diff --git a/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/opencores/aemb/rtl/verilog/aeMB_core_BE.v deleted file mode 100644 index 9ffa20ff2..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_core_BE.v +++ /dev/null @@ -1,62 +0,0 @@ - -// Wrapper for aeMB core: -// Drive wb_cyc_o (just tied to wb_stb_o for now) -// Make input reset active high (like the signal name makes it sound....) -// No longer needed -// Make it big-endian like the standard MicroBlaze - -module aeMB_core_BE - #(parameter ISIZ=32, parameter DSIZ=32, - parameter MUL=0, parameter BSF=0) - (input sys_clk_i, - input sys_rst_i, - - output iwb_stb_o, - output [ISIZ-1:0] iwb_adr_o, - input [31:0] iwb_dat_i, - input iwb_ack_i, - - output dwb_we_o, - output dwb_stb_o, - output [DSIZ-1:0] dwb_adr_o, - output [31:0] dwb_dat_o, - input [31:0] dwb_dat_i, - input dwb_ack_i, - output [3:0] dwb_sel_o, - output dwb_cyc_o, - - input sys_int_i, - input sys_exc_i); - - assign dwb_cyc_o = dwb_stb_o; - - aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF)) - aeMB_edk32 (.sys_clk_i(sys_clk_i), - .sys_rst_i(sys_rst_i), - - .iwb_stb_o(iwb_stb_o), - .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), - .iwb_ack_i(iwb_ack_i), - .iwb_dat_i(iwb_dat_i), - - .dwb_wre_o(dwb_we_o), - .dwb_stb_o(dwb_stb_o), - .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), - .dwb_ack_i(dwb_ack_i), - .dwb_sel_o(dwb_sel_o), - .dwb_dat_i(dwb_dat_i), - .dwb_dat_o(dwb_dat_o), - - .fsl_wre_o(), - .fsl_tag_o(), - .fsl_stb_o(), - .fsl_dat_o(), - .fsl_adr_o(), - .fsl_dat_i(32'b0), - .fsl_ack_i(1'b0), - .sys_int_i(sys_int_i) ); - - assign iwb_adr_o[1:0] = 2'b0; - assign dwb_adr_o[1:0] = 2'b0; - -endmodule // aeMB_core_BE diff --git a/opencores/aemb/rtl/verilog/aeMB_ctrl.v b/opencores/aemb/rtl/verilog/aeMB_ctrl.v deleted file mode 100644 index 88d4e51ce..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_ctrl.v +++ /dev/null @@ -1,336 +0,0 @@ -// $Id: aeMB_ctrl.v,v 1.10 2007/11/30 16:44:40 sybreon Exp $ -// -// AEMB CONTROL UNIT -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see . -// -// $Log: aeMB_ctrl.v,v $ -// Revision 1.10 2007/11/30 16:44:40 sybreon -// Minor code cleanup. -// -// Revision 1.9 2007/11/15 09:26:43 sybreon -// Fixed minor typo causing synthesis failure. -// -// Revision 1.8 2007/11/14 23:19:24 sybreon -// Fixed minor typo. -// -// Revision 1.7 2007/11/14 22:14:34 sybreon -// Changed interrupt handling system (reported by M. Ettus). -// -// Revision 1.6 2007/11/10 16:39:38 sybreon -// Upgraded license to LGPLv3. -// Significant performance optimisations. -// -// Revision 1.5 2007/11/09 20:51:52 sybreon -// Added GET/PUT support through a FSL bus. -// -// Revision 1.4 2007/11/08 17:48:14 sybreon -// Fixed data WISHBONE arbitration problem (reported by J Lee). -// -// Revision 1.3 2007/11/08 14:17:47 sybreon -// Parameterised optional components. -// -// Revision 1.2 2007/11/02 19:20:58 sybreon -// Added better (beta) interrupt support. -// Changed MSR_IE to disabled at reset as per MB docs. -// -// Revision 1.1 2007/11/02 03:25:40 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// - -module aeMB_ctrl (/*AUTOARG*/ - // Outputs - rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o, - fsl_stb_o, fsl_wre_o, - // Inputs - rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG, - dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena - ); - // INTERNAL - //output [31:2] rPCLNK; - output [1:0] rMXDST; - output [1:0] rMXSRC, rMXTGT, rMXALT; - output [2:0] rMXALU; - output [4:0] rRW; - - input rDLY; - input [15:0] rIMM; - input [10:0] rALT; - input [5:0] rOPC; - input [4:0] rRD, rRA, rRB; - input [31:2] rPC; - input rBRA; - input rMSR_IE; - input [31:0] xIREG; - - // DATA WISHBONE - output dwb_stb_o; - output dwb_wre_o; - input dwb_ack_i; - - // INST WISHBONE - input iwb_ack_i; - - // FSL WISHBONE - output fsl_stb_o; - output fsl_wre_o; - input fsl_ack_i; - - // SYSTEM - input gclk, grst, gena; - - // --- DECODE INSTRUCTIONS - // TODO: Simplify - - wire [5:0] wOPC; - wire [4:0] wRD, wRA, wRB; - wire [10:0] wALT; - - assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian - - wire fSFT = (rOPC == 6'o44); - wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4); - - wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30); - wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31); - wire fDIV = (rOPC == 6'o22); - - wire fRTD = (rOPC == 6'o55); - wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57); - wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56); - wire fBRA = fBRU & rRA[3]; - - wire fIMM = (rOPC == 6'o54); - wire fMOV = (rOPC == 6'o45); - - wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6); - wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7); - wire fLDST = (&rOPC[5:4]); - - wire fPUT = (rOPC == 6'o33) & rRB[4]; - wire fGET = (rOPC == 6'o33) & !rRB[4]; - - - wire wSFT = (wOPC == 6'o44); - wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4); - - wire wMUL = (wOPC == 6'o20) | (wOPC == 6'o30); - wire wBSF = (wOPC == 6'o21) | (wOPC == 6'o31); - wire wDIV = (wOPC == 6'o22); - - wire wRTD = (wOPC == 6'o55); - wire wBCC = (wOPC == 6'o47) | (wOPC == 6'o57); - wire wBRU = (wOPC == 6'o46) | (wOPC == 6'o56); - wire wBRA = wBRU & wRA[3]; - - wire wIMM = (wOPC == 6'o54); - wire wMOV = (wOPC == 6'o45); - - wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6); - wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7); - wire wLDST = (&wOPC[5:4]); - - wire wPUT = (wOPC == 6'o33) & wRB[4]; - wire wGET = (wOPC == 6'o33) & !wRB[4]; - - - // --- BRANCH SLOT REGISTERS --------------------------- - - reg [31:2] rPCLNK, xPCLNK; - reg [1:0] rMXDST, xMXDST; - reg [4:0] rRW, xRW; - - reg [1:0] rMXSRC, xMXSRC; - reg [1:0] rMXTGT, xMXTGT; - reg [1:0] rMXALT, xMXALT; - - - // --- OPERAND SELECTOR --------------------------------- - - wire wRDWE = |xRW; - wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE; - wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE; - wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE; - wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE; - - always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M - or wBFWD_R or wBRU or wOPC) - //if (rBRA | |rXCE) begin - if (rBRA) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xMXALT <= 2'h0; - xMXSRC <= 2'h0; - xMXTGT <= 2'h0; - // End of automatics - end else begin - xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC - (wAFWD_M) ? 2'o2 : // RAM - (wAFWD_R) ? 2'o1 : // FWD - 2'o0; // REG - xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM - (wBFWD_M) ? 2'o2 : // RAM - (wBFWD_R) ? 2'o1 : // FWD - 2'o0; // REG - xMXALT <= (wAFWD_M) ? 2'o2 : // RAM - (wAFWD_R) ? 2'o1 : // FWD - 2'o0; // REG - end // else: !if(rBRA) - - // --- ALU CONTROL --------------------------------------- - - reg [2:0] rMXALU, xMXALU; - - always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV - or wMUL or wSFT) - //if (rBRA | |rXCE) begin - if (rBRA) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xMXALU <= 3'h0; - // End of automatics - end else begin - xMXALU <= (wBRA | wMOV) ? 3'o3 : - (wSFT) ? 3'o2 : - (wLOG) ? 3'o1 : - (wMUL) ? 3'o4 : - (wBSF) ? 3'o5 : - (wDIV) ? 3'o6 : - 3'o0; - end // else: !if(rBRA) - - // --- DELAY SLOT REGISTERS ------------------------------ - - wire fSKIP = (rBRA & !rDLY); - - always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP - or fSTR or rRD) - if (fSKIP) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xMXDST <= 2'h0; - xRW <= 5'h0; - // End of automatics - end else begin - xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 : - (fLOD | fGET) ? 2'o2 : - (fBRU) ? 2'o1 : - 2'o0; - xRW <= rRD; - end // else: !if(fSKIP) - - - // --- DATA WISHBONE ---------------------------------- - - wire fDACK = !(dwb_stb_o ^ dwb_ack_i); - - reg rDWBSTB, xDWBSTB; - reg rDWBWRE, xDWBWRE; - - assign dwb_stb_o = rDWBSTB; - assign dwb_wre_o = rDWBWRE; - - - always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i) - //if (fSKIP | |rXCE) begin - if (fSKIP) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xDWBSTB <= 1'h0; - xDWBWRE <= 1'h0; - // End of automatics - end else begin - xDWBSTB <= (fLOD | fSTR) & iwb_ack_i; - xDWBWRE <= fSTR & iwb_ack_i; - end - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rDWBSTB <= 1'h0; - rDWBWRE <= 1'h0; - // End of automatics - end else if (fDACK) begin - rDWBSTB <= #1 xDWBSTB; - rDWBWRE <= #1 xDWBWRE; - end - - - // --- FSL WISHBONE ----------------------------------- - - wire fFACK = !(fsl_stb_o ^ fsl_ack_i); - - reg rFSLSTB, xFSLSTB; - reg rFSLWRE, xFSLWRE; - - assign fsl_stb_o = rFSLSTB; - assign fsl_wre_o = rFSLWRE; - - always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i) - //if (fSKIP | |rXCE) begin - if (fSKIP) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xFSLSTB <= 1'h0; - xFSLWRE <= 1'h0; - // End of automatics - end else begin - xFSLSTB <= (fPUT | fGET) & iwb_ack_i; - xFSLWRE <= fPUT & iwb_ack_i; - end - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rFSLSTB <= 1'h0; - rFSLWRE <= 1'h0; - // End of automatics - end else if (fFACK) begin - rFSLSTB <= #1 xFSLSTB; - rFSLWRE <= #1 xFSLWRE; - end - - // --- PIPELINE CONTROL DELAY ---------------------------- - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rMXALT <= 2'h0; - rMXALU <= 3'h0; - rMXDST <= 2'h0; - rMXSRC <= 2'h0; - rMXTGT <= 2'h0; - rRW <= 5'h0; - // End of automatics - end else if (gena) begin // if (grst) - //rPCLNK <= #1 xPCLNK; - rMXDST <= #1 xMXDST; - rRW <= #1 xRW; - rMXSRC <= #1 xMXSRC; - rMXTGT <= #1 xMXTGT; - rMXALT <= #1 xMXALT; - rMXALU <= #1 xMXALU; - end - - -endmodule // aeMB_ctrl diff --git a/opencores/aemb/rtl/verilog/aeMB_edk32.v b/opencores/aemb/rtl/verilog/aeMB_edk32.v deleted file mode 100644 index 8bf4f7cac..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_edk32.v +++ /dev/null @@ -1,289 +0,0 @@ -/* $Id: aeMB_edk32.v,v 1.14 2008/01/19 16:01:22 sybreon Exp $ -** -** AEMB EDK 3.2 Compatible Core -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aeMB_edk32 (/*AUTOARG*/ - // Outputs - iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, - fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, - // Inputs - sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i, - dwb_ack_i, sys_clk_i, sys_rst_i - ); - // Bus widths - parameter IW = 32; /// Instruction bus address width - parameter DW = 32; /// Data bus address width - - // Optional functions - parameter MUL = 0; // Multiplier - parameter BSF = 1; // Barrel Shifter - - /*AUTOOUTPUT*/ - // Beginning of automatic outputs (from unused autoinst outputs) - output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v - output [31:0] dwb_dat_o; // From regf of aeMB_regf.v - output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v - output dwb_stb_o; // From ctrl of aeMB_ctrl.v - output dwb_wre_o; // From ctrl of aeMB_ctrl.v - output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v - output [31:0] fsl_dat_o; // From regf of aeMB_regf.v - output fsl_stb_o; // From ctrl of aeMB_ctrl.v - output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v - output fsl_wre_o; // From ctrl of aeMB_ctrl.v - output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v - output iwb_stb_o; // From ibuf of aeMB_ibuf.v - // End of automatics - /*AUTOINPUT*/ - // Beginning of automatic inputs (from unused autoinst inputs) - input dwb_ack_i; // To ctrl of aeMB_ctrl.v - input [31:0] dwb_dat_i; // To regf of aeMB_regf.v - input fsl_ack_i; // To ctrl of aeMB_ctrl.v - input [31:0] fsl_dat_i; // To regf of aeMB_regf.v - input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ... - input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v - input sys_int_i; // To ibuf of aeMB_ibuf.v - // End of automatics - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [10:0] rALT; // From ibuf of aeMB_ibuf.v - wire rBRA; // From bpcu of aeMB_bpcu.v - wire rDLY; // From bpcu of aeMB_bpcu.v - wire [31:0] rDWBDI; // From regf of aeMB_regf.v - wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v - wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v - wire rMSR_BIP; // From xecu of aeMB_xecu.v - wire rMSR_IE; // From xecu of aeMB_xecu.v - wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v - wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v - wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v - wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v - wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v - wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v - wire [31:2] rPC; // From bpcu of aeMB_bpcu.v - wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v - wire [4:0] rRA; // From ibuf of aeMB_ibuf.v - wire [4:0] rRB; // From ibuf of aeMB_ibuf.v - wire [4:0] rRD; // From ibuf of aeMB_ibuf.v - wire [31:0] rREGA; // From regf of aeMB_regf.v - wire [31:0] rREGB; // From regf of aeMB_regf.v - wire [31:0] rRESULT; // From xecu of aeMB_xecu.v - wire [4:0] rRW; // From ctrl of aeMB_ctrl.v - wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v - wire rSTALL; // From ibuf of aeMB_ibuf.v - wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v - // End of automatics - - input sys_clk_i; - input sys_rst_i; - - wire grst = sys_rst_i; - wire gclk = sys_clk_i; - wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL; - wire oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i); - - // --- INSTANTIATIONS ------------------------------------- - - aeMB_ibuf - ibuf (/*AUTOINST*/ - // Outputs - .rIMM (rIMM[15:0]), - .rRA (rRA[4:0]), - .rRD (rRD[4:0]), - .rRB (rRB[4:0]), - .rALT (rALT[10:0]), - .rOPC (rOPC[5:0]), - .rSIMM (rSIMM[31:0]), - .xIREG (xIREG[31:0]), - .rSTALL (rSTALL), - .iwb_stb_o (iwb_stb_o), - // Inputs - .rBRA (rBRA), - .rMSR_IE (rMSR_IE), - .rMSR_BIP (rMSR_BIP), - .iwb_dat_i (iwb_dat_i[31:0]), - .iwb_ack_i (iwb_ack_i), - .sys_int_i (sys_int_i), - .gclk (gclk), - .grst (grst), - .gena (gena), - .oena (oena)); - - aeMB_ctrl - ctrl (/*AUTOINST*/ - // Outputs - .rMXDST (rMXDST[1:0]), - .rMXSRC (rMXSRC[1:0]), - .rMXTGT (rMXTGT[1:0]), - .rMXALT (rMXALT[1:0]), - .rMXALU (rMXALU[2:0]), - .rRW (rRW[4:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_wre_o (dwb_wre_o), - .fsl_stb_o (fsl_stb_o), - .fsl_wre_o (fsl_wre_o), - // Inputs - .rDLY (rDLY), - .rIMM (rIMM[15:0]), - .rALT (rALT[10:0]), - .rOPC (rOPC[5:0]), - .rRD (rRD[4:0]), - .rRA (rRA[4:0]), - .rRB (rRB[4:0]), - .rPC (rPC[31:2]), - .rBRA (rBRA), - .rMSR_IE (rMSR_IE), - .xIREG (xIREG[31:0]), - .dwb_ack_i (dwb_ack_i), - .iwb_ack_i (iwb_ack_i), - .fsl_ack_i (fsl_ack_i), - .gclk (gclk), - .grst (grst), - .gena (gena)); - - aeMB_bpcu #(IW) - bpcu (/*AUTOINST*/ - // Outputs - .iwb_adr_o (iwb_adr_o[IW-1:2]), - .rPC (rPC[31:2]), - .rPCLNK (rPCLNK[31:2]), - .rBRA (rBRA), - .rDLY (rDLY), - // Inputs - .rMXALT (rMXALT[1:0]), - .rOPC (rOPC[5:0]), - .rRD (rRD[4:0]), - .rRA (rRA[4:0]), - .rRESULT (rRESULT[31:0]), - .rDWBDI (rDWBDI[31:0]), - .rREGA (rREGA[31:0]), - .gclk (gclk), - .grst (grst), - .gena (gena)); - - aeMB_regf - regf (/*AUTOINST*/ - // Outputs - .rREGA (rREGA[31:0]), - .rREGB (rREGB[31:0]), - .rDWBDI (rDWBDI[31:0]), - .dwb_dat_o (dwb_dat_o[31:0]), - .fsl_dat_o (fsl_dat_o[31:0]), - // Inputs - .rOPC (rOPC[5:0]), - .rRA (rRA[4:0]), - .rRB (rRB[4:0]), - .rRW (rRW[4:0]), - .rRD (rRD[4:0]), - .rMXDST (rMXDST[1:0]), - .rPCLNK (rPCLNK[31:2]), - .rRESULT (rRESULT[31:0]), - .rDWBSEL (rDWBSEL[3:0]), - .rBRA (rBRA), - .rDLY (rDLY), - .dwb_dat_i (dwb_dat_i[31:0]), - .fsl_dat_i (fsl_dat_i[31:0]), - .gclk (gclk), - .grst (grst), - .gena (gena)); - - aeMB_xecu #(DW, MUL, BSF) - xecu (/*AUTOINST*/ - // Outputs - .dwb_adr_o (dwb_adr_o[DW-1:2]), - .dwb_sel_o (dwb_sel_o[3:0]), - .fsl_adr_o (fsl_adr_o[6:2]), - .fsl_tag_o (fsl_tag_o[1:0]), - .rRESULT (rRESULT[31:0]), - .rDWBSEL (rDWBSEL[3:0]), - .rMSR_IE (rMSR_IE), - .rMSR_BIP (rMSR_BIP), - // Inputs - .rREGA (rREGA[31:0]), - .rREGB (rREGB[31:0]), - .rMXSRC (rMXSRC[1:0]), - .rMXTGT (rMXTGT[1:0]), - .rRA (rRA[4:0]), - .rRB (rRB[4:0]), - .rMXALU (rMXALU[2:0]), - .rBRA (rBRA), - .rDLY (rDLY), - .rALT (rALT[10:0]), - .rSTALL (rSTALL), - .rSIMM (rSIMM[31:0]), - .rIMM (rIMM[15:0]), - .rOPC (rOPC[5:0]), - .rRD (rRD[4:0]), - .rDWBDI (rDWBDI[31:0]), - .rPC (rPC[31:2]), - .gclk (gclk), - .grst (grst), - .gena (gena)); - - -endmodule // aeMB_edk32 - -/* - $Log: aeMB_edk32.v,v $ - Revision 1.14 2008/01/19 16:01:22 sybreon - Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) - - Revision 1.13 2007/12/25 22:15:09 sybreon - Stalls pipeline on MUL/BSF instructions results in minor speed improvements. - - Revision 1.12 2007/12/23 20:40:44 sybreon - Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. - - Revision 1.11 2007/11/30 17:08:29 sybreon - Moved simulation kernel into code. - - Revision 1.10 2007/11/16 21:52:03 sybreon - Added fsl_tag_o to FSL bus (tag either address or data). - - Revision 1.9 2007/11/14 23:19:24 sybreon - Fixed minor typo. - - Revision 1.8 2007/11/14 22:14:34 sybreon - Changed interrupt handling system (reported by M. Ettus). - - Revision 1.7 2007/11/10 16:39:38 sybreon - Upgraded license to LGPLv3. - Significant performance optimisations. - - Revision 1.6 2007/11/09 20:51:52 sybreon - Added GET/PUT support through a FSL bus. - - Revision 1.5 2007/11/08 17:48:14 sybreon - Fixed data WISHBONE arbitration problem (reported by J Lee). - - Revision 1.4 2007/11/08 14:17:47 sybreon - Parameterised optional components. - - Revision 1.3 2007/11/03 08:34:55 sybreon - Minor code cleanup. - - Revision 1.2 2007/11/02 19:20:58 sybreon - Added better (beta) interrupt support. - Changed MSR_IE to disabled at reset as per MB docs. - - Revision 1.1 2007/11/02 03:25:40 sybreon - New EDK 3.2 compatible design with optional barrel-shifter and multiplier. - Fixed various minor data hazard bugs. - Code compatible with -O0/1/2/3/s generated code. -*/ \ No newline at end of file diff --git a/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/opencores/aemb/rtl/verilog/aeMB_ibuf.v deleted file mode 100644 index a4edf1d90..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_ibuf.v +++ /dev/null @@ -1,192 +0,0 @@ -/* $Id: aeMB_ibuf.v,v 1.10 2008/01/21 01:02:26 sybreon Exp $ -** -** AEMB INSTRUCTION BUFFER -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aeMB_ibuf (/*AUTOARG*/ - // Outputs - rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o, - // Inputs - rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk, - grst, gena, oena - ); - // INTERNAL - output [15:0] rIMM; - output [4:0] rRA, rRD, rRB; - output [10:0] rALT; - output [5:0] rOPC; - output [31:0] rSIMM; - output [31:0] xIREG; - output rSTALL; - - input rBRA; - //input [1:0] rXCE; - input rMSR_IE; - input rMSR_BIP; - - // INST WISHBONE - output iwb_stb_o; - input [31:0] iwb_dat_i; - input iwb_ack_i; - - // SYSTEM - input sys_int_i; - - // SYSTEM - input gclk, grst, gena, oena; - - reg [15:0] rIMM; - reg [4:0] rRA, rRD; - reg [5:0] rOPC; - - // FIXME: Endian - wire [31:0] wIDAT = iwb_dat_i; - assign {rRB, rALT} = rIMM; - - // TODO: Assign to FIFO not full. - assign iwb_stb_o = 1'b1; - - reg [31:0] rSIMM, xSIMM; - reg rSTALL; - - wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08 - wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10 - wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18 - wire [31:0] wBRAOP = 32'h88000000; // NOP for branches - - wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT}; - reg [31:0] xIREG; - - - // --- INTERRUPT LATCH -------------------------------------- - // Debounce and latch onto the positive level. This is independent - // of the pipeline so that stalls do not affect it. - - reg rFINT; - reg [1:0] rDINT; - wire wSHOT = rDINT[0]; - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rDINT <= 2'h0; - rFINT <= 1'h0; - // End of automatics - end else begin - if (rMSR_IE) - rDINT <= #1 - {rDINT[0], sys_int_i}; - - rFINT <= #1 - //(wIREG == wINTOP) ? 1'b0 : - (rFINT | wSHOT) & rMSR_IE; - end - - wire fIMM = (rOPC == 6'o54); - wire fRTD = (rOPC == 6'o55); - wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)); - wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57)); - - // --- DELAY SLOT ------------------------------------------- - - always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT - or wBRAOP or wIDAT or wINTOP) begin - xIREG <= (rBRA) ? wBRAOP : - (!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP : - wIDAT; - end - - always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin - xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} : - {rIMM, wIDAT[15:0]}; - end - - // --- PIPELINE -------------------------------------------- - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rIMM <= 16'h0; - rOPC <= 6'h0; - rRA <= 5'h0; - rRD <= 5'h0; - rSIMM <= 32'h0; - // End of automatics - end else if (gena) begin - {rOPC, rRD, rRA, rIMM} <= #1 xIREG; - rSIMM <= #1 xSIMM; - end - - // --- STALL FOR MUL/BSF ----------------------------------- - - wire [5:0] wOPC = xIREG[31:26]; - - wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30); - wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31); - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rSTALL <= 1'h0; - // End of automatics - end else begin - rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL); - end - -endmodule // aeMB_ibuf - -/* - $Log: aeMB_ibuf.v,v $ - Revision 1.10 2008/01/21 01:02:26 sybreon - Patch interrupt bug. - - Revision 1.9 2008/01/19 16:01:22 sybreon - Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) - - Revision 1.8 2007/12/25 22:15:09 sybreon - Stalls pipeline on MUL/BSF instructions results in minor speed improvements. - - Revision 1.7 2007/11/22 15:11:15 sybreon - Change interrupt to positive level triggered interrupts. - - Revision 1.6 2007/11/14 23:39:51 sybreon - Fixed interrupt signal synchronisation. - - Revision 1.5 2007/11/14 22:14:34 sybreon - Changed interrupt handling system (reported by M. Ettus). - - Revision 1.4 2007/11/10 16:39:38 sybreon - Upgraded license to LGPLv3. - Significant performance optimisations. - - Revision 1.3 2007/11/03 08:34:55 sybreon - Minor code cleanup. - - Revision 1.2 2007/11/02 19:20:58 sybreon - Added better (beta) interrupt support. - Changed MSR_IE to disabled at reset as per MB docs. - - Revision 1.1 2007/11/02 03:25:40 sybreon - New EDK 3.2 compatible design with optional barrel-shifter and multiplier. - Fixed various minor data hazard bugs. - Code compatible with -O0/1/2/3/s generated code. -*/ diff --git a/opencores/aemb/rtl/verilog/aeMB_regf.v b/opencores/aemb/rtl/verilog/aeMB_regf.v deleted file mode 100644 index 9ac45299b..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_regf.v +++ /dev/null @@ -1,241 +0,0 @@ -// $Id: aeMB_regf.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $ -// -// AEMB REGISTER FILE -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see . -// -// $Log: aeMB_regf.v,v $ -// Revision 1.3 2007/11/10 16:39:38 sybreon -// Upgraded license to LGPLv3. -// Significant performance optimisations. -// -// Revision 1.2 2007/11/09 20:51:52 sybreon -// Added GET/PUT support through a FSL bus. -// -// Revision 1.1 2007/11/02 03:25:41 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// - -module aeMB_regf (/*AUTOARG*/ - // Outputs - rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o, - // Inputs - rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA, - rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena - ); - // INTERNAL - output [31:0] rREGA, rREGB; - output [31:0] rDWBDI; - input [5:0] rOPC; - input [4:0] rRA, rRB, rRW, rRD; - input [1:0] rMXDST; - input [31:2] rPCLNK; - input [31:0] rRESULT; - input [3:0] rDWBSEL; - input rBRA, rDLY; - - // DATA WISHBONE - output [31:0] dwb_dat_o; - input [31:0] dwb_dat_i; - - // FSL WISHBONE - output [31:0] fsl_dat_o; - input [31:0] fsl_dat_i; - - // SYSTEM - input gclk, grst, gena; - - // --- LOAD SIZER ---------------------------------------------- - // Moves the data bytes around depending on the size of the - // operation. - - wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian - wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian - - reg [31:0] rDWBDI; - reg [1:0] rSIZ; - - always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin - /* 51.2 - case (rSIZ) - // FSL - 2'o3: rDWBDI <= wFSLDI; - // 32'bit - 2'o2: rDWBDI <= wDWBDI; - // 16'bit - 2'o1: case (rRESULT[1]) - 1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]}; - 1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]}; - endcase // case (rRESULT[1]) - // 8'bit - 2'o0: case (rRESULT[1:0]) - 2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]}; - 2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]}; - 2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]}; - 2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]}; - endcase // case (rRESULT[1:0]) - endcase // case (rSIZ) - */ - - /* 50.6 - case ({rSIZ, rRESULT[1:0]}) - // FSL - 4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI; - // 32'bit - 4'h8: rDWBDI <= wDWBDI; - // 16'bit - 4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]}; - 4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]}; - // 8'bit - 4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]}; - 4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]}; - 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]}; - 4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]}; - default: rDWBDI <= 32'hX; - endcase // case (rSIZ) - */ - - // 52.0 - case (rDWBSEL) - // 8'bit - 4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]}; - 4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]}; - 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]}; - 4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]}; - // 16'bit - 4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]}; - 4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]}; - // 32'bit - 4'hF: rDWBDI <= wDWBDI; - // FSL - 4'h0: rDWBDI <= wFSLDI; - // Undefined - default: rDWBDI <= 32'hX; - endcase - - end - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rSIZ <= 2'h0; - // End of automatics - end else if (gena) begin - rSIZ <= rOPC[1:0]; - end - - // --- GENERAL PURPOSE REGISTERS (R0-R31) ----------------------- - // LUT RAM implementation is smaller and faster. R0 gets written - // during reset with 0x00 and doesn't change after. - - reg [31:0] mARAM[0:31], - mBRAM[0:31], - mDRAM[0:31]; - - wire [31:0] rREGW = mDRAM[rRW]; - wire [31:0] rREGD = mDRAM[rRD]; - assign rREGA = mARAM[rRA]; - assign rREGB = mBRAM[rRB]; - - wire fRDWE = |rRW; - - reg [31:0] xWDAT; - - always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW - or rRESULT) - case (rMXDST) - 2'o2: xWDAT <= rDWBDI; - 2'o1: xWDAT <= {rPCLNK, 2'o0}; - 2'o0: xWDAT <= rRESULT; - 2'o3: xWDAT <= rREGW; // No change - endcase // case (rMXDST) - - always @(posedge gclk) - if (grst | fRDWE) begin - mARAM[rRW] <= xWDAT; - mBRAM[rRW] <= xWDAT; - mDRAM[rRW] <= xWDAT; - end - - // --- STORE SIZER --------------------------------------------- - // Replicates the data bytes across depending on the size of the - // operation. - - reg [31:0] rDWBDO, xDWBDO; - - wire [31:0] xFSL; - wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE; - wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE; - - assign fsl_dat_o = rDWBDO; - assign xFSL = (fFFWD_M) ? rDWBDI : - (fFFWD_R) ? rRESULT : - rREGA; - - wire [31:0] xDST; - wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE; - wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE; - - assign dwb_dat_o = rDWBDO; - assign xDST = (fDFWD_M) ? rDWBDI : - (fDFWD_R) ? rRESULT : - rREGD; - - always @(/*AUTOSENSE*/rOPC or xDST or xFSL) - case (rOPC[1:0]) - // 8'bit - 2'h0: xDWBDO <= {(4){xDST[7:0]}}; - // 16'bit - 2'h1: xDWBDO <= {(2){xDST[15:0]}}; - // 32'bit - 2'h2: xDWBDO <= xDST; - // FSL - 2'h3: xDWBDO <= xFSL; - //default: xDWBDO <= 32'hX; - endcase // case (rOPC[1:0]) - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rDWBDO <= 32'h0; - // End of automatics - end else if (gena) begin - rDWBDO <= #1 xDWBDO; - end - - // --- SIMULATION ONLY ------------------------------------------ - // Randomise memory to simulate real-world memory - // synopsys translate_off - - integer i; - initial begin - for (i=0; i<32; i=i+1) begin - mARAM[i] <= $random; - mBRAM[i] <= $random; - mDRAM[i] <= $random; - end - end - - // synopsys translate_on - - -endmodule // aeMB_regf diff --git a/opencores/aemb/rtl/verilog/aeMB_sim.v b/opencores/aemb/rtl/verilog/aeMB_sim.v deleted file mode 100644 index 83248e4ba..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_sim.v +++ /dev/null @@ -1,312 +0,0 @@ -/* $Id: aeMB_sim.v,v 1.2 2008/06/06 09:36:02 sybreon Exp $ -** -** AEMB EDK 3.2 Compatible Core -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aeMB_sim (/*AUTOARG*/ - // Outputs - iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, - fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, - // Inputs - sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, - fsl_ack_i, dwb_dat_i, dwb_ack_i - ); - // Bus widths - parameter IW = 32; /// Instruction bus address width - parameter DW = 32; /// Data bus address width - - // Optional functions - parameter MUL = 1; // Multiplier - parameter BSF = 1; // Barrel Shifter - - /*AUTOOUTPUT*/ - // Beginning of automatic outputs (from unused autoinst outputs) - output [DW-1:2] dwb_adr_o; // From cpu of aeMB_edk32.v - output [31:0] dwb_dat_o; // From cpu of aeMB_edk32.v - output [3:0] dwb_sel_o; // From cpu of aeMB_edk32.v - output dwb_stb_o; // From cpu of aeMB_edk32.v - output dwb_wre_o; // From cpu of aeMB_edk32.v - output [6:2] fsl_adr_o; // From cpu of aeMB_edk32.v - output [31:0] fsl_dat_o; // From cpu of aeMB_edk32.v - output fsl_stb_o; // From cpu of aeMB_edk32.v - output [1:0] fsl_tag_o; // From cpu of aeMB_edk32.v - output fsl_wre_o; // From cpu of aeMB_edk32.v - output [IW-1:2] iwb_adr_o; // From cpu of aeMB_edk32.v - output iwb_stb_o; // From cpu of aeMB_edk32.v - // End of automatics - /*AUTOINPUT*/ - // Beginning of automatic inputs (from unused autoinst inputs) - input dwb_ack_i; // To cpu of aeMB_edk32.v - input [31:0] dwb_dat_i; // To cpu of aeMB_edk32.v - input fsl_ack_i; // To cpu of aeMB_edk32.v - input [31:0] fsl_dat_i; // To cpu of aeMB_edk32.v - input iwb_ack_i; // To cpu of aeMB_edk32.v - input [31:0] iwb_dat_i; // To cpu of aeMB_edk32.v - input sys_clk_i; // To cpu of aeMB_edk32.v - input sys_int_i; // To cpu of aeMB_edk32.v - input sys_rst_i; // To cpu of aeMB_edk32.v - // End of automatics - /*AUTOWIRE*/ - - aeMB_edk32 - #(/*AUTOINSTPARAM*/ - // Parameters - .IW (IW), - .DW (DW), - .MUL (MUL), - .BSF (BSF)) - cpu - (/*AUTOINST*/ - // Outputs - .dwb_adr_o (dwb_adr_o[DW-1:2]), - .dwb_dat_o (dwb_dat_o[31:0]), - .dwb_sel_o (dwb_sel_o[3:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_wre_o (dwb_wre_o), - .fsl_adr_o (fsl_adr_o[6:2]), - .fsl_dat_o (fsl_dat_o[31:0]), - .fsl_stb_o (fsl_stb_o), - .fsl_tag_o (fsl_tag_o[1:0]), - .fsl_wre_o (fsl_wre_o), - .iwb_adr_o (iwb_adr_o[IW-1:2]), - .iwb_stb_o (iwb_stb_o), - // Inputs - .dwb_ack_i (dwb_ack_i), - .dwb_dat_i (dwb_dat_i[31:0]), - .fsl_ack_i (fsl_ack_i), - .fsl_dat_i (fsl_dat_i[31:0]), - .iwb_ack_i (iwb_ack_i), - .iwb_dat_i (iwb_dat_i[31:0]), - .sys_int_i (sys_int_i), - .sys_clk_i (sys_clk_i), - .sys_rst_i (sys_rst_i)); - - // --- SIMULATION KERNEL ---------------------------------- - // synopsys translate_off - - wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0}; - wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0}; - wire [1:0] wBRA = {cpu.rBRA, cpu.rDLY}; - wire [3:0] wMSR = {cpu.xecu.rMSR_BIP, cpu.xecu.rMSR_C, cpu.xecu.rMSR_IE, cpu.xecu.rMSR_BE}; - - - `ifdef AEMB_SIM_KERNEL - always @(posedge cpu.gclk) begin - if (cpu.gena) begin - - $write ("\n", ($stime/10)); - $writeh (" PC=", iwb_adr ); - $writeh ("\t"); - - case (wBRA) - 2'b00: $write(" "); - 2'b01: $write("."); - 2'b10: $write("-"); - 2'b11: $write("+"); - endcase // case (cpu.wBRA) - - case (cpu.rOPC) - 6'o00: if (cpu.rRD == 0) $write(" "); else $write("ADD"); - 6'o01: $write("RSUB"); - 6'o02: $write("ADDC"); - 6'o03: $write("RSUBC"); - 6'o04: $write("ADDK"); - 6'o05: case (cpu.rIMM[1:0]) - 2'o0: $write("RSUBK"); - 2'o1: $write("CMP"); - 2'o3: $write("CMPU"); - default: $write("XXX"); - endcase // case (cpu.rIMM[1:0]) - 6'o06: $write("ADDKC"); - 6'o07: $write("RSUBKC"); - - 6'o10: $write("ADDI"); - 6'o11: $write("RSUBI"); - 6'o12: $write("ADDIC"); - 6'o13: $write("RSUBIC"); - 6'o14: $write("ADDIK"); - 6'o15: $write("RSUBIK"); - 6'o16: $write("ADDIKC"); - 6'o17: $write("RSUBIKC"); - - 6'o20: $write("MUL"); - 6'o21: case (cpu.rALT[10:9]) - 2'o0: $write("BSRL"); - 2'o1: $write("BSRA"); - 2'o2: $write("BSLL"); - default: $write("XXX"); - endcase // case (cpu.rALT[10:9]) - 6'o22: $write("IDIV"); - - 6'o30: $write("MULI"); - 6'o31: case (cpu.rALT[10:9]) - 2'o0: $write("BSRLI"); - 2'o1: $write("BSRAI"); - 2'o2: $write("BSLLI"); - default: $write("XXX"); - endcase // case (cpu.rALT[10:9]) - 6'o33: case (cpu.rRB[4:2]) - 3'o0: $write("GET"); - 3'o4: $write("PUT"); - 3'o2: $write("NGET"); - 3'o6: $write("NPUT"); - 3'o1: $write("CGET"); - 3'o5: $write("CPUT"); - 3'o3: $write("NCGET"); - 3'o7: $write("NCPUT"); - endcase // case (cpu.rRB[4:2]) - - 6'o40: $write("OR"); - 6'o41: $write("AND"); - 6'o42: if (cpu.rRD == 0) $write(" "); else $write("XOR"); - 6'o43: $write("ANDN"); - 6'o44: case (cpu.rIMM[6:5]) - 2'o0: $write("SRA"); - 2'o1: $write("SRC"); - 2'o2: $write("SRL"); - 2'o3: if (cpu.rIMM[0]) $write("SEXT16"); else $write("SEXT8"); - endcase // case (cpu.rIMM[6:5]) - - 6'o45: $write("MOV"); - 6'o46: case (cpu.rRA[3:2]) - 3'o0: $write("BR"); - 3'o1: $write("BRL"); - 3'o2: $write("BRA"); - 3'o3: $write("BRAL"); - endcase // case (cpu.rRA[3:2]) - - 6'o47: case (cpu.rRD[2:0]) - 3'o0: $write("BEQ"); - 3'o1: $write("BNE"); - 3'o2: $write("BLT"); - 3'o3: $write("BLE"); - 3'o4: $write("BGT"); - 3'o5: $write("BGE"); - default: $write("XXX"); - endcase // case (cpu.rRD[2:0]) - - 6'o50: $write("ORI"); - 6'o51: $write("ANDI"); - 6'o52: $write("XORI"); - 6'o53: $write("ANDNI"); - 6'o54: $write("IMMI"); - 6'o55: case (cpu.rRD[1:0]) - 2'o0: $write("RTSD"); - 2'o1: $write("RTID"); - 2'o2: $write("RTBD"); - default: $write("XXX"); - endcase // case (cpu.rRD[1:0]) - 6'o56: case (cpu.rRA[3:2]) - 3'o0: $write("BRI"); - 3'o1: $write("BRLI"); - 3'o2: $write("BRAI"); - 3'o3: $write("BRALI"); - endcase // case (cpu.rRA[3:2]) - 6'o57: case (cpu.rRD[2:0]) - 3'o0: $write("BEQI"); - 3'o1: $write("BNEI"); - 3'o2: $write("BLTI"); - 3'o3: $write("BLEI"); - 3'o4: $write("BGTI"); - 3'o5: $write("BGEI"); - default: $write("XXX"); - endcase // case (cpu.rRD[2:0]) - - 6'o60: $write("LBU"); - 6'o61: $write("LHU"); - 6'o62: $write("LW"); - 6'o64: $write("SB"); - 6'o65: $write("SH"); - 6'o66: $write("SW"); - - 6'o70: $write("LBUI"); - 6'o71: $write("LHUI"); - 6'o72: $write("LWI"); - 6'o74: $write("SBI"); - 6'o75: $write("SHI"); - 6'o76: $write("SWI"); - - default: $write("XXX"); - endcase // case (cpu.rOPC) - - case (cpu.rOPC[3]) - 1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM); - 1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," "); - endcase // case (cpu.rOPC[3]) - - - // ALU - $write("\t"); - $writeh(" A=",cpu.xecu.rOPA); - $writeh(" B=",cpu.xecu.rOPB); - - case (cpu.rMXALU) - 3'o0: $write(" ADD"); - 3'o1: $write(" LOG"); - 3'o2: $write(" SFT"); - 3'o3: $write(" MOV"); - 3'o4: $write(" MUL"); - 3'o5: $write(" BSF"); - default: $write(" XXX"); - endcase // case (cpu.rMXALU) - $writeh("=h",cpu.xecu.xRESULT); - - // WRITEBACK - $writeh("\tSR=", wMSR," "); - - if (cpu.regf.fRDWE) begin - case (cpu.rMXDST) - 2'o2: begin - if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")"); - if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")"); - end - 2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")"); - 2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")"); - endcase // case (cpu.rMXDST) - end - - // STORE - if (dwb_stb_o & dwb_wre_o) begin - $writeh("RAM(", dwb_adr ,")=", dwb_dat_o); - case (dwb_sel_o) - 4'hF: $write(":L"); - 4'h3,4'hC: $write(":W"); - 4'h1,4'h2,4'h4,4'h8: $write(":B"); - endcase // case (dwb_sel_o) - - end - - end // if (cpu.gena) - - end // always @ (posedge cpu.gclk) - `endif // `ifdef AEMB_SIM_KERNEL - - // synopsys translate_on - -endmodule // aeMB_sim - -/* - $Log: aeMB_sim.v,v $ - Revision 1.2 2008/06/06 09:36:02 sybreon - single thread design - - Revision 1.1 2007/12/23 20:40:45 sybreon - Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. - - */ \ No newline at end of file diff --git a/opencores/aemb/rtl/verilog/aeMB_xecu.v b/opencores/aemb/rtl/verilog/aeMB_xecu.v deleted file mode 100644 index 5de2ea619..000000000 --- a/opencores/aemb/rtl/verilog/aeMB_xecu.v +++ /dev/null @@ -1,412 +0,0 @@ -/* $Id: aeMB_xecu.v,v 1.12 2008/05/11 13:48:46 sybreon Exp $ -** -** AEMB MAIN EXECUTION ALU -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aeMB_xecu (/*AUTOARG*/ - // Outputs - dwb_adr_o, dwb_sel_o, fsl_adr_o, fsl_tag_o, rRESULT, rDWBSEL, - rMSR_IE, rMSR_BIP, - // Inputs - rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT, - rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena - ); - parameter DW=32; - - parameter MUL=0; - parameter BSF=0; - - // DATA WISHBONE - output [DW-1:2] dwb_adr_o; - output [3:0] dwb_sel_o; - - // FSL WISHBONE - output [6:2] fsl_adr_o; - output [1:0] fsl_tag_o; - - // INTERNAL - output [31:0] rRESULT; - output [3:0] rDWBSEL; - output rMSR_IE; - output rMSR_BIP; - input [31:0] rREGA, rREGB; - input [1:0] rMXSRC, rMXTGT; - input [4:0] rRA, rRB; - input [2:0] rMXALU; - input rBRA, rDLY; - input [10:0] rALT; - - input rSTALL; - input [31:0] rSIMM; - input [15:0] rIMM; - input [5:0] rOPC; - input [4:0] rRD; - input [31:0] rDWBDI; - input [31:2] rPC; - - // SYSTEM - input gclk, grst, gena; - - reg rMSR_C, xMSR_C; - reg rMSR_IE, xMSR_IE; - reg rMSR_BE, xMSR_BE; - reg rMSR_BIP, xMSR_BIP; - - wire fSKIP = rBRA & !rDLY; - - // --- OPERAND SELECT - - reg [31:0] rOPA, rOPB; - always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT) - case (rMXSRC) - 2'o0: rOPA <= rREGA; - 2'o1: rOPA <= rRESULT; - 2'o2: rOPA <= rDWBDI; - 2'o3: rOPA <= {rPC, 2'o0}; - endcase // case (rMXSRC) - - always @(/*AUTOSENSE*/rDWBDI or rMXTGT or rREGB or rRESULT or rSIMM) - case (rMXTGT) - 2'o0: rOPB <= rREGB; - 2'o1: rOPB <= rRESULT; - 2'o2: rOPB <= rDWBDI; - 2'o3: rOPB <= rSIMM; - endcase // case (rMXTGT) - - // --- ADD/SUB SELECTOR ---- - - reg rRES_ADDC; - reg [31:0] rRES_ADD; - - wire [31:0] wADD; - wire wADC; - - wire fCCC = !rOPC[5] & rOPC[1]; // & !rOPC[4] - wire fSUB = !rOPC[5] & rOPC[0]; // & !rOPC[4] - wire fCMP = !rOPC[3] & rIMM[1]; // unsigned only - wire wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust - - wire [31:0] wOPA = (fSUB) ? ~rOPA : rOPA; - wire wOPC = (fCCC) ? rMSR_C : fSUB; - - assign {wADC, wADD} = (rOPB + wOPA) + wOPC; // add carry - - always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin - {rRES_ADDC, rRES_ADD} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry - end - - // --- LOGIC SELECTOR -------------------------------------- - - reg [31:0] rRES_LOG; - always @(/*AUTOSENSE*/rOPA or rOPB or rOPC) - case (rOPC[1:0]) - 2'o0: rRES_LOG <= #1 rOPA | rOPB; - 2'o1: rRES_LOG <= #1 rOPA & rOPB; - 2'o2: rRES_LOG <= #1 rOPA ^ rOPB; - 2'o3: rRES_LOG <= #1 rOPA & ~rOPB; - endcase // case (rOPC[1:0]) - - // --- SHIFTER SELECTOR ------------------------------------ - - reg [31:0] rRES_SFT; - reg rRES_SFTC; - - always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA) - case (rIMM[6:5]) - 2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]}; - 2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]}; - 2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]}; - 2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} : - { {(24){rOPA[7]}}, rOPA[7:0], rMSR_C}; - endcase // case (rIMM[6:5]) - - // --- MOVE SELECTOR --------------------------------------- - - wire [31:0] wMSR = {rMSR_C, 3'o0, - 20'h0ED32, - 4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE}; - wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0]; - wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0]; - reg [31:0] rRES_MOV; - always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA - or wMSR) - rRES_MOV <= (fMFSR) ? wMSR : - (fMFPC) ? rPC : - (rRA[3]) ? rOPB : - rOPA; - - // --- MULTIPLIER ------------------------------------------ - // TODO: 2 stage multiplier - - reg [31:0] rRES_MUL, rRES_MUL0, xRES_MUL; - always @(/*AUTOSENSE*/rOPA or rOPB) begin - xRES_MUL <= (rOPA * rOPB); - end - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rRES_MUL <= 32'h0; - // End of automatics - end else if (rSTALL) begin - rRES_MUL <= #1 xRES_MUL; - end - - - // --- BARREL SHIFTER -------------------------------------- - - reg [31:0] rRES_BSF; - reg [31:0] xBSRL, xBSRA, xBSLL; - - // Infer a logical left barrel shifter. - always @(/*AUTOSENSE*/rOPA or rOPB) - xBSLL <= rOPA << rOPB[4:0]; - - // Infer a logical right barrel shifter. - always @(/*AUTOSENSE*/rOPA or rOPB) - xBSRL <= rOPA >> rOPB[4:0]; - - // Infer a arithmetic right barrel shifter. - always @(/*AUTOSENSE*/rOPA or rOPB) - case (rOPB[4:0]) - 5'd00: xBSRA <= rOPA; - 5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]}; - 5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]}; - 5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]}; - 5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]}; - 5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]}; - 5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]}; - 5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]}; - 5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]}; - 5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]}; - 5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]}; - 5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]}; - 5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]}; - 5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]}; - 5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]}; - 5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]}; - 5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]}; - 5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]}; - 5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]}; - 5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]}; - 5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]}; - 5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]}; - 5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]}; - 5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]}; - 5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]}; - 5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]}; - 5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]}; - 5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]}; - 5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]}; - 5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]}; - 5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]}; - 5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]}; - endcase // case (rOPB[4:0]) - - reg [31:0] rBSRL, rBSRA, rBSLL; - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rBSLL <= 32'h0; - rBSRA <= 32'h0; - rBSRL <= 32'h0; - // End of automatics - end else if (rSTALL) begin - rBSRL <= #1 xBSRL; - rBSRA <= #1 xBSRA; - rBSLL <= #1 xBSLL; - end - - always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL) - case (rALT[10:9]) - 2'd0: rRES_BSF <= rBSRL; - 2'd1: rRES_BSF <= rBSRA; - 2'd2: rRES_BSF <= rBSLL; - default: rRES_BSF <= 32'hX; - endcase // case (rALT[10:9]) - - - // --- MSR REGISTER ----------------- - - // C - wire fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP; - wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0); - - always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU - or rOPA or rRES_ADDC or rRES_SFTC) - //if (fSKIP | |rXCE) begin - if (fSKIP) begin - xMSR_C <= rMSR_C; - end else - case (rMXALU) - 3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; - 3'o1: xMSR_C <= rMSR_C; // LOGIC - 3'o2: xMSR_C <= rRES_SFTC; // SHIFT - 3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C; - 3'o4: xMSR_C <= rMSR_C; - 3'o5: xMSR_C <= rMSR_C; - default: xMSR_C <= 1'hX; - endcase // case (rMXALU) - - // IE/BIP/BE - wire fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP; - wire fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP; - wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC); - wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE); - - always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA) - xMSR_IE <= (fINT) ? 1'b0 : - (fRTID) ? 1'b1 : - (fMTS) ? rOPA[1] : - rMSR_IE; - - always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA) - xMSR_BIP <= (fBRK) ? 1'b1 : - (fRTBD) ? 1'b0 : - (fMTS) ? rOPA[3] : - rMSR_BIP; - - always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA) - xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE; - - // --- RESULT SELECTOR ------------------------------------------- - // Selects results from functional units. - reg [31:0] rRESULT, xRESULT; - - // RESULT - always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF - or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT) - if (fSKIP) - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xRESULT <= 32'h0; - // End of automatics - else - case (rMXALU) - 3'o0: xRESULT <= rRES_ADD; - 3'o1: xRESULT <= rRES_LOG; - 3'o2: xRESULT <= rRES_SFT; - 3'o3: xRESULT <= rRES_MOV; - 3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX; - 3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX; - default: xRESULT <= 32'hX; - endcase // case (rMXALU) - - // --- DATA WISHBONE ----- - - reg [3:0] rDWBSEL, xDWBSEL; - assign dwb_adr_o = rRESULT[DW-1:2]; - assign dwb_sel_o = rDWBSEL; - - always @(/*AUTOSENSE*/rOPC or wADD) - case (rOPC[1:0]) - 2'o0: case (wADD[1:0]) // 8'bit - 2'o0: xDWBSEL <= 4'h8; - 2'o1: xDWBSEL <= 4'h4; - 2'o2: xDWBSEL <= 4'h2; - 2'o3: xDWBSEL <= 4'h1; - endcase // case (wADD[1:0]) - 2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit - 2'o2: xDWBSEL <= 4'hF; // 32'bit - 2'o3: xDWBSEL <= 4'h0; // FSL - endcase // case (rOPC[1:0]) - - // --- FSL WISHBONE -------------------- - - reg [14:2] rFSLADR, xFSLADR; - - assign {fsl_adr_o, fsl_tag_o} = rFSLADR[8:2]; - - always @(/*AUTOSENSE*/rALT or rRB) begin - xFSLADR <= {rALT, rRB[3:2]}; - end - - // --- SYNC --- - - always @(posedge gclk) - if (grst) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - rDWBSEL <= 4'h0; - rFSLADR <= 13'h0; - rMSR_BE <= 1'h0; - rMSR_BIP <= 1'h0; - rMSR_C <= 1'h0; - rMSR_IE <= 1'h0; - rRESULT <= 32'h0; - // End of automatics - end else if (gena) begin // if (grst) - rRESULT <= #1 xRESULT; - rDWBSEL <= #1 xDWBSEL; - rMSR_C <= #1 xMSR_C; - rMSR_IE <= #1 xMSR_IE; - rMSR_BE <= #1 xMSR_BE; - rMSR_BIP <= #1 xMSR_BIP; - rFSLADR <= #1 xFSLADR; - end - -endmodule // aeMB_xecu - -/* - $Log: aeMB_xecu.v,v $ - Revision 1.12 2008/05/11 13:48:46 sybreon - Backported Adder from AEMB2_EDK62. - Fixes 64-bit math problem reported by M. Ettus. - - Revision 1.11 2008/01/19 15:57:36 sybreon - Fix MTS during interrupt vectoring bug (reported by M. Ettus). - - Revision 1.10 2007/12/25 22:15:09 sybreon - Stalls pipeline on MUL/BSF instructions results in minor speed improvements. - - Revision 1.9 2007/11/30 16:42:51 sybreon - Minor code cleanup. - - Revision 1.8 2007/11/16 21:52:03 sybreon - Added fsl_tag_o to FSL bus (tag either address or data). - - Revision 1.7 2007/11/14 22:14:34 sybreon - Changed interrupt handling system (reported by M. Ettus). - - Revision 1.6 2007/11/10 16:39:38 sybreon - Upgraded license to LGPLv3. - Significant performance optimisations. - - Revision 1.5 2007/11/09 20:51:52 sybreon - Added GET/PUT support through a FSL bus. - - Revision 1.4 2007/11/08 14:17:47 sybreon - Parameterised optional components. - - Revision 1.3 2007/11/03 08:34:55 sybreon - Minor code cleanup. - - Revision 1.2 2007/11/02 19:20:58 sybreon - Added better (beta) interrupt support. - Changed MSR_IE to disabled at reset as per MB docs. - - Revision 1.1 2007/11/02 03:25:41 sybreon - New EDK 3.2 compatible design with optional barrel-shifter and multiplier. - Fixed various minor data hazard bugs. - Code compatible with -O0/1/2/3/s generated code. - -*/ \ No newline at end of file diff --git a/opencores/aemb/sim/.gitignore b/opencores/aemb/sim/.gitignore deleted file mode 100644 index 4ef5da542..000000000 --- a/opencores/aemb/sim/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/*.bin -/*.dump -/*.vcd -/*.rom diff --git a/opencores/aemb/sim/CODE_DEBUG.sav b/opencores/aemb/sim/CODE_DEBUG.sav deleted file mode 100644 index f777173c4..000000000 --- a/opencores/aemb/sim/CODE_DEBUG.sav +++ /dev/null @@ -1,16 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-5.188574 2727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -testbench.dut.dwb_we_o -@22 -testbench.dut.dwb_sel_o[3:0] -testbench.dut.dwb_adr_o[15:0] -@28 -testbench.dut.sys_clk_i -@22 -testbench.dut.dwb_dat_o[31:0] -@821 -testbench.dut.dwb_dat_i[31:0] -@22 -testbench.dut.dwb_dat_i[31:0] diff --git a/opencores/aemb/sim/CVS/Entries b/opencores/aemb/sim/CVS/Entries deleted file mode 100644 index bf457ae67..000000000 --- a/opencores/aemb/sim/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -D/verilog//// -/cversim/1.5/Tue Jan 15 18:38:57 2008// -/iversim/1.5/Tue Jan 15 18:38:57 2008// diff --git a/opencores/aemb/sim/CVS/Repository b/opencores/aemb/sim/CVS/Repository deleted file mode 100644 index c6bd1aa80..000000000 --- a/opencores/aemb/sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/sim diff --git a/opencores/aemb/sim/CVS/Root b/opencores/aemb/sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/aemb/sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/aemb/sim/CVS/Template b/opencores/aemb/sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/aemb/sim/cversim b/opencores/aemb/sim/cversim deleted file mode 100755 index 0dbb7aea1..000000000 --- a/opencores/aemb/sim/cversim +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh -# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ -# $Log: cversim,v $ -# Revision 1.5 2007/12/11 00:44:30 sybreon -# Modified for AEMB2 -# -# Revision 1.4 2007/11/30 17:08:30 sybreon -# Moved simulation kernel into code. -# -# Revision 1.3 2007/11/05 10:59:31 sybreon -# Added random seed for simulation. -# -# Revision 1.2 2007/04/12 20:21:33 sybreon -# Moved testbench into /sim/verilog. -# Simulation cleanups. -# -# Revision 1.1 2007/03/09 17:41:55 sybreon -# initial import -# -RANDOM=$(date +%s) -echo "parameter randseed = $RANDOM;" > random.v -cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v diff --git a/opencores/aemb/sim/iversim b/opencores/aemb/sim/iversim deleted file mode 100755 index 9d2384b5a..000000000 --- a/opencores/aemb/sim/iversim +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh -# $Id: iversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ -# $Log: iversim,v $ -# Revision 1.5 2007/12/11 00:44:30 sybreon -# Modified for AEMB2 -# -# Revision 1.4 2007/11/30 17:08:30 sybreon -# Moved simulation kernel into code. -# -# Revision 1.3 2007/11/09 20:50:51 sybreon -# Added log output to iverilog.log -# -# Revision 1.2 2007/11/05 10:59:31 sybreon -# Added random seed for simulation. -# -# Revision 1.1 2007/03/09 17:41:55 sybreon -# initial import -# -RANDOM=$(date +%s) -echo "parameter randseed = $RANDOM;" > random.v -iverilog $@ -DAEMBX_SIMULATION_KERNEL ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out diff --git a/opencores/aemb/sim/verilog/CVS/Entries b/opencores/aemb/sim/verilog/CVS/Entries deleted file mode 100644 index 34e896e80..000000000 --- a/opencores/aemb/sim/verilog/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/aemb2.v/1.3/Tue Jan 15 18:38:57 2008// -/edk32.v/1.12/Tue Jan 15 18:38:57 2008// -D diff --git a/opencores/aemb/sim/verilog/CVS/Repository b/opencores/aemb/sim/verilog/CVS/Repository deleted file mode 100644 index ff3eabf2d..000000000 --- a/opencores/aemb/sim/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/sim/verilog diff --git a/opencores/aemb/sim/verilog/CVS/Root b/opencores/aemb/sim/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/aemb/sim/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/aemb/sim/verilog/CVS/Template b/opencores/aemb/sim/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/aemb/sim/verilog/aemb2.v b/opencores/aemb/sim/verilog/aemb2.v deleted file mode 100644 index bda1704e3..000000000 --- a/opencores/aemb/sim/verilog/aemb2.v +++ /dev/null @@ -1,242 +0,0 @@ -/* $Id: aemb2.v,v 1.3 2007/12/28 21:44:50 sybreon Exp $ -** -** AEMB2 TEST BENCH -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -module aemb2 (); - parameter IWB=16; - parameter DWB=16; - - parameter TXE = 0; ///< thread execution enable - - parameter MUL = 1; ///< enable hardware multiplier - parameter BSF = 1; ///< enable barrel shifter - parameter FSL = 1; ///< enable FSL bus - parameter DIV = 0; ///< enable hardware divider - -`include "random.v" - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [6:2] cwb_adr_o; // From dut of aeMB2_sim.v - wire [31:0] cwb_dat_o; // From dut of aeMB2_sim.v - wire [3:0] cwb_sel_o; // From dut of aeMB2_sim.v - wire cwb_stb_o; // From dut of aeMB2_sim.v - wire [1:0] cwb_tga_o; // From dut of aeMB2_sim.v - wire cwb_wre_o; // From dut of aeMB2_sim.v - wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_sim.v - wire dwb_cyc_o; // From dut of aeMB2_sim.v - wire [31:0] dwb_dat_o; // From dut of aeMB2_sim.v - wire [3:0] dwb_sel_o; // From dut of aeMB2_sim.v - wire dwb_stb_o; // From dut of aeMB2_sim.v - wire dwb_tga_o; // From dut of aeMB2_sim.v - wire dwb_wre_o; // From dut of aeMB2_sim.v - wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_sim.v - wire iwb_stb_o; // From dut of aeMB2_sim.v - wire iwb_tga_o; // From dut of aeMB2_sim.v - wire iwb_wre_o; // From dut of aeMB2_sim.v - // End of automatics - /*AUTOREGINPUT*/ - // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) - reg cwb_ack_i; // To dut of aeMB2_sim.v - reg dwb_ack_i; // To dut of aeMB2_sim.v - reg iwb_ack_i; // To dut of aeMB2_sim.v - reg sys_clk_i; // To dut of aeMB2_sim.v - reg sys_int_i; // To dut of aeMB2_sim.v - reg sys_rst_i; // To dut of aeMB2_sim.v - // End of automatics - - // INITIAL SETUP ////////////////////////////////////////////////////// - - //reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i; - reg svc; - integer inttime; - integer seed; - integer theend; - - always #5 sys_clk_i = ~sys_clk_i; - - initial begin - //$dumpfile("dump.vcd"); - //$dumpvars(1,dut, dut.bpcu); - end - - initial begin - seed = randseed; - theend = 0; - svc = 0; - sys_clk_i = $random(seed); - sys_rst_i = 1; - sys_int_i = 0; - #50 sys_rst_i = 0; - #3500000 $finish; - end - - // FAKE MEMORY //////////////////////////////////////////////////////// - - reg [31:0] rom [0:65535]; - reg [31:0] ram[0:65535]; - reg [31:0] dwblat; - reg [15:2] dadr, iadr; - - wire [31:0] dwb_dat_t = ram[dwb_adr_o]; - wire [31:0] iwb_dat_i = rom[iadr]; - wire [31:0] dwb_dat_i = ram[dadr]; - wire [31:0] cwb_dat_i = cwb_adr_o; - -`ifdef POSEDGE -`else // !`ifdef POSEDGE - - always @(negedge sys_clk_i) - if (sys_rst_i) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - cwb_ack_i <= 1'h0; - dwb_ack_i <= 1'h0; - iwb_ack_i <= 1'h0; - // End of automatics - end else begin - iwb_ack_i <= #1 iwb_stb_o; - dwb_ack_i <= #1 dwb_stb_o; - cwb_ack_i <= #1 cwb_stb_o; - end // else: !if(sys_rst_i) - - always @(negedge sys_clk_i) begin - iadr <= #1 iwb_adr_o; - dadr <= #1 dwb_adr_o; - - if (dwb_wre_o & dwb_stb_o) begin - case (dwb_sel_o) - 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; - 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; - 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; - 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; - 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; - 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; - 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; - endcase // case (dwb_sel_o) - end // if (dwb_we_o & dwb_stb_o) - end // always @ (negedge sys_clk_i) - -`endif // !`ifdef POSEDGE - - - integer i; - initial begin - for (i=0;i<65535;i=i+1) begin - ram[i] <= $random; - end - #1 $readmemh("dump.vmem",rom); - #1 $readmemh("dump.vmem",ram); - end - - // DISPLAY OUTPUTS /////////////////////////////////////////////////// - - integer rnd; - - always @(posedge sys_clk_i) begin - - // Interrupt Monitors - if (!dut.sim.rMSR_IE) begin - rnd = $random % 30; - inttime = $stime + 1000 + (rnd*rnd * 10); - end - if ($stime > inttime) begin - sys_int_i = 1; - svc = 0; - end - if (($stime > inttime + 500) && !svc) begin - $display("\n\t*** INTERRUPT TIMEOUT ***", inttime); - $finish; - end - if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; - /* - if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin - svc = 1; - //$display("\nLATENCY: ", ($stime - inttime)/10); - end - */ - - // Pass/Fail Monitors - if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin - $display("\n\tFAIL"); - $finish; - end - - if (iwb_dat_i == 32'hb8000000) begin - theend = theend + 1; - end - - if (theend == 5) begin - $display("\n\t*** PASSED ALL TESTS ***"); - $finish; - end - - end // always @ (posedge sys_clk_i) - - // INTERNAL WIRING //////////////////////////////////////////////////// - - aeMB2_sim - #(/*AUTOINSTPARAM*/ - // Parameters - .IWB (IWB), - .DWB (DWB), - .TXE (TXE), - .MUL (MUL), - .BSF (BSF), - .FSL (FSL), - .DIV (DIV)) - dut (/*AUTOINST*/ - // Outputs - .cwb_adr_o (cwb_adr_o[6:2]), - .cwb_dat_o (cwb_dat_o[31:0]), - .cwb_sel_o (cwb_sel_o[3:0]), - .cwb_stb_o (cwb_stb_o), - .cwb_tga_o (cwb_tga_o[1:0]), - .cwb_wre_o (cwb_wre_o), - .dwb_adr_o (dwb_adr_o[DWB-1:2]), - .dwb_cyc_o (dwb_cyc_o), - .dwb_dat_o (dwb_dat_o[31:0]), - .dwb_sel_o (dwb_sel_o[3:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_tga_o (dwb_tga_o), - .dwb_wre_o (dwb_wre_o), - .iwb_adr_o (iwb_adr_o[IWB-1:2]), - .iwb_stb_o (iwb_stb_o), - .iwb_tga_o (iwb_tga_o), - .iwb_wre_o (iwb_wre_o), - // Inputs - .cwb_ack_i (cwb_ack_i), - .cwb_dat_i (cwb_dat_i[31:0]), - .dwb_ack_i (dwb_ack_i), - .dwb_dat_i (dwb_dat_i[31:0]), - .iwb_ack_i (iwb_ack_i), - .iwb_dat_i (iwb_dat_i[31:0]), - .sys_clk_i (sys_clk_i), - .sys_int_i (sys_int_i), - .sys_rst_i (sys_rst_i)); - -endmodule // edk32 - -/* $Log $ */ - -// Local Variables: -// verilog-library-directories:("." "../../rtl/verilog/") -// verilog-library-files:("") -// End: diff --git a/opencores/aemb/sim/verilog/edk32.v b/opencores/aemb/sim/verilog/edk32.v deleted file mode 100644 index 68465e9e0..000000000 --- a/opencores/aemb/sim/verilog/edk32.v +++ /dev/null @@ -1,288 +0,0 @@ -/* $Id: edk32.v,v 1.12 2007/12/23 20:40:51 sybreon Exp $ -** -** AEMB EDK 3.2 Compatible Core TEST -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -`define AEMB_SIMULATION_KERNEL - -module edk32 (); - -`include "random.v" - - // INITIAL SETUP ////////////////////////////////////////////////////// - - reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i; - reg svc; - integer inttime; - integer seed; - integer theend; - - always #5 sys_clk_i = ~sys_clk_i; - - initial begin - //$dumpfile("dump.vcd"); - //$dumpvars(1,dut); - end - - initial begin - seed = randseed; - theend = 0; - svc = 0; - sys_clk_i = $random(seed); - sys_rst_i = 1; - sys_int_i = 0; - sys_exc_i = 0; - #50 sys_rst_i = 0; - end - - initial fork - //inttime $display("FSADFASDFSDAF"); - //#10000 sys_int_i = 1; - //#1100 sys_int_i = 0; - //#100000 $displayh("\nTest Completed."); - //#4000 $finish; - join - - - // FAKE MEMORY //////////////////////////////////////////////////////// - - wire fsl_stb_o; - wire fsl_wre_o; - wire [31:0] fsl_dat_o; - wire [31:0] fsl_dat_i; - wire [6:2] fsl_adr_o; - - wire [15:2] iwb_adr_o; - wire iwb_stb_o; - wire dwb_stb_o; - reg [31:0] rom [0:65535]; - wire [31:0] iwb_dat_i; - reg iwb_ack_i, dwb_ack_i, fsl_ack_i; - - reg [31:0] ram[0:65535]; - wire [31:0] dwb_dat_i; - reg [31:0] dwblat; - wire dwb_we_o; - reg [15:2] dadr,iadr; - wire [3:0] dwb_sel_o; - wire [31:0] dwb_dat_o; - wire [15:2] dwb_adr_o; - wire [31:0] dwb_dat_t; - - initial begin - dwb_ack_i = 0; - iwb_ack_i = 0; - fsl_ack_i = 0; - end - - assign dwb_dat_t = ram[dwb_adr_o]; - assign iwb_dat_i = ram[iadr]; - assign dwb_dat_i = ram[dadr]; - assign fsl_dat_i = fsl_adr_o; - -`ifdef POSEDGE - - always @(posedge sys_clk_i) - if (sys_rst_i) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - dwb_ack_i <= 1'h0; - fsl_ack_i <= 1'h0; - iwb_ack_i <= 1'h0; - // End of automatics - end else begin - iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i; - dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i; - fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i; - end // else: !if(sys_rst_i) - - always @(posedge sys_clk_i) begin - iadr <= #1 iwb_adr_o; - dadr <= #1 dwb_adr_o; - - if (dwb_we_o & dwb_stb_o) begin - case (dwb_sel_o) - 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; - 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; - 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; - 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; - 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; - 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; - 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; - endcase // case (dwb_sel_o) - end // if (dwb_we_o & dwb_stb_o) - end // always @ (posedge sys_clk_i) - -`else // !`ifdef POSEDGE - - always @(negedge sys_clk_i) - if (sys_rst_i) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - dwb_ack_i <= 1'h0; - fsl_ack_i <= 1'h0; - iwb_ack_i <= 1'h0; - // End of automatics - end else begin - iwb_ack_i <= #1 iwb_stb_o; - dwb_ack_i <= #1 dwb_stb_o; - fsl_ack_i <= #1 fsl_stb_o; - end // else: !if(sys_rst_i) - - always @(negedge sys_clk_i) begin - iadr <= #1 iwb_adr_o; - dadr <= #1 dwb_adr_o; - - if (dwb_we_o & dwb_stb_o) begin - case (dwb_sel_o) - 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; - 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; - 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; - 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; - 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; - 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; - 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; - endcase // case (dwb_sel_o) - end // if (dwb_we_o & dwb_stb_o) - end // always @ (negedge sys_clk_i) - -`endif // !`ifdef POSEDGE - - - integer i; - initial begin - for (i=0;i<65535;i=i+1) begin - ram[i] <= $random; - end - #1 $readmemh("dump.vmem",ram); - end - - // DISPLAY OUTPUTS /////////////////////////////////////////////////// - - integer rnd; - - always @(posedge sys_clk_i) begin - - // Interrupt Monitors - if (!dut.cpu.rMSR_IE) begin - rnd = $random % 30; - inttime = $stime + 1000 + (rnd*rnd * 10); - end - if ($stime > inttime) begin - sys_int_i = 1; - svc = 0; - end - if (($stime > inttime + 500) && !svc) begin - $display("\n\t*** INTERRUPT TIMEOUT ***", inttime); - $finish; - end - if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; - if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin - svc = 1; - //$display("\nLATENCY: ", ($stime - inttime)/10); - end - - // Pass/Fail Monitors - if (dwb_we_o & (dwb_dat_o == "FAIL")) begin - $display("\n\tFAIL"); - $finish; - end - - if (iwb_dat_i == 32'hb8000000) begin - theend = theend + 1; - end - - if (theend == 5) begin - $display("\n\t*** PASSED ALL TESTS ***"); - $finish; - end - end // always @ (posedge sys_clk_i) - - // INTERNAL WIRING //////////////////////////////////////////////////// - - aeMB_sim #(16,16) - dut ( - .sys_int_i(sys_int_i), - .dwb_ack_i(dwb_ack_i), - .dwb_stb_o(dwb_stb_o), - .dwb_adr_o(dwb_adr_o), - .dwb_dat_o(dwb_dat_o), - .dwb_dat_i(dwb_dat_i), - .dwb_wre_o(dwb_we_o), - .dwb_sel_o(dwb_sel_o), - - .fsl_ack_i(fsl_ack_i), - .fsl_stb_o(fsl_stb_o), - .fsl_adr_o(fsl_adr_o), - .fsl_dat_o(fsl_dat_o), - .fsl_dat_i(fsl_dat_i), - .fsl_wre_o(fsl_we_o), - - .iwb_adr_o(iwb_adr_o), - .iwb_dat_i(iwb_dat_i), - .iwb_stb_o(iwb_stb_o), - .iwb_ack_i(iwb_ack_i), - .sys_clk_i(sys_clk_i), - .sys_rst_i(sys_rst_i) - ); - -endmodule // edk32 - -/* - $Log: edk32.v,v $ - Revision 1.12 2007/12/23 20:40:51 sybreon - Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. - - Revision 1.11 2007/12/11 00:44:31 sybreon - Modified for AEMB2 - - Revision 1.10 2007/11/30 17:08:30 sybreon - Moved simulation kernel into code. - - Revision 1.9 2007/11/20 18:36:00 sybreon - Removed unnecessary byte acrobatics with VMEM data. - - Revision 1.8 2007/11/18 19:41:45 sybreon - Minor simulation fixes. - - Revision 1.7 2007/11/14 22:11:41 sybreon - Added posedge/negedge bus interface. - Modified interrupt test system. - - Revision 1.6 2007/11/13 23:37:28 sybreon - Updated simulation to also check BRI 0x00 instruction. - - Revision 1.5 2007/11/09 20:51:53 sybreon - Added GET/PUT support through a FSL bus. - - Revision 1.4 2007/11/08 14:18:00 sybreon - Parameterised optional components. - - Revision 1.3 2007/11/05 10:59:31 sybreon - Added random seed for simulation. - - Revision 1.2 2007/11/02 19:16:10 sybreon - Added interrupt simulation. - Changed "human readable" simulation output. - - Revision 1.1 2007/11/02 03:25:45 sybreon - New EDK 3.2 compatible design with optional barrel-shifter and multiplier. - Fixed various minor data hazard bugs. - Code compatible with -O0/1/2/3/s generated code. - */ \ No newline at end of file diff --git a/opencores/aemb/sw/CVS/Entries b/opencores/aemb/sw/CVS/Entries deleted file mode 100644 index 45725bed9..000000000 --- a/opencores/aemb/sw/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -D/c//// -/gccrom/1.13/Sun Jan 20 19:47:57 2008// diff --git a/opencores/aemb/sw/CVS/Repository b/opencores/aemb/sw/CVS/Repository deleted file mode 100644 index 6de31b8b0..000000000 --- a/opencores/aemb/sw/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/sw diff --git a/opencores/aemb/sw/CVS/Root b/opencores/aemb/sw/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/aemb/sw/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/aemb/sw/CVS/Template b/opencores/aemb/sw/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/aemb/sw/c/CVS/Entries b/opencores/aemb/sw/c/CVS/Entries deleted file mode 100644 index 4867b6318..000000000 --- a/opencores/aemb/sw/c/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/aeMB_testbench.c/1.14/Tue Jan 15 18:38:57 2008// -/libaemb.h/1.3/Tue Jan 15 18:38:57 2008// -D diff --git a/opencores/aemb/sw/c/CVS/Repository b/opencores/aemb/sw/c/CVS/Repository deleted file mode 100644 index 86c411d03..000000000 --- a/opencores/aemb/sw/c/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/sw/c diff --git a/opencores/aemb/sw/c/CVS/Root b/opencores/aemb/sw/c/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/aemb/sw/c/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/aemb/sw/c/CVS/Template b/opencores/aemb/sw/c/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/aemb/sw/c/aeMB_testbench.c b/opencores/aemb/sw/c/aeMB_testbench.c deleted file mode 100644 index c3402e0ef..000000000 --- a/opencores/aemb/sw/c/aeMB_testbench.c +++ /dev/null @@ -1,385 +0,0 @@ -/* $Id: aeMB_testbench.c,v 1.14 2007/12/28 21:44:04 sybreon Exp $ -** -** AEMB Function Verification C Testbench -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU General Public License as published by -** the Free Software Foundation, either version 3 of the License, or -** (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -** License for more details. -** -** You should have received a copy of the GNU General Public License -** along with AEMB. If not, see . -*/ - -#include -#include -#include - -#include "libaemb.h" - -/** - INTERRUPT TEST - - This tests for the following: - - Pointer addressing - - Interrupt handling - */ - -void __attribute__ ((interrupt_handler)) int_handler(); -volatile int service = 0xDEADDEAD; - -void int_service() -{ - int* pio = (int*)0xFFFFFFFC; - *pio = 0x52544E49; // "INTR" - service = 0; -} - -void int_handler() -{ - int_service(); -} - -/** - INTERRUPT TEST ROUTINE -*/ -int int_test () -{ - // Delay loop until hardware interrupt triggers - volatile int i; - for (i=0; i < 999; i++) { - if (service == 0) return 0; - }; - - return -1; -} - -/** - FIBONACCI TEST - http://en.literateprograms.org/Fibonacci_numbers_(C) - - This tests for the following: - - Recursion & Iteration - - 32/16/8-bit data handling -*/ - -unsigned int fib_slow(unsigned int n) -{ - return n < 2 ? n : fib_slow(n-1) + fib_slow(n-2); -} - -unsigned int fib_fast(unsigned int n) -{ - unsigned int a[3]; - unsigned int *p=a; - unsigned int i; - - for(i=0; i<=n; ++i) { - if(i<2) *p=i; - else { - if(p==a) *p=*(a+1)+*(a+2); - else if(p==a+1) *p=*a+*(a+2); - else *p=*a+*(a+1); - } - if(++p>a+2) p=a; - } - - return p==a?*(p+2):*(p-1); -} - -int fib_test(int max) { - unsigned int n; - unsigned int fast, slow; - // 32-bit LUT - unsigned int fib_lut32[] = { - 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 - }; - // 16-bit LUT - unsigned short fib_lut16[] = { - 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 - }; - // 8-bit LUT - unsigned char fib_lut8[] = { - 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 - }; - - for (n=0;n a) goto b_larger; - while (1) { - a = a % b; - if (a == 0) return b; - b_larger: - b = b % a; - if (b == 0) return a; - } -} - -int euclid_test(int max) -{ - int n; - int euclid; - // Random Numbers - int euclid_a[] = { - 1804289383, 1681692777, 1957747793, 719885386, 596516649, - 1025202362, 783368690, 2044897763, 1365180540, 304089172, - 35005211, 294702567, 336465782, 278722862 - }; - int euclid_b[] = { - 846930886, 1714636915, 424238335, 1649760492, 1189641421, - 1350490027, 1102520059, 1967513926, 1540383426, 1303455736, - 521595368, 1726956429, 861021530, 233665123 - }; - - // GCD - int euclid_lut[] = { - 1, 1, 1, 2, 1, 1, 1, 1, 6, 4, 1, 3, 2, 1 - }; - - for (n=0;n 0.0) - { - xn = (i+(i-1))/2.0; - break; - } - } - while (!(iters++ >= 100 - || x == xn)) - { - x = xn; - xn = x - (x * x - n) / (2 * x); - } - return xn; -} - -int newton_test (int max) { - int n; - float newt; - // 32-bit LUT - float newt_lut[] = { - 0.000000000000000000000000, - 1.000000000000000000000000, - 1.414213538169860839843750, - 1.732050776481628417968750, - 2.000000000000000000000000, - 2.236068010330200195312500, - 2.449489831924438476562500, - 2.645751237869262695312500, - 2.828427076339721679687500, - 3.000000000000000000000000, - 3.162277698516845703125000, - 3.316624879837036132812500, - 3.464101552963256835937500, - 3.605551242828369140625000, - 3.741657495498657226562500 - }; - - for (n=0;n_errno; - // return &errnum; -} -*/ - -int malloc_test() -{ - void *alloc; - - alloc = (void *)malloc(256); // allocate 32 bytes - - if (alloc == NULL) - return -1; - else - return (int) alloc; -} - -/** - MAIN TEST PROGRAMME - - This is the main test procedure. It will output signals onto the - MPI port that is checked by the testbench. - */ - -int main () -{ - // Message Passing Port - int* mpi = (int*)0xFFFFFFFF; - - // Number of each test to run - int max = 10; - - // lock T0 if it's multi-threaded - /* - if ((aemb_isthreaded() == 0) && (aemb_isthread1() != 0)) { - while (1) { - asm volatile ("nop;"); - } - } - */ - - // Enable Global Interrupts - aemb_enable_interrupt(); - - // INT TEST - //if (int_test() == -1) { *mpi = 0x4641494C; } - - // TEST MALLOC - if (malloc_test() == -1) { *mpi = 0x4641494C; } - - // FSL TEST - //if (fsl_test() == -1) { *mpi = 0x4641494C; } - - // Fibonacci Test - if (fib_test(max) == -1) { *mpi = 0x4641494C; } - - // Euclid Test - if (euclid_test(max) == -1) { *mpi = 0x4641494C; } - - // Newton-Rhapson Test - if (newton_test(max) == -1) { *mpi = 0x4641494C; } - - // Disable Global Interrupts - aemb_disable_interrupt(); - - // ALL PASSED - return 0; -} - -/* - HISTORY - $Log: aeMB_testbench.c,v $ - Revision 1.14 2007/12/28 21:44:04 sybreon - Added malloc() test - - Revision 1.13 2007/12/11 00:44:31 sybreon - Modified for AEMB2 - - Revision 1.12 2007/11/18 19:41:45 sybreon - Minor simulation fixes. - - Revision 1.11 2007/11/14 23:41:06 sybreon - Fixed minor interrupt test typo. - - Revision 1.10 2007/11/14 22:12:02 sybreon - Added interrupt test routine. - - Revision 1.9 2007/11/09 20:51:53 sybreon - Added GET/PUT support through a FSL bus. - - Revision 1.8 2007/11/03 08:40:18 sybreon - Minor code cleanup. - - Revision 1.7 2007/11/02 18:32:19 sybreon - Enable MSR_IE with software. - - Revision 1.6 2007/04/30 15:57:10 sybreon - Removed byte acrobatics. - - Revision 1.5 2007/04/27 15:17:59 sybreon - Added code documentation. - Added new tests that test floating point, modulo arithmetic and multiplication/division. - - Revision 1.4 2007/04/25 22:15:05 sybreon - Added support for 8-bit and 16-bit data types. - - Revision 1.3 2007/04/04 14:09:04 sybreon - Added initial interrupt/exception support. - - Revision 1.2 2007/04/04 06:07:45 sybreon - Fixed C code bug which passes the test - - Revision 1.1 2007/03/09 17:41:57 sybreon - initial import -*/ diff --git a/opencores/aemb/sw/c/endian-test.c b/opencores/aemb/sw/c/endian-test.c deleted file mode 100644 index b585f7a30..000000000 --- a/opencores/aemb/sw/c/endian-test.c +++ /dev/null @@ -1,86 +0,0 @@ - -#include "memory_map.h" - -int main() { - char *p = (char *)0x4000; - short *q = (short *)0x5000; - int *r= (int *)0x6000; - - int *output = (int *)0x7000; - - char s; - short t; - int u; - - // Write - // Bytes - *p = (char)1; - p++; - *p = (char)2; - p++; - *p = (char)3; - p++; - *p = (char)4; - p++; - *p = (char)5; - - // Words - *q = (short) 0x1112; - q++; - *q = (short) 0x1314; - q++; - *q = (short) 0x1516; - - // Double Words - *r = 0x21222324; - r++; - *r = 0x25262728; - r++; - *r = 0x292a2b2c; - - - // Read - p = (char *)0x6000; - s = *p; - if(s == 0x21) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - p = (char *)0x6001; - s = *p; - if(s == 0x22) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - p = (char *)0x6002; - s = *p; - if(s == 0x23) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - - p = (char *)0x6003; - s = *p; - if(s == 0x24) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - q = (short *)0x4000; - t = *q; - if(t == 0x0102) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - - r = (int *)0x4000; - u = *r; - if(u == 0x01020304) - *output = 0x53534150; // PASS - else - *output = 0x4C494146; // FAIL - -} diff --git a/opencores/aemb/sw/c/libaemb.h b/opencores/aemb/sw/c/libaemb.h deleted file mode 100644 index 329a327a1..000000000 --- a/opencores/aemb/sw/c/libaemb.h +++ /dev/null @@ -1,218 +0,0 @@ -/* $Id: libaemb.h,v 1.3 2007/12/16 03:26:37 sybreon Exp $ -** -** AEMB2 CUSTOM LIBRARY -** -** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap -** -** This file is part of AEMB. -** -** AEMB is free software: you can redistribute it and/or modify it -** under the terms of the GNU Lesser General Public License as -** published by the Free Software Foundation, either version 3 of the -** License, or (at your option) any later version. -** -** AEMB is distributed in the hope that it will be useful, but WITHOUT -** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -** Public License for more details. -** -** You should have received a copy of the GNU Lesser General Public -** License along with AEMB. If not, see . -*/ - -#ifndef LIBAEMB_H -#define LIBAEMB_H - -#define AEMB_TXE 0x0100 -#define AEMB_TXP 0x0400 -#define AEMB_TX0 0x0300 -#define AEMB_TX1 0x0700 -#define AEMB_MSK 0x0F00 - -#define AEMB_BIP 0x0008 -#define AEMB_CCC 0x0004 -#define AEMB_ITE 0x0002 -#define AEMB_BLE 0x0001 - - -// Linker symbols -extern void* _STACK_SIZE; -extern void* _stack_end; - - -void aemb_hook_init () asm ("_program_init"); -void aemb_hook_clean () asm ("_program_clean"); - -inline void aemb_enable_interrupt (); -inline void aemb_disable_interrupt (); -inline int aemb_isthread1(); -inline int aemb_isthread0(); -inline int aemb_isthreaded(); - -/*! -* Assembly macro to enable MSR_IE -*/ -void aemb_enable_interrupt () -{ - int msr, tmp; - asm volatile ("mfs %0, rmsr;" - "ori %1, %0, 0x02;" - "mts rmsr, %1;" - : "=r"(msr) - : "r" (tmp) - ); -} - -/*! -* Assembly macro to disable MSR_IE -*/ -void aemb_disable_interrupt () -{ - int msr, tmp; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, 0xFD;" - "mts rmsr, %1;" - : "=r"(msr) - : "r" (tmp) - ); -} - -/*! -* Bootstrap Hook Override -*/ - -void aemb_hook_init () -{ - int msr, tmp; - int stk_end, stk_siz; - - /* - // Check to see if hardware threads are enabled - if (((msr & AEMB_TXE) != AEMB_TXE) || - // Check to see if second thread is started - ((msr & AEMB_TX1) == AEMB_TX1)) return; - */ - //return; - asm volatile ("mfs %0, rmsr;" - // Check for BIP - "andi %1, %0, %5;" - "xori %1, %1, %5;" - "beqi %1, 44;" - - // Check for TXE - "andi %1, %0, %2;" - "xori %1, %1, %2;" - "bnei %1, 36;" - - // Check for TX1 - "andi %1, %0, %3;" - "xori %1, %1, %3;" - "beqi %1, 20;" - - // reallocate stack pointer for T0 - "ori %1, r0, %4;" - "sra %1, %1;" - "rsubk r1, %1, r1;" - - // reboot the machine - //"brki r0, _crtinit;" - "brid 0;" - "nop;" - - // clear BIP - "andni %1, %0, %5;" - "mts rmsr, %1;" - - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE), "i"(AEMB_BIP) - ); - -} - -/*! - Undo the changes made by programme init -*/ - -void aemb_hook_clean () -{ - int msr, tmp; - int stk_end, stk_siz; - - /* - // Check to see if hardware threads are enabled - if (((msr & AEMB_TXE) != AEMB_TXE) || - // Check to see if second thread is started - ((msr & AEMB_TX1) == AEMB_TX1)) return; - */ - return; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, %2;" - "xori %1, %1, %2;" - "bnei %1, 28;" - "andi %1, %0, %3;" - "xori %1, %1, %3;" - "beqi %1, 16;" - - // reallocate stack pointer for T0 - "ori %1, r0, %4;" - "sra %1, %1;" - "addk r1, %1, r1;" - - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE) - ); - - -} - -/* Checks if it's T1, and returns 0 if true */ - -int aemb_isthread1 () -{ - int msr, tmp, res; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, %3;" - "xori %1, %1, %3;" - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXE), "i"(AEMB_TXP) - ); - return tmp; -} - -/* Checks if it's T0, and returns 0 if true */ - -int aemb_isthread0 () -{ - int msr, tmp, res; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, %3;" - "xori %1, %1, %2;" - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXP), "i"(AEMB_MSK) - ); - return tmp; -} - -/* Checks if TXE is available, and returns 0 if true */ - -int aemb_isthreaded () -{ - int msr, tmp, res; - asm volatile ("mfs %0, rmsr;" - "andi %1, %0, %2;" - "xori %1, %1, %2;" - :"=r"(msr), "=r"(tmp) - :"i"(AEMB_TXE), "i"(AEMB_MSK) - ); - return tmp; -} - -#endif - -/* $Log: libaemb.h,v $ -/* Revision 1.3 2007/12/16 03:26:37 sybreon -/* Made T0 loop. -/* -/* Revision 1.1 2007/12/11 00:44:04 sybreon -/* initial import -/* */ diff --git a/opencores/aemb/sw/gccrom b/opencores/aemb/sw/gccrom deleted file mode 100755 index f6e581f1f..000000000 --- a/opencores/aemb/sw/gccrom +++ /dev/null @@ -1,62 +0,0 @@ -#!/bin/sh -# $Id: gccrom,v 1.13 2008/01/19 16:42:54 sybreon Exp $ - -# Compile using C++ pre-processor -mb-g++ -g -Wl,-defsym -Wl,_HEAP_SIZE=0x800 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul -mno-clearbss $@ -o rom.elf -lc_m_bs -lm_m_bs && \ - -# Create a text listing of the compiled code -mb-objdump -DSC rom.elf > rom.dump && \ - -# Convert the ELF file to an SREC file -mb-objcopy -O srec rom.elf rom.srec && \ - -# Generate a Verilog VMEM file from the SREC file -srec_cat rom.srec -o ../sim/dump.vmem -vmem 32 && \ - -# Cleanup code -rm rom.srec && \ - -# Say Cheeze! -echo "ROM generated" - -# $Log: gccrom,v $ -# Revision 1.13 2008/01/19 16:42:54 sybreon -# Uses multiplier + barrel shifter as default. -# -# Revision 1.12 2007/12/11 00:44:32 sybreon -# Modified for AEMB2 -# -# Revision 1.11 2007/11/30 17:09:27 sybreon -# Minor code cleanup. -# -# Revision 1.10 2007/11/20 18:35:34 sybreon -# Generate VMEM instead of HEX dumps of programme. -# -# Revision 1.9 2007/11/18 19:41:46 sybreon -# Minor simulation fixes. -# -# Revision 1.8 2007/11/09 20:52:37 sybreon -# Added some compilation optimisations. -# -# Revision 1.7 2007/11/04 05:16:25 sybreon -# Added -msoft-float and -mxl-soft-div compiler flags. -# -# Revision 1.6 2007/11/02 03:25:46 sybreon -# New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -# Fixed various minor data hazard bugs. -# Code compatible with -O0/1/2/3/s generated code. -# -# Revision 1.5 2007/10/22 19:14:38 sybreon -# Recommended to compile code with -O2/3/s -# -# Revision 1.4 2007/04/30 15:57:31 sybreon -# Modified compilation sequence. -# -# Revision 1.3 2007/04/25 22:15:06 sybreon -# Added support for 8-bit and 16-bit data types. -# -# Revision 1.2 2007/04/04 06:14:39 sybreon -# Minor changes -# -# Revision 1.1 2007/03/09 17:41:56 sybreon -# initial import diff --git a/opencores/i2c/CVS/Entries b/opencores/i2c/CVS/Entries deleted file mode 100644 index d6947544a..000000000 --- a/opencores/i2c/CVS/Entries +++ /dev/null @@ -1,8 +0,0 @@ -D/bench//// -D/doc//// -D/documentation//// -D/rtl//// -D/sim//// -D/software//// -D/verilog//// -D/vhdl//// diff --git a/opencores/i2c/CVS/Repository b/opencores/i2c/CVS/Repository deleted file mode 100644 index 1a9fe8960..000000000 --- a/opencores/i2c/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c diff --git a/opencores/i2c/CVS/Root b/opencores/i2c/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/CVS/Template b/opencores/i2c/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/bench/CVS/Entries b/opencores/i2c/bench/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/opencores/i2c/bench/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/opencores/i2c/bench/CVS/Repository b/opencores/i2c/bench/CVS/Repository deleted file mode 100644 index 5597c8aac..000000000 --- a/opencores/i2c/bench/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/bench diff --git a/opencores/i2c/bench/CVS/Root b/opencores/i2c/bench/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/bench/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/bench/CVS/Template b/opencores/i2c/bench/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/bench/verilog/CVS/Entries b/opencores/i2c/bench/verilog/CVS/Entries deleted file mode 100644 index 2dd779100..000000000 --- a/opencores/i2c/bench/verilog/CVS/Entries +++ /dev/null @@ -1,5 +0,0 @@ -/i2c_slave_model.v/1.7/Mon Sep 4 09:08:51 2006// -/spi_slave_model.v/1.1/Sat Feb 28 15:32:54 2004// -/tst_bench_top.v/1.8/Mon Sep 4 09:08:51 2006// -/wb_master_model.v/1.4/Sat Feb 28 15:40:42 2004// -D diff --git a/opencores/i2c/bench/verilog/CVS/Repository b/opencores/i2c/bench/verilog/CVS/Repository deleted file mode 100644 index b37c379e9..000000000 --- a/opencores/i2c/bench/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/bench/verilog diff --git a/opencores/i2c/bench/verilog/CVS/Root b/opencores/i2c/bench/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/bench/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/bench/verilog/CVS/Template b/opencores/i2c/bench/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/bench/verilog/i2c_slave_model.v b/opencores/i2c/bench/verilog/i2c_slave_model.v deleted file mode 100644 index 0c8ecae0d..000000000 --- a/opencores/i2c/bench/verilog/i2c_slave_model.v +++ /dev/null @@ -1,360 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant synthesizable I2C Slave model //// -//// //// -//// //// -//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// -//// John Sheahan (jrsheahan@optushome.com.au) //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001,2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_slave_model.v,v 1.7 2006/09/04 09:08:51 rherveille Exp $ -// -// $Date: 2006/09/04 09:08:51 $ -// $Revision: 1.7 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_slave_model.v,v $ -// Revision 1.7 2006/09/04 09:08:51 rherveille -// fixed (n)ack generation -// -// Revision 1.6 2005/02/28 11:33:48 rherveille -// Fixed Tsu:sta timing check. -// Added Thd:sta timing check. -// -// Revision 1.5 2003/12/05 11:05:19 rherveille -// Fixed slave address MSB='1' bug -// -// Revision 1.4 2003/09/11 08:25:37 rherveille -// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. -// -// Revision 1.3 2002/10/30 18:11:06 rherveille -// Added timing tests to i2c_model. -// Updated testbench. -// -// Revision 1.2 2002/03/17 10:26:38 rherveille -// Fixed some race conditions in the i2c-slave model. -// Added debug information. -// Added headers. -// - -`include "timescale.v" - -module i2c_slave_model (scl, sda); - - // - // parameters - // - parameter I2C_ADR = 7'b001_0000; - - // - // input && outpus - // - input scl; - inout sda; - - // - // Variable declaration - // - wire debug = 1'b1; - - reg [7:0] mem [3:0]; // initiate memory - reg [7:0] mem_adr; // memory address - reg [7:0] mem_do; // memory data output - - reg sta, d_sta; - reg sto, d_sto; - - reg [7:0] sr; // 8bit shift register - reg rw; // read/write direction - - wire my_adr; // my address called ?? - wire i2c_reset; // i2c-statemachine reset - reg [2:0] bit_cnt; // 3bit downcounter - wire acc_done; // 8bits transfered - reg ld; // load downcounter - - reg sda_o; // sda-drive level - wire sda_dly; // delayed version of sda - - // statemachine declaration - parameter idle = 3'b000; - parameter slave_ack = 3'b001; - parameter get_mem_adr = 3'b010; - parameter gma_ack = 3'b011; - parameter data = 3'b100; - parameter data_ack = 3'b101; - - reg [2:0] state; // synopsys enum_state - - // - // module body - // - - initial - begin - sda_o = 1'b1; - state = idle; - end - - // generate shift register - always @(posedge scl) - sr <= #1 {sr[6:0],sda}; - - //detect my_address - assign my_adr = (sr[7:1] == I2C_ADR); - // FIXME: This should not be a generic assign, but rather - // qualified on address transfer phase and probably reset by stop - - //generate bit-counter - always @(posedge scl) - if(ld) - bit_cnt <= #1 3'b111; - else - bit_cnt <= #1 bit_cnt - 3'h1; - - //generate access done signal - assign acc_done = !(|bit_cnt); - - // generate delayed version of sda - // this model assumes a hold time for sda after the falling edge of scl. - // According to the Phillips i2c spec, there s/b a 0 ns hold time for sda - // with regards to scl. If the data changes coincident with the clock, the - // acknowledge is missed - // Fix by Michael Sosnoski - assign #1 sda_dly = sda; - - - //detect start condition - always @(negedge sda) - if(scl) - begin - sta <= #1 1'b1; - d_sta <= #1 1'b0; - sto <= #1 1'b0; - - if(debug) - $display("DEBUG i2c_slave; start condition detected at %t", $time); - end - else - sta <= #1 1'b0; - - always @(posedge scl) - d_sta <= #1 sta; - - // detect stop condition - always @(posedge sda) - if(scl) - begin - sta <= #1 1'b0; - sto <= #1 1'b1; - - if(debug) - $display("DEBUG i2c_slave; stop condition detected at %t", $time); - end - else - sto <= #1 1'b0; - - //generate i2c_reset signal - assign i2c_reset = sta || sto; - - // generate statemachine - always @(negedge scl or posedge sto) - if (sto || (sta && !d_sta) ) - begin - state <= #1 idle; // reset statemachine - - sda_o <= #1 1'b1; - ld <= #1 1'b1; - end - else - begin - // initial settings - sda_o <= #1 1'b1; - ld <= #1 1'b0; - - case(state) // synopsys full_case parallel_case - idle: // idle state - if (acc_done && my_adr) - begin - state <= #1 slave_ack; - rw <= #1 sr[0]; - sda_o <= #1 1'b0; // generate i2c_ack - - #2; - if(debug && rw) - $display("DEBUG i2c_slave; command byte received (read) at %t", $time); - if(debug && !rw) - $display("DEBUG i2c_slave; command byte received (write) at %t", $time); - - if(rw) - begin - mem_do <= #1 mem[mem_adr]; - - if(debug) - begin - #2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr); - #2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]); - end - end - end - - slave_ack: - begin - if(rw) - begin - state <= #1 data; - sda_o <= #1 mem_do[7]; - end - else - state <= #1 get_mem_adr; - - ld <= #1 1'b1; - end - - get_mem_adr: // wait for memory address - if(acc_done) - begin - state <= #1 gma_ack; - mem_adr <= #1 sr; // store memory address - sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address - - if(debug) - #1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o); - end - - gma_ack: - begin - state <= #1 data; - ld <= #1 1'b1; - end - - data: // receive or drive data - begin - if(rw) - sda_o <= #1 mem_do[7]; - - if(acc_done) - begin - state <= #1 data_ack; - mem_adr <= #2 mem_adr + 8'h1; - sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read - - if(rw) - begin - #3 mem_do <= mem[mem_adr]; - - if(debug) - #5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr); - end - - if(!rw) - begin - mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory - - if(debug) - #2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr); - end - end - end - - data_ack: - begin - ld <= #1 1'b1; - - if(rw) - if(sr[0]) // read operation && master send NACK - begin - state <= #1 idle; - sda_o <= #1 1'b1; - end - else - begin - state <= #1 data; - sda_o <= #1 mem_do[7]; - end - else - begin - state <= #1 data; - sda_o <= #1 1'b1; - end - end - - endcase - end - - // read data from memory - always @(posedge scl) - if(!acc_done && rw) - mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation - - // generate tri-states - assign sda = sda_o ? 1'bz : 1'b0; - - - // - // Timing checks - // - - wire tst_sto = sto; - wire tst_sta = sta; - - specify - specparam normal_scl_low = 4700, - normal_scl_high = 4000, - normal_tsu_sta = 4700, - normal_thd_sta = 4000, - normal_tsu_sto = 4000, - normal_tbuf = 4700, - - fast_scl_low = 1300, - fast_scl_high = 600, - fast_tsu_sta = 1300, - fast_thd_sta = 600, - fast_tsu_sto = 600, - fast_tbuf = 1300; - - $width(negedge scl, normal_scl_low); // scl low time - $width(posedge scl, normal_scl_high); // scl high time - - $setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start - $setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start - $setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop - - $setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time - endspecify - -endmodule - - diff --git a/opencores/i2c/bench/verilog/spi_slave_model.v b/opencores/i2c/bench/verilog/spi_slave_model.v deleted file mode 100644 index 7d2f436f9..000000000 --- a/opencores/i2c/bench/verilog/spi_slave_model.v +++ /dev/null @@ -1,128 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// SPI Slave Model //// -//// //// -//// //// -//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// -//// //// -//// http://www.opencores.org/projects/simple_spi/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2004 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: spi_slave_model.v,v 1.1 2004/02/28 15:32:54 rherveille Exp $ -// -// $Date: 2004/02/28 15:32:54 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: spi_slave_model.v,v $ -// Revision 1.1 2004/02/28 15:32:54 rherveille -// Added testbench -// -// -// - - -// Requires: Verilog2001 - -`include "timescale.v" - -module spi_slave_model ( - input wire csn; - input wire sck - input wire di; - output wire do -); - - // - // Variable declaration - // - wire debug = 1'b1; - - wire cpol = 1'b0; - wire cpha = 1'b0; - - reg [7:0] mem [7:0]; // initiate memory - reg [2:0] mem_adr; // memory address - reg [7:0] mem_do; // memory data output - - reg [7:0] sri, sro; // 8bit shift register - - reg [2:0] bit_cnt; - reg ld; - - wire clk; - - // - // module body - // - - assign clk = cpol ^ cpha ^ sck; - - // generate shift registers - always @(posedge clk) - sri <= #1 {sri[6:0],di}; - - always @(posedge clk) - if (&bit_cnt) - sro <= #1 mem[mem_adr]; - else - sro <= #1 {sro[6:0],1'bx}; - - assign do = sro[7]; - - //generate bit-counter - always @(posedge clk, posedge csn) - if(csn) - bit_cnt <= #1 3'b111; - else - bit_cnt <= #1 bit_cnt - 3'h1; - - //generate access done signal - always @(posedge clk) - ld <= #1 ~(|bit_cnt); - - always @(negedge clk) - if (ld) begin - mem[mem_adr] <= #1 sri; - mem_adr <= #1 mem_adr + 1'b1; - end - - initial - begin - bit_cnt=3'b111; - mem_adr = 0; - sro = mem[mem_adr]; - end -endmodule - - diff --git a/opencores/i2c/bench/verilog/tst_bench_top.v b/opencores/i2c/bench/verilog/tst_bench_top.v deleted file mode 100644 index 66284e4d4..000000000 --- a/opencores/i2c/bench/verilog/tst_bench_top.v +++ /dev/null @@ -1,467 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant I2C Master controller Testbench //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: tst_bench_top.v,v 1.8 2006/09/04 09:08:51 rherveille Exp $ -// -// $Date: 2006/09/04 09:08:51 $ -// $Revision: 1.8 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: tst_bench_top.v,v $ -// Revision 1.8 2006/09/04 09:08:51 rherveille -// fixed (n)ack generation -// -// Revision 1.7 2005/02/27 09:24:18 rherveille -// Fixed scl, sda delay. -// -// Revision 1.6 2004/02/28 15:40:42 rherveille -// *** empty log message *** -// -// Revision 1.4 2003/12/05 11:04:38 rherveille -// Added slave address configurability -// -// Revision 1.3 2002/10/30 18:11:06 rherveille -// Added timing tests to i2c_model. -// Updated testbench. -// -// Revision 1.2 2002/03/17 10:26:38 rherveille -// Fixed some race conditions in the i2c-slave model. -// Added debug information. -// Added headers. -// - -`include "timescale.v" - -module tst_bench_top(); - - // - // wires && regs - // - reg clk; - reg rstn; - - wire [31:0] adr; - wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i; - wire we; - wire stb; - wire cyc; - wire ack; - wire inta; - - reg [7:0] q, qq; - - wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen; - wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen; - - parameter PRER_LO = 3'b000; - parameter PRER_HI = 3'b001; - parameter CTR = 3'b010; - parameter RXR = 3'b011; - parameter TXR = 3'b011; - parameter CR = 3'b100; - parameter SR = 3'b100; - - parameter TXR_R = 3'b101; // undocumented / reserved output - parameter CR_R = 3'b110; // undocumented / reserved output - - parameter RD = 1'b1; - parameter WR = 1'b0; - parameter SADR = 7'b0010_000; - - // - // Module body - // - - // generate clock - always #5 clk = ~clk; - - // hookup wishbone master model - wb_master_model #(8, 32) u0 ( - .clk(clk), - .rst(rstn), - .adr(adr), - .din(dat_i), - .dout(dat_o), - .cyc(cyc), - .stb(stb), - .we(we), - .sel(), - .ack(ack), - .err(1'b0), - .rty(1'b0) - ); - - wire stb0 = stb & ~adr[3]; - wire stb1 = stb & adr[3]; - - assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i); - - // hookup wishbone_i2c_master core - i2c_master_top i2c_top ( - - // wishbone interface - .wb_clk_i(clk), - .wb_rst_i(1'b0), - .arst_i(rstn), - .wb_adr_i(adr[2:0]), - .wb_dat_i(dat_o), - .wb_dat_o(dat0_i), - .wb_we_i(we), - .wb_stb_i(stb0), - .wb_cyc_i(cyc), - .wb_ack_o(ack), - .wb_inta_o(inta), - - // i2c signals - .scl_pad_i(scl), - .scl_pad_o(scl0_o), - .scl_padoen_o(scl0_oen), - .sda_pad_i(sda), - .sda_pad_o(sda0_o), - .sda_padoen_o(sda0_oen) - ), - i2c_top2 ( - - // wishbone interface - .wb_clk_i(clk), - .wb_rst_i(1'b0), - .arst_i(rstn), - .wb_adr_i(adr[2:0]), - .wb_dat_i(dat_o), - .wb_dat_o(dat1_i), - .wb_we_i(we), - .wb_stb_i(stb1), - .wb_cyc_i(cyc), - .wb_ack_o(ack), - .wb_inta_o(inta), - - // i2c signals - .scl_pad_i(scl), - .scl_pad_o(scl1_o), - .scl_padoen_o(scl1_oen), - .sda_pad_i(sda), - .sda_pad_o(sda1_o), - .sda_padoen_o(sda1_oen) - ); - - - // hookup i2c slave model - i2c_slave_model #(SADR) i2c_slave ( - .scl(scl), - .sda(sda) - ); - - // create i2c lines - delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl), - m1_scl (scl1_oen ? 1'bz : scl1_o, scl), - m0_sda (sda0_oen ? 1'bz : sda0_o, sda), - m1_sda (sda1_oen ? 1'bz : sda1_o, sda); - - pullup p1(scl); // pullup scl line - pullup p2(sda); // pullup sda line - - initial - begin - `ifdef WAVES - $shm_open("waves"); - $shm_probe("AS",tst_bench_top,"AS"); - $display("INFO: Signal dump enabled ...\n\n"); - `endif - -// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information - force i2c_slave.debug = 1'b0; // disable i2c_slave debug information - - $display("\nstatus: %t Testbench started\n\n", $time); - -// $dumpfile("bench.vcd"); -// $dumpvars(1, tst_bench_top); -// $dumpvars(1, tst_bench_top.i2c_slave); - - // initially values - clk = 0; - - // reset system - rstn = 1'b1; // negate reset - #2; - rstn = 1'b0; // assert reset - repeat(1) @(posedge clk); - rstn = 1'b1; // negate reset - - $display("status: %t done reset", $time); - - @(posedge clk); - - // - // program core - // - - // program internal registers - u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte - u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte - u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte - $display("status: %t programmed registers", $time); - - u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte - u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte - $display("status: %t verified registers", $time); - - u0.wb_write(1, CTR, 8'h80); // enable core - $display("status: %t core enabled", $time); - - // - // access slave (write) - // - - // drive slave address - u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit - u0.wb_write(0, CR, 8'h90 ); // set command (start, write) - $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} ); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(0, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory address - u0.wb_write(1, TXR, 8'h01); // present slave's memory address - u0.wb_write(0, CR, 8'h10); // set command (write) - $display("status: %t write slave memory address 01", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(0, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory contents - u0.wb_write(1, TXR, 8'ha5); // present data - u0.wb_write(0, CR, 8'h10); // set command (write) - $display("status: %t write data a5", $time); - -while (scl) #1; -force scl= 1'b0; -#100000; -release scl; - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory contents for next memory address (auto_inc) - u0.wb_write(1, TXR, 8'h5a); // present data - u0.wb_write(0, CR, 8'h50); // set command (stop, write) - $display("status: %t write next data 5a, generate 'stop'", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // - // delay - // -// #100000; // wait for 100us. -// $display("status: %t wait 100us", $time); - - // - // access slave (read) - // - - // drive slave address - u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit - u0.wb_write(0, CR, 8'h90 ); // set command (start, write) - $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} ); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory address - u0.wb_write(1, TXR, 8'h01); // present slave's memory address - u0.wb_write(0, CR, 8'h10); // set command (write) - $display("status: %t write slave address 01", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // drive slave address - u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit - u0.wb_write(0, CR, 8'h90 ); // set command (start, write) - $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} ); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // read data from slave - u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) - $display("status: %t read + ack", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // check data just received - u0.wb_read(1, RXR, qq); - if(qq !== 8'ha5) - $display("\nERROR: Expected a5, received %x at time %t", qq, $time); - else - $display("status: %t received %x", $time, qq); - - // read data from slave - u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) - $display("status: %t read + ack", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // check data just received - u0.wb_read(1, RXR, qq); - if(qq !== 8'h5a) - $display("\nERROR: Expected 5a, received %x at time %t", qq, $time); - else - $display("status: %t received %x", $time, qq); - - // read data from slave - u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) - $display("status: %t read + ack", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // check data just received - u0.wb_read(1, RXR, qq); - $display("status: %t received %x from 3rd read address", $time, qq); - - // read data from slave - u0.wb_write(1, CR, 8'h28); // set command (read, nack_read) - $display("status: %t read + nack", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // check data just received - u0.wb_read(1, RXR, qq); - $display("status: %t received %x from 4th read address", $time, qq); - - // - // check invalid slave memory address - // - - // drive slave address - u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit - u0.wb_write(0, CR, 8'h90 ); // set command (start, write) - $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} ); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // send memory address - u0.wb_write(1, TXR, 8'h10); // present slave's memory address - u0.wb_write(0, CR, 8'h10); // set command (write) - $display("status: %t write slave memory address 10", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - // slave should have send NACK - $display("status: %t Check for nack", $time); - if(!q[7]) - $display("\nERROR: Expected NACK, received ACK\n"); - - // read data from slave - u0.wb_write(1, CR, 8'h40); // set command (stop) - $display("status: %t generate 'stop'", $time); - - // check tip bit - u0.wb_read(1, SR, q); - while(q[1]) - u0.wb_read(1, SR, q); // poll it until it is zero - $display("status: %t tip==0", $time); - - #250000; // wait 250us - $display("\n\nstatus: %t Testbench done", $time); - $finish; - end - -endmodule - -module delay (in, out); - input in; - output out; - - assign out = in; - - specify - (in => out) = (600,600); - endspecify -endmodule - - diff --git a/opencores/i2c/bench/verilog/wb_master_model.v b/opencores/i2c/bench/verilog/wb_master_model.v deleted file mode 100644 index 14ed6cbf5..000000000 --- a/opencores/i2c/bench/verilog/wb_master_model.v +++ /dev/null @@ -1,205 +0,0 @@ -/////////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 Wishbone Master model //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/mem_ctrl //// -//// //// -/////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -/////////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $ -// -// $Date: 2004/02/28 15:40:42 $ -// $Revision: 1.4 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// -`include "timescale.v" - -module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); - -parameter dwidth = 32; -parameter awidth = 32; - -input clk, rst; -output [awidth -1:0] adr; -input [dwidth -1:0] din; -output [dwidth -1:0] dout; -output cyc, stb; -output we; -output [dwidth/8 -1:0] sel; -input ack, err, rty; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -reg [awidth -1:0] adr; -reg [dwidth -1:0] dout; -reg cyc, stb; -reg we; -reg [dwidth/8 -1:0] sel; - -reg [dwidth -1:0] q; - -//////////////////////////////////////////////////////////////////// -// -// Memory Logic -// - -initial - begin - //adr = 32'hxxxx_xxxx; - //adr = 0; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - cyc = 1'b0; - stb = 1'bx; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - #1; - $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); - end - -//////////////////////////////////////////////////////////////////// -// -// Wishbone write cycle -// - -task wb_write; - input delay; - integer delay; - - input [awidth -1:0] a; - input [dwidth -1:0] d; - - begin - - // wait initial delay - repeat(delay) @(posedge clk); - - // assert wishbone signal - #1; - adr = a; - dout = d; - cyc = 1'b1; - stb = 1'b1; - we = 1'b1; - sel = {dwidth/8{1'b1}}; - @(posedge clk); - - // wait for acknowledge from slave - while(~ack) @(posedge clk); - - // negate wishbone signals - #1; - cyc = 1'b0; - stb = 1'bx; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - - end -endtask - -//////////////////////////////////////////////////////////////////// -// -// Wishbone read cycle -// - -task wb_read; - input delay; - integer delay; - - input [awidth -1:0] a; - output [dwidth -1:0] d; - - begin - - // wait initial delay - repeat(delay) @(posedge clk); - - // assert wishbone signals - #1; - adr = a; - dout = {dwidth{1'bx}}; - cyc = 1'b1; - stb = 1'b1; - we = 1'b0; - sel = {dwidth/8{1'b1}}; - @(posedge clk); - - // wait for acknowledge from slave - while(~ack) @(posedge clk); - - // negate wishbone signals - #1; - cyc = 1'b0; - stb = 1'bx; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - d = din; - - end -endtask - -//////////////////////////////////////////////////////////////////// -// -// Wishbone compare cycle (read data from location and compare with expected data) -// - -task wb_cmp; - input delay; - integer delay; - - input [awidth -1:0] a; - input [dwidth -1:0] d_exp; - - begin - wb_read (delay, a, q); - - if (d_exp !== q) - $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); - end -endtask - -endmodule - - diff --git a/opencores/i2c/doc/CVS/Entries b/opencores/i2c/doc/CVS/Entries deleted file mode 100644 index ec323c90b..000000000 --- a/opencores/i2c/doc/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/i2c_specs.pdf/1.3/Thu Jul 3 15:20:47 2003/-kb/ -D/src//// diff --git a/opencores/i2c/doc/CVS/Repository b/opencores/i2c/doc/CVS/Repository deleted file mode 100644 index 2ee10951a..000000000 --- a/opencores/i2c/doc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/doc diff --git a/opencores/i2c/doc/CVS/Root b/opencores/i2c/doc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/doc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/doc/CVS/Template b/opencores/i2c/doc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/doc/i2c_specs.pdf b/opencores/i2c/doc/i2c_specs.pdf deleted file mode 100644 index 72021df11..000000000 Binary files a/opencores/i2c/doc/i2c_specs.pdf and /dev/null differ diff --git a/opencores/i2c/doc/src/CVS/Entries b/opencores/i2c/doc/src/CVS/Entries deleted file mode 100644 index 5eeda5738..000000000 --- a/opencores/i2c/doc/src/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/I2C_specs.doc/1.7/Thu Jul 3 15:21:23 2003/-kb/ -D diff --git a/opencores/i2c/doc/src/CVS/Repository b/opencores/i2c/doc/src/CVS/Repository deleted file mode 100644 index 74dd64858..000000000 --- a/opencores/i2c/doc/src/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/doc/src diff --git a/opencores/i2c/doc/src/CVS/Root b/opencores/i2c/doc/src/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/doc/src/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/doc/src/CVS/Template b/opencores/i2c/doc/src/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/doc/src/I2C_specs.doc b/opencores/i2c/doc/src/I2C_specs.doc deleted file mode 100644 index 31ab2684f..000000000 Binary files a/opencores/i2c/doc/src/I2C_specs.doc and /dev/null differ diff --git a/opencores/i2c/documentation/CVS/Entries b/opencores/i2c/documentation/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/i2c/documentation/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/i2c/documentation/CVS/Repository b/opencores/i2c/documentation/CVS/Repository deleted file mode 100644 index 1ccd8f6ce..000000000 --- a/opencores/i2c/documentation/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/documentation diff --git a/opencores/i2c/documentation/CVS/Root b/opencores/i2c/documentation/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/documentation/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/documentation/CVS/Template b/opencores/i2c/documentation/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/rtl/CVS/Entries b/opencores/i2c/rtl/CVS/Entries deleted file mode 100644 index 354f0dfb5..000000000 --- a/opencores/i2c/rtl/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -D/verilog//// -D/vhdl//// diff --git a/opencores/i2c/rtl/CVS/Repository b/opencores/i2c/rtl/CVS/Repository deleted file mode 100644 index cfb83efd3..000000000 --- a/opencores/i2c/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/rtl diff --git a/opencores/i2c/rtl/CVS/Root b/opencores/i2c/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/rtl/CVS/Template b/opencores/i2c/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/rtl/verilog/CVS/Entries b/opencores/i2c/rtl/verilog/CVS/Entries deleted file mode 100644 index 441bd81af..000000000 --- a/opencores/i2c/rtl/verilog/CVS/Entries +++ /dev/null @@ -1,6 +0,0 @@ -/i2c_master_bit_ctrl.v/1.12/Mon Sep 4 09:08:13 2006// -/i2c_master_byte_ctrl.v/1.7/Wed Feb 18 11:40:46 2004// -/i2c_master_defines.v/1.3/Mon Nov 5 11:59:25 2001// -/i2c_master_top.v/1.11/Sun Feb 27 09:26:24 2005// -/timescale.v/1.1/Mon Sep 24 12:21:50 2001// -D diff --git a/opencores/i2c/rtl/verilog/CVS/Repository b/opencores/i2c/rtl/verilog/CVS/Repository deleted file mode 100644 index 49cc6cce0..000000000 --- a/opencores/i2c/rtl/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/rtl/verilog diff --git a/opencores/i2c/rtl/verilog/CVS/Root b/opencores/i2c/rtl/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/rtl/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/rtl/verilog/CVS/Template b/opencores/i2c/rtl/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v b/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v deleted file mode 100644 index edab94f61..000000000 --- a/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v +++ /dev/null @@ -1,538 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant I2C Master bit-controller //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_master_bit_ctrl.v,v 1.12 2006/09/04 09:08:13 rherveille Exp $ -// -// $Date: 2006/09/04 09:08:13 $ -// $Revision: 1.12 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_master_bit_ctrl.v,v $ -// Revision 1.12 2006/09/04 09:08:13 rherveille -// fixed short scl high pulse after clock stretch -// fixed slave model not returning correct '(n)ack' signal -// -// Revision 1.11 2004/05/07 11:02:26 rherveille -// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. -// -// Revision 1.10 2003/08/09 07:01:33 rherveille -// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. -// Fixed a potential bug in the byte controller's host-acknowledge generation. -// -// Revision 1.9 2003/03/10 14:26:37 rherveille -// Fixed cmd_ack generation item (no bug). -// -// Revision 1.8 2003/02/05 00:06:10 rherveille -// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. -// -// Revision 1.7 2002/12/26 16:05:12 rherveille -// Small code simplifications -// -// Revision 1.6 2002/12/26 15:02:32 rherveille -// Core is now a Multimaster I2C controller -// -// Revision 1.5 2002/11/30 22:24:40 rherveille -// Cleaned up code -// -// Revision 1.4 2002/10/30 18:10:07 rherveille -// Fixed some reported minor start/stop generation timing issuess. -// -// Revision 1.3 2002/06/15 07:37:03 rherveille -// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. -// -// Revision 1.2 2001/11/05 11:59:25 rherveille -// Fixed wb_ack_o generation bug. -// Fixed bug in the byte_controller statemachine. -// Added headers. -// - -// -///////////////////////////////////// -// Bit controller section -///////////////////////////////////// -// -// Translate simple commands into SCL/SDA transitions -// Each command has 5 states, A/B/C/D/idle -// -// start: SCL ~~~~~~~~~~\____ -// SDA ~~~~~~~~\______ -// x | A | B | C | D | i -// -// repstart SCL ____/~~~~\___ -// SDA __/~~~\______ -// x | A | B | C | D | i -// -// stop SCL ____/~~~~~~~~ -// SDA ==\____/~~~~~ -// x | A | B | C | D | i -// -//- write SCL ____/~~~~\____ -// SDA ==X=========X= -// x | A | B | C | D | i -// -//- read SCL ____/~~~~\____ -// SDA XXXX=====XXXX -// x | A | B | C | D | i -// - -// Timing: Normal mode Fast mode -/////////////////////////////////////////////////////////////////////// -// Fscl 100KHz 400KHz -// Th_scl 4.0us 0.6us High period of SCL -// Tl_scl 4.7us 1.3us Low period of SCL -// Tsu:sta 4.7us 0.6us setup time for a repeated start condition -// Tsu:sto 4.0us 0.6us setup time for a stop conditon -// Tbuf 4.7us 1.3us Bus free time between a stop and start condition -// - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on - -`include "i2c_master_defines.v" - -module i2c_master_bit_ctrl( - clk, rst, nReset, - clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout, - scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen - ); - - // - // inputs & outputs - // - input clk; - input rst; - input nReset; - input ena; // core enable signal - - input [15:0] clk_cnt; // clock prescale value - - input [3:0] cmd; - output cmd_ack; // command complete acknowledge - reg cmd_ack; - output busy; // i2c bus busy - reg busy; - output al; // i2c bus arbitration lost - reg al; - - input din; - output dout; - reg dout; - - // I2C lines - input scl_i; // i2c clock line input - output scl_o; // i2c clock line output - output scl_oen; // i2c clock line output enable (active low) - reg scl_oen; - input sda_i; // i2c data line input - output sda_o; // i2c data line output - output sda_oen; // i2c data line output enable (active low) - reg sda_oen; - - - // - // variable declarations - // - - reg sSCL, sSDA; // synchronized SCL and SDA inputs - reg dscl_oen; // delayed scl_oen - reg sda_chk; // check SDA output (Multi-master arbitration) - reg clk_en; // clock generation signals - wire slave_wait; -// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation) - reg [15:0] cnt; // clock divider counter (synthesis) - - // state machine variable - reg [16:0] c_state; // synopsys enum_state - - // - // module body - // - - // whenever the slave is not ready it can delay the cycle by pulling SCL low - // delay scl_oen - always @(posedge clk) - dscl_oen <= #1 scl_oen; - - assign slave_wait = dscl_oen && !sSCL; - - - // generate clk enable signal - always @(posedge clk or negedge nReset) - if(~nReset) - begin - cnt <= #1 16'h0; - clk_en <= #1 1'b1; - end - else if (rst) - begin - cnt <= #1 16'h0; - clk_en <= #1 1'b1; - end - else if ( ~|cnt || !ena) - begin - cnt <= #1 clk_cnt; - clk_en <= #1 1'b1; - end - else if (slave_wait) - begin - cnt <= #1 cnt; - clk_en <= #1 1'b0; - end - else - begin - cnt <= #1 cnt - 16'h1; - clk_en <= #1 1'b0; - end - - - // generate bus status controller - reg dSCL, dSDA; - reg sta_condition; - reg sto_condition; - - // synchronize SCL and SDA inputs - // reduce metastability risc - always @(posedge clk or negedge nReset) - if (~nReset) - begin - sSCL <= #1 1'b1; - sSDA <= #1 1'b1; - - dSCL <= #1 1'b1; - dSDA <= #1 1'b1; - end - else if (rst) - begin - sSCL <= #1 1'b1; - sSDA <= #1 1'b1; - - dSCL <= #1 1'b1; - dSDA <= #1 1'b1; - end - else - begin - sSCL <= #1 scl_i; - sSDA <= #1 sda_i; - - dSCL <= #1 sSCL; - dSDA <= #1 sSDA; - end - - // detect start condition => detect falling edge on SDA while SCL is high - // detect stop condition => detect rising edge on SDA while SCL is high - always @(posedge clk or negedge nReset) - if (~nReset) - begin - sta_condition <= #1 1'b0; - sto_condition <= #1 1'b0; - end - else if (rst) - begin - sta_condition <= #1 1'b0; - sto_condition <= #1 1'b0; - end - else - begin - sta_condition <= #1 ~sSDA & dSDA & sSCL; - sto_condition <= #1 sSDA & ~dSDA & sSCL; - end - - // generate i2c bus busy signal - always @(posedge clk or negedge nReset) - if(!nReset) - busy <= #1 1'b0; - else if (rst) - busy <= #1 1'b0; - else - busy <= #1 (sta_condition | busy) & ~sto_condition; - - // generate arbitration lost signal - // aribitration lost when: - // 1) master drives SDA high, but the i2c bus is low - // 2) stop detected while not requested - reg cmd_stop; - always @(posedge clk or negedge nReset) - if (~nReset) - cmd_stop <= #1 1'b0; - else if (rst) - cmd_stop <= #1 1'b0; - else if (clk_en) - cmd_stop <= #1 cmd == `I2C_CMD_STOP; - - always @(posedge clk or negedge nReset) - if (~nReset) - al <= #1 1'b0; - else if (rst) - al <= #1 1'b0; - else - al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop); - - - // generate dout signal (store SDA on rising edge of SCL) - always @(posedge clk) - if(sSCL & ~dSCL) - dout <= #1 sSDA; - - // generate statemachine - - // nxt_state decoder - parameter [16:0] idle = 17'b0_0000_0000_0000_0000; - parameter [16:0] start_a = 17'b0_0000_0000_0000_0001; - parameter [16:0] start_b = 17'b0_0000_0000_0000_0010; - parameter [16:0] start_c = 17'b0_0000_0000_0000_0100; - parameter [16:0] start_d = 17'b0_0000_0000_0000_1000; - parameter [16:0] start_e = 17'b0_0000_0000_0001_0000; - parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000; - parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000; - parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000; - parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000; - parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000; - parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000; - parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000; - parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000; - parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000; - parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000; - parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000; - parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000; - - always @(posedge clk or negedge nReset) - if (!nReset) - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b0; - scl_oen <= #1 1'b1; - sda_oen <= #1 1'b1; - sda_chk <= #1 1'b0; - end - else if (rst | al) - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b0; - scl_oen <= #1 1'b1; - sda_oen <= #1 1'b1; - sda_chk <= #1 1'b0; - end - else - begin - cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle - - if (clk_en) - case (c_state) // synopsys full_case parallel_case - // idle state - idle: - begin - case (cmd) // synopsys full_case parallel_case - `I2C_CMD_START: - c_state <= #1 start_a; - - `I2C_CMD_STOP: - c_state <= #1 stop_a; - - `I2C_CMD_WRITE: - c_state <= #1 wr_a; - - `I2C_CMD_READ: - c_state <= #1 rd_a; - - default: - c_state <= #1 idle; - endcase - - scl_oen <= #1 scl_oen; // keep SCL in same state - sda_oen <= #1 sda_oen; // keep SDA in same state - sda_chk <= #1 1'b0; // don't check SDA output - end - - // start - start_a: - begin - c_state <= #1 start_b; - scl_oen <= #1 scl_oen; // keep SCL in same state - sda_oen <= #1 1'b1; // set SDA high - sda_chk <= #1 1'b0; // don't check SDA output - end - - start_b: - begin - c_state <= #1 start_c; - scl_oen <= #1 1'b1; // set SCL high - sda_oen <= #1 1'b1; // keep SDA high - sda_chk <= #1 1'b0; // don't check SDA output - end - - start_c: - begin - c_state <= #1 start_d; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b0; // set SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - start_d: - begin - c_state <= #1 start_e; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b0; // keep SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - start_e: - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b1; - scl_oen <= #1 1'b0; // set SCL low - sda_oen <= #1 1'b0; // keep SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - // stop - stop_a: - begin - c_state <= #1 stop_b; - scl_oen <= #1 1'b0; // keep SCL low - sda_oen <= #1 1'b0; // set SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - stop_b: - begin - c_state <= #1 stop_c; - scl_oen <= #1 1'b1; // set SCL high - sda_oen <= #1 1'b0; // keep SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - stop_c: - begin - c_state <= #1 stop_d; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b0; // keep SDA low - sda_chk <= #1 1'b0; // don't check SDA output - end - - stop_d: - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b1; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b1; // set SDA high - sda_chk <= #1 1'b0; // don't check SDA output - end - - // read - rd_a: - begin - c_state <= #1 rd_b; - scl_oen <= #1 1'b0; // keep SCL low - sda_oen <= #1 1'b1; // tri-state SDA - sda_chk <= #1 1'b0; // don't check SDA output - end - - rd_b: - begin - c_state <= #1 rd_c; - scl_oen <= #1 1'b1; // set SCL high - sda_oen <= #1 1'b1; // keep SDA tri-stated - sda_chk <= #1 1'b0; // don't check SDA output - end - - rd_c: - begin - c_state <= #1 rd_d; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 1'b1; // keep SDA tri-stated - sda_chk <= #1 1'b0; // don't check SDA output - end - - rd_d: - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b1; - scl_oen <= #1 1'b0; // set SCL low - sda_oen <= #1 1'b1; // keep SDA tri-stated - sda_chk <= #1 1'b0; // don't check SDA output - end - - // write - wr_a: - begin - c_state <= #1 wr_b; - scl_oen <= #1 1'b0; // keep SCL low - sda_oen <= #1 din; // set SDA - sda_chk <= #1 1'b0; // don't check SDA output (SCL low) - end - - wr_b: - begin - c_state <= #1 wr_c; - scl_oen <= #1 1'b1; // set SCL high - sda_oen <= #1 din; // keep SDA - sda_chk <= #1 1'b1; // check SDA output - end - - wr_c: - begin - c_state <= #1 wr_d; - scl_oen <= #1 1'b1; // keep SCL high - sda_oen <= #1 din; - sda_chk <= #1 1'b1; // check SDA output - end - - wr_d: - begin - c_state <= #1 idle; - cmd_ack <= #1 1'b1; - scl_oen <= #1 1'b0; // set SCL low - sda_oen <= #1 din; - sda_chk <= #1 1'b0; // don't check SDA output (SCL low) - end - - endcase - end - - - // assign scl and sda output (always gnd) - assign scl_o = 1'b0; - assign sda_o = 1'b0; - -endmodule diff --git a/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v b/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v deleted file mode 100644 index d091d1e36..000000000 --- a/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v +++ /dev/null @@ -1,344 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant I2C Master byte-controller //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $ -// -// $Date: 2004/02/18 11:40:46 $ -// $Revision: 1.7 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_master_byte_ctrl.v,v $ -// Revision 1.7 2004/02/18 11:40:46 rherveille -// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. -// -// Revision 1.6 2003/08/09 07:01:33 rherveille -// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. -// Fixed a potential bug in the byte controller's host-acknowledge generation. -// -// Revision 1.5 2002/12/26 15:02:32 rherveille -// Core is now a Multimaster I2C controller -// -// Revision 1.4 2002/11/30 22:24:40 rherveille -// Cleaned up code -// -// Revision 1.3 2001/11/05 11:59:25 rherveille -// Fixed wb_ack_o generation bug. -// Fixed bug in the byte_controller statemachine. -// Added headers. -// - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on - -`include "i2c_master_defines.v" - -module i2c_master_byte_ctrl ( - clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din, - cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen ); - - // - // inputs & outputs - // - input clk; // master clock - input rst; // synchronous active high reset - input nReset; // asynchronous active low reset - input ena; // core enable signal - - input [15:0] clk_cnt; // 4x SCL - - // control inputs - input start; - input stop; - input read; - input write; - input ack_in; - input [7:0] din; - - // status outputs - output cmd_ack; - reg cmd_ack; - output ack_out; - reg ack_out; - output i2c_busy; - output i2c_al; - output [7:0] dout; - - // I2C signals - input scl_i; - output scl_o; - output scl_oen; - input sda_i; - output sda_o; - output sda_oen; - - - // - // Variable declarations - // - - // statemachine - parameter [4:0] ST_IDLE = 5'b0_0000; - parameter [4:0] ST_START = 5'b0_0001; - parameter [4:0] ST_READ = 5'b0_0010; - parameter [4:0] ST_WRITE = 5'b0_0100; - parameter [4:0] ST_ACK = 5'b0_1000; - parameter [4:0] ST_STOP = 5'b1_0000; - - // signals for bit_controller - reg [3:0] core_cmd; - reg core_txd; - wire core_ack, core_rxd; - - // signals for shift register - reg [7:0] sr; //8bit shift register - reg shift, ld; - - // signals for state machine - wire go; - reg [2:0] dcnt; - wire cnt_done; - - // - // Module body - // - - // hookup bit_controller - i2c_master_bit_ctrl bit_controller ( - .clk ( clk ), - .rst ( rst ), - .nReset ( nReset ), - .ena ( ena ), - .clk_cnt ( clk_cnt ), - .cmd ( core_cmd ), - .cmd_ack ( core_ack ), - .busy ( i2c_busy ), - .al ( i2c_al ), - .din ( core_txd ), - .dout ( core_rxd ), - .scl_i ( scl_i ), - .scl_o ( scl_o ), - .scl_oen ( scl_oen ), - .sda_i ( sda_i ), - .sda_o ( sda_o ), - .sda_oen ( sda_oen ) - ); - - // generate go-signal - assign go = (read | write | stop) & ~cmd_ack; - - // assign dout output to shift-register - assign dout = sr; - - // generate shift register - always @(posedge clk or negedge nReset) - if (!nReset) - sr <= #1 8'h0; - else if (rst) - sr <= #1 8'h0; - else if (ld) - sr <= #1 din; - else if (shift) - sr <= #1 {sr[6:0], core_rxd}; - - // generate counter - always @(posedge clk or negedge nReset) - if (!nReset) - dcnt <= #1 3'h0; - else if (rst) - dcnt <= #1 3'h0; - else if (ld) - dcnt <= #1 3'h7; - else if (shift) - dcnt <= #1 dcnt - 3'h1; - - assign cnt_done = ~(|dcnt); - - // - // state machine - // - reg [4:0] c_state; // synopsis enum_state - - always @(posedge clk or negedge nReset) - if (!nReset) - begin - core_cmd <= #1 `I2C_CMD_NOP; - core_txd <= #1 1'b0; - shift <= #1 1'b0; - ld <= #1 1'b0; - cmd_ack <= #1 1'b0; - c_state <= #1 ST_IDLE; - ack_out <= #1 1'b0; - end - else if (rst | i2c_al) - begin - core_cmd <= #1 `I2C_CMD_NOP; - core_txd <= #1 1'b0; - shift <= #1 1'b0; - ld <= #1 1'b0; - cmd_ack <= #1 1'b0; - c_state <= #1 ST_IDLE; - ack_out <= #1 1'b0; - end - else - begin - // initially reset all signals - core_txd <= #1 sr[7]; - shift <= #1 1'b0; - ld <= #1 1'b0; - cmd_ack <= #1 1'b0; - - case (c_state) // synopsys full_case parallel_case - ST_IDLE: - if (go) - begin - if (start) - begin - c_state <= #1 ST_START; - core_cmd <= #1 `I2C_CMD_START; - end - else if (read) - begin - c_state <= #1 ST_READ; - core_cmd <= #1 `I2C_CMD_READ; - end - else if (write) - begin - c_state <= #1 ST_WRITE; - core_cmd <= #1 `I2C_CMD_WRITE; - end - else // stop - begin - c_state <= #1 ST_STOP; - core_cmd <= #1 `I2C_CMD_STOP; - end - - ld <= #1 1'b1; - end - - ST_START: - if (core_ack) - begin - if (read) - begin - c_state <= #1 ST_READ; - core_cmd <= #1 `I2C_CMD_READ; - end - else - begin - c_state <= #1 ST_WRITE; - core_cmd <= #1 `I2C_CMD_WRITE; - end - - ld <= #1 1'b1; - end - - ST_WRITE: - if (core_ack) - if (cnt_done) - begin - c_state <= #1 ST_ACK; - core_cmd <= #1 `I2C_CMD_READ; - end - else - begin - c_state <= #1 ST_WRITE; // stay in same state - core_cmd <= #1 `I2C_CMD_WRITE; // write next bit - shift <= #1 1'b1; - end - - ST_READ: - if (core_ack) - begin - if (cnt_done) - begin - c_state <= #1 ST_ACK; - core_cmd <= #1 `I2C_CMD_WRITE; - end - else - begin - c_state <= #1 ST_READ; // stay in same state - core_cmd <= #1 `I2C_CMD_READ; // read next bit - end - - shift <= #1 1'b1; - core_txd <= #1 ack_in; - end - - ST_ACK: - if (core_ack) - begin - if (stop) - begin - c_state <= #1 ST_STOP; - core_cmd <= #1 `I2C_CMD_STOP; - end - else - begin - c_state <= #1 ST_IDLE; - core_cmd <= #1 `I2C_CMD_NOP; - - // generate command acknowledge signal - cmd_ack <= #1 1'b1; - end - - // assign ack_out output to bit_controller_rxd (contains last received bit) - ack_out <= #1 core_rxd; - - core_txd <= #1 1'b1; - end - else - core_txd <= #1 ack_in; - - ST_STOP: - if (core_ack) - begin - c_state <= #1 ST_IDLE; - core_cmd <= #1 `I2C_CMD_NOP; - - // generate command acknowledge signal - cmd_ack <= #1 1'b1; - end - - endcase - end -endmodule diff --git a/opencores/i2c/rtl/verilog/i2c_master_defines.v b/opencores/i2c/rtl/verilog/i2c_master_defines.v deleted file mode 100644 index ee3b694fa..000000000 --- a/opencores/i2c/rtl/verilog/i2c_master_defines.v +++ /dev/null @@ -1,64 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE rev.B2 compliant I2C Master controller defines //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $ -// -// $Date: 2001/11/05 11:59:25 $ -// $Revision: 1.3 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_master_defines.v,v $ -// Revision 1.3 2001/11/05 11:59:25 rherveille -// Fixed wb_ack_o generation bug. -// Fixed bug in the byte_controller statemachine. -// Added headers. -// - - -// I2C registers wishbone addresses - -// bitcontroller states -`define I2C_CMD_NOP 4'b0000 -`define I2C_CMD_START 4'b0001 -`define I2C_CMD_STOP 4'b0010 -`define I2C_CMD_WRITE 4'b0100 -`define I2C_CMD_READ 4'b1000 diff --git a/opencores/i2c/rtl/verilog/i2c_master_top.v b/opencores/i2c/rtl/verilog/i2c_master_top.v deleted file mode 100644 index 30689bd70..000000000 --- a/opencores/i2c/rtl/verilog/i2c_master_top.v +++ /dev/null @@ -1,301 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE revB.2 compliant I2C Master controller Top-level //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/projects/i2c/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $ -// -// $Date: 2005/02/27 09:26:24 $ -// $Revision: 1.11 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: i2c_master_top.v,v $ -// Revision 1.11 2005/02/27 09:26:24 rherveille -// Fixed register overwrite issue. -// Removed full_case pragma, replaced it by a default statement. -// -// Revision 1.10 2003/09/01 10:34:38 rherveille -// Fix a blocking vs. non-blocking error in the wb_dat output mux. -// -// Revision 1.9 2003/01/09 16:44:45 rherveille -// Fixed a bug in the Command Register declaration. -// -// Revision 1.8 2002/12/26 16:05:12 rherveille -// Small code simplifications -// -// Revision 1.7 2002/12/26 15:02:32 rherveille -// Core is now a Multimaster I2C controller -// -// Revision 1.6 2002/11/30 22:24:40 rherveille -// Cleaned up code -// -// Revision 1.5 2001/11/10 10:52:55 rherveille -// Changed PRER reset value from 0x0000 to 0xffff, conform specs. -// - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on - -`include "i2c_master_defines.v" - -module i2c_master_top( - wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o, - wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, - scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); - - // parameters - parameter ARST_LVL = 1'b0; // asynchronous reset level - - // - // inputs & outputs - // - - // wishbone signals - input wb_clk_i; // master clock input - input wb_rst_i; // synchronous active high reset - input arst_i; // asynchronous reset - input [2:0] wb_adr_i; // lower address bits - input [7:0] wb_dat_i; // databus input - output [7:0] wb_dat_o; // databus output - input wb_we_i; // write enable input - input wb_stb_i; // stobe/core select signal - input wb_cyc_i; // valid bus cycle input - output wb_ack_o; // bus cycle acknowledge output - output wb_inta_o; // interrupt request signal output - - reg [7:0] wb_dat_o; - reg wb_ack_o; - reg wb_inta_o; - - // I2C signals - // i2c clock line - input scl_pad_i; // SCL-line input - output scl_pad_o; // SCL-line output (always 1'b0) - output scl_padoen_o; // SCL-line output enable (active low) - - // i2c data line - input sda_pad_i; // SDA-line input - output sda_pad_o; // SDA-line output (always 1'b0) - output sda_padoen_o; // SDA-line output enable (active low) - - - // - // variable declarations - // - - // registers - reg [15:0] prer; // clock prescale register - reg [ 7:0] ctr; // control register - reg [ 7:0] txr; // transmit register - wire [ 7:0] rxr; // receive register - reg [ 7:0] cr; // command register - wire [ 7:0] sr; // status register - - // done signal: command completed, clear command register - wire done; - - // core enable signal - wire core_en; - wire ien; - - // status register signals - wire irxack; - reg rxack; // received aknowledge from slave - reg tip; // transfer in progress - reg irq_flag; // interrupt pending flag - wire i2c_busy; // bus busy (start signal detected) - wire i2c_al; // i2c bus arbitration lost - reg al; // status register arbitration lost bit - - // - // module body - // - - // generate internal reset - wire rst_i = arst_i ^ ARST_LVL; - - // generate wishbone signals - wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i; - - // generate acknowledge output signal - always @(posedge wb_clk_i) - wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored - - // assign DAT_O - always @(posedge wb_clk_i) - begin - case (wb_adr_i) // synopsis parallel_case - 3'b000: wb_dat_o <= #1 prer[ 7:0]; - 3'b001: wb_dat_o <= #1 prer[15:8]; - 3'b010: wb_dat_o <= #1 ctr; - 3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr) - 3'b100: wb_dat_o <= #1 sr; // write is command register (cr) - 3'b101: wb_dat_o <= #1 txr; - 3'b110: wb_dat_o <= #1 cr; - 3'b111: wb_dat_o <= #1 0; // reserved - endcase - end - - // generate registers - always @(posedge wb_clk_i or negedge rst_i) - if (!rst_i) - begin - prer <= #1 16'hffff; - ctr <= #1 8'h0; - txr <= #1 8'h0; - end - else if (wb_rst_i) - begin - prer <= #1 16'hffff; - ctr <= #1 8'h0; - txr <= #1 8'h0; - end - else - if (wb_wacc) - case (wb_adr_i) // synopsis parallel_case - 3'b000 : prer [ 7:0] <= #1 wb_dat_i; - 3'b001 : prer [15:8] <= #1 wb_dat_i; - 3'b010 : ctr <= #1 wb_dat_i; - 3'b011 : txr <= #1 wb_dat_i; - default: ; - endcase - - // generate command register (special case) - always @(posedge wb_clk_i or negedge rst_i) - if (~rst_i) - cr <= #1 8'h0; - else if (wb_rst_i) - cr <= #1 8'h0; - else if (wb_wacc) - begin - if (core_en & (wb_adr_i == 3'b100) ) - cr <= #1 wb_dat_i; - end - else - begin - if (done | i2c_al) - cr[7:4] <= #1 4'h0; // clear command bits when done - // or when aribitration lost - cr[2:1] <= #1 2'b0; // reserved bits - cr[0] <= #1 2'b0; // clear IRQ_ACK bit - end - - - // decode command register - wire sta = cr[7]; - wire sto = cr[6]; - wire rd = cr[5]; - wire wr = cr[4]; - wire ack = cr[3]; - wire iack = cr[0]; - - // decode control register - assign core_en = ctr[7]; - assign ien = ctr[6]; - - // hookup byte controller block - i2c_master_byte_ctrl byte_controller ( - .clk ( wb_clk_i ), - .rst ( wb_rst_i ), - .nReset ( rst_i ), - .ena ( core_en ), - .clk_cnt ( prer ), - .start ( sta ), - .stop ( sto ), - .read ( rd ), - .write ( wr ), - .ack_in ( ack ), - .din ( txr ), - .cmd_ack ( done ), - .ack_out ( irxack ), - .dout ( rxr ), - .i2c_busy ( i2c_busy ), - .i2c_al ( i2c_al ), - .scl_i ( scl_pad_i ), - .scl_o ( scl_pad_o ), - .scl_oen ( scl_padoen_o ), - .sda_i ( sda_pad_i ), - .sda_o ( sda_pad_o ), - .sda_oen ( sda_padoen_o ) - ); - - // status register block + interrupt request signal - always @(posedge wb_clk_i or negedge rst_i) - if (!rst_i) - begin - al <= #1 1'b0; - rxack <= #1 1'b0; - tip <= #1 1'b0; - irq_flag <= #1 1'b0; - end - else if (wb_rst_i) - begin - al <= #1 1'b0; - rxack <= #1 1'b0; - tip <= #1 1'b0; - irq_flag <= #1 1'b0; - end - else - begin - al <= #1 i2c_al | (al & ~sta); - rxack <= #1 irxack; - tip <= #1 (rd | wr); - irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated - end - - // generate interrupt request signals - always @(posedge wb_clk_i or negedge rst_i) - if (!rst_i) - wb_inta_o <= #1 1'b0; - else if (wb_rst_i) - wb_inta_o <= #1 1'b0; - else - wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set) - - // assign status register bits - assign sr[7] = rxack; - assign sr[6] = i2c_busy; - assign sr[5] = al; - assign sr[4:2] = 3'h0; // reserved - assign sr[1] = tip; - assign sr[0] = irq_flag; - -endmodule diff --git a/opencores/i2c/rtl/verilog/timescale.v b/opencores/i2c/rtl/verilog/timescale.v deleted file mode 100644 index 60d4ecbd1..000000000 --- a/opencores/i2c/rtl/verilog/timescale.v +++ /dev/null @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - diff --git a/opencores/i2c/rtl/vhdl/CVS/Entries b/opencores/i2c/rtl/vhdl/CVS/Entries deleted file mode 100644 index 2a33278f7..000000000 --- a/opencores/i2c/rtl/vhdl/CVS/Entries +++ /dev/null @@ -1,7 +0,0 @@ -/I2C.VHD/1.1/Mon Sep 24 12:21:51 2001// -/i2c_master_bit_ctrl.vhd/1.14/Wed Oct 11 12:10:13 2006// -/i2c_master_byte_ctrl.vhd/1.5/Wed Feb 18 11:41:48 2004// -/i2c_master_top.vhd/1.7/Sun Mar 14 10:17:03 2004// -/readme/1.2/Sat Nov 30 22:25:47 2002// -/tst_ds1621.vhd/1.1/Mon Sep 24 12:21:51 2001// -D diff --git a/opencores/i2c/rtl/vhdl/CVS/Repository b/opencores/i2c/rtl/vhdl/CVS/Repository deleted file mode 100644 index c210ff4e3..000000000 --- a/opencores/i2c/rtl/vhdl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/rtl/vhdl diff --git a/opencores/i2c/rtl/vhdl/CVS/Root b/opencores/i2c/rtl/vhdl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/rtl/vhdl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/rtl/vhdl/CVS/Template b/opencores/i2c/rtl/vhdl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/rtl/vhdl/I2C.VHD b/opencores/i2c/rtl/vhdl/I2C.VHD deleted file mode 100644 index 64d1eb656..000000000 --- a/opencores/i2c/rtl/vhdl/I2C.VHD +++ /dev/null @@ -1,620 +0,0 @@ --- --- Simple I2C controller --- --- 1) No multimaster --- 2) No slave mode --- 3) No fifo's --- --- notes: --- Every command is acknowledged. Do not set a new command before previous is acknowledged. --- Dout is available 1 clock cycle later as cmd_ack --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -package I2C is - component simple_i2c is - port ( - clk : in std_logic; - ena : in std_logic; - nReset : in std_logic; - - clk_cnt : in unsigned(7 downto 0); -- 4x SCL - - -- input signals - start, - stop, - read, - write, - ack_in : std_logic; - Din : in std_logic_vector(7 downto 0); - - -- output signals - cmd_ack : out std_logic; - ack_out : out std_logic; - Dout : out std_logic_vector(7 downto 0); - - -- i2c signals - SCL : inout std_logic; - SDA : inout std_logic - ); - end component simple_i2c; -end package I2C; - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity simple_i2c is - port ( - clk : in std_logic; - ena : in std_logic; - nReset : in std_logic; - - clk_cnt : in unsigned(7 downto 0); -- 4x SCL - - -- input signals - start, - stop, - read, - write, - ack_in : std_logic; - Din : in std_logic_vector(7 downto 0); - - -- output signals - cmd_ack : out std_logic; - ack_out : out std_logic; - Dout : out std_logic_vector(7 downto 0); - - -- i2c signals - SCL : inout std_logic; - SDA : inout std_logic - ); -end entity simple_i2c; - -architecture structural of simple_i2c is - component i2c_core is - port ( - clk : in std_logic; - nReset : in std_logic; - - clk_cnt : in unsigned(7 downto 0); - - cmd : in std_logic_vector(2 downto 0); - cmd_ack : out std_logic; - busy : out std_logic; - - Din : in std_logic; - Dout : out std_logic; - - SCL : inout std_logic; - SDA : inout std_logic - ); - end component i2c_core; - - -- commands for i2c_core - constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; - constant CMD_START : std_logic_vector(2 downto 0) := "010"; - constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; - constant CMD_READ : std_logic_vector(2 downto 0) := "100"; - constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; - - -- signals for i2c_core - signal core_cmd : std_logic_vector(2 downto 0); - signal core_ack, core_busy, core_txd, core_rxd : std_logic; - - -- signals for shift register - signal sr : std_logic_vector(7 downto 0); -- 8bit shift register - signal shift, ld : std_logic; - - -- signals for state machine - signal go, host_ack : std_logic; -begin - -- hookup i2c core - u1: i2c_core port map (clk, nReset, clk_cnt, core_cmd, core_ack, core_busy, core_txd, core_rxd, SCL, SDA); - - -- generate host-command-acknowledge - cmd_ack <= host_ack; - - -- generate go-signal - go <= (read or write) and not host_ack; - - -- assign Dout output to shift-register - Dout <= sr; - - -- assign ack_out output to core_rxd (contains last received bit) - ack_out <= core_rxd; - - -- generate shift register - shift_register: process(clk) - begin - if (clk'event and clk = '1') then - if (ld = '1') then - sr <= din; - elsif (shift = '1') then - sr <= (sr(6 downto 0) & core_rxd); - end if; - end if; - end process shift_register; - - -- - -- state machine - -- - statemachine : block - type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); - signal state : states; - signal dcnt : unsigned(2 downto 0); - begin - -- - -- command interpreter, translate complex commands into simpler I2C commands - -- - nxt_state_decoder: process(clk, nReset, state) - variable nxt_state : states; - variable idcnt : unsigned(2 downto 0); - variable ihost_ack : std_logic; - variable icore_cmd : std_logic_vector(2 downto 0); - variable icore_txd : std_logic; - variable ishift, iload : std_logic; - begin - -- 8 databits (1byte) of data to shift-in/out - idcnt := dcnt; - - -- no acknowledge (until command complete) - ihost_ack := '0'; - - icore_txd := core_txd; - - -- keep current command to i2c_core - icore_cmd := core_cmd; - - -- no shifting or loading of shift-register - ishift := '0'; - iload := '0'; - - -- keep current state; - nxt_state := state; - case state is - when st_idle => - if (go = '1') then - if (start = '1') then - nxt_state := st_start; - icore_cmd := CMD_START; - elsif (read = '1') then - nxt_state := st_read; - icore_cmd := CMD_READ; - idcnt := "111"; - else - nxt_state := st_write; - icore_cmd := CMD_WRITE; - idcnt := "111"; - iload := '1'; - end if; - end if; - - when st_start => - if (core_ack = '1') then - if (read = '1') then - nxt_state := st_read; - icore_cmd := CMD_READ; - idcnt := "111"; - else - nxt_state := st_write; - icore_cmd := CMD_WRITE; - idcnt := "111"; - iload := '1'; - end if; - end if; - - when st_write => - if (core_ack = '1') then - idcnt := dcnt -1; -- count down Data_counter - icore_txd := sr(7); - if (dcnt = 0) then - nxt_state := st_ack; - icore_cmd := CMD_READ; - else - ishift := '1'; --- icore_txd := sr(7); - end if; - end if; - - when st_read => - if (core_ack = '1') then - idcnt := dcnt -1; -- count down Data_counter - ishift := '1'; - if (dcnt = 0) then - nxt_state := st_ack; - icore_cmd := CMD_WRITE; - icore_txd := ack_in; - end if; - end if; - - when st_ack => - if (core_ack = '1') then - -- generate command acknowledge signal - ihost_ack := '1'; - - -- Perform an additional shift, needed for 'read' (store last received bit in shift register) - ishift := '1'; - - -- check for stop; Should a STOP command be generated ? - if (stop = '1') then - nxt_state := st_stop; - icore_cmd := CMD_STOP; - else - nxt_state := st_idle; - icore_cmd := CMD_NOP; - end if; - end if; - - when st_stop => - if (core_ack = '1') then - nxt_state := st_idle; - icore_cmd := CMD_NOP; - end if; - - when others => -- illegal states - nxt_state := st_idle; - icore_cmd := CMD_NOP; - end case; - - -- generate registers - if (nReset = '0') then - core_cmd <= CMD_NOP; - core_txd <= '0'; - - shift <= '0'; - ld <= '0'; - - dcnt <= "111"; - host_ack <= '0'; - - state <= st_idle; - elsif (clk'event and clk = '1') then - if (ena = '1') then - state <= nxt_state; - - dcnt <= idcnt; - shift <= ishift; - ld <= iload; - - core_cmd <= icore_cmd; - core_txd <= icore_txd; - - host_ack <= ihost_ack; - end if; - end if; - end process nxt_state_decoder; - - end block statemachine; - -end architecture structural; - - --- --- --- I2C Core --- --- Translate simple commands into SCL/SDA transitions --- Each command has 5 states, A/B/C/D/idle --- --- start: SCL ~~~~~~~~~~\____ --- SDA ~~~~~~~~\______ --- x | A | B | C | D | i --- --- repstart SCL ____/~~~~\___ --- SDA __/~~~\______ --- x | A | B | C | D | i --- --- stop SCL ____/~~~~~~~~ --- SDA ==\____/~~~~~ --- x | A | B | C | D | i --- ---- write SCL ____/~~~~\____ --- SDA ==X=========X= --- x | A | B | C | D | i --- ---- read SCL ____/~~~~\____ --- SDA XXXX=====XXXX --- x | A | B | C | D | i --- - --- Timing: Normal mode Fast mode ------------------------------------------------------------------ --- Fscl 100KHz 400KHz --- Th_scl 4.0us 0.6us High period of SCL --- Tl_scl 4.7us 1.3us Low period of SCL --- Tsu:sta 4.7us 0.6us setup time for a repeated start condition --- Tsu:sto 4.0us 0.6us setup time for a stop conditon --- Tbuf 4.7us 1.3us Bus free time between a stop and start condition --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity i2c_core is - port ( - clk : in std_logic; - nReset : in std_logic; - - clk_cnt : in unsigned(7 downto 0); - - cmd : in std_logic_vector(2 downto 0); - cmd_ack : out std_logic; - busy : out std_logic; - - Din : in std_logic; - Dout : out std_logic; - - SCL : inout std_logic; - SDA : inout std_logic - ); -end entity i2c_core; - -architecture structural of i2c_core is - constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; - constant CMD_START : std_logic_vector(2 downto 0) := "010"; - constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; - constant CMD_READ : std_logic_vector(2 downto 0) := "100"; - constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; - - type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); - signal state : cmds; - signal SDAo, SCLo : std_logic; - signal txd : std_logic; - signal clk_en, slave_wait :std_logic; - signal cnt : unsigned(7 downto 0) := clk_cnt; -begin - -- whenever the slave is not ready it can delay the cycle by pulling SCL low - slave_wait <= '1' when ((SCLo = '1') and (SCL = '0')) else '0'; - - -- generate clk enable signal - gen_clken: process(clk, nReset) - begin - if (nReset = '0') then - cnt <= (others => '0'); - clk_en <= '1'; --'0'; - elsif (clk'event and clk = '1') then - if (cnt = 0) then - clk_en <= '1'; - cnt <= clk_cnt; - else - if (slave_wait = '0') then - cnt <= cnt -1; - end if; - clk_en <= '0'; - end if; - end if; - end process gen_clken; - - -- generate statemachine - nxt_state_decoder : process (clk, nReset, state, cmd, SDA) - variable nxt_state : cmds; - variable icmd_ack, ibusy, store_sda : std_logic; - variable itxd : std_logic; - begin - - nxt_state := state; - - icmd_ack := '0'; -- default no acknowledge - ibusy := '1'; -- default busy - - store_sda := '0'; - - itxd := txd; - - case (state) is - -- idle - when idle => - case cmd is - when CMD_START => - nxt_state := start_a; - icmd_ack := '1'; -- command completed - - when CMD_STOP => - nxt_state := stop_a; - icmd_ack := '1'; -- command completed - - when CMD_WRITE => - nxt_state := wr_a; - icmd_ack := '1'; -- command completed - itxd := Din; - - when CMD_READ => - nxt_state := rd_a; - icmd_ack := '1'; -- command completed - - when others => - nxt_state := idle; --- don't acknowledge NOP command icmd_ack := '1'; -- command completed - ibusy := '0'; - end case; - - -- start - when start_a => - nxt_state := start_b; - - when start_b => - nxt_state := start_c; - - when start_c => - nxt_state := start_d; - - when start_d => - nxt_state := idle; - ibusy := '0'; -- not busy when idle - - - -- stop - when stop_a => - nxt_state := stop_b; - - when stop_b => - nxt_state := stop_c; - - when stop_c => --- nxt_state := stop_d; - --- when stop_d => - nxt_state := idle; - ibusy := '0'; -- not busy when idle - - -- read - when rd_a => - nxt_state := rd_b; - - when rd_b => - nxt_state := rd_c; - - when rd_c => - nxt_state := rd_d; - store_sda := '1'; - - when rd_d => - nxt_state := idle; - ibusy := '0'; -- not busy when idle - - -- write - when wr_a => - nxt_state := wr_b; - - when wr_b => - nxt_state := wr_c; - - when wr_c => - nxt_state := wr_d; - - when wr_d => - nxt_state := idle; - ibusy := '0'; -- not busy when idle - - end case; - - -- generate regs - if (nReset = '0') then - state <= idle; - cmd_ack <= '0'; - busy <= '0'; - txd <= '0'; - Dout <= '0'; - elsif (clk'event and clk = '1') then - if (clk_en = '1') then - state <= nxt_state; - busy <= ibusy; - - txd <= itxd; - if (store_sda = '1') then - Dout <= SDA; - end if; - end if; - - cmd_ack <= icmd_ack and clk_en; - end if; - end process nxt_state_decoder; - - -- - -- convert states to SCL and SDA signals - -- - output_decoder: process (clk, nReset, state) - variable iscl, isda : std_logic; - begin - case (state) is - when idle => - iscl := SCLo; -- keep SCL in same state - isda := SDA; -- keep SDA in same state - - -- start - when start_a => - iscl := SCLo; -- keep SCL in same state (for repeated start) - isda := '1'; -- set SDA high - - when start_b => - iscl := '1'; -- set SCL high - isda := '1'; -- keep SDA high - - when start_c => - iscl := '1'; -- keep SCL high - isda := '0'; -- sel SDA low - - when start_d => - iscl := '0'; -- set SCL low - isda := '0'; -- keep SDA low - - -- stop - when stop_a => - iscl := '0'; -- keep SCL disabled - isda := '0'; -- set SDA low - - when stop_b => - iscl := '1'; -- set SCL high - isda := '0'; -- keep SDA low - - when stop_c => - iscl := '1'; -- keep SCL high - isda := '1'; -- set SDA high - - -- write - when wr_a => - iscl := '0'; -- keep SCL low --- isda := txd; -- set SDA - isda := Din; - - when wr_b => - iscl := '1'; -- set SCL high --- isda := txd; -- set SDA - isda := Din; - - when wr_c => - iscl := '1'; -- keep SCL high --- isda := txd; -- set SDA - isda := Din; - - when wr_d => - iscl := '0'; -- set SCL low --- isda := txd; -- set SDA - isda := Din; - - -- read - when rd_a => - iscl := '0'; -- keep SCL low - isda := '1'; -- tri-state SDA - - when rd_b => - iscl := '1'; -- set SCL high - isda := '1'; -- tri-state SDA - - when rd_c => - iscl := '1'; -- keep SCL high - isda := '1'; -- tri-state SDA - - when rd_d => - iscl := '0'; -- set SCL low - isda := '1'; -- tri-state SDA - end case; - - -- generate registers - if (nReset = '0') then - SCLo <= '1'; - SDAo <= '1'; - elsif (clk'event and clk = '1') then - if (clk_en = '1') then - SCLo <= iscl; - SDAo <= isda; - end if; - end if; - end process output_decoder; - - SCL <= '0' when (SCLo = '0') else 'Z'; -- since SCL is externally pulled-up convert a '1' to a 'Z'(tri-state) - SDA <= '0' when (SDAo = '0') else 'Z'; -- since SDA is externally pulled-up convert a '1' to a 'Z'(tri-state) --- SCL <= SCLo; --- SDA <= SDAo; - -end architecture structural; - - - - diff --git a/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd b/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd deleted file mode 100644 index 1b8eb96d2..000000000 --- a/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd +++ /dev/null @@ -1,495 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- WISHBONE revB2 I2C Master Core; bit-controller ---- ----- ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ----- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2000 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- CVS Log --- --- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $ --- --- $Date: 2006/10/11 12:10:13 $ --- $Revision: 1.14 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: i2c_master_bit_ctrl.vhd,v $ --- Revision 1.14 2006/10/11 12:10:13 rherveille --- Added missing semicolons ';' on endif --- --- Revision 1.13 2006/10/06 10:48:24 rherveille --- fixed short scl high pulse after clock stretch --- --- Revision 1.12 2004/05/07 11:53:31 rherveille --- Fixed previous fix :) Made a variable vs signal mistake. --- --- Revision 1.11 2004/05/07 11:04:00 rherveille --- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. --- --- Revision 1.10 2004/02/27 07:49:43 rherveille --- Fixed a bug in the arbitration-lost signal generation. VHDL version only. --- --- Revision 1.9 2003/08/12 14:48:37 rherveille --- Forgot an 'end if' :-/ --- --- Revision 1.8 2003/08/09 07:01:13 rherveille --- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. --- Fixed a potential bug in the byte controller's host-acknowledge generation. --- --- Revision 1.7 2003/02/05 00:06:02 rherveille --- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. --- --- Revision 1.6 2003/02/01 02:03:06 rherveille --- Fixed a few 'arbitration lost' bugs. VHDL version only. --- --- Revision 1.5 2002/12/26 16:05:47 rherveille --- Core is now a Multimaster I2C controller. --- --- Revision 1.4 2002/11/30 22:24:37 rherveille --- Cleaned up code --- --- Revision 1.3 2002/10/30 18:09:53 rherveille --- Fixed some reported minor start/stop generation timing issuess. --- --- Revision 1.2 2002/06/15 07:37:04 rherveille --- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. --- --- Revision 1.1 2001/11/05 12:02:33 rherveille --- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. --- Code updated, is now up-to-date to doc. rev.0.4. --- Added headers. --- - - --- -------------------------------------- --- Bit controller section ------------------------------------- --- --- Translate simple commands into SCL/SDA transitions --- Each command has 5 states, A/B/C/D/idle --- --- start: SCL ~~~~~~~~~~~~~~\____ --- SDA XX/~~~~~~~\______ --- x | A | B | C | D | i --- --- repstart SCL ______/~~~~~~~\___ --- SDA __/~~~~~~~\______ --- x | A | B | C | D | i --- --- stop SCL _______/~~~~~~~~~~~ --- SDA ==\___________/~~~~~ --- x | A | B | C | D | i --- ---- write SCL ______/~~~~~~~\____ --- SDA XXX===============XX --- x | A | B | C | D | i --- ---- read SCL ______/~~~~~~~\____ --- SDA XXXXXXX=XXXXXXXXXXX --- x | A | B | C | D | i --- - --- Timing: Normal mode Fast mode ------------------------------------------------------------------ --- Fscl 100KHz 400KHz --- Th_scl 4.0us 0.6us High period of SCL --- Tl_scl 4.7us 1.3us Low period of SCL --- Tsu:sta 4.7us 0.6us setup time for a repeated start condition --- Tsu:sto 4.0us 0.6us setup time for a stop conditon --- Tbuf 4.7us 1.3us Bus free time between a stop and start condition --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity i2c_master_bit_ctrl is - port ( - clk : in std_logic; - rst : in std_logic; - nReset : in std_logic; - ena : in std_logic; -- core enable signal - - clk_cnt : in unsigned(15 downto 0); -- clock prescale value - - cmd : in std_logic_vector(3 downto 0); - cmd_ack : out std_logic; -- command completed - busy : out std_logic; -- i2c bus busy - al : out std_logic; -- arbitration lost - - din : in std_logic; - dout : out std_logic; - - -- i2c lines - scl_i : in std_logic; -- i2c clock line input - scl_o : out std_logic; -- i2c clock line output - scl_oen : out std_logic; -- i2c clock line output enable, active low - sda_i : in std_logic; -- i2c data line input - sda_o : out std_logic; -- i2c data line output - sda_oen : out std_logic -- i2c data line output enable, active low - ); -end entity i2c_master_bit_ctrl; - -architecture structural of i2c_master_bit_ctrl is - constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; - constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; - constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; - constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; - constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; - - type states is (idle, start_a, start_b, start_c, start_d, start_e, - stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); - signal c_state : states; - - signal iscl_oen, isda_oen : std_logic; -- internal I2C lines - signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) - signal dscl_oen : std_logic; -- delayed scl_oen signals - signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs - signal clk_en, slave_wait : std_logic; -- clock generation signals - signal ial : std_logic; -- internal arbitration lost signal --- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation) - signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) - -begin - -- whenever the slave is not ready it can delay the cycle by pulling SCL low - -- delay scl_oen - process (clk) - begin - if (clk'event and clk = '1') then - dscl_oen <= iscl_oen; - end if; - end process; - slave_wait <= dscl_oen and not sSCL; - - -- generate clk enable signal - gen_clken: process(clk, nReset) - begin - if (nReset = '0') then - cnt <= (others => '0'); - clk_en <= '1'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - cnt <= (others => '0'); - clk_en <= '1'; - elsif ( (cnt = 0) or (ena = '0') ) then - cnt <= clk_cnt; - clk_en <= '1'; - elsif (slave_wait = '1') then - cnt <= cnt; - clk_en <= '0'; - else - cnt <= cnt -1; - clk_en <= '0'; - end if; - end if; - end process gen_clken; - - - -- generate bus status controller - bus_status_ctrl: block - signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA - signal sta_condition : std_logic; -- start detected - signal sto_condition : std_logic; -- stop detected - signal cmd_stop : std_logic; -- STOP command - signal ibusy : std_logic; -- internal busy signal - begin - -- synchronize SCL and SDA inputs - synch_scl_sda: process(clk, nReset) - begin - if (nReset = '0') then - sSCL <= '1'; - sSDA <= '1'; - - dSCL <= '1'; - dSDA <= '1'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - sSCL <= '1'; - sSDA <= '1'; - - dSCL <= '1'; - dSDA <= '1'; - else - sSCL <= scl_i; - sSDA <= sda_i; - - dSCL <= sSCL; - dSDA <= sSDA; - end if; - end if; - end process synch_SCL_SDA; - - -- detect start condition => detect falling edge on SDA while SCL is high - -- detect stop condition => detect rising edge on SDA while SCL is high - detect_sta_sto: process(clk, nReset) - begin - if (nReset = '0') then - sta_condition <= '0'; - sto_condition <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - sta_condition <= '0'; - sto_condition <= '0'; - else - sta_condition <= (not sSDA and dSDA) and sSCL; - sto_condition <= (sSDA and not dSDA) and sSCL; - end if; - end if; - end process detect_sta_sto; - - -- generate i2c-bus busy signal - gen_busy: process(clk, nReset) - begin - if (nReset = '0') then - ibusy <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - ibusy <= '0'; - else - ibusy <= (sta_condition or ibusy) and not sto_condition; - end if; - end if; - end process gen_busy; - busy <= ibusy; - - - -- generate arbitration lost signal - -- aribitration lost when: - -- 1) master drives SDA high, but the i2c bus is low - -- 2) stop detected while not requested (detect during 'idle' state) - gen_al: process(clk, nReset) - begin - if (nReset = '0') then - cmd_stop <= '0'; - ial <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - cmd_stop <= '0'; - ial <= '0'; - else - if (clk_en = '1') then - if (cmd = I2C_CMD_STOP) then - cmd_stop <= '1'; - else - cmd_stop <= '0'; - end if; - end if; - - if (c_state = idle) then - ial <= (sda_chk and not sSDA and isda_oen); - else - ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop); - end if; - - end if; - end if; - end process gen_al; - al <= ial; - - -- generate dout signal, store dout on rising edge of SCL - gen_dout: process(clk) - begin - if (clk'event and clk = '1') then - if (sSCL = '1' and dSCL = '0') then - dout <= sSDA; - end if; - end if; - end process gen_dout; - end block bus_status_ctrl; - - - -- generate statemachine - nxt_state_decoder : process (clk, nReset, c_state, cmd) - begin - if (nReset = '0') then - c_state <= idle; - cmd_ack <= '0'; - iscl_oen <= '1'; - isda_oen <= '1'; - sda_chk <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1' or ial = '1') then - c_state <= idle; - cmd_ack <= '0'; - iscl_oen <= '1'; - isda_oen <= '1'; - sda_chk <= '0'; - else - cmd_ack <= '0'; -- default no acknowledge - - if (clk_en = '1') then - case (c_state) is - -- idle - when idle => - case cmd is - when I2C_CMD_START => c_state <= start_a; - when I2C_CMD_STOP => c_state <= stop_a; - when I2C_CMD_WRITE => c_state <= wr_a; - when I2C_CMD_READ => c_state <= rd_a; - when others => c_state <= idle; -- NOP command - end case; - - iscl_oen <= iscl_oen; -- keep SCL in same state - isda_oen <= isda_oen; -- keep SDA in same state - sda_chk <= '0'; -- don't check SDA - - -- start - when start_a => - c_state <= start_b; - iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start) - isda_oen <= '1'; -- set SDA high - sda_chk <= '0'; -- don't check SDA - - when start_b => - c_state <= start_c; - iscl_oen <= '1'; -- set SCL high - isda_oen <= '1'; -- keep SDA high - sda_chk <= '0'; -- don't check SDA - - when start_c => - c_state <= start_d; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '0'; -- set SDA low - sda_chk <= '0'; -- don't check SDA - - when start_d => - c_state <= start_e; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '0'; -- keep SDA low - sda_chk <= '0'; -- don't check SDA - - when start_e => - c_state <= idle; - cmd_ack <= '1'; -- command completed - iscl_oen <= '0'; -- set SCL low - isda_oen <= '0'; -- keep SDA low - sda_chk <= '0'; -- don't check SDA - - -- stop - when stop_a => - c_state <= stop_b; - iscl_oen <= '0'; -- keep SCL low - isda_oen <= '0'; -- set SDA low - sda_chk <= '0'; -- don't check SDA - - when stop_b => - c_state <= stop_c; - iscl_oen <= '1'; -- set SCL high - isda_oen <= '0'; -- keep SDA low - sda_chk <= '0'; -- don't check SDA - - when stop_c => - c_state <= stop_d; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '0'; -- keep SDA low - sda_chk <= '0'; -- don't check SDA - - when stop_d => - c_state <= idle; - cmd_ack <= '1'; -- command completed - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '1'; -- set SDA high - sda_chk <= '0'; -- don't check SDA - - -- read - when rd_a => - c_state <= rd_b; - iscl_oen <= '0'; -- keep SCL low - isda_oen <= '1'; -- tri-state SDA - sda_chk <= '0'; -- don't check SDA - - when rd_b => - c_state <= rd_c; - iscl_oen <= '1'; -- set SCL high - isda_oen <= '1'; -- tri-state SDA - sda_chk <= '0'; -- don't check SDA - - when rd_c => - c_state <= rd_d; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= '1'; -- tri-state SDA - sda_chk <= '0'; -- don't check SDA - - when rd_d => - c_state <= idle; - cmd_ack <= '1'; -- command completed - iscl_oen <= '0'; -- set SCL low - isda_oen <= '1'; -- tri-state SDA - sda_chk <= '0'; -- don't check SDA - - -- write - when wr_a => - c_state <= wr_b; - iscl_oen <= '0'; -- keep SCL low - isda_oen <= din; -- set SDA - sda_chk <= '0'; -- don't check SDA (SCL low) - - when wr_b => - c_state <= wr_c; - iscl_oen <= '1'; -- set SCL high - isda_oen <= din; -- keep SDA - sda_chk <= '1'; -- check SDA - - when wr_c => - c_state <= wr_d; - iscl_oen <= '1'; -- keep SCL high - isda_oen <= din; -- keep SDA - sda_chk <= '1'; -- check SDA - - when wr_d => - c_state <= idle; - cmd_ack <= '1'; -- command completed - iscl_oen <= '0'; -- set SCL low - isda_oen <= din; -- keep SDA - sda_chk <= '0'; -- don't check SDA (SCL low) - - when others => - - end case; - end if; - end if; - end if; - end process nxt_state_decoder; - - - -- assign outputs - scl_o <= '0'; - scl_oen <= iscl_oen; - sda_o <= '0'; - sda_oen <= isda_oen; -end architecture structural; - diff --git a/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd b/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd deleted file mode 100644 index bdb2a881e..000000000 --- a/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd +++ /dev/null @@ -1,370 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- ----- ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ----- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2000 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- CVS Log --- --- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $ --- --- $Date: 2004/02/18 11:41:48 $ --- $Revision: 1.5 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: i2c_master_byte_ctrl.vhd,v $ --- Revision 1.5 2004/02/18 11:41:48 rherveille --- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. --- --- Revision 1.4 2003/08/09 07:01:13 rherveille --- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. --- Fixed a potential bug in the byte controller's host-acknowledge generation. --- --- Revision 1.3 2002/12/26 16:05:47 rherveille --- Core is now a Multimaster I2C controller. --- --- Revision 1.2 2002/11/30 22:24:37 rherveille --- Cleaned up code --- --- Revision 1.1 2001/11/05 12:02:33 rherveille --- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. --- Code updated, is now up-to-date to doc. rev.0.4. --- Added headers. --- - - - - --- ------------------------------------------- --- Byte controller section ------------------------------------------- --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity i2c_master_byte_ctrl is - port ( - clk : in std_logic; - rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) - nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) - ena : in std_logic; -- core enable signal - - clk_cnt : in unsigned(15 downto 0); -- 4x SCL - - -- input signals - start, - stop, - read, - write, - ack_in : std_logic; - din : in std_logic_vector(7 downto 0); - - -- output signals - cmd_ack : out std_logic; -- command done - ack_out : out std_logic; - i2c_busy : out std_logic; -- arbitration lost - i2c_al : out std_logic; -- i2c bus busy - dout : out std_logic_vector(7 downto 0); - - -- i2c lines - scl_i : in std_logic; -- i2c clock line input - scl_o : out std_logic; -- i2c clock line output - scl_oen : out std_logic; -- i2c clock line output enable, active low - sda_i : in std_logic; -- i2c data line input - sda_o : out std_logic; -- i2c data line output - sda_oen : out std_logic -- i2c data line output enable, active low - ); -end entity i2c_master_byte_ctrl; - -architecture structural of i2c_master_byte_ctrl is - component i2c_master_bit_ctrl is - port ( - clk : in std_logic; - rst : in std_logic; - nReset : in std_logic; - ena : in std_logic; -- core enable signal - - clk_cnt : in unsigned(15 downto 0); -- clock prescale value - - cmd : in std_logic_vector(3 downto 0); - cmd_ack : out std_logic; -- command done - busy : out std_logic; -- i2c bus busy - al : out std_logic; -- arbitration lost - - din : in std_logic; - dout : out std_logic; - - -- i2c lines - scl_i : in std_logic; -- i2c clock line input - scl_o : out std_logic; -- i2c clock line output - scl_oen : out std_logic; -- i2c clock line output enable, active low - sda_i : in std_logic; -- i2c data line input - sda_o : out std_logic; -- i2c data line output - sda_oen : out std_logic -- i2c data line output enable, active low - ); - end component i2c_master_bit_ctrl; - - -- commands for bit_controller block - constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; - constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; - constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; - constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; - constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; - - -- signals for bit_controller - signal core_cmd : std_logic_vector(3 downto 0); - signal core_ack, core_txd, core_rxd : std_logic; - signal al : std_logic; - - -- signals for shift register - signal sr : std_logic_vector(7 downto 0); -- 8bit shift register - signal shift, ld : std_logic; - - -- signals for state machine - signal go, host_ack : std_logic; - signal dcnt : unsigned(2 downto 0); -- data counter - signal cnt_done : std_logic; - -begin - -- hookup bit_controller - bit_ctrl: i2c_master_bit_ctrl port map( - clk => clk, - rst => rst, - nReset => nReset, - ena => ena, - clk_cnt => clk_cnt, - cmd => core_cmd, - cmd_ack => core_ack, - busy => i2c_busy, - al => al, - din => core_txd, - dout => core_rxd, - scl_i => scl_i, - scl_o => scl_o, - scl_oen => scl_oen, - sda_i => sda_i, - sda_o => sda_o, - sda_oen => sda_oen - ); - i2c_al <= al; - - -- generate host-command-acknowledge - cmd_ack <= host_ack; - - -- generate go-signal - go <= (read or write or stop) and not host_ack; - - -- assign Dout output to shift-register - dout <= sr; - - -- generate shift register - shift_register: process(clk, nReset) - begin - if (nReset = '0') then - sr <= (others => '0'); - elsif (clk'event and clk = '1') then - if (rst = '1') then - sr <= (others => '0'); - elsif (ld = '1') then - sr <= din; - elsif (shift = '1') then - sr <= (sr(6 downto 0) & core_rxd); - end if; - end if; - end process shift_register; - - -- generate data-counter - data_cnt: process(clk, nReset) - begin - if (nReset = '0') then - dcnt <= (others => '0'); - elsif (clk'event and clk = '1') then - if (rst = '1') then - dcnt <= (others => '0'); - elsif (ld = '1') then - dcnt <= (others => '1'); -- load counter with 7 - elsif (shift = '1') then - dcnt <= dcnt -1; - end if; - end if; - end process data_cnt; - - cnt_done <= '1' when (dcnt = 0) else '0'; - - -- - -- state machine - -- - statemachine : block - type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); - signal c_state : states; - begin - -- - -- command interpreter, translate complex commands into simpler I2C commands - -- - nxt_state_decoder: process(clk, nReset) - begin - if (nReset = '0') then - core_cmd <= I2C_CMD_NOP; - core_txd <= '0'; - shift <= '0'; - ld <= '0'; - host_ack <= '0'; - c_state <= st_idle; - ack_out <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1' or al = '1') then - core_cmd <= I2C_CMD_NOP; - core_txd <= '0'; - shift <= '0'; - ld <= '0'; - host_ack <= '0'; - c_state <= st_idle; - ack_out <= '0'; - else - -- initialy reset all signal - core_txd <= sr(7); - shift <= '0'; - ld <= '0'; - host_ack <= '0'; - - case c_state is - when st_idle => - if (go = '1') then - if (start = '1') then - c_state <= st_start; - core_cmd <= I2C_CMD_START; - elsif (read = '1') then - c_state <= st_read; - core_cmd <= I2C_CMD_READ; - elsif (write = '1') then - c_state <= st_write; - core_cmd <= I2C_CMD_WRITE; - else -- stop - c_state <= st_stop; - core_cmd <= I2C_CMD_STOP; - end if; - - ld <= '1'; - end if; - - when st_start => - if (core_ack = '1') then - if (read = '1') then - c_state <= st_read; - core_cmd <= I2C_CMD_READ; - else - c_state <= st_write; - core_cmd <= I2C_CMD_WRITE; - end if; - - ld <= '1'; - end if; - - when st_write => - if (core_ack = '1') then - if (cnt_done = '1') then - c_state <= st_ack; - core_cmd <= I2C_CMD_READ; - else - c_state <= st_write; -- stay in same state - core_cmd <= I2C_CMD_WRITE; -- write next bit - shift <= '1'; - end if; - end if; - - when st_read => - if (core_ack = '1') then - if (cnt_done = '1') then - c_state <= st_ack; - core_cmd <= I2C_CMD_WRITE; - else - c_state <= st_read; -- stay in same state - core_cmd <= I2C_CMD_READ; -- read next bit - end if; - - shift <= '1'; - core_txd <= ack_in; - end if; - - when st_ack => - if (core_ack = '1') then - -- check for stop; Should a STOP command be generated ? - if (stop = '1') then - c_state <= st_stop; - core_cmd <= I2C_CMD_STOP; - else - c_state <= st_idle; - core_cmd <= I2C_CMD_NOP; - - -- generate command acknowledge signal - host_ack <= '1'; - end if; - - -- assign ack_out output to core_rxd (contains last received bit) - ack_out <= core_rxd; - - core_txd <= '1'; - else - core_txd <= ack_in; - end if; - - when st_stop => - if (core_ack = '1') then - c_state <= st_idle; - core_cmd <= I2C_CMD_NOP; - - -- generate command acknowledge signal - host_ack <= '1'; - end if; - - when others => -- illegal states - c_state <= st_idle; - core_cmd <= I2C_CMD_NOP; - report ("Byte controller entered illegal state."); - - end case; - - end if; - end if; - end process nxt_state_decoder; - - end block statemachine; - -end architecture structural; - diff --git a/opencores/i2c/rtl/vhdl/i2c_master_top.vhd b/opencores/i2c/rtl/vhdl/i2c_master_top.vhd deleted file mode 100644 index a2557120f..000000000 --- a/opencores/i2c/rtl/vhdl/i2c_master_top.vhd +++ /dev/null @@ -1,359 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- WISHBONE revB2 compl. I2C Master Core; top level ---- ----- ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ----- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2000 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- CVS Log --- --- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $ --- --- $Date: 2004/03/14 10:17:03 $ --- $Revision: 1.7 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: i2c_master_top.vhd,v $ --- Revision 1.7 2004/03/14 10:17:03 rherveille --- Fixed simulation issue when writing to CR register --- --- Revision 1.6 2003/08/09 07:01:13 rherveille --- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. --- Fixed a potential bug in the byte controller's host-acknowledge generation. --- --- Revision 1.5 2003/02/01 02:03:06 rherveille --- Fixed a few 'arbitration lost' bugs. VHDL version only. --- --- Revision 1.4 2002/12/26 16:05:47 rherveille --- Core is now a Multimaster I2C controller. --- --- Revision 1.3 2002/11/30 22:24:37 rherveille --- Cleaned up code --- --- Revision 1.2 2001/11/10 10:52:44 rherveille --- Changed PRER reset value from 0x0000 to 0xffff, conform specs. --- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity i2c_master_top is - generic( - ARST_LVL : std_logic := '0' -- asynchronous reset level - ); - port ( - -- wishbone signals - wb_clk_i : in std_logic; -- master clock input - wb_rst_i : in std_logic := '0'; -- synchronous active high reset - arst_i : in std_logic := not ARST_LVL; -- asynchronous reset - wb_adr_i : in unsigned(2 downto 0); -- lower address bits - wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input - wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output - wb_we_i : in std_logic; -- Write enable input - wb_stb_i : in std_logic; -- Strobe signals / core select signal - wb_cyc_i : in std_logic; -- Valid bus cycle input - wb_ack_o : out std_logic; -- Bus cycle acknowledge output - wb_inta_o : out std_logic; -- interrupt request output signal - - -- i2c lines - scl_pad_i : in std_logic; -- i2c clock line input - scl_pad_o : out std_logic; -- i2c clock line output - scl_padoen_o : out std_logic; -- i2c clock line output enable, active low - sda_pad_i : in std_logic; -- i2c data line input - sda_pad_o : out std_logic; -- i2c data line output - sda_padoen_o : out std_logic -- i2c data line output enable, active low - ); -end entity i2c_master_top; - -architecture structural of i2c_master_top is - component i2c_master_byte_ctrl is - port ( - clk : in std_logic; - rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) - nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) - ena : in std_logic; -- core enable signal - - clk_cnt : in unsigned(15 downto 0); -- 4x SCL - - -- input signals - start, - stop, - read, - write, - ack_in : std_logic; - din : in std_logic_vector(7 downto 0); - - -- output signals - cmd_ack : out std_logic; - ack_out : out std_logic; - i2c_busy : out std_logic; - i2c_al : out std_logic; - dout : out std_logic_vector(7 downto 0); - - -- i2c lines - scl_i : in std_logic; -- i2c clock line input - scl_o : out std_logic; -- i2c clock line output - scl_oen : out std_logic; -- i2c clock line output enable, active low - sda_i : in std_logic; -- i2c data line input - sda_o : out std_logic; -- i2c data line output - sda_oen : out std_logic -- i2c data line output enable, active low - ); - end component i2c_master_byte_ctrl; - - -- registers - signal prer : unsigned(15 downto 0); -- clock prescale register - signal ctr : std_logic_vector(7 downto 0); -- control register - signal txr : std_logic_vector(7 downto 0); -- transmit register - signal rxr : std_logic_vector(7 downto 0); -- receive register - signal cr : std_logic_vector(7 downto 0); -- command register - signal sr : std_logic_vector(7 downto 0); -- status register - - -- internal reset signal - signal rst_i : std_logic; - - -- wishbone write access - signal wb_wacc : std_logic; - - -- internal acknowledge signal - signal iack_o : std_logic; - - -- done signal: command completed, clear command register - signal done : std_logic; - - -- command register signals - signal sta, sto, rd, wr, ack, iack : std_logic; - - signal core_en : std_logic; -- core enable signal - signal ien : std_logic; -- interrupt enable signal - - -- status register signals - signal irxack, rxack : std_logic; -- received aknowledge from slave - signal tip : std_logic; -- transfer in progress - signal irq_flag : std_logic; -- interrupt pending flag - signal i2c_busy : std_logic; -- i2c bus busy (start signal detected) - signal i2c_al, al : std_logic; -- arbitration lost - -begin - -- generate internal reset signal - rst_i <= arst_i xor ARST_LVL; - - -- generate acknowledge output signal - gen_ack_o : process(wb_clk_i) - begin - if (wb_clk_i'event and wb_clk_i = '1') then - iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored - end if; - end process gen_ack_o; - wb_ack_o <= iack_o; - - - -- generate wishbone write access signal - wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i; - - -- assign wb_dat_o - assign_dato : process(wb_clk_i) - begin - if (wb_clk_i'event and wb_clk_i = '1') then - case wb_adr_i is - when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0)); - when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8)); - when "010" => wb_dat_o <= ctr; - when "011" => wb_dat_o <= rxr; -- write is transmit register TxR - when "100" => wb_dat_o <= sr; -- write is command register CR - - -- Debugging registers: - -- These registers are not documented. - -- Functionality could change in future releases - when "101" => wb_dat_o <= txr; - when "110" => wb_dat_o <= cr; - when "111" => wb_dat_o <= (others => '0'); - when others => wb_dat_o <= (others => 'X'); -- for simulation only - end case; - end if; - end process assign_dato; - - - -- generate registers (CR, SR see below) - gen_regs: process(rst_i, wb_clk_i) - begin - if (rst_i = '0') then - prer <= (others => '1'); - ctr <= (others => '0'); - txr <= (others => '0'); - elsif (wb_clk_i'event and wb_clk_i = '1') then - if (wb_rst_i = '1') then - prer <= (others => '1'); - ctr <= (others => '0'); - txr <= (others => '0'); - elsif (wb_wacc = '1') then - case wb_adr_i is - when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i); - when "001" => prer(15 downto 8) <= unsigned(wb_dat_i); - when "010" => ctr <= wb_dat_i; - when "011" => txr <= wb_dat_i; - when "100" => null; --write to CR, avoid executing the others clause - - -- illegal cases, for simulation only - when others => - report ("Illegal write address, setting all registers to unknown."); - prer <= (others => 'X'); - ctr <= (others => 'X'); - txr <= (others => 'X'); - end case; - end if; - end if; - end process gen_regs; - - - -- generate command register - gen_cr: process(rst_i, wb_clk_i) - begin - if (rst_i = '0') then - cr <= (others => '0'); - elsif (wb_clk_i'event and wb_clk_i = '1') then - if (wb_rst_i = '1') then - cr <= (others => '0'); - elsif (wb_wacc = '1') then - if ( (core_en = '1') and (wb_adr_i = 4) ) then - -- only take new commands when i2c core enabled - -- pending commands are finished - cr <= wb_dat_i; - end if; - else - if (done = '1' or i2c_al = '1') then - cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost - end if; - - cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' - cr(0) <= '0'; -- clear IRQ_ACK bit - end if; - end if; - end process gen_cr; - - -- decode command register - sta <= cr(7); - sto <= cr(6); - rd <= cr(5); - wr <= cr(4); - ack <= cr(3); - iack <= cr(0); - - -- decode control register - core_en <= ctr(7); - ien <= ctr(6); - - -- hookup byte controller block - byte_ctrl: i2c_master_byte_ctrl port map ( - clk => wb_clk_i, - rst => wb_rst_i, - nReset => rst_i, - ena => core_en, - clk_cnt => prer, - start => sta, - stop => sto, - read => rd, - write => wr, - ack_in => ack, - i2c_busy => i2c_busy, - i2c_al => i2c_al, - din => txr, - cmd_ack => done, - ack_out => irxack, - dout => rxr, - scl_i => scl_pad_i, - scl_o => scl_pad_o, - scl_oen => scl_padoen_o, - sda_i => sda_pad_i, - sda_o => sda_pad_o, - sda_oen => sda_padoen_o - ); - - - -- status register block + interrupt request signal - st_irq_block : block - begin - -- generate status register bits - gen_sr_bits: process (wb_clk_i, rst_i) - begin - if (rst_i = '0') then - al <= '0'; - rxack <= '0'; - tip <= '0'; - irq_flag <= '0'; - elsif (wb_clk_i'event and wb_clk_i = '1') then - if (wb_rst_i = '1') then - al <= '0'; - rxack <= '0'; - tip <= '0'; - irq_flag <= '0'; - else - al <= i2c_al or (al and not sta); - rxack <= irxack; - tip <= (rd or wr); - - -- interrupt request flag is always generated - irq_flag <= (done or i2c_al or irq_flag) and not iack; - end if; - end if; - end process gen_sr_bits; - - -- generate interrupt request signals - gen_irq: process (wb_clk_i, rst_i) - begin - if (rst_i = '0') then - wb_inta_o <= '0'; - elsif (wb_clk_i'event and wb_clk_i = '1') then - if (wb_rst_i = '1') then - wb_inta_o <= '0'; - else - -- interrupt signal is only generated when IEN (interrupt enable bit) is set - wb_inta_o <= irq_flag and ien; - end if; - end if; - end process gen_irq; - - -- assign status register bits - sr(7) <= rxack; - sr(6) <= i2c_busy; - sr(5) <= al; - sr(4 downto 2) <= (others => '0'); -- reserved - sr(1) <= tip; - sr(0) <= irq_flag; - end block; - -end architecture structural; diff --git a/opencores/i2c/rtl/vhdl/readme b/opencores/i2c/rtl/vhdl/readme deleted file mode 100644 index 0d049f736..000000000 --- a/opencores/i2c/rtl/vhdl/readme +++ /dev/null @@ -1,25 +0,0 @@ - - --- This code is provided for free and may be used and -- --- distributed without restriction provided that the -- --- copyright statement is not removed from the file and -- --- that any derivative work contains the original -- --- copyright notice and the associated disclaimer. -- - --- Comments and suggestions are always welcome -- - -The i2c_master core consists of three files: - -- i2c_master_top -- top level -- i2c_master_byte_ctrl -- byte controller -- i2c_master_bit_ctrl -- bit controller - -VHDL needs to be compiled in order. The files are listed -above in descending order. - -I2C.VHD and tst_ds1621.vhd are not supported anymore. -They remain mostly for historical purposes, altough they -might prove usefull. - -Richard Herveille -rherveille@opencores.org diff --git a/opencores/i2c/rtl/vhdl/tst_ds1621.vhd b/opencores/i2c/rtl/vhdl/tst_ds1621.vhd deleted file mode 100644 index ccf50460c..000000000 --- a/opencores/i2c/rtl/vhdl/tst_ds1621.vhd +++ /dev/null @@ -1,283 +0,0 @@ --- --- --- State machine for reading data from Dallas 1621 --- --- Testsystem for i2c controller --- --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.i2c.all; - -entity DS1621_interface is - port ( - clk : in std_logic; - nReset : in std_logic; - - Dout : out std_logic_vector(7 downto 0); -- data read from ds1621 - - error : out std_logic; -- no correct ack received - - SCL : inout std_logic; - SDA : inout std_logic - ); -end entity DS1621_interface; - -architecture structural of DS1621_interface is - constant SLAVE_ADDR : std_logic_vector(6 downto 0) := "1001000"; - constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(20, 8); - - signal cmd_ack : std_logic; - signal D : std_logic_vector(7 downto 0); - signal lack, store_dout : std_logic; - - signal start, read, write, ack, stop : std_logic; - signal i2c_dout : std_logic_vector(7 downto 0); - -begin - -- hookup I2C controller - u1: simple_i2c port map (clk => clk, ena => '1', clk_cnt => clk_cnt, nReset => nReset, - read => read, write => write, start => start, stop => stop, ack_in => ack, cmd_ack => cmd_ack, - Din => D, Dout => i2c_dout, ack_out => lack, SCL => SCL, SDA => SDA); - - init_statemachine : block - type states is (i1, i2, i3, i4, i5, t1, t2, t3, t4, t5); - signal state : states; - begin - nxt_state_decoder: process(clk, nReset, state) - variable nxt_state : states; - variable iD : std_logic_vector(7 downto 0); - variable ierr : std_logic; - variable istart, iread, iwrite, iack, istop : std_logic; - variable istore_dout : std_logic; - begin - nxt_state := state; - ierr := '0'; - istore_dout := '0'; - - istart := start; - iread := read; - iwrite := write; - iack := ack; - istop := stop; - iD := D; - - case (state) is - -- init DS1621 - -- 1) send start condition - -- 2) send slave address + write - -- 3) check ack - -- 4) send "access config" command (0xAC) - -- 5) check ack - -- 6) send config register data (0x00) - -- 7) check ack - -- 8) send stop condition - -- 9) send start condition - -- 10) send slave address + write - -- 11) check ack - -- 12) send "start conversion" command (0xEE) - -- 13) check ack - -- 14) send stop condition - - when i1 => -- send start condition, sent slave address + write - nxt_state := i2; - istart := '1'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := (slave_addr & '0'); -- write to slave (R/W = '0') - - when i2 => -- send "access config" command - if (cmd_ack = '1') then - nxt_state := i3; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := x"AC"; - end if; - - when i3 => -- send config register data, sent stop condition - if (cmd_ack = '1') then - nxt_state := i4; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '1'; - iD := x"00"; - end if; - - when i4 => -- send start condition, sent slave address + write - if (cmd_ack = '1') then - nxt_state := i5; - - istart := '1'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := (slave_addr & '0'); -- write to slave (R/W = '0') - end if; - - when i5 => -- send "start conversion" command + stop condition - if (cmd_ack = '1') then - nxt_state := t1; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '1'; - iD := x"EE"; - end if; - -- read temperature - -- 1) sent start condition - -- 2) sent slave address + write - -- 3) check ack - -- 4) sent "read temperature" command (0xAA) - -- 5) check ack - -- 6) sent start condition - -- 7) sent slave address + read - -- 8) check ack - -- 9) read msb - -- 10) send ack - -- 11) read lsb - -- 12) send nack - -- 13) send stop condition - - when t1 => -- send start condition, sent slave address + write - if (cmd_ack = '1') then - nxt_state := t2; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '1'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := (slave_addr & '0'); -- write to slave (R/W = '0') - end if; - - when t2 => -- send read temperature command - if (cmd_ack = '1') then - nxt_state := t3; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := x"AA"; - end if; - - when t3 => -- send (repeated) start condition, send slave address + read - if (cmd_ack = '1') then - nxt_state := t4; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received, expected ACK - end if; - - istart := '1'; - iread := '0'; - iwrite := '1'; - iack := '0'; - istop := '0'; - iD := (slave_addr & '1'); -- read from slave (R/W = '1') - end if; - - when t4 => -- read MSB (hi-byte), send acknowledge - if (cmd_ack = '1') then - nxt_state := t5; - -- check aknowledge bit - if (lack = '1') then - ierr := '1'; -- no acknowledge received from last command, expected ACK - end if; - - istart := '0'; - iread := '1'; - iwrite := '0'; - iack := '0'; --ACK - istop := '0'; - end if; - - when t5 => -- read LSB (lo-byte), send acknowledge, sent stop - if (cmd_ack = '1') then - nxt_state := t1; - - istart := '0'; - iread := '1'; - iwrite := '0'; - iack := '1'; --NACK - istop := '1'; - - istore_dout := '1'; - end if; - end case; - - -- genregs - if (nReset = '0') then - state <= i1; - error <= '0'; - store_dout <= '0'; - - start <= '0'; - read <= '0'; - write <= '0'; - ack <= '0'; - stop <= '0'; - D <= (others => '0'); - elsif (clk'event and clk = '1') then - state <= nxt_state; - error <= ierr; - store_dout <= istore_dout; - - start <= istart; - read <= iread; - write <= iwrite; - ack <= iack; - stop <= istop; - D <= iD; - end if; - end process nxt_state_decoder; - end block init_statemachine; - - -- store temp - gen_dout : process(clk) - begin - if (clk'event and clk = '1') then - if (store_dout = '1') then - Dout <= i2c_dout; - end if; - end if; - end process gen_dout; - -end architecture structural; - - diff --git a/opencores/i2c/sim/CVS/Entries b/opencores/i2c/sim/CVS/Entries deleted file mode 100644 index d08a896a5..000000000 --- a/opencores/i2c/sim/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/i2c_verilog//// diff --git a/opencores/i2c/sim/CVS/Repository b/opencores/i2c/sim/CVS/Repository deleted file mode 100644 index 500d85906..000000000 --- a/opencores/i2c/sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/sim diff --git a/opencores/i2c/sim/CVS/Root b/opencores/i2c/sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/sim/CVS/Template b/opencores/i2c/sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/sim/i2c_verilog/CVS/Entries b/opencores/i2c/sim/i2c_verilog/CVS/Entries deleted file mode 100644 index 8ab9f73a7..000000000 --- a/opencores/i2c/sim/i2c_verilog/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/run//// diff --git a/opencores/i2c/sim/i2c_verilog/CVS/Repository b/opencores/i2c/sim/i2c_verilog/CVS/Repository deleted file mode 100644 index b97ee33c8..000000000 --- a/opencores/i2c/sim/i2c_verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/sim/i2c_verilog diff --git a/opencores/i2c/sim/i2c_verilog/CVS/Root b/opencores/i2c/sim/i2c_verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/sim/i2c_verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/sim/i2c_verilog/CVS/Template b/opencores/i2c/sim/i2c_verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/sim/i2c_verilog/run/CVS/Entries b/opencores/i2c/sim/i2c_verilog/run/CVS/Entries deleted file mode 100644 index ddea0baae..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/CVS/Entries +++ /dev/null @@ -1,6 +0,0 @@ -/bench.vcd/1.1/Sat Jun 15 07:37:05 2002// -/ncverilog.key/1.1/Sat Jun 15 07:37:11 2002// -/ncverilog.log/1.1/Sat Jun 15 07:37:11 2002// -/run/1.2/Fri Apr 6 09:02:38 2007// -D/INCA_libs//// -D/waves//// diff --git a/opencores/i2c/sim/i2c_verilog/run/CVS/Repository b/opencores/i2c/sim/i2c_verilog/run/CVS/Repository deleted file mode 100644 index bdd990e7c..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/sim/i2c_verilog/run diff --git a/opencores/i2c/sim/i2c_verilog/run/CVS/Root b/opencores/i2c/sim/i2c_verilog/run/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/sim/i2c_verilog/run/CVS/Template b/opencores/i2c/sim/i2c_verilog/run/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries b/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository b/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository deleted file mode 100644 index 6b760e397..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/sim/i2c_verilog/run/INCA_libs diff --git a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root b/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template b/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/sim/i2c_verilog/run/bench.vcd b/opencores/i2c/sim/i2c_verilog/run/bench.vcd deleted file mode 100644 index 9a364415f..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/bench.vcd +++ /dev/null @@ -1,1496812 +0,0 @@ -$date - Jun 15, 2002 13:36:37 -$end -$version - ncsim: v03.40.(b001) -$end -$timescale - 10 ps -$end - -$scope module tst_bench_top $end -$var reg 1 ! clk $end -$var reg 1 " rstn $end -$var wire 1 # adr [31] $end -$var wire 1 $ adr [30] $end -$var wire 1 % adr [29] $end -$var wire 1 & adr [28] $end -$var wire 1 ' adr [27] $end -$var wire 1 ( adr [26] $end -$var wire 1 ) adr [25] $end -$var wire 1 * adr [24] $end -$var wire 1 + adr [23] $end -$var wire 1 , adr [22] $end -$var wire 1 - adr [21] $end -$var wire 1 . adr [20] $end -$var wire 1 / adr [19] $end -$var wire 1 0 adr [18] $end -$var wire 1 1 adr [17] $end -$var wire 1 2 adr [16] $end -$var wire 1 3 adr [15] $end -$var wire 1 4 adr [14] $end -$var wire 1 5 adr [13] $end -$var wire 1 6 adr [12] $end -$var wire 1 7 adr [11] $end -$var wire 1 8 adr [10] $end -$var wire 1 9 adr [9] $end -$var wire 1 : adr [8] $end -$var wire 1 ; adr [7] $end -$var wire 1 < adr [6] $end -$var wire 1 = adr [5] $end -$var wire 1 > adr [4] $end -$var wire 1 ? adr [3] $end -$var wire 1 @ adr [2] $end -$var wire 1 A adr [1] $end -$var wire 1 B adr [0] $end -$var wire 8 C dat_i [7:0] $end -$var wire 8 D dat_o [7:0] $end -$var wire 1 E we $end -$var wire 1 F stb $end -$var wire 1 G cyc $end -$var wire 1 H ack $end -$var wire 1 I inta $end -$var reg 8 J q [7:0] $end -$var reg 8 K qq [7:0] $end -$var wire 1 L scl $end -$var wire 1 M scl_o $end -$var wire 1 N scl_oen $end -$var wire 1 O sda $end -$var wire 1 P sda_o $end -$var wire 1 Q sda_oen $end -$var parameter 3 R PRER_LO $end -$var parameter 3 S PRER_HI $end -$var parameter 3 T CTR $end -$var parameter 3 U RXR $end -$var parameter 3 V TXR $end -$var parameter 3 W CR $end -$var parameter 3 X SR $end -$var parameter 3 Y TXR_R $end -$var parameter 3 Z CR_R $end - -$scope module i2c_slave $end -$var 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-#43366500 -1! -#43367000 -0! -#43367500 -1! -#43368000 -0! -#43368500 -1! -#43369000 -0! -#43369500 -1! -#43370000 -0! -#43370500 -1! -#43371000 -0! -#43371500 -1! -#43372000 -0! -#43372500 -1! -#43373000 -0! -#43373500 -1! -#43374000 -0! -#43374500 -1! -#43375000 -0! -#43375500 -1! -#43376000 -0! -#43376500 -1! -#43377000 -0! -#43377500 -1! -#43378000 -0! -#43378500 -1! -#43379000 -0! -#43379500 -1! -#43380000 -0! -#43380500 -1! -#43381000 -0! -#43381500 -1! -#43382000 -0! -#43382500 -1! -#43383000 -0! -#43383500 -1! -#43384000 -0! -#43384500 -1! -#43385000 -0! -#43385500 -1! -#43386000 -0! -#43386500 -1! -#43387000 -0! -#43387500 -1! -#43388000 -0! -#43388500 -1! -#43388600 diff --git a/opencores/i2c/sim/i2c_verilog/run/ncverilog.key b/opencores/i2c/sim/i2c_verilog/run/ncverilog.key deleted file mode 100644 index a3abe5090..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/ncverilog.key +++ /dev/null @@ -1 +0,0 @@ -exit diff --git a/opencores/i2c/sim/i2c_verilog/run/ncverilog.log b/opencores/i2c/sim/i2c_verilog/run/ncverilog.log deleted file mode 100644 index 420a1b9e5..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/ncverilog.log +++ /dev/null @@ -1,118 +0,0 @@ -ncverilog: v03.40.(b001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc. -ncverilog: v03.40.(b001): Started on Jun 15, 2002 at 13:36:36 -ncverilog - +access+rwc - +linedebug - +define+"WAVES" - +incdir+../../../../bench/verilog - +incdir+../../../../rtl/verilog - +libext+.v - -y - /tools/synopsys/dw/sim_ver/ - ../../../../rtl/verilog/i2c_master_bit_ctrl.v - ../../../../rtl/verilog/i2c_master_byte_ctrl.v - ../../../../rtl/verilog/i2c_master_top.v - ../../../../bench/verilog/i2c_slave_model.v - ../../../../bench/verilog/wb_master_model.v - ../../../../bench/verilog/tst_bench_top.v - -ncverilog: *W,BADPRF: The +linedebug option may have an adverse performance impact. -file: ../../../../rtl/verilog/i2c_master_bit_ctrl.v - module worklib.i2c_master_bit_ctrl:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../rtl/verilog/i2c_master_byte_ctrl.v - module worklib.i2c_master_byte_ctrl:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../rtl/verilog/i2c_master_top.v - module worklib.i2c_master_top:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../bench/verilog/i2c_slave_model.v - module worklib.i2c_slave_model:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../bench/verilog/wb_master_model.v - module worklib.wb_master_model:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../bench/verilog/tst_bench_top.v - module worklib.tst_bench_top:v - errors: 0, warnings: 0 -ncvlog: *W,LIBNOU: Library "/tools/synopsys/dw/sim_ver/" given but not used. - Total errors/warnings found outside modules and primitives: - errors: 0, warnings: 1 - Caching library 'worklib' ....... Done - Elaborating the design hierarchy: - Building instance overlay tables: .................... Done - Generating native compiled code: - worklib.tst_bench_top:v <0x7fb52c98> - streams: 12, words: 59009 - Loading native compiled code: .................... Done - Building instance specific data structures. - Design hierarchy summary: - Instances Unique - Modules: 6 6 - Primitives: 2 1 - Registers: 68 68 - Scalar wires: 48 - - Expanded wires: 36 2 - Vectored wires: 6 - - Always blocks: 23 23 - Initial blocks: 3 3 - Cont. assignments: 28 28 - Pseudo assignments: 11 14 - Simulation timescale: 10ps - Writing initial simulation snapshot: worklib.tst_bench_top:v -Loading snapshot worklib.tst_bench_top:v .................... Done -ncsim> source /cds/tools/inca/files/ncsimrc -ncsim> run -INFO: Signal dump enabled ... - - - -status: 0 Testbench started - - - -INFO: WISHBONE MASTER MODEL INSTANTIATED (tst_bench_top.u0) - -status: 19500 done reset -status: 23600 programmed registers -status: 25600 verified registers -status: 27600 enabled core -status: 30600 generate 'start', write cmd a0 (slave address+write) -status: 2582600 tip==0 -status: 2585600 write slave memory address 01 -status: 4877600 tip==0 -status: 4880600 write data a5 -status: 7172600 tip==0 -status: 7175600 write next data 5a, generate 'stop' -status: 9467600 tip==0 -status: 19467600 wait 100us -status: 19470600 generate 'start', write cmd a0 (slave address+write) -status: 22014600 tip==0 -status: 22017600 write slave address 01 -status: 24309600 tip==0 -status: 24312600 generate 'repeated start', write cmd a1 (slave address+read) -status: 26858600 tip==0 -status: 26860600 read + ack -status: 29154600 tip==0 -status: 29158600 read + ack -status: 31448600 tip==0 -status: 31452600 read + ack -status: 33744600 tip==0 -status: 33746600 received xx from 3rd read address -status: 33748600 read + nack -status: 36038600 tip==0 -status: 36040600 received xx from 4th read address -status: 36043600 generate 'start', write cmd a0 (slave address+write). Check invalid address -status: 38589600 tip==0 -status: 38592600 write slave memory address 10 -status: 40884600 tip==0 -status: 40884600 Check for nack -status: 40886600 generate 'stop' -status: 40888600 tip==0 - - -status: 43388600 Testbench done -Simulation stopped via $stop(1) at time 433886 NS + 0 -/mnt/pooh/projects/I2C/bench/verilog/tst_bench_top.v:427 $stop; -ncsim> exit -ncverilog: v03.40.(b001): Exiting on Jun 15, 2002 at 13:47:48 (total: 00:11:12) diff --git a/opencores/i2c/sim/i2c_verilog/run/run b/opencores/i2c/sim/i2c_verilog/run/run deleted file mode 100755 index 41bcaab30..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/run +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/csh - -set i2c = ../../.. -set bench = $i2c/bench -set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves - -ncverilog \ - \ - +access+rwc \ - +define+WAVES \ - \ - +incdir+$bench/verilog \ - +incdir+$i2c/rtl/verilog \ - \ - $i2c/rtl/verilog/i2c_master_bit_ctrl.v \ - $i2c/rtl/verilog/i2c_master_byte_ctrl.v \ - $i2c/rtl/verilog/i2c_master_top.v \ - \ - $bench/verilog/i2c_slave_model.v \ - $bench/verilog/wb_master_model.v \ - $bench/verilog/tst_bench_top.v - - - - diff --git a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries b/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository b/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository deleted file mode 100644 index 94d106eb0..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/sim/i2c_verilog/run/waves diff --git a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root b/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template b/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/software/CVS/Entries b/opencores/i2c/software/CVS/Entries deleted file mode 100644 index 934613477..000000000 --- a/opencores/i2c/software/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -D/drivers//// -D/include//// diff --git a/opencores/i2c/software/CVS/Repository b/opencores/i2c/software/CVS/Repository deleted file mode 100644 index 1b4c9f0bb..000000000 --- a/opencores/i2c/software/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/software diff --git a/opencores/i2c/software/CVS/Root b/opencores/i2c/software/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/software/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/software/CVS/Template b/opencores/i2c/software/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/software/drivers/CVS/Entries b/opencores/i2c/software/drivers/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/i2c/software/drivers/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/i2c/software/drivers/CVS/Repository b/opencores/i2c/software/drivers/CVS/Repository deleted file mode 100644 index 260d7873c..000000000 --- a/opencores/i2c/software/drivers/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/software/drivers diff --git a/opencores/i2c/software/drivers/CVS/Root b/opencores/i2c/software/drivers/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/software/drivers/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/software/drivers/CVS/Template b/opencores/i2c/software/drivers/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/software/include/CVS/Entries b/opencores/i2c/software/include/CVS/Entries deleted file mode 100644 index ef11b0c73..000000000 --- a/opencores/i2c/software/include/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/oc_i2c_master.h/1.1/Thu Nov 22 10:02:19 2001// -D diff --git a/opencores/i2c/software/include/CVS/Repository b/opencores/i2c/software/include/CVS/Repository deleted file mode 100644 index 2ea08eeec..000000000 --- a/opencores/i2c/software/include/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/software/include diff --git a/opencores/i2c/software/include/CVS/Root b/opencores/i2c/software/include/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/software/include/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/software/include/CVS/Template b/opencores/i2c/software/include/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/software/include/oc_i2c_master.h b/opencores/i2c/software/include/oc_i2c_master.h deleted file mode 100644 index 7f7cfc417..000000000 --- a/opencores/i2c/software/include/oc_i2c_master.h +++ /dev/null @@ -1,102 +0,0 @@ -/* -///////////////////////////////////////////////////////////////////// -//// //// -//// Include file for OpenCores I2C Master core //// -//// //// -//// File : oc_i2c_master.h //// -//// Function: c-include file //// -//// //// -//// Authors: Richard Herveille (richard@asics.ws) //// -//// Filip Miletic //// -//// //// -//// www.opencores.org //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// Filip Miletic //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -*/ - -/* - * Definitions for the Opencores i2c master core - */ - -/* --- Definitions for i2c master's registers --- */ - -/* ----- Read-write access */ - -#define OC_I2C_PRER_LO 0x00 /* Low byte clock prescaler register */ -#define OC_I2C_PRER_HI 0x01 /* High byte clock prescaler register */ -#define OC_I2C_CTR 0x02 /* Control register */ - -/* ----- Write-only registers */ - -#define OC_I2C_TXR 0x03 /* Transmit byte register */ -#define OC_I2C_CR 0x04 /* Command register */ - -/* ----- Read-only registers */ - -#define OC_I2C_RXR 0x03 /* Receive byte register */ -#define OC_I2C_SR 0x04 /* Status register */ - -/* ----- Bits definition */ - -/* ----- Control register */ - -#define OC_I2C_EN (1<<7) /* Core enable bit: */ - /* 1 - core is enabled */ - /* 0 - core is disabled */ -#define OC_I2C_IEN (1<<6) /* Interrupt enable bit */ - /* 1 - Interrupt enabled */ - /* 0 - Interrupt disabled */ - /* Other bits in CR are reserved */ - -/* ----- Command register bits */ - -#define OC_I2C_STA (1<<7) /* Generate (repeated) start condition*/ -#define OC_I2C_STO (1<<6) /* Generate stop condition */ -#define OC_I2C_RD (1<<5) /* Read from slave */ -#define OC_I2C_WR (1<<4) /* Write to slave */ -#define OC_I2C_ACK (1<<3) /* Acknowledge from slave */ - /* 1 - ACK */ - /* 0 - NACK */ -#define OC_I2C_IACK (1<<0) /* Interrupt acknowledge */ - -/* ----- Status register bits */ - -#define OC_I2C_RXACK (1<<7) /* ACK received from slave */ - /* 1 - ACK */ - /* 0 - NACK */ -#define OC_I2C_BUSY (1<<6) /* Busy bit */ -#define OC_I2C_TIP (1<<1) /* Transfer in progress */ -#define OC_I2C_IF (1<<0) /* Interrupt flag */ - -/* bit testing and setting macros */ - -#define OC_ISSET(reg,bitmask) ((reg)&(bitmask)) -#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask))) -#define OC_BITSET(reg,bitmask) ((reg)|(bitmask)) -#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask))) -#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask)) -#define OC_REGMOVE(reg,value) ((reg)=(value)) \ No newline at end of file diff --git a/opencores/i2c/verilog/CVS/Entries b/opencores/i2c/verilog/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/i2c/verilog/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/i2c/verilog/CVS/Repository b/opencores/i2c/verilog/CVS/Repository deleted file mode 100644 index acc23265f..000000000 --- a/opencores/i2c/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/verilog diff --git a/opencores/i2c/verilog/CVS/Root b/opencores/i2c/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/verilog/CVS/Template b/opencores/i2c/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/i2c/vhdl/CVS/Entries b/opencores/i2c/vhdl/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/i2c/vhdl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/i2c/vhdl/CVS/Repository b/opencores/i2c/vhdl/CVS/Repository deleted file mode 100644 index 8ee00a788..000000000 --- a/opencores/i2c/vhdl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/vhdl diff --git a/opencores/i2c/vhdl/CVS/Root b/opencores/i2c/vhdl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/i2c/vhdl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/vhdl/CVS/Template b/opencores/i2c/vhdl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/simple_gpio/CVS/Entries b/opencores/simple_gpio/CVS/Entries deleted file mode 100644 index df1462bb9..000000000 --- a/opencores/simple_gpio/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/rtl//// diff --git a/opencores/simple_gpio/CVS/Repository b/opencores/simple_gpio/CVS/Repository deleted file mode 100644 index b869a0de8..000000000 --- a/opencores/simple_gpio/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -simple_gpio diff --git a/opencores/simple_gpio/CVS/Root b/opencores/simple_gpio/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/simple_gpio/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/simple_gpio/CVS/Template b/opencores/simple_gpio/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/simple_gpio/rtl/CVS/Entries b/opencores/simple_gpio/rtl/CVS/Entries deleted file mode 100644 index 8c6258130..000000000 --- a/opencores/simple_gpio/rtl/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/simple_gpio.v/1.2/Sun Dec 22 16:10:17 2002// -D diff --git a/opencores/simple_gpio/rtl/CVS/Repository b/opencores/simple_gpio/rtl/CVS/Repository deleted file mode 100644 index 955303d8a..000000000 --- a/opencores/simple_gpio/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -simple_gpio/rtl diff --git a/opencores/simple_gpio/rtl/CVS/Root b/opencores/simple_gpio/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/simple_gpio/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/simple_gpio/rtl/CVS/Template b/opencores/simple_gpio/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/simple_gpio/rtl/simple_gpio.v b/opencores/simple_gpio/rtl/simple_gpio.v deleted file mode 100644 index 0b78f9921..000000000 --- a/opencores/simple_gpio/rtl/simple_gpio.v +++ /dev/null @@ -1,193 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple General Purpose IO core //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: simple_gpio.v,v 1.2 2002/12/22 16:10:17 rherveille Exp $ -// -// $Date: 2002/12/22 16:10:17 $ -// $Revision: 1.2 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: simple_gpio.v,v $ -// Revision 1.2 2002/12/22 16:10:17 rherveille -// Fixed some typos in the documentation section. -// -// - - - -// -// Very basic 8bit GPIO core -// -// -// Registers: -// -// 0x00: Control Register -// bits 7:0 R/W Input/Output '1' = output mode -// '0' = input mode -// 0x01: Line Register -// bits 7:0 R Status Current GPIO pin level -// W Output GPIO pin output level -// -// -// HOWTO: -// -// Use a pin as an input: -// Program the corresponding bit in the control register to 'input mode' ('0'). -// The pin's state (input level) can be checked by reading the Line Register. -// Writing to the GPIO pin's Line Register bit while in input mode has no effect. -// -// Use a pin as an output: -// Program the corresponding bit in the control register to 'output mode' ('1'). -// Program the GPIO pin's output level by writing to the corresponding bit in -// the Line Register. -// Reading the GPIO pin's Line Register bit while in output mode returns the -// current output level. -// -// Addapt the core for fewer GPIOs: -// If less than 8 GPIOs are required, than the 'io' parameter can be set to -// the amount of required interrupts. GPIOs are mapped starting at the LSBs. -// So only the 'io' LSBs per register are valid. -// All other bits (i.e. the 8-'io' MSBs) are set to zero '0'. -// Codesize is approximately linear to the amount of interrupts. I.e. using -// 4 instead of 8 GPIO sources reduces the size by approx. half. -// - - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on - -module simple_gpio( - clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, - gpio -); - - // - // Inputs & outputs - // - parameter io = 8; // number of GPIOs - - // 8bit WISHBONE bus slave interface - input clk_i; // clock - input rst_i; // reset (asynchronous active low) - input cyc_i; // cycle - input stb_i; // strobe - input adr_i; // address adr_i[1] - input we_i; // write enable - input [ 7:0] dat_i; // data output - output [ 7:0] dat_o; // data input - output ack_o; // normal bus termination - - // GPIO pins - inout [io:1] gpio; - - // - // Module body - // - reg [io:1] ctrl, line; // ControlRegister, LineRegister - reg [io:1] lgpio, llgpio; // LatchedGPIO pins - - // - // perform parameter checks - // - // synopsys translate_off - initial - begin - if(io > 8) - $display("simple_gpio: max. 8 GPIOs supported."); - end - // synopsys translate_on - - // - // WISHBONE interface - - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i or negedge rst_i) - if (~rst_i) - begin - ctrl <= #1 {io{1'b0}}; - line <= #1 {io{1'b0}}; - end - else if (wb_wr) - if ( adr_i ) - line <= #1 dat_i[io-1:0]; - else - ctrl <= #1 dat_i[io-1:0]; - - - reg [7:0] dat_o; - always @(posedge clk_i) - if ( adr_i ) - dat_o <= #1 { {(8-io){1'b0}}, llgpio}; - else - dat_o <= #1 { {(8-io){1'b0}}, ctrl}; - - reg ack_o; - always @(posedge clk_i or negedge rst_i) - if (~rst_i) - ack_o <= #1 1'b0; - else - ack_o <= #1 wb_acc & !ack_o; - - - // - // GPIO section - - // latch GPIO input pins - always @(posedge clk_i) - lgpio <= #1 gpio; - - // latch again (reduce meta-stability risc) - always @(posedge clk_i) - llgpio <= #1 lgpio; - - // assign GPIO outputs - integer n; - reg [io:1] igpio; // temporary internal signal - - always @(ctrl or line) - for(n=1;n<=io;n=n+1) - igpio[n] <= ctrl[n] ? line[n] : 1'bz; - - assign gpio = igpio; - -endmodule - diff --git a/opencores/simple_pic/CVS/Entries b/opencores/simple_pic/CVS/Entries deleted file mode 100644 index df1462bb9..000000000 --- a/opencores/simple_pic/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/rtl//// diff --git a/opencores/simple_pic/CVS/Repository b/opencores/simple_pic/CVS/Repository deleted file mode 100644 index 73de5bf2b..000000000 --- a/opencores/simple_pic/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -simple_pic diff --git a/opencores/simple_pic/CVS/Root b/opencores/simple_pic/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/simple_pic/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/simple_pic/CVS/Template b/opencores/simple_pic/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/simple_pic/rtl/CVS/Entries b/opencores/simple_pic/rtl/CVS/Entries deleted file mode 100644 index e5e641097..000000000 --- a/opencores/simple_pic/rtl/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/simple_pic.v/1.3/Tue Dec 24 10:26:51 2002// -D diff --git a/opencores/simple_pic/rtl/CVS/Repository b/opencores/simple_pic/rtl/CVS/Repository deleted file mode 100644 index 2639a29e2..000000000 --- a/opencores/simple_pic/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -simple_pic/rtl diff --git a/opencores/simple_pic/rtl/CVS/Root b/opencores/simple_pic/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/simple_pic/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/simple_pic/rtl/CVS/Template b/opencores/simple_pic/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/simple_pic/rtl/simple_pic.v b/opencores/simple_pic/rtl/simple_pic.v deleted file mode 100644 index 28184cbe2..000000000 --- a/opencores/simple_pic/rtl/simple_pic.v +++ /dev/null @@ -1,228 +0,0 @@ - -// Modified by M. Ettus, 2008 for 32 bit width - -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores Simple Programmable Interrupt Controller //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -// -// This is a simple Programmable Interrupt Controller. -// The number of interrupts is depending on the databus size. -// There's one interrupt input per databit (i.e. 16 interrupts for a 16 -// bit databus). -// All attached devices share the same CPU priority level. -// -// -// -// Registers: -// -// 0x00: EdgeEnable Register -// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source -// '0' = level triggered interrupt source -// 0x01: PolarityRegister -// bits 7:0 R/W Polarity '1' = high level / rising edge -// '0' = low level / falling edge -// 0x02: MaskRegister -// bits 7:0 R/W Mask '1' = interrupt masked (disabled) -// '0' = interrupt not masked (enabled) -// 0x03: PendingRegister -// bits 7:0 R/W Pending '1' = interrupt pending -// '0' = no interrupt pending -// -// A CPU interrupt is generated when an interrupt is pending and its -// MASK bit is cleared. -// -// -// -// HOWTO: -// -// Clearing pending interrupts: -// Writing a '1' to a bit in the interrupt pending register clears the -// interrupt. Make sure to clear the interrupt at the source before -// writing to the interrupt pending register. Otherwise the interrupt -// will be set again. -// -// Priority based interrupts: -// Upon reception of an interrupt, check the interrupt register and -// determine the highest priority interrupt. Mask all interrupts from the -// current level to the lowest level. This negates the interrupt line, and -// makes sure only interrupts with a higher level are triggered. After -// completion of the interrupt service routine, clear the interrupt source, -// the interrupt bit in the pending register, and restore the MASK register -// to it's previous state. -// -// Addapt the core for fewer interrupt sources: -// If less than 8 interrupt sources are required, than the 'is' parameter -// can be set to the amount of required interrupts. Interrupts are mapped -// starting at the LSBs. So only the 'is' LSBs per register are valid. All -// other bits (i.e. the 8-'is' MSBs) are set to zero '0'. -// Codesize is approximately linear to the amount of interrupts. I.e. using -// 4 instead of 8 interrupt sources reduces the size by approx. half. -// - - -module simple_pic( - clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o, - irq -); - parameter is = 8; // Number of interrupt sources - parameter dwidth = 32; - // - // Inputs & outputs - // - - // 8bit WISHBONE bus slave interface - input clk_i; // clock - input rst_i; // reset (asynchronous active low) - input cyc_i; // cycle - input stb_i; // strobe (cycle and strobe are the same signal) - input [ 2:1] adr_i; // address - input we_i; // write enable - input [ dwidth-1:0] dat_i; // data output - output [ dwidth-1:0] dat_o; // data input - output ack_o; // normal bus termination - - output int_o; // interrupt output - - // - // Interrupt sources - // - input [is:1] irq; // interrupt request inputs - - - // - // Module body - // - reg [is:1] pol, edgen, pending, mask; // register bank - reg [is:1] lirq, dirq; // latched irqs, delayed latched irqs - - - // - // perform parameter checks - // - // synopsys translate_off - initial - begin - if(is > dwidth) - $display("simple_pic: max number of interrupts = data bus width."); - end - // synopsys translate_on - - // - // latch interrupt inputs - always @(posedge clk_i) - lirq <= #1 irq; - - // - // generate delayed latched irqs - always @(posedge clk_i) - dirq <= #1 lirq; - - - // - // generate actual triggers - function trigger; - input edgen, pol, lirq, dirq; - - reg edge_irq, level_irq; - begin - edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq); - level_irq = pol ? lirq : ~lirq; - - trigger = edgen ? edge_irq : level_irq; - end - endfunction - - reg [is:1] irq_event; - integer n; - always @(posedge clk_i) - for(n=1; n<=is; n=n+1) - irq_event[n] <= #1 trigger(edgen[n], pol[n], lirq[n], dirq[n]); - - // - // generate wishbone register bank writes - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - always @(posedge clk_i) - if (rst_i) - begin - pol <= #1 {is{1'b0}}; // clear polarity register - edgen <= #1 {is{1'b0}}; // clear edge enable register - mask <= #1 {is{1'b1}}; // mask all interrupts - end - else if(wb_wr) // wishbone write cycle?? - case (adr_i) // synopsys full_case parallel_case - 2'b00: edgen <= #1 dat_i[is-1:0]; // EDGE-ENABLE register - 2'b01: pol <= #1 dat_i[is-1:0]; // POLARITY register - 2'b10: mask <= #1 dat_i[is-1:0]; // MASK register - 2'b11: ; // PENDING register is a special case (see below) - endcase - - - // pending register is a special case - always @(posedge clk_i) - if (rst_i) - pending <= #1 {is{1'b0}}; // clear all pending interrupts - else if ( wb_wr & (&adr_i) ) - pending <= #1 (pending & ~dat_i[is-1:0]) | irq_event; - else - pending <= #1 pending | irq_event; - - // - // generate dat_o - reg [dwidth-1:0] dat_o; - always @(posedge clk_i) - case (adr_i) // synopsys full_case parallel_case - 2'b00: dat_o <= #1 { {(dwidth-is){1'b0}}, edgen}; - 2'b01: dat_o <= #1 { {(dwidth-is){1'b0}}, pol}; - 2'b10: dat_o <= #1 { {(dwidth-is){1'b0}}, mask}; - 2'b11: dat_o <= #1 { {(dwidth-is){1'b0}}, pending}; - endcase - - // - // generate ack_o - reg ack_o; - always @(posedge clk_i) - ack_o <= #1 wb_acc & !ack_o; - - // - // generate CPU interrupt signal - reg int_o; - always @(posedge clk_i) - if(rst_i) - int_o <= #1 0; - else - int_o <= #1 |(pending & ~mask); - -endmodule - diff --git a/opencores/spi/CVS/Entries b/opencores/spi/CVS/Entries deleted file mode 100644 index 62011c465..000000000 --- a/opencores/spi/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -D/bench//// -D/doc//// -D/rtl//// -D/sim//// diff --git a/opencores/spi/CVS/Repository b/opencores/spi/CVS/Repository deleted file mode 100644 index c928c4b77..000000000 --- a/opencores/spi/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi diff --git a/opencores/spi/CVS/Root b/opencores/spi/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/CVS/Template b/opencores/spi/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/bench/CVS/Entries b/opencores/spi/bench/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/opencores/spi/bench/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/opencores/spi/bench/CVS/Repository b/opencores/spi/bench/CVS/Repository deleted file mode 100644 index f45728d0f..000000000 --- a/opencores/spi/bench/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/bench diff --git a/opencores/spi/bench/CVS/Root b/opencores/spi/bench/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/bench/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/bench/CVS/Template b/opencores/spi/bench/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/bench/verilog/CVS/Entries b/opencores/spi/bench/verilog/CVS/Entries deleted file mode 100644 index 68404f871..000000000 --- a/opencores/spi/bench/verilog/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -/spi_slave_model.v/1.2/Wed Mar 26 16:00:03 2003// -/tb_spi_top.v/1.6/Mon Mar 15 17:46:04 2004// -/wb_master_model.v/1.1.1.1/Wed Jun 12 15:45:23 2002// -D diff --git a/opencores/spi/bench/verilog/CVS/Repository b/opencores/spi/bench/verilog/CVS/Repository deleted file mode 100644 index 78a3c4a9f..000000000 --- a/opencores/spi/bench/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/bench/verilog diff --git a/opencores/spi/bench/verilog/CVS/Root b/opencores/spi/bench/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/bench/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/bench/verilog/CVS/Template b/opencores/spi/bench/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/bench/verilog/spi_slave_model.v b/opencores/spi/bench/verilog/spi_slave_model.v deleted file mode 100644 index dfdaed929..000000000 --- a/opencores/spi/bench/verilog/spi_slave_model.v +++ /dev/null @@ -1,73 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_slave_model.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "timescale.v" - -module spi_slave_model (rst, ss, sclk, mosi, miso); - - input rst; // reset - input ss; // slave select - input sclk; // serial clock - input mosi; // master out slave in - output miso; // master in slave out - - reg miso; - - reg rx_negedge; // slave receiving on negedge - reg tx_negedge; // slave transmiting on negedge - reg [31:0] data; // data register - - parameter Tp = 1; - - always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst) - begin - if (rst) - data <= #Tp 32'b0; - else if (!ss) - data <= #Tp {data[30:0], mosi}; - end - - always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge)) - begin - miso <= #Tp data[31]; - end - -endmodule - diff --git a/opencores/spi/bench/verilog/tb_spi_top.v b/opencores/spi/bench/verilog/tb_spi_top.v deleted file mode 100644 index 529c0aca1..000000000 --- a/opencores/spi/bench/verilog/tb_spi_top.v +++ /dev/null @@ -1,339 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// tb_spi_top.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// Based on: //// -//// - i2c/bench/verilog/tst_bench_top.v //// -//// Copyright (C) 2001 Richard Herveille //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "timescale.v" - -module tb_spi_top(); - - reg clk; - reg rst; - wire [31:0] adr; - wire [31:0] dat_i, dat_o; - wire we; - wire [3:0] sel; - wire stb; - wire cyc; - wire ack; - wire err; - wire int; - - wire [7:0] ss; - wire sclk; - wire mosi; - wire miso; - - reg [31:0] q; - reg [31:0] q1; - reg [31:0] q2; - reg [31:0] q3; - reg [31:0] result; - - parameter SPI_RX_0 = 5'h0; - parameter SPI_RX_1 = 5'h4; - parameter SPI_RX_2 = 5'h8; - parameter SPI_RX_3 = 5'hc; - parameter SPI_TX_0 = 5'h0; - parameter SPI_TX_1 = 5'h4; - parameter SPI_TX_2 = 5'h8; - parameter SPI_TX_3 = 5'hc; - parameter SPI_CTRL = 5'h10; - parameter SPI_DIVIDE = 5'h14; - parameter SPI_SS = 5'h18; - - // Generate clock - always #5 clk = ~clk; - - // Wishbone master model - wb_master_model #(32, 32) i_wb_master ( - .clk(clk), .rst(rst), - .adr(adr), .din(dat_i), .dout(dat_o), - .cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0) - ); - - // SPI master core - spi_top i_spi_top ( - .wb_clk_i(clk), .wb_rst_i(rst), - .wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i), - .wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb), - .wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int), - .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) - ); - - // SPI slave model - spi_slave_model i_spi_slave ( - .rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso) - ); - - initial - begin - $display("\nstatus: %t Testbench started\n\n", $time); - - $dumpfile("bench.vcd"); - $dumpvars(1, tb_spi_top); - $dumpvars(1, tb_spi_top.i_spi_slave); - - // Initial values - clk = 0; - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b0; - - result = 32'h0; - - // Reset system - rst = 1'b0; // negate reset - #2; - rst = 1'b1; // assert reset - repeat(20) @(posedge clk); - rst = 1'b0; // negate reset - - $display("status: %t done reset", $time); - - @(posedge clk); - - // Program core - i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register - i_wb_master.wb_write(0, SPI_TX_0, 32'h5a); // set tx register to 0x5a - i_wb_master.wb_write(0, SPI_CTRL, 32'h208); // set 8 bit transfer - i_wb_master.wb_write(0, SPI_SS, 32'h01); // set ss 0 - - $display("status: %t programmed registers", $time); - - i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00); // verify devider register - i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a); // verify tx register - i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208); // verify tx register - i_wb_master.wb_cmp(0, SPI_SS, 32'h01); // verify ss register - - $display("status: %t verified registers", $time); - - i_spi_slave.rx_negedge = 1'b1; - i_spi_slave.tx_negedge = 1'b0; - i_spi_slave.data[31:0] = 32'ha5967e5a; - i_wb_master.wb_write(0, SPI_CTRL, 32'h308); // set 8 bit transfer, start transfer - - $display("status: %t generate transfer: 8 bit, msb first, tx posedge, rx negedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b1; - i_wb_master.wb_write(0, SPI_TX_0, 32'ha5); - i_wb_master.wb_write(0, SPI_CTRL, 32'h408); // set 8 bit transfer, tx negedge - i_wb_master.wb_write(0, SPI_CTRL, 32'h508); // set 8 bit transfer, tx negedge, start transfer - - $display("status: %t generate transfer: 8 bit, msb first, tx negedge, rx posedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b1; - i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5); - i_wb_master.wb_write(0, SPI_CTRL, 32'hc10); // set 16 bit transfer, tx negedge, lsb - i_wb_master.wb_write(0, SPI_CTRL, 32'hd10); // set 16 bit transfer, tx negedge, start transfer - - $display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b1; - i_spi_slave.tx_negedge = 1'b0; - i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210); - i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98); - i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40); // set 64 bit transfer, rx negedge, lsb - i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40); // set 64 bit transfer, rx negedge, start transfer - - $display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - i_wb_master.wb_read(1, SPI_RX_1, q1); - result = result + q1; - - if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b1; - i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff); - i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb); - i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677); - i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233); - i_wb_master.wb_write(0, SPI_CTRL, 32'h400); - i_wb_master.wb_write(0, SPI_CTRL, 32'h500); - - $display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time); - - // Check bsy bit - i_wb_master.wb_read(0, SPI_CTRL, q); - while (q[8]) - i_wb_master.wb_read(1, SPI_CTRL, q); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - i_wb_master.wb_read(1, SPI_RX_1, q1); - result = result + q1; - i_wb_master.wb_read(1, SPI_RX_2, q2); - result = result + q2; - i_wb_master.wb_read(1, SPI_RX_3, q3); - result = result + q3; - - if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b0; - i_spi_slave.tx_negedge = 1'b1; - i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5); - i_wb_master.wb_write(0, SPI_CTRL, 32'h1420); - i_wb_master.wb_write(0, SPI_CTRL, 32'h1520); - - $display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time); - - // Check interrupt signal - while (!int) - @(posedge clk); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - @(posedge clk); - if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b1; - i_spi_slave.tx_negedge = 1'b0; - i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421); - i_wb_master.wb_write(0, SPI_CTRL, 32'h3220); - i_wb_master.wb_write(0, SPI_CTRL, 32'h3320); - - $display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time); - - while (!int) - @(posedge clk); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - @(posedge clk); - if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - i_spi_slave.rx_negedge = 1'b1; - i_spi_slave.tx_negedge = 1'b0; - i_wb_master.wb_write(0, SPI_TX_0, 32'h1); - i_wb_master.wb_write(0, SPI_CTRL, 32'h3201); - i_wb_master.wb_write(0, SPI_CTRL, 32'h3301); - - $display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time); - - while (!int) - @(posedge clk); - - i_wb_master.wb_read(1, SPI_RX_0, q); - result = result + q; - - @(posedge clk); - if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0) - $display("status: %t transfer completed: ok", $time); - else - $display("status: %t transfer completed: nok", $time); - - $display("\n\nstatus: %t Testbench done", $time); - - #25000; // wait 25us - - $display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead); - $display("exit (%h)", result ^ 32'h2e8b36ab); - - $stop; - end - -endmodule - - diff --git a/opencores/spi/bench/verilog/wb_master_model.v b/opencores/spi/bench/verilog/wb_master_model.v deleted file mode 100644 index 3f8b7ee6a..000000000 --- a/opencores/spi/bench/verilog/wb_master_model.v +++ /dev/null @@ -1,176 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// wb_master_model.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// Based on: //// -//// - i2c/bench/verilog/wb_master_model.v //// -//// Copyright (C) 2001 Richard Herveille //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "timescale.v" - -module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); - - parameter dwidth = 32; - parameter awidth = 32; - - input clk, rst; - output [awidth -1:0] adr; - input [dwidth -1:0] din; - output [dwidth -1:0] dout; - output cyc, stb; - output we; - output [dwidth/8 -1:0] sel; - input ack, err, rty; - - // Internal signals - reg [awidth -1:0] adr; - reg [dwidth -1:0] dout; - reg cyc, stb; - reg we; - reg [dwidth/8 -1:0] sel; - - reg [dwidth -1:0] q; - - // Memory Logic - initial - begin - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - cyc = 1'b0; - stb = 1'bx; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - #1; - end - - // Wishbone write cycle - task wb_write; - input delay; - integer delay; - - input [awidth -1:0] a; - input [dwidth -1:0] d; - - begin - - // wait initial delay - repeat(delay) @(posedge clk); - - // assert wishbone signal - #1; - adr = a; - dout = d; - cyc = 1'b1; - stb = 1'b1; - we = 1'b1; - sel = {dwidth/8{1'b1}}; - @(posedge clk); - - // wait for acknowledge from slave - while(~ack) @(posedge clk); - - // negate wishbone signals - #1; - cyc = 1'b0; - stb = 1'bx; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - - end - endtask - - // Wishbone read cycle - task wb_read; - input delay; - integer delay; - - input [awidth -1:0] a; - output [dwidth -1:0] d; - - begin - - // wait initial delay - repeat(delay) @(posedge clk); - - // assert wishbone signals - #1; - adr = a; - dout = {dwidth{1'bx}}; - cyc = 1'b1; - stb = 1'b1; - we = 1'b0; - sel = {dwidth/8{1'b1}}; - @(posedge clk); - - // wait for acknowledge from slave - while(~ack) @(posedge clk); - - // negate wishbone signals - #1; - cyc = 1'b0; - stb = 1'bx; - adr = {awidth{1'bx}}; - dout = {dwidth{1'bx}}; - we = 1'hx; - sel = {dwidth/8{1'bx}}; - d = din; - - end - endtask - - // Wishbone compare cycle (read data from location and compare with expected data) - task wb_cmp; - input delay; - integer delay; - - input [awidth -1:0] a; - input [dwidth -1:0] d_exp; - - begin - wb_read (delay, a, q); - - if (d_exp !== q) - $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); - end - endtask - -endmodule - diff --git a/opencores/spi/doc/CVS/Entries b/opencores/spi/doc/CVS/Entries deleted file mode 100644 index ff33fa590..000000000 --- a/opencores/spi/doc/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/spi.pdf/1.5/Mon Mar 15 17:46:05 2004/-kb/ -D/src//// diff --git a/opencores/spi/doc/CVS/Repository b/opencores/spi/doc/CVS/Repository deleted file mode 100644 index 772adcef5..000000000 --- a/opencores/spi/doc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/doc diff --git a/opencores/spi/doc/CVS/Root b/opencores/spi/doc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/doc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/doc/CVS/Template b/opencores/spi/doc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/doc/spi.pdf b/opencores/spi/doc/spi.pdf deleted file mode 100644 index d88ee2807..000000000 Binary files a/opencores/spi/doc/spi.pdf and /dev/null differ diff --git a/opencores/spi/doc/src/CVS/Entries b/opencores/spi/doc/src/CVS/Entries deleted file mode 100644 index adcbf083d..000000000 --- a/opencores/spi/doc/src/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/spi.doc/1.7/Mon Mar 15 17:46:06 2004/-kb/ -D diff --git a/opencores/spi/doc/src/CVS/Repository b/opencores/spi/doc/src/CVS/Repository deleted file mode 100644 index 09b1f4a98..000000000 --- a/opencores/spi/doc/src/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/doc/src diff --git a/opencores/spi/doc/src/CVS/Root b/opencores/spi/doc/src/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/doc/src/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/doc/src/CVS/Template b/opencores/spi/doc/src/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/doc/src/spi.doc b/opencores/spi/doc/src/spi.doc deleted file mode 100755 index b04700177..000000000 Binary files a/opencores/spi/doc/src/spi.doc and /dev/null differ diff --git a/opencores/spi/rtl/CVS/Entries b/opencores/spi/rtl/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/opencores/spi/rtl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/opencores/spi/rtl/CVS/Repository b/opencores/spi/rtl/CVS/Repository deleted file mode 100644 index 5fd79b19b..000000000 --- a/opencores/spi/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/rtl diff --git a/opencores/spi/rtl/CVS/Root b/opencores/spi/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/rtl/CVS/Template b/opencores/spi/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/rtl/verilog/CVS/Entries b/opencores/spi/rtl/verilog/CVS/Entries deleted file mode 100644 index d125a1657..000000000 --- a/opencores/spi/rtl/verilog/CVS/Entries +++ /dev/null @@ -1,6 +0,0 @@ -/spi_clgen.v/1.3/Thu Jul 3 17:32:15 2003// -/spi_defines.v/1.8/Mon Mar 15 17:46:08 2004// -/spi_shift.v/1.7/Tue Jul 8 15:36:37 2003// -/spi_top.v/1.8/Tue Jul 8 15:36:37 2003// -/timescale.v/1.1.1.1/Wed Jun 12 15:45:23 2002// -D diff --git a/opencores/spi/rtl/verilog/CVS/Repository b/opencores/spi/rtl/verilog/CVS/Repository deleted file mode 100644 index 361b93bf8..000000000 --- a/opencores/spi/rtl/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/rtl/verilog diff --git a/opencores/spi/rtl/verilog/CVS/Root b/opencores/spi/rtl/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/rtl/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/rtl/verilog/CVS/Template b/opencores/spi/rtl/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/rtl/verilog/spi_clgen.v b/opencores/spi/rtl/verilog/spi_clgen.v deleted file mode 100644 index 7bc4f6e5e..000000000 --- a/opencores/spi/rtl/verilog/spi_clgen.v +++ /dev/null @@ -1,108 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_clgen.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "spi_defines.v" -`include "timescale.v" - -module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); - - parameter Tp = 1; - - input clk_in; // input clock (system clock) - input rst; // reset - input enable; // clock enable - input go; // start transfer - input last_clk; // last clock - input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value) - output clk_out; // output clock - output pos_edge; // pulse marking positive edge of clk_out - output neg_edge; // pulse marking negative edge of clk_out - - reg clk_out; - reg pos_edge; - reg neg_edge; - - reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter - wire cnt_zero; // conter is equal to zero - wire cnt_one; // conter is equal to one - - - assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}}; - assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; - - // Counter counts half period - always @(posedge clk_in or posedge rst) - begin - if(rst) - cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}}; - else - begin - if(!enable || cnt_zero) - cnt <= #Tp divider; - else - cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; - end - end - - // clk_out is asserted every other half period - always @(posedge clk_in or posedge rst) - begin - if(rst) - clk_out <= #Tp 1'b0; - else - clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; - end - - // Pos and neg edge signals - always @(posedge clk_in or posedge rst) - begin - if(rst) - begin - pos_edge <= #Tp 1'b0; - neg_edge <= #Tp 1'b0; - end - else - begin - pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); - neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); - end - end -endmodule - diff --git a/opencores/spi/rtl/verilog/spi_defines.v b/opencores/spi/rtl/verilog/spi_defines.v deleted file mode 100644 index a6925918e..000000000 --- a/opencores/spi/rtl/verilog/spi_defines.v +++ /dev/null @@ -1,159 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_define.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// -// Number of bits used for devider register. If used in system with -// low frequency of system clock this can be reduced. -// Use SPI_DIVIDER_LEN for fine tuning theexact number. -// -//`define SPI_DIVIDER_LEN_8 -`define SPI_DIVIDER_LEN_16 -//`define SPI_DIVIDER_LEN_24 -//`define SPI_DIVIDER_LEN_32 - -`ifdef SPI_DIVIDER_LEN_8 - `define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8 -`endif -`ifdef SPI_DIVIDER_LEN_16 - `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 -`endif -`ifdef SPI_DIVIDER_LEN_24 - `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 -`endif -`ifdef SPI_DIVIDER_LEN_32 - `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 -`endif - -// -// Maximum nuber of bits that can be send/received at once. -// Use SPI_MAX_CHAR for fine tuning the exact number, when using -// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. -// -`define SPI_MAX_CHAR_128 -//`define SPI_MAX_CHAR_64 -//`define SPI_MAX_CHAR_32 -//`define SPI_MAX_CHAR_24 -//`define SPI_MAX_CHAR_16 -//`define SPI_MAX_CHAR_8 - -`ifdef SPI_MAX_CHAR_128 - `define SPI_MAX_CHAR 128 // Can only be set to 128 - `define SPI_CHAR_LEN_BITS 7 -`endif -`ifdef SPI_MAX_CHAR_64 - `define SPI_MAX_CHAR 64 // Can only be set to 64 - `define SPI_CHAR_LEN_BITS 6 -`endif -`ifdef SPI_MAX_CHAR_32 - `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 - `define SPI_CHAR_LEN_BITS 5 -`endif -`ifdef SPI_MAX_CHAR_24 - `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 - `define SPI_CHAR_LEN_BITS 5 -`endif -`ifdef SPI_MAX_CHAR_16 - `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 - `define SPI_CHAR_LEN_BITS 4 -`endif -`ifdef SPI_MAX_CHAR_8 - `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 - `define SPI_CHAR_LEN_BITS 3 -`endif - -// -// Number of device select signals. Use SPI_SS_NB for fine tuning the -// exact number. -// -`define SPI_SS_NB_8 -//`define SPI_SS_NB_16 -//`define SPI_SS_NB_24 -//`define SPI_SS_NB_32 - -`ifdef SPI_SS_NB_8 - `define SPI_SS_NB 8 // Can be set from 1 to 8 -`endif -`ifdef SPI_SS_NB_16 - `define SPI_SS_NB 16 // Can be set from 9 to 16 -`endif -`ifdef SPI_SS_NB_24 - `define SPI_SS_NB 24 // Can be set from 17 to 24 -`endif -`ifdef SPI_SS_NB_32 - `define SPI_SS_NB 32 // Can be set from 25 to 32 -`endif - -// -// Bits of WISHBONE address used for partial decoding of SPI registers. -// -`define SPI_OFS_BITS 4:2 - -// -// Register offset -// -`define SPI_RX_0 0 -`define SPI_RX_1 1 -`define SPI_RX_2 2 -`define SPI_RX_3 3 -`define SPI_TX_0 0 -`define SPI_TX_1 1 -`define SPI_TX_2 2 -`define SPI_TX_3 3 -`define SPI_CTRL 4 -`define SPI_DEVIDE 5 -`define SPI_SS 6 - -// -// Number of bits in ctrl register -// -`define SPI_CTRL_BIT_NB 14 - -// -// Control register bit position -// -`define SPI_CTRL_ASS 13 -`define SPI_CTRL_IE 12 -`define SPI_CTRL_LSB 11 -`define SPI_CTRL_TX_NEGEDGE 10 -`define SPI_CTRL_RX_NEGEDGE 9 -`define SPI_CTRL_GO 8 -`define SPI_CTRL_RES_1 7 -`define SPI_CTRL_CHAR_LEN 6:0 - diff --git a/opencores/spi/rtl/verilog/spi_shift.v b/opencores/spi/rtl/verilog/spi_shift.v deleted file mode 100644 index b17ac8b1f..000000000 --- a/opencores/spi/rtl/verilog/spi_shift.v +++ /dev/null @@ -1,238 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_shift.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "spi_defines.v" -`include "timescale.v" - -module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, - pos_edge, neg_edge, rx_negedge, tx_negedge, - tip, last, - p_in, p_out, s_clk, s_in, s_out); - - parameter Tp = 1; - - input clk; // system clock - input rst; // reset - input [3:0] latch; // latch signal for storing the data in shift register - input [3:0] byte_sel; // byte select signals for storing the data in shift register - input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one) - input lsb; // lbs first on the line - input go; // start stansfer - input pos_edge; // recognize posedge of sclk - input neg_edge; // recognize negedge of sclk - input rx_negedge; // s_in is sampled on negative edge - input tx_negedge; // s_out is driven on negative edge - output tip; // transfer in progress - output last; // last bit - input [31:0] p_in; // parallel in - output [`SPI_MAX_CHAR-1:0] p_out; // parallel out - input s_clk; // serial clock - input s_in; // serial in - output s_out; // serial out - - reg s_out; - reg tip; - - reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count - reg [`SPI_MAX_CHAR-1:0] data; // shift register - wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position - wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position - wire rx_clk; // rx clock enable - wire tx_clk; // tx clock enable - - assign p_out = data; - - assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}; - assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : - (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}); - - assign last = !(|cnt); - - assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk); - assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; - - // Character bit counter - always @(posedge clk or posedge rst) - begin - if(rst) - cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; - else - begin - if(tip) - cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; - else - cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; - end - end - - // Transfer in progress - always @(posedge clk or posedge rst) - begin - if(rst) - tip <= #Tp 1'b0; - else if(go && ~tip) - tip <= #Tp 1'b1; - else if(tip && last && pos_edge) - tip <= #Tp 1'b0; - end - - // Sending bits to the line - always @(posedge clk or posedge rst) - begin - if (rst) - s_out <= #Tp 1'b0; - else - s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; - end - - // Receiving bits from the line - always @(posedge clk or posedge rst) - begin - if (rst) - data <= #Tp {`SPI_MAX_CHAR{1'b0}}; -`ifdef SPI_MAX_CHAR_128 - else if (latch[0] && !tip) - begin - if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; - if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; - if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; - if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; - end - else if (latch[1] && !tip) - begin - if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; - if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; - if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; - if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; - end - else if (latch[2] && !tip) - begin - if (byte_sel[3]) - data[95:88] <= #Tp p_in[31:24]; - if (byte_sel[2]) - data[87:80] <= #Tp p_in[23:16]; - if (byte_sel[1]) - data[79:72] <= #Tp p_in[15:8]; - if (byte_sel[0]) - data[71:64] <= #Tp p_in[7:0]; - end - else if (latch[3] && !tip) - begin - if (byte_sel[3]) - data[127:120] <= #Tp p_in[31:24]; - if (byte_sel[2]) - data[119:112] <= #Tp p_in[23:16]; - if (byte_sel[1]) - data[111:104] <= #Tp p_in[15:8]; - if (byte_sel[0]) - data[103:96] <= #Tp p_in[7:0]; - end -`else -`ifdef SPI_MAX_CHAR_64 - else if (latch[0] && !tip) - begin - if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; - if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; - if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; - if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; - end - else if (latch[1] && !tip) - begin - if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; - if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; - if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; - if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; - end -`else - else if (latch[0] && !tip) - begin - `ifdef SPI_MAX_CHAR_8 - if (byte_sel[0]) - data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0]; - `endif - `ifdef SPI_MAX_CHAR_16 - if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; - if (byte_sel[1]) - data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8]; - `endif - `ifdef SPI_MAX_CHAR_24 - if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; - if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; - if (byte_sel[2]) - data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16]; - `endif - `ifdef SPI_MAX_CHAR_32 - if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; - if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; - if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; - if (byte_sel[3]) - data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24]; - `endif - end -`endif -`endif - else - data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; - end - -endmodule - diff --git a/opencores/spi/rtl/verilog/spi_top.v b/opencores/spi/rtl/verilog/spi_top.v deleted file mode 100644 index 09b2e50e1..000000000 --- a/opencores/spi/rtl/verilog/spi_top.v +++ /dev/null @@ -1,287 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// spi_top.v //// -//// //// -//// This file is part of the SPI IP core project //// -//// http://www.opencores.org/projects/spi/ //// -//// //// -//// Author(s): //// -//// - Simon Srot (simons@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - - -`include "spi_defines.v" -`include "timescale.v" - -module spi_top -( - // Wishbone signals - wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, - wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, - - // SPI signals - ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i -); - - parameter Tp = 1; - - // Wishbone signals - input wb_clk_i; // master clock input - input wb_rst_i; // synchronous active high reset - input [4:0] wb_adr_i; // lower address bits - input [32-1:0] wb_dat_i; // databus input - output [32-1:0] wb_dat_o; // databus output - input [3:0] wb_sel_i; // byte select inputs - input wb_we_i; // write enable input - input wb_stb_i; // stobe/core select signal - input wb_cyc_i; // valid bus cycle input - output wb_ack_o; // bus cycle acknowledge output - output wb_err_o; // termination w/ error - output wb_int_o; // interrupt request signal output - - // SPI signals - output [`SPI_SS_NB-1:0] ss_pad_o; // slave select - output sclk_pad_o; // serial clock - output mosi_pad_o; // master out slave in - input miso_pad_i; // master in slave out - - reg [32-1:0] wb_dat_o; - reg wb_ack_o; - reg wb_int_o; - - // Internal signals - reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register - reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register - reg [`SPI_SS_NB-1:0] ss; // Slave select register - reg [32-1:0] wb_dat; // wb data out - wire [`SPI_MAX_CHAR-1:0] rx; // Rx register - wire rx_negedge; // miso is sampled on negative edge - wire tx_negedge; // mosi is driven on negative edge - wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len - wire go; // go - wire lsb; // lsb first on line - wire ie; // interrupt enable - wire ass; // automatic slave select - wire spi_divider_sel; // divider register select - wire spi_ctrl_sel; // ctrl register select - wire [3:0] spi_tx_sel; // tx_l register select - wire spi_ss_sel; // ss register select - wire tip; // transfer in progress - wire pos_edge; // recognize posedge of sclk - wire neg_edge; // recognize negedge of sclk - wire last_bit; // marks last character bit - - // Address decoder - assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE); - assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); - assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); - assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); - assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_2); - assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_3); - assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); - - // Read from registers - always @(wb_adr_i or rx or ctrl or divider or ss) - begin - case (wb_adr_i[`SPI_OFS_BITS]) -`ifdef SPI_MAX_CHAR_128 - `SPI_RX_0: wb_dat = rx[31:0]; - `SPI_RX_1: wb_dat = rx[63:32]; - `SPI_RX_2: wb_dat = rx[95:64]; - `SPI_RX_3: wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]}; -`else -`ifdef SPI_MAX_CHAR_64 - `SPI_RX_0: wb_dat = rx[31:0]; - `SPI_RX_1: wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]}; - `SPI_RX_2: wb_dat = 32'b0; - `SPI_RX_3: wb_dat = 32'b0; -`else - `SPI_RX_0: wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]}; - `SPI_RX_1: wb_dat = 32'b0; - `SPI_RX_2: wb_dat = 32'b0; - `SPI_RX_3: wb_dat = 32'b0; -`endif -`endif - `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; - `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; - `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; - default: wb_dat = 32'bx; - endcase - end - - // Wb data out - always @(posedge wb_clk_i or posedge wb_rst_i) - begin - if (wb_rst_i) - wb_dat_o <= #Tp 32'b0; - else - wb_dat_o <= #Tp wb_dat; - end - - // Wb acknowledge - always @(posedge wb_clk_i or posedge wb_rst_i) - begin - if (wb_rst_i) - wb_ack_o <= #Tp 1'b0; - else - wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; - end - - // Wb error - assign wb_err_o = 1'b0; - - // Interrupt - always @(posedge wb_clk_i or posedge wb_rst_i) - begin - if (wb_rst_i) - wb_int_o <= #Tp 1'b0; - else if (ie && tip && last_bit && pos_edge) - wb_int_o <= #Tp 1'b1; - else if (wb_ack_o) - wb_int_o <= #Tp 1'b0; - end - - // Divider register - always @(posedge wb_clk_i or posedge wb_rst_i) - begin - if (wb_rst_i) - divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}}; - else if (spi_divider_sel && wb_we_i && !tip) - begin - `ifdef SPI_DIVIDER_LEN_8 - if (wb_sel_i[0]) - divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0]; - `endif - `ifdef SPI_DIVIDER_LEN_16 - if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; - if (wb_sel_i[1]) - divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8]; - `endif - `ifdef SPI_DIVIDER_LEN_24 - if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; - if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; - if (wb_sel_i[2]) - divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16]; - `endif - `ifdef SPI_DIVIDER_LEN_32 - if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; - if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; - if (wb_sel_i[2]) - divider[23:16] <= #Tp wb_dat_i[23:16]; - if (wb_sel_i[3]) - divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24]; - `endif - end - end - - // Ctrl register - always @(posedge wb_clk_i or posedge wb_rst_i) - begin - if (wb_rst_i) - ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}}; - else if(spi_ctrl_sel && wb_we_i && !tip) - begin - if (wb_sel_i[0]) - ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; - if (wb_sel_i[1]) - ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; - end - else if(tip && last_bit && pos_edge) - ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; - end - - assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; - assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; - assign go = ctrl[`SPI_CTRL_GO]; - assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; - assign lsb = ctrl[`SPI_CTRL_LSB]; - assign ie = ctrl[`SPI_CTRL_IE]; - assign ass = ctrl[`SPI_CTRL_ASS]; - - // Slave select register - always @(posedge wb_clk_i or posedge wb_rst_i) - begin - if (wb_rst_i) - ss <= #Tp {`SPI_SS_NB{1'b0}}; - else if(spi_ss_sel && wb_we_i && !tip) - begin - `ifdef SPI_SS_NB_8 - if (wb_sel_i[0]) - ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; - `endif - `ifdef SPI_SS_NB_16 - if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; - if (wb_sel_i[1]) - ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8]; - `endif - `ifdef SPI_SS_NB_24 - if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; - if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; - if (wb_sel_i[2]) - ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16]; - `endif - `ifdef SPI_SS_NB_32 - if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; - if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; - if (wb_sel_i[2]) - ss[23:16] <= #Tp wb_dat_i[23:16]; - if (wb_sel_i[3]) - ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24]; - `endif - end - end - - assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); - - spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), - .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), - .neg_edge(neg_edge)); - - spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), - .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb), - .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), - .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), - .tip(tip), .last(last_bit), - .p_in(wb_dat_i), .p_out(rx), - .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); -endmodule - diff --git a/opencores/spi/rtl/verilog/timescale.v b/opencores/spi/rtl/verilog/timescale.v deleted file mode 100644 index 60d4ecbd1..000000000 --- a/opencores/spi/rtl/verilog/timescale.v +++ /dev/null @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - diff --git a/opencores/spi/sim/CVS/Entries b/opencores/spi/sim/CVS/Entries deleted file mode 100644 index 545533337..000000000 --- a/opencores/spi/sim/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -D/rtl_sim//// -D/run//// diff --git a/opencores/spi/sim/CVS/Repository b/opencores/spi/sim/CVS/Repository deleted file mode 100644 index 9ec769309..000000000 --- a/opencores/spi/sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/sim diff --git a/opencores/spi/sim/CVS/Root b/opencores/spi/sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/sim/CVS/Template b/opencores/spi/sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/sim/rtl_sim/CVS/Entries b/opencores/spi/sim/rtl_sim/CVS/Entries deleted file mode 100644 index 8ab9f73a7..000000000 --- a/opencores/spi/sim/rtl_sim/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/run//// diff --git a/opencores/spi/sim/rtl_sim/CVS/Repository b/opencores/spi/sim/rtl_sim/CVS/Repository deleted file mode 100644 index c8c6a94c6..000000000 --- a/opencores/spi/sim/rtl_sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/sim/rtl_sim diff --git a/opencores/spi/sim/rtl_sim/CVS/Root b/opencores/spi/sim/rtl_sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/sim/rtl_sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/sim/rtl_sim/CVS/Template b/opencores/spi/sim/rtl_sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/sim/rtl_sim/run/CVS/Entries b/opencores/spi/sim/rtl_sim/run/CVS/Entries deleted file mode 100644 index 8947f64a0..000000000 --- a/opencores/spi/sim/rtl_sim/run/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -/rtl.fl/1.1/Mon Mar 15 17:46:08 2004// -/run_sim/1.1/Mon Mar 15 17:46:08 2004// -/sim.fl/1.1/Mon Mar 15 17:46:08 2004// -D diff --git a/opencores/spi/sim/rtl_sim/run/CVS/Repository b/opencores/spi/sim/rtl_sim/run/CVS/Repository deleted file mode 100644 index 5200bb196..000000000 --- a/opencores/spi/sim/rtl_sim/run/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/sim/rtl_sim/run diff --git a/opencores/spi/sim/rtl_sim/run/CVS/Root b/opencores/spi/sim/rtl_sim/run/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/sim/rtl_sim/run/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/sim/rtl_sim/run/CVS/Template b/opencores/spi/sim/rtl_sim/run/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi/sim/rtl_sim/run/rtl.fl b/opencores/spi/sim/rtl_sim/run/rtl.fl deleted file mode 100644 index d84a0840d..000000000 --- a/opencores/spi/sim/rtl_sim/run/rtl.fl +++ /dev/null @@ -1,3 +0,0 @@ -spi_top.v -spi_clgen.v -spi_shift.v diff --git a/opencores/spi/sim/rtl_sim/run/run_sim b/opencores/spi/sim/rtl_sim/run/run_sim deleted file mode 100755 index 1b13a35b9..000000000 --- a/opencores/spi/sim/rtl_sim/run/run_sim +++ /dev/null @@ -1,108 +0,0 @@ -#!/bin/csh -f - -set current_par = 0 -set output_waveform = 0 -while ( $current_par < $# ) - @ current_par = $current_par + 1 - case wave: - @ output_waveform = 1 - breaksw - default: - echo 'Unknown option "'$argv[$current_par]'"!' - exit - breaksw - endsw -end - -echo "TEST: spi" - -#echo "-CDSLIB ./cds.lib" > ncvlog.args -#echo "-HDLVAR ./hdl.var" >> ncvlog.args -echo "-MESSAGES" > ncvlog.args -echo "-INCDIR ../../../bench/verilog" >> ncvlog.args -echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args -echo "-NOCOPYRIGHT" >> ncvlog.args -echo "-UPDATE" >> ncvlog.args -echo "-LOGFILE ncvlog.log" >> ncvlog.args - -foreach filename ( `cat ./rtl.fl` ) - echo "../../../rtl/verilog/"$filename >> ncvlog.args -end - -foreach filename ( `cat ./sim.fl` ) - echo "../../../bench/verilog/"$filename >> ncvlog.args -end - -ncvlog -f ncvlog.args -if ($status != 0) then - echo "STATUS: failed" - exit -endif - - -echo "-MESSAGES" > ncelab.args -echo "-NOCOPYRIGHT" >> ncelab.args -#echo "-CDSLIB ./cds.lib" >> ncelab.args -#echo "-HDLVAR ./hdl.var" >> ncelab.args -echo "-LOGFILE ncelab.log" >> ncelab.args -echo "-SNAPSHOT worklib.tb_spi_top:v" >> ncelab.args -echo "-NOTIMINGCHECKS" >> ncelab.args -echo "-ACCESS +RWC" >> ncelab.args -echo "tb_spi_top" >> ncelab.args - -ncelab -f ncelab.args -if ($status != 0) then - echo "STATUS: failed" - exit -endif - - -echo "-MESSAGES" > ncsim.args -echo "-NOCOPYRIGHT" >> ncsim.args -#echo "-CDSLIB ./cds.lib" >> ncsim.args -#echo "-HDLVAR ./hdl.var" >> ncsim.args -echo "-INPUT ncsim.tcl" >> ncsim.args -echo "-LOGFILE ncsim.log" >> ncsim.args -echo "worklib.tb_spi_top:v" >> ncsim.args - -if ( $output_waveform ) then - echo "database -open waves -shm -into ../out/wav" > ./ncsim.tcl - echo "probe -create -database waves -shm tb_spi_top -all -depth all" >> ./ncsim.tcl - echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl - echo "run" >> ./ncsim.tcl -else - echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl - echo "run" > ./ncsim.tcl -endif - -echo "exit" >> ncsim.tcl - -ncsim -LICQUEUE -f ./ncsim.args - -set exit_line_nb = `sed -n '/exit/=' < ./ncsim.log` - -set dead_line_nb = 0 - -if ( $exit_line_nb ) then - - @ dead_line_nb = $exit_line_nb - 1 - set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ./ncsim.log` - set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ./ncsim.log` - - if ( "$dead_line" == "report (deaddead)" ) then - if ( "$exit_line" == "exit (00000000)" ) then - echo "STATUS: passed" #|tee -a ./run_sim.log 2>&1 - else - echo "STATUS: failed" #|tee -a ./run_sim.log 2>&1 - endif - else - echo "STATUS: failed" - endif - -endif - -exit - - - - diff --git a/opencores/spi/sim/rtl_sim/run/sim.fl b/opencores/spi/sim/rtl_sim/run/sim.fl deleted file mode 100644 index 283aad1f8..000000000 --- a/opencores/spi/sim/rtl_sim/run/sim.fl +++ /dev/null @@ -1,3 +0,0 @@ -tb_spi_top.v -wb_master_model.v -spi_slave_model.v diff --git a/opencores/spi/sim/run/CVS/Entries b/opencores/spi/sim/run/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/spi/sim/run/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/spi/sim/run/CVS/Repository b/opencores/spi/sim/run/CVS/Repository deleted file mode 100644 index e8646e70d..000000000 --- a/opencores/spi/sim/run/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi/sim/run diff --git a/opencores/spi/sim/run/CVS/Root b/opencores/spi/sim/run/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi/sim/run/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi/sim/run/CVS/Template b/opencores/spi/sim/run/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/COMPILE_LIST b/opencores/spi_boot/COMPILE_LIST deleted file mode 100644 index fc8f7d418..000000000 --- a/opencores/spi_boot/COMPILE_LIST +++ /dev/null @@ -1,33 +0,0 @@ - -Compile list for the spi_boot core -================================== -Version: $Date: 2005/04/14 21:26:22 $ - -bench/vhdl/tb.vhd -rtl/vhdl/spi_boot_pack-p.vhd -bench/vhdl/tb_pack-p.vhd -bench/vhdl/tb_elem.vhd -rtl/vhdl/chip-e.vhd -rtl/vhdl/chip-full-a.vhd -rtl/vhdl/spi_boot.vhd -rtl/vhdl/spi_counter.vhd -rtl/vhdl/spi_counter-c.vhd -rtl/vhdl/spi_boot-c.vhd -rtl/vhdl/chip-full-c.vhd -bench/vhdl/card.vhd -bench/vhdl/card-c.vhd -bench/vhdl/tb_elem-full-c.vhd -rtl/vhdl/chip-mmc-a.vhd -rtl/vhdl/chip-mmc-c.vhd -bench/vhdl/tb_elem-mmc-c.vhd -rtl/vhdl/chip-sd-a.vhd -rtl/vhdl/chip-sd-c.vhd -bench/vhdl/tb_elem-sd-c.vhd -rtl/vhdl/chip-minimal-a.vhd -rtl/vhdl/chip-minimal-c.vhd -bench/vhdl/tb_elem-minimal-c.vhd -bench/vhdl/tb-c.vhd -bench/vhdl/tb_rl.vhd -rtl/vhdl/sample/ram_loader.vhd -rtl/vhdl/sample/ram_loader-c.vhd -bench/vhdl/tb_rl-c.vhd diff --git a/opencores/spi_boot/COPYING b/opencores/spi_boot/COPYING deleted file mode 100644 index 60549be51..000000000 --- a/opencores/spi_boot/COPYING +++ /dev/null @@ -1,340 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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It is safest -to attach them to the start of each source file to most effectively -convey the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) 19yy - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - -Also add information on how to contact you by electronic and paper mail. - -If the program is interactive, make it output a short notice like this -when it starts in an interactive mode: - - Gnomovision version 69, Copyright (C) 19yy name of author - Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, the commands you use may -be called something other than `show w' and `show c'; they could even be -mouse-clicks or menu items--whatever suits your program. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the program, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the program - `Gnomovision' (which makes passes at compilers) written by James Hacker. - - , 1 April 1989 - Ty Coon, President of Vice - -This General Public License does not permit incorporating your program into -proprietary programs. If your program is a subroutine library, you may -consider it more useful to permit linking proprietary applications with the -library. If this is what you want to do, use the GNU Library General -Public License instead of this License. diff --git a/opencores/spi_boot/CVS/Entries b/opencores/spi_boot/CVS/Entries deleted file mode 100644 index d339433f3..000000000 --- a/opencores/spi_boot/CVS/Entries +++ /dev/null @@ -1,9 +0,0 @@ -/COMPILE_LIST/1.2/Thu Apr 14 21:26:22 2005// -/COPYING/1.1/Tue Feb 8 20:14:49 2005// -/KNOWN_BUGS/1.1/Sun Feb 13 18:28:35 2005// -/README/1.12/Thu Apr 14 21:32:58 2005// -D/bench//// -D/doc//// -D/rtl//// -D/sim//// -D/sw//// diff --git a/opencores/spi_boot/CVS/Repository b/opencores/spi_boot/CVS/Repository deleted file mode 100644 index 6aa579d49..000000000 --- a/opencores/spi_boot/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot diff --git a/opencores/spi_boot/CVS/Root b/opencores/spi_boot/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/CVS/Template b/opencores/spi_boot/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/KNOWN_BUGS b/opencores/spi_boot/KNOWN_BUGS deleted file mode 100644 index 298e4ba2e..000000000 --- a/opencores/spi_boot/KNOWN_BUGS +++ /dev/null @@ -1,4 +0,0 @@ - -Known bugs of the spi_boot core -=============================== -Version: $Date: 2005/02/13 18:28:35 $ diff --git a/opencores/spi_boot/README b/opencores/spi_boot/README deleted file mode 100644 index 926b35bff..000000000 --- a/opencores/spi_boot/README +++ /dev/null @@ -1,170 +0,0 @@ - -README for the spi_boot core -============================ -Version: $Date: 2005/04/14 21:32:58 $ - - -Description ------------ - -The SD/MMC Bootloader is a CPLD design that manages configuration and -bootstrapping of FPGAs. It is able to retrieve the required data from -SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA -configuration process. SD cards as well as MMCs are operated in SPI mode which -is part of both standards thus eliminating the need for dedicated -implementations. The SD/MMC Bootloader fits both. Beyond configuration, this -core supports a bootstrapping strategy where multiple images are stored on one -single memory card. -For example consider a system completely based on SRAM. The bootloader -provides the initial configuration data from the first image to the FPGA. This -image contains a design which pulls the next image from the memory card and -transfers this data to SRAM. In the third step the final FPGA design is loaded -from the third image. -These images are clustered in sets which can be selected by external switches -for example. Several configuration sets can be stored on one memory card -allowing you to provide a number of applications which are downloaded quickly -to the FPGA. -The schematic (rev. B) shows how the core can be used with an FPGA board. I -use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300 -board. SV2 fits the "SERIAL MODE" connector on this board but you will have to -add a separate wire from R6 to attach INIT. Please check the proper use of the -pull-up resistors for your specific board. - - -Features --------- - -* Configuration mode: configures SRAM based FPGAs via slave serial mode - (Xilinx and Altera) -* Data mode: provides stored data over a simple synchronous serial interface -* Broad compatability using SPI mode - + SecureDigital cards using dedicated initialization command - + MultiMediaCards (see below) -* Operation triggerd by power-up or card insertion -* Multiple configuration sets stored on on single memory card - - -Compatability -------------- - -These cards have been tested with the SD/MMC Bootloader: - - * Hama 64 MB SD - * SanDisk 128 MB SD - * SanDisk 64 MB MMC - * Panasonic 32 MB SD - -Some MMC might fail with this core as not all cards support CMD18 -(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific -model. In case your MMC does not implement CMD18 you might want to have a look -at the FPGA MMC-Card Config project. - - -Tools ------ - -Downloading the configuration data to the card is a straight forward -process. The images have to be written starting at dedicated locations. For -the provided toplevel designs, these locations are multiples of 256 K. I.e. 0, -0x40000, 0x80000 and so forth. - -dd (part of the GNU coreutils) serves this purpose: -$ dd if=ram_loader.bin of=/dev/sdX bs=512 -$ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512 -$ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024 - -The name of the device node depends on how the card reader is attached to the -kernel. For Linux systems this is most often something like /dev/sdX with X -ranging from a-z. Please note that it is essential to use the device without -any trailing numbers as they refer to partitions leading to wrong offsets for -data written to the card. -All this works perfectly for my Spartan IIe device as this FPGA expects the -configuration data as it is delivered from the card: Consecutive bytes each -with its most significant bit first. Altera devices like the FLEX family are -different here. They expect the bytes with least significant bit -first. Therefore, the configuration data has to be swapped bitwise before it -is written to the card. - - -Verification ------------- - -The spi_boot core comes with a simple testbench that simulates an SD/MMC -card. All four implementations of the core are verified there in parallel -while transferring the data for several sets. -You should normally not need to run the testbench. But in case you modified -the VHDL code the testbench gives some hints if the design has been broken. - - -Directory Structure -------------------- - -The core's directory structure follows the proposal of OpenCores.org. - -spi_boot - | - \--+-- doc : Documentation - | | - | \-- src : Source files of documentation - | - +-- rtl - | | - | \-- vhdl : VHDL code containing the RTL description - | of the core. - | - +-- bench - | | - | \-- vhdl : VHDL testbench code. - | - \-- sim - | - \-- rtl_sim : Directory for running simulations. - - -RAM Loader ----------- - -Directory rtl/vhdl/ram_loader contains the sample design which loads the next -image from the card and stores its contents to external asynchronous -RAM. After reading 64 KB it triggers a new configuration process for the final -FPGA design. -Refer to the code for the mechanisms involved. - - -Compiling the VHDL Code ------------------------ - -VHDL compilation and simulation tasks take place inside in sim/rtl_sim -directory. The project setup supports only the GHDL simulator (see -http://ghdl.free.fr). - -To compile the code simply type at the shell - -$ make - -This should result in a file called tb_behav_c0 which can be executed as any -other executable. - -The basic simple sequence list can be found in COMPILE_LIST. This can be -useful to quickly set up the analyze stage of any compiler or -synthesizer. Especially when synthesizing the code, you want to skip the VHDL -configurations in *-c.vhd and everything below the bench/ directory. - - -References ----------- - - * SanDisk SD Card Product Manual - http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf - - * SanDisk MMC Product Manual - http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf - - * Toshiba SD Card Specification - http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf - - * BurchED - http://burched.biz/ - - * FPGA MMC-Card Config project - http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview diff --git a/opencores/spi_boot/bench/CVS/Entries b/opencores/spi_boot/bench/CVS/Entries deleted file mode 100644 index a4756ee6f..000000000 --- a/opencores/spi_boot/bench/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/vhdl//// diff --git a/opencores/spi_boot/bench/CVS/Repository b/opencores/spi_boot/bench/CVS/Repository deleted file mode 100644 index ac45542a6..000000000 --- a/opencores/spi_boot/bench/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/bench diff --git a/opencores/spi_boot/bench/CVS/Root b/opencores/spi_boot/bench/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/bench/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/bench/CVS/Template b/opencores/spi_boot/bench/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/bench/vhdl/CVS/Entries b/opencores/spi_boot/bench/vhdl/CVS/Entries deleted file mode 100644 index 8649c9f90..000000000 --- a/opencores/spi_boot/bench/vhdl/CVS/Entries +++ /dev/null @@ -1,13 +0,0 @@ -/card-c.vhd/1.1/Tue Feb 8 21:09:18 2005// -/card.vhd/1.2/Sun Feb 13 17:06:22 2005// -/tb-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem-full-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem-minimal-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem-mmc-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem-sd-c.vhd/1.1/Tue Feb 8 21:09:20 2005// -/tb_elem.vhd/1.7/Thu Apr 7 20:43:36 2005// -/tb_pack-p.vhd/1.2/Tue Mar 8 22:06:39 2005// -/tb_rl-c.vhd/1.1/Sun Apr 10 18:07:26 2005// -/tb_rl.vhd/1.1/Sun Apr 10 18:07:25 2005// -D diff --git a/opencores/spi_boot/bench/vhdl/CVS/Repository b/opencores/spi_boot/bench/vhdl/CVS/Repository deleted file mode 100644 index ce62c2b8e..000000000 --- a/opencores/spi_boot/bench/vhdl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/bench/vhdl diff --git a/opencores/spi_boot/bench/vhdl/CVS/Root b/opencores/spi_boot/bench/vhdl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/bench/vhdl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/bench/vhdl/CVS/Template b/opencores/spi_boot/bench/vhdl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/bench/vhdl/card-c.vhd b/opencores/spi_boot/bench/vhdl/card-c.vhd deleted file mode 100644 index 797eb1c90..000000000 --- a/opencores/spi_boot/bench/vhdl/card-c.vhd +++ /dev/null @@ -1,14 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: card-c.vhd,v 1.1 2005/02/08 21:09:18 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration card_behav_c0 of card is - - for behav - end for; - -end card_behav_c0; diff --git a/opencores/spi_boot/bench/vhdl/card.vhd b/opencores/spi_boot/bench/vhdl/card.vhd deleted file mode 100644 index dcd676095..000000000 --- a/opencores/spi_boot/bench/vhdl/card.vhd +++ /dev/null @@ -1,446 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Simple SD and MMC model --- --- $Id: card.vhd,v 1.2 2005/02/13 17:06:22 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity card is - - generic ( - card_type_g : string := "none"; - is_sd_card_g : integer := 1 - ); - - port ( - spi_clk_i : in std_logic; - spi_cs_n_i : in std_logic; - spi_data_i : in std_logic; - spi_data_o : out std_logic - ); - -end card; - - -library ieee; -use ieee.numeric_std.all; -library std; -use std.textio.all; - -use work.tb_pack.all; - -architecture behav of card is - - signal power_on_n_s : std_logic; - signal soft_res_n_s : std_logic; - signal res_n_s : std_logic; - - signal rx_s : std_logic_vector(47 downto 0); - - signal set_spi_mode_s, - spi_mode_q : boolean; - signal set_idle_mode_s, - poll_idle_mode_s : boolean; - signal idle_mode_q : natural; - - signal block_len_q, - block_len_s : unsigned(31 downto 0); - signal set_block_len_s : boolean; - - signal new_read_addr_s, - read_addr_q : unsigned(31 downto 0); - signal set_read_addr_s, - inc_read_addr_s : boolean; - - signal cmd_spi_data_s, - read_spi_data_s : std_logic; - signal start_read_s : boolean; - signal reading_s : boolean; - - procedure rise_clk is - begin - wait until spi_clk_i'event and to_X01(spi_clk_i) = '1'; - end rise_clk; - --- procedure rise_clk(num : natural) is --- begin --- for i in 1 to num loop --- rise_clk; --- end loop; --- end rise_clk; - - procedure fall_clk is - begin - wait until spi_clk_i'event and to_X01(spi_clk_i) = '0'; - end fall_clk; - - procedure fall_clk(num : natural) is - begin - for i in 1 to num loop - fall_clk; - end loop; - end fall_clk; - -begin - - res_n_s <= power_on_n_s and soft_res_n_s; - - ----------------------------------------------------------------------------- - -- Power on reset - ----------------------------------------------------------------------------- - por: process - begin - power_on_n_s <= '0'; - wait for 200 ns; - power_on_n_s <= '1'; - wait; - end process por; - - - ----------------------------------------------------------------------------- - -- - ctrl: process - - function check_crc(payload : in std_logic_vector(47 downto 0)) - return boolean is - - begin - - return calc_crc(payload(47 downto 8)) = payload(7 downto 1); - end check_crc; - - variable rx_v : std_logic_vector(47 downto 0); - variable cmd_v : std_logic_vector( 5 downto 0); - variable arg_v : std_logic_vector(31 downto 0); - variable crc_v : std_logic_vector( 6 downto 0); - variable wrong_v : std_logic; - variable read_data_v : boolean; - - begin - rx_s <= (others => '0'); - set_spi_mode_s <= false; - set_idle_mode_s <= false; - poll_idle_mode_s <= false; - cmd_spi_data_s <= '1'; - soft_res_n_s <= '1'; - set_block_len_s <= false; - block_len_s <= (others => '0'); - new_read_addr_s <= (others => '0'); - set_read_addr_s <= false; - start_read_s <= false; - read_data_v := false; - - loop - - rise_clk; - -- wait for startbit of command - while to_X01(spi_data_i) = '1' loop - rise_clk; - end loop; - rx_v(47) := '0'; - - -- read remaining 47 bits of command - for i in 46 downto 0 loop - rise_clk; - rx_v(i) := to_X01(spi_data_i); - end loop; - rx_s <= rx_v; - - -- dissect received data - cmd_v := rx_v(45 downto 40); - arg_v := rx_v(39 downto 8); - crc_v := rx_v( 7 downto 1); - - assert spi_mode_q or check_crc(payload => rx_v) - report "CRC mismatch" - severity error; - - wrong_v := '0'; - case cmd_v is - -- CMD0: GO_IDLE_STATE ------------------------------------------------ - when "000000" => - set_spi_mode_s <= true; - set_idle_mode_s <= true; - -- CMD1: SEND_OP_COND ------------------------------------------------- - when "000001" => - poll_idle_mode_s <= true; - -- CMD12: STOP_TRANSMISSION ------------------------------------------- - when "001100" => - start_read_s <= false; - read_data_v := false; - -- CMD16: SET_BLOCKLEN ------------------------------------------------ - when "010000" => - block_len_s <= unsigned(arg_v); - set_block_len_s <= true; - -- CMD18: READ_MULTIPLE_BLOCK ----------------------------------------- - when "010010" => - new_read_addr_s <= unsigned(arg_v); - set_read_addr_s <= true; - read_data_v := true; - -- CMD55: APPL_CMD ---------------------------------------------------- - when "110111" => - -- command only available for SD card - if is_sd_card_g /= 1 then - wrong_v := '1'; - end if; - -- ACMD41: SEND_OP_COND ----------------------------------------------- - when "101001" => - -- command only available for SD card - if is_sd_card_g /= 1 then - wrong_v := '1'; - else - poll_idle_mode_s <= true; - end if; - - when others => - wrong_v := '1'; - null; - end case; - - - -- spend some time before removing control signals - fall_clk(2); - poll_idle_mode_s <= false; - set_idle_mode_s <= false; - fall_clk(6); - set_spi_mode_s <= false; - set_block_len_s <= false; - set_read_addr_s <= false; - - if reading_s then - wait until not reading_s; - end if; - - - -- wait for a total two "bytes" before sending out response - for i in 1 to 8 loop - fall_clk; - end loop; - - for i in 7 downto 0 loop - fall_clk; - case i is - when 2 => - cmd_spi_data_s <= wrong_v; - when 0 => - if idle_mode_q = 0 then - cmd_spi_data_s <= '0'; - else - cmd_spi_data_s <= '1'; - end if; - when others => - cmd_spi_data_s <= '0'; - end case; - end loop; - fall_clk; - cmd_spi_data_s <= '1'; - - -- transmit data if requested - start_read_s <= read_data_v; - - end loop; - end process ctrl; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- - seq: process (res_n_s, - spi_clk_i, - set_spi_mode_s, - set_idle_mode_s, - poll_idle_mode_s, - set_block_len_s, - block_len_s) - - begin - if res_n_s = '0' then - spi_mode_q <= false; - idle_mode_q <= 5; - block_len_q <= (others => '0'); - read_addr_q <= (others => '0'); - - elsif spi_clk_i'event and spi_clk_i = '1' then - if set_spi_mode_s then - spi_mode_q <= true; - end if; - - if set_idle_mode_s then - idle_mode_q <= 5; - elsif poll_idle_mode_s then - if idle_mode_q > 0 then - idle_mode_q <= idle_mode_q - 1; - end if; - end if; - - if set_block_len_s then - block_len_q <= block_len_s; - end if; - - if set_read_addr_s then - read_addr_q <= new_read_addr_s; - elsif inc_read_addr_s then - read_addr_q <= read_addr_q + 1; - end if; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- - read_block: process - - variable t_v : unsigned(7 downto 0); - - begin - -- default assignments - inc_read_addr_s <= false; - reading_s <= false; - read_spi_data_s <= '1'; - - loop - if not start_read_s then - wait until start_read_s; - end if; - - reading_s <= true; - - fall_clk(8); -- delay for one "byte" - - -- send data token - fall_clk(7); -- 7 ones in a data token - read_spi_data_s <= '0'; - - -- send payload - payload: for i in 0 to to_integer(block_len_q)-1 loop - t_v := read_addr_q(0) & calc_crc(read_addr_q); - for bit in 7 downto 0 loop - fall_clk; - read_spi_data_s <= t_v(bit); - - exit payload when not start_read_s; - end loop; - inc_read_addr_s <= true; - rise_clk; - inc_read_addr_s <= false; - wait for 10 ns; - end loop; - - if start_read_s then - -- send crc - for i in 0 to 15 loop - fall_clk; - t_v := to_unsigned(i, 8); - read_spi_data_s <= t_v(0); - end loop; - fall_clk; - end if; - - read_spi_data_s <= '1'; - reading_s <= false; - -- loop for one "byte" - fall_clk(8); - - end loop; - end process read_block; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- - clk_check: process (spi_clk_i) - - variable last_rising_v : time := 0 ns; - variable dump_line : line; - - begin - if spi_clk_i'event and spi_clk_i = '1' then - if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and - idle_mode_q > 0 then - if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then - write(dump_line, card_type_g); - write(dump_line, string'(" @ ")); - write(dump_line, now); - write(dump_line, string'(": Last rising edge of SPI clock ")); - write(dump_line, now - last_rising_v); - write(dump_line, string'(" ago.")); - writeline(output, dump_line); - end if; - - last_rising_v := now; - end if; - end if; - end process clk_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - spi_data_o <= cmd_spi_data_s and read_spi_data_s - when spi_cs_n_i = '0' else - 'Z'; - -end behav; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: card.vhd,v $ --- Revision 1.2 2005/02/13 17:06:22 arniml --- handle termination properly --- --- Revision 1.1 2005/02/08 21:09:20 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/bench/vhdl/tb-c.vhd b/opencores/spi_boot/bench/vhdl/tb-c.vhd deleted file mode 100644 index caa171362..000000000 --- a/opencores/spi_boot/bench/vhdl/tb-c.vhd +++ /dev/null @@ -1,31 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_behav_c0 of tb is - - for behav - - for tb_elem_full_b : tb_elem - use configuration work.tb_elem_behav_full; - end for; - - for tb_elem_mmc_b : tb_elem - use configuration work.tb_elem_behav_mmc; - end for; - - for tb_elem_sd_b : tb_elem - use configuration work.tb_elem_behav_sd; - end for; - - for tb_elem_minimal_b : tb_elem - use configuration work.tb_elem_behav_minimal; - end for; - - end for; - -end tb_behav_c0; diff --git a/opencores/spi_boot/bench/vhdl/tb.vhd b/opencores/spi_boot/bench/vhdl/tb.vhd deleted file mode 100644 index b359fa7c5..000000000 --- a/opencores/spi_boot/bench/vhdl/tb.vhd +++ /dev/null @@ -1,201 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Testbench --- --- $Id: tb.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -entity tb is - -end tb; - - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb is - - component tb_elem - generic ( - chip_type_g : string := "none"; - has_sd_card_g : integer := 1 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - eos_o : out boolean - ); - end component; - - constant period_c : time := 100 ns; - constant reset_level_c : integer := 0; - - signal clk_s : std_logic; - signal reset_s : std_logic; - - signal eos_full_s, - eos_mmc_s, - eos_sd_s, - eos_minimal_s : boolean; - -begin - - - ----------------------------------------------------------------------------- - -- Testbench element including full featured chip - ----------------------------------------------------------------------------- - tb_elem_full_b : tb_elem - generic map ( - chip_type_g => "Full Chip", - has_sd_card_g => 1 - ) - port map ( - clk_i => clk_s, - reset_i => reset_s, - eos_o => eos_full_s - ); - - - ----------------------------------------------------------------------------- - -- Testbench element including MMC chip - ----------------------------------------------------------------------------- - tb_elem_mmc_b : tb_elem - generic map ( - chip_type_g => "MMC Chip", - has_sd_card_g => 0 - ) - port map ( - clk_i => clk_s, - reset_i => reset_s, - eos_o => eos_mmc_s - ); - - - ----------------------------------------------------------------------------- - -- Testbench element including SD chip - ----------------------------------------------------------------------------- - tb_elem_sd_b : tb_elem - generic map ( - chip_type_g => "SD Chip", - has_sd_card_g => 1 - ) - port map ( - clk_i => clk_s, - reset_i => reset_s, - eos_o => eos_sd_s - ); - - - ----------------------------------------------------------------------------- - -- Testbench element including cip with minimal features - ----------------------------------------------------------------------------- - tb_elem_minimal_b : tb_elem - generic map ( - chip_type_g => "Minimal Chip", - has_sd_card_g => 0 - ) - port map ( - clk_i => clk_s, - reset_i => reset_s, - eos_o => eos_minimal_s - ); - - - ----------------------------------------------------------------------------- - -- Clock Generator - ----------------------------------------------------------------------------- - clk: process - begin - clk_s <= '0'; - wait for period_c / 2; - clk_s <= '1'; - wait for period_c / 2; - end process clk; - - - ----------------------------------------------------------------------------- - -- Reset Generator - ----------------------------------------------------------------------------- - reset: process - begin - if reset_level_c = 0 then - reset_s <= '0'; - else - reset_s <= '1'; - end if; - - wait for period_c * 4 + 10 ns; - - reset_s <= not reset_s; - - wait; - end process reset; - - - ----------------------------------------------------------------------------- - -- End Of Simulation Detection - ----------------------------------------------------------------------------- - eos: process (eos_full_s, - eos_mmc_s, - eos_sd_s, - eos_minimal_s) - begin - - if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then - assert false - report "End of Simulation." - severity failure; - end if; - - end process eos; - -end behav; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: tb.vhd,v $ --- Revision 1.1 2005/02/08 21:09:20 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd b/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd deleted file mode 100644 index 3c0fb902f..000000000 --- a/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_elem-full-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_elem_behav_full of tb_elem is - - for behav - - for dut_b : chip - use configuration work.chip_full_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - end for; - -end tb_elem_behav_full; diff --git a/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd b/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd deleted file mode 100644 index 1c33ac3d0..000000000 --- a/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_elem-minimal-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_elem_behav_minimal of tb_elem is - - for behav - - for dut_b : chip - use configuration work.chip_minimal_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - end for; - -end tb_elem_behav_minimal; diff --git a/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd b/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd deleted file mode 100644 index b5baf604e..000000000 --- a/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_elem-mmc-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_elem_behav_mmc of tb_elem is - - for behav - - for dut_b : chip - use configuration work.chip_mmc_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - end for; - -end tb_elem_behav_mmc; diff --git a/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd b/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd deleted file mode 100644 index 9cdf3eaa1..000000000 --- a/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_elem-sd-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_elem_behav_sd of tb_elem is - - for behav - - for dut_b : chip - use configuration work.chip_sd_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - end for; - -end tb_elem_behav_sd; diff --git a/opencores/spi_boot/bench/vhdl/tb_elem.vhd b/opencores/spi_boot/bench/vhdl/tb_elem.vhd deleted file mode 100644 index 689cec037..000000000 --- a/opencores/spi_boot/bench/vhdl/tb_elem.vhd +++ /dev/null @@ -1,376 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Generic testbench element for a specific feature set --- --- $Id: tb_elem.vhd,v 1.7 2005/04/07 20:43:36 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity tb_elem is - - generic ( - chip_type_g : string := "none"; - has_sd_card_g : integer := 1 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - eos_o : out boolean - ); - -end tb_elem; - - -library ieee; -use ieee.numeric_std.all; -library std; -use std.textio.all; - -use work.spi_boot_pack.all; -use work.tb_pack.all; - -architecture behav of tb_elem is - - component chip - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_n_i : in std_logic_vector(3 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - component card - generic ( - card_type_g : string := "none"; - is_sd_card_g : integer := 1 - ); - port ( - spi_clk_i : in std_logic; - spi_cs_n_i : in std_logic; - spi_data_i : in std_logic; - spi_data_o : out std_logic - ); - end component; - - signal reset_s : std_logic; - - -- SPI interface signals - signal spi_clk_s : std_logic; - signal spi_data_to_card_s : std_logic; - signal spi_data_from_card_s : std_logic; - signal spi_cs_n_s : std_logic; - - -- config related signals - signal start_s : std_logic; - signal mode_s : std_logic; - signal config_n_s : std_logic; - signal cfg_init_n_s : std_logic; - signal cfg_done_s : std_logic; - signal dat_done_s : std_logic; - signal cfg_clk_s : std_logic; - signal cfg_dat_s : std_logic; - signal data_s : unsigned(7 downto 0); - - signal set_sel_n_s : std_logic_vector(3 downto 0); - - constant verbose_c : boolean := false; - -begin - - -- weak pull-ups - spi_clk_s <= 'H'; - spi_cs_n_s <= 'H'; - spi_data_to_card_s <= 'H'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - dut_b : chip - port map ( - clk_i => clk_i, - reset_i => reset_s, - set_sel_n_i => set_sel_n_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_from_card_s, - spi_data_out_o => spi_data_to_card_s, - start_i => start_s, - mode_i => mode_s, - config_n_o => config_n_s, - detached_o => open, - cfg_init_n_i => cfg_init_n_s, - cfg_done_i => cfg_done_s, - dat_done_i => dat_done_s, - cfg_clk_o => cfg_clk_s, - cfg_dat_o => cfg_dat_s - ); - - card_b : card - generic map ( - card_type_g => chip_type_g, - is_sd_card_g => has_sd_card_g - ) - port map ( - spi_clk_i => spi_clk_s, - spi_cs_n_i => spi_cs_n_s, - spi_data_i => spi_data_to_card_s, - spi_data_o => spi_data_from_card_s - ); - - - ----------------------------------------------------------------------------- - -- DUT Stimuli - -- - stim: process - - procedure rise_cfg_clk(num : integer) is - begin - for i in 1 to num loop - wait until cfg_clk_s'event and cfg_clk_s = '1'; - end loop; - end rise_cfg_clk; - --- procedure fall_cfg_clk(num : integer) is --- begin --- for i in 1 to num loop --- wait until cfg_clk_s'event and cfg_clk_s = '0'; --- end loop; --- end fall_cfg_clk; - - procedure rise_clk(num : integer) is - begin - for i in 1 to num loop - wait until clk_i'event and clk_i = '1'; - end loop; - end rise_clk; - - procedure read_check_byte(ref : unsigned(7 downto 0)) is - variable byte_v : unsigned(7 downto 0); - variable dump_line : line; - begin - for bit in 7 downto 0 loop - rise_cfg_clk(1); - byte_v(bit) := cfg_dat_s; - end loop; - data_s <= byte_v; - - if byte_v /= ref then - write(dump_line, chip_type_g); - write(dump_line, string'(" at ")); - write(dump_line, now); - write(dump_line, string'(": read_check_byte failed ")); - write(dump_line, to_integer(byte_v)); - write(dump_line, string'(" ")); - write(dump_line, to_integer(ref)); - writeline(output, dump_line); - end if; - end read_check_byte; - - variable dump_line : line; - variable addr_v : unsigned(31 downto 0); - variable temp_v : unsigned( 7 downto 0); - variable set_sel_v : unsigned(3 downto 0); - - begin - -- default assignments - -- these defaults show the required pull resistors - -- except start_i as this must be pulled high for automatic start - start_s <= '0'; - mode_s <= '1'; - cfg_init_n_s <= '1'; - cfg_done_s <= '0'; - dat_done_s <= '1'; - data_s <= (others => '1'); - addr_v := (others => '0'); - eos_o <= false; - set_sel_n_s <= (others => '1'); - reset_s <= '0'; - - -- loop through some sets - for set in 0 to 3 loop - set_sel_v := to_unsigned(set, 4); - addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g - -- plus width_img_cnt_g - set_sel_n_s <= not std_logic_vector(set_sel_v); - - assert not verbose_c - report chip_type_g & ": Processing set " & to_string(set) - severity note; - - wait for 100 us; - reset_s <= '1'; - - assert not verbose_c - report chip_type_g & ": Requesting image 0" - severity note; - - -- signal start - start_s <= '1'; - mode_s <= '1'; - cfg_done_s <= '0'; - addr_v(19 downto 0) := (others => '0'); - wait until config_n_s = '0'; - -- run through configuration sequence - rise_clk(1); - cfg_init_n_s <= '0'; - rise_clk(3); - cfg_init_n_s <= '1'; - - -- and receive 32 bytes from image 0 - for i in 1 to 32 loop - temp_v := addr_v(0) & calc_crc(addr_v); - read_check_byte(temp_v); - addr_v := addr_v + 1; - end loop; - start_s <= '0'; - cfg_done_s <= '1'; - - rise_clk(10); - - assert not verbose_c - report chip_type_g & ": Requesting image 1" - severity note; - - -- request next image - mode_s <= '0'; - start_s <= '1'; - addr_v(17 downto 0) := (others => '0'); - addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd - dat_done_s <= '0'; - - -- receive another 32 bytes from image 1 - for i in 1 to 32 loop - temp_v := addr_v(0) & calc_crc(addr_v); - read_check_byte(temp_v); - addr_v := addr_v + 1; - end loop; - start_s <= '0'; - dat_done_s <= '1'; - - - rise_clk(10); - - assert not verbose_c - report chip_type_g & ": Requesting image 2" - severity note; - - -- request next image - mode_s <= '1'; - start_s <= '1'; - addr_v(17 downto 0) := (others => '0'); - addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd - - wait until config_n_s = '0'; - -- run through configuration sequence - rise_clk(1); - cfg_done_s <= '0'; - cfg_init_n_s <= '0'; - rise_clk(3); - cfg_init_n_s <= '1'; - - -- receive another 32 bytes from image 2 - for i in 1 to 32 loop - temp_v := addr_v(0) & calc_crc(addr_v); - read_check_byte(temp_v); - addr_v := addr_v + 1; - end loop; - start_s <= '0'; - cfg_done_s <= '1'; - - -- give dut a chance to stop current transfer - wait until spi_cs_n_s = '1'; - rise_clk(10); - - reset_s <= '0'; - end loop; - - eos_o <= true; - wait; - end process stim; - -- - ----------------------------------------------------------------------------- - -end behav; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: tb_elem.vhd,v $ --- Revision 1.7 2005/04/07 20:43:36 arniml --- add new port detached_o --- --- Revision 1.6 2005/03/09 19:48:04 arniml --- make verbosity level switchable --- --- Revision 1.5 2005/03/08 22:06:21 arniml --- added set selection --- --- Revision 1.4 2005/02/17 18:59:23 arniml --- clarify wording for images --- --- Revision 1.3 2005/02/16 19:34:56 arniml --- add weak pull-ups for SPI lines --- --- Revision 1.2 2005/02/13 17:14:03 arniml --- change dat_done handling --- --- Revision 1.1 2005/02/08 21:09:20 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd b/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd deleted file mode 100644 index 7534aafdc..000000000 --- a/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd +++ /dev/null @@ -1,93 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_pack-p.vhd,v 1.2 2005/03/08 22:06:39 arniml Exp $ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package tb_pack is - - function calc_crc(payload : in std_logic_vector) return std_logic_vector; - function calc_crc(payload : in unsigned) return unsigned; - - function to_string(value : in integer) return string; - -end tb_pack; - - -package body tb_pack is - - function calc_crc(payload : in std_logic_vector) return std_logic_vector is - - variable crc_v : std_logic_vector(6 downto 0); - variable temp_v : std_logic; - - begin - - crc_v := (others => '0'); - - for i in payload'high downto payload'low loop - temp_v := payload(i) xor crc_v(6); - - crc_v(6 downto 4) := crc_v(5 downto 3); - crc_v(3) := crc_v(2) xor temp_v; - crc_v(2 downto 1) := crc_v(1 downto 0); - crc_v(0) := temp_v; - end loop; - - return crc_v; - end calc_crc; - - function calc_crc(payload : in unsigned) return unsigned is - begin - return unsigned(calc_crc(std_logic_vector(payload))); - end calc_crc; - - function to_string(value : in integer) return string is - variable str: string (11 downto 1); - variable val: integer := value; - variable digit: natural; - variable index: natural := 0; - begin - -- Taken from: - -- textio package body. This file is part of GHDL. - -- Copyright (C) 2002 Tristan Gingold. - -- Note: the absolute value of VAL cannot be directly taken, since - -- it may be greather that the maximum value of an INTEGER. - loop - -- LRM93 7.2.6 - -- (A rem B) has the sign of A and an absolute value less then - -- the absoulte value of B. - digit := abs (val rem 10); - val := val / 10; - index := index + 1; - str (index) := character'val(48 + digit); - exit when val = 0; - end loop; - if value < 0 then - index := index + 1; - str(index) := '-'; - end if; - - return str; - end to_string; - -end tb_pack; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: tb_pack-p.vhd,v $ --- Revision 1.2 2005/03/08 22:06:39 arniml --- added integer->string conversion function --- --- Revision 1.1 2005/02/08 21:09:20 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd b/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd deleted file mode 100644 index 84273abc5..000000000 --- a/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd +++ /dev/null @@ -1,27 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: tb_rl-c.vhd,v 1.1 2005/04/10 18:07:26 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration tb_rl_behav_c0 of tb_rl is - - for behav - - for dut_b : chip - use configuration work.chip_full_c0; - end for; - - for card_b : card - use configuration work.card_behav_c0; - end for; - - for rl_b : ram_loader - use configuration work.ram_loader_rtl_c0; - end for; - - end for; - -end tb_rl_behav_c0; diff --git a/opencores/spi_boot/bench/vhdl/tb_rl.vhd b/opencores/spi_boot/bench/vhdl/tb_rl.vhd deleted file mode 100644 index 9f28e62b4..000000000 --- a/opencores/spi_boot/bench/vhdl/tb_rl.vhd +++ /dev/null @@ -1,259 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Testbench for ram_loader --- --- $Id: tb_rl.vhd,v 1.1 2005/04/10 18:07:25 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -entity tb_rl is - -end tb_rl; - - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_rl is - - component chip - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_n_i : in std_logic_vector(3 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - component card - generic ( - card_type_g : string := "none"; - is_sd_card_g : integer := 1 - ); - port ( - spi_clk_i : in std_logic; - spi_cs_n_i : in std_logic; - spi_data_i : in std_logic; - spi_data_o : out std_logic - ); - end component; - - component ram_loader - port ( - clk_i : in std_logic; - reset_i : in std_logic; - lamp_o : out std_logic; - cfg_clk_i : in std_logic; - cfg_data_i : in std_logic; - start_o : out std_logic; - mode_o : out std_logic; - done_o : out std_logic; - detached_i : in std_logic; - ram_addr_o : out std_logic_vector(15 downto 0); - ram_data_b : out std_logic_vector( 7 downto 0); - ram_ce_no : out std_logic_vector( 3 downto 0); - ram_oe_no : out std_logic; - ram_we_no : out std_logic - ); - end component; - - constant period_c : time := 100 ns; - constant rl_period_c : time := 20 ns; - constant reset_level_c : integer := 0; - - signal clk_s : std_logic; - signal rl_clk_s: std_logic; - signal reset_s : std_logic; - - -- SPI interface signals - signal spi_clk_s : std_logic; - signal spi_data_to_card_s : std_logic; - signal spi_data_from_card_s : std_logic; - signal spi_cs_n_s : std_logic; - - -- config related signals - signal start_s : std_logic; - signal mode_s : std_logic; - signal config_n_s : std_logic; - signal cfg_init_n_s : std_logic; - signal cfg_done_s : std_logic; - signal dat_done_s : std_logic; - signal cfg_clk_s : std_logic; - signal cfg_dat_s : std_logic; - signal detached_s : std_logic; - - signal set_sel_n_s : std_logic_vector(3 downto 0); - -begin - - set_sel_n_s <= (others => '1'); - cfg_init_n_s <= '1'; - cfg_done_s <= '1'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - dut_b : chip - port map ( - clk_i => clk_s, - reset_i => reset_s, - set_sel_n_i => set_sel_n_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_from_card_s, - spi_data_out_o => spi_data_to_card_s, - start_i => start_s, - mode_i => mode_s, - config_n_o => config_n_s, - detached_o => detached_s, - cfg_init_n_i => cfg_init_n_s, - cfg_done_i => cfg_done_s, - dat_done_i => dat_done_s, - cfg_clk_o => cfg_clk_s, - cfg_dat_o => cfg_dat_s - ); - - card_b : card - generic map ( - card_type_g => "Full Chip", - is_sd_card_g => 1 - ) - port map ( - spi_clk_i => spi_clk_s, - spi_cs_n_i => spi_cs_n_s, - spi_data_i => spi_data_to_card_s, - spi_data_o => spi_data_from_card_s - ); - - rl_b : ram_loader - port map ( - clk_i => rl_clk_s, - reset_i => reset_s, - lamp_o => open, - cfg_clk_i => cfg_clk_s, - cfg_data_i => cfg_dat_s, - start_o => start_s, - mode_o => mode_s, - done_o => dat_done_s, - detached_i => detached_s, - ram_addr_o => open, - ram_data_b => open, - ram_ce_no => open, - ram_oe_no => open, - ram_we_no => open - ); - - ----------------------------------------------------------------------------- - -- Clock Generator - ----------------------------------------------------------------------------- - clk: process - begin - clk_s <= '0'; - wait for period_c / 2; - clk_s <= '1'; - wait for period_c / 2; - end process clk; - - rl_clk: process - begin - rl_clk_s <= '0'; - wait for rl_period_c / 2; - rl_clk_s <= '1'; - wait for rl_period_c / 2; - end process rl_clk; - - - ----------------------------------------------------------------------------- - -- Reset Generator - ----------------------------------------------------------------------------- - reset: process - begin - if reset_level_c = 0 then - reset_s <= '0'; - else - reset_s <= '1'; - end if; - - wait for period_c * 4 + 10 ns; - - reset_s <= not reset_s; - - wait; - end process reset; - - - ----------------------------------------------------------------------------- - -- End of Simulation - ----------------------------------------------------------------------------- - eos: process - begin - wait for 4 ms; - assert false - report "No checks have been performed. Investigate waveforms." - severity note; - assert false - report "End of simulation." - severity failure; - end process eos; - -end behav; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: tb_rl.vhd,v $ --- Revision 1.1 2005/04/10 18:07:25 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/doc/CVS/Entries b/opencores/spi_boot/doc/CVS/Entries deleted file mode 100644 index 630615f41..000000000 --- a/opencores/spi_boot/doc/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/spi_boot.pdf/1.6/Thu Mar 16 17:09:56 2006/-kb/ -/spi_boot_schematic.pdf/1.3/Thu Apr 14 21:20:35 2005/-kb/ -D/src//// diff --git a/opencores/spi_boot/doc/CVS/Repository b/opencores/spi_boot/doc/CVS/Repository deleted file mode 100644 index 07fb78846..000000000 --- a/opencores/spi_boot/doc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/doc diff --git a/opencores/spi_boot/doc/CVS/Root b/opencores/spi_boot/doc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/doc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/doc/CVS/Template b/opencores/spi_boot/doc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/doc/spi_boot.pdf b/opencores/spi_boot/doc/spi_boot.pdf deleted file mode 100644 index a889c3f22..000000000 Binary files a/opencores/spi_boot/doc/spi_boot.pdf and /dev/null differ diff --git a/opencores/spi_boot/doc/spi_boot_schematic.pdf b/opencores/spi_boot/doc/spi_boot_schematic.pdf deleted file mode 100644 index 92755d5f3..000000000 Binary files a/opencores/spi_boot/doc/spi_boot_schematic.pdf and /dev/null differ diff --git a/opencores/spi_boot/doc/src/CVS/Entries b/opencores/spi_boot/doc/src/CVS/Entries deleted file mode 100644 index b2d32af23..000000000 --- a/opencores/spi_boot/doc/src/CVS/Entries +++ /dev/null @@ -1,10 +0,0 @@ -/architecture.eps/1.4/Thu Apr 14 21:18:11 2005/-kb/ -/architecture.fig/1.4/Thu Apr 14 21:18:11 2005/-kb/ -/initialization.eps/1.2/Thu Mar 16 15:41:16 2006/-kb/ -/initialization.fig/1.2/Thu Mar 16 15:41:16 2006/-kb/ -/memory_organization.eps/1.2/Thu Mar 16 16:50:57 2006/-kb/ -/memory_organization.fig/1.2/Thu Mar 16 16:50:57 2006/-kb/ -/spi_boot.sxw/1.6/Thu Mar 16 17:09:31 2006/-kb/ -/transfer.eps/1.1/Sun Feb 27 19:24:30 2005/-kb/ -/transfer.fig/1.1/Sun Feb 27 19:24:35 2005/-kb/ -D diff --git a/opencores/spi_boot/doc/src/CVS/Repository b/opencores/spi_boot/doc/src/CVS/Repository deleted file mode 100644 index 5f8aafef8..000000000 --- a/opencores/spi_boot/doc/src/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/doc/src diff --git a/opencores/spi_boot/doc/src/CVS/Root b/opencores/spi_boot/doc/src/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/doc/src/CVS/Root +++ /dev/null @@ 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-3765 4522 m 3765 4567 l 3886 4567 l 3796 4545 l 3886 4522 l cp -eoclip -n 6660 8370 m 6660 8640 l 5310 8640 l 5310 4545 l - 3780 4545 l gs col0 s gr gr - -% arrowhead -n 3886 4522 m 3796 4545 l 3886 4567 l 3886 4522 l cp gs 0.00 setgray ef gr col0 s -% Polyline -gs clippath -6637 5775 m 6682 5775 l 6682 5654 l 6660 5744 l 6637 5654 l cp -eoclip -n 6660 5400 m - 6660 5760 l gs col0 s gr gr - -% arrowhead -n 6637 5654 m 6660 5744 l 6682 5654 l 6637 5654 l cp gs 0.00 setgray ef gr col0 s -% Polyline -gs clippath -6637 6765 m 6682 6765 l 6682 6644 l 6660 6734 l 6637 6644 l cp -eoclip -n 6660 6390 m - 6660 6750 l gs col0 s gr gr - -% arrowhead -n 6637 6644 m 6660 6734 l 6682 6644 l 6637 6644 l cp gs 0.00 setgray ef gr col0 s -% Polyline -gs clippath -6637 7755 m 6682 7755 l 6682 7634 l 6660 7724 l 6637 7634 l cp -eoclip -n 6660 7380 m - 6660 7740 l gs col0 s gr gr - -% arrowhead -n 6637 7634 m 6660 7724 l 6682 7634 l 6637 7634 l cp gs 0.00 setgray ef gr col0 s -/Helvetica ff 150.00 scf sf -3870 7560 m -gs 1 -1 sc (Yes) col0 sh gr -/Helvetica ff 150.00 scf sf -4590 6930 m -gs 1 -1 sc (No) col0 sh gr -/Helvetica ff 150.00 scf sf -4770 3600 m -gs 1 -1 sc (start) col0 sh gr -/Helvetica ff 150.00 scf sf -3690 4590 m -gs 1 -1 sc (No) dup sw pop neg 0 rm col0 sh gr -/Helvetica ff 150.00 scf sf -4590 3960 m -gs 1 -1 sc (Yes) col0 sh gr -/Helvetica ff 150.00 scf sf -7470 5940 m -gs 1 -1 sc (No) col0 sh gr -/Helvetica ff 150.00 scf sf -6570 6570 m -gs 1 -1 sc (Yes) dup sw pop neg 0 rm col0 sh gr -/Helvetica ff 150.00 scf sf -7470 7920 m -gs 1 -1 sc (No) col0 sh gr -/Helvetica ff 150.00 scf sf -6750 8550 m -gs 1 -1 sc (Yes) col0 sh gr -$F2psEnd -rs diff --git a/opencores/spi_boot/doc/src/transfer.fig b/opencores/spi_boot/doc/src/transfer.fig deleted file mode 100644 index 3d1724050..000000000 --- a/opencores/spi_boot/doc/src/transfer.fig +++ /dev/null @@ -1,119 +0,0 @@ -#FIG 3.2 -Landscape -Center -Metric -A4 -65.00 -Single --2 -1200 2 -6 2700 4725 4860 5445 -6 2970 4860 4590 5265 -4 1 0 50 0 16 10 0.0000 4 120 435 3780 5017 CMD18\001 -4 1 0 50 0 16 10 0.0000 4 120 1560 3780 5242 READ_MULTIPLE_BLOCKS\001 --6 -2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 2745 4770 4815 4770 4815 5400 2745 5400 2745 4770 --6 -6 3015 2745 4545 3465 -2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 3060 2790 4500 2790 4500 3420 3060 3420 3060 2790 -4 1 0 50 0 16 10 0.0000 4 120 705 3780 3150 Wait for start\001 --6 -6 3015 3735 4545 4455 -2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 3780 3780 4500 4050 3780 4410 3060 4050 3780 3780 -4 1 0 50 0 16 10 0.0000 4 135 615 3780 4132 mode = 1?\001 --6 -6 3015 5715 4545 6435 -2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 3060 5760 4500 5760 4500 6390 3060 6390 3060 5760 -4 1 0 50 0 16 10 0.0000 4 120 645 3780 6120 Read block\001 --6 -6 3015 6705 4545 7425 -2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 3780 6750 4500 7020 3780 7380 3060 7020 3780 6750 -4 1 0 50 0 16 10 0.0000 4 120 675 3780 7102 ???_done?\001 --6 -6 2835 7695 4725 8415 -6 3105 7830 4455 8235 -4 1 0 50 0 16 10 0.0000 4 120 435 3780 7987 CMD12\001 -4 1 0 50 0 16 10 0.0000 4 120 1290 3780 8212 STOP_TRANSMISSION\001 --6 -2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 2880 7740 4680 7740 4680 8370 2880 8370 2880 7740 --6 -6 5895 4725 7425 5445 -2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 5940 4770 7380 4770 7380 5400 5940 5400 5940 4770 -4 1 0 50 0 16 10 0.0000 4 135 960 6660 5130 Activate config_n\001 --6 -6 5895 5715 7425 6435 -2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 6660 5760 7380 6030 6660 6390 5940 6030 6660 5760 -4 1 0 50 0 16 10 0.0000 4 135 855 6660 6112 cfg_init_n low?\001 --6 -6 5895 6705 7425 7425 -2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 5940 6750 7380 6750 7380 7380 5940 7380 5940 6750 -4 1 0 50 0 16 10 0.0000 4 135 1125 6660 7110 Deactivate config_n\001 --6 -6 5895 7695 7425 8415 -2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 - 6660 7740 7380 8010 6660 8370 5940 8010 6660 7740 -4 1 0 50 0 16 10 0.0000 4 135 915 6660 8092 cfg_init_n high?\001 --6 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 3420 3780 3780 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 4410 3780 4770 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 5400 3780 5760 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 6390 3780 6750 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 3780 7380 3780 7740 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 - 1 1 1.00 45.00 90.00 - 4545 7020 5130 7020 5130 5535 3780 5535 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 6 - 1 1 1.00 45.00 90.00 - 3780 8370 3780 8640 2520 8640 2520 2520 3780 2520 3780 2790 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 4680 3555 3780 3555 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 3 - 1 1 1.00 45.00 90.00 - 4500 4050 6660 4050 6660 4770 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 - 1 1 1.00 45.00 90.00 - 7380 6030 7920 6030 7920 4050 6660 4050 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 - 1 1 1.00 45.00 90.00 - 7380 8010 7920 8010 7920 6525 6660 6525 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 5 - 1 1 1.00 45.00 90.00 - 6660 8370 6660 8640 5310 8640 5310 4545 3780 4545 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 6660 5400 6660 5760 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 6660 6390 6660 6750 -2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 - 1 1 1.00 45.00 90.00 - 6660 7380 6660 7740 -4 0 0 50 0 16 10 0.0000 4 105 210 3870 7560 Yes\001 -4 0 0 50 0 16 10 0.0000 4 105 165 4590 6930 No\001 -4 0 0 50 0 16 10 0.0000 4 105 240 4770 3600 start\001 -4 2 0 50 0 16 10 0.0000 4 105 165 3690 4590 No\001 -4 0 0 50 0 16 10 0.0000 4 105 210 4590 3960 Yes\001 -4 0 0 50 0 16 10 0.0000 4 105 165 7470 5940 No\001 -4 2 0 50 0 16 10 0.0000 4 105 210 6570 6570 Yes\001 -4 0 0 50 0 16 10 0.0000 4 105 165 7470 7920 No\001 -4 0 0 50 0 16 10 0.0000 4 105 210 6750 8550 Yes\001 diff --git a/opencores/spi_boot/rtl/CVS/Entries b/opencores/spi_boot/rtl/CVS/Entries deleted file mode 100644 index a4756ee6f..000000000 --- a/opencores/spi_boot/rtl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/vhdl//// diff --git a/opencores/spi_boot/rtl/CVS/Repository b/opencores/spi_boot/rtl/CVS/Repository deleted file mode 100644 index dcb0a69bc..000000000 --- a/opencores/spi_boot/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/rtl diff --git a/opencores/spi_boot/rtl/CVS/Root b/opencores/spi_boot/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/rtl/CVS/Template b/opencores/spi_boot/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/rtl/vhdl/CVS/Entries b/opencores/spi_boot/rtl/vhdl/CVS/Entries deleted file mode 100644 index 880f353ca..000000000 --- a/opencores/spi_boot/rtl/vhdl/CVS/Entries +++ /dev/null @@ -1,15 +0,0 @@ -/chip-e.vhd/1.3/Thu Apr 7 20:44:23 2005// -/chip-full-a.vhd/1.6/Thu Apr 7 20:44:23 2005// -/chip-full-c.vhd/1.1/Tue Feb 8 20:41:31 2005// -/chip-minimal-a.vhd/1.6/Thu Apr 7 20:44:23 2005// -/chip-minimal-c.vhd/1.1/Tue Feb 8 20:41:32 2005// -/chip-mmc-a.vhd/1.6/Thu Apr 7 20:44:23 2005// -/chip-mmc-c.vhd/1.1/Tue Feb 8 20:41:32 2005// -/chip-sd-a.vhd/1.6/Thu Apr 7 20:44:23 2005// -/chip-sd-c.vhd/1.1/Tue Feb 8 20:41:33 2005// -/spi_boot-c.vhd/1.2/Fri Feb 18 06:42:11 2005// -/spi_boot.vhd/1.9/Sun Feb 25 18:24:12 2007// -/spi_boot_pack-p.vhd/1.1/Tue Feb 8 20:41:33 2005// -/spi_counter-c.vhd/1.1/Tue Feb 8 20:41:33 2005// -/spi_counter.vhd/1.2/Sun Feb 25 18:24:12 2007// -D/sample//// diff --git a/opencores/spi_boot/rtl/vhdl/CVS/Repository b/opencores/spi_boot/rtl/vhdl/CVS/Repository deleted file mode 100644 index a09f391ea..000000000 --- a/opencores/spi_boot/rtl/vhdl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/rtl/vhdl diff --git a/opencores/spi_boot/rtl/vhdl/CVS/Root b/opencores/spi_boot/rtl/vhdl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/rtl/vhdl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/rtl/vhdl/CVS/Template b/opencores/spi_boot/rtl/vhdl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/rtl/vhdl/chip-e.vhd b/opencores/spi_boot/rtl/vhdl/chip-e.vhd deleted file mode 100644 index 0bdd05aff..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-e.vhd +++ /dev/null @@ -1,91 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel --- --- $Id: chip-e.vhd,v 1.3 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity chip is - - port ( - -- System Interface ------------------------------------------------------- - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_n_i : in std_logic_vector(3 downto 0); - -- SD Card Interface ------------------------------------------------------ - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - -- FPGA Configuration Interface ------------------------------------------- - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - -end chip; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-e.vhd,v $ --- Revision 1.3 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.2 2005/03/08 22:07:11 arniml --- added set selection --- --- Revision 1.1 2005/02/08 20:41:30 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd b/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd deleted file mode 100644 index e43ecb3c4..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd +++ /dev/null @@ -1,164 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel design with full feature set --- --- $Id: chip-full-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -architecture full of chip is - - component spi_boot - generic ( - width_set_sel_g : integer := 4; - width_bit_cnt_g : integer := 6; - width_img_cnt_g : integer := 2; - num_bits_per_img_g : integer := 18; - sd_init_g : integer := 0; - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - reset_level_g : integer := 0 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - signal spi_clk_s : std_logic; - signal spi_cs_n_s : std_logic; - signal spi_data_out_s : std_logic; - signal spi_en_outs_s : std_logic; - - signal set_sel_s : std_logic_vector(3 downto 0); - -begin - - set_sel_s <= not set_sel_n_i; - - spi_boot_b : spi_boot - generic map ( - width_set_sel_g => 4, -- 16 sets - width_bit_cnt_g => 12, -- 512 bytes per block - width_img_cnt_g => 2, -- 4 images - num_bits_per_img_g => 18, -- 256 kByte per image - sd_init_g => 1, -- use SD specific initialization - mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2) - width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider - ) - port map ( - clk_i => clk_i, - reset_i => reset_i, - set_sel_i => set_sel_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_in_i, - spi_data_out_o => spi_data_out_s, - spi_en_outs_o => spi_en_outs_s, - start_i => start_i, - mode_i => mode_i, - config_n_o => config_n_o, - detached_o => detached_o, - cfg_init_n_i => cfg_init_n_i, - cfg_done_i => cfg_done_i, - dat_done_i => dat_done_i, - cfg_clk_o => cfg_clk_o, - cfg_dat_o => cfg_dat_o - ); - - ----------------------------------------------------------------------------- - -- Three state drivers for SPI outputs. - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_s - when spi_en_outs_s = '1' else - 'Z'; - spi_cs_n_o <= spi_cs_n_s - when spi_en_outs_s = '1' else - 'Z'; - spi_data_out_o <= spi_data_out_s - when spi_en_outs_s = '1' else - 'Z'; - -end full; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-full-a.vhd,v $ --- Revision 1.6 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.5 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.4 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.3 2005/02/18 06:42:11 arniml --- clarify wording for images --- --- Revision 1.2 2005/02/16 18:54:37 arniml --- added tri-state drivers for spi outputs --- --- Revision 1.1 2005/02/08 20:41:31 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd b/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd deleted file mode 100644 index da88552c4..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd +++ /dev/null @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: chip-full-c.vhd,v 1.1 2005/02/08 20:41:31 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration chip_full_c0 of chip is - - for full - - for spi_boot_b : spi_boot - use configuration work.spi_boot_rtl_c0; - end for; - - end for; - -end chip_full_c0; diff --git a/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd b/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd deleted file mode 100644 index 090d0b79c..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd +++ /dev/null @@ -1,164 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel design with minimal feature set --- --- $Id: chip-minimal-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -architecture minimal of chip is - - component spi_boot - generic ( - width_set_sel_g : integer := 4; - width_bit_cnt_g : integer := 6; - width_img_cnt_g : integer := 2; - num_bits_per_img_g : integer := 18; - sd_init_g : integer := 0; - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - reset_level_g : integer := 0 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - signal spi_clk_s : std_logic; - signal spi_cs_n_s : std_logic; - signal spi_data_out_s : std_logic; - signal spi_en_outs_s : std_logic; - - signal set_sel_s : std_logic_vector(3 downto 0); - -begin - - set_sel_s <= not set_sel_n_i; - - spi_boot_b : spi_boot - generic map ( - width_set_sel_g => 4, -- 16 sets - width_bit_cnt_g => 6, -- 8 bytes per block - width_img_cnt_g => 2, -- 4 images - num_bits_per_img_g => 18, -- 256 kByte per image - sd_init_g => 0, -- no SD specific initialization - mmc_compat_clk_div_g => 0, -- no MMC compatibility - width_mmc_clk_div_g => 0 -- no MMC compatibility - ) - port map ( - clk_i => clk_i, - reset_i => reset_i, - set_sel_i => set_sel_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_in_i, - spi_data_out_o => spi_data_out_s, - spi_en_outs_o => spi_en_outs_s, - start_i => start_i, - mode_i => mode_i, - config_n_o => config_n_o, - detached_o => detached_o, - cfg_init_n_i => cfg_init_n_i, - cfg_done_i => cfg_done_i, - dat_done_i => dat_done_i, - cfg_clk_o => cfg_clk_o, - cfg_dat_o => cfg_dat_o - ); - - ----------------------------------------------------------------------------- - -- Three state drivers for SPI outputs. - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_s - when spi_en_outs_s = '1' else - 'Z'; - spi_cs_n_o <= spi_cs_n_s - when spi_en_outs_s = '1' else - 'Z'; - spi_data_out_o <= spi_data_out_s - when spi_en_outs_s = '1' else - 'Z'; - -end minimal; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-minimal-a.vhd,v $ --- Revision 1.6 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.5 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.4 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.3 2005/02/18 06:42:12 arniml --- clarify wording for images --- --- Revision 1.2 2005/02/16 18:54:39 arniml --- added tri-state drivers for spi outputs --- --- Revision 1.1 2005/02/08 20:41:31 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd b/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd deleted file mode 100644 index 5547747b2..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd +++ /dev/null @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: chip-minimal-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration chip_minimal_c0 of chip is - - for minimal - - for spi_boot_b : spi_boot - use configuration work.spi_boot_rtl_c0; - end for; - - end for; - -end chip_minimal_c0; diff --git a/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd b/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd deleted file mode 100644 index cef42d268..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd +++ /dev/null @@ -1,164 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel design with MMC feature set --- --- $Id: chip-mmc-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -architecture mmc of chip is - - component spi_boot - generic ( - width_set_sel_g : integer := 4; - width_bit_cnt_g : integer := 6; - width_img_cnt_g : integer := 2; - num_bits_per_img_g : integer := 18; - sd_init_g : integer := 0; - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - reset_level_g : integer := 0 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - signal spi_clk_s : std_logic; - signal spi_cs_n_s : std_logic; - signal spi_data_out_s : std_logic; - signal spi_en_outs_s : std_logic; - - signal set_sel_s : std_logic_vector(3 downto 0); - -begin - - set_sel_s <= not set_sel_n_i; - - spi_boot_b : spi_boot - generic map ( - width_set_sel_g => 4, -- 16 sets - width_bit_cnt_g => 12, -- 512 bytes per block - width_img_cnt_g => 2, -- 4 images - num_bits_per_img_g => 18, -- 256 kByte per image - sd_init_g => 0, -- no SD specific initialization - mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2) - width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider - ) - port map ( - clk_i => clk_i, - reset_i => reset_i, - set_sel_i => set_sel_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_in_i, - spi_data_out_o => spi_data_out_s, - spi_en_outs_o => spi_en_outs_s, - start_i => start_i, - mode_i => mode_i, - config_n_o => config_n_o, - detached_o => detached_o, - cfg_init_n_i => cfg_init_n_i, - cfg_done_i => cfg_done_i, - dat_done_i => dat_done_i, - cfg_clk_o => cfg_clk_o, - cfg_dat_o => cfg_dat_o - ); - - ----------------------------------------------------------------------------- - -- Three state drivers for SPI outputs. - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_s - when spi_en_outs_s = '1' else - 'Z'; - spi_cs_n_o <= spi_cs_n_s - when spi_en_outs_s = '1' else - 'Z'; - spi_data_out_o <= spi_data_out_s - when spi_en_outs_s = '1' else - 'Z'; - -end mmc; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-mmc-a.vhd,v $ --- Revision 1.6 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.5 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.4 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.3 2005/02/18 06:42:13 arniml --- clarify wording for images --- --- Revision 1.2 2005/02/16 18:54:39 arniml --- added tri-state drivers for spi outputs --- --- Revision 1.1 2005/02/08 20:41:32 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd b/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd deleted file mode 100644 index 6131013e4..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd +++ /dev/null @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: chip-mmc-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration chip_mmc_c0 of chip is - - for mmc - - for spi_boot_b : spi_boot - use configuration work.spi_boot_rtl_c0; - end for; - - end for; - -end chip_mmc_c0; diff --git a/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd b/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd deleted file mode 100644 index c955a5f3a..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd +++ /dev/null @@ -1,164 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Chip toplevel design with SD feature set --- --- $Id: chip-sd-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -architecture sd of chip is - - component spi_boot - generic ( - width_set_sel_g : integer := 4; - width_bit_cnt_g : integer := 6; - width_img_cnt_g : integer := 2; - num_bits_per_img_g : integer := 18; - sd_init_g : integer := 0; - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - reset_level_g : integer := 0 - ); - port ( - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - end component; - - signal spi_clk_s : std_logic; - signal spi_cs_n_s : std_logic; - signal spi_data_out_s : std_logic; - signal spi_en_outs_s : std_logic; - - signal set_sel_s : std_logic_vector(3 downto 0); - -begin - - set_sel_s <= not set_sel_n_i; - - spi_boot_b : spi_boot - generic map ( - width_set_sel_g => 4, -- 16 sets - width_bit_cnt_g => 12, -- 512 bytes per block - width_img_cnt_g => 2, -- 4 images - num_bits_per_img_g => 18, -- 256 kByte per image - sd_init_g => 1, -- SD specific initialization - mmc_compat_clk_div_g => 0, -- no MMC compatibility - width_mmc_clk_div_g => 0 -- no MMC compatibility - ) - port map ( - clk_i => clk_i, - reset_i => reset_i, - set_sel_i => set_sel_s, - spi_clk_o => spi_clk_s, - spi_cs_n_o => spi_cs_n_s, - spi_data_in_i => spi_data_in_i, - spi_data_out_o => spi_data_out_s, - spi_en_outs_o => spi_en_outs_s, - start_i => start_i, - mode_i => mode_i, - config_n_o => config_n_o, - detached_o => detached_o, - cfg_init_n_i => cfg_init_n_i, - cfg_done_i => cfg_done_i, - dat_done_i => dat_done_i, - cfg_clk_o => cfg_clk_o, - cfg_dat_o => cfg_dat_o - ); - - ----------------------------------------------------------------------------- - -- Three state drivers for SPI outputs. - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_s - when spi_en_outs_s = '1' else - 'Z'; - spi_cs_n_o <= spi_cs_n_s - when spi_en_outs_s = '1' else - 'Z'; - spi_data_out_o <= spi_data_out_s - when spi_en_outs_s = '1' else - 'Z'; - -end sd; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: chip-sd-a.vhd,v $ --- Revision 1.6 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.5 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.4 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.3 2005/02/18 06:42:14 arniml --- clarify wording for images --- --- Revision 1.2 2005/02/16 18:54:39 arniml --- added tri-state drivers for spi outputs --- --- Revision 1.1 2005/02/08 20:41:32 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd b/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd deleted file mode 100644 index 91e41ddfb..000000000 --- a/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd +++ /dev/null @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: chip-sd-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration chip_sd_c0 of chip is - - for sd - - for spi_boot_b : spi_boot - use configuration work.spi_boot_rtl_c0; - end for; - - end for; - -end chip_sd_c0; diff --git a/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries b/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries deleted file mode 100644 index 552a7baad..000000000 --- a/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/ram_loader-c.vhd/1.1/Sun Apr 10 18:02:32 2005// -/ram_loader.vhd/1.2/Sun Apr 10 17:17:23 2005// -D diff --git a/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository b/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository deleted file mode 100644 index 026a73983..000000000 --- a/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/rtl/vhdl/sample diff --git a/opencores/spi_boot/rtl/vhdl/sample/CVS/Root b/opencores/spi_boot/rtl/vhdl/sample/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/rtl/vhdl/sample/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/rtl/vhdl/sample/CVS/Template b/opencores/spi_boot/rtl/vhdl/sample/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd b/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd deleted file mode 100644 index 8b26c4d57..000000000 --- a/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd +++ /dev/null @@ -1,10 +0,0 @@ -------------------------------------------------------------------------------- --- $Id: ram_loader-c.vhd,v 1.1 2005/04/10 18:02:32 arniml Exp $ -------------------------------------------------------------------------------- - -configuration ram_loader_rtl_c0 of ram_loader is - - for rtl - end for; - -end ram_loader_rtl_c0; diff --git a/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd b/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd deleted file mode 100644 index c604876d7..000000000 --- a/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd +++ /dev/null @@ -1,355 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Sample client for loading an image to asynchronous SRAM --- --- $Id: ram_loader.vhd,v 1.2 2005/04/10 17:17:23 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity ram_loader is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - reset_i : in std_logic; - lamp_o : out std_logic; - -- Config Interface ------------------------------------------------------- - cfg_clk_i : in std_logic; - cfg_data_i : in std_logic; - start_o : out std_logic; - mode_o : out std_logic; - done_o : out std_logic; - detached_i : in std_logic; - -- Asynchronous RAM Interface --------------------------------------------- - ram_addr_o : out std_logic_vector(15 downto 0); - ram_data_b : out std_logic_vector( 7 downto 0); - ram_ce_no : out std_logic_vector( 3 downto 0); - ram_oe_no : out std_logic; - ram_we_no : out std_logic - ); - -end ram_loader; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of ram_loader is - - signal addr_q : unsigned(17 downto 0); - signal inc_addr_s : boolean; - - signal shift_dat_q : std_logic_vector(7 downto 0); - signal ser_dat_q : std_logic_vector(7 downto 0); - signal bit_q : unsigned(2 downto 0); - signal bit_ovfl_q : boolean; - - type fsm_t is (IDLE, - WE_ON, - WE_OFF, - INC_ADDR1, INC_ADDR2, - FINISHED); - signal fsm_s, - fsm_q : fsm_t; - signal done_q : std_logic; - signal done_s : boolean; - signal mode_q, - mode_s : std_logic; - - signal ram_we_n_q, - ram_we_n_s : std_logic; - signal ram_ce_n_q, - ram_ce_n_s : std_logic_vector(3 downto 0); - - type start_fsm_t is (WAIT_DETACH, - CHECK_NO_DONE, - WAIT_DONE); - signal start_fsm_s, - start_fsm_q : start_fsm_t; - - signal start_s, - start_q : std_logic; - signal enable_s, - enable_q : boolean; - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential elements clocked with cfg_clk_i. - -- - seq: process (cfg_clk_i, reset_i) - begin - if reset_i = '0' then - addr_q <= (others => '0'); - shift_dat_q <= (others => '0'); - ser_dat_q <= (others => '0'); - bit_q <= (others => '0'); - bit_ovfl_q <= false; - fsm_q <= IDLE; - ram_we_n_q <= '1'; - ram_ce_n_q <= (others => '1'); - done_q <= '0'; - mode_q <= '0'; - - elsif cfg_clk_i'event and cfg_clk_i = '1' then - if inc_addr_s then - addr_q <= addr_q + 1; - end if; - - if enable_q then - bit_q <= bit_q + 1; - bit_ovfl_q <= bit_q = 7; - - shift_dat_q(0) <= cfg_data_i; - shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0); - end if; - - -- update register when 8 serial bits have been shifted in - if bit_ovfl_q then - ser_dat_q <= shift_dat_q; - end if; - - fsm_q <= fsm_s; - - ram_we_n_q <= ram_we_n_s; - ram_ce_n_q <= ram_ce_n_s; - - -- done only settable once - if done_s then - done_q <= '1'; - end if; - - mode_q <= mode_s; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process fsm - -- - -- Purpose: - -- Implements the combinational logic of the RAM loader FSM. - -- - fsm: process (fsm_q, - bit_ovfl_q, - start_q, - addr_q) - begin - -- default assignments - inc_addr_s <= false; - ram_we_n_s <= '1'; - done_s <= false; - fsm_s <= IDLE; - lamp_o <= '1'; - mode_s <= '0'; - - case fsm_q is - when IDLE => - lamp_o <= '0'; - if start_q = '1' then - if bit_ovfl_q then - fsm_s <= WE_ON; - end if; - end if; - - when WE_ON => - ram_we_n_s <= '0'; - fsm_s <= WE_OFF; - - when WE_OFF => - fsm_s <= INC_ADDR1; - - when INC_ADDR1 => - fsm_s <= INC_ADDR2; - - when INC_ADDR2 => - if addr_q = "001111111111111111" then -- load only 64k - fsm_s <= FINISHED; - done_s <= true; - mode_s <= '1'; - else - inc_addr_s <= true; - fsm_s <= IDLE; - end if; - - when FINISHED => - fsm_s <= FINISHED; - lamp_o <= '1'; - mode_s <= '1'; - - when others => - end case; - - end process fsm; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process ce_gen - -- - -- Purpose: - -- Generates the four CE signals for the external RAM chips. - -- - ce_gen: process (addr_q) - begin - ram_ce_n_s <= (others => '1'); - ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0'; - end process ce_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process start_seq - -- - -- Purpose: - -- Implements the sequential elements clocked with clk_i. - -- - start_seq: process (clk_i, reset_i) - begin - if reset_i = '0' then - start_fsm_q <= WAIT_DETACH; - start_q <= '0'; - enable_q <= false; - - elsif clk_i'event and clk_i = '1' then - start_fsm_q <= start_fsm_s; - - enable_q <= enable_s; - - start_q <= start_s; - - end if; - end process start_seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process start_comb - -- - -- Purpose: - -- Implements the combinational logic of the start FSM. - -- - start_comb: process (start_fsm_q, - detached_i, - done_q, - enable_q, - start_q) - begin - -- default assignments - start_fsm_s <= WAIT_DETACH; - enable_s <= enable_q; - start_s <= start_q; - - case start_fsm_q is - -- Wait for detached_i to become '1' - -- This state is entered/left twice: - -- 1. after reset to start the data download - -- 2. after data download to start the next configuration cycle - when WAIT_DETACH => - if detached_i = '1' then - start_fsm_s <= CHECK_NO_DONE; - enable_s <= true; - start_s <= '1'; - - else - start_fsm_s <= WAIT_DETACH; - end if; - - -- Wait until done_q is '0' - -- This ensures that the FSM stalls when it has started the configuration - -- download. There must be no further action in this case. - when CHECK_NO_DONE => - if done_q = '0' then - start_fsm_s <= WAIT_DONE; - else - start_fsm_s <= CHECK_NO_DONE; - end if; - - -- Wait until done_q is '1' - -- done_q is the signal that the main FSM has finished its work. We - -- need to start the configuration download. - when WAIT_DONE => - if done_q = '1' then - start_fsm_s <= WAIT_DETACH; - enable_s <= false; - start_s <= '0'; - else - start_fsm_s <= WAIT_DONE; - end if; - - when others => - null; - - end case; - - end process start_comb; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - start_o <= start_q; - mode_o <= mode_q; - done_o <= done_q - when start_q = '1' else - '1'; - ram_addr_o <= std_logic_vector(addr_q(15 downto 0)); - ram_data_b <= ser_dat_q; - ram_oe_no <= '1'; - ram_ce_no <= ram_ce_n_q; - ram_we_no <= ram_we_n_q; - -end rtl; diff --git a/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd b/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd deleted file mode 100644 index 6f11ed34b..000000000 --- a/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd +++ /dev/null @@ -1,27 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: spi_boot-c.vhd,v 1.2 2005/02/18 06:42:11 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration spi_boot_rtl_c0 of spi_boot is - - for rtl - - for img_cnt - for img_cnt_b : spi_counter - use configuration work.spi_counter_rtl_c0; - end for; - end for; - - for mmc_cnt - for mmc_cnt_b : spi_counter - use configuration work.spi_counter_rtl_c0; - end for; - end for; - - end for; - -end spi_boot_rtl_c0; diff --git a/opencores/spi_boot/rtl/vhdl/spi_boot.vhd b/opencores/spi_boot/rtl/vhdl/spi_boot.vhd deleted file mode 100644 index 3d2b81da7..000000000 --- a/opencores/spi_boot/rtl/vhdl/spi_boot.vhd +++ /dev/null @@ -1,979 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity spi_boot is - - generic ( - -- width of set selection - width_set_sel_g : integer := 4; - -- width of bit counter: minimum 6, maximum 12 - width_bit_cnt_g : integer := 6; - -- width of image counter: minimum 0, maximum n - width_img_cnt_g : integer := 2; - -- number of bits required to address one image - num_bits_per_img_g : integer := 18; - -- SD specific initialization - sd_init_g : integer := 0; - -- clock divider to reach 400 kHz for MMC compatibility - mmc_compat_clk_div_g : integer := 0; - width_mmc_clk_div_g : integer := 0; - -- active level of reset_i - reset_level_g : integer := 0 - ); - - port ( - -- System Interface ------------------------------------------------------- - clk_i : in std_logic; - reset_i : in std_logic; - set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); - -- Card Interface --------------------------------------------------------- - spi_clk_o : out std_logic; - spi_cs_n_o : out std_logic; - spi_data_in_i : in std_logic; - spi_data_out_o : out std_logic; - spi_en_outs_o : out std_logic; - -- FPGA Configuration Interface ------------------------------------------- - start_i : in std_logic; - mode_i : in std_logic; - config_n_o : out std_logic; - detached_o : out std_logic; - cfg_init_n_i : in std_logic; - cfg_done_i : in std_logic; - dat_done_i : in std_logic; - cfg_clk_o : out std_logic; - cfg_dat_o : out std_logic - ); - -end spi_boot; - - -library ieee; -use ieee.numeric_std.all; -use work.spi_boot_pack.all; - -architecture rtl of spi_boot is - - component spi_counter - generic ( - cnt_width_g : integer := 4; - cnt_max_g : integer := 15 - ); - port ( - clk_i : in std_logic; - reset_i : in boolean; - cnt_en_i : in boolean; - cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); - cnt_ovfl_o : out boolean - ); - end component; - - - ----------------------------------------------------------------------------- - -- States of the controller FSM - -- - type ctrl_states_t is (POWER_UP1, POWER_UP2, - CMD0, - CMD1, - CMD55, ACMD41, - CMD16, - WAIT_START, - WAIT_INIT_LOW, WAIT_INIT_HIGH, - CMD18, CMD18_DATA, - CMD12, - INC_IMG_CNT); - -- - signal ctrl_fsm_q, - ctrl_fsm_s : ctrl_states_t; - -- - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- States of the command FSM - -- - type cmd_states_t is (CMD, START, R1, PAUSE); - -- - signal cmd_fsm_q, - cmd_fsm_s : cmd_states_t; - -- - ----------------------------------------------------------------------------- - - subtype op_r is integer range 5 downto 0; - type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7); - signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0); - signal res_bc_s : res_bc_t; - signal upper_bitcnt_zero_s : boolean; - - signal cfg_dat_q : std_logic; - - signal spi_clk_q : std_logic; - signal spi_clk_rising_q : boolean; - signal spi_clk_falling_q : boolean; - signal spi_dat_q, - spi_dat_s : std_logic; - signal spi_cs_n_q, - spi_cs_n_s : std_logic; - - signal cfg_clk_q : std_logic; - - signal start_q : std_logic; - - signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0); - signal cnt_en_img_s : boolean; - signal mmc_cnt_ovfl_s : boolean; - signal mmc_compat_s : boolean; - - signal cmd_finished_s : boolean; - - signal r1_result_q : std_logic; - signal done_q, - send_cmd12_q : boolean; - - signal en_outs_s, - en_outs_q : boolean; - - signal reset_s : boolean; - - signal true_s : boolean; - -begin - - true_s <= true; - - reset_s <= true - when (reset_level_g = 1 and reset_i = '1') or - (reset_level_g = 0 and reset_i = '0') else - false; - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements several sequential elements. - -- - seq: process (clk_i, reset_s) - - variable bit_cnt_v : unsigned(1 downto 0); - - begin - if reset_s then - -- reset bit counter to 63 for power up - bit_cnt_q <= (others => '0'); - bit_cnt_q(op_r) <= "111111"; - spi_dat_q <= '1'; - spi_cs_n_q <= '1'; - cfg_dat_q <= '1'; - start_q <= '0'; - done_q <= false; - send_cmd12_q <= false; - ctrl_fsm_q <= POWER_UP1; - cmd_fsm_q <= CMD; - r1_result_q <= '0'; - en_outs_q <= false; - - elsif clk_i'event and clk_i = '1' then - -- bit counter control - if spi_clk_rising_q then - case res_bc_s is - when NONE => - bit_cnt_q <= bit_cnt_q - 1; - when RES_MAX => - bit_cnt_q <= (others => '1'); - when RES_47 => - bit_cnt_q <= (others => '0'); - bit_cnt_q(op_r) <= "101111"; - when RES_15 => - bit_cnt_q <= (others => '0'); - bit_cnt_q(op_r) <= "001111"; - when RES_7 => - bit_cnt_q <= (others => '0'); - bit_cnt_q(op_r) <= "000111"; - when others => - bit_cnt_q <= (others => '0'); - end case; - end if; - - -- Card data output register - -- spi_clk_falling_q acts as enable during MMC clock compatibility mode. - -- As soon as this mode is left, the register must start latching. - -- There is no explicit relation to spi_clk_q anymore in normal mode. - -- Instead, spi_dat_s is operated by bit_cnt_q above which changes its - -- value after the rising edge of spi_clk_q. - -- -> spi_dat_q changes upon falling edge of spi_clk_q - if spi_clk_falling_q or not mmc_compat_s then - spi_dat_q <= spi_dat_s; - end if; - - -- config data output register - -- a new value is loaded when config clock is high, - -- i.e. input data is sampled with rising spi_clk - -- while output value changes on falling edge of cfg_clk - if cfg_clk_q = '1' and spi_clk_rising_q then - cfg_dat_q <= spi_data_in_i; - end if; - - -- Controller FSM state - ctrl_fsm_q <= ctrl_fsm_s; - - -- Command FSM state - cmd_fsm_q <= cmd_fsm_s; - - -- CS signal for SPI card - if spi_clk_q = '1' then - spi_cs_n_q <= spi_cs_n_s; - end if; - - -- Extract flags from R1 response - if cmd_fsm_q = R1 then - bit_cnt_v := bit_cnt_q(1 downto 0); - case bit_cnt_v(1 downto 0) is - when "10" => - -- always save "Illegal Command" flag - r1_result_q <= to_X01(spi_data_in_i); - when "00" => - -- overwrite with "Idle State" flag when not in CMD55 - if ctrl_fsm_q /= CMD55 then - r1_result_q <= to_X01(spi_data_in_i); - end if; - when others => - null; - end case; - end if; - - -- Start trigger register for rising edge detection - -- the reset value is '0' thus a rising edge will always be detected - -- after reset even though start_i is tied to '1' - if start_i = '0' then - start_q <= '0'; - elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then - start_q <= start_i; - end if; - - -- Marker for cfg_done and dat_done - if ctrl_fsm_q = CMD18_DATA then - if cfg_done_i = '1' and dat_done_i = '1' then - done_q <= true; - end if; - - if done_q and - (not upper_bitcnt_zero_s or cmd_fsm_q = START) then - -- activate sending of CMD12 when it is safe: - -- * upper bits of bit counter are not zero - -- -> transmission of CMD12 is not running - -- * cmd FSM is in START state - -- -> also no transmission running - send_cmd12_q <= true; - end if; - elsif ctrl_fsm_q = WAIT_START then - -- reset done_q when WAIT_START has been reached - -- this is necessary to let the stop transmission process come to - -- an end without interruption or generation of unwanted cfg_clk_q - done_q <= false; - send_cmd12_q <= false; - end if; - - -- output enable - if spi_clk_rising_q then - en_outs_q <= en_outs_s; - end if; - - end if; - - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process upper_bits - -- - -- Purpose: - -- Detects that the upper bits of the bit counter are zero. - -- Upper bits = n downto 6, i.e. the optional part that is not required for - -- commands but for extension of data blocks. - -- - upper_bits: process (bit_cnt_q) - variable zero_v : boolean; - begin - - zero_v := true; - for i in bit_cnt_q'high downto 6 loop - if bit_cnt_q(i) = '1' then - zero_v := false; - end if; - end loop; - - upper_bitcnt_zero_s <= zero_v; - - end process upper_bits; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process clk_gen - -- - -- Purpose: - -- Generates clocks for card and FPGA configuration. - -- The card clock is free running with a divide by two of clk_i. - -- The clock for FPGA config has an enable and is stopped on high level. - -- There is a phase shift of half a period between spi_clk and cfg_clk. - -- - clk_gen: process (clk_i, reset_s) - begin - if reset_s then - spi_clk_q <= '0'; - cfg_clk_q <= '1'; - - elsif clk_i'event and clk_i = '1' then - - -- spi_clk_q rises according to the flag - -- it falls with overflow indication - -- the resulting duty cycle is not exactly 50:50, - -- high time is a bit longer - if mmc_compat_s then - -- MMC clock compatibility mode: - -- spi_clk_q rises when flagged by spi_clk_rising_q - if spi_clk_rising_q then - spi_clk_q <= '1'; - elsif mmc_cnt_ovfl_s then - -- upon counter overflow spi_clk_q falls in case it does not rise - spi_clk_q <= '0'; - end if; - else - -- normal mode - -- spi_clk_q follows spi_clk_rising_q - if spi_clk_rising_q then - spi_clk_q <= '1'; - else - spi_clk_q <= '0'; - end if; - end if; - - -- clock for FPGA config must be enabled and follows spi_clk - if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and - not done_q then - cfg_clk_q <= spi_clk_q; - else - cfg_clk_q <= '1'; - end if; - - end if; - - end process clk_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Indication flags for rising and falling spi_clk_q. - -- Essential for MMC clock compatibility mode. - ----------------------------------------------------------------------------- - mmc_comap: if mmc_compat_clk_div_g > 0 generate - mmc_compat_sig: process (clk_i, reset_s) - begin - if reset_s then - spi_clk_rising_q <= false; - spi_clk_falling_q <= false; - - elsif clk_i'event and clk_i = '1' then - if mmc_compat_s then - -- MMC clock compatibility mode: - -- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q - -- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q - if mmc_cnt_ovfl_s then - spi_clk_rising_q <= spi_clk_q = '0'; - spi_clk_falling_q <= spi_clk_q = '1'; - else - spi_clk_rising_q <= false; - spi_clk_falling_q <= false; - end if; - else - -- normal mode - spi_clk_rising_q <= not spi_clk_rising_q; - spi_clk_falling_q <= true; - end if; - - end if; - end process mmc_compat_sig; - end generate; - - no_mmc_compat: if mmc_compat_clk_div_g = 0 generate - -- SPI clock rising whenever spi_clk_q is '0' - spi_clk_rising_q <= spi_clk_q = '0'; - -- SPI clock falling whenever spi_clk_q is '1' - spi_clk_falling_q <= spi_clk_q = '1'; - end generate; - - - ----------------------------------------------------------------------------- - -- Process ctrl_fsm - -- - -- Purpose: - -- Implements the controller FSM. - -- - ctrl_fsm: process (ctrl_fsm_q, - cmd_finished_s, r1_result_q, - start_i, start_q, mode_i, - cfg_init_n_i) - - variable mmc_compat_v : boolean; - - begin - -- default assignments - ctrl_fsm_s <= POWER_UP1; - config_n_o <= '1'; - cnt_en_img_s <= false; - spi_cs_n_s <= '0'; - mmc_compat_v := false; - en_outs_s <= true; - - case ctrl_fsm_q is - -- Let card finish power up, step 1 ------------------------------------- - when POWER_UP1 => - mmc_compat_v := true; - spi_cs_n_s <= '1'; - if cmd_finished_s then - ctrl_fsm_s <= POWER_UP2; - else - ctrl_fsm_s <= POWER_UP1; - end if; - - - -- Let card finish power up, step 2 ------------------------------------- - when POWER_UP2 => - mmc_compat_v := true; - if cmd_finished_s then - ctrl_fsm_s <= CMD0; - else - spi_cs_n_s <= '1'; - ctrl_fsm_s <= POWER_UP2; - end if; - - - -- Issue CMD0: GO_IDLE_STATE -------------------------------------------- - when CMD0 => - mmc_compat_v := true; - if cmd_finished_s then - if sd_init_g = 1 then - ctrl_fsm_s <= CMD55; - else - ctrl_fsm_s <= CMD1; - end if; - else - ctrl_fsm_s <= CMD0; - end if; - - - -- Issue CMD55: APP_CMD ------------------------------------------------- - when CMD55 => - if sd_init_g = 1 then - - mmc_compat_v := true; - if cmd_finished_s then - if r1_result_q = '0' then - -- command accepted, it's an SD card - ctrl_fsm_s <= ACMD41; - else - -- command rejected, it's an MMC card - ctrl_fsm_s <= CMD1; - end if; - else - ctrl_fsm_s <= CMD55; - end if; - - end if; - - - -- Issue ACMD41: SEND_OP_COND ------------------------------------------- - when ACMD41 => - if sd_init_g = 1 then - - mmc_compat_v := true; - if cmd_finished_s then - if r1_result_q = '0' then - ctrl_fsm_s <= CMD16; - else - ctrl_fsm_s <= CMD55; - end if; - else - ctrl_fsm_s <= ACMD41; - end if; - - end if; - - - -- Issue CMD1: SEND_OP_COND --------------------------------------------- - when CMD1 => - mmc_compat_v := true; - if cmd_finished_s then - if r1_result_q = '0' then - ctrl_fsm_s <= CMD16; - else - ctrl_fsm_s <= CMD1; - end if; - else - ctrl_fsm_s <= CMD1; - end if; - - - -- Issue CMD16: SET_BLOCKLEN -------------------------------------------- - when CMD16 => - if cmd_finished_s then - ctrl_fsm_s <= WAIT_START; - else - ctrl_fsm_s <= CMD16; - end if; - - - -- Wait for configuration start request --------------------------------- - when WAIT_START => - spi_cs_n_s <= '1'; - - -- detect rising edge of start_i - if start_i = '1' and start_q = '0' then - -- decide which mode is requested - if cmd_finished_s then - if mode_i = '0' then - ctrl_fsm_s <= CMD18; - else - ctrl_fsm_s <= WAIT_INIT_LOW; - end if; - else - en_outs_s <= false; - ctrl_fsm_s <= WAIT_START; - end if; - else - en_outs_s <= false; - ctrl_fsm_s <= WAIT_START; - end if; - - - -- Wait for INIT to become low ------------------------------------------ - when WAIT_INIT_LOW => - spi_cs_n_s <= '1'; - -- activate FPGA configuration - config_n_o <= '0'; - - if cfg_init_n_i = '0' then - ctrl_fsm_s <= WAIT_INIT_HIGH; - else - ctrl_fsm_s <= WAIT_INIT_LOW; - end if; - - - -- Wait for INIT to become high ----------------------------------------- - when WAIT_INIT_HIGH => - spi_cs_n_s <= '1'; - - if cfg_init_n_i = '1' and cmd_finished_s then - ctrl_fsm_s <= CMD18; - else - ctrl_fsm_s <= WAIT_INIT_HIGH; - end if; - - - -- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------ - when CMD18 => - if cmd_finished_s then - ctrl_fsm_s <= CMD18_DATA; - else - ctrl_fsm_s <= CMD18; - end if; - -- - -- receive a data block - when CMD18_DATA => - if cmd_finished_s then - ctrl_fsm_s <= CMD12; - else - ctrl_fsm_s <= CMD18_DATA; - end if; - - - -- Issued CMD12: STOP_TRANSMISSION -------------------------------------- - when CMD12 => - if cmd_finished_s then - ctrl_fsm_s <= INC_IMG_CNT; - else - ctrl_fsm_s <= CMD12; - end if; - - - -- Increment Image Counter ---------------------------------------------- - when INC_IMG_CNT => - spi_cs_n_s <= '1'; - ctrl_fsm_s <= WAIT_START; - cnt_en_img_s <= true; - - - - when others => - null; - - end case; - - -- mmc_compat_s is suppressed if MMC clock compatibility is not required - if mmc_compat_clk_div_g > 0 then - mmc_compat_s <= mmc_compat_v; - else - mmc_compat_s <= false; - end if; - - end process ctrl_fsm; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process cmd_fsm - -- - -- Purpose: - -- Implements the command FSM. - -- - cmd_fsm: process (spi_clk_rising_q, - spi_data_in_i, - bit_cnt_q, - ctrl_fsm_q, - cmd_fsm_q, - send_cmd12_q) - - variable cnt_zero_v : boolean; - variable spi_data_low_v : boolean; - variable no_startbit_v : boolean; - - begin - -- default assignments - cmd_finished_s <= false; - cmd_fsm_s <= CMD; - res_bc_s <= NONE; - - cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0; - spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0'; - - -- these are no real commands thus there will be no startbit - case ctrl_fsm_q is - when POWER_UP1 | POWER_UP2 | - WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW => - no_startbit_v := true; - when others => - no_startbit_v := false; - end case; - - - case cmd_fsm_q is - -- Send the command ----------------------------------------------------- - when CMD => - if cnt_zero_v then - if ctrl_fsm_q /= CMD18_DATA then - -- normal commands including CMD12 require startbit of R1 response - cmd_fsm_s <= START; - else - if not send_cmd12_q then - -- CMD18_DATA needs to read CRC - cmd_fsm_s <= R1; - res_bc_s <= RES_15; - else - -- CMD18_DATA finished, scan for startbit of response - cmd_finished_s <= true; - cmd_fsm_s <= START; - end if; - end if; - else - cmd_fsm_s <= CMD; - end if; - - -- Wait for startbit of response ---------------------------------------- - when START => - -- startbit detection or skip of this check - if no_startbit_v and spi_clk_rising_q then - cmd_fsm_s <= R1; - res_bc_s <= RES_7; - elsif spi_data_low_v then - if ctrl_fsm_q /= CMD18_DATA then - cmd_fsm_s <= R1; - else - -- CMD18_DATA startbit detected, read payload - cmd_fsm_s <= CMD; - res_bc_s <= RES_MAX; - end if; - else - cmd_fsm_s <= START; - res_bc_s <= RES_7; - end if; - - -- Read R1 response ----------------------------------------------------- - when R1 => - if cnt_zero_v then - res_bc_s <= RES_7; - - if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then - cmd_fsm_s <= PAUSE; - else - -- CMD18 needs another startbit detection for the data token. - -- CMD18_DATA needs a startbit after having received the CRC, either - -- * next data token - -- * R1 response of CMD12 - cmd_fsm_s <= START; - - if ctrl_fsm_q = CMD18 then - -- CMD18 response received -> advance to CMD18_DATA - cmd_finished_s <= true; - end if; - end if; - else - cmd_fsm_s <= R1; - end if; - - -- PAUSE state -> required for Nrc, card response to host command ------- - when PAUSE => - if cnt_zero_v then - cmd_fsm_s <= CMD; - res_bc_s <= RES_47; - cmd_finished_s <= true; - else - cmd_fsm_s <= PAUSE; - end if; - - when others => - null; - - end case; - - end process cmd_fsm; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process transmit - -- - -- Purpose: - -- Generates the serial data output values based on the current FSM state - -- - -- The local variable cmd_v is 64 bits wide in contrast to an SPI command - -- with 48 bits. There are two reasons for this: - -- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit - -- counter will start from 3F on its lowest 6 bits. Therefore, it is - -- necessary to provide all 64 positions in cmd_v. - -- * Reduces logic. - -- - transmit: process (ctrl_fsm_q, - cmd_fsm_q, - bit_cnt_q, - img_cnt_s, - send_cmd12_q, - set_sel_i, - upper_bitcnt_zero_s) - - subtype cmd_r is natural range 47 downto 0; - subtype cmd_t is std_logic_vector(cmd_r); - subtype ext_cmd_t is std_logic_vector(63 downto 0); - -- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS - constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101"; - constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1"; - constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1"; - constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1"; - constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1"; - constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1"; - constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1"; - - variable cmd_v : ext_cmd_t; - variable tx_v : boolean; - - begin - -- default assignments - spi_dat_s <= '1'; - cmd_v := (others => '1'); - tx_v := false; - - if cmd_fsm_q = CMD then - case ctrl_fsm_q is - when CMD0 => - cmd_v(cmd_r) := cmd0_c; - tx_v := true; - when CMD1 => - cmd_v(cmd_r) := cmd1_c; - tx_v := true; - when CMD16 => - cmd_v(cmd_r) := cmd16_c; - cmd_v(8 + width_bit_cnt_g-3) := '1'; - tx_v := true; - when CMD18 => - cmd_v(cmd_r) := cmd18_c; - -- insert image counter - cmd_v(8 + num_bits_per_img_g + width_img_cnt_g - downto 8 + num_bits_per_img_g) := img_cnt_s; - -- insert set selection - cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1 - downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i; - tx_v := true; - when CMD18_DATA => - cmd_v(cmd_r) := cmd12_c; - - if send_cmd12_q and upper_bitcnt_zero_s then - tx_v := true; - end if; - when CMD55 => - cmd_v(cmd_r) := cmd55_c; - tx_v := true; - when ACMD41 => - cmd_v(cmd_r) := acmd41_c; - tx_v := true; - - when others => - null; - end case; - end if; - - if tx_v then - spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0))); - end if; - - end process transmit; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Optional Image Counter - ----------------------------------------------------------------------------- - img_cnt: if width_img_cnt_g > 0 generate - img_cnt_b : spi_counter - generic map ( - cnt_width_g => width_img_cnt_g, - cnt_max_g => 2**width_img_cnt_g - 1 - ) - port map ( - clk_i => clk_i, - reset_i => reset_s, - cnt_en_i => cnt_en_img_s, - cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0), - cnt_ovfl_o => open - ); - img_cnt_s(width_img_cnt_g) <= '0'; - end generate; - - no_img_cnt: if width_img_cnt_g = 0 generate - img_cnt_s <= (others => '0'); - end generate; - - - ----------------------------------------------------------------------------- - -- Optional MMC compatibility counter - ----------------------------------------------------------------------------- - mmc_cnt: if mmc_compat_clk_div_g > 0 generate - mmc_cnt_b : spi_counter - generic map ( - cnt_width_g => width_mmc_clk_div_g, - cnt_max_g => mmc_compat_clk_div_g - ) - port map ( - clk_i => clk_i, - reset_i => reset_s, - cnt_en_i => true_s, - cnt_o => open, - cnt_ovfl_o => mmc_cnt_ovfl_s - ); - end generate; - - no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate - mmc_cnt_ovfl_s <= true; - end generate; - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - spi_clk_o <= spi_clk_q; - spi_cs_n_o <= spi_cs_n_q; - spi_data_out_o <= spi_dat_q; - spi_en_outs_o <= '1' - when en_outs_q else - '0'; - cfg_clk_o <= cfg_clk_q; - cfg_dat_o <= cfg_dat_q; - detached_o <= '0' - when en_outs_q else - '1'; - -end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: spi_boot.vhd,v $ --- Revision 1.9 2007/02/25 18:24:12 arniml --- fix type handling of resets --- --- Revision 1.8 2006/09/11 23:03:36 arniml --- disable outputs with reset --- --- Revision 1.7 2005/04/07 20:44:23 arniml --- add new port detached_o --- --- Revision 1.6 2005/03/09 19:48:34 arniml --- invert level of set_sel input --- --- Revision 1.5 2005/03/08 22:07:12 arniml --- added set selection --- --- Revision 1.4 2005/02/18 06:42:08 arniml --- clarify wording for images --- --- Revision 1.3 2005/02/16 18:59:10 arniml --- include output enable control for SPI outputs --- --- Revision 1.2 2005/02/13 17:25:51 arniml --- major update to fix several problems --- configuration/data download of multiple sets works now --- --- Revision 1.1 2005/02/08 20:41:33 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd b/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd deleted file mode 100644 index ac8b544f9..000000000 --- a/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd +++ /dev/null @@ -1,54 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: spi_boot_pack-p.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package spi_boot_pack is - - function "=" (a : std_logic; b : integer) return boolean; - -end spi_boot_pack; - -package body spi_boot_pack is - - function "=" (a : std_logic; b : integer) return boolean is - variable result_v : boolean; - begin - result_v := false; - - case a is - when '0' => - if b = 0 then - result_v := true; - end if; - - when '1' => - if b = 1 then - result_v := true; - end if; - - when others => - null; - - end case; - - return result_v; - end; - -end spi_boot_pack; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: spi_boot_pack-p.vhd,v $ --- Revision 1.1 2005/02/08 20:41:33 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd b/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd deleted file mode 100644 index d81e20db6..000000000 --- a/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd +++ /dev/null @@ -1,14 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- --- $Id: spi_counter-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ --- -------------------------------------------------------------------------------- - -configuration spi_counter_rtl_c0 of spi_counter is - - for rtl - end for; - -end spi_counter_rtl_c0; diff --git a/opencores/spi_boot/rtl/vhdl/spi_counter.vhd b/opencores/spi_boot/rtl/vhdl/spi_counter.vhd deleted file mode 100644 index 8ec7357ea..000000000 --- a/opencores/spi_boot/rtl/vhdl/spi_counter.vhd +++ /dev/null @@ -1,118 +0,0 @@ -------------------------------------------------------------------------------- --- --- SD/MMC Bootloader --- Generic counter module --- --- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved, see COPYING. --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/projects.cgi/web/spi_boot/overview --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity spi_counter is - - generic ( - cnt_width_g : integer := 4; - cnt_max_g : integer := 15 - ); - - port ( - clk_i : in std_logic; - reset_i : in boolean; - cnt_en_i : in boolean; - cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); - cnt_ovfl_o : out boolean - ); - -end spi_counter; - - -library ieee; -use ieee.numeric_std.all; -use work.spi_boot_pack.all; - -architecture rtl of spi_counter is - - signal cnt_q : unsigned(cnt_width_g-1 downto 0); - signal cnt_ovfl_s : boolean; - -begin - - cnt: process (clk_i, reset_i) - begin - if reset_i then - cnt_q <= (others => '0'); - - elsif clk_i'event and clk_i = '1' then - if cnt_en_i then - if not cnt_ovfl_s then - cnt_q <= cnt_q + 1; - else - cnt_q <= (others => '0'); - end if; - end if; - end if; - end process cnt; - - cnt_ovfl_s <= cnt_q = cnt_max_g; - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - cnt_ovfl_o <= cnt_ovfl_s; - cnt_o <= std_logic_vector(cnt_q); - -end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: spi_counter.vhd,v $ --- Revision 1.2 2007/02/25 18:24:12 arniml --- fix type handling of resets --- --- Revision 1.1 2005/02/08 20:41:33 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/opencores/spi_boot/sim/CVS/Entries b/opencores/spi_boot/sim/CVS/Entries deleted file mode 100644 index 9487498ad..000000000 --- a/opencores/spi_boot/sim/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/rtl_sim//// diff --git a/opencores/spi_boot/sim/CVS/Repository b/opencores/spi_boot/sim/CVS/Repository deleted file mode 100644 index 4e2e09740..000000000 --- a/opencores/spi_boot/sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/sim diff --git a/opencores/spi_boot/sim/CVS/Root b/opencores/spi_boot/sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/sim/CVS/Template b/opencores/spi_boot/sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/sim/rtl_sim/CVS/Entries b/opencores/spi_boot/sim/rtl_sim/CVS/Entries deleted file mode 100644 index e3d0dc145..000000000 --- a/opencores/spi_boot/sim/rtl_sim/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile/1.2/Sun Apr 10 18:14:19 2005// -D diff --git a/opencores/spi_boot/sim/rtl_sim/CVS/Repository b/opencores/spi_boot/sim/rtl_sim/CVS/Repository deleted file mode 100644 index 114ab862f..000000000 --- a/opencores/spi_boot/sim/rtl_sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/sim/rtl_sim diff --git a/opencores/spi_boot/sim/rtl_sim/CVS/Root b/opencores/spi_boot/sim/rtl_sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/sim/rtl_sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/sim/rtl_sim/CVS/Template b/opencores/spi_boot/sim/rtl_sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/sim/rtl_sim/Makefile b/opencores/spi_boot/sim/rtl_sim/Makefile deleted file mode 100644 index 46fb3c635..000000000 --- a/opencores/spi_boot/sim/rtl_sim/Makefile +++ /dev/null @@ -1,159 +0,0 @@ -############################################################################## -# -# Makefile for the spi_boot project. -# -# The dependencies for all VHDL source files are stored here. -# -# Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) -# -# All rights reserved -# -############################################################################## - - -PROJECT_DIR = ../.. -RTL_DIR = $(PROJECT_DIR)/rtl/vhdl -BENCH_DIR = $(PROJECT_DIR)/bench/vhdl - - - -ANALYZE=ghdl -a --std=87 --workdir=work -ELABORATE=ghdl -e --std=87 --workdir=work - -.PHONY: all -all: work elaborate - -work: - mkdir work - -work/spi_boot_pack-p.o: $(RTL_DIR)/spi_boot_pack-p.vhd - $(ANALYZE) $(RTL_DIR)/spi_boot_pack-p.vhd - -work/spi_counter.o: $(RTL_DIR)/spi_counter.vhd \ - work/spi_boot_pack-p.o - $(ANALYZE) $(RTL_DIR)/spi_counter.vhd -work/spi_counter-c.o: $(RTL_DIR)/spi_counter-c.vhd \ - work/spi_counter.o - $(ANALYZE) $(RTL_DIR)/spi_counter-c.vhd - -work/spi_boot.o: $(RTL_DIR)/spi_boot.vhd \ - work/spi_boot_pack-p.o - $(ANALYZE) $(RTL_DIR)/spi_boot.vhd -work/spi_boot-c.o: $(RTL_DIR)/spi_boot-c.vhd \ - work/spi_boot.o \ - work/spi_counter-c.o - $(ANALYZE) $(RTL_DIR)/spi_boot-c.vhd - -work/chip-e.o: $(RTL_DIR)/chip-e.vhd - $(ANALYZE) $(RTL_DIR)/chip-e.vhd - -work/chip-full-a.o: $(RTL_DIR)/chip-full-a.vhd \ - work/chip-e.o - $(ANALYZE) $(RTL_DIR)/chip-full-a.vhd -work/chip-full-c.o: $(RTL_DIR)/chip-full-c.vhd \ - work/chip-full-a.o \ - work/spi_boot-c.o - $(ANALYZE) $(RTL_DIR)/chip-full-c.vhd - -work/chip-mmc-a.o: $(RTL_DIR)/chip-mmc-a.vhd \ - work/chip-e.o - $(ANALYZE) $(RTL_DIR)/chip-mmc-a.vhd -work/chip-mmc-c.o: $(RTL_DIR)/chip-mmc-c.vhd \ - work/chip-mmc-a.o \ - work/spi_boot-c.o - $(ANALYZE) $(RTL_DIR)/chip-mmc-c.vhd - -work/chip-sd-a.o: $(RTL_DIR)/chip-sd-a.vhd \ - work/chip-e.o - $(ANALYZE) $(RTL_DIR)/chip-sd-a.vhd -work/chip-sd-c.o: $(RTL_DIR)/chip-sd-c.vhd \ - work/chip-sd-a.o \ - work/spi_boot-c.o - $(ANALYZE) $(RTL_DIR)/chip-sd-c.vhd - -work/chip-minimal-a.o: $(RTL_DIR)/chip-minimal-a.vhd \ - work/chip-e.o - $(ANALYZE) $(RTL_DIR)/chip-minimal-a.vhd -work/chip-minimal-c.o: $(RTL_DIR)/chip-minimal-c.vhd \ - work/chip-minimal-a.o \ - work/spi_boot-c.o - $(ANALYZE) $(RTL_DIR)/chip-minimal-c.vhd - -work/ram_loader.o: $(RTL_DIR)/sample/ram_loader.vhd - $(ANALYZE) $(RTL_DIR)/sample/ram_loader.vhd -work/ram_loader-c.o: $(RTL_DIR)/sample/ram_loader-c.vhd \ - work/ram_loader.o - $(ANALYZE) $(RTL_DIR)/sample/ram_loader-c.vhd - -work/tb_pack-p.o: $(BENCH_DIR)/tb_pack-p.vhd - $(ANALYZE) $(BENCH_DIR)/tb_pack-p.vhd - -work/card.o: $(BENCH_DIR)/card.vhd \ - work/tb_pack-p.o - $(ANALYZE) $(BENCH_DIR)/card.vhd -work/card-c.o: $(BENCH_DIR)/card-c.vhd \ - work/card.o - $(ANALYZE) $(BENCH_DIR)/card-c.vhd - -work/tb_elem.o: $(BENCH_DIR)/tb_elem.vhd \ - work/spi_boot_pack-p.o \ - work/tb_pack-p.o - $(ANALYZE) $(BENCH_DIR)/tb_elem.vhd -work/tb_elem-full-c.o: $(BENCH_DIR)/tb_elem-full-c.vhd \ - work/tb_elem.o \ - work/chip-full-c.o \ - work/card-c.o - $(ANALYZE) $(BENCH_DIR)/tb_elem-full-c.vhd -work/tb_elem-mmc-c.o: $(BENCH_DIR)/tb_elem-mmc-c.vhd \ - work/tb_elem.o \ - work/chip-mmc-c.o \ - work/card-c.o - $(ANALYZE) $(BENCH_DIR)/tb_elem-mmc-c.vhd -work/tb_elem-sd-c.o: $(BENCH_DIR)/tb_elem-sd-c.vhd \ - work/tb_elem.o \ - work/chip-sd-c.o \ - work/card-c.o - $(ANALYZE) $(BENCH_DIR)/tb_elem-sd-c.vhd -work/tb_elem-minimal-c.o: $(BENCH_DIR)/tb_elem-minimal-c.vhd \ - work/tb_elem.o \ - work/chip-minimal-c.o \ - work/card-c.o - $(ANALYZE) $(BENCH_DIR)/tb_elem-minimal-c.vhd - -work/tb.o: $(BENCH_DIR)/tb.vhd - $(ANALYZE) $(BENCH_DIR)/tb.vhd -work/tb-c.o: $(BENCH_DIR)/tb-c.vhd \ - work/tb.o \ - work/tb_elem-full-c.o \ - work/tb_elem-mmc-c.o \ - work/tb_elem-sd-c.o \ - work/tb_elem-minimal-c.o - $(ANALYZE) $(BENCH_DIR)/tb-c.vhd - -work/tb_rl.o: $(BENCH_DIR)/tb_rl.vhd - $(ANALYZE) $(BENCH_DIR)/tb_rl.vhd -work/tb_rl-c.o: $(BENCH_DIR)/tb_rl-c.vhd \ - work/tb_rl.o \ - work/chip-full-c.o \ - work/card-c.o \ - work/ram_loader-c.o - $(ANALYZE) $(BENCH_DIR)/tb_rl-c.vhd - - -.PHONY: elaborate -elaborate: tb_behav_c0 tb_rl_behav_c0 - -tb_behav_c0: work/tb-c.o - $(ELABORATE) tb_behav_c0; \ - strip tb_behav_c0 - -tb_rl_behav_c0: work/tb_rl-c.o - $(ELABORATE) tb_rl_behav_c0; \ - strip tb_rl_behav_c0 - -.PHONY: analyze -analyze: work/tb-c.o work/tb_rl-c.o - -.PHONY: clean -clean: - rm -rf work tb_behav_c0 tb_rl_behav_c0 *~ diff --git a/opencores/spi_boot/sw/CVS/Entries b/opencores/spi_boot/sw/CVS/Entries deleted file mode 100644 index 0f2bd88d4..000000000 --- a/opencores/spi_boot/sw/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/misc//// diff --git a/opencores/spi_boot/sw/CVS/Repository b/opencores/spi_boot/sw/CVS/Repository deleted file mode 100644 index 98d181ecb..000000000 --- a/opencores/spi_boot/sw/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/sw diff --git a/opencores/spi_boot/sw/CVS/Root b/opencores/spi_boot/sw/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/sw/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/sw/CVS/Template b/opencores/spi_boot/sw/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/sw/misc/CVS/Entries b/opencores/spi_boot/sw/misc/CVS/Entries deleted file mode 100644 index e46425fde..000000000 --- a/opencores/spi_boot/sw/misc/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/bit_reverse.c/1.1/Sun May 21 11:58:00 2006/-ko/ -D diff --git a/opencores/spi_boot/sw/misc/CVS/Repository b/opencores/spi_boot/sw/misc/CVS/Repository deleted file mode 100644 index 0519f4b59..000000000 --- a/opencores/spi_boot/sw/misc/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -spi_boot/sw/misc diff --git a/opencores/spi_boot/sw/misc/CVS/Root b/opencores/spi_boot/sw/misc/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/spi_boot/sw/misc/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/spi_boot/sw/misc/CVS/Template b/opencores/spi_boot/sw/misc/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/spi_boot/sw/misc/bit_reverse.c b/opencores/spi_boot/sw/misc/bit_reverse.c deleted file mode 100644 index 9defb106a..000000000 --- a/opencores/spi_boot/sw/misc/bit_reverse.c +++ /dev/null @@ -1,74 +0,0 @@ -// Altera requires configuration bytes to be sent LSB first but the -// SD Card reads bytes MSB first -// This code reverses the bits of the altera bitstream so -// it will come out correct when read from the SD card -// $Log: bit_reverse.c,v $ -// Revision 1.1 2006/01/06 14:44:17 mbl -// initial version -// - - - -#include "stdio.h" -#include "string.h" - -FILE* fileOut; -FILE* fileIn; - -void outIOerror(char* pfn); -void inIOerror(char* pfn); - -int main(int argc, char* arg[]) -{ - unsigned char input, output; - unsigned char in_mask, out_mask; - int i; - - fileOut = fopen(arg[2],"wb"); - if (fileOut == NULL) - { - outIOerror(arg[2]); - exit(-1); - } - - printf("Opening input file %s\n", arg[1]); - fileIn = fopen(arg[1],"rb"); - if (fileIn == NULL) - { - inIOerror(arg[1]); - exit(-1); - } - - while (!feof(fileIn) && fgets((char*)&input, 2 ,fileIn) != NULL) - { - in_mask = 1; - out_mask = 0x80; - output = 0; - - for ( i=0; i < 8; ++i ) - { - if (input & in_mask) - { - output |= out_mask; - } - out_mask = out_mask >> 1; - in_mask = in_mask << 1; - } - fwrite((void*)&output,sizeof(char),1,fileOut); - } - - fclose(fileIn); - fclose(fileOut); - printf("\n%s has been created\n", arg[2]); - exit(0); -} - -void outIOerror(char *pfn) -{ - printf("I/O Error while writing to file=%s\n",pfn); -} - -void inIOerror(char *pfn) -{ - printf("I/O Error while reading file=%s\n",pfn); -} diff --git a/opencores/wb_zbt/CVS/Entries b/opencores/wb_zbt/CVS/Entries deleted file mode 100644 index ef78b4f27..000000000 --- a/opencores/wb_zbt/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/wb_zbt.v/1.1/Tue Feb 5 22:31:22 2008// -D diff --git a/opencores/wb_zbt/CVS/Repository b/opencores/wb_zbt/CVS/Repository deleted file mode 100644 index ca9c641d0..000000000 --- a/opencores/wb_zbt/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -wb_zbt diff --git a/opencores/wb_zbt/CVS/Root b/opencores/wb_zbt/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/wb_zbt/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/wb_zbt/CVS/Template b/opencores/wb_zbt/CVS/Template deleted file mode 100644 index e69de29bb..000000000 diff --git a/opencores/wb_zbt/wb_zbt.v b/opencores/wb_zbt/wb_zbt.v deleted file mode 100644 index 8f9232752..000000000 --- a/opencores/wb_zbt/wb_zbt.v +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Multi-port ZBT SRAM WISHBONE controller - * Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net - * This file is part of Milkymist. - * - * Milkymist is free software; you can redistribute it and/or modify it - * under the terms of the GNU Library General Public License as published - * by the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Library General Public License for more details. - * - * You should have received a copy of the GNU Library General Public - * License along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, - * USA. - */ - -module wb_zbt( - input clk, - input rst, - // Wishbone bus A, highest priority, with prefetch - input [31:0] wbA_adr_i, - input [31:0] wbA_dat_i, - output [31:0] wbA_dat_o, - input [ 3:0] wbA_sel_i, - input wbA_cyc_i, - input wbA_stb_i, - output wbA_ack_o, - input wbA_we_i, - // Wishbone bus B, lower priority - input [31:0] wbB_adr_i, - input [31:0] wbB_dat_i, - output [31:0] wbB_dat_o, - input [ 3:0] wbB_sel_i, - input wbB_cyc_i, - input wbB_stb_i, - output wbB_ack_o, - input wbB_we_i, - // Memory connection - output sram_clk, - output [17:0] sram_a, - inout [31:0] sram_d, - output sram_we, - output [ 3:0] sram_bw, - output sram_adv, - output sram_ce, - output sram_oe, - output sram_mode, - output sram_zz -); - -assign sram_clk = clk; -assign sram_oe = 1'b0; -assign sram_ce = 1'b0; -assign sram_adv = 1'b0; -assign sram_mode = 1'b0; -assign sram_zz = 1'b0; - -/* Wishbone decoding */ - -wire busA_active; -wire busB_active; - -assign busA_active = wbA_cyc_i & wbA_stb_i; -assign busB_active = wbB_cyc_i & wbB_stb_i; - -/* Those are used to represent the state of the SRAM pipeline - * Bit 0 = Write Enable - * Bits 18..1 = Address - */ -wire [18:0] pipeline_in; -reg [18:0] pipeline_internal; -reg [18:0] pipeline_out; - -always @(posedge clk or posedge rst) begin - if(rst) begin - pipeline_internal <= 0; - pipeline_out <= 0; - end else begin - pipeline_internal <= pipeline_in; - pipeline_out <= pipeline_internal; - end -end - -/* Pipeline contents decode */ - -wire inprogressA; -wire inprogressB; - -assign inprogressA = (pipeline_internal[18:1] == wbA_adr_i[19:2]) & (pipeline_internal[0] == wbA_we_i); -assign inprogressB = (pipeline_internal[18:1] == wbB_adr_i[19:2]) & (pipeline_internal[0] == wbB_we_i); - -wire hitA; -wire hitB; - -assign hitA = (pipeline_out[18:1] == wbA_adr_i[19:2]) & (pipeline_out[0] == wbA_we_i); -assign hitB = (pipeline_out[18:1] == wbB_adr_i[19:2]) & (pipeline_out[0] == wbB_we_i); - -/* Access arbitration */ - -wire [1:0] bus_request; - -assign bus_request[0] = busA_active & ~inprogressA & ~hitA; -assign bus_request[1] = busB_active & ~inprogressB & ~hitB; - -wire prefetch_enable; -reg [17:0] prefetch_address; - -assign prefetch_enable = ~bus_request[0] & ~bus_request[1]; -always @(posedge clk) begin - if(prefetch_enable) - prefetch_address <= wbA_adr_i[19:2] + 2; - else - prefetch_address <= wbA_adr_i[19:2] + 1; -end - -wire [1:0] bus_selected; - -assign bus_selected[0] = bus_request[0]; -assign bus_selected[1] = bus_request[1] & ~bus_request[0]; - -assign pipeline_in[18:1] = ({18{bus_selected[0]}} & wbA_adr_i[19:2]) - | ({18{bus_selected[1]}} & wbB_adr_i[19:2]) - | ({18{prefetch_enable}} & prefetch_address); -assign pipeline_in[0] = (bus_selected[0] & wbA_we_i)|(bus_selected[1] & wbB_we_i); - -/* SRAM control */ - -assign sram_a = pipeline_in[18:1]; -assign sram_bw = ~(({4{bus_selected[0]}} & wbA_sel_i)|({4{bus_selected[1]}} & wbB_sel_i)); -assign sram_we = ~pipeline_in[0]; - -/* SRAM data */ - -wire [31:0] bus_wdata; - -assign wbA_ack_o = busA_active & hitA; -assign wbB_ack_o = busB_active & hitB; - -assign bus_wdata = ({32{hitA}} & wbA_dat_i)|({32{hitB}} & wbB_dat_i); -assign sram_d = pipeline_out[0] ? bus_wdata : 32'hzzzzzzzz; -assign wbA_dat_o = sram_d; -assign wbB_dat_o = sram_d; - -endmodule diff --git a/sdr_lib/.gitignore b/sdr_lib/.gitignore deleted file mode 100644 index 3c782d589..000000000 --- a/sdr_lib/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/a.out -/db -/*.vcd diff --git a/sdr_lib/HB.sav b/sdr_lib/HB.sav deleted file mode 100644 index c5087e8a6..000000000 --- a/sdr_lib/HB.sav +++ /dev/null @@ -1,56 +0,0 @@ -[size] 1400 967 -[pos] -1 -1 -*-46.395245 2565000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] hb_dec_tb. -@420 -hb_dec_tb.data_in[17:0] -@28 -hb_dec_tb.strobe_in -hb_dec_tb.strobe_out -hb_dec_tb.uut.write_even -@22 -hb_dec_tb.uut.addr_even[3:0] -@420 -hb_dec_tb.uut.data_even[17:0] -hb_dec_tb.uut.data_odd_a[17:0] -hb_dec_tb.uut.data_odd_b[17:0] -hb_dec_tb.uut.data_odd_c[17:0] -hb_dec_tb.uut.data_odd_d[17:0] -@28 -hb_dec_tb.uut.write_odd -@420 -hb_dec_tb.uut.prod1[35:0] -hb_dec_tb.uut.prod2[35:0] -@24 -hb_dec_tb.uut.phase[2:0] -@28 -hb_dec_tb.uut.stb_in -hb_dec_tb.uut.stb_out -@420 -hb_dec_tb.uut.sum2[17:0] -hb_dec_tb.uut.stb_out_pre[15:0] -@28 -hb_dec_tb.uut.do_acc -hb_dec_tb.uut.clear -@420 -hb_dec_tb.uut.sum1[17:0] -hb_dec_tb.uut.coeff1[17:0] -hb_dec_tb.uut.prod1[35:0] -hb_dec_tb.uut.prod2[35:0] -hb_dec_tb.uut.final_sum[17:0] -hb_dec_tb.uut.coeff2[17:0] -hb_dec_tb.uut.sum_of_prod[21:0] -hb_dec_tb.data_out[17:0] -@28 -hb_dec_tb.uut.do_acc -hb_dec_tb.uut.clear -@24 -hb_dec_tb.uut.addr_odd_a[3:0] -hb_dec_tb.uut.addr_odd_b[3:0] -hb_dec_tb.uut.addr_odd_c[3:0] -hb_dec_tb.uut.addr_odd_d[3:0] -@28 -hb_dec_tb.uut.write_odd -hb_dec_tb.uut.write_even -@22 -hb_dec_tb.uut.data_even[17:0] diff --git a/sdr_lib/SMALL_HB.sav b/sdr_lib/SMALL_HB.sav deleted file mode 100644 index 96ba00636..000000000 --- a/sdr_lib/SMALL_HB.sav +++ /dev/null @@ -1,40 +0,0 @@ -[size] 1400 967 -[pos] -1 -1 -*-11.608687 1834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] small_hb_dec_tb. -[treeopen] small_hb_dec_tb.uut. -@28 -small_hb_dec_tb.uut.clk -small_hb_dec_tb.uut.phase -@10421 -small_hb_dec_tb.uut.data_in[17:0] -@420 -small_hb_dec_tb.uut.d1[17:0] -small_hb_dec_tb.uut.d2[17:0] -small_hb_dec_tb.uut.d3[17:0] -small_hb_dec_tb.uut.d4[17:0] -small_hb_dec_tb.uut.d5[17:0] -small_hb_dec_tb.uut.d6[17:0] -small_hb_dec_tb.uut.coeff[17:0] -small_hb_dec_tb.uut.sum[17:0] -small_hb_dec_tb.uut.prod[35:0] -small_hb_dec_tb.uut.accum_rnd[17:0] -@28 -small_hb_dec_tb.uut.stb_in -@420 -small_hb_dec_tb.uut.final_sum[17:0] -@28 -small_hb_dec_tb.uut.go -small_hb_dec_tb.uut.go_d1 -small_hb_dec_tb.uut.go_d2 -small_hb_dec_tb.uut.go_d3 -small_hb_dec_tb.uut.go_d4 -small_hb_dec_tb.uut.stb_out -@420 -small_hb_dec_tb.uut.data_out[17:0] -small_hb_dec_tb.uut.prod[35:0] -small_hb_dec_tb.uut.accum_rnd[17:0] -small_hb_dec_tb.uut.final_sum[17:0] -@10421 -small_hb_dec_tb.uut.round_acc.out[17:0] -small_hb_dec_tb.uut.data_out[17:0] diff --git a/sdr_lib/acc.v b/sdr_lib/acc.v deleted file mode 100644 index a2da9c86d..000000000 --- a/sdr_lib/acc.v +++ /dev/null @@ -1,28 +0,0 @@ - -module acc - #(parameter IWIDTH=16, OWIDTH=30) - (input clk, - input clear, - input acc, - input [IWIDTH-1:0] in, - output reg [OWIDTH-1:0] out); - - wire [OWIDTH-1:0] in_signext; - sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) - acc_signext (.in(in),.out(in_signext)); - - // CLEAR & ~ACC --> clears the accumulator - // CLEAR & ACC --> loads the accumulator - // ~CLEAR & ACC --> accumulates - // ~CLEAR & ~ACC --> hold - - wire [OWIDTH-1:0] addend1 = clear ? 0 : out; - wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext; - wire [OWIDTH-1:0] sum_int = addend1 + addend2; - - always @(posedge clk) - out <= sum_int; - -endmodule // acc - - diff --git a/sdr_lib/add2.v b/sdr_lib/add2.v deleted file mode 100644 index 13fff803e..000000000 --- a/sdr_lib/add2.v +++ /dev/null @@ -1,11 +0,0 @@ - -module add2 - #(parameter WIDTH=16) - (input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output [WIDTH-1:0] sum); - - wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; - assign sum = sum_int[WIDTH:1]; // Note -- will have some bias - -endmodule // add2 diff --git a/sdr_lib/add2_and_round.v b/sdr_lib/add2_and_round.v deleted file mode 100644 index 146af28da..000000000 --- a/sdr_lib/add2_and_round.v +++ /dev/null @@ -1,11 +0,0 @@ - -module add2_and_round - #(parameter WIDTH=16) - (input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output [WIDTH-1:0] sum); - - wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; - assign sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]); - -endmodule // add2_and_round diff --git a/sdr_lib/add2_and_round_reg.v b/sdr_lib/add2_and_round_reg.v deleted file mode 100644 index e7fcbf1a1..000000000 --- a/sdr_lib/add2_and_round_reg.v +++ /dev/null @@ -1,16 +0,0 @@ - -module add2_and_round_reg - #(parameter WIDTH=16) - (input clk, - input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output reg [WIDTH-1:0] sum); - - wire [WIDTH-1:0] sum_int; - - add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int)); - - always @(posedge clk) - sum <= sum_int; - -endmodule // add2_and_round_reg diff --git a/sdr_lib/add2_reg.v b/sdr_lib/add2_reg.v deleted file mode 100644 index 456cf315b..000000000 --- a/sdr_lib/add2_reg.v +++ /dev/null @@ -1,17 +0,0 @@ - -module add2_reg - #(parameter WIDTH=16) - (input clk, - input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output reg [WIDTH-1:0] sum); - - wire [WIDTH-1:0] sum_int; - - add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int)); - - always @(posedge clk) - sum <= sum_int; - -endmodule // add2_reg - diff --git a/sdr_lib/cic_dec_shifter.v b/sdr_lib/cic_dec_shifter.v deleted file mode 100644 index aa5ac895b..000000000 --- a/sdr_lib/cic_dec_shifter.v +++ /dev/null @@ -1,106 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// NOTE This only works for N=4, max decim rate of 128 -// NOTE signal "rate" is EQUAL TO the actual rate, no more -1 BS - -module cic_dec_shifter(rate,signal_in,signal_out); - parameter bw = 16; - parameter maxbitgain = 28; - - input [7:0] rate; - input wire [bw+maxbitgain-1:0] signal_in; - output reg [bw-1:0] signal_out; - - function [4:0] bitgain; - input [7:0] rate; - case(rate) - // Exact Cases -- N*log2(rate) - 8'd1 : bitgain = 0; - 8'd2 : bitgain = 4; - 8'd4 : bitgain = 8; - 8'd8 : bitgain = 12; - 8'd16 : bitgain = 16; - 8'd32 : bitgain = 20; - 8'd64 : bitgain = 24; - 8'd128 : bitgain = 28; - - // Nearest without overflow -- ceil(N*log2(rate)) - 8'd3 : bitgain = 7; - 8'd5 : bitgain = 10; - 8'd6 : bitgain = 11; - 8'd7 : bitgain = 12; - 8'd9 : bitgain = 13; - 8'd10,8'd11 : bitgain = 14; - 8'd12,8'd13 : bitgain = 15; - 8'd14,8'd15 : bitgain = 16; - 8'd17,8'd18,8'd19 : bitgain = 17; - 8'd20,8'd21,8'd22 : bitgain = 18; - 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; - 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; - 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; - 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; - 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; - 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; - 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; - 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; - 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; - default : bitgain = 28; - endcase // case(rate) - endfunction // bitgain - - wire [4:0] shift = bitgain(rate); - - // We should be able to do this, but can't .... - // assign signal_out = signal_in[shift+bw-1:shift]; - - always @* - case(shift) - 5'd0 : signal_out = signal_in[0+bw-1:0]; - 5'd4 : signal_out = signal_in[4+bw-1:4]; - 5'd7 : signal_out = signal_in[7+bw-1:7]; - 5'd8 : signal_out = signal_in[8+bw-1:8]; - 5'd10 : signal_out = signal_in[10+bw-1:10]; - 5'd11 : signal_out = signal_in[11+bw-1:11]; - 5'd12 : signal_out = signal_in[12+bw-1:12]; - 5'd13 : signal_out = signal_in[13+bw-1:13]; - 5'd14 : signal_out = signal_in[14+bw-1:14]; - 5'd15 : signal_out = signal_in[15+bw-1:15]; - 5'd16 : signal_out = signal_in[16+bw-1:16]; - 5'd17 : signal_out = signal_in[17+bw-1:17]; - 5'd18 : signal_out = signal_in[18+bw-1:18]; - 5'd19 : signal_out = signal_in[19+bw-1:19]; - 5'd20 : signal_out = signal_in[20+bw-1:20]; - 5'd21 : signal_out = signal_in[21+bw-1:21]; - 5'd22 : signal_out = signal_in[22+bw-1:22]; - 5'd23 : signal_out = signal_in[23+bw-1:23]; - 5'd24 : signal_out = signal_in[24+bw-1:24]; - 5'd25 : signal_out = signal_in[25+bw-1:25]; - 5'd26 : signal_out = signal_in[26+bw-1:26]; - 5'd27 : signal_out = signal_in[27+bw-1:27]; - 5'd28 : signal_out = signal_in[28+bw-1:28]; - - default : signal_out = signal_in[28+bw-1:28]; - endcase // case(shift) - -endmodule // cic_dec_shifter - diff --git a/sdr_lib/cic_decim.v b/sdr_lib/cic_decim.v deleted file mode 100755 index 9a03081b0..000000000 --- a/sdr_lib/cic_decim.v +++ /dev/null @@ -1,88 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -module cic_decim - #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7) - (input clock, - input reset, - input enable, - input [7:0] rate, - input strobe_in, - input strobe_out, - input [bw-1:0] signal_in, - output reg [bw-1:0] signal_out); - - localparam maxbitgain = N * log2_of_max_rate; - - wire [bw+maxbitgain-1:0] signal_in_ext; - reg [bw+maxbitgain-1:0] integrator [0:N-1]; - reg [bw+maxbitgain-1:0] differentiator [0:N-1]; - reg [bw+maxbitgain-1:0] pipeline [0:N-1]; - reg [bw+maxbitgain-1:0] sampler; - - integer i; - - sign_extend #(bw,bw+maxbitgain) - ext_input (.in(signal_in),.out(signal_in_ext)); - - always @(posedge clock) - if(reset) - for(i=0;i "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - cordic_z24 #(.bitwidth(24)) - cordic(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]), - .xo(i_cordic),.yo(q_cordic),.zo() ); - - cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate), - .strobe_fast(1),.strobe_slow(strobe_cic) ); - - cic_decim #(.bw(24)) - decim_i (.clock(clk),.reset(rst),.enable(run), - .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), - .signal_in(i_cordic),.signal_out(i_cic)); - - cic_decim #(.bw(24)) - decim_q (.clock(clk),.reset(rst),.enable(run), - .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), - .signal_in(q_cordic),.signal_out(q_cic)); - - round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled)); - round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled)); - reg strobe_cic_d1; - always @(posedge clk) strobe_cic_d1 <= strobe_cic; - - small_hb_dec #(.WIDTH(18)) small_hb_i - (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), - .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1)); - - small_hb_dec #(.WIDTH(18)) small_hb_q - (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), - .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1)); - - wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate}; - hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), - .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2)); - - hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), - .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); - - round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); - round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); - - // Streaming GPIO - // - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - - reg [31:0] sample_reg; - always @(posedge clk) - begin - sample_reg[31:17] <= i_out[15:1]; - sample_reg[15:1] <= q_out[15:1]; - sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; - sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; - end - - assign sample = sample_reg; - assign strobe = strobe_hb2; - assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; - -endmodule // dsp_core_rx diff --git a/sdr_lib/dsp_core_tx.v b/sdr_lib/dsp_core_tx.v deleted file mode 100644 index 346d65ced..000000000 --- a/sdr_lib/dsp_core_tx.v +++ /dev/null @@ -1,152 +0,0 @@ - -`define DSP_CORE_TX_BASE 128 - -module dsp_core_tx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - output reg [15:0] dac_a, - output reg [15:0] dac_b, - - // To tx_control - input [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] i, q, scale_i, scale_q; - wire [31:0] phase_inc; - reg [31:0] phase; - wire [7:0] interp_rate; - wire [3:0] dacmux_a, dacmux_b; - wire enable_hb1, enable_hb2; - - setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_TX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_TX_BASE+4)) sr_4 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({dacmux_b,dacmux_a}),.changed()); - - // Strobes are all now delayed by 1 cycle for timing reasons - wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre; - reg strobe_cic = 1; - reg strobe_hb1 = 1; - reg strobe_hb2 = 1; - - cic_strober #(.WIDTH(8)) - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), - .strobe_fast(1),.strobe_slow(strobe_cic_pre) ); - cic_strober #(.WIDTH(2)) - hb2_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb2 ? 2 : 1), - .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) ); - cic_strober #(.WIDTH(2)) - hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb1 ? 2 : 1), - .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) ); - - always @(posedge clk) strobe_hb1 <= strobe_hb1_pre; - always @(posedge clk) strobe_hb2 <= strobe_hb2_pre; - always @(posedge clk) strobe_cic <= strobe_cic_pre; - - // NCO - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - wire signed [17:0] da, db; - wire signed [35:0] prod_i, prod_q; - - wire [17:0] bb_i = {sample[31:16],2'b0}; - wire [17:0] bb_q = {sample[15:0],2'b0}; - wire [17:0] i_interp, q_interp; - - wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q; - - wire [7:0] cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate; - // Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true, - // but the default case inside hb_interp handles this - - hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_i - (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_i),.stb_out(strobe_hb2),.data_out(hb1_i)); - hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_q - (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_q),.stb_out(strobe_hb2),.data_out(hb1_q)); - - small_hb_int #(.WIDTH(18)) small_hb_interp_i - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i), - .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i)); - small_hb_int #(.WIDTH(18)) small_hb_interp_q - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q), - .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q)); - - cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) - cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), - .strobe_in(strobe_cic),.strobe_out(1), - .signal_in(hb2_i),.signal_out(i_interp)); - - cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) - cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), - .strobe_in(strobe_cic),.strobe_out(1), - .signal_in(hb2_q),.signal_out(q_interp)); - - assign strobe = strobe_hb1; - - localparam cwidth = 24; // was 18 - localparam zwidth = 24; // was 16 - - wire [cwidth-1:0] da_c, db_c; - - cordic_z24 #(.bitwidth(cwidth)) - cordic(.clock(clk), .reset(rst), .enable(run), - .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}), - .zi(phase[31:32-zwidth]), - .xo(da_c),.yo(db_c),.zo() ); - - MULT18X18S MULT18X18S_inst - (.P(prod_i), // 36-bit multiplier output - .A(da_c[cwidth-1:cwidth-18]), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S MULT18X18S_inst_2 - (.P(prod_q), // 36-bit multiplier output - .A(db_c[cwidth-1:cwidth-18]), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - always @(posedge clk) - case(dacmux_a) - 0 : dac_a <= prod_i[28:13]; - 1 : dac_a <= prod_q[28:13]; - default : dac_a <= 0; - endcase // case(dacmux_a) - - always @(posedge clk) - case(dacmux_b) - 0 : dac_b <= prod_i[28:13]; - 1 : dac_b <= prod_q[28:13]; - default : dac_b <= 0; - endcase // case(dacmux_b) - - assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run}; - -endmodule // dsp_core diff --git a/sdr_lib/duc.v b/sdr_lib/duc.v deleted file mode 100755 index 6dac95b49..000000000 --- a/sdr_lib/duc.v +++ /dev/null @@ -1,95 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// DUC block - -module duc(input clock, - input reset, - input enable, - input [3:0] rate1, - input [3:0] rate2, - output strobe, - input [31:0] freq, - input [15:0] i_in, - input [15:0] q_in, - output [15:0] i_out, - output [15:0] q_out - ); - parameter bw = 16; - parameter zw = 16; - - wire [15:0] i_interp_out, q_interp_out; - wire [31:0] phase; - - wire strobe1, strobe2; - reg [3:0] strobe_ctr1,strobe_ctr2; - - always @(posedge clock) - if(reset | ~enable) - strobe_ctr2 <= #1 4'd0; - else if(strobe2) - strobe_ctr2 <= #1 4'd0; - else - strobe_ctr2 <= #1 strobe_ctr2 + 4'd1; - - always @(posedge clock) - if(reset | ~enable) - strobe_ctr1 <= #1 4'd0; - else if(strobe1) - strobe_ctr1 <= #1 4'd0; - else if(strobe2) - strobe_ctr1 <= #1 strobe_ctr1 + 4'd1; - - - assign strobe2 = enable & ( strobe_ctr2 == rate2 ); - assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 ); - - assign strobe = strobe1; - - function [2:0] log_ceil; - input [3:0] val; - - log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; - endfunction - - wire [2:0] shift1 = log_ceil(rate1); - wire [2:0] shift2 = log_ceil(rate2); - - cordic #(.bitwidth(bw),.zwidth(zw),.stages(16)) - cordic(.clock(clock), .reset(reset), .enable(enable), - .xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]), - .xo(i_out), .yo(q_out), .zo() ); - - cic_interp_2stage #(.bw(bw),.N(4)) - interp_i(.clock(clock),.reset(reset),.enable(enable), - .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), - .signal_in(i_in),.signal_out(i_interp_out)); - - cic_interp_2stage #(.bw(bw),.N(4)) - interp_q(.clock(clock),.reset(reset),.enable(enable), - .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), - .signal_in(q_in),.signal_out(q_interp_out)); - - phase_acc #(.resolution(32)) - nco (.clk(clock),.reset(reset),.enable(enable), - .freq(freq),.phase(phase)); - -endmodule diff --git a/sdr_lib/dummy_rx.v b/sdr_lib/dummy_rx.v deleted file mode 100644 index 99290ecec..000000000 --- a/sdr_lib/dummy_rx.v +++ /dev/null @@ -1,62 +0,0 @@ - -`define DSP_CORE_RX_BASE 160 -module dummy_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - output [31:0] sample, - input run, - output strobe - ); - - wire [15:0] scale_i, scale_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [23:0] i_decim, q_decim; - wire [7:0] decim_rate; - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(decim_rate),.changed()); - - strobe_gen strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_in(1),.strobe(strobe) ); - - reg [15:0] i_out, q_out; - assign sample = {i_out,q_out}; - - always @(posedge clk) - if(rst) - i_out <= 0; - else if(~run) - i_out <= 0; - else if(strobe) - i_out <= i_out + 1; - - reg run_d1; - always @(posedge clk) - if(rst) - run_d1 <= 0; - else - run_d1 <= run; - - always @(posedge clk) - if(rst) - q_out <= 0; - else if (run & ~run_d1) - q_out <= q_out + 1; - - -endmodule // dsp_core_rx diff --git a/sdr_lib/gen_cordic_consts.py b/sdr_lib/gen_cordic_consts.py deleted file mode 100755 index 261e8c223..000000000 --- a/sdr_lib/gen_cordic_consts.py +++ /dev/null @@ -1,10 +0,0 @@ -#!/usr/bin/env python - -import math - -zwidth = 24 - -for i in range(24): - c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth) - print "localparam c%02d = %d'd%d;" % (i, zwidth, round (c)) - diff --git a/sdr_lib/halfband_ideal.v b/sdr_lib/halfband_ideal.v deleted file mode 100644 index 484cfff2a..000000000 --- a/sdr_lib/halfband_ideal.v +++ /dev/null @@ -1,84 +0,0 @@ -module halfband_ideal ( - input clock, - input reset, - input enable, - input strobe_in, - input wire signed [17:0] data_in, - output reg strobe_out, - output reg signed [17:0] data_out -) ; - - parameter decim = 1 ; - parameter rate = 2 ; - - reg signed [40:0] temp ; - reg signed [17:0] delay[30:0] ; - reg signed [17:0] coeffs[30:0] ; - reg [7:0] count ; - integer i ; - - initial begin - for( i = 0 ; i < 31 ; i = i + 1 ) begin - coeffs[i] = 18'd0 ; - end - coeffs[0] = -1390 ; - coeffs[2] = 1604 ; - coeffs[4] = -1896 ; - coeffs[6] = 2317 ; - coeffs[8] = -2979 ; - coeffs[10] = 4172 ; - coeffs[12] = -6953 ; - coeffs[14] = 20860 ; - coeffs[15] = 32768 ; - coeffs[16] = 20860 ; - coeffs[18] = -6953 ; - coeffs[20] = 4172 ; - coeffs[22] = -2979 ; - coeffs[24] = 2317 ; - coeffs[26] = -1896 ; - coeffs[28] = 1604 ; - coeffs[30] = -1390 ; - end - - always @(posedge clock) begin - if( reset ) begin - count <= 0 ; - for( i = 0 ; i < 31 ; i = i + 1 ) begin - delay[i] <= 18'd0 ; - end - temp <= 41'd0 ; - data_out <= 18'd0 ; - strobe_out <= 1'b0 ; - end else if( enable ) begin - - if( (decim && (count == rate-1)) || !decim ) - strobe_out <= strobe_in ; - else - strobe_out <= 1'b0 ; - - - if( strobe_in ) begin - // Increment decimation count - count <= count + 1 ; - - // Shift the input - for( i = 30 ; i > 0 ; i = i - 1 ) begin - delay[i] = delay[i-1] ; - end - delay[0] = data_in ; - - // clear the temp reg - temp = 18'd0 ; - if( (decim && (count == rate-1)) || !decim ) begin - count <= 0 ; - for( i = 0 ; i < 31 ; i = i + 1 ) begin - // Multiply Accumulate - temp = temp + delay[i]*coeffs[i] ; - end - // Assign data output - data_out <= temp >>> 15 ; - end - end - end - end -endmodule diff --git a/sdr_lib/halfband_tb.v b/sdr_lib/halfband_tb.v deleted file mode 100644 index 231dd00d7..000000000 --- a/sdr_lib/halfband_tb.v +++ /dev/null @@ -1,120 +0,0 @@ -module halfband_tb( ) ; - - // Parameters for instantiation - parameter clocks = 2 ; // Number of clocks per input - parameter decim = 0 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - reg strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #100 reset = 1'b0 ; - - // Enable the entire system - initial enable = 1'b1 ; - - // Instantiate UUT - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - - integer i, ri, ro, infile, outfile ; - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - strobe_in <= 1'd0 ; - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( posedge clock ) begin - #1 ; - strobe_in <= 1'b1 ; - if( !$feof(infile) ) - ri = $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - - // Clocked in - set the strobe to 0 if the number of - // clocks per sample is greater than 1 - if( clocks > 1 ) begin - @(posedge clock) begin - strobe_in <= 1'b0 ; - end - - // Wait for the specified number of cycles - for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin - @(posedge clock) #1 ; - end - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $stop ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - $display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - endofsim <= 1'b1 ; - end - end - end - -endmodule diff --git a/sdr_lib/hb/acc.v b/sdr_lib/hb/acc.v deleted file mode 100644 index 195d5ea94..000000000 --- a/sdr_lib/hb/acc.v +++ /dev/null @@ -1,22 +0,0 @@ - - -module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, - input signed [30:0] addend, output reg signed [33:0] sum ); - - always @(posedge clock) - if(reset) - sum <= #1 34'd0; - //else if(clear & enable_in) - // sum <= #1 addend; - //else if(clear) - // sum <= #1 34'd0; - else if(clear) - sum <= #1 addend; - else if(enable_in) - sum <= #1 sum + addend; - - always @(posedge clock) - enable_out <= #1 enable_in; - -endmodule // acc - diff --git a/sdr_lib/hb/coeff_ram.v b/sdr_lib/hb/coeff_ram.v deleted file mode 100644 index 65460822f..000000000 --- a/sdr_lib/hb/coeff_ram.v +++ /dev/null @@ -1,26 +0,0 @@ - - -module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data); - - always @(posedge clock) - case (rd_addr) - 4'd0 : rd_data <= #1 -16'd16; - 4'd1 : rd_data <= #1 16'd74; - 4'd2 : rd_data <= #1 -16'd254; - 4'd3 : rd_data <= #1 16'd669; - 4'd4 : rd_data <= #1 -16'd1468; - 4'd5 : rd_data <= #1 16'd2950; - 4'd6 : rd_data <= #1 -16'd6158; - 4'd7 : rd_data <= #1 16'd20585; - 4'd8 : rd_data <= #1 16'd20585; - 4'd9 : rd_data <= #1 -16'd6158; - 4'd10 : rd_data <= #1 16'd2950; - 4'd11 : rd_data <= #1 -16'd1468; - 4'd12 : rd_data <= #1 16'd669; - 4'd13 : rd_data <= #1 -16'd254; - 4'd14 : rd_data <= #1 16'd74; - 4'd15 : rd_data <= #1 -16'd16; - default : rd_data <= #1 16'd0; - endcase // case(rd_addr) - -endmodule // ram diff --git a/sdr_lib/hb/coeff_rom.v b/sdr_lib/hb/coeff_rom.v deleted file mode 100644 index 7f8886b4e..000000000 --- a/sdr_lib/hb/coeff_rom.v +++ /dev/null @@ -1,19 +0,0 @@ - - -module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); - - always @(posedge clock) - case (addr) - 3'd0 : data <= #1 -16'd49; - 3'd1 : data <= #1 16'd165; - 3'd2 : data <= #1 -16'd412; - 3'd3 : data <= #1 16'd873; - 3'd4 : data <= #1 -16'd1681; - 3'd5 : data <= #1 16'd3135; - 3'd6 : data <= #1 -16'd6282; - 3'd7 : data <= #1 16'd20628; - endcase // case(addr) - -endmodule // coeff_rom - - diff --git a/sdr_lib/hb/halfband_decim.v b/sdr_lib/hb/halfband_decim.v deleted file mode 100644 index dff4d902c..000000000 --- a/sdr_lib/hb/halfband_decim.v +++ /dev/null @@ -1,163 +0,0 @@ -/* -*- verilog -*- - * - * USRP - Universal Software Radio Peripheral - * - * Copyright (C) 2005 Matt Ettus - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA - */ - -/* - * This implements a 31-tap halfband filter that decimates by two. - * The coefficients are symmetric, and with the exception of the middle tap, - * every other coefficient is zero. The middle section of taps looks like this: - * - * ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ... - * | - * middle tap -------+ - * - * See coeff_rom.v for the full set. The taps are scaled relative to 32768, - * thus the middle tap equals 1.0. Not counting the middle tap, there are 8 - * non-zero taps on each side, and they are symmetric. A naive implementation - * requires a mulitply for each non-zero tap. Because of symmetry, we can - * replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output - * sample, we need to perform 8 multiplications. Since the middle tap is 1.0, - * we just add the corresponding delay line value. - * - * About timing: We implement this with a single multiplier, so it takes - * 8 cycles to compute a single output. However, since we're decimating by two - * we can accept a new input value every 4 cycles. strobe_in is asserted when - * there's a new input sample available. Depending on the overall decimation - * rate, strobe_in may be asserted less frequently than once every 4 clocks. - * On the output side, we assert strobe_out when output contains a new sample. - * - * Implementation: Every time strobe_in is asserted we store the new data into - * the delay line. We split the delay line into two components, one for the - * even samples, and one for the odd samples. ram16_odd is the delay line for - * the odd samples. This ram is written on each odd assertion of strobe_in, and - * is read on each clock when we're computing the dot product. ram16_even is - * similar, although because it holds the even samples we must be able to read - * two samples from different addresses at the same time, while writing the incoming - * even samples. Thus it's "triple-ported". - */ - -module halfband_decim - (input clock, input reset, input enable, input strobe_in, output wire strobe_out, - input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl); - - reg [3:0] rd_addr1; - reg [3:0] rd_addr2; - reg [3:0] phase; - reg [3:0] base_addr; - - wire signed [15:0] mac_out,middle_data, sum, coeff; - wire signed [30:0] product; - wire signed [33:0] sum_even; - wire clear; - reg store_odd; - - always @(posedge clock) - if(reset) - store_odd <= #1 1'b0; - else - if(strobe_in) - store_odd <= #1 ~store_odd; - - wire start = strobe_in & store_odd; - always @(posedge clock) - if(reset) - base_addr <= #1 4'd0; - else if(start) - base_addr <= #1 base_addr + 4'd1; - - always @(posedge clock) - if(reset) - phase <= #1 4'd8; - else if (start) - phase <= #1 4'd0; - else if(phase != 4'd8) - phase <= #1 phase + 4'd1; - - reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD; - always @(posedge clock) - begin - start_d1 <= #1 start; - start_d2 <= #1 start_d1; - start_d3 <= #1 start_d2; - start_d4 <= #1 start_d3; - start_d5 <= #1 start_d4; - start_d6 <= #1 start_d5; - start_d7 <= #1 start_d6; - start_d8 <= #1 start_d7; - start_d9 <= #1 start_d8; - start_dA <= #1 start_d9; - start_dB <= #1 start_dA; - start_dC <= #1 start_dB; - start_dD <= #1 start_dC; - end // always @ (posedge clock) - - reg mult_en, mult_en_pre; - always @(posedge clock) - begin - mult_en_pre <= #1 phase!=8; - mult_en <= #1 mult_en_pre; - end - - assign clear = start_d4; // was dC - wire latch_result = start_d4; // was dC - assign strobe_out = start_d5; // was dD - wire acc_en; - - always @* - case(phase[2:0]) - 3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end - 3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end - 3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end - 3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end - 3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end - 3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end - 3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end - 3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end - default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end - endcase // case(phase) - - coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff)); - - ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), - .wr_addr(base_addr),.wr_data(data_in), - .rd_addr1(rd_addr1),.rd_addr2(rd_addr2), - .sum(sum)); - - ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items - .wr_addr(base_addr),.wr_data(data_in), - //.rd_addr(base_addr+4'd7),.rd_data(middle_data)); - .rd_addr(base_addr+4'd6),.rd_data(middle_data)); - - mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en)); - - acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(), - .clear(clear),.addend(product),.sum(sum_even)); - - wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!! - - always @(posedge clock) - if(reset) - data_out <= #1 16'd0; - else if(latch_result) - data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]); - - assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase}; - -endmodule // halfband_decim diff --git a/sdr_lib/hb/halfband_interp.v b/sdr_lib/hb/halfband_interp.v deleted file mode 100644 index cdb11c1f6..000000000 --- a/sdr_lib/hb/halfband_interp.v +++ /dev/null @@ -1,121 +0,0 @@ - - -module halfband_interp - (input clock, input reset, input enable, - input strobe_in, input strobe_out, - input [15:0] signal_in_i, input [15:0] signal_in_q, - output reg [15:0] signal_out_i, output reg [15:0] signal_out_q, - output wire [12:0] debug); - - wire [15:0] coeff_ram_out; - wire [15:0] data_ram_out_i; - wire [15:0] data_ram_out_q; - - wire [3:0] data_rd_addr; - reg [3:0] data_wr_addr; - reg [2:0] coeff_rd_addr; - - wire filt_done; - - wire [15:0] mac_out_i; - wire [15:0] mac_out_q; - reg [15:0] delayed_middle_i, delayed_middle_q; - wire [7:0] shift = 8'd9; - - reg stb_out_happened; - - wire [15:0] data_ram_out_i_b; - - always @(posedge clock) - if(strobe_in) - stb_out_happened <= #1 1'b0; - else if(strobe_out) - stb_out_happened <= #1 1'b1; - -assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr}; - - wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i; - wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q; - -/* always @(posedge clock) - if(reset) - begin - signal_out_i <= #1 16'd0; - signal_out_q <= #1 16'd0; - end - else if(strobe_in) - begin - signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff - signal_out_q <= #1 delayed_middle_q; - end - //else if(filt_done&stb_out_happened) - else if(stb_out_happened) - begin - signal_out_i <= #1 mac_out_i; - signal_out_q <= #1 mac_out_q; - end -*/ - - always @(posedge clock) - if(reset) - coeff_rd_addr <= #1 3'd0; - else if(coeff_rd_addr != 3'd0) - coeff_rd_addr <= #1 coeff_rd_addr + 3'd1; - else if(strobe_in) - coeff_rd_addr <= #1 3'd1; - - reg filt_done_d1; - always@(posedge clock) - filt_done_d1 <= #1 filt_done; - - always @(posedge clock) - if(reset) - data_wr_addr <= #1 4'd0; - //else if(strobe_in) - else if(filt_done & ~filt_done_d1) - data_wr_addr <= #1 data_wr_addr + 4'd1; - - always @(posedge clock) - if(coeff_rd_addr == 3'd7) - begin - delayed_middle_i <= #1 data_ram_out_i_b; - // delayed_middle_q <= #1 data_ram_out_q_b; - end - -// always @(posedge clock) -// if(reset) -// data_rd_addr <= #1 4'd0; -// else if(strobe_in) -// data_rd_addr <= #1 data_wr_addr + 4'd1; -// else if(!filt_done) -// data_rd_addr <= #1 data_rd_addr + 4'd1; -// else -// data_rd_addr <= #1 data_wr_addr; - - wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr}; - wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr}; -// always @(posedge clock) -// if(reset) -// filt_done <= #1 1'b1; -// else if(strobe_in) - // filt_done <= #1 1'b0; -// else if(coeff_rd_addr == 4'd0) -// filt_done <= #1 1'b1; - - assign filt_done = (coeff_rd_addr == 3'd0); - - coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) ); - - ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i), - .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i)); - - ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q), - .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q)); - - mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), - .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) ); - - mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), - .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) ); - -endmodule // halfband_interp diff --git a/sdr_lib/hb/hbd_tb/HBD b/sdr_lib/hb/hbd_tb/HBD deleted file mode 100644 index 574fbba91..000000000 --- a/sdr_lib/hb/hbd_tb/HBD +++ /dev/null @@ -1,80 +0,0 @@ -*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -test_hbd.clock -test_hbd.reset -@420 -test_hbd.halfband_decim.middle_data[15:0] -@22 -test_hbd.halfband_decim.sum_even[33:0] -test_hbd.halfband_decim.base_addr[3:0] -@420 -test_hbd.i_in[15:0] -@24 -test_hbd.halfband_decim.phase[3:0] -test_hbd.halfband_decim.ram16_even.rd_addr1[3:0] -test_hbd.halfband_decim.ram16_even.rd_addr2[3:0] -test_hbd.halfband_decim.ram16_even.wr_addr[3:0] -test_hbd.halfband_decim.ram16_even.wr_data[15:0] -@28 -test_hbd.halfband_decim.ram16_even.write -@420 -test_hbd.halfband_decim.sum[15:0] -test_hbd.halfband_decim.product[30:0] -test_hbd.halfband_decim.dout[33:0] -test_hbd.halfband_decim.sum_even[33:0] -@22 -test_hbd.halfband_decim.acc.addend[30:0] -@28 -test_hbd.halfband_decim.acc.reset -@420 -test_hbd.halfband_decim.acc.sum[33:0] -test_hbd.halfband_decim.mult.x[15:0] -test_hbd.halfband_decim.mult.y[15:0] -@28 -test_hbd.halfband_decim.acc.clear -test_hbd.strobe_in -test_hbd.strobe_out -test_hbd.halfband_decim.acc_en -@420 -test_hbd.i_out[15:0] -@28 -test_hbd.halfband_decim.mult_en -test_hbd.halfband_decim.latch_result -@420 -test_hbd.halfband_decim.sum[15:0] -test_hbd.halfband_decim.sum_even[33:0] -test_hbd.halfband_decim.dout[33:0] -test_hbd.halfband_decim.data_out[15:0] -@22 -test_hbd.halfband_decim.data_out[15:0] -@28 -test_hbd.halfband_decim.dout[33:0] -@29 -test_hbd.halfband_decim.acc_en -@22 -test_hbd.halfband_decim.base_addr[3:0] -@28 -test_hbd.halfband_decim.clear -test_hbd.halfband_decim.latch_result -test_hbd.halfband_decim.mult_en -test_hbd.halfband_decim.mult_en_pre -@22 -test_hbd.halfband_decim.phase[3:0] -@28 -test_hbd.halfband_decim.start -test_hbd.halfband_decim.start_d1 -test_hbd.halfband_decim.start_d2 -test_hbd.halfband_decim.start_d3 -test_hbd.halfband_decim.start_d4 -test_hbd.halfband_decim.start_d5 -test_hbd.halfband_decim.start_d6 -test_hbd.halfband_decim.start_d7 -test_hbd.halfband_decim.start_d8 -test_hbd.halfband_decim.start_d9 -test_hbd.halfband_decim.start_dA -test_hbd.halfband_decim.start_dB -test_hbd.halfband_decim.start_dC -test_hbd.halfband_decim.start_dD -test_hbd.halfband_decim.store_odd -test_hbd.halfband_decim.strobe_in -test_hbd.halfband_decim.strobe_out diff --git a/sdr_lib/hb/hbd_tb/really_golden b/sdr_lib/hb/hbd_tb/really_golden deleted file mode 100644 index 2d24a9e14..000000000 --- a/sdr_lib/hb/hbd_tb/really_golden +++ /dev/null @@ -1,142 +0,0 @@ -VCD info: dumpfile test_hbd.vcd opened for output. - x - x - x - x - x - x - x - x - x - x - x - x - x - x - x - x - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8192 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 -- 4 - 18 -- 63 - 167 -- 367 - 737 -- 1539 - 5146 - 5146 -- 1539 - 737 -- 367 - 167 -- 63 - 18 -- 4 - 0 - 0 - 0 - 0 - 0 -- 4 - 14 -- 49 - 118 -- 249 - 488 - 7141 -12287 -17433 -15894 -16631 -16264 -16432 -16368 -16387 -16383 -16383 -16383 -16383 -16383 -16387 -16368 -16432 -16264 -16631 -15894 - 9241 - 4095 -- 1051 - 488 -- 249 - 118 -- 49 - 14 -- 4 - 0 - 0 - 0 - 0 - 0 -- 4 - 14 -- 49 - 118 -- 249 - 488 -- 1051 -12287 -17433 -15894 -16631 -16264 -16432 -16368 -16387 -16383 -16383 -16383 -16383 -16383 -16387 -16368 -16432 -16264 -16631 -15894 -17433 - 4095 -- 1051 - 488 -- 249 - 118 -- 49 - 14 -- 4 - 0 - 0 - 0 - 0 diff --git a/sdr_lib/hb/hbd_tb/regression b/sdr_lib/hb/hbd_tb/regression deleted file mode 100644 index fc279c2f2..000000000 --- a/sdr_lib/hb/hbd_tb/regression +++ /dev/null @@ -1,95 +0,0 @@ -echo "Baseline 1000" -iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden -diff golden really_golden - -echo -echo "Test 100" -iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 50" -iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 40" -iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 30" -iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 25" -iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 20" -iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 19" -iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 18" -iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 17" -iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 16" -iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 15" -iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 14" -iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 13" -iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 12" -iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 11" -iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 10" -iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 9" -iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 8" -iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 7" -iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 6" -iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 5" -iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 4" -iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden - -echo -echo "Test 3" -iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden diff --git a/sdr_lib/hb/hbd_tb/run_hbd b/sdr_lib/hb/hbd_tb/run_hbd deleted file mode 100755 index b8aec7574..000000000 --- a/sdr_lib/hb/hbd_tb/run_hbd +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -iverilog -y .. -o test_hbd test_hbd.v -./test_hbd diff --git a/sdr_lib/hb/hbd_tb/test_hbd.v b/sdr_lib/hb/hbd_tb/test_hbd.v deleted file mode 100644 index 01ab5e7e0..000000000 --- a/sdr_lib/hb/hbd_tb/test_hbd.v +++ /dev/null @@ -1,75 +0,0 @@ - - -module test_hbd(); - - reg clock; - initial clock = 1'b0; - always #5 clock <= ~clock; - - reg reset; - initial reset = 1'b1; - initial #1000 reset = 1'b0; - - initial $dumpfile("test_hbd.vcd"); - initial $dumpvars(0,test_hbd); - - reg [15:0] i_in, q_in; - wire [15:0] i_out, q_out; - - reg strobe_in; - wire strobe_out; - reg coeff_write; - reg [15:0] coeff_data; - reg [4:0] coeff_addr; - - halfband_decim halfband_decim - ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), - .data_in(i_in),.data_out(i_out) ); - - always @(posedge strobe_out) - if(i_out[15]) - $display("-%d",65536-i_out); - else - $display("%d",i_out); - - initial - begin - strobe_in = 1'b0; - @(negedge reset); - @(posedge clock); - while(1) - begin - strobe_in <= #1 1'b1; - @(posedge clock); - strobe_in <= #1 1'b0; - repeat (`RATE) - @(posedge clock); - end - end - - initial #10000000 $finish; // Just in case... - - initial - begin - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd16384; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (41) @(posedge strobe_in); - i_in <= #1 16'd16384; - repeat (40) @(posedge strobe_in); - i_in <= #1 16'd0; - repeat (40) @(posedge strobe_in); - repeat (7) @(posedge clock); - $finish; - end // initial begin -endmodule // test_hb diff --git a/sdr_lib/hb/mac.v b/sdr_lib/hb/mac.v deleted file mode 100644 index 5a270bc73..000000000 --- a/sdr_lib/hb/mac.v +++ /dev/null @@ -1,58 +0,0 @@ - - -module mac (input clock, input reset, input enable, input clear, - input signed [15:0] x, input signed [15:0] y, - input [7:0] shift, output [15:0] z ); - - reg signed [30:0] product; - reg signed [39:0] z_int; - reg signed [15:0] z_shift; - - reg enable_d1; - always @(posedge clock) - enable_d1 <= #1 enable; - - always @(posedge clock) - if(reset | clear) - z_int <= #1 40'd0; - else if(enable_d1) - z_int <= #1 z_int + {{9{product[30]}},product}; - - always @(posedge clock) - product <= #1 x*y; - - always @* // FIXME full case? parallel case? - case(shift) - //8'd0 : z_shift <= z_int[39:24]; - //8'd1 : z_shift <= z_int[38:23]; - //8'd2 : z_shift <= z_int[37:22]; - //8'd3 : z_shift <= z_int[36:21]; - //8'd4 : z_shift <= z_int[35:20]; - //8'd5 : z_shift <= z_int[34:19]; - 8'd6 : z_shift <= z_int[33:18]; - 8'd7 : z_shift <= z_int[32:17]; - 8'd8 : z_shift <= z_int[31:16]; - 8'd9 : z_shift <= z_int[30:15]; - 8'd10 : z_shift <= z_int[29:14]; - 8'd11 : z_shift <= z_int[28:13]; - //8'd12 : z_shift <= z_int[27:12]; - //8'd13 : z_shift <= z_int[26:11]; - //8'd14 : z_shift <= z_int[25:10]; - //8'd15 : z_shift <= z_int[24:9]; - //8'd16 : z_shift <= z_int[23:8]; - //8'd17 : z_shift <= z_int[22:7]; - //8'd18 : z_shift <= z_int[21:6]; - //8'd19 : z_shift <= z_int[20:5]; - //8'd20 : z_shift <= z_int[19:4]; - //8'd21 : z_shift <= z_int[18:3]; - //8'd22 : z_shift <= z_int[17:2]; - //8'd23 : z_shift <= z_int[16:1]; - //8'd24 : z_shift <= z_int[15:0]; - default : z_shift <= z_int[15:0]; - endcase // case(shift) - - // FIXME do we need to saturate? - //assign z = z_shift; - assign z = z_int[15:0]; - -endmodule // mac diff --git a/sdr_lib/hb/mult.v b/sdr_lib/hb/mult.v deleted file mode 100644 index a8d4cb1b7..000000000 --- a/sdr_lib/hb/mult.v +++ /dev/null @@ -1,16 +0,0 @@ - - -module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, - input enable_in, output reg enable_out ); - - always @(posedge clock) - if(enable_in) - product <= #1 x*y; - else - product <= #1 31'd0; - - always @(posedge clock) - enable_out <= #1 enable_in; - -endmodule // mult - diff --git a/sdr_lib/hb/ram16_2port.v b/sdr_lib/hb/ram16_2port.v deleted file mode 100644 index e1761a926..000000000 --- a/sdr_lib/hb/ram16_2port.v +++ /dev/null @@ -1,22 +0,0 @@ - - -module ram16_2port (input clock, input write, - input [3:0] wr_addr, input [15:0] wr_data, - input [3:0] rd_addr1, output reg [15:0] rd_data1, - input [3:0] rd_addr2, output reg [15:0] rd_data2); - - reg [15:0] ram_array [0:31]; - - always @(posedge clock) - rd_data1 <= #1 ram_array[rd_addr1]; - - always @(posedge clock) - rd_data2 <= #1 ram_array[rd_addr2]; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - -endmodule // ram16_2port - - diff --git a/sdr_lib/hb/ram16_2sum.v b/sdr_lib/hb/ram16_2sum.v deleted file mode 100644 index 559b06fd5..000000000 --- a/sdr_lib/hb/ram16_2sum.v +++ /dev/null @@ -1,27 +0,0 @@ - - -module ram16_2sum (input clock, input write, - input [3:0] wr_addr, input [15:0] wr_data, - input [3:0] rd_addr1, input [3:0] rd_addr2, - output reg [15:0] sum); - - reg signed [15:0] ram_array [0:15]; - reg signed [15:0] a,b; - wire signed [16:0] sum_int; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - - always @(posedge clock) - begin - a <= #1 ram_array[rd_addr1]; - b <= #1 ram_array[rd_addr2]; - end - - assign sum_int = {a[15],a} + {b[15],b}; - - always @(posedge clock) - sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); - -endmodule // ram16_2sum diff --git a/sdr_lib/hb/ram32_2sum.v b/sdr_lib/hb/ram32_2sum.v deleted file mode 100644 index d1f55b7d0..000000000 --- a/sdr_lib/hb/ram32_2sum.v +++ /dev/null @@ -1,22 +0,0 @@ - - -module ram32_2sum (input clock, input write, - input [4:0] wr_addr, input [15:0] wr_data, - input [4:0] rd_addr1, input [4:0] rd_addr2, - output reg [15:0] sum); - - reg [15:0] ram_array [0:31]; - wire [16:0] sum_int; - - always @(posedge clock) - if(write) - ram_array[wr_addr] <= #1 wr_data; - - assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; - - always @(posedge clock) - sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); - - -endmodule // ram32_2sum - diff --git a/sdr_lib/hb_dec.v b/sdr_lib/hb_dec.v deleted file mode 100644 index 8fb5ba222..000000000 --- a/sdr_lib/hb_dec.v +++ /dev/null @@ -1,171 +0,0 @@ -// Final halfband decimator -// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] -// Strobe in cannot come faster than every 2nd clock cycle -// These taps designed by halfgen4 from ldoolittle -// myfilt = round(2^18 * halfgen4(.7/4,8)) - -module hb_dec - #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=24) - (input clk, - input rst, - input bypass, - input run, - input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block - input stb_in, - input [IWIDTH-1:0] data_in, - output reg stb_out, - output reg [OWIDTH-1:0] data_out); - - // Control - reg [3:0] addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d; - wire write_odd, write_even, do_mult; - reg odd; - reg [2:0] phase, phase_d1; - reg stb_out_int; - wire clear, do_acc; - assign do_mult = 1; - - always @(posedge clk) - if(rst | ~run) - odd <= 0; - else if(stb_in) - odd <= ~odd; - - assign write_odd = stb_in & odd; - assign write_even = stb_in & ~odd; - - always @(posedge clk) - if(rst | ~run) - phase <= 0; - else if(stb_in & odd) - phase <= 1; - else if(phase == 4) - phase <= 0; - else if(phase != 0) - phase <= phase + 1; - - always @(posedge clk) - phase_d1 <= phase; - - reg [15:0] stb_out_pre; - always @(posedge clk) - if(rst) - stb_out_pre <= 0; - else - stb_out_pre <= {stb_out_pre[14:0],(stb_in & odd)}; - - always @* - case(phase) - 1 : begin addr_odd_a = 0; addr_odd_b = 15; end - 2 : begin addr_odd_a = 1; addr_odd_b = 14; end - 3 : begin addr_odd_a = 2; addr_odd_b = 13; end - 4 : begin addr_odd_a = 3; addr_odd_b = 12; end - default : begin addr_odd_a = 0; addr_odd_b = 15; end - endcase // case(phase) - - always @* - case(phase) - 1 : begin addr_odd_c = 4; addr_odd_d = 11; end - 2 : begin addr_odd_c = 5; addr_odd_d = 10; end - 3 : begin addr_odd_c = 6; addr_odd_d = 9; end - 4 : begin addr_odd_c = 7; addr_odd_d = 8; end - default : begin addr_odd_c = 4; addr_odd_d = 11; end - endcase // case(phase) - - assign do_acc = |stb_out_pre[6:3]; - assign clear = stb_out_pre[3]; - - // Data - wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d; - wire [IWIDTH-1:0] sum1, sum2; - wire [OWIDTH-1:0] final_sum; - reg [CWIDTH-1:0] coeff1, coeff2; - wire [35:0] prod1, prod2; - - always @* // Outer coeffs - case(phase_d1) - 1 : coeff1 = -107; - 2 : coeff1 = 445; - 3 : coeff1 = -1271; - 4 : coeff1 = 2959; - default : coeff1 = -107; - endcase // case(phase) - - always @* // Inner coeffs - case(phase_d1) - 1 : coeff2 = -6107; - 2 : coeff2 = 11953; - 3 : coeff2 = -24706; - 4 : coeff2 = 82359; - default : coeff2 = -6107; - endcase // case(phase) - - srl #(.WIDTH(IWIDTH)) srl_odd_a - (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_a),.out(data_odd_a)); - srl #(.WIDTH(IWIDTH)) srl_odd_b - (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_b),.out(data_odd_b)); - srl #(.WIDTH(IWIDTH)) srl_odd_c - (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_c),.out(data_odd_c)); - srl #(.WIDTH(IWIDTH)) srl_odd_d - (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d)); - - add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1)); - add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2)); - - wire [IWIDTH-1:0] data_even; - reg [3:0] addr_even; - - always @(posedge clk) - case(cpi) - // 1 is an error - 2 : addr_even <= 9; // Maximum speed (overall decim by 4) - 3, 4, 5, 6, 7 : addr_even <= 8; - default : addr_even <= 7; - endcase // case(cpi) - - srl #(.WIDTH(IWIDTH)) srl_even - (.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even)); - - localparam MWIDTH = ACCWIDTH-2; - wire [MWIDTH-1:0] sum_of_prod; - - MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); - MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); - add2_and_round_reg #(.WIDTH(MWIDTH)) - add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod)); - - wire [ACCWIDTH-1:0] acc_out; - - acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) - acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out)); - - localparam SHIFT_FACTOR = ACCWIDTH-IWIDTH-5; - wire [ACCWIDTH-1:0] data_even_signext; - wire [ACCWIDTH:0] final_sum_unrounded; - - sign_extend #(.bits_in(IWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) - signext_data_even (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR])); - assign data_even_signext[SHIFT_FACTOR-1:0] = 0; - - add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1)) - final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded)); - - round_reg #(.bits_in(ACCWIDTH-4),.bits_out(OWIDTH)) - final_round (.clk(clk),.in(final_sum_unrounded[ACCWIDTH-5:0]),.out(final_sum)); - - // Output - always @(posedge clk) - if(bypass) - data_out <= data_in; - else if(stb_out_pre[9]) - data_out <= final_sum; - - always @(posedge clk) - if(rst) - stb_out <= 0; - else if(bypass) - stb_out <= stb_in; - else - stb_out <= stb_out_pre[9]; - -endmodule // hb_dec diff --git a/sdr_lib/hb_dec_tb.v b/sdr_lib/hb_dec_tb.v deleted file mode 100644 index 3e5faa80a..000000000 --- a/sdr_lib/hb_dec_tb.v +++ /dev/null @@ -1,140 +0,0 @@ -module hb_dec_tb( ) ; - - // Parameters for instantiation - parameter clocks = 9'd2 ; // Number of clocks per input - parameter decim = 1 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - reg strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - initial - begin - $dumpfile("hb_dec_tb.vcd"); - $dumpvars(0,hb_dec_tb); - end - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #1000 reset = 1'b0 ; - - // Enable the entire system - initial enable = 1'b1 ; - - // Instantiate UUT - /* - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - */ - - - hb_dec #(.IWIDTH(18),.OWIDTH(18),.CWIDTH(18),.ACCWIDTH(24)) uut - (.clk(clock),.rst(reset),.bypass(0),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in), - .stb_out(strobe_out),.data_out(data_out) ); - - integer i, ri, ro, infile, outfile ; - - always @(posedge clock) - begin - if(strobe_out) - $display(data_out); - end - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - strobe_in <= 1'd0 ; - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( posedge clock ) begin - //#1 ; - strobe_in <= 1'b1 ; - if( !$feof(infile) ) - ri = $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - - // Clocked in - set the strobe to 0 if the number of - // clocks per sample is greater than 1 - if( clocks > 1 ) begin - @(posedge clock) begin - strobe_in <= 1'b0 ; - end - - // Wait for the specified number of cycles - for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin - @(posedge clock) #1 ; - end - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $finish ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - //$display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - endofsim <= 1'b1 ; - end - end - end - -endmodule // hb_dec_tb - diff --git a/sdr_lib/hb_interp.v b/sdr_lib/hb_interp.v deleted file mode 100644 index d16807e15..000000000 --- a/sdr_lib/hb_interp.v +++ /dev/null @@ -1,157 +0,0 @@ -// First halfband iterpolator -// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] -// Strobe in cannot come faster than every 4th clock cycle, -// Strobe out cannot come faster than every 2nd clock cycle - -// These taps designed by halfgen4 from ldoolittle -// myfilt = round(2^18 * halfgen4(.7/4,8)) - -module hb_interp - #(parameter IWIDTH=18, OWIDTH=18, ACCWIDTH=24) - (input clk, - input rst, - input bypass, - input [7:0] cpo, // Clocks per output, must be at least 2 - input stb_in, - input [IWIDTH-1:0] data_in, - input stb_out, - output reg [OWIDTH-1:0] data_out); - - localparam MWIDTH = ACCWIDTH-2; - localparam CWIDTH = 18; - - reg [CWIDTH-1:0] coeff1, coeff2; - reg [3:0] addr_a, addr_b, addr_c, addr_d, addr_e; - wire [IWIDTH-1:0] data_a, data_b, data_c, data_d, data_e, sum1, sum2; - wire [35:0] prod1, prod2; - - reg [2:0] phase, phase_d1, phase_d2, phase_d3, phase_d4, phase_d5; - - always @(posedge clk) - if(rst) - phase <= 0; - else - if(stb_in) - phase <= 1; - else if(phase==4) - phase <= 0; - else if(phase!=0) - phase <= phase + 1; - always @(posedge clk) phase_d1 <= phase; - always @(posedge clk) phase_d2 <= phase_d1; - always @(posedge clk) phase_d3 <= phase_d2; - always @(posedge clk) phase_d4 <= phase_d3; - always @(posedge clk) phase_d5 <= phase_d4; - - srl #(.WIDTH(IWIDTH)) srl_a - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_a),.out(data_a)); - srl #(.WIDTH(IWIDTH)) srl_b - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_b),.out(data_b)); - srl #(.WIDTH(IWIDTH)) srl_c - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_c),.out(data_c)); - srl #(.WIDTH(IWIDTH)) srl_d - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_d),.out(data_d)); - srl #(.WIDTH(IWIDTH)) srl_e - (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_e),.out(data_e)); - - always @* - case(phase) - 1 : begin addr_a = 0; addr_b = 15; end - 2 : begin addr_a = 1; addr_b = 14; end - 3 : begin addr_a = 2; addr_b = 13; end - 4 : begin addr_a = 3; addr_b = 12; end - default : begin addr_a = 0; addr_b = 15; end - endcase // case(phase) - - always @* - case(phase) - 1 : begin addr_c = 4; addr_d = 11; end - 2 : begin addr_c = 5; addr_d = 10; end - 3 : begin addr_c = 6; addr_d = 9; end - 4 : begin addr_c = 7; addr_d = 8; end - default : begin addr_c = 4; addr_d = 11; end - endcase // case(phase) - - always @* - case(cpo) - 2 : addr_e <= 9; - 3,4,5,6,7,8 : addr_e <= 8; - default : addr_e <= 7; // This case works for 256, which = 0 due to overflow outside this block - endcase // case(cpo) - - always @* // Outer coeffs - case(phase_d1) - 1 : coeff1 = -107; - 2 : coeff1 = 445; - 3 : coeff1 = -1271; - 4 : coeff1 = 2959; - default : coeff1 = -107; - endcase // case(phase) - - always @* // Inner coeffs - case(phase_d1) - 1 : coeff2 = -6107; - 2 : coeff2 = 11953; - 3 : coeff2 = -24706; - 4 : coeff2 = 82359; - default : coeff2 = -6107; - endcase // case(phase) - - add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_a),.in2(data_b),.sum(sum1)); - add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_c),.in2(data_d),.sum(sum2)); - // sum1, sum2 available on phase_d1 - - wire do_mult = 1; - MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); - MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); - // prod1, prod2 available on phase_d2 - - wire [MWIDTH-1:0] sum_of_prod; - - add2_and_round_reg #(.WIDTH(MWIDTH)) - add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod)); - // sum_of_prod available on phase_d3 - - wire [ACCWIDTH-1:0] acc_out; - wire [OWIDTH-1:0] acc_round; - - wire clear = (phase_d3 == 1); - wire do_acc = (phase_d3 != 0); - - acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) - acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out)); - // acc_out available on phase_d4 - - wire [ACCWIDTH-6:0] clipped_acc; - clip #(.bits_in(ACCWIDTH),.bits_out(ACCWIDTH-5)) final_clip(.in(acc_out),.out(clipped_acc)); - - reg [ACCWIDTH-6:0] clipped_reg; - always @(posedge clk) - if(phase_d4 == 4) - clipped_reg <= clipped_acc; - // clipped_reg available on phase_d5 - - wire [OWIDTH-1:0] data_out_round; - round #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH)) final_round (.in(clipped_reg),.out(data_out_round)); - - reg odd; - always @(posedge clk) - if(rst) - odd <= 0; - else if(stb_in) - odd <= 0; - else if(stb_out) - odd <= 1; - - always @(posedge clk) - if(bypass) - data_out <= data_in; - else if(stb_out) - if(odd) - data_out <= data_e; - else - data_out <= data_out_round; - - // data_out available on phase_d6 - -endmodule // hb_interp diff --git a/sdr_lib/hb_interp_tb.v b/sdr_lib/hb_interp_tb.v deleted file mode 100644 index 52f137f28..000000000 --- a/sdr_lib/hb_interp_tb.v +++ /dev/null @@ -1,132 +0,0 @@ -module hb_interp_tb( ) ; - - // Parameters for instantiation - parameter clocks = 8'd2 ; // Number of clocks per output - parameter decim = 1 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - wire strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - initial - begin - $dumpfile("hb_interp_tb.vcd"); - $dumpvars(0,hb_interp_tb); - end - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #1000 reset = 1'b0 ; - - always @(posedge clock) - enable <= ~reset; - - // Instantiate UUT - /* - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - */ - - cic_strober #(.WIDTH(8)) - out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks), - .strobe_fast(1),.strobe_slow(strobe_out) ); - - cic_strober #(.WIDTH(8)) - in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2), - .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); - - hb_interp #() uut - (.clk(clock),.rst(reset),.bypass(0),.cpo(clocks),.stb_in(strobe_in),.data_in(data_in), - .stb_out(strobe_out),/* .output_rate(clocks), */ .data_out(data_out) ); - - integer i, ri, ro, infile, outfile ; - - always @(posedge clock) - begin - if(strobe_out) - $display(data_out); - end - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( negedge clock ) begin - if(strobe_in) - if( !$feof(infile) ) - ri <= #1 $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $finish ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - //$display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - if($feof(infile)) - endofsim <= 1'b1 ; - end - end - end - -endmodule // small_hb_int_tb diff --git a/sdr_lib/hb_tb.v b/sdr_lib/hb_tb.v deleted file mode 100644 index 7e960fd13..000000000 --- a/sdr_lib/hb_tb.v +++ /dev/null @@ -1,155 +0,0 @@ - -module hb_tb(); - - localparam SWIDTH = 17; - localparam CWIDTH = 18; - localparam TWIDTH = 20; - localparam ACC_WIDTH = 40; - - reg clk = 0, rst = 1; - wire strobe_in, strobe_out; - reg [SWIDTH-1:0] sample_in; - wire signed [SWIDTH:0] sample_out; - - reg set_stb; - reg [7:0] set_addr; - reg [31:0] set_data; - - localparam DECIM = 3; - - initial $dumpfile("hb_tb.vcd"); - initial $dumpvars(0,hb_tb); - - always #5 clk <= ~clk; - initial - begin - @(posedge clk); - @(negedge clk); - rst <= 0; - end - - reg [7:0] stb_counter; - always @(posedge clk) - if(rst) - stb_counter <= 0; - else - if(stb_counter == 0) - stb_counter <= DECIM; - else - stb_counter <= stb_counter - 1; - assign strobe_in = (stb_counter == 0); - - hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH), - .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim - (.clk(clk), .rst(rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .sample_in(sample_in), - .strobe_in(strobe_in), - .sample_out(sample_out), - .strobe_out(strobe_out) - ); - - initial - begin : load_coeffs - @(negedge rst); - @(posedge clk); - set_addr <= 124; // load coeffs - set_stb <= 1; - set_data <= -18'd49; - @(posedge clk); - set_data <= 18'd165; - @(posedge clk); - set_data <= -18'd412; - @(posedge clk); - set_data <= 18'd873; - @(posedge clk); - set_data <= -18'd1681; - @(posedge clk); - set_data <= 18'd3135; - @(posedge clk); - set_data <= -18'd6282; - @(posedge clk); - set_data <= 18'd20628; - @(posedge clk); - set_addr <=125; // load table - // { stb_out, accum, load_accum, done, even_addr, odd_addr_a, odd_addr_b, coeff_addr } - set_data <= {1'b1,1'b1,1'b0,1'b1,4'd15,4'd15,4'd0,4'd0}; // Phase 8 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd14,4'd1,4'd1}; // Phase 7 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd13,4'd2,4'd2}; // Phase 6 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd12,4'd3,4'd3}; // Phase 5 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd11,4'd4,4'd4}; // Phase 4 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd10,4'd5,4'd5}; // Phase 3 - @(posedge clk); - set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd9,4'd6,4'd6}; // Phase 2 - @(posedge clk); - set_data <= {1'b0,1'b0,1'b1,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 1 - @(posedge clk); - set_data <= {1'b0,1'b0,1'b0,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 0 - @(posedge clk); - set_stb <= 0; - end // block: load_coeffs - - initial - begin - sample_in <= 0; - repeat(40) - @(posedge strobe_in); - $display("EVEN"); - sample_in <= 0; - repeat(10) - @(posedge strobe_in); - sample_in <= 1; - @(posedge strobe_in); - sample_in <= 0; - repeat(40) - @(posedge strobe_in); - sample_in <= 1; - repeat(40) - @(posedge strobe_in); - sample_in <= 0; - repeat(60) - @(posedge strobe_in); - sample_in <= 1; - repeat(2) - @(posedge strobe_in); - sample_in <= 0; - repeat(60) - @(posedge strobe_in); - $display("ODD"); - sample_in <= 0; - repeat(10) - @(posedge strobe_in); - sample_in <= 1; - @(posedge strobe_in); - sample_in <= 0; - repeat(40) - @(posedge strobe_in); - sample_in <= 1; - repeat(40) - @(posedge strobe_in); - sample_in <= 0; - repeat(60) - @(posedge strobe_in); - sample_in <= 1; - repeat(2) - @(posedge strobe_in); - sample_in <= 0; - repeat(60) - @(posedge strobe_in); - $finish; - end - - always @(posedge clk) - if(strobe_in) - $display(sample_in); - - always @(posedge clk) - if(strobe_out) - $display("\t",sample_out); - -endmodule // hb_tb diff --git a/sdr_lib/input.dat b/sdr_lib/input.dat deleted file mode 100644 index 1e649ac2e..000000000 --- a/sdr_lib/input.dat +++ /dev/null @@ -1,341 +0,0 @@ -0 -0 -0 -0 -0 -0 -0 -0 --131072 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -131071 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -100000 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 --131072 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 --131072 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 diff --git a/sdr_lib/integrate.v b/sdr_lib/integrate.v deleted file mode 100644 index db33de979..000000000 --- a/sdr_lib/integrate.v +++ /dev/null @@ -1,38 +0,0 @@ -module integrate - #(parameter INPUTW = 16, - parameter ACCUMW = 32, - parameter OUTPUTW = 16) - - (input clk_i, - input rst_i, - input ena_i, - - input dump_i, - input [INPUTW-1:0] data_i, - - output reg stb_o, - output reg [OUTPUTW-1:0] integ_o - ); - - wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i}; - reg [ACCUMW-1:0] accum; - - always @(posedge clk_i) - if (rst_i | ~ena_i) - begin - accum <= 0; - integ_o <= 0; - end - else - if (dump_i) - begin - integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW]; - accum <= data_ext; - end - else - accum <= accum + data_ext; - - always @(posedge clk_i) - stb_o <= dump_i; - -endmodule // integrate diff --git a/sdr_lib/med_hb_int.v b/sdr_lib/med_hb_int.v deleted file mode 100644 index bc8066509..000000000 --- a/sdr_lib/med_hb_int.v +++ /dev/null @@ -1,95 +0,0 @@ -// Medium halfband decimator (intended to be followed by another stage) -// Implements impulse responses of the form [A 0 B 0 C 0 D 0.5 D 0 C 0 B 0 A] -// -// These taps designed by halfgen_test: -// 2 * 131072 * halfgen_test(.8/8,4,1) -// -597, 0, 4283, 0, -17516, 0, 79365, 131072, 79365, 0, -17516, 0, 4283, 0, -597 - - -module med_hb_int - #(parameter WIDTH=18) - (input clk, - input rst, - input bypass, - input stb_in, - input [WIDTH-1:0] data_in, - input [7:0] output_rate, - input stb_out, - output reg [WIDTH-1:0] data_out); - - localparam coeff_a = -597; - localparam coeff_b = 4283; - localparam coeff_c = -17516; - localparam coeff_d = 79365; - - reg phase; - reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6, d7, d8; - - localparam MWIDTH = 36; - wire [MWIDTH-1:0] prod; - - reg [6:0] stbin_d; - - always @(posedge clk) - stbin_d <= {stbin_d[5:0],stb_in}; - - always @(posedge clk) - if(stb_in) - begin - d1 <= data_in; - d2 <= d1; - d3 <= d2; - d4 <= d3; - d5 <= d4; - d6 <= d5; - d7 <= d6; - d8 <= d7; - end - - wire [WIDTH-1:0] sum_a, sum_b, sum_c, sum_d; - add2_and_round_reg #(.WIDTH(WIDTH)) add_a (.clk(clk),.in1(d1),.in2(d8),.sum(sum_a)); - add2_and_round_reg #(.WIDTH(WIDTH)) add_b (.clk(clk),.in1(d2),.in2(d7),.sum(sum_b)); - add2_and_round_reg #(.WIDTH(WIDTH)) add_c (.clk(clk),.in1(d3),.in2(d6),.sum(sum_c)); - add2_and_round_reg #(.WIDTH(WIDTH)) add_d (.clk(clk),.in1(d4),.in2(d5),.sum(sum_d)); - - MULT18X18S mult1(.C(clk), .CE(1), .R(rst), .P(prod1), .A(stbin_d[1] ? coeff_a : coeff_b), - .B(stbin_d[1] ? sum_a : sum_b) ); - MULT18X18S mult2(.C(clk), .CE(1), .R(rst), .P(prod2), .A(stbin_d[1] ? coeff_c : coeff_d), - .B(stbin_d[1] ? sum_c : sum_d) ); - - wire [MWIDTH:0] accum; - acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) - acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum)); - - wire [WIDTH+2:0] accum_rnd; - round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3)) - final_round (.clk(clk),.in(accum),.out(accum_rnd)); - - wire [WIDTH-1:0] clipped; - clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) - final_clip (.clk(clk),.in(accum_rnd),.out(clipped)); - - reg [WIDTH-1:0] saved, saved_d3; - always @(posedge clk) - if(stbin_d[6]) - saved <= clipped; - - always @(posedge clk) - if(stbin_d[3]) - saved_d3 <= d3; - - always @(posedge clk) - if(bypass) - data_out <= data_in; - else if(stb_in & stb_out) - case(output_rate) - 1 : data_out <= d6; - 2 : data_out <= d4; - 3, 4, 5, 6, 7 : data_out <= d3; - default : data_out <= d2; - endcase // case(output_rate) - else if(stb_out) - data_out <= saved; - -endmodule // small_hb_int - diff --git a/sdr_lib/output.dat b/sdr_lib/output.dat deleted file mode 100644 index 15db3ced4..000000000 --- a/sdr_lib/output.dat +++ /dev/null @@ -1,130 +0,0 @@ --1390 -0 -1604 -0 --1896 -0 -2317 -0 --2979 -0 -4172 -0 --6953 -0 -20860 -32768 -20860 -0 --6953 -0 -4172 -0 --2979 -0 -2317 -0 --1896 -0 -1604 -0 --1390 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 - diff --git a/sdr_lib/round.v b/sdr_lib/round.v deleted file mode 100644 index c4f9ec9cd..000000000 --- a/sdr_lib/round.v +++ /dev/null @@ -1,33 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Rounding "macro" -// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation) - -module round - #(parameter bits_in=0, - parameter bits_out=0) - (input [bits_in-1:0] in, - output [bits_out-1:0] out); - - assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]); - -endmodule // round diff --git a/sdr_lib/round_reg.v b/sdr_lib/round_reg.v deleted file mode 100644 index aa0972dab..000000000 --- a/sdr_lib/round_reg.v +++ /dev/null @@ -1,39 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Rounding "macro" -// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero) - -module round_reg - #(parameter bits_in=0, - parameter bits_out=0) - (input clk, - input [bits_in-1:0] in, - output reg [bits_out-1:0] out); - - wire [bits_out-1:0] temp; - - round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp)); - - always @(posedge clk) - out <= temp; - -endmodule // round diff --git a/sdr_lib/rssi.v b/sdr_lib/rssi.v deleted file mode 100644 index e45e2148c..000000000 --- a/sdr_lib/rssi.v +++ /dev/null @@ -1,30 +0,0 @@ - - -module rssi (input clock, input reset, input enable, - input [11:0] adc, output [15:0] rssi, output [15:0] over_count); - - wire over_hi = (adc == 12'h7FF); - wire over_lo = (adc == 12'h800); - wire over = over_hi | over_lo; - - reg [25:0] over_count_int; - always @(posedge clock) - if(reset | ~enable) - over_count_int <= #1 26'd0; - else - over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10]; - - assign over_count = over_count_int[25:10]; - - wire [11:0] abs_adc = adc[11] ? ~adc : adc; - - reg [25:0] rssi_int; - always @(posedge clock) - if(reset | ~enable) - rssi_int <= #1 26'd0; - else - rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10]; - - assign rssi = rssi_int[25:10]; - -endmodule // rssi diff --git a/sdr_lib/rx_control.v b/sdr_lib/rx_control.v deleted file mode 100644 index 0adeb0794..000000000 --- a/sdr_lib/rx_control.v +++ /dev/null @@ -1,180 +0,0 @@ - -`define DSP_CORE_RX_BASE 160 - -module rx_control - #(parameter FIFOSIZE = 10) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [31:0] master_time, - output overrun, - - // To FIFO interface of Buffer Pool - output [31:0] wr_dat_o, - output [3:0] wr_flags_o, - input wr_ready_i, - output wr_ready_o, - - // From DSP Core - input [31:0] sample, - output run, - input strobe, - - // FIFO Levels - output [15:0] fifo_occupied, - output fifo_full, - output fifo_empty, - - // Debug - output [31:0] debug_rx - ); - - wire [31:0] new_time, new_command; - wire sc_pre1, clear_overrun; - wire [31:0] rcvtime_pre; - reg [31:0] rcvtime; - wire [8:0] lines_per_frame; - wire [20:0] numlines; - wire send_imm_pre, chain_pre; - reg send_imm, chain; - wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl; - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(new_time),.changed(sc_pre1)); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+4)) sr_4 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(new_command),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+5)) sr_5 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_overrun)); - - reg sc_pre2; - always @(posedge clk) - sc_pre2 <= sc_pre1; - assign write_ctrl = sc_pre1 & ~sc_pre2; - - shortfifo #(.WIDTH(64)) commandfifo - (.clk(clk),.rst(rst),.clear(clear_overrun), - .datain({new_command,new_time}), .write(write_ctrl), .full(full_ctrl), - .dataout({send_imm_pre,chain_pre,numlines,lines_per_frame,rcvtime_pre}), - .read(read_ctrl), .empty(empty_ctrl) ); - - // Buffer interface to internal FIFO - wire have_space, write; - wire [35:0] fifo_line; - - // Internal FIFO, size 9 is 2K, size 10 is 4K - fifo_cascade #(.WIDTH(36),.SIZE(FIFOSIZE)) rxfifo - (.clk(clk),.reset(rst),.clear(clear_overrun), - .datain(fifo_line), .src_rdy_i(write), .dst_rdy_o(have_space), - .dataout({wr_flags_o,wr_dat_o}), .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), - .space(),.occupied(fifo_occupied) ); - assign fifo_full = ~have_space; - assign fifo_empty = ~wr_ready_o; - - // Internal FIFO to DSP interface - reg [22:0] lines_left; - reg [8:0] lines_left_frame; - localparam IBS_IDLE = 0; - localparam IBS_WAITING = 1; - localparam IBS_FIRSTLINE = 2; - localparam IBS_RUNNING = 3; - localparam IBS_OVERRUN = 4; - - reg [2:0] ibs_state; - - wire [32:0] delta_time = {1'b0,rcvtime}-{1'b0,master_time}; - wire too_late = (delta_time[32:31] == 2'b11) & ~send_imm; - wire go_now = send_imm | ( master_time == rcvtime ); - - always @(posedge clk) - if(rst) - begin - ibs_state <= IBS_IDLE; - lines_left <= 0; - lines_left_frame <= 0; - rcvtime <= 0; - send_imm <= 0; - chain <= 0; - end - else - if(clear_overrun) - begin - ibs_state <= IBS_IDLE; - lines_left <= 0; - lines_left_frame <= 0; - rcvtime <= 0; - send_imm <= 0; - chain <= 0; - end - else - case(ibs_state) - IBS_IDLE : - if(~empty_ctrl) - begin - lines_left <= numlines; - lines_left_frame <= lines_per_frame; - rcvtime <= rcvtime_pre; - ibs_state <= IBS_WAITING; - send_imm <= send_imm_pre; - chain <= chain_pre; - end - IBS_WAITING : - if(go_now) - ibs_state <= IBS_FIRSTLINE; - else if(too_late) - ibs_state <= IBS_OVERRUN; - IBS_FIRSTLINE : - if(~have_space | strobe) - ibs_state <= IBS_OVERRUN; - else - ibs_state <= IBS_RUNNING; - IBS_RUNNING : - if(strobe) - if(~have_space) - ibs_state <= IBS_OVERRUN; - else - begin - lines_left <= lines_left - 1; - if(lines_left == 1) - if(~chain) - ibs_state <= IBS_IDLE; - else if(empty_ctrl) - ibs_state <= IBS_OVERRUN; - else - begin - lines_left <= numlines; - lines_left_frame <= lines_per_frame; - rcvtime <= rcvtime_pre; - ibs_state <= IBS_FIRSTLINE; - send_imm <= send_imm_pre; - chain <= chain_pre; - end - else if(lines_left_frame == 1) - begin - lines_left_frame <= lines_per_frame; - ibs_state <= IBS_FIRSTLINE; - end - else - lines_left_frame <= lines_left_frame - 1; - end // else: !if(~have_space) - endcase // case(ibs_state) - - assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {2'b0,1'b0,1'b1,master_time} : - {2'b0,((lines_left==1)|(lines_left_frame==1)),1'b0,sample}; - - assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & have_space; // & (ibs_state == IBS_RUNNING) should strobe only when running - assign overrun = (ibs_state == IBS_OVERRUN); - assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE); - assign read_ctrl = ( (ibs_state == IBS_IDLE) | - ((ibs_state == IBS_RUNNING) & strobe & have_space & (lines_left==1) & chain) ) - & ~empty_ctrl; - - assign debug_rx = { 8'd0, - 1'd0, send_imm, chain, wr_ready_i,wr_ready_o, 2'b0, run, - write,have_space,wr_flags_o[1:0],write_ctrl,full_ctrl,read_ctrl,empty_ctrl, - sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] }; -endmodule // rx_control diff --git a/sdr_lib/rx_dcoffset.v b/sdr_lib/rx_dcoffset.v deleted file mode 100644 index bedbd40e6..000000000 --- a/sdr_lib/rx_dcoffset.v +++ /dev/null @@ -1,43 +0,0 @@ - - -module rx_dcoffset - #(parameter WIDTH=14, - parameter ADDR=8'd0) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out); - - // Because of some extra delays to make timing easier, the transfer function is: - // (z-1)/(z^2-z-alpha) where alpha is 1/2^n - - wire set_now = set_stb & (ADDR == set_addr); - - reg fixed; // uses fixed offset - wire signed [WIDTH-1:0] fixed_dco; - reg signed [31:0] integrator; - - always @(posedge clk) - if(rst) - begin - fixed <= 0; - integrator <= 32'd0; - end - else if(set_now) - begin - integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}}; - fixed <= set_data[31]; - end - else if(~fixed) - integrator <= integrator + adc_out; - - wire [WIDTH:0] scaled_integrator; - - round #(.bits_in(33),.bits_out(15)) round (.in({integrator[31],integrator}),.out(scaled_integrator)); - - wire [WIDTH:0] adc_out_int = {adc_in[WIDTH-1],adc_in} - scaled_integrator; - - clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc - (.clk(clk),.in(adc_out_int),.out(adc_out)); - - -endmodule // rx_dcoffset diff --git a/sdr_lib/rx_dcoffset_tb.v b/sdr_lib/rx_dcoffset_tb.v deleted file mode 100644 index a8b4ec20f..000000000 --- a/sdr_lib/rx_dcoffset_tb.v +++ /dev/null @@ -1,25 +0,0 @@ - -`timescale 1ns/1ns -module rx_dcoffset_tb(); - - reg clk, rst; - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #5 clk = ~clk; - - initial $dumpfile("rx_dcoffset_tb.vcd"); - initial $dumpvars(0,rx_dcoffset_tb); - - reg [13:0] adc_in = 7; - wire [13:0] adc_out; - - always @(posedge clk) - $display("%d\t%d",adc_in,adc_out); - - rx_dcoffset #(.WIDTH(14),.ADDR(0)) - rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0), - .adc_in(adc_in),.adc_out(adc_out)); - -endmodule // longfifo_tb diff --git a/sdr_lib/sign_extend.v b/sdr_lib/sign_extend.v deleted file mode 100644 index eae67faf2..000000000 --- a/sdr_lib/sign_extend.v +++ /dev/null @@ -1,35 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// Sign extension "macro" -// bits_out should be greater than bits_in - -module sign_extend (in,out); - parameter bits_in=0; // FIXME Quartus insists on a default - parameter bits_out=0; - - input [bits_in-1:0] in; - output [bits_out-1:0] out; - - assign out = {{(bits_out-bits_in){in[bits_in-1]}},in}; - -endmodule diff --git a/sdr_lib/small_hb_dec.v b/sdr_lib/small_hb_dec.v deleted file mode 100644 index 8519b628a..000000000 --- a/sdr_lib/small_hb_dec.v +++ /dev/null @@ -1,111 +0,0 @@ -// Short halfband decimator (intended to be followed by another stage) -// Implements impulse responses of the form [A 0 B 0.5 B 0 A] -// -// These taps designed by halfgen4 from ldoolittle: -// 2 * 131072 * halfgen4(.75/8,2) -module small_hb_dec - #(parameter WIDTH=18) - (input clk, - input rst, - input bypass, - input run, - input stb_in, - input [WIDTH-1:0] data_in, - output reg stb_out, - output [WIDTH-1:0] data_out); - - reg stb_in_d1; - reg [WIDTH-1:0] data_in_d1; - always @(posedge clk) stb_in_d1 <= stb_in; - always @(posedge clk) data_in_d1 <= data_in; - - wire go; - reg phase, go_d1, go_d2, go_d3, go_d4; - always @(posedge clk) - if(rst | ~run) - phase <= 0; - else if(stb_in_d1) - phase <= ~phase; - assign go = stb_in_d1 & phase; - always @(posedge clk) - if(rst | ~run) - begin - go_d1 <= 0; - go_d2 <= 0; - go_d3 <= 0; - go_d4 <= 0; - end - else - begin - go_d1 <= go; - go_d2 <= go_d1; - go_d3 <= go_d2; - go_d4 <= go_d3; - end - - wire [17:0] coeff_a = -10690; - wire [17:0] coeff_b = 75809; - - reg [WIDTH-1:0] d1, d2, d3, d4 , d5, d6; - always @(posedge clk) - if(stb_in_d1 | rst) - begin - d1 <= data_in_d1; - d2 <= d1; - d3 <= d2; - d4 <= d3; - d5 <= d4; - d6 <= d5; - end - - reg [17:0] sum_a, sum_b, middle, middle_d1; - wire [17:0] sum_a_unreg, sum_b_unreg; - add2 #(.WIDTH(18)) add2_a (.in1(data_in_d1),.in2(d6),.sum(sum_a_unreg)); - add2 #(.WIDTH(18)) add2_b (.in1(d2),.in2(d4),.sum(sum_b_unreg)); - - always @(posedge clk) - if(go) - begin - sum_a <= sum_a_unreg; - sum_b <= sum_b_unreg; - middle <= d3; - end - - always @(posedge clk) - if(go_d1) - middle_d1 <= middle; - - wire [17:0] sum = go_d1 ? sum_b : sum_a; - wire [17:0] coeff = go_d1 ? coeff_b : coeff_a; - wire [35:0] prod; - MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) ); - - reg [35:0] accum; - always @(posedge clk) - if(rst) - accum <= 0; - else if(go_d2) - accum <= {middle_d1[17],middle_d1[17],middle_d1,16'd0} + {prod}; - else if(go_d3) - accum <= accum + {prod}; - - wire [17:0] accum_rnd; - round #(.bits_in(36),.bits_out(18)) round_acc (.in(accum),.out(accum_rnd)); - - reg [17:0] final_sum; - always @(posedge clk) - if(bypass) - final_sum <= data_in_d1; - else if(go_d4) - final_sum <= accum_rnd; - - assign data_out = final_sum; - - always @(posedge clk) - if(rst) - stb_out <= 0; - else if(bypass) - stb_out <= stb_in_d1; - else - stb_out <= go_d4; -endmodule // small_hb_dec diff --git a/sdr_lib/small_hb_dec_tb.v b/sdr_lib/small_hb_dec_tb.v deleted file mode 100644 index 0d6a0689e..000000000 --- a/sdr_lib/small_hb_dec_tb.v +++ /dev/null @@ -1,140 +0,0 @@ -module hb_dec_tb( ) ; - - // Parameters for instantiation - parameter clocks = 9'd2 ; // Number of clocks per input - parameter decim = 1 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - reg strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - initial - begin - $dumpfile("hb_dec_tb.vcd"); - $dumpvars(0,hb_dec_tb); - end - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #1000 reset = 1'b0 ; - - // Enable the entire system - initial enable = 1'b1 ; - - // Instantiate UUT - /* - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - */ - - - small_hb_dec #(.WIDTH(18)) uut - (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), - .stb_out(strobe_out),.data_out(data_out) ); - - integer i, ri, ro, infile, outfile ; - - always @(posedge clock) - begin - if(strobe_out) - $display(data_out); - end - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - strobe_in <= 1'd0 ; - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( posedge clock ) begin - //#1 ; - strobe_in <= 1'b1 ; - if( !$feof(infile) ) - ri = $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - - // Clocked in - set the strobe to 0 if the number of - // clocks per sample is greater than 1 - if( clocks > 1 ) begin - @(posedge clock) begin - strobe_in <= 1'b0 ; - end - - // Wait for the specified number of cycles - for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin - @(posedge clock) #1 ; - end - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $finish ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - //$display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - endofsim <= 1'b1 ; - end - end - end - -endmodule // hb_dec_tb - diff --git a/sdr_lib/small_hb_int.v b/sdr_lib/small_hb_int.v deleted file mode 100644 index f80d3cac3..000000000 --- a/sdr_lib/small_hb_int.v +++ /dev/null @@ -1,85 +0,0 @@ -// Short halfband decimator (intended to be followed by another stage) -// Implements impulse responses of the form [A 0 B 0.5 B 0 A] -// -// These taps designed by halfgen4 from ldoolittle: -// 2 * 131072 * halfgen4(.75/8,2) - -module small_hb_int - #(parameter WIDTH=18) - (input clk, - input rst, - input bypass, - input stb_in, - input [WIDTH-1:0] data_in, - input [7:0] output_rate, - input stb_out, - output reg [WIDTH-1:0] data_out); - - reg phase; - reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6; - - localparam MWIDTH = 36; - wire [MWIDTH-1:0] prod; - - reg [6:0] stbin_d; - - always @(posedge clk) - stbin_d <= {stbin_d[5:0],stb_in}; - - always @(posedge clk) - if(stb_in) - begin - d1 <= data_in; - d2 <= d1; - d3 <= d2; - d4 <= d3; - d5 <= d4; - d6 <= d5; - end - - wire [WIDTH-1:0] sum_outer, sum_inner; - add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer)); - add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner)); - - wire [17:0] coeff_outer = -10690; - wire [17:0] coeff_inner = 75809; - - MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner), - .B(stbin_d[1] ? sum_outer : sum_inner) ); - - wire [MWIDTH:0] accum; - acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) - acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum)); - - wire [WIDTH+2:0] accum_rnd; - round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3)) - final_round (.clk(clk),.in(accum),.out(accum_rnd)); - - wire [WIDTH-1:0] clipped; - clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) - final_clip (.clk(clk),.in(accum_rnd),.out(clipped)); - - reg [WIDTH-1:0] saved, saved_d3; - always @(posedge clk) - if(stbin_d[6]) - saved <= clipped; - - always @(posedge clk) - if(stbin_d[3]) - saved_d3 <= d3; - - always @(posedge clk) - if(bypass) - data_out <= data_in; - else if(stb_in & stb_out) - case(output_rate) - 1 : data_out <= d6; - 2 : data_out <= d4; - 3, 4, 5, 6, 7 : data_out <= d3; - default : data_out <= d2; - endcase // case(output_rate) - else if(stb_out) - data_out <= saved; - -endmodule // small_hb_int - diff --git a/sdr_lib/small_hb_int_tb.v b/sdr_lib/small_hb_int_tb.v deleted file mode 100644 index 71d77f0a8..000000000 --- a/sdr_lib/small_hb_int_tb.v +++ /dev/null @@ -1,132 +0,0 @@ -module small_hb_int_tb( ) ; - - // Parameters for instantiation - parameter clocks = 8'd1 ; // Number of clocks per output - parameter decim = 1 ; // Sets the filter to decimate - parameter rate = 2 ; // Sets the decimation rate - - reg clock ; - reg reset ; - reg enable ; - wire strobe_in ; - reg signed [17:0] data_in ; - wire strobe_out ; - wire signed [17:0] data_out ; - - initial - begin - $dumpfile("small_hb_int_tb.vcd"); - $dumpvars(0,small_hb_int_tb); - end - - // Setup the clock - initial clock = 1'b0 ; - always #5 clock <= ~clock ; - - // Come out of reset after a while - initial reset = 1'b1 ; - initial #1000 reset = 1'b0 ; - - always @(posedge clock) - enable <= ~reset; - - // Instantiate UUT - /* - halfband_ideal - #( - .decim ( decim ), - .rate ( rate ) - ) uut( - .clock ( clock ), - .reset ( reset ), - .enable ( enable ), - .strobe_in ( strobe_in ), - .data_in ( data_in ), - .strobe_out ( strobe_out ), - .data_out ( data_out ) - ) ; - */ - - cic_strober #(.WIDTH(8)) - out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks), - .strobe_fast(1),.strobe_slow(strobe_out) ); - - cic_strober #(.WIDTH(8)) - in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2), - .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); - - small_hb_int #(.WIDTH(18)) uut - (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), - .stb_out(strobe_out),.output_rate(clocks),.data_out(data_out) ); - - integer i, ri, ro, infile, outfile ; - - always @(posedge clock) - begin - if(strobe_out) - $display(data_out); - end - - // Setup file IO - initial begin - infile = $fopen("input.dat","r") ; - outfile = $fopen("output.dat","r") ; - $timeformat(-9, 2, " ns", 10) ; - end - - reg endofsim ; - reg signed [17:0] compare ; - integer noe ; - initial noe = 0 ; - - initial begin - // Initialize inputs - data_in <= 18'd0 ; - - // Wait for reset to go away - @(negedge reset) #0 ; - - // While we're still simulating ... - while( !endofsim ) begin - - // Write the input from the file or 0 if EOF... - @( negedge clock ) begin - if(strobe_in) - if( !$feof(infile) ) - ri <= #1 $fscanf( infile, "%d", data_in ) ; - else - data_in <= 18'd0 ; - end - end - - // Print out the number of errors that occured - if( noe ) - $display( "FAILED: %d errors during simulation", noe ) ; - else - $display( "PASSED: Simulation successful" ) ; - - $finish ; - end - - // Output comparison of simulated values versus known good values - always @ (posedge clock) begin - if( reset ) - endofsim <= 1'b0 ; - else begin - if( !$feof(outfile) ) begin - if( strobe_out ) begin - ro = $fscanf( outfile, "%d\n", compare ) ; - if( compare != data_out ) begin - //$display( "%t: %d != %d", $realtime, data_out, compare ) ; - noe = noe + 1 ; - end - end - end else begin - // Signal end of simulation when no more outputs - if($feof(infile)) - endofsim <= 1'b1 ; - end - end - end - -endmodule // small_hb_int_tb diff --git a/sdr_lib/tx_control.v b/sdr_lib/tx_control.v deleted file mode 100644 index e5fed0b93..000000000 --- a/sdr_lib/tx_control.v +++ /dev/null @@ -1,168 +0,0 @@ - -`define DSP_CORE_TX_BASE 128 - -module tx_control - #(parameter FIFOSIZE = 10) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [31:0] master_time, - output underrun, - - // To FIFO interface from Buffer Pool - input [31:0] rd_dat_i, - input [3:0] rd_flags_i, - input rd_ready_i, - output rd_ready_o, - - // To DSP Core - output [31:0] sample, - output run, - input strobe, - - // FIFO Levels - output [15:0] fifo_occupied, - output fifo_full, - output fifo_empty, - - // Debug - output [31:0] debug - ); - - wire rd_sop_i = rd_flags_i[0]; // Unused - wire rd_eop_i = rd_flags_i[1]; - wire rd_occ_i = rd_flags_i[3:2]; // Unused, should always be 0 - - // Buffer interface to internal FIFO - wire write_data, write_ctrl, full_data, full_ctrl; - wire read_data, read_ctrl, empty_data, empty_ctrl; - wire clear_state; - reg [1:0] xfer_state; - reg [2:0] held_flags; - - localparam XFER_IDLE = 0; - localparam XFER_CTRL = 1; - localparam XFER_PKT = 2; - // Add underrun state? - - always @(posedge clk) - if(rst) - xfer_state <= XFER_IDLE; - else if(clear_state) - xfer_state <= XFER_IDLE; - else - if(rd_ready_i & rd_ready_o) - case(xfer_state) - XFER_IDLE : - begin - xfer_state <= XFER_CTRL; - held_flags <= rd_dat_i[2:0]; - end - XFER_CTRL : - xfer_state <= XFER_PKT; - XFER_PKT : - if(rd_eop_i) - xfer_state <= XFER_IDLE; - endcase // case(xfer_state) - - wire have_data_space; - assign full_data = ~have_data_space; - - assign write_data = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o; - assign write_ctrl = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o; - - assign rd_ready_o = ~full_data & ~full_ctrl; - - wire [31:0] data_o; - wire eop_o, eob, sob, send_imm; - wire [31:0] sendtime; - wire [4:0] occ_ctrl; -/* - cascadefifo2 #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo - (.clk(clk),.rst(rst),.clear(clear_state), - .datain({rd_eop_i,rd_dat_i[31:0]}), .write(write_data), .full(full_data), - .dataout({eop_o,data_o}), .read(read_data), .empty(empty_data), - .space(), .occupied(fifo_occupied) ); -*/ - wire have_data; - assign empty_data = ~have_data; - - fifo_cascade #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo - (.clk(clk),.reset(rst),.clear(clear_state), - .datain({rd_eop_i,rd_dat_i[31:0]}), .src_rdy_i(write_data), .dst_rdy_o(have_data_space), - .dataout({eop_o,data_o}), .src_rdy_o(have_data), .dst_rdy_i(read_data), - .space(), .occupied(fifo_occupied) ); - assign fifo_full = full_data; - assign fifo_empty = empty_data; - - shortfifo #(.WIDTH(35)) ctrlfifo - (.clk(clk),.rst(rst),.clear(clear_state), - .datain({held_flags[2:0],rd_dat_i[31:0]}), .write(write_ctrl), .full(full_ctrl), - .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), .empty(empty_ctrl), - .space(), .occupied(occ_ctrl) ); - - // Internal FIFO to DSP interface - reg [2:0] ibs_state; - - localparam IBS_IDLE = 0; - localparam IBS_WAIT = 1; - localparam IBS_RUNNING = 2; - localparam IBS_CONT_BURST = 3; - localparam IBS_UNDERRUN = 7; - - wire [32:0] delta_time = {1'b0,sendtime}-{1'b0,master_time}; - - wire too_late = (delta_time[32:31] == 2'b11); - wire go_now = ( master_time == sendtime ); - - always @(posedge clk) - if(rst) - ibs_state <= IBS_IDLE; - else - case(ibs_state) - IBS_IDLE : - if(~empty_ctrl & ~empty_data) - ibs_state <= IBS_WAIT; - IBS_WAIT : - if(send_imm) - ibs_state <= IBS_RUNNING; - else if(too_late) - ibs_state <= IBS_UNDERRUN; - else if(go_now) - ibs_state <= IBS_RUNNING; - IBS_RUNNING : - if(strobe) - if(empty_data) - ibs_state <= IBS_UNDERRUN; - else if(eop_o) - if(eob) - ibs_state <= IBS_IDLE; - else - ibs_state <= IBS_CONT_BURST; - IBS_CONT_BURST : - if(~empty_ctrl) // & ~empty_data) - ibs_state <= IBS_RUNNING; - else if(strobe) - ibs_state <= IBS_UNDERRUN; - IBS_UNDERRUN : // FIXME Should probably clean everything out - if(clear_state) - ibs_state <= IBS_IDLE; - endcase // case(ibs_state) - - assign read_ctrl = (ibs_state == IBS_RUNNING) & strobe & eop_o; // & ~empty_ctrl; - assign read_data = (ibs_state == IBS_RUNNING) & strobe & ~empty_data; - assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_CONT_BURST); - assign underrun = (ibs_state == IBS_UNDERRUN); - - wire [7:0] interp_rate; - setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_state)); - - assign sample = data_o; - - assign debug = { {16'b0}, - { read_data, write_data, read_ctrl, write_ctrl, xfer_state[1:0],full_ctrl,empty_ctrl }, - { occ_ctrl, eop_o, clear_state, underrun} }; - -endmodule // tx_control diff --git a/serdes/serdes.v b/serdes/serdes.v deleted file mode 100644 index 17049bfe6..000000000 --- a/serdes/serdes.v +++ /dev/null @@ -1,63 +0,0 @@ - -// SERDES TX and RX along with all flow control logic - -module serdes - #(parameter TXFIFOSIZE = 9, - parameter RXFIFOSIZE = 9) - (input clk, input rst, - // TX side - output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb, - input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input rd_ready_i, - // RX side - input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb, - output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input wr_ready_i, - - output [15:0] tx_occupied, output tx_full, output tx_empty, - output [15:0] rx_occupied, output rx_full, output rx_empty, - - output serdes_link_up, - - output [31:0] debug0, - output [31:0] debug1); - - wire [15:0] fifo_space; - wire xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent; - wire [31:0] debug_rx, debug_tx; - - serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx - (.clk(clk),.rst(rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i), - .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent), - .fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty), - .debug(debug_tx) ); - - serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx - (.clk(clk),.rst(rst), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i), - .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd), - .fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty), - .serdes_link_up(serdes_link_up), .debug(debug_rx) ); - - serdes_fc_tx serdes_fc_tx - (.clk(clk),.rst(rst), - .xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) ); - - serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx - (.clk(clk),.rst(rst), - .fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) ); - - //assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] }; - //assign debug = debug_rx; - - assign debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]}, - { debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb}, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug1 = { { debug_rx[7:0] }, /* odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */ - { wr_flags_o[1:0], wr_ready_i, wr_ready_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb }, - { ser_r[15:8] }, - { ser_r[7:0] } }; -endmodule // serdes diff --git a/serdes/serdes_fc_rx.v b/serdes/serdes_fc_rx.v deleted file mode 100644 index 4dd46e27f..000000000 --- a/serdes/serdes_fc_rx.v +++ /dev/null @@ -1,62 +0,0 @@ - - -module serdes_fc_rx - #(parameter LWMARK = 64, - parameter HWMARK = 320) - (input clk, input rst, - input [15:0] fifo_space, - output reg send_xon, - output reg send_xoff, - input sent); - - reg [15:0] countdown; - reg send_xon_int, send_xoff_int; - - always @(posedge clk) - if(rst) - begin - send_xon_int <= 0; - send_xoff_int <= 0; - countdown <= 0; - end - else - begin - send_xon_int <= 0; - send_xoff_int <= 0; - if(countdown == 0) - if(fifo_space < LWMARK) - begin - send_xoff_int <= 1; - countdown <= 240; - end - else - ; - else - if(fifo_space > HWMARK) - begin - send_xon_int <= 1; - countdown <= 0; - end - else - countdown <= countdown - 1; - end // else: !if(rst) - - // If we are between the high and low water marks, we let the countdown expire - - always @(posedge clk) - if(rst) - send_xon <= 0; - else if(send_xon_int) - send_xon <= 1; - else if(sent) - send_xon <= 0; - - always @(posedge clk) - if(rst) - send_xoff <= 0; - else if(send_xoff_int) - send_xoff <= 1; - else if(sent) - send_xoff <= 0; - -endmodule // serdes_fc_rx diff --git a/serdes/serdes_fc_tx.v b/serdes/serdes_fc_tx.v deleted file mode 100644 index 2fe967c8d..000000000 --- a/serdes/serdes_fc_tx.v +++ /dev/null @@ -1,24 +0,0 @@ - - -module serdes_fc_tx - (input clk, input rst, - input xon_rcvd, input xoff_rcvd, output reg inhibit_tx); - - // XOFF means stop sending, XON means start sending - // clock domain stuff happens elsewhere, everything here is on main clk - - reg [15:0] state; - always @(posedge clk) - if(rst) - state <= 0; - else if(xoff_rcvd) - state <= 255; - else if(xon_rcvd) - state <= 0; - else if(state !=0) - state <= state - 1; - - always @(posedge clk) - inhibit_tx <= (state != 0); - -endmodule // serdes_fc_tx diff --git a/serdes/serdes_rx.v b/serdes/serdes_rx.v deleted file mode 100644 index afefccaa1..000000000 --- a/serdes/serdes_rx.v +++ /dev/null @@ -1,292 +0,0 @@ - -// SERDES Interface - -// LS-Byte is sent first, MS-Byte is second -// Invalid K Codes -// K0.0 000-00000 Error detected -// K31.7 111-11111 Loss of input signal - -// Valid K Codes -// K28.0 000-11100 -// K28.1 001-11100 Alternate COMMA? -// K28.2 010-11100 -// K28.3 011-11100 -// K28.4 100-11100 -// K28.5 101-11100 Standard COMMA? -// K28.6 110-11100 -// K28.7 111-11100 Bad COMMA? -// K23.7 111-10111 -// K27.7 111-11011 -// K29.7 111-11101 -// K30.7 111-11110 - -module serdes_rx - #(parameter FIFOSIZE = 9) - (input clk, - input rst, - - // RX HW Interface - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - output [31:0] wr_dat_o, - output [3:0] wr_flags_o, - input wr_ready_i, - output wr_ready_o, - - output [15:0] fifo_space, - output xon_rcvd, output xoff_rcvd, - - output [15:0] fifo_occupied, output fifo_full, output fifo_empty, - output reg serdes_link_up, - output [31:0] debug - ); - - localparam K_COMMA = 8'b101_11100; // 0xBC K28.5 - localparam K_IDLE = 8'b001_11100; // 0x3C K28.1 - localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6 - localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4 - localparam K_XON = 8'b010_11100; // 0x5C K28.2 - localparam K_XOFF = 8'b011_11100; // 0x7C K28.3 - localparam K_LOS = 8'b111_11111; // 0xFF K31.7 - localparam K_ERROR = 8'b000_00000; // 0x00 K00.0 - localparam D_56 = 8'b110_00101; // 0xC5 D05.6 - - localparam IDLE = 3'd0; - localparam FIRSTLINE1 = 3'd1; - localparam FIRSTLINE2 = 3'd2; - localparam PKT1 = 3'd3; - localparam PKT2 = 3'd4; - localparam CRC_CHECK = 3'd5; - localparam ERROR = 3'd6; - localparam DONE = 3'd7; - - wire [17:0] even_data; - reg [17:0] odd_data; - wire [17:0] chosen_data; - reg odd; - - reg [31:0] line_i; - reg sop_i, eop_i, error_i; - wire error_o, sop_o, eop_o, write; - reg [15:0] halfline; - reg [8:0] holder; - wire [31:0] line_o; - - reg [2:0] state; - - reg [15:0] CRC; - wire [15:0] nextCRC; - reg write_d; - - wire rst_rxclk; - wire have_space; - - oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk)); - - assign even_data = {ser_rkmsb,ser_rklsb,ser_r}; - - always @(posedge ser_rx_clk) - if(rst_rxclk) - holder <= 9'd0; - else - holder <= {even_data[17],even_data[15:8]}; - - always @(posedge ser_rx_clk) - if(rst_rxclk) - odd_data <= 18'd0; - else - odd_data <= {even_data[16],holder[8],even_data[7:0],holder[7:0]}; - - assign chosen_data = odd ? odd_data : even_data; - - // Transfer xon and xoff info to the main system clock for flow control purposes - reg xon_rcvd_rxclk, xoff_rcvd_rxclk; - always @(posedge ser_rx_clk) - xon_rcvd_rxclk = ({1'b1,K_XON} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XON} == {ser_rklsb,ser_r[7:0]} ); - always @(posedge ser_rx_clk) - xoff_rcvd_rxclk = ({1'b1,K_XOFF} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XOFF} == {ser_rklsb,ser_r[7:0]} ); - - oneshot_2clk xon_1s(.clk_in(ser_rx_clk),.in(xon_rcvd_rxclk),.clk_out(clk),.out(xon_rcvd)); - oneshot_2clk xoff_1s(.clk_in(ser_rx_clk),.in(xoff_rcvd_rxclk),.clk_out(clk),.out(xoff_rcvd)); - - // If the other side is sending xon or xoff, or is flow controlled (b/c we told them to be), don't fill the fifos - wire wait_here = ((chosen_data == {2'b10,K_COMMA,D_56})|| - (chosen_data == {2'b11,K_XON,K_XON})|| - (chosen_data == {2'b11,K_XOFF,K_XOFF}) ); - - always @(posedge ser_rx_clk) - if(rst_rxclk) sop_i <= 0; - else if(state == FIRSTLINE1) sop_i <= 1; - else if(write_d) sop_i <= 0; - - reg write_pre; - always @(posedge ser_rx_clk) - if(rst_rxclk) - begin - state <= IDLE; - odd <= 0; - halfline <= 0; - line_i <= 0; - eop_i <= 0; - error_i <= 0; - write_pre <= 0; - end - else - case(state) - IDLE : - begin - error_i <= 0; - write_pre <= 0; - if(even_data == {2'b11,K_PKT_START,K_PKT_START}) - begin - state <= FIRSTLINE1; - odd <= 0; - end - else if(odd_data == {2'b11,K_PKT_START,K_PKT_START}) - begin - state <= FIRSTLINE1; - odd <= 1; - end - end - - FIRSTLINE1 : - if(chosen_data[17:16] == 0) - begin - halfline <= chosen_data[15:0]; - state <= FIRSTLINE2; - end - else if(wait_here) - ; // Flow Controlled, so wait here and do nothing - else - state <= ERROR; - - FIRSTLINE2 : - if(chosen_data[17:16] == 0) - begin - line_i <= {chosen_data[15:0],halfline}; - if(~have_space) // No space to write to! Should have been avoided by flow control - state <= ERROR; - else - begin - state <= PKT1; - write_pre <= 1; - end - end // if (chosen_data[17:16] == 0) - else if(wait_here) - ; // Flow Controlled, so wait here and do nothing - else - state <= ERROR; - - PKT1 : - begin - write_pre <= 0; - if(chosen_data[17:16] == 0) - begin - halfline <= chosen_data[15:0]; - state <= PKT2; - end - else if(wait_here) - ; // Flow Controlled - else if(chosen_data == {2'b11,K_PKT_END,K_PKT_END}) - state <= CRC_CHECK; - else - state <= ERROR; - end // case: PKT1 - - PKT2 : - if(chosen_data[17:16] == 0) - begin - line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline}; - if(~have_space) // No space to write to! - state <= ERROR; - else - begin - state <= PKT1; - write_pre <= 1; - end - end // if (chosen_data[17:16] == 0) - else if(wait_here) - ; // Flow Controlled - else - state <= ERROR; - - CRC_CHECK : - if(chosen_data[17:0] == {2'b00,CRC}) - begin - if(~have_space) - state <= ERROR; - else - begin - eop_i <= 1; - state <= DONE; - end - end - else if(wait_here) - ; - else - state <= ERROR; - - ERROR : - begin - error_i <= 1; - if(have_space) - state <= IDLE; - end - DONE : - begin - state <= IDLE; - eop_i <= 0; - end - - endcase // case(state) - - - always @(posedge ser_rx_clk) - if(rst_rxclk) - CRC <= 16'hFFFF; - else if(state == IDLE) - CRC <= 16'hFFFF; - else if(chosen_data[17:16] == 2'b00) - CRC <= nextCRC; - - CRC16_D16 crc_blk(chosen_data[15:0],CRC,nextCRC); - - always @(posedge ser_rx_clk) - if(rst_rxclk) write_d <= 0; - else write_d <= write_pre; - - // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes - assign write = eop_i | (error_i & have_space) | (write_d & (state != CRC_CHECK)); - - fifo_2clock_cascade #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo - (.arst(rst), - .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), - .src_rdy_i(write), .dst_rdy_o(have_space), .space(fifo_space), - .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), - .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), .occupied(fifo_occupied) ); - - assign fifo_full = ~have_space; // Note -- in the wrong clock domain - assign fifo_empty = ~wr_ready_o; - - // Internal FIFO to Buffer interface - assign wr_dat_o = line_o; - assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o }; - - wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) || - ({2'b11,K_LOS,K_LOS}=={ser_rkmsb,ser_rklsb,ser_r})); - - reg [3:0] slu_reg; - - always @(posedge clk) - if(rst) slu_reg <= 0; - else slu_reg <= {slu_reg[2:0],slu}; - - always @(posedge clk) - serdes_link_up <= &slu_reg[3:1]; - - assign debug = { have_space, wr_ready_o, odd, sop_i, eop_i, error_i, state[2:0] }; - -endmodule // serdes_rx diff --git a/serdes/serdes_tb.v b/serdes/serdes_tb.v deleted file mode 100644 index eb8e019fc..000000000 --- a/serdes/serdes_tb.v +++ /dev/null @@ -1,328 +0,0 @@ - -// FIXME need to add flow control - -module serdes_tb(); - - reg clk, rst; - wire ser_rx_clk, ser_tx_clk; - wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb; - wire [15:0] ser_r, ser_t; - - initial clk = 0; - initial rst = 1; - initial #1000 rst = 0; - always #100 clk = ~clk; - - // Wishbone - reg [31:0] wb_dat_i; - wire [31:0] wb_dat_o_rx, wb_dat_o_tx; - reg wb_we, wb_en_rx, wb_en_tx; - reg [8:0] wb_adr; - - // Buffer Control - reg go, clear, read, write; - reg [3:0] buf_num; - wire [31:0] ctrl_word = {buf_num,3'b0,clear,write,read,step,lastline,firstline}; - reg [8:0] firstline = 0, lastline = 0; - reg [3:0] step = 1; - reg first_tx = 1, first_rx = 1; // for verif - - // TX Side - reg wb_we_tx; - wire en_tx, we_tx; - wire [8:0] addr_tx; - wire [31:0] f2r_tx, r2f_tx; - wire [31:0] data_tx; - wire read_tx, done_tx, error_tx, sop_tx, eop_tx; - - wire fdone_tx, ferror_tx; - - reg even; - reg channel_error = 0; - - serdes_tx serdes_tx - (.clk(clk),.rst(rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(data_tx),.rd_read_o(read_tx),.rd_done_o(done_tx), - .rd_error_o(error_tx),.rd_sop_i(sop_tx),.rd_eop_i(eop_tx) ); - - ram_2port #(.DWIDTH(32),.AWIDTH(9)) - ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we_tx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx), - .clkb(clk),.enb(en_tx),.web(we_tx),.addrb(addr_tx),.dib(f2r_tx),.dob(r2f_tx)); - - buffer_int #(.BUFF_NUM(1)) buffer_int_tx - (.clk(clk),.rst(rst), - .ctrl_word(ctrl_word),.go(go), - .done(fdone_tx),.error(ferror_tx), - - .en_o(en_tx),.we_o(we_tx),.addr_o(addr_tx),.dat_to_buf(f2r_tx),.dat_from_buf(r2f_tx), - - .wr_dat_i(0),.wr_write_i(0),.wr_done_i(0), - .wr_error_i(0),.wr_ready_o(),.wr_full_o(), - - .rd_dat_o(data_tx),.rd_read_i(read_tx),.rd_done_i(done_tx), - .rd_error_i(error_tx),.rd_sop_o(sop_tx),.rd_eop_o(eop_tx) ); - - - // RX Side - reg wb_we_rx; - wire en_rx, we_rx; - wire [8:0] addr_rx; - wire [31:0] f2r_rx, r2f_rx; - wire [31:0] data_rx; - wire write_rx, done_rx, error_rx, ready_rx, empty_rx; - - wire fdone_rx, ferror_rx; - - serdes_rx serdes_rx - (.clk(clk),.rst(rst), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(data_rx),.wr_write_o(write_rx),.wr_done_o(done_rx), - .wr_error_o(error_rx),.wr_ready_i(ready_rx),.wr_full_i(full_rx) ); - - ram_2port #(.DWIDTH(32),.AWIDTH(9)) - ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we_rx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx), - .clkb(clk),.enb(en_rx),.web(we_rx),.addrb(addr_rx),.dib(f2r_rx),.dob(r2f_rx) ); - - buffer_int #(.BUFF_NUM(0)) buffer_int_rx - (.clk(clk),.rst(rst), - .ctrl_word(ctrl_word),.go(go), - .done(fdone_rx),.error(ferror_rx), - - .en_o(en_rx),.we_o(we_rx),.addr_o(addr_rx),.dat_to_buf(f2r_rx),.dat_from_buf(r2f_rx), - - .wr_dat_i(data_rx),.wr_write_i(write_rx),.wr_done_i(done_rx), - .wr_error_i(error_rx),.wr_ready_o(ready_rx),.wr_full_o(full_rx), - - .rd_dat_o(),.rd_read_i(0),.rd_done_i(0), - .rd_error_i(0),.rd_sop_o(),.rd_eop_o() ); - - // Simulate the connection - serdes_model serdes_model - (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), - .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), - .even(even), .error(channel_error) ); - - initial begin - wb_en_rx <= 0; - wb_en_tx <=0; - wb_we_tx <= 0; - wb_we_rx <= 0; - wb_adr <= 0; - wb_dat_i <= 0; - go <= 0; - even <= 0; - @(negedge rst); - @(posedge clk); - FillTXRAM; - ClearRXRAM; - ResetBuffer(0); - ResetBuffer(1); - - // receive a full buffer - ReceiveSERDES(0,10); - SendSERDES(0,10); - - // Receive a partial buffer - SendSERDES(11,20); - ReceiveSERDES(11,50); - - // Receive too many for buffer - SendSERDES(21,100); - ReceiveSERDES(21,30); - - // Send 3 packets, then wait to receive them, so they stack up in the rx fifo - SendSERDES(31,40); - SendSERDES(41,50); - SendSERDES(51,60); - repeat (10) - @(posedge clk); - ReceiveSERDES(31,40); - ReceiveSERDES(41,50); - repeat (1000) - @(posedge clk); - ReceiveSERDES(51,60); - - // Overfill the FIFO, should get an error on 3rd packet - SendSERDES(1,400); - SendSERDES(1,400); - - - WaitForTX; - //WaitForRX; - - - repeat(1000) - @(posedge clk); - ReceiveSERDES(101,500); - ReceiveSERDES(101,500); - ReadRAM(80); - $finish; - end // initial begin - - always @(posedge clk) - if(write_rx) - $display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO FULL %d",data_rx, ready_rx, full_rx); - - always @(posedge clk) - if(read_tx) - $display("SERDES TX, FIFO READ %x, SOP %d, EOP %d",data_tx, sop_tx, eop_tx); - - initial begin - $dumpfile("serdes_tb.vcd"); - $dumpvars(0,serdes_tb); - end - - initial #10000000 $finish; - - initial #259300 channel_error <= 1; - initial #259500 channel_error <= 0; - - task FillTXRAM; - begin - wb_adr <= 0; - wb_dat_i <= 32'h10802000; - wb_we_tx <= 1; - wb_en_tx <= 1; - @(posedge clk); - repeat(511) begin - wb_dat_i <= wb_dat_i + 32'h00010001; - wb_adr <= wb_adr + 1; - @(posedge clk); - end // repeat (511) - wb_we_tx <= 0; - wb_en_tx <= 0; - @(posedge clk); - $display("Done entering Data into TX RAM\n"); - end - endtask // FillTXRAM - - task ClearRXRAM; - begin - wb_adr <= 0; - wb_dat_i <= 0; - wb_we_rx <= 1; - wb_en_rx <= 1; - wb_dat_i <= 0; - @(posedge clk); - repeat(511) begin - wb_adr <= wb_adr + 1; - @(posedge clk); - end // repeat (511) - wb_we_rx <= 0; - wb_en_rx <= 0; - @(posedge clk); - $display("Done clearing RX RAM\n"); - end - endtask // FillRAM - - task ReadRAM; - input [8:0] lastline; - begin - wb_en_rx <= 1; - wb_adr <= 0; - @(posedge clk); - @(posedge clk); - repeat(lastline) begin - $display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx); - wb_adr <= wb_adr + 1; - @(posedge clk); - @(posedge clk); - end // repeat (511) - $display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx); - wb_en_rx <= 0; - @(posedge clk); - $display("Done reading out RX RAM\n"); - end - endtask // FillRAM - - task ResetBuffer; - input [3:0] buffer_num; - begin - buf_num <= buffer_num; - clear <= 1; read <= 0; write <= 0; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Reset"); - end - endtask // ClearBuffer - - task SetBufferWrite; - input [3:0] buffer_num; - input [8:0] start; - input [8:0] stop; - begin - buf_num <= buffer_num; - clear <= 0; read <= 0; write <= 1; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Write"); - end - endtask // SetBufferWrite - - task SetBufferRead; - input [3:0] buffer_num; - input [8:0] start; - input [8:0] stop; - begin - buf_num <= buffer_num; - clear <= 0; read <= 1; write <= 0; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Read"); - end - endtask // SetBufferRead - - task WaitForTX; - begin - while (!(fdone_tx | ferror_tx)) - @(posedge clk); - end - endtask // WaitForTX - - task WaitForRX; - begin - while (!(fdone_rx | ferror_rx)) - @(posedge clk); - end - endtask // WaitForRX - - task SendSERDES; - input [8:0] start; - input [8:0] stop; - begin - if(~first_tx) - WaitForTX; - else - first_tx <= 0; - ResetBuffer(1); - SetBufferRead(1,start,stop); - $display("Here"); - end - endtask // SendSERDES - - task ReceiveSERDES; - input [8:0] start; - input [8:0] stop; - begin - if(~first_rx) - WaitForRX; - else - first_rx <= 0; - ResetBuffer(0); - SetBufferWrite(0,start,stop); - $display("Here2"); - end - endtask // ReceiveSERDES - -endmodule // serdes_tb diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v deleted file mode 100644 index 2e5e3bd80..000000000 --- a/serdes/serdes_tx.v +++ /dev/null @@ -1,186 +0,0 @@ - -// SERDES Interface - -// LS-Byte is sent first, MS-Byte is second -// Invalid K Codes -// K0.0 000-00000 Error detected -// K31.7 111-11111 Loss of input signal - -// Valid K Codes -// K28.0 000-11100 -// K28.1 001-11100 Alternate COMMA? -// K28.2 010-11100 -// K28.3 011-11100 -// K28.4 100-11100 -// K28.5 101-11100 Standard COMMA? -// K28.6 110-11100 -// K28.7 111-11100 Bad COMMA? -// K23.7 111-10111 -// K27.7 111-11011 -// K29.7 111-11101 -// K30.7 111-11110 - -module serdes_tx - #(parameter FIFOSIZE = 9) - (input clk, - input rst, - - // TX HW Interface - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - // TX Stream Interface - input [31:0] rd_dat_i, - input [3:0] rd_flags_i, - output rd_ready_o, - input rd_ready_i, - - // Flow control interface - input inhibit_tx, - input send_xon, - input send_xoff, - output sent, - - // FIFO Levels - output [15:0] fifo_occupied, - output fifo_full, - output fifo_empty, - - // DEBUG - output [31:0] debug - ); - - localparam K_COMMA = 8'b101_11100; // 0xBC K28.5 - localparam K_IDLE = 8'b001_11100; // 0x3C K28.1 - localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6 - localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4 - localparam K_XON = 8'b010_11100; // 0x5C K28.2 - localparam K_XOFF = 8'b011_11100; // 0x7C K28.3 - localparam K_LOS = 8'b111_11111; // 0xFF K31.7 - localparam K_ERROR = 8'b000_00000; // 0x00 K00.0 - localparam D_56 = 8'b110_00101; // 0xC5 D05.6 - assign ser_tx_clk = clk; - - localparam IDLE = 3'd0; - localparam RUN1 = 3'd1; - localparam RUN2 = 3'd2; - localparam DONE = 3'd3; - localparam SENDCRC = 3'd4; - localparam WAIT = 3'd5; - - reg [2:0] state; - - reg [15:0] CRC; - wire [15:0] nextCRC; - reg [3:0] wait_count; - - // Internal FIFO, size 9 is 2K, size 10 is 4K bytes - wire sop_o, eop_o; - wire [31:0] data_o; - - wire rd_sop_i = rd_flags_i[0]; - wire rd_eop_i = rd_flags_i[1]; - wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused - - wire have_data, empty, read; - fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo - (.clk(clk),.reset(rst),.clear(0), - .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o), - .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data), - .space(), .occupied(fifo_occupied) ); - - assign fifo_full = ~rd_ready_o; - assign empty = ~have_data; - assign fifo_empty = empty; - - // FIXME Implement flow control - reg [15:0] second_word; - reg [33:0] pipeline; - - assign read = (~send_xon & ~send_xoff & (state==RUN2)) | ((state==IDLE) & ~empty & ~sop_o); - assign sent = send_xon | send_xoff; - // 2nd half of above probably not necessary. Just in case we get junk between packets - - always @(posedge clk) - if(rst) - begin - state <= IDLE; - wait_count <= 0; - {ser_tkmsb,ser_tklsb,ser_t} <= 18'd0; - //{2'b10,K_COMMA,K_COMMA}; - // make tkmsb and tklsb different so they can go in IOFFs - end - else - if(send_xon) - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XON,K_XON}; - else if(send_xoff) - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XOFF,K_XOFF}; - else - case(state) - IDLE : - begin - if(sop_o & ~empty & ~inhibit_tx) - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_START,K_PKT_START}; - state <= RUN1; - end - else - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; - end - RUN1 : - begin - if(empty | inhibit_tx) - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; - else - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[15:0]}; - state <= RUN2; - end - end - RUN2 : - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[31:16]}; - if(eop_o) - state <= DONE; - else - state <= RUN1; - end - DONE : - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_END,K_PKT_END}; - state <= SENDCRC; - end - SENDCRC : - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC}; - state <= WAIT; - wait_count <= 4'd15; - end - WAIT : - begin - {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; - if(wait_count == 0) - state <= IDLE; - else - wait_count <= wait_count - 1; - end - default - state <= IDLE; - endcase // case(state) - - always @(posedge clk) - if(rst) - CRC <= 16'hFFFF; - else if(state == IDLE) - CRC <= 16'hFFFF; - else if( (~empty & ~inhibit_tx & (state==RUN1)) || (state==RUN2) ) - CRC <= nextCRC; - - CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC); - - assign debug = { 28'd0, state[2:0] }; - -endmodule // serdes_tx - diff --git a/simple_gemac/.gitignore b/simple_gemac/.gitignore deleted file mode 100644 index 17f35e962..000000000 --- a/simple_gemac/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/a.out -/*.vcd -simple_gemac_wrapper_tb - diff --git a/simple_gemac/address_filter.v b/simple_gemac/address_filter.v deleted file mode 100644 index 50a52b954..000000000 --- a/simple_gemac/address_filter.v +++ /dev/null @@ -1,35 +0,0 @@ - - -module address_filter - (input clk, - input reset, - input go, - input [7:0] data, - input [47:0] address, - output match, - output done); - - reg [2:0] af_state; - - always @(posedge clk) - if(reset) - af_state <= 0; - else - if(go) - af_state <= (data == address[47:40]) ? 1 : 7; - else - case(af_state) - 1 : af_state <= (data == address[39:32]) ? 2 : 7; - 2 : af_state <= (data == address[31:24]) ? 3 : 7; - 3 : af_state <= (data == address[23:16]) ? 4 : 7; - 4 : af_state <= (data == address[15:8]) ? 5 : 7; - 5 : af_state <= (data == address[7:0]) ? 6 : 7; - 6, 7 : af_state <= 0; - endcase // case (af_state) - - assign match = (af_state==6); - assign done = (af_state==6)|(af_state==7); - -endmodule // address_filter - - diff --git a/simple_gemac/crc.v b/simple_gemac/crc.v deleted file mode 100644 index ac019083a..000000000 --- a/simple_gemac/crc.v +++ /dev/null @@ -1,66 +0,0 @@ - -module crc - (input clk, - input reset, - input clear, - input [7:0] data, - input calc, - output [31:0] crc_out, - output match); - - function[31:0] NextCRC; - input[7:0] D; - input[31:0] C; - reg[31:0] NewCRC; - begin - NewCRC[0] = C[24]^C[30]^D[1]^D[7]; - NewCRC[1] = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[2] = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[3] = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; - NewCRC[4] = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; - NewCRC[5] = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[6] = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; - NewCRC[7] = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; - NewCRC[8] = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; - NewCRC[9] = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; - NewCRC[10] = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; - NewCRC[11] = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; - NewCRC[12] = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[13] = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; - NewCRC[14] = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; - NewCRC[15] = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; - NewCRC[16] = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; - NewCRC[17] = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; - NewCRC[18] = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; - NewCRC[19] = C[11]^C[31]^D[0]^C[27]^D[4]; - NewCRC[20] = C[12]^C[28]^D[3]; - NewCRC[21] = C[13]^C[29]^D[2]; - NewCRC[22] = C[14]^C[24]^D[7]; - NewCRC[23] = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; - NewCRC[24] = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; - NewCRC[25] = C[17]^C[27]^D[4]^C[26]^D[5]; - NewCRC[26] = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; - NewCRC[27] = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; - NewCRC[28] = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; - NewCRC[29] = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; - NewCRC[30] = C[22]^C[31]^D[0]^C[28]^D[3]; - NewCRC[31] = C[23]^C[29]^D[2]; - NextCRC = NewCRC; - end - endfunction - - reg [31:0] crc_reg; - always @ (posedge clk) - if (reset | clear) - crc_reg <= 32'hffffffff; - else if (calc) - crc_reg <= NextCRC(data,crc_reg); - - assign crc_out = ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31], - crc_reg[16],crc_reg[17],crc_reg[18],crc_reg[19],crc_reg[20],crc_reg[21],crc_reg[22],crc_reg[23], - crc_reg[8],crc_reg[9],crc_reg[10],crc_reg[11],crc_reg[12],crc_reg[13],crc_reg[14],crc_reg[15], - crc_reg[0],crc_reg[1],crc_reg[2],crc_reg[3],crc_reg[4],crc_reg[5],crc_reg[6],crc_reg[7] }; - - assign match = (crc_reg == 32'hc704_dd7b); - -endmodule // crc diff --git a/simple_gemac/delay_line.v b/simple_gemac/delay_line.v deleted file mode 100644 index d371bb9c5..000000000 --- a/simple_gemac/delay_line.v +++ /dev/null @@ -1,21 +0,0 @@ - - -module delay_line - #(parameter WIDTH=32) - (input clk, - input [3:0] delay, - input [WIDTH-1:0] din, - output [WIDTH-1:0] dout); - - genvar i; - generate - for (i=0;i pause_hi_thresh)); - - always @(posedge rx_clk) - if(rx_reset) - countdown <= 0; - else if(xoff) - countdown <= pq_reduced; - else if(xon) - countdown <= 0; - else if(countdown != 0) - countdown <= countdown - 1; - - // Cross clock domains - wire xon_tx, xoff_tx; - oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx)); - oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx)); - - always @(posedge tx_clk) - if(xoff_tx) - pause_time_req <= pause_time; - else if(xon_tx) - pause_time_req <= 0; - - always @(posedge tx_clk) - if(tx_reset) - pause_req <= 0; - else - pause_req <= xon_tx | xoff_tx; - -endmodule // flow_ctrl_rx diff --git a/simple_gemac/flow_ctrl_tx.v b/simple_gemac/flow_ctrl_tx.v deleted file mode 100644 index f80f5a76d..000000000 --- a/simple_gemac/flow_ctrl_tx.v +++ /dev/null @@ -1,39 +0,0 @@ - -// TX side of flow control -- when other side sends PAUSE, we wait - -module flow_ctrl_tx - (input rst, - input tx_clk, - //host processor - input tx_pause_en, - // From MAC_rx_ctrl - input [15:0] pause_quanta, - input pause_quanta_val, - // MAC_tx_ctrl - output pause_apply, - input paused); - - // ****************************************************************************** - // Inhibit our TX from transmitting because they sent us a PAUSE frame - // ****************************************************************************** - - // Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be - // as big as 16 bits, so 22 bits are needed for the counter - - reg [15+6:0] pause_quanta_counter; - reg pqval_d1, pqval_d2; - - always @(posedge tx_clk) pqval_d1 <= pause_quanta_val; - always @(posedge tx_clk) pqval_d2 <= pqval_d1; - - always @ (posedge tx_clk or posedge rst) - if (rst) - pause_quanta_counter <= 0; - else if (pqval_d1 & ~pqval_d2) - pause_quanta_counter <= {pause_quanta, 6'b0}; - else if((pause_quanta_counter!=0) & paused) - pause_quanta_counter <= pause_quanta_counter - 1; - - assign pause_apply = tx_pause_en & (pause_quanta_counter != 0); - -endmodule // flow_ctrl diff --git a/simple_gemac/ll8_shortfifo.v b/simple_gemac/ll8_shortfifo.v deleted file mode 100644 index e69de29bb..000000000 diff --git a/simple_gemac/ll8_to_txmac.v b/simple_gemac/ll8_to_txmac.v deleted file mode 100644 index 3530a0c59..000000000 --- a/simple_gemac/ll8_to_txmac.v +++ /dev/null @@ -1,43 +0,0 @@ - -module ll8_to_txmac - (input clk, input reset, input clear, - input [7:0] ll_data, input ll_sof, input ll_eof, input ll_src_rdy, output ll_dst_rdy, - output [7:0] tx_data, output tx_valid, output tx_error, input tx_ack ); - - reg [2:0] xfer_state; - - localparam XFER_IDLE = 0; - localparam XFER_ACTIVE = 1; - localparam XFER_WAIT1 = 2; - localparam XFER_UNDERRUN = 3; - localparam XFER_DROP = 4; - - always @(posedge clk) - if(reset | clear) - xfer_state <= XFER_IDLE; - else - case(xfer_state) - XFER_IDLE : - if(tx_ack) - xfer_state <= XFER_ACTIVE; - XFER_ACTIVE : - if(~ll_src_rdy) - xfer_state <= XFER_UNDERRUN; - else if(ll_eof) - xfer_state <= XFER_WAIT1; - XFER_WAIT1 : - xfer_state <= XFER_IDLE; - XFER_UNDERRUN : - xfer_state <= XFER_DROP; - XFER_DROP : - if(ll_eof) - xfer_state <= XFER_IDLE; - endcase // case (xfer_state) - - assign ll_dst_rdy = (xfer_state == XFER_ACTIVE) | tx_ack | (xfer_state == XFER_DROP); - assign tx_valid = (ll_src_rdy & (xfer_state == XFER_IDLE))|(xfer_state == XFER_ACTIVE); - assign tx_data = ll_data; - assign tx_error = (xfer_state == XFER_UNDERRUN); - -endmodule // ll8_to_txmac - diff --git a/simple_gemac/miim/eth_clockgen.v b/simple_gemac/miim/eth_clockgen.v deleted file mode 100644 index 9da732f7f..000000000 --- a/simple_gemac/miim/eth_clockgen.v +++ /dev/null @@ -1,141 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_clockgen.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_clockgen.v,v $ -// Revision 1.2 2005/12/13 12:54:49 maverickist -// first simulation passed -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -// Revision 1.2 2005/04/27 15:58:45 Administrator -// no message -// -// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator -// no message -// -// Revision 1.3 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.2 2001/10/19 08:43:51 mohor -// eth_timescale.v changed to timescale.v This is done because of the -// simulation of the few cores in a one joined project. -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// Revision 1.3 2001/06/01 22:28:55 mohor -// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. -// -// - -module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); - -//parameter Tp=1; - -input Clk; // Input clock (Host clock) -input Reset; // Reset signal -input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) - -output Mdc; // Output clock -output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. -output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. - -reg Mdc; -reg [7:0] Counter; - -wire CountEq0; -wire [7:0] CounterPreset; -wire [7:0] TempDivider; - - -assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 -assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period - - -// Counter counts half period -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - Counter[7:0] <= 8'h1; - else - begin - if(CountEq0) - begin - Counter[7:0] <= CounterPreset[7:0]; - end - else - Counter[7:0] <= Counter - 8'h1; - end -end - - -// Mdc is asserted every other half period -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - Mdc <= 1'b0; - else - begin - if(CountEq0) - Mdc <= ~Mdc; - end -end - - -assign CountEq0 = Counter == 8'h0; -assign MdcEn = CountEq0 & ~Mdc; -assign MdcEn_n = CountEq0 & Mdc; - -endmodule - - diff --git a/simple_gemac/miim/eth_miim.v b/simple_gemac/miim/eth_miim.v deleted file mode 100644 index a15c94205..000000000 --- a/simple_gemac/miim/eth_miim.v +++ /dev/null @@ -1,470 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_miim.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_miim.v,v $ -// Revision 1.3 2006/01/19 14:07:53 maverickist -// verification is complete. -// -// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator -// no message -// -// Revision 1.4 2005/08/16 12:07:57 Administrator -// no message -// -// Revision 1.3 2005/05/19 07:04:29 Administrator -// no message -// -// Revision 1.2 2005/04/27 15:58:46 Administrator -// no message -// -// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator -// no message -// -// Revision 1.5 2003/05/16 10:08:27 mohor -// Busy was set 2 cycles too late. Reported by Dennis Scott. -// -// Revision 1.4 2002/08/14 18:32:10 mohor -// - Busy signal was not set on time when scan status operation was performed -// and clock was divided with more than 2. -// - Nvalid remains valid two more clocks (was previously cleared too soon). -// -// Revision 1.3 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.2 2001/10/19 08:43:51 mohor -// eth_timescale.v changed to timescale.v This is done because of the -// simulation of the few cores in a one joined project. -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.2 2001/08/02 09:25:31 mohor -// Unconnected signals are now connected. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// Revision 1.3 2001/06/01 22:28:56 mohor -// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. -// -// - -module eth_miim -( - Clk, - Reset, - Divider, - NoPre, - CtrlData, - Rgad, - Fiad, - WCtrlData, - RStat, - ScanStat, - Mdio, - Mdc, - Busy, - Prsd, - LinkFail, - Nvalid, - WCtrlDataStart, - RStatStart, - UpdateMIIRX_DATAReg -); - -input Clk; // Host Clock -input Reset; // General Reset -input [7:0] Divider; // Divider for the host clock -input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) -input [4:0] Rgad; // Register Address (within the PHY) -input [4:0] Fiad; // PHY Address -input NoPre; // No Preamble (no 32-bit preamble) -input WCtrlData; // Write Control Data operation -input RStat; // Read Status operation -input ScanStat; // Scan Status operation -inout Mdio; // MII Management Data In - -output Mdc; // MII Management Data Clock - -output Busy; // Busy Signal -output LinkFail; // Link Integrity Signal -output Nvalid; // Invalid Status (qualifier for the valid scan result) - -output [15:0] Prsd; // Read Status Data (data read from the PHY) - -output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register -output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register -output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data - -//parameter Tp = 1; - - -reg Nvalid; -reg EndBusy_d; // Pre-end Busy signal -reg EndBusy; // End Busy signal (stops the operation in progress) - -reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle -reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles -reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles -reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) -reg WCtrlDataStart_q; -reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle -reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles - -reg RStat_q1; // Read Status operation delayed 1 Clk cycle -reg RStat_q2; // Read Status operation delayed 2 Clk cycles -reg RStat_q3; // Read Status operation delayed 3 Clk cycles -reg RStatStart; // Start Read Status Command (positive edge detected) -reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle -reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles - -reg ScanStat_q1; // Scan Status operation delayed 1 cycle -reg ScanStat_q2; // Scan Status operation delayed 2 cycles -reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn - -wire WriteDataOp; // Write Data Operation (positive edge detected) -wire ReadStatusOp; // Read Status Operation (positive edge detected) -wire ScanStatusOp; // Scan Status Operation (positive edge detected) -wire StartOp; // Start Operation (start of any of the preceding operations) -wire EndOp; // End of Operation - -reg InProgress; // Operation in progress -reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle -reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles -reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles - -reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) -reg [6:0] BitCounter; // Bit Counter - - -wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. -wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. -wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal - - -wire LatchByte1_d2; -wire LatchByte0_d2; -reg LatchByte1_d; -reg LatchByte0_d; -reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register - -reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data - -wire Mdo; // MII Management Data Output -wire MdoEn; // MII Management Data Output Enable -wire Mdi; - -assign Mdi=Mdio; -assign Mdio=MdoEn?Mdo:1'bz; - - - -// Generation of the EndBusy signal. It is used for ending the MII Management operation. -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - EndBusy_d <= 1'b0; - EndBusy <= 1'b0; - end - else - begin - EndBusy_d <= ~InProgress_q2 & InProgress_q3; - EndBusy <= EndBusy_d; - end -end - - -// Update MII RX_DATA register -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - UpdateMIIRX_DATAReg <= 0; - else - if(EndBusy & ~WCtrlDataStart_q) - UpdateMIIRX_DATAReg <= 1; - else - UpdateMIIRX_DATAReg <= 0; -end - - - -// Generation of the delayed signals used for positive edge triggering. -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - WCtrlData_q1 <= 1'b0; - WCtrlData_q2 <= 1'b0; - WCtrlData_q3 <= 1'b0; - - RStat_q1 <= 1'b0; - RStat_q2 <= 1'b0; - RStat_q3 <= 1'b0; - - ScanStat_q1 <= 1'b0; - ScanStat_q2 <= 1'b0; - SyncStatMdcEn <= 1'b0; - end - else - begin - WCtrlData_q1 <= WCtrlData; - WCtrlData_q2 <= WCtrlData_q1; - WCtrlData_q3 <= WCtrlData_q2; - - RStat_q1 <= RStat; - RStat_q2 <= RStat_q1; - RStat_q3 <= RStat_q2; - - ScanStat_q1 <= ScanStat; - ScanStat_q2 <= ScanStat_q1; - if(MdcEn) - SyncStatMdcEn <= ScanStat_q2; - end -end - - -// Generation of the Start Commands (Write Control Data or Read Status) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - WCtrlDataStart <= 1'b0; - WCtrlDataStart_q <= 1'b0; - RStatStart <= 1'b0; - end - else - begin - if(EndBusy) - begin - WCtrlDataStart <= 1'b0; - RStatStart <= 1'b0; - end - else - begin - if(WCtrlData_q2 & ~WCtrlData_q3) - WCtrlDataStart <= 1'b1; - if(RStat_q2 & ~RStat_q3) - RStatStart <= 1'b1; - WCtrlDataStart_q <= WCtrlDataStart; - end - end -end - - -// Generation of the Nvalid signal (indicates when the status is invalid) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - Nvalid <= 1'b0; - else - begin - if(~InProgress_q2 & InProgress_q3) - begin - Nvalid <= 1'b0; - end - else - begin - if(ScanStat_q2 & ~SyncStatMdcEn) - Nvalid <= 1'b1; - end - end -end - -// Signals used for the generation of the Operation signals (positive edge) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - WCtrlDataStart_q1 <= 1'b0; - WCtrlDataStart_q2 <= 1'b0; - - RStatStart_q1 <= 1'b0; - RStatStart_q2 <= 1'b0; - - InProgress_q1 <= 1'b0; - InProgress_q2 <= 1'b0; - InProgress_q3 <= 1'b0; - - LatchByte0_d <= 1'b0; - LatchByte1_d <= 1'b0; - - LatchByte <= 2'b00; - end - else - begin - if(MdcEn) - begin - WCtrlDataStart_q1 <= WCtrlDataStart; - WCtrlDataStart_q2 <= WCtrlDataStart_q1; - - RStatStart_q1 <= RStatStart; - RStatStart_q2 <= RStatStart_q1; - - LatchByte[0] <= LatchByte0_d; - LatchByte[1] <= LatchByte1_d; - - LatchByte0_d <= LatchByte0_d2; - LatchByte1_d <= LatchByte1_d2; - - InProgress_q1 <= InProgress; - InProgress_q2 <= InProgress_q1; - InProgress_q3 <= InProgress_q2; - end - end -end - - -// Generation of the Operation signals -assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; -assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; -assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; -assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; - -// Busy -reg Busy; -always @ (posedge Clk or posedge Reset) - if (Reset) - Busy <=0; - else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid) - Busy <=1; - else - Busy <=0; - -//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; - - -// Generation of the InProgress signal (indicates when an operation is in progress) -// Generation of the WriteOp signal (indicates when a write is in progress) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - InProgress <= 1'b0; - WriteOp <= 1'b0; - end - else - begin - if(MdcEn) - begin - if(StartOp) - begin - if(~InProgress) - WriteOp <= WriteDataOp; - InProgress <= 1'b1; - end - else - begin - if(EndOp) - begin - InProgress <= 1'b0; - WriteOp <= 1'b0; - end - end - end - end -end - - - -// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - BitCounter[6:0] <= 7'h0; - else - begin - if(MdcEn) - begin - if(InProgress) - begin - if(NoPre & ( BitCounter == 7'h0 )) - BitCounter[6:0] <= 7'h21; - else - BitCounter[6:0] <= BitCounter[6:0] + 1'b1; - end - else - BitCounter[6:0] <= 7'h0; - end - end -end - - -// Operation ends when the Bit Counter reaches 63 -assign EndOp = BitCounter==63; - -assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); -assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); -assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); -assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); - - -// Latch Byte selects which part of Read Status Data is updated from the shift register -assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; -assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; - -wire MdcEn_n; - -// Connecting the Clock Generator Module -eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) - ); - -// Connecting the Shift Register Module -eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), - .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), - .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) - ); - -// Connecting the Output Control Module -eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), - .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), - .Mdo(Mdo), .MdoEn(MdoEn) - ); - -endmodule diff --git a/simple_gemac/miim/eth_outputcontrol.v b/simple_gemac/miim/eth_outputcontrol.v deleted file mode 100644 index 3df6c560a..000000000 --- a/simple_gemac/miim/eth_outputcontrol.v +++ /dev/null @@ -1,158 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_outputcontrol.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_outputcontrol.v,v $ -// Revision 1.2 2005/12/13 12:54:49 maverickist -// first simulation passed -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -// Revision 1.2 2005/04/27 15:58:46 Administrator -// no message -// -// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator -// no message -// -// Revision 1.4 2002/07/09 20:11:59 mohor -// Comment removed. -// -// Revision 1.3 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.2 2001/10/19 08:43:51 mohor -// eth_timescale.v changed to timescale.v This is done because of the -// simulation of the few cores in a one joined project. -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// Revision 1.3 2001/06/01 22:28:56 mohor -// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. -// -// - -module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); - -input Clk; // Host Clock -input Reset; // General Reset -input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) -input NoPre; // No Preamble (no 32-bit preamble) -input InProgress; // Operation in progress -input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal -input [6:0] BitCounter; // Bit Counter -input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. - -output Mdo; // MII Management Data Output -output MdoEn; // MII Management Data Output Enable - -wire SerialEn; - -reg MdoEn_2d; -reg MdoEn_d; -reg MdoEn; - -reg Mdo_2d; -reg Mdo_d; -reg Mdo; // MII Management Data Output - - - -// Generation of the Serial Enable signal (enables the serialization of the data) -assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) - | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); - - -// Generation of the MdoEn signal -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - MdoEn_2d <= 1'b0; - MdoEn_d <= 1'b0; - MdoEn <= 1'b0; - end - else - begin - if(MdcEn_n) - begin - MdoEn_2d <= SerialEn | InProgress & BitCounter<32; - MdoEn_d <= MdoEn_2d; - MdoEn <= MdoEn_d; - end - end -end - - -// Generation of the Mdo signal. -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - Mdo_2d <= 1'b0; - Mdo_d <= 1'b0; - Mdo <= 1'b0; - end - else - begin - if(MdcEn_n) - begin - Mdo_2d <= ~SerialEn & BitCounter<32; - Mdo_d <= ShiftedBit | Mdo_2d; - Mdo <= Mdo_d; - end - end -end - - - -endmodule diff --git a/simple_gemac/miim/eth_shiftreg.v b/simple_gemac/miim/eth_shiftreg.v deleted file mode 100644 index 0b97bb7bc..000000000 --- a/simple_gemac/miim/eth_shiftreg.v +++ /dev/null @@ -1,159 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_shiftreg.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_shiftreg.v,v $ -// Revision 1.2 2005/12/13 12:54:49 maverickist -// first simulation passed -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -// Revision 1.2 2005/04/27 15:58:47 Administrator -// no message -// -// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator -// no message -// -// Revision 1.5 2002/08/14 18:16:59 mohor -// LinkFail signal was not latching appropriate bit. -// -// Revision 1.4 2002/03/02 21:06:01 mohor -// LinkFail signal was not latching appropriate bit. -// -// Revision 1.3 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.2 2001/10/19 08:43:51 mohor -// eth_timescale.v changed to timescale.v This is done because of the -// simulation of the few cores in a one joined project. -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// Revision 1.3 2001/06/01 22:28:56 mohor -// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. -// -// - -module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, - LatchByte, ShiftedBit, Prsd, LinkFail); - - -input Clk; // Input clock (Host clock) -input Reset; // Reset signal -input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. -input Mdi; // MII input data -input [4:0] Fiad; // PHY address -input [4:0] Rgad; // Register address (within the selected PHY) -input [15:0]CtrlData; // Control data (data to be written to the PHY) -input WriteOp; // The current operation is a PHY register write operation -input [3:0] ByteSelect; // Byte select -input [1:0] LatchByte; // Byte select for latching (read operation) - -output ShiftedBit; // Bit shifted out of the shift register -output[15:0]Prsd; // Read Status Data (data read from the PHY) -output LinkFail; // Link Integrity Signal - -reg [7:0] ShiftReg; // Shift register for shifting the data in and out -reg [15:0]Prsd; -reg LinkFail; - - - - -// ShiftReg[7:0] :: Shift Register Data -always @ (posedge Clk or posedge Reset) -begin - if(Reset) - begin - ShiftReg[7:0] <= 8'h0; - Prsd[15:0] <= 16'h0; - LinkFail <= 1'b0; - end - else - begin - if(MdcEn_n) - begin - if(|ByteSelect) - begin - case (ByteSelect[3:0]) - 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; - 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10}; - 4'h4 : ShiftReg[7:0] <= CtrlData[15:8]; - 4'h8 : ShiftReg[7:0] <= CtrlData[7:0]; - default : ShiftReg[7:0] <= 8'h0; - endcase - end - else - begin - ShiftReg[7:0] <= {ShiftReg[6:0], Mdi}; - if(LatchByte[0]) - begin - Prsd[7:0] <= {ShiftReg[6:0], Mdi}; - if(Rgad == 5'h01) - LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet - end - else - begin - if(LatchByte[1]) - Prsd[15:8] <= {ShiftReg[6:0], Mdi}; - end - end - end - end -end - - -assign ShiftedBit = ShiftReg[7]; - - -endmodule diff --git a/simple_gemac/rxmac_to_ll8.v b/simple_gemac/rxmac_to_ll8.v deleted file mode 100644 index 5ec233d95..000000000 --- a/simple_gemac/rxmac_to_ll8.v +++ /dev/null @@ -1,54 +0,0 @@ - -module rxmac_to_ll8 - (input clk, input reset, input clear, - input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack, - output [7:0] ll_data, output ll_sof, output ll_eof, output ll_error, output ll_src_rdy, input ll_dst_rdy ); - - reg [2:0] xfer_state; - - localparam XFER_IDLE = 0; - localparam XFER_ACTIVE = 1; - localparam XFER_ERROR = 2; - localparam XFER_ERROR2 = 3; - localparam XFER_OVERRUN = 4; - localparam XFER_OVERRUN2 = 5; - - assign ll_data = rx_data; - assign ll_src_rdy = ((rx_valid & (xfer_state != XFER_OVERRUN2) ) - | (xfer_state == XFER_ERROR) - | (xfer_state == XFER_OVERRUN)); - assign ll_sof = ((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN)); - assign ll_eof = (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN)); - assign ll_error = (xfer_state == XFER_ERROR)|(xfer_state==XFER_OVERRUN); - - always @(posedge clk) - if(reset | clear) - xfer_state <= XFER_IDLE; - else - case(xfer_state) - XFER_IDLE : - if(rx_valid) - xfer_state <= XFER_ACTIVE; - XFER_ACTIVE : - if(rx_error) - xfer_state <= XFER_ERROR; - else if(~rx_valid) - xfer_state <= XFER_IDLE; - else if(~ll_dst_rdy) - xfer_state <= XFER_OVERRUN; - XFER_ERROR : - if(ll_dst_rdy) - xfer_state <= XFER_ERROR2; - XFER_ERROR2 : - if(~rx_error) - xfer_state <= XFER_IDLE; - XFER_OVERRUN : - if(ll_dst_rdy) - xfer_state <= XFER_OVERRUN2; - XFER_OVERRUN2 : - if(~rx_valid) - xfer_state <= XFER_IDLE; - endcase // case (xfer_state) - - -endmodule // rxmac_to_ll8 diff --git a/simple_gemac/simple_gemac.v b/simple_gemac/simple_gemac.v deleted file mode 100644 index e7f327358..000000000 --- a/simple_gemac/simple_gemac.v +++ /dev/null @@ -1,61 +0,0 @@ - -module simple_gemac - (input clk125, input reset, - // GMII - output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, - input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, - - // Flow Control Interface - input pause_req, input [15:0] pause_time_req, input pause_respect_en, - - // Settings - input [47:0] ucast_addr, input [47:0] mcast_addr, - input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all, - - // RX Client Interface - output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error, output rx_ack, - - // TX Client Interface - output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack - ); - - localparam SGE_IFG = 8'd12; // 12 should be the absolute minimum - - wire rst_rxclk, rst_txclk; - reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk)); - reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk)); - - wire [15:0] pause_quanta_rcvd; - wire pause_rcvd, pause_apply, paused; - - simple_gemac_tx simple_gemac_tx - (.clk125(clk125),.reset(rst_txclk), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack), - .ifg(SGE_IFG), .mac_addr(ucast_addr), - .pause_req(pause_req), .pause_time(pause_time_req), // We request flow control - .pause_apply(pause_apply), .paused(paused) // We respect flow control - ); - - simple_gemac_rx simple_gemac_rx - (.reset(rst_rxclk), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .rx_clk(rx_clk), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), - .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), - .pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd) - ); - - flow_ctrl_tx flow_ctrl_tx - (.rst(rst_txclk), .tx_clk(tx_clk), - .tx_pause_en(pause_respect_en), - .pause_quanta(pause_quanta_rcvd), // 16 bit value - .pause_quanta_val(pause_rcvd), - .pause_apply(pause_apply), - .paused(paused) - ); - -endmodule // simple_gemac diff --git a/simple_gemac/simple_gemac_rx.v b/simple_gemac/simple_gemac_rx.v deleted file mode 100644 index 45ddd6dfa..000000000 --- a/simple_gemac/simple_gemac_rx.v +++ /dev/null @@ -1,174 +0,0 @@ - - -module simple_gemac_rx - (input reset, - input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, - output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack, - input [47:0] ucast_addr, input [47:0] mcast_addr, - input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all, - output reg [15:0] pause_quanta_rcvd, output pause_rcvd ); - - localparam RX_IDLE = 0; - localparam RX_PREAMBLE = 1; - localparam RX_FRAME = 2; - localparam RX_GOODFRAME = 3; - localparam RX_DO_PAUSE = 4; - localparam RX_ERROR = 5; - localparam RX_DROP = 6; - - localparam RX_PAUSE = 16; - localparam RX_PAUSE_CHK88 = RX_PAUSE + 5; - localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1; - localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1; - localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1; - localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1; - localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1; - localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1; - - reg [7:0] rxd_d1; - reg rx_dv_d1, rx_er_d1; - assign rx_clk = GMII_RX_CLK; - - always @(posedge rx_clk) - begin - rx_dv_d1 <= GMII_RX_DV; - rx_er_d1 <= GMII_RX_ER; - rxd_d1 <= GMII_RXD; - end - - reg [7:0] rx_state; - wire [7:0] rxd_del; - wire rx_dv_del, rx_er_del; - reg go_filt; - - wire match_crc; - wire clear_crc = rx_state == RX_IDLE; - wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1; - - localparam DELAY = 6; - delay_line #(.WIDTH(10)) rx_delay - (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del})); - - always @(posedge rx_clk) - if(reset) - rx_ack <= 0; - else - rx_ack <= (rx_state == RX_GOODFRAME); - - wire is_ucast, is_bcast, is_mcast, is_pause; - wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | - (pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all; - - assign rx_data = rxd_del; - assign rx_error = (rx_state == RX_ERROR); - - always @(posedge rx_clk) - if(reset) - rx_valid <= 0; - else if(keep_packet) - rx_valid <= 1; - else if((rx_state == RX_IDLE)|(rx_state == RX_ERROR)) - rx_valid <= 0; - - address_filter af_ucast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .address(ucast_addr), .match(is_ucast), .done()); - address_filter af_mcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .address(mcast_addr), .match(is_mcast), .done()); - address_filter af_bcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done()); - address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), - .address(48'h0180_c200_0001), .match(is_pause), .done()); - - always @(posedge rx_clk) - go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5); - - reg [15:0] pkt_len_ctr; - always @(posedge rx_clk) - if(reset |(rx_state == RX_IDLE)) - pkt_len_ctr <= 0; - else - pkt_len_ctr <= pkt_len_ctr + 1; - - localparam MIN_PAUSE_LEN = 71; // 6 - wire pkt_long_enough = (pkt_len_ctr >= MIN_PAUSE_LEN); - always @(posedge rx_clk) - if(reset) - rx_state <= RX_IDLE; - else - if(rx_er_d1) // | (~pkt_long_enough & ~rx_dv_d1) & (rx_state != RX_IDLE)) - rx_state <= RX_ERROR; - else - case(rx_state) - RX_IDLE : - if(rx_dv_d1) - if(rxd_d1 == 8'h55) - rx_state <= RX_PREAMBLE; - else - rx_state <= RX_ERROR; - RX_PREAMBLE : - if(~rx_dv_d1) - rx_state <= RX_ERROR; - else if(rxd_d1 == 8'hD5) - rx_state <= RX_FRAME; - else if(rxd_d1 != 8'h55) - rx_state <= RX_ERROR; - RX_FRAME : - if(is_pause) - rx_state <= RX_PAUSE; - else if(~rx_dv_d1) - if(match_crc) - rx_state <= RX_GOODFRAME; - else - rx_state <= RX_ERROR; - RX_PAUSE_CHK88 : - if(rxd_d1 != 8'h88) - rx_state <= RX_DROP; - else - rx_state <= RX_PAUSE_CHK08; - RX_PAUSE_CHK08 : - if(rxd_d1 != 8'h08) - rx_state <= RX_DROP; - else - rx_state <= RX_PAUSE_CHK00; - RX_PAUSE_CHK00 : - if(rxd_d1 != 8'h00) - rx_state <= RX_DROP; - else - rx_state <= RX_PAUSE_CHK01; - RX_PAUSE_CHK01 : - if(rxd_d1 != 8'h01) - rx_state <= RX_DROP; - else - rx_state <= RX_PAUSE_STORE_MSB; - RX_PAUSE_WAIT_CRC : - if(pkt_long_enough) - if(match_crc) - rx_state <= RX_DO_PAUSE; - else - rx_state <= RX_DROP; - RX_DO_PAUSE : - rx_state <= RX_IDLE; - RX_GOODFRAME : - rx_state <= RX_IDLE; - RX_DROP, RX_ERROR : - if(~rx_dv_d1) - rx_state <= RX_IDLE; - default - rx_state <= rx_state + 1; - endcase // case (rx_state) - - assign pause_rcvd = (rx_state == RX_DO_PAUSE); - crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc), - .data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc)); - - always @(posedge rx_clk) - if(reset) - pause_quanta_rcvd <= 0; - else if(rx_state == RX_PAUSE_STORE_MSB) - pause_quanta_rcvd[15:8] <= rxd_d1; - else if(rx_state == RX_PAUSE_STORE_LSB) - pause_quanta_rcvd[7:0] <= rxd_d1; - - assign rx_clk = GMII_RX_CLK; - -endmodule // simple_gemac_rx diff --git a/simple_gemac/simple_gemac_tb.v b/simple_gemac/simple_gemac_tb.v deleted file mode 100644 index 6091751a7..000000000 --- a/simple_gemac/simple_gemac_tb.v +++ /dev/null @@ -1,200 +0,0 @@ - - -module simple_gemac_tb; -`include "eth_tasks.v" - - reg clk = 0; - reg reset = 1; - - initial #1000 reset = 0; - always #50 clk = ~clk; - - wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; - wire [7:0] GMII_RXD, GMII_TXD; - - wire rx_valid, rx_error, rx_ack; - wire tx_ack, tx_valid, tx_error; - - wire [7:0] rx_data, tx_data; - - reg [15:0] pause_time; - reg pause_req = 0; - - wire GMII_RX_CLK = GMII_GTX_CLK; - - reg [7:0] FORCE_DAT_ERR = 0; - reg FORCE_ERR = 0; - - // Loopback - assign GMII_RX_DV = GMII_TX_EN; - assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; - assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; - - wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6; - wire [47:0] mcast_addr = 0; - wire pass_ucast =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0; - - simple_gemac simple_gemac - (.clk125(clk), .reset(reset), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .pause_en(1), - .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), - .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), - .rx_clk(rx_clk), .rx_data(rx_data), - .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .tx_clk(tx_clk), .tx_data(tx_data), - .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack) - ); - - wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2; - reg rx_ll_dst_rdy2 = 1; - wire [7:0] rx_ll_data, rx_ll_data2; - wire rx_ll_error, rx_ll_error2; - - rxmac_to_ll8 rx_adapt - (.clk(clk), .reset(reset), .clear(0), - .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), - .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); - - ll8_shortfifo rx_sfifo - (.clk(clk), .reset(reset), .clear(0), - .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), - .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); - - wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - reg tx_ll_sof2=0, tx_ll_eof2=0; - reg tx_ll_src_rdy2 = 0; - wire tx_ll_dst_rdy2; - wire [7:0] tx_ll_data; - reg [7:0] tx_ll_data2 = 0; - wire tx_ll_error; - wire tx_ll_error2 = 0; - - ll8_shortfifo tx_sfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), - .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), - .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), - .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); - - ll8_to_txmac ll8_to_txmac - (.clk(clk), .reset(reset), .clear(clear), - .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), - .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), - .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - - initial $dumpfile("simple_gemac_tb.vcd"); - initial $dumpvars(0,simple_gemac_tb); - - integer i; - reg [7:0] pkt_rom[0:65535]; - reg [1023:0] ROMFile; - - initial - for (i=0;i<65536;i=i+1) - pkt_rom[i] <= 8'h0; - - initial - begin - @(negedge reset); - repeat (10) - @(posedge clk); - SendFlowCtrl(16'h0007); // Send flow control - @(posedge clk); - #30000; - @(posedge clk); - SendFlowCtrl(16'h0009); // Increas flow control before it expires - #10000; - @(posedge clk); - SendFlowCtrl(16'h0000); // Cancel flow control before it expires - @(posedge clk); - - SendPacket_to_ll8(8'hAA,10); // This packet gets dropped by the filters - repeat (10) - @(posedge clk); - - SendPacketFromFile_ll8(60,0,0); // The rest are valid packets - repeat (10) - @(posedge clk); - - SendPacketFromFile_ll8(61,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_ll8(62,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_ll8(63,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(64,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_ll8(59,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(58,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(100,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(200,150,30); // waiting 14 empties the fifo, 15 underruns - repeat (1) - @(posedge clk); - SendPacketFromFile_ll8(100,0,30); - #10000 $finish; - end - - // Force a CRC error - initial - begin - #90000; - @(posedge clk); - FORCE_DAT_ERR <= 8'h10; - @(posedge clk); - FORCE_DAT_ERR <= 8'h00; - end - - // Force an RX_ER error (i.e. link loss) - initial - begin - #116000; - @(posedge clk); - FORCE_ERR <= 1; - @(posedge clk); - FORCE_ERR <= 0; - end - - // Cause receive fifo to fill, causing an RX overrun - initial - begin - #126000; - @(posedge clk); - rx_ll_dst_rdy2 <= 0; - repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows - @(posedge clk); - rx_ll_dst_rdy2 <= 1; - end - - // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun - // Still need to test: CRC errors on Pause Frames - - always @(posedge clk) - if(rx_ll_src_rdy2 & rx_ll_dst_rdy2) - begin - if(rx_ll_sof2 & ~rx_ll_eof2) - $display("RX-PKT-START %d",$time); - $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2); - if(rx_ll_eof2 & ~rx_ll_sof2) - $display("RX-PKT-END %d",$time); - end - -endmodule // simple_gemac_tb diff --git a/simple_gemac/simple_gemac_tx.v b/simple_gemac/simple_gemac_tx.v deleted file mode 100644 index dd870d04d..000000000 --- a/simple_gemac/simple_gemac_tx.v +++ /dev/null @@ -1,254 +0,0 @@ - -module simple_gemac_tx - (input clk125, input reset, - output GMII_GTX_CLK, output reg GMII_TX_EN, output reg GMII_TX_ER, output reg [7:0] GMII_TXD, - output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack, - input [7:0] ifg, input [47:0] mac_addr, - input pause_req, input [15:0] pause_time, - input pause_apply, output reg paused - ); - - reg tx_en_pre, tx_er_pre; - reg [7:0] txd_pre; - - assign GMII_GTX_CLK = clk125; - assign tx_clk = clk125; - - reg [7:0] tx_state; - reg [7:0] ifg_ctr; - reg [15:0] frame_len_ctr; - reg [7:0] pause_ctr, pause_dat; - - wire in_ifg = (ifg_ctr != 0); - - wire [31:0] crc_out; - - localparam TX_IDLE = 0; - localparam TX_PREAMBLE = 1; - localparam TX_SOF_DEL = TX_PREAMBLE + 7; - localparam TX_FIRSTBYTE = TX_SOF_DEL + 1; - localparam TX_IN_FRAME = TX_FIRSTBYTE + 1; - localparam TX_IN_FRAME_2 = TX_IN_FRAME + 1; - localparam TX_PAD = TX_IN_FRAME_2 + 1; - localparam TX_CRC_0 = 16; - localparam TX_CRC_1 = TX_CRC_0 + 1; - localparam TX_CRC_2 = TX_CRC_0 + 2; - localparam TX_CRC_3 = TX_CRC_0 + 3; - localparam TX_ERROR = 32; - localparam TX_PAUSE = 55; - localparam TX_PAUSE_SOF = TX_PAUSE + 7; - localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1; - localparam TX_PAUSE_END = TX_PAUSE_SOF + 18; - - localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes preamble but not CRC - localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we want to handle? - always @(posedge tx_clk) - if(reset |(tx_state == TX_IDLE)) - frame_len_ctr <= 0; - else - frame_len_ctr <= frame_len_ctr + 1; - - reg send_pause; - reg [15:0] pause_time_held; - - always @(posedge tx_clk) - if(reset) - send_pause <= 0; - else if(pause_req) - send_pause <= 1; - else if(tx_state == TX_PAUSE) - send_pause <= 0; - - always @(posedge tx_clk) - if(pause_req) - pause_time_held <= pause_time; - - always @(posedge tx_clk) - if(reset) - tx_state <= TX_IDLE; - else - case(tx_state) - TX_IDLE : - if(~in_ifg) - if(send_pause) - tx_state <= TX_PAUSE; - else if(tx_valid & ~pause_apply) - tx_state <= TX_PREAMBLE; - TX_FIRSTBYTE : - if(tx_error) - tx_state <= TX_ERROR; // underrun - else if(~tx_valid) - tx_state <= TX_PAD; - else - tx_state <= TX_IN_FRAME; - TX_IN_FRAME : - if(tx_error) - tx_state <= TX_ERROR; // underrun - else if(~tx_valid) - tx_state <= TX_PAD; - else if(frame_len_ctr == MIN_FRAME_LEN - 1) - tx_state <= TX_IN_FRAME_2; - TX_IN_FRAME_2 : - if(tx_error) - tx_state <= TX_ERROR; // underrun - else if(~tx_valid) - tx_state <= TX_CRC_0; - TX_PAD : - if(frame_len_ctr == MIN_FRAME_LEN) - tx_state <= TX_CRC_0; - TX_CRC_3 : - tx_state <= TX_IDLE; - TX_ERROR : - tx_state <= TX_IDLE; - TX_PAUSE_END : - tx_state <= TX_PAD; - default : - tx_state <= tx_state + 1; - endcase // case (tx_state) - - always @(posedge tx_clk) - if(reset) - begin - tx_en_pre <= 0; - tx_er_pre <= 0; - txd_pre <= 0; - end - else - casex(tx_state) - TX_IDLE : - begin - tx_en_pre <= 0; - tx_er_pre <= 0; - txd_pre <= 0; - end - TX_PREAMBLE, TX_PAUSE : - begin - txd_pre <= 8'h55; - tx_en_pre <= 1; - end - TX_SOF_DEL, TX_PAUSE_SOF : - txd_pre <= 8'hD5; - TX_FIRSTBYTE, TX_IN_FRAME, TX_IN_FRAME_2 : - txd_pre <= tx_valid ? tx_data : 0; - TX_ERROR : - begin - tx_er_pre <= 1; - txd_pre <= 0; - end - TX_CRC_3 : - tx_en_pre <= 0; - TX_PAD : - txd_pre <= 0; - TX_PAUSE_FIRST, 8'b01xx_xxxx : // In Pause Frame - txd_pre <= pause_dat; - endcase // case (tx_state) - - localparam SGE_FLOW_CTRL_ADDR = 48'h01_80_C2_00_00_01; - always @(posedge tx_clk) - case(tx_state) - TX_PAUSE_SOF : - pause_dat <= SGE_FLOW_CTRL_ADDR[47:40]; // Note everything must be 1 cycle early - TX_PAUSE_SOF + 1: - pause_dat <= SGE_FLOW_CTRL_ADDR[39:32]; - TX_PAUSE_SOF + 2: - pause_dat <= SGE_FLOW_CTRL_ADDR[31:24]; - TX_PAUSE_SOF + 3: - pause_dat <= SGE_FLOW_CTRL_ADDR[23:16]; - TX_PAUSE_SOF + 4: - pause_dat <= SGE_FLOW_CTRL_ADDR[15:8]; - TX_PAUSE_SOF + 5: - pause_dat <= SGE_FLOW_CTRL_ADDR[7:0]; - TX_PAUSE_SOF + 6: - pause_dat <= mac_addr[47:40]; - TX_PAUSE_SOF + 7: - pause_dat <= mac_addr[39:32]; - TX_PAUSE_SOF + 8: - pause_dat <= mac_addr[31:24]; - TX_PAUSE_SOF + 9: - pause_dat <= mac_addr[23:16]; - TX_PAUSE_SOF + 10: - pause_dat <= mac_addr[15:8]; - TX_PAUSE_SOF + 11: - pause_dat <= mac_addr[7:0]; - TX_PAUSE_SOF + 12: - pause_dat <= 8'h88; // Type = 8808 = MAC ctrl frame - TX_PAUSE_SOF + 13: - pause_dat <= 8'h08; - TX_PAUSE_SOF + 14: - pause_dat <= 8'h00; // Opcode = 0001 = PAUSE - TX_PAUSE_SOF + 15: - pause_dat <= 8'h01; - TX_PAUSE_SOF + 16: - pause_dat <= pause_time_held[15:8]; - TX_PAUSE_SOF + 17: - pause_dat <= pause_time_held[7:0]; - endcase // case (tx_state) - - wire start_ifg = (tx_state == TX_CRC_3); - always @(posedge tx_clk) - if(reset) - ifg_ctr <= 100; - else if(start_ifg) - ifg_ctr <= ifg; - else if(ifg_ctr != 0) - ifg_ctr <= ifg_ctr - 1; - - wire clear_crc = (tx_state == TX_IDLE); - - wire calc_crc = - (tx_state==TX_IN_FRAME) | - (tx_state==TX_IN_FRAME_2) | - (tx_state==TX_PAD) | - (tx_state[6]); - - crc crc(.clk(tx_clk), .reset(reset), .clear(clear_crc), - .data(txd_pre), .calc(calc_crc), .crc_out(crc_out)); - - assign tx_ack = (tx_state == TX_FIRSTBYTE); - - always @(posedge tx_clk) - begin - GMII_TX_EN <= tx_en_pre; - GMII_TX_ER <= tx_er_pre; - case(tx_state) - TX_CRC_0 : - GMII_TXD <= crc_out[31:24]; - TX_CRC_1 : - GMII_TXD <= crc_out[23:16]; - TX_CRC_2 : - GMII_TXD <= crc_out[15:8]; - TX_CRC_3 : - GMII_TXD <= crc_out[7:0]; - default : - GMII_TXD <= txd_pre; - endcase // case (tx_state) - end - - // report that we are paused only when we get back to IDLE - always @(posedge tx_clk) - if(reset) - paused <= 0; - else if(~pause_apply) - paused <= 0; - else if(tx_state == TX_IDLE) - paused <= 1; - -endmodule // simple_gemac_tx - -// Testing code -/* - reg [7:0] crc_ctr; - reg calc_crc_d1; - always @(posedge tx_clk) - calc_crc_d1 <= calc_crc; - - always @(posedge tx_clk) - if(reset) - crc_ctr <= 0; - else if(calc_crc) - crc_ctr <= crc_ctr+1; - else if(calc_crc_d1) - $display("CRC COUNT = %d",crc_ctr); - else - crc_ctr <= 0; -*/ diff --git a/simple_gemac/simple_gemac_wb.v b/simple_gemac/simple_gemac_wb.v deleted file mode 100644 index 6df277e3e..000000000 --- a/simple_gemac/simple_gemac_wb.v +++ /dev/null @@ -1,161 +0,0 @@ - -module wb_reg - #(parameter ADDR=0, - parameter DEFAULT=0) - (input clk, input rst, - input [5:0] adr, input wr_acc, - input [31:0] dat_i, output reg [31:0] dat_o); - - always @(posedge clk) - if(rst) - dat_o <= DEFAULT; - else if(wr_acc & (adr == ADDR)) - dat_o <= dat_i; - -endmodule // wb_reg - - - -module simple_gemac_wb - (input wb_clk, input wb_rst, - input wb_cyc, input wb_stb, output reg wb_ack, input wb_we, - input [7:0] wb_adr, input [31:0] wb_dat_i, output reg [31:0] wb_dat_o, - - inout mdio, output mdc, - output [47:0] ucast_addr, output [47:0] mcast_addr, - output pass_ucast, output pass_mcast, output pass_bcast, - output pass_pause, output pass_all, - output pause_respect_en, output pause_request_en, - output [15:0] pause_time, output [15:0] pause_thresh ); - - wire acc = wb_cyc & wb_stb; - wire wr_acc = wb_cyc & wb_stb & wb_we; - wire rd_acc = wb_cyc & wb_stb & ~wb_we; - - always @(posedge wb_clk) - if(wb_rst) - wb_ack <= 0; - else - wb_ack <= acc & ~wb_ack; - - wire [6:0] misc_settings; - assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings; - - wb_reg #(.ADDR(0),.DEFAULT(7'b0111001)) - wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(misc_settings) ); - wb_reg #(.ADDR(1),.DEFAULT(0)) - wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) ); - wb_reg #(.ADDR(2),.DEFAULT(0)) - wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) ); - wb_reg #(.ADDR(3),.DEFAULT(0)) - wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) ); - wb_reg #(.ADDR(4),.DEFAULT(0)) - wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) ); - - //MII to CPU - wire [7:0] Divider; // Divider for the host clock - wire [15:0] CtrlData; // Control Data (to be written to the PHY reg.) - wire [4:0] Rgad; // Register Address (within the PHY) - wire [4:0] Fiad; // PHY Address - wire NoPre; // No Preamble (no 32-bit preamble) - wire WCtrlData; // Write Control Data operation - wire RStat; // Read Status operation - wire ScanStat; // Scan Status operation - wire Busy; // Busy Signal - wire LinkFail; // Link Integrity Signal - wire Nvalid; // Invalid Status (qualifier for the valid scan result) - wire [15:0] Prsd; // Read Status Data (data read from the PHY) - wire WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register - wire RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register - wire UpdateMIIRX_DATAReg; // Updates MII RX_DATA register with read data - - // registers for controlling the MII interface - reg [2:0] MIICOMMAND; - wire [12:0] MIIADDRESS; - reg [15:0] MIIRX_DATA; - wire [2:0] MIISTATUS; - - wb_reg #(.ADDR(5),.DEFAULT(0)) - wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) ); - - wb_reg #(.ADDR(6),.DEFAULT(0)) - wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(MIIADDRESS) ); - - wb_reg #(.ADDR(7),.DEFAULT(0)) - wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(CtrlData) ); - - // MIICOMMAND register - needs special treatment because of auto-resetting bits - always @ (posedge wb_clk) - if (wb_rst) - MIICOMMAND <= 0; - else - if (wr_acc & (wb_adr[7:2] == 6'd8)) - MIICOMMAND <= wb_dat_i; - else - begin - if ( WCtrlDataStart ) - MIICOMMAND[2] <= 0; - if ( RStatStart ) - MIICOMMAND[1] <= 0; - end - - // MIIRX_DATA register - always @(posedge wb_clk) - if (wb_rst) - MIIRX_DATA <= 0; - else - if (UpdateMIIRX_DATAReg ) - MIIRX_DATA <= Prsd; - - // MIICOMMAND - assign WCtrlData = MIICOMMAND[2]; - assign RStat = MIICOMMAND[1]; - assign ScanStat = MIICOMMAND[0]; - // MIIADDRESS - assign Rgad = MIIADDRESS[12:8]; - assign Fiad = MIIADDRESS[4:0]; - // MIISTATUS - assign MIISTATUS[2:0] = { Nvalid, Busy, LinkFail }; - - eth_miim eth_miim - (.Clk(wb_clk), .Reset(wb_rst), - .Divider(Divider), .NoPre(NoPre), .CtrlData(CtrlData), .Rgad(Rgad), .Fiad(Fiad), - .WCtrlData(WCtrlData), .RStat(RStat), .ScanStat(ScanStat), .Mdio(mdio), .Mdc(mdc), - .Busy(Busy), .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(Nvalid), - .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), - .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) ); - - wb_reg #(.ADDR(11),.DEFAULT(0)) - wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(pause_time) ); - - wb_reg #(.ADDR(12),.DEFAULT(0)) - wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), - .dat_i(wb_dat_i), .dat_o(pause_thresh) ); - - always @(posedge wb_clk) - case(wb_adr[7:2]) - 0 : wb_dat_o <= misc_settings; - 1 : wb_dat_o <= ucast_addr[47:32]; - 2 : wb_dat_o <= ucast_addr[31:0]; - 3 : wb_dat_o <= mcast_addr[47:32]; - 4 : wb_dat_o <= mcast_addr[31:0]; - 5 : wb_dat_o <= {NoPre,Divider}; - 6 : wb_dat_o <= MIIADDRESS; - 7 : wb_dat_o <= CtrlData; - 8 : wb_dat_o <= MIICOMMAND; - 9 : wb_dat_o <= MIISTATUS; - 10: wb_dat_o <= MIIRX_DATA; - 11: wb_dat_o <= pause_time; - 12: wb_dat_o <= pause_thresh; - endcase // case (wb_adr[7:2]) - -endmodule // simple_gemac_wb diff --git a/simple_gemac/simple_gemac_wrapper.build b/simple_gemac/simple_gemac_wrapper.build deleted file mode 100755 index 30f65ab17..000000000 --- a/simple_gemac/simple_gemac_wrapper.build +++ /dev/null @@ -1 +0,0 @@ -iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v deleted file mode 100644 index efcf89276..000000000 --- a/simple_gemac/simple_gemac_wrapper.v +++ /dev/null @@ -1,165 +0,0 @@ - -module simple_gemac_wrapper - #(parameter RXFIFOSIZE=9, - parameter TXFIFOSIZE=6) - (input clk125, input reset, - // GMII - output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, - input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, - - // Client FIFO Interfaces - input sys_clk, - output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, - input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, - - // Wishbone Interface - input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, - input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, - - // MIIM - inout mdio, output mdc, - output [31:0] debug); - - wire clear = 0; - wire [7:0] rx_data, tx_data; - wire tx_clk, tx_valid, tx_error, tx_ack; - wire rx_clk, rx_valid, rx_error, rx_ack; - - wire [47:0] ucast_addr, mcast_addr; - wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all; - wire pause_req; - wire pause_request_en, pause_respect_en; - wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; - - wire tx_reset, rx_reset; - reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset)); - reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset)); - - simple_gemac simple_gemac - (.clk125(clk125), .reset(reset), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time_req(pause_time_req), - .pause_respect_en(pause_respect_en), - .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), - .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), - .rx_clk(rx_clk), .rx_data(rx_data), - .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .tx_clk(tx_clk), .tx_data(tx_data), - .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack) - ); - - simple_gemac_wb simple_gemac_wb - (.wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we), - .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), - .mdio(mdio), .mdc(mdc), - .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), - .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), - .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en), - .pause_time(pause_time), .pause_thresh(pause_thresh) ); - - // RX FIFO Chain - wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; - wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; - - wire [7:0] rx_ll_data, rx_ll_data2; - - wire [35:0] rx_f36_data_int1; - wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; - - rxmac_to_ll8 rx_adapt - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof - .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); - - ll8_shortfifo rx_sfifo - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), - .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); - - assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; - assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2; - assign rx_ll_sof2_n = ~rx_ll_sof2; - assign rx_ll_eof2_n = ~rx_ll_eof2; - - ll8_to_fifo36 ll8_to_fifo36 - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n), - .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), - .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1)); - - fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo - (.wclk(rx_clk), .datain(rx_f36_data_int1), - .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space), - .rclk(sys_clk), .dataout(rx_f36_data), - .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset)); - - // TX FIFO Chain - wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; - wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n; - wire [7:0] tx_ll_data, tx_ll_data2; - wire [35:0] tx_f36_data_int1; - wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; - - fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo - (.wclk(sys_clk), .datain(tx_f36_data), - .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), - .rclk(tx_clk), .dataout(tx_f36_data_int1), - .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset)); - - fifo36_to_ll8 fifo36_to_ll8 - (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), - .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), - .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n)); - - assign tx_ll_sof2 = ~tx_ll_sof2_n; - assign tx_ll_eof2 = ~tx_ll_eof2_n; - assign tx_ll_src_rdy2 = ~tx_ll_src_rdy2_n; - assign tx_ll_dst_rdy2_n = ~tx_ll_dst_rdy2; - - ll8_shortfifo tx_sfifo - (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), - .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), - .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), - .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); - - ll8_to_txmac ll8_to_txmac - (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), - .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), - .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - - flow_ctrl_rx flow_ctrl_rx - (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh), - .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space), - .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req)); - - wire [31:0] debug_tx, debug_rx; - - assign debug_tx = { { tx_ll_data }, - { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, - tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, - { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, - { tx_data} }; - assign debug_rx = { { rx_ll_data }, - { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, - rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 }, - { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]}, - { rx_data} }; - - assign debug = debug_rx; - -endmodule // simple_gemac_wrapper diff --git a/simple_gemac/simple_gemac_wrapper_f36_tb.v b/simple_gemac/simple_gemac_wrapper_f36_tb.v deleted file mode 100644 index 804fa8748..000000000 --- a/simple_gemac/simple_gemac_wrapper_f36_tb.v +++ /dev/null @@ -1,243 +0,0 @@ - - -module simple_gemac_wrapper_f36_tb; -`include "eth_tasks_f36.v" - - reg clk = 0; - reg reset = 1; - - initial #1000 reset = 0; - always #50 clk = ~clk; - - reg wb_clk = 0; - wire wb_rst = reset; - always #173 wb_clk = ~wb_clk; - - wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; - wire [7:0] GMII_RXD, GMII_TXD; - - wire rx_valid, rx_error, rx_ack; - wire tx_ack, tx_valid, tx_error; - - wire [7:0] rx_data, tx_data; - - reg [15:0] pause_time; - reg pause_req = 0; - - wire GMII_RX_CLK = GMII_GTX_CLK; - - reg [7:0] FORCE_DAT_ERR = 0; - reg FORCE_ERR = 0; - - // Loopback - assign GMII_RX_DV = GMII_TX_EN; - assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; - assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; - - - wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2; - wire rx_ll_dst_rdy2; - wire [7:0] rx_ll_data, rx_ll_data2; - wire rx_ll_error, rx_ll_error2; - - wire [31:0] wb_dat_o; - reg [31:0] wb_dat_i; - reg [7:0] wb_adr; - reg wb_stb=0, wb_cyc=0, wb_we=0; - wire wb_ack; - - reg [35:0] tx_f36_dat; - reg tx_f36_src_rdy; - wire tx_f36_dst_rdy; - - wire [35:0] rx_f36_dat; - wire rx_f36_src_rdy; - reg rx_f36_dst_rdy = 1; - - simple_gemac_wrapper simple_gemac_wrapper - (.clk125(clk), .reset(reset), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), - .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof), - .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), .rx_ll_dst_rdy(rx_ll_dst_rdy), - .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof), - .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), .tx_ll_dst_rdy(tx_ll_dst_rdy), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), - .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), - .mdio(mdio), .mdc(mdc) ); - - wire rx_ll_dst_rdy2_n; - assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; - - ll8_shortfifo rx_sfifo - (.clk(clk), .reset(reset), .clear(0), - .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), - .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); - - ll8_to_fifo36 ll8_to_fifo36 - (.clk(clk), .reset(reset), .clear(0), - .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2), - .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), - .f36_data(rx_f36_dat), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy)); - - wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - wire tx_ll_sof2_n, tx_ll_eof2_n; - wire tx_ll_src_rdy2_n, tx_ll_dst_rdy2; - wire [7:0] tx_ll_data, tx_ll_data2; - wire tx_ll_error; - wire tx_ll_error2 = 0; - - fifo36_to_ll8 fifo36_to_ll8 - (.clk(clk), .reset(reset), .clear(clear), - .f36_data(tx_f36_dat), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), - .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), - .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2)); - - ll8_shortfifo tx_sfifo - (.clk(clk), .reset(reset), .clear(clear), - .datain(tx_ll_data2), .sof_i(~tx_ll_sof2_n), .eof_i(~tx_ll_eof2_n), - .error_i(tx_ll_error2), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2), - .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), - .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); - - initial $dumpfile("simple_gemac_wrapper_f36_tb.vcd"); - initial $dumpvars(0,simple_gemac_wrapper_f36_tb); - - integer i; - reg [7:0] pkt_rom[0:65535]; - reg [1023:0] ROMFile; - - initial - for (i=0;i<65536;i=i+1) - pkt_rom[i] <= 8'h0; - - initial - begin - @(negedge reset); - repeat (10) - @(posedge clk); - WishboneWR(0,6'b111001); - WishboneWR(4,16'hF1F2); - WishboneWR(8,32'hF3F4_F5F6); - WishboneWR(12,16'h0000); - WishboneWR(16,32'h0000_0000); - - @(posedge clk); - SendFlowCtrl(16'h0007); // Send flow control - @(posedge clk); - #30000; - @(posedge clk); - SendFlowCtrl(16'h0009); // Increase flow control before it expires - #10000; - @(posedge clk); - SendFlowCtrl(16'h0000); // Cancel flow control before it expires - @(posedge clk); - - SendPacket_to_fifo36(8'hAA,10); // This packet gets dropped by the filters - repeat (10) - @(posedge clk); - - SendPacketFromFile_fifo36(60,0,0); // The rest are valid packets - repeat (10) - @(posedge clk); - - SendPacketFromFile_fifo36(61,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_fifo36(62,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_fifo36(63,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(64,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_fifo36(59,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(58,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(100,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(200,150,30); // waiting 14 empties the fifo, 15 underruns - repeat (1) - @(posedge clk); - SendPacketFromFile_fifo36(100,0,30); - #10000 $finish; - end -/* - // Force a CRC error - initial - begin - #90000; - @(posedge clk); - FORCE_DAT_ERR <= 8'h10; - @(posedge clk); - FORCE_DAT_ERR <= 8'h00; - end - - // Force an RX_ER error (i.e. link loss) - initial - begin - #116000; - @(posedge clk); - FORCE_ERR <= 1; - @(posedge clk); - FORCE_ERR <= 0; - end - - // Cause receive fifo to fill, causing an RX overrun - initial - begin - #126000; - @(posedge clk); - rx_f36_dst_rdy <= 0; - repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows - @(posedge clk); - rx_f36_dst_rdy <= 1; - end - */ - // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun - // Still need to test: CRC errors on Pause Frames, MDIO, wishbone - - task WishboneWR; - input [7:0] adr; - input [31:0] value; - begin - wb_adr <= adr; - wb_dat_i <= value; - wb_stb <= 1; - wb_cyc <= 1; - wb_we <= 1; - while (~wb_ack) - @(posedge wb_clk); - @(posedge wb_clk); - wb_stb <= 0; - wb_cyc <= 0; - wb_we <= 0; - end - endtask // WishboneWR - - always @(posedge clk) - if(rx_f36_src_rdy & rx_f36_dst_rdy) - begin - if(rx_f36_dat[32] & ~rx_f36_dat[33]) - $display("RX-PKT-START %d",$time); - $display("RX-PKT SOF %d EOF %d ERR %d OCC %d DAT %x",rx_f36_dat[32],rx_f36_dat[33], - &rx_f36_dat[33:32],rx_f36_dat[35:34],rx_f36_dat[31:0]); - if(rx_f36_dat[33] & ~rx_f36_dat[32]) - $display("RX-PKT-END %d",$time); - if(rx_f36_dat[33] & rx_f36_dat[32]) - $display("RX-PKT-ERROR %d",$time); - end - -endmodule // simple_gemac_wrapper_tb diff --git a/simple_gemac/simple_gemac_wrapper_tb.v b/simple_gemac/simple_gemac_wrapper_tb.v deleted file mode 100644 index 26a471a49..000000000 --- a/simple_gemac/simple_gemac_wrapper_tb.v +++ /dev/null @@ -1,209 +0,0 @@ - - -module simple_gemac_wrapper_tb; -`include "eth_tasks_f36.v" - - reg reset = 1; - initial #1000 reset = 0; - wire wb_rst = reset; - - reg eth_clk = 0; - always #50 eth_clk = ~eth_clk; - - reg wb_clk = 0; - always #173 wb_clk = ~wb_clk; - - reg sys_clk = 0; - always #77 sys_clk = ~ sys_clk; - - wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; - wire [7:0] GMII_RXD, GMII_TXD; - - wire rx_valid, rx_error, rx_ack; - wire tx_ack, tx_valid, tx_error; - - wire [7:0] rx_data, tx_data; - - reg [15:0] pause_time; - reg pause_req = 0; - - wire GMII_RX_CLK = GMII_GTX_CLK; - - reg [7:0] FORCE_DAT_ERR = 0; - reg FORCE_ERR = 0; - - // Loopback - assign GMII_RX_DV = GMII_TX_EN; - assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; - assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; - - - wire [31:0] wb_dat_o; - reg [31:0] wb_dat_i; - reg [7:0] wb_adr; - reg wb_stb=0, wb_cyc=0, wb_we=0; - wire wb_ack; - - reg [35:0] tx_f36_data=0; - reg tx_f36_src_rdy = 0; - wire tx_f36_dst_rdy; - wire rx_f36_data; - wire rx_f36_src_rdy; - wire rx_f36_dst_rdy = 1; - - simple_gemac_wrapper simple_gemac_wrapper - (.clk125(eth_clk), .reset(reset), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), - - .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy), - .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy), - - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we), - .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), - - .mdio(), .mdc(), - .debug() ); - - initial $dumpfile("simple_gemac_wrapper_tb.vcd"); - initial $dumpvars(0,simple_gemac_wrapper_tb); - - integer i; - reg [7:0] pkt_rom[0:65535]; - reg [1023:0] ROMFile; - - initial - for (i=0;i<65536;i=i+1) - pkt_rom[i] <= 8'h0; - - initial - begin - @(negedge reset); - repeat (10) - @(posedge wb_clk); - WishboneWR(0,6'b111101); - WishboneWR(4,16'hA0B0); - WishboneWR(8,32'hC0D0_A1B1); - WishboneWR(12,16'h0000); - WishboneWR(16,32'h0000_0000); - - @(posedge eth_clk); - SendFlowCtrl(16'h0007); // Send flow control - @(posedge eth_clk); - #30000; - @(posedge eth_clk); - SendFlowCtrl(16'h0009); // Increase flow control before it expires - #10000; - @(posedge eth_clk); - SendFlowCtrl(16'h0000); // Cancel flow control before it expires - @(posedge eth_clk); - - repeat (1000) - @(posedge sys_clk); - SendPacket_to_fifo36(32'hA0B0C0D0,10); // This packet gets dropped by the filters - repeat (1000) - @(posedge sys_clk); - - SendPacket_to_fifo36(32'hAABBCCDD,100); // This packet gets dropped by the filters - repeat (10) - @(posedge sys_clk); -/* - SendPacketFromFile_f36(60,0,0); // The rest are valid packets - repeat (10) - @(posedge clk); - - SendPacketFromFile_f36(61,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_f36(62,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_f36(63,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(64,0,0); - repeat (10) - @(posedge clk); - SendPacketFromFile_f36(59,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(58,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(100,0,0); - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(200,150,30); // waiting 14 empties the fifo, 15 underruns - repeat (1) - @(posedge clk); - SendPacketFromFile_f36(100,0,30); - */ - #100000 $finish; - end - - // Force a CRC error - initial - begin - #90000; - @(posedge eth_clk); - FORCE_DAT_ERR <= 8'h10; - @(posedge eth_clk); - FORCE_DAT_ERR <= 8'h00; - end - - // Force an RX_ER error (i.e. link loss) - initial - begin - #116000; - @(posedge eth_clk); - FORCE_ERR <= 1; - @(posedge eth_clk); - FORCE_ERR <= 0; - end -/* - // Cause receive fifo to fill, causing an RX overrun - initial - begin - #126000; - @(posedge clk); - rx_ll_dst_rdy2 <= 0; - repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows - @(posedge clk); - rx_ll_dst_rdy2 <= 1; - end - */ - // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun - // Still need to test: CRC errors on Pause Frames, MDIO, wishbone - - task WishboneWR; - input [7:0] adr; - input [31:0] value; - begin - wb_adr <= adr; - wb_dat_i <= value; - wb_stb <= 1; - wb_cyc <= 1; - wb_we <= 1; - while (~wb_ack) - @(posedge wb_clk); - @(posedge wb_clk); - wb_stb <= 0; - wb_cyc <= 0; - wb_we <= 0; - end - endtask // WishboneWR - /* - always @(posedge clk) - if(rx_ll_src_rdy2 & rx_ll_dst_rdy2) - begin - if(rx_ll_sof2 & ~rx_ll_eof2) - $display("RX-PKT-START %d",$time); - $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2); - if(rx_ll_eof2 & ~rx_ll_sof2) - $display("RX-PKT-END %d",$time); - end - */ -endmodule // simple_gemac_wrapper_tb diff --git a/simple_gemac/test_packet.mem b/simple_gemac/test_packet.mem deleted file mode 100644 index 7f41d3e42..000000000 --- a/simple_gemac/test_packet.mem +++ /dev/null @@ -1,66 +0,0 @@ -ff -ff -ff -ff -ff -ff -08 -00 -07 -5c -2e -e4 -08 -06 -00 -01 -08 -04 -06 -02 -00 -01 -08 -00 -07 -5c -2e -e4 -03 -64 -00 -00 -00 -00 -00 -00 -02 -64 -00 -3a -f3 -5c -4f -12 -01 -10 -00 -01 -00 -00 -00 -00 -00 -00 -20 -41 -42 -41 -08 -00 -AA -BB -CC -DD -EE -FF diff --git a/testbench/.gitignore b/testbench/.gitignore deleted file mode 100644 index eedcf9652..000000000 --- a/testbench/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -/single_u2_sim -/dual_u2_sim -/*.lxt -/*.vcd -/*.sav diff --git a/testbench/BOOTSTRAP.sav b/testbench/BOOTSTRAP.sav deleted file mode 100644 index 41501945f..000000000 --- a/testbench/BOOTSTRAP.sav +++ /dev/null @@ -1,82 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -u2_sim_top.cpld_clk -u2_sim_top.cpld_detached -u2_sim_top.cpld_din -u2_sim_top.cpld_done -u2_sim_top.cpld_start -u2_sim_top.aux_clk -u2_sim_top.clk_fpga -u2_sim_top.clk_sel[1:0] -u2_sim_top.clk_en[1:0] -u2_sim_top.u2_basic.ram_loader_rst -u2_sim_top.u2_basic.wb_rst -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.sysctrl.ram_loader_done_i -u2_sim_top.cpld_model.sclk -u2_sim_top.cpld_model.start -u2_sim_top.u2_basic.ram_loader.rst_i -u2_sim_top.sen_clk -u2_sim_top.sen_dac -u2_sim_top.sclk -@22 -u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0] -u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0] -u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0] -@28 -u2_sim_top.u2_basic.shared_spi.wb_we_i -u2_sim_top.u2_basic.shared_spi.wb_stb_i -u2_sim_top.u2_basic.shared_spi.wb_ack_o -@22 -u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] -u2_sim_top.u2_basic.shared_spi.ctrl[13:0] -u2_sim_top.u2_basic.shared_spi.divider[15:0] -u2_sim_top.u2_basic.shared_spi.char_len[6:0] -u2_sim_top.u2_basic.shared_spi.ss[7:0] -u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0] -u2_sim_top.u2_basic.shared_spi.rx[127:0] -@28 -u2_sim_top.u2_basic.control_lines.wb_stb_i -u2_sim_top.u2_basic.control_lines.wb_we_i -@22 -u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0] -u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0] -u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] -@28 -u2_sim_top.u2_basic.control_lines.wb_cyc_i -@22 -u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] -@28 -u2_sim_top.clock_ready -u2_sim_top.u2_basic.ram_loader.done_o -u2_sim_top.u2_basic.dsp_rst -u2_sim_top.u2_basic.ram_loader_rst -u2_sim_top.u2_basic.wb_rst -@22 -u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0] -@28 -u2_sim_top.u2_basic.aeMB.iwb_ack_i -u2_sim_top.u2_basic.ram_loader_done -@22 -u2_sim_top.u2_basic.iram_rd_adr[15:0] -u2_sim_top.u2_basic.iram_rd_dat[31:0] -@28 -u2_sim_top.u2_basic.iram_wr_we -u2_sim_top.u2_basic.iram_wr_stb -@22 -u2_sim_top.u2_basic.iram_wr_sel[3:0] -u2_sim_top.u2_basic.iram_wr_dat[31:0] -u2_sim_top.u2_basic.iram_wr_adr[15:0] -@28 -u2_sim_top.u2_basic.ram_loader.ram_loader_done_o -u2_sim_top.u2_basic.ID_ram.dwb_we_i -u2_sim_top.u2_basic.ID_ram.iwb_we_i -u2_sim_top.u2_basic.ram_loader.ram_we -u2_sim_top.u2_basic.ram_loader.ram_we_q -u2_sim_top.u2_basic.ram_loader.ram_we_s -u2_sim_top.u2_basic.ram_loader.wb_ack_i -u2_sim_top.u2_basic.ID_ram.iwb_ack_o -u2_sim_top.u2_basic.ID_ram.iwb_stb_i -u2_sim_top.u2_basic.ID_ram.wb_rst_i diff --git a/testbench/Makefile b/testbench/Makefile deleted file mode 100644 index 6032a0123..000000000 --- a/testbench/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -all: single dual - -single: - iverilog -Wimplicit -Wportbind -c cmdfile ../top/single_u2_sim/single_u2_sim.v -o single_u2_sim - -dual: - iverilog -Wimplicit -Wportbind -c cmdfile ../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim - -clean: - rm -f single_u2_sim dual_u2_sim *.vcd *.lxt diff --git a/testbench/PAUSE.sav b/testbench/PAUSE.sav deleted file mode 100644 index f5e1ea1ac..000000000 --- a/testbench/PAUSE.sav +++ /dev/null @@ -1,62 +0,0 @@ -[size] 1400 967 -[pos] -1 -1 -*-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] u2_sim_top. -[treeopen] u2_sim_top.u2_basic. -[treeopen] u2_sim_top.u2_basic.MAC_top. -[treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx. -@22 -u2_sim_top.GMII_TXD[7:0] -@28 -u2_sim_top.GMII_TX_EN -@200 -- -@24 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0] -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0] -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en -@22 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0] -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk -@24 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0] -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk -@200 -- -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1 -@200 -- -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1 -@200 -- -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply -@22 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0] -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en -u2_sim_top.u2_basic.proc_int -@22 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0] -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] -@25 -u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0] diff --git a/testbench/README b/testbench/README deleted file mode 100644 index 14bbb68bb..000000000 --- a/testbench/README +++ /dev/null @@ -1,5 +0,0 @@ -The path to happiness: - -make clean -make -./u2_sim +rom=../../firmware/eth_test.rom -lxt2 diff --git a/testbench/SERDES.sav b/testbench/SERDES.sav deleted file mode 100644 index 3bb6ba929..000000000 --- a/testbench/SERDES.sav +++ /dev/null @@ -1,35 +0,0 @@ -[size] 1400 967 -[pos] -1 -1 -*-30.885946 6591910000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] u2_sim_top. -[treeopen] u2_sim_top.u2_basic. -[treeopen] u2_sim_top.u2_basic.serdes. -@22 -u2_sim_top.u2_basic.serdes.ser_t[15:0] -@28 -u2_sim_top.u2_basic.serdes.ser_tklsb -u2_sim_top.u2_basic.serdes.ser_tkmsb -u2_sim_top.u2_basic.ram_loader.ram_loader_done_o -u2_sim_top.u2_basic.proc_int -@22 -u2_sim_top.u2_basic.serdes.fifo_space[15:0] -@28 -u2_sim_top.u2_basic.serdes.inhibit_tx -u2_sim_top.u2_basic.serdes.send_xoff -u2_sim_top.u2_basic.serdes.send_xon -u2_sim_top.u2_basic.serdes.sent -u2_sim_top.u2_basic.serdes.xoff_rcvd -u2_sim_top.u2_basic.serdes.xon_rcvd -u2_sim_top.u2_basic.serdes.serdes_rx.wr_write_o -u2_sim_top.u2_basic.serdes.serdes_rx.wr_done_o -u2_sim_top.u2_basic.serdes.serdes_rx.write -@22 -u2_sim_top.u2_basic.serdes.serdes_rx.line_i[31:0] -@28 -(0)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] -(1)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] -@22 -#chosen_data[15:0] (2)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (3)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (4)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (5)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (6)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (7)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (8)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (9)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (10)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (11)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (12)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (13)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (14)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (15)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (16)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (17)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] -u2_sim_top.u2_basic.serdes.ser_t[15:0] -@28 -u2_sim_top.u2_basic.serdes.ser_tklsb diff --git a/testbench/U2_SIM.sav b/testbench/U2_SIM.sav deleted file mode 100644 index d320c2b6c..000000000 --- a/testbench/U2_SIM.sav +++ /dev/null @@ -1,95 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -u2_sim_top.adc_oen_a -u2_sim_top.adc_oen_b -u2_sim_top.adc_pdn_a -u2_sim_top.adc_pdn_b -u2_sim_top.aux_clk -u2_sim_top.POR -u2_sim_top.clk_fpga -u2_sim_top.clk_en[1:0] -u2_sim_top.clk_sel[1:0] -u2_sim_top.led1 -u2_sim_top.led2 -u2_sim_top.sclk -u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0] -u2_sim_top.sda_pad_o -u2_sim_top.sda_pad_oen_o -u2_sim_top.sdi -u2_sim_top.sdo -u2_sim_top.sen_clk -u2_sim_top.sen_dac -u2_sim_top.ser_enable -u2_sim_top.ser_loopen -u2_sim_top.ser_prbsen -u2_sim_top.ser_rx_en -u2_sim_top.u2_basic.sysctrl.start -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.done -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.sysctrl.aux_clk -u2_sim_top.u2_basic.sysctrl.clk_fpga -u2_sim_top.u2_basic.sysctrl.done -u2_sim_top.u2_basic.bus_writer.start -u2_sim_top.u2_basic.bus_writer.done -@22 -u2_sim_top.u2_basic.bus_writer.rom_addr[15:0] -u2_sim_top.u2_basic.bus_writer.rom_data[47:0] -u2_sim_top.u2_basic.bus_writer.state[3:0] -@29 -u2_sim_top.u2_basic.bus_writer.wb_ack_i -@22 -u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0] -@28 -u2_sim_top.u2_basic.bus_writer.wb_clk_i -u2_sim_top.u2_basic.bus_writer.wb_cyc_o -@22 -u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0] -u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0] -@28 -u2_sim_top.u2_basic.bus_writer.wb_stb_o -u2_sim_top.u2_basic.bus_writer.wb_we_o -u2_sim_top.u2_basic.bus_writer.wb_rst_i -u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0] -u2_sim_top.sda_pad_i -u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i -u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o -@22 -u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0] -u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0] -@28 -u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i -u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i -u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i -u2_sim_top.u2_basic.control_lines.wb_cyc_i -u2_sim_top.u2_basic.control_lines.wb_stb_i -u2_sim_top.u2_basic.control_lines.wb_we_i -u2_sim_top.u2_basic.control_lines.wb_ack_o -u2_sim_top.u2_basic.s0_ack -@22 -u2_sim_top.u2_basic.control_lines.internal_reg[31:0] -u2_sim_top.u2_basic.control_lines.port_output[31:0] -@28 -u2_sim_top.u2_basic.led1 -u2_sim_top.u2_basic.led2 -@22 -u2_sim_top.u2_basic.misc_outs[7:0] -u2_sim_top.u2_basic.clock_outs[7:0] -u2_sim_top.u2_basic.adc_outs[7:0] -u2_sim_top.u2_basic.serdes_outs[7:0] -@28 -u2_sim_top.u2_basic.shared_spi.miso_pad_i -u2_sim_top.u2_basic.shared_spi.mosi_pad_o -@22 -u2_sim_top.u2_basic.shared_spi.ss[7:0] -u2_sim_top.u2_basic.shared_spi.divider[15:0] -@28 -u2_sim_top.u2_basic.shared_spi.sclk_pad_o -@22 -u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] diff --git a/testbench/cmdfile b/testbench/cmdfile deleted file mode 100644 index 8083eb92a..000000000 --- a/testbench/cmdfile +++ /dev/null @@ -1,27 +0,0 @@ - -# My stuff --y . --y ../top/u2_core --y ../control_lib --y ../control_lib/newfifo --y ../serdes --y ../sdr_lib --y ../timing --y ../coregen --y ../extram --y ../simple_gemac --y ../simple_gemac/miim - -# Models --y ../models --y ../models/CY7C1356C - -# Open Cores --y ../opencores/8b10b --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog --y ../opencores/aemb/rtl/verilog --y ../opencores/simple_pic/rtl - diff --git a/timing/.gitignore b/timing/.gitignore deleted file mode 100644 index 515552fdb..000000000 --- a/timing/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/a.out -/*.vcd diff --git a/timing/time_64bit.v b/timing/time_64bit.v deleted file mode 100644 index c0a846e74..000000000 --- a/timing/time_64bit.v +++ /dev/null @@ -1,63 +0,0 @@ - - -module time_64bit - #(parameter TICKS_PER_SEC = 32'd100000000, - parameter BASE = 0) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input pps, - output [63:0] vita_time - ); - - localparam NEXT_TICKS = 0; - localparam NEXT_SECS = 1; - localparam ROLLOVER = TICKS_PER_SEC - 1; - - assign vita_time = {seconds,ticks}; - - wire [31:0] next_ticks_preset; - wire [31:0] next_seconds_preset; - wire set_on_pps_trig; - reg set_on_next_pps; - - setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(next_ticks_preset),.changed()); - - setting_reg #(.my_addr(BASE+NEXT_SECS)) sr_next_secs - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig)); - - reg [31:0] seconds; - reg [31:0] ticks; - - wire end_of_second; - - always @(posedge clk) - if(rst) - set_on_next_pps <= 0; - else if(set_on_pps_trig) - set_on_next_pps <= 1; - else if(pps) - set_on_next_pps <= 0; - - always @(posedge clk) - if(rst) - begin - seconds <= 32'd0; - ticks <= 32'd0; - end - else if(pps & set_on_next_pps) - begin - seconds <= next_seconds_preset; - ticks <= next_ticks_preset; - end - else if(ticks == ROLLOVER) - begin - seconds <= seconds + 1; - ticks <= 0; - end - else - ticks <= ticks + 1; - -endmodule // time_64bit diff --git a/timing/time_receiver.v b/timing/time_receiver.v deleted file mode 100644 index 8e7d3f1ea..000000000 --- a/timing/time_receiver.v +++ /dev/null @@ -1,94 +0,0 @@ - -module time_receiver - (input clk, input rst, - output [31:0] master_time, - output sync_rcvd, - input exp_pps_in); - - wire code_err, disp_err, dispout, complete_word; - reg disp_reg; - reg [9:0] shiftreg; - reg [3:0] bit_count; - wire [8:0] dataout; - reg [8:0] dataout_reg; - - always @(posedge clk) - shiftreg <= {exp_pps_in, shiftreg[9:1]}; - - localparam COMMA_0 = 10'h283; - localparam COMMA_1 = 10'h17c; - - wire found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1); - wire set_disp = (shiftreg == COMMA_1); - - always @(posedge clk) - if(rst) - bit_count <= 0; - else if(found_comma | complete_word) - bit_count <= 0; - else - bit_count <= bit_count + 1; - assign complete_word = (bit_count == 9); - - always @(posedge clk) - if(set_disp) - disp_reg <= 1; - else if(complete_word) - disp_reg <= dispout; - - always @(posedge clk) - if(complete_word) - dataout_reg <= dataout; - - decode_8b10b decode_8b10b - (.datain(shiftreg),.dispin(disp_reg), - .dataout(dataout),.dispout(dispout), - .code_err(code_err),.disp_err(disp_err) ); - - reg error; - always @(posedge clk) - if(complete_word) - error <= code_err | disp_err; - - localparam STATE_IDLE = 0; - localparam STATE_T0 = 1; - localparam STATE_T1 = 2; - localparam STATE_T2 = 3; - localparam STATE_T3 = 4; - - localparam HEAD = 9'h13c; - - reg [7:0] clock_a, clock_b, clock_c; - reg [2:0] state; - - always @(posedge clk) - if(rst) - state <= STATE_IDLE; - else if(complete_word) - case(state) - STATE_IDLE : - if(dataout_reg == HEAD) - state <= STATE_T0; - STATE_T0 : - begin - clock_a <= dataout_reg[7:0]; - state <= STATE_T1; - end - STATE_T1 : - begin - clock_b <= dataout_reg[7:0]; - state <= STATE_T2; - end - STATE_T2 : - begin - clock_c <= dataout_reg[7:0]; - state <= STATE_T3; - end - STATE_T3 : - state <= STATE_IDLE; - endcase // case(state) - - assign master_time = {clock_a, clock_b, clock_c, dataout_reg[7:0]}; - assign sync_rcvd = (complete_word & (state == STATE_T3)); - -endmodule // time_sender diff --git a/timing/time_sender.v b/timing/time_sender.v deleted file mode 100644 index aa2fcbbdb..000000000 --- a/timing/time_sender.v +++ /dev/null @@ -1,110 +0,0 @@ - - -module time_sender - (input clk, input rst, - input [31:0] master_time, - input send_sync, - output exp_pps_out); - - reg [7:0] datain; - reg k; - wire [9:0] dataout; - reg [9:0] dataout_reg; - reg disp_reg; - wire disp, new_word; - - encode_8b10b encode_8b10b - (.datain({k,datain}),.dispin(disp_reg), - .dataout(dataout),.dispout(disp)); - - assign exp_pps_out = dataout_reg[0]; - - always @(posedge clk) - if(rst) - disp_reg <= 0; - else if(new_word) - disp_reg <= disp; - - always @(posedge clk) - if(rst) - dataout_reg <= 0; - else if(new_word) - dataout_reg <= dataout; - else - dataout_reg <= {1'b0,dataout_reg[9:1]}; - - reg [4:0] state; - reg [3:0] bit_count; - - assign new_word = (bit_count == 9); - - always @(posedge clk) - if(rst) - bit_count <= 0; - else if(new_word | send_sync) - bit_count <= 0; - else - bit_count <= bit_count + 1; - - localparam SEND_IDLE = 0; - localparam SEND_HEAD = 1; - localparam SEND_T0 = 2; - localparam SEND_T1 = 3; - localparam SEND_T2 = 4; - localparam SEND_T3 = 5; - - localparam COMMA = 8'hBC; - localparam HEAD = 8'h3C; - - reg [31:0] master_time_reg; - - always @(posedge clk) - if(rst) - master_time_reg <= 0; - else if(send_sync) - master_time_reg <= master_time; - - always @(posedge clk) - if(rst) - begin - {k,datain} <= 0; - state <= SEND_IDLE; - end - else - if(send_sync) - state <= SEND_HEAD; - else if(new_word) - case(state) - SEND_IDLE : - {k,datain} <= {1'b1,COMMA}; - SEND_HEAD : - begin - {k,datain} <= {1'b1, HEAD}; - state <= SEND_T0; - end - SEND_T0 : - begin - {k,datain} <= {1'b0, master_time_reg[31:24] }; - state <= SEND_T1; - end - SEND_T1 : - begin - {k,datain} <= {1'b0, master_time_reg[23:16]}; - state <= SEND_T2; - end - SEND_T2 : - begin - {k,datain} <= {1'b0, master_time_reg[15:8]}; - state <= SEND_T3; - end - SEND_T3 : - begin - {k,datain} <= {1'b0, master_time_reg[7:0]}; - state <= SEND_IDLE; - end - default : - state <= SEND_IDLE; - endcase // case(state) - - -endmodule // time_sender diff --git a/timing/time_sync.v b/timing/time_sync.v deleted file mode 100644 index c0c8e195f..000000000 --- a/timing/time_sync.v +++ /dev/null @@ -1,146 +0,0 @@ - - -module time_sync - (input wb_clk_i, input rst_i, - input cyc_i, input stb_i, input [2:0] adr_i, - input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, - input sys_clk_i, output [31:0] master_time_o, - input pps_posedge, input pps_negedge, - input exp_pps_in, output exp_pps_out, - output reg int_o, - output reg epoch_o, - output reg pps_o ); - - wire [31:0] master_time_rcvd; - reg [31:0] master_time; - reg [31:0] delta_time; - - reg internal_tick; - wire sync_rcvd, pps_ext; - reg [31:0] tick_time, tick_time_wb; - wire tick_free_run; - reg tick_int_enable, tick_source, external_sync; - reg [31:0] tick_interval; - reg sync_on_next_pps; - reg sync_every_pps; - reg pps_edge; - - // Generate master time - always @(posedge sys_clk_i) - if(rst_i) - master_time <= 0; - else if(external_sync & sync_rcvd) - master_time <= master_time_rcvd + delta_time; - else if(pps_ext & (sync_on_next_pps|sync_every_pps)) - master_time <= 0; - else - master_time <= master_time + 1; - assign master_time_o = master_time; - - time_sender time_sender - (.clk(sys_clk_i),.rst(rst_i), - .master_time(master_time), - .send_sync(internal_tick), - .exp_pps_out(exp_pps_out) ); - - time_receiver time_receiver - (.clk(sys_clk_i),.rst(rst_i), - .master_time(master_time_rcvd), - .sync_rcvd(sync_rcvd), - .exp_pps_in(exp_pps_in) ); - - assign ack_o = stb_i; - wire wb_write = cyc_i & stb_i & we_i; - wire wb_read = cyc_i & stb_i & ~we_i; - wire wb_acc = cyc_i & stb_i; - - always @(posedge wb_clk_i) - if(rst_i) - begin - tick_source <= 0; - tick_int_enable <= 0; - external_sync <= 0; - tick_interval <= 100000-1; // default to 1K times per second - delta_time <= 0; - pps_edge <= 0; - sync_every_pps <= 0; - end - else if(wb_write) - case(adr_i[2:0]) - 3'd0 : - begin - tick_source <= dat_i[0]; - tick_int_enable <= dat_i[1]; - external_sync <= dat_i[2]; - pps_edge <= dat_i[3]; - sync_every_pps <= dat_i[4]; - end - 3'd1 : - tick_interval <= dat_i; - 3'd2 : - delta_time <= dat_i; - 3'd3 : - ; - // Do nothing here, this is to arm the sync_on_next - endcase // case(adr_i[2:0]) - - always @(posedge sys_clk_i) - if(rst_i) - sync_on_next_pps <= 0; - else if(pps_ext) - sync_on_next_pps <= 0; - else if(wb_write & (adr_i[2:0] == 3)) - sync_on_next_pps <= 1; - - always @(posedge sys_clk_i) - if(internal_tick) - tick_time <= master_time; - - always @(posedge wb_clk_i) - tick_time_wb <= tick_time; - - assign dat_o = tick_time_wb; - - always @(posedge sys_clk_i) - internal_tick <= (tick_source == 0) ? tick_free_run : pps_ext; - - reg [31:0] counter; - always @(posedge sys_clk_i) - if(rst_i) - counter <= 0; - else if(tick_free_run) - counter <= 0; - else - counter <= counter + 1; - assign tick_free_run = (counter >= tick_interval); - - // Properly Latch and edge detect External PPS input - reg pps_in_d1, pps_in_d2; - always @(posedge sys_clk_i) - begin - pps_in_d1 <= pps_edge ? pps_posedge : pps_negedge; - pps_in_d2 <= pps_in_d1; - end - assign pps_ext = pps_in_d1 & ~pps_in_d2; - - always @(posedge sys_clk_i) - pps_o <= pps_ext; - - // Need to register this? - reg internal_tick_d1; - always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick; - - always @(posedge wb_clk_i) - if(rst_i) - int_o <= 0; - else if(tick_int_enable & (internal_tick | internal_tick_d1)) - int_o <= 1; - else - int_o <= 0; - - always @(posedge sys_clk_i) - if(rst_i) - epoch_o <= 0; - else - epoch_o <= (master_time_o[27:0] == 0); -endmodule // time_sync diff --git a/timing/time_transfer_tb.v b/timing/time_transfer_tb.v deleted file mode 100644 index 2b75c60bd..000000000 --- a/timing/time_transfer_tb.v +++ /dev/null @@ -1,50 +0,0 @@ - -`timescale 1ns / 1ps - -module time_transfer_tb(); - - reg clk = 0, rst = 1; - always #5 clk = ~clk; - - initial - begin - @(negedge clk); - @(negedge clk); - rst <= 0; - end - - initial $dumpfile("time_transfer_tb.vcd"); - initial $dumpvars(0,time_transfer_tb); - - initial #100000000 $finish; - - wire exp_pps, pps, pps_rcv; - wire [31:0] master_clock_rcv; - reg [31:0] master_clock = 0; - reg [31:0] counter = 0; - - localparam PPS_PERIOD = 109; - always @(posedge clk) - if(counter == PPS_PERIOD) - counter <= 0; - else - counter <= counter + 1; - assign pps = (counter == (PPS_PERIOD-1)); - - always @(posedge clk) - master_clock <= master_clock + 1; - - time_sender time_sender - (.clk(clk),.rst(rst), - .master_clock(master_clock), - .pps(pps), - .exp_pps_out(exp_pps) ); - - time_receiver time_receiver - (.clk(clk),.rst(rst), - .master_clock(master_clock_rcv), - .pps(pps_rcv), - .exp_pps_in(exp_pps) ); - - wire [31:0] delta = master_clock - master_clock_rcv; -endmodule // time_transfer_tb diff --git a/timing/timer.v b/timing/timer.v deleted file mode 100644 index 70c9746be..000000000 --- a/timing/timer.v +++ /dev/null @@ -1,40 +0,0 @@ - - -module timer - (input wb_clk_i, input rst_i, - input cyc_i, input stb_i, input [2:0] adr_i, - input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, - input sys_clk_i, input [31:0] master_time_i, - output int_o ); - - reg [31:0] time_wb; - always @(posedge wb_clk_i) - time_wb <= master_time_i; - - assign ack_o = stb_i; - - reg [31:0] int_time; - reg int_reg; - - always @(posedge sys_clk_i) - if(rst_i) - begin - int_time <= 0; - int_reg <= 0; - end - else if(|int_time && (master_time_i == int_time)) - begin - int_time <= 0; - int_reg <= 1; - end - else if(stb_i & we_i) - begin - int_time <= dat_i; - int_reg <= 0; - end - - assign dat_o = time_wb; - assign int_o = int_reg; - -endmodule // timer - diff --git a/top/.gitignore b/top/.gitignore deleted file mode 100644 index bf1b77066..000000000 --- a/top/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/*.sav diff --git a/top/eth_test/.gitignore b/top/eth_test/.gitignore deleted file mode 100644 index b30397081..000000000 --- a/top/eth_test/.gitignore +++ /dev/null @@ -1,43 +0,0 @@ -/xst -/_ngo -/_xmsgs -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*_log -/*.lfp -/*.bit -/*.bin -/*.vcd -/*.unroutes -/*.drc -/*_map.* -/*_guide.* -/*.twr -/*.twx -/a.out -/*.xpi -/*_pad.txt -/*.bgn -/*.par diff --git a/top/eth_test/eth_sim_top.v b/top/eth_test/eth_sim_top.v deleted file mode 100644 index 640a4e60f..000000000 --- a/top/eth_test/eth_sim_top.v +++ /dev/null @@ -1,437 +0,0 @@ -////////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_basic -////////////////////////////////////////////////////////////////////////////////// - -module eth_sim_top - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output led1, - output led2, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - input PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] ser_debug; - - ////////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - parameter dw = 32; // Data bus width - parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i; - wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; - wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel; - wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack; - wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb; - wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc; - wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err; - wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty; - wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we; - - wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01), - .s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010), - .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty) - ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we; - wire [3:0] iram_wr_sel; - wire [aw-1:0] iram_wr_adr, iram_rd_adr; - wire [dw-1:0] iram_wr_dat, iram_rd_dat; - - wire bus_error, proc_int; - - assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0; - assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack; - - ram_loader #(.AWIDTH(16)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start), - .mode_o(cpld_mode), - .done_o(cpld_done), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr), - .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel), - .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack), - .ram_loader_done_o(ram_loader_done)); - - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr), - .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - assign proc_int = 1'b0; - - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - ram_wb_harvard #(.AWIDTH(14)) - ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat), - .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb), - .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel), - - .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel)); - - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - - // Buffer Pool, slave #1 - wire rd0_read, rd0_ready, rd0_done, rd0_empty; - wire rd1_read, rd1_ready, rd1_done, rd1_empty; - wire rd2_read, rd2_ready, rd2_done, rd2_empty; - wire rd3_read, rd3_ready, rd3_done, rd3_empty; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_write, wr0_done, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_ready, wr3_full; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - -/* - buffer_pool buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), - - .stream_clk(dsp_clk),.stream_rst(dsp_rst), - // Write Interfaces - .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(), - .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(), - .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(), - .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(), - // Read Interfaces - .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty), - .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty), - .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty), - .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty) - ); -*/ - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i), - .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack), - - .wb_err_o(s2_err),.wb_int_o(s2_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - assign s2_rty = 1'b0; - - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(st_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_err = 1'b0; - assign s3_rty = 1'b0; - - // GPIOs -- Slave #4 - wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d; - assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d; - - simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a), - .gpio(/* io_tx[7:0]*/) ); - - simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b), - .gpio(/* io_tx[15:8] */) ); - - simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c), - .gpio(/* io_rx[7:0] */) ); - - simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d), - .gpio(/* io_rx[15:8]*/) ); - - assign s4_err = 1'b0; - assign s4_rty = 1'b0; - - // Output control lines, SLAVE #5 - wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0]; - assign {led2, led1} = misc_outs[1:0]; - - wb_output_pins32 control_lines - (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i), - .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc), - .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) ); - - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - - // Ethernet slave, #6 - eth_wrapper eth_wrapper - (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(), - .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode - .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER), - .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - // FIFO Interfaces - .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(), - .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(), - // Wishbone - .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack) - ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_err = 1'b0; - assign s7_rty = 1'b0; - assign s7_dat_i = 32'd0; - - /////////////////////////////////////////////////////////////////////////// - // DSP - reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; - reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; - - always @(posedge dsp_clk) - begin - adc_a_reg1 <= adc_a; - adc_a_reg2 <= adc_a_reg1; - adc_b_reg1 <= adc_b; - adc_b_reg2 <= adc_b_reg1; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_a_reg2 <= adc_ovf_a_reg1; - adc_ovf_b_reg1 <= adc_ovf_b; - adc_ovf_b_reg2 <= adc_ovf_b_reg1; - end // always @ (posedge dsp_clk) - - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done), - .rx_ready_i(wr1_ready),.rx_full_i(wr1_full), - .overrun() ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done), - .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty), - .underrun() ); - - assign dsp_rst = wb_rst; - - ///////////////////////////////////////////////////////////////////////////////////// - // SERDES - serdes_tx serdes_tx - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done), - .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty) - ); - - serdes_rx serdes_rx - (.clk(dsp_clk),.rst(dsp_rst), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done) - ); - - // Debug Pins - wire [31:0] debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst}, - {1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached}, - {8'hAF}, - {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}}; - - wire [31:0] debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst}, - {iram_rd_adr[15:8]}, - {iram_rd_adr[7:0]}, - {serdes_outs}}; - - assign io_rx = ser_debug[31:16]; - assign io_tx = ser_debug[15:0]; - - assign debug = debug_wb; - - assign debug_clk[0] = wb_clk; - assign debug_clk[1] = dsp_clk; - -endmodule // eth_test - - -// Local Variables: -// verilog-library-directories:("." "subdir" "subdir2") -// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v") -// verilog-library-extensions:(".v" ".h") -// End: diff --git a/top/eth_test/eth_tb.v b/top/eth_test/eth_tb.v deleted file mode 100644 index 451ce1e7e..000000000 --- a/top/eth_test/eth_tb.v +++ /dev/null @@ -1,257 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -// Nearly everything is an input - -module eth_tb(); - // Misc, debug - wire led1; - wire led2; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_oen_a; - wire adc_pdn_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_oen_b; - wire adc_pdn_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - wire clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk, wb_rst; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #7 clk_fpga = ~clk_fpga; - - - wire div_clk; - reg [2:0] div_ctr = 0; - - always @(posedge clk_fpga or negedge clk_fpga) - if(div_ctr==5) - div_ctr = 0; - else - div_ctr = div_ctr + 1; - assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2); - - assign dsp_clk = clk_fpga; - assign wb_clk = clock_ready ? div_clk : aux_clk; - - initial - $monitor($time, ,clock_ready); - - initial begin - $dumpfile("eth_tb.vcd"); - $dumpvars(0,eth_tb); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - eth_sim_top eth_sim_top(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .led1 (led1), - .led2 (led2), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .PHY_CLK (PHY_CLK), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_oen_a (adc_oen_a), - .adc_pdn_a (adc_pdn_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_oen_b (adc_oen_b), - .adc_pdn_b (adc_pdn_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0])); - - // Experimental printf-like function - always @(posedge wb_clk) - begin - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000)) - $write("%x",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100)) - $display("%x",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004)) - $write("%c",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104)) - $display("%c",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008)) - $display(""); - end - - -endmodule // u2_sim_top - -// Local Variables: -// verilog-library-directories:("." "subdir" "subdir2") -// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v") -// verilog-library-extensions:(".v" ".h") -// End: diff --git a/top/single_u2_sim/single_u2_sim.v b/top/single_u2_sim/single_u2_sim.v deleted file mode 100644 index 2a7b24849..000000000 --- a/top/single_u2_sim/single_u2_sim.v +++ /dev/null @@ -1,324 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module single_u2_sim(); - // Misc, debug - wire [7:0] leds; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_on_a, adc_oe_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_on_b, adc_oe_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - reg clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #6 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #5 clk_fpga = ~clk_fpga; - - initial clk_to_mac = 0; - always #4 clk_to_mac = ~clk_to_mac; - - wire div_clk, dsp_clk; - reg [7:0] div_ctr = 0; - - assign dsp_clk = clock_ready ? clk_fpga : aux_clk; - assign wb_clk = div_clk; - -`define CLK_DIV_2 1 -//`define CLK_DIV_3 - -`ifdef CLK_DIV_2 - localparam clock_divider = 4'd2; - always @(posedge dsp_clk) - div_ctr <= div_ctr + 1; - assign div_clk = div_ctr[0]; -`endif - -`ifdef CLK_DIV_3 - localparam clock_divider = 2; - always @(posedge dsp_clk or negedge dsp_clk) - if(div_ctr == 5) - div_ctr <= 0; - else - div_ctr <= div_ctr + 1; - assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); -`endif - - initial - $monitor($time, ,clock_ready); - - always #1000000 $monitor("Time in ns ",$time); - - initial begin - @(negedge cpld_done); - @(posedge cpld_done); - $dumpfile("single_u2_sim.lxt"); - $dumpvars(0,single_u2_sim); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - serdes_model serdes_model - (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), - .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), - .even(0),.error(0) ); - - adc_model adc_model - (.clk(dsp_clk),.rst(0), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); - - wire [2:0] speed; - phy_sim phy_model - (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), - .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), - .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), - .Crs(GMII_CRS), .Col(GMII_COL), - .Speed(speed), .Done(0) ); - pullup p3(MDIO); - - miim_model miim_model - (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), - .phy_intn_o(PHY_INTn),.speed_o(speed) ); - - xlnx_glbl glbl (.GSR(),.GTS()); - - wire RAM_MODE = 1'b0; - cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), - .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), - .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), - .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); - - M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), - .SDA(SDA),.SCL(SCL),.RESET(0)); - - wire scl_pad_i, scl_pad_o, scl_pad_oen_o; - wire sda_pad_i, sda_pad_o, sda_pad_oen_o; - - pullup p1(SCL); - pullup p2(SDA); - - assign scl_pad_i = SCL; - assign sda_pad_i = SDA; - - assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; - assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; - - // printf output - wire uart_baud_o, uart_tx_o, uart_rx_i; - assign uart_rx_i = 1'b1; - - uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); - - // End the simulation - always @(posedge wb_clk) - if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) - begin - $display($time, "Finish called.",); - $finish; - end - - u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_init_b (1), - .por (0), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (uart_baud_o), - .sim_mode (1'b1), - .clock_divider (clock_divider) - ); - -endmodule // single_u2_sim diff --git a/top/tcl/ise_helper.tcl b/top/tcl/ise_helper.tcl deleted file mode 100644 index fe9db87af..000000000 --- a/top/tcl/ise_helper.tcl +++ /dev/null @@ -1,89 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -proc set_props {process options} { - if ![string compare $options ""] { - return - } - set state 1 - foreach opt $options { - if $state { - set key $opt - set state 0 - } else { - puts ">>> Setting: $process\[$key\] = $opt" - if ![string compare $process "Project"] { - project set $key $opt - } else { - project set $key $opt -process $process - } - set state 1 - } - } -} - -if [file isfile $env(PROJ_FILE)] { - puts ">>> Opening project: $env(PROJ_FILE)" - project open $env(PROJ_FILE) -} else { - puts ">>> Creating project: $env(PROJ_FILE)" - project new $env(PROJ_FILE) - - ################################################## - # Set the project properties - ################################################## - set_props "Project" $env(PROJECT_PROPERTIES) - - ################################################## - # Add the sources - ################################################## - foreach source $env(SOURCES) { - set source $env(SOURCE_ROOT)$source - puts ">>> Adding source to project: $source" - xfile add $source - } - - ################################################## - # Set the top level module - ################################################## - project set top $env(TOP_MODULE) - - ################################################## - # Set the process properties - ################################################## - set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES) - set_props "Translate" $env(TRANSLATE_PROPERTIES) - set_props "Map" $env(MAP_PROPERTIES) - set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES) - set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES) - set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES) - set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES) -} - -if [string compare $env(PROCESS_RUN) ""] { - puts ">>> Running Process: $env(PROCESS_RUN)" - process run $env(PROCESS_RUN) -} - -project close -exit - - diff --git a/top/u2_core/.gitignore b/top/u2_core/.gitignore deleted file mode 100644 index 9728395c1..000000000 --- a/top/u2_core/.gitignore +++ /dev/null @@ -1,44 +0,0 @@ -*~ -/xst -/_ngo -/_xmsgs -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*_log -/*.lfp -/*.bit -/*.bin -/*.vcd -/*.unroutes -/*.drc -/*_map.* -/*_guide.* -/*.twr -/*.twx -/a.out -/*.xpi -/*_pad.txt -/*.bgn -/*.par diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v deleted file mode 100755 index fd17a10a7..000000000 --- a/top/u2_core/u2_core.v +++ /dev/null @@ -1,761 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=32768) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; - - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) - ); - - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; - - setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - assign irq= {{8'b0}, - {8'b0}, - {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps_in; - always @(posedge dsp_clk) pps_posedge <= pps_in; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), - .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), - .wb_ack_o(sd_ack) ); - - assign sd_dat_i[31:8] = 0; - - // ///////////////////////////////////////////////////////////////////////// - // DSP - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); - - // dummy_rx dsp_core_rx - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), - .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = 0; // wb_clk; - assign debug_clk[1] = clk_to_mac; -/* - - wire mdio_cpy = MDIO; - assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, - { s6_adr[15:8] }, - { s6_adr[7:0] }, - { 6'd0, mdio_cpy, MDC } }; -*/ -/* - assign debug = { { GMII_TXD }, - { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, - { wr2_flags, rd2_flags }, - { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - */ - assign debug = { { GMII_RXD }, - { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, - { wr2_flags, rd2_flags }, - { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - - assign debug_gpio_0 = debug_mac; //eth_mac_debug; - assign debug_gpio_1 = 0; - -endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/top/u2_rev1/.gitignore b/top/u2_rev1/.gitignore deleted file mode 100644 index de5b50277..000000000 --- a/top/u2_rev1/.gitignore +++ /dev/null @@ -1,52 +0,0 @@ -/templates -/netgen -/_ngo -/_xmsgs -/_pace.ucf -/*.cmd -/*.ibs -/*.lfp -/*.mfp -/*.bit -/*.bin -/*.stx -/*.par -/*.unroutes -/*.ntrc_log -/*.ngr -/*.mrp -/*.html -/*.lso -/*.twr -/*.bld -/*.ncd -/*.txt -/*.cmd_log -/*.drc -/*.map -/*.twr -/*.xml -/*.syr -/*.ngm -/*.xst -/*.csv -/*.html -/*.lock -/*.ncd -/*.twx -/*.ise_ISE_Backup -/*.xml -/*.ut -/*.xpi -/*.ngd -/*.ncd -/*.pad -/*.bgn -/*.ngc -/*.pcf -/*.ngd -/xst -/*.log -/*.rpt -/*.cel -/*.restore diff --git a/top/u2_rev1/Makefile b/top/u2_rev1/Makefile deleted file mode 100644 index b3245d883..000000000 --- a/top/u2_rev1/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -FILENAME=u2_fpga_top -PARTNUM=xc3s1500-5fg456 - -all: project command xst ngd ncd ncd2 bit - -xst: - xst -ifn ${FILENAME}.cmd -ofn xst.log - -ngd: - ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME} - -ncd: - rm -rf ${FILENAME}.ncd - map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf - -# Place and route ncd file into new ncd file -ncd2: - par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf - -bit: - bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit - -clean: - @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \ - *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \ - *.blc *.bld *.ise_ISE_Backup *~ \ - *.pad *.ngm *.ngd *.par *.pcf *.unroutes \ - *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \ - *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \ - output.dat coregen.log *.ngo *.log ${FILENAME}.map \ - ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr - -command: - rm -rf ${FILENAME}.cmd - @echo "identification" >> ${FILENAME}.cmd - @echo "status" >> ${FILENAME}.cmd - @echo "time short" >> ${FILENAME}.cmd - @echo "memory on" >> ${FILENAME}.cmd - @echo "run " >> ${FILENAME}.cmd - @echo "-top ${FILENAME}" >> ${FILENAME}.cmd - @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd - @echo "-ifmt Verilog " >> ${FILENAME}.cmd - @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd - @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd - @echo "-bufg 6" >> ${FILENAME}.cmd - @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd - -project: - rm -f ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/TECH/duram.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/sign_extend.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/cordic_stage.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/cic_int_shifter.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/cic_dec_shifter.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/Reg_int.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/ram_2port.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/cordic.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/cic_interp.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/cic_decim.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/eth_miim.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/RMON.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/Phy_int.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_tx.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_rx.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/strobe_gen.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/ss_rcvr.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/shortfifo.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/setting_reg.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/mux8.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/mux4.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/longfifo.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/decoder_3_8.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/buffer_int.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/CRC16_D16.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/tx_control.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/rx_control.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/dsp_core_tx.v" ' >> ${FILENAME}.prj - @echo '`include "../../sdr_lib/dsp_core_rx.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" ' >> ${FILENAME}.prj - @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/MAC_top.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/mac_txfifo_int.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/mac_rxfifo_int.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/wb_readback_mux.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/wb_1master.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/timer.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/system_control.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/settings_bus.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/serdes_tx.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/serdes_rx.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/ram_wb_harvard.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/ram_loader.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/nsgpio.v" ' >> ${FILENAME}.prj - @echo '`include "../../control_lib/buffer_pool.v" ' >> ${FILENAME}.prj - @echo '`include "../u2_basic/u2_basic.v" ' >> ${FILENAME}.prj - @echo '`include "u2_fpga_top.v" ' >> ${FILENAME}.prj - @echo '`include "../../eth/rtl/verilog/elastic_buffer.v" ' >> ${FILENAME}.prj diff --git a/top/u2_rev1/u2_fpga.ise b/top/u2_rev1/u2_fpga.ise deleted file mode 100644 index f90caf024..000000000 Binary files a/top/u2_rev1/u2_fpga.ise and /dev/null differ diff --git a/top/u2_rev1/u2_fpga.ucf b/top/u2_rev1/u2_fpga.ucf deleted file mode 100755 index 5d2124819..000000000 --- a/top/u2_rev1/u2_fpga.ucf +++ /dev/null @@ -1,341 +0,0 @@ -NET "adc_a[0]" LOC = "A14" ; -NET "adc_a[10]" LOC = "D20" ; -NET "adc_a[11]" LOC = "D19" ; -NET "adc_a[12]" LOC = "D21" ; -NET "adc_a[13]" LOC = "E18" ; -NET "adc_a[1]" LOC = "B14" ; -NET "adc_a[2]" LOC = "C13" ; -NET "adc_a[3]" LOC = "D13" ; -NET "adc_a[4]" LOC = "A13" ; -NET "adc_a[5]" LOC = "B13" ; -NET "adc_a[6]" LOC = "E12" ; -NET "adc_a[7]" LOC = "C22" ; -NET "adc_a[8]" LOC = "C20" ; -NET "adc_a[9]" LOC = "C21" ; -NET "adc_b[0]" LOC = "A12" ; -NET "adc_b[10]" LOC = "D18" ; -NET "adc_b[11]" LOC = "B18" ; -NET "adc_b[12]" LOC = "D17" ; -NET "adc_b[13]" LOC = "E17" ; -NET "adc_b[1]" LOC = "E16" ; -NET "adc_b[2]" LOC = "F12" ; -NET "adc_b[3]" LOC = "F13" ; -NET "adc_b[4]" LOC = "F16" ; -NET "adc_b[5]" LOC = "F17" ; -NET "adc_b[6]" LOC = "C19" ; -NET "adc_b[7]" LOC = "B20" ; -NET "adc_b[8]" LOC = "B19" ; -NET "adc_b[9]" LOC = "C18" ; -NET "clk_en[0]" LOC = "C4" ; -NET "clk_en[1]" LOC = "D1" ; -NET "clk_sel[0]" LOC = "C3" ; -NET "clk_sel[1]" LOC = "C2" ; -NET "dac_a[0]" LOC = "A5" ; -NET "dac_a[10]" LOC = "L2" ; -NET "dac_a[11]" LOC = "L4" ; -NET "dac_a[12]" LOC = "L3" ; -NET "dac_a[13]" LOC = "L6" ; -NET "dac_a[14]" LOC = "L5" ; -NET "dac_a[15]" LOC = "K2" ; -NET "dac_a[1]" LOC = "B5" ; -NET "dac_a[2]" LOC = "C5" ; -NET "dac_a[3]" LOC = "D5" ; -NET "dac_a[4]" LOC = "A4" ; -NET "dac_a[5]" LOC = "B4" ; -NET "dac_a[6]" LOC = "F6" ; -NET "dac_a[7]" LOC = "D10" ; -NET "dac_a[8]" LOC = "D9" ; -NET "dac_a[9]" LOC = "A10" ; -NET "dac_b[0]" LOC = "D11" ; -NET "dac_b[10]" LOC = "F9" ; -NET "dac_b[11]" LOC = "A8" ; -NET "dac_b[12]" LOC = "B8" ; -NET "dac_b[13]" LOC = "D7" ; -NET "dac_b[14]" LOC = "E7" ; -NET "dac_b[15]" LOC = "B6" ; -NET "dac_b[1]" LOC = "E11" ; -NET "dac_b[2]" LOC = "F11" ; -NET "dac_b[3]" LOC = "B10" ; -NET "dac_b[4]" LOC = "C10" ; -NET "dac_b[5]" LOC = "E10" ; -NET "dac_b[6]" LOC = "F10" ; -NET "dac_b[7]" LOC = "A9" ; -NET "dac_b[8]" LOC = "B9" ; -NET "dac_b[9]" LOC = "E9" ; -NET "debug[0]" LOC = "N5" ; -NET "debug[10]" LOC = "R4" ; -NET "debug[11]" LOC = "T3" ; -NET "debug[12]" LOC = "U3" ; -NET "debug[13]" LOC = "M2" ; -NET "debug[14]" LOC = "M3" ; -NET "debug[15]" LOC = "M4" ; -NET "debug[16]" LOC = "M5" ; -NET "debug[17]" LOC = "M6" ; -NET "debug[18]" LOC = "N1" ; -NET "debug[19]" LOC = "N2" ; -NET "debug[1]" LOC = "N6" ; -NET "debug[20]" LOC = "N3" ; -NET "debug[21]" LOC = "T1" ; -NET "debug[22]" LOC = "T2" ; -NET "debug[23]" LOC = "U2" ; -NET "debug[24]" LOC = "T4" ; -NET "debug[25]" LOC = "U4" ; -NET "debug[26]" LOC = "T5" ; -NET "debug[27]" LOC = "T6" ; -NET "debug[28]" LOC = "U5" ; -NET "debug[29]" LOC = "V5" ; -NET "debug[2]" LOC = "P1" ; -NET "debug[30]" LOC = "W2" ; -NET "debug[31]" LOC = "W3" ; -NET "debug[3]" LOC = "P2" ; -NET "debug[4]" LOC = "P4" ; -NET "debug[5]" LOC = "P5" ; -NET "debug[6]" LOC = "R1" ; -NET "debug[7]" LOC = "R2" ; -NET "debug[8]" LOC = "P6" ; -NET "debug[9]" LOC = "R5" ; -NET "debug_clk[0]" LOC = "N4" ; -NET "debug_clk[1]" LOC = "M1" ; -NET "GMII_RXD[0]" LOC = "AA15" ; -NET "GMII_RXD[1]" LOC = "AB15" ; -NET "GMII_RXD[2]" LOC = "U14" ; -NET "GMII_RXD[3]" LOC = "V14" ; -NET "GMII_RXD[4]" LOC = "U13" ; -NET "GMII_RXD[5]" LOC = "V13" ; -NET "GMII_RXD[6]" LOC = "Y13" ; -NET "GMII_RXD[7]" LOC = "AA13" ; -NET "GMII_TXD[0]" LOC = "W14" ; -NET "GMII_TXD[1]" LOC = "AA20" ; -NET "GMII_TXD[2]" LOC = "AB20" ; -NET "GMII_TXD[3]" LOC = "Y18" ; -NET "GMII_TXD[4]" LOC = "AA18" ; -NET "GMII_TXD[5]" LOC = "AB18" ; -NET "GMII_TXD[6]" LOC = "V17" ; -NET "GMII_TXD[7]" LOC = "W17" ; -NET "io_rx[0]" LOC = "L21" ; -NET "io_rx[10]" LOC = "F21" ; -NET "io_rx[11]" LOC = "F20" ; -NET "io_rx[12]" LOC = "G19" ; -NET "io_rx[13]" LOC = "G18" ; -NET "io_rx[14]" LOC = "G17" ; -NET "io_rx[15]" LOC = "E22" ; -NET "io_rx[1]" LOC = "L20" ; -NET "io_rx[2]" LOC = "L19" ; -NET "io_rx[3]" LOC = "L18" ; -NET "io_rx[4]" LOC = "L17" ; -NET "io_rx[5]" LOC = "K22" ; -NET "io_rx[6]" LOC = "K21" ; -NET "io_rx[7]" LOC = "K20" ; -NET "io_rx[8]" LOC = "G22" ; -NET "io_rx[9]" LOC = "G21" ; -NET "io_tx[0]" LOC = "K4" ; -NET "io_tx[10]" LOC = "E1" ; -NET "io_tx[11]" LOC = "E3" ; -NET "io_tx[12]" LOC = "F4" ; -NET "io_tx[13]" LOC = "D2" ; -NET "io_tx[14]" LOC = "D4" ; -NET "io_tx[15]" LOC = "E4" ; -NET "io_tx[1]" LOC = "K3" ; -NET "io_tx[2]" LOC = "G1" ; -NET "io_tx[3]" LOC = "G5" ; -NET "io_tx[4]" LOC = "H5" ; -NET "io_tx[5]" LOC = "F3" ; -NET "io_tx[6]" LOC = "F2" ; -NET "io_tx[7]" LOC = "F5" ; -NET "io_tx[8]" LOC = "G6" ; -NET "io_tx[9]" LOC = "E2" ; -NET "RAM_A[0]" LOC = "N22" ; -NET "RAM_A[10]" LOC = "P18" ; -NET "RAM_A[11]" LOC = "R19" ; -NET "RAM_A[12]" LOC = "P19" ; -NET "RAM_A[13]" LOC = "R21" ; -NET "RAM_A[14]" LOC = "R22" ; -NET "RAM_A[15]" LOC = "T19" ; -NET "RAM_A[16]" LOC = "T20" ; -NET "RAM_A[17]" LOC = "U20" ; -NET "RAM_A[18]" LOC = "W19" ; -NET "RAM_A[1]" LOC = "N20" ; -NET "RAM_A[2]" LOC = "T21" ; -NET "RAM_A[3]" LOC = "M22" ; -NET "RAM_A[4]" LOC = "N19" ; -NET "RAM_A[5]" LOC = "N17" ; -NET "RAM_A[6]" LOC = "N18" ; -NET "RAM_A[7]" LOC = "P21" ; -NET "RAM_A[8]" LOC = "P22" ; -NET "RAM_A[9]" LOC = "P17" ; -NET "RAM_D[0]" LOC = "Y21" ; -NET "RAM_D[10]" LOC = "V22" ; -NET "RAM_D[11]" LOC = "V21" ; -NET "RAM_D[12]" LOC = "T17" ; -NET "RAM_D[13]" LOC = "U18" ; -NET "RAM_D[14]" LOC = "U21" ; -NET "RAM_D[15]" LOC = "R18" ; -NET "RAM_D[16]" LOC = "T18" ; -NET "RAM_D[17]" LOC = "T22" ; -NET "RAM_D[1]" LOC = "Y20" ; -NET "RAM_D[2]" LOC = "Y19" ; -NET "RAM_D[3]" LOC = "W22" ; -NET "RAM_D[4]" LOC = "Y22" ; -NET "RAM_D[5]" LOC = "V19" ; -NET "RAM_D[6]" LOC = "W21" ; -NET "RAM_D[7]" LOC = "W20" ; -NET "RAM_D[8]" LOC = "U19" ; -NET "RAM_D[9]" LOC = "V20" ; -NET "ser_r[0]" LOC = "AB10" ; -NET "ser_r[10]" LOC = "W10" ; -NET "ser_r[11]" LOC = "Y1" ; -NET "ser_r[12]" LOC = "Y3" ; -NET "ser_r[13]" LOC = "Y2" ; -NET "ser_r[14]" LOC = "W4" ; -NET "ser_r[15]" LOC = "W1" ; -NET "ser_r[1]" LOC = "AA10" ; -NET "ser_r[2]" LOC = "U9" ; -NET "ser_r[3]" LOC = "U6" ; -NET "ser_r[4]" LOC = "AB11" ; -NET "ser_r[5]" LOC = "Y7" ; -NET "ser_r[6]" LOC = "W7" ; -NET "ser_r[7]" LOC = "AB7" ; -NET "ser_r[8]" LOC = "AA7" ; -NET "ser_r[9]" LOC = "W9" ; -NET "ser_t[0]" LOC = "V7" ; -NET "ser_t[10]" LOC = "AA6" ; -NET "ser_t[11]" LOC = "Y6" ; -NET "ser_t[12]" LOC = "W8" ; -NET "ser_t[13]" LOC = "V8" ; -NET "ser_t[14]" LOC = "AB8" ; -NET "ser_t[15]" LOC = "AA8" ; -NET "ser_t[1]" LOC = "V10" ; -NET "ser_t[2]" LOC = "AB4" ; -NET "ser_t[3]" LOC = "AA4" ; -NET "ser_t[4]" LOC = "Y5" ; -NET "ser_t[5]" LOC = "W5" ; -NET "ser_t[6]" LOC = "AB5" ; -NET "ser_t[7]" LOC = "AA5" ; -NET "ser_t[8]" LOC = "W6" ; -NET "ser_t[9]" LOC = "V6" ; -NET "clk_muxed" TNM_NET = "clk_muxed"; -TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %; -NET "clk_to_mac" TNM_NET = "clk_to_mac"; -TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; -NET "cpld_clk" TNM_NET = "cpld_clk"; -TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; -NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; -TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; -NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; -TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; -#PACE: Start of Constraints generated by PACE - -#PACE: Start of PACE I/O Pin Assignments -NET "adc_oen_a" LOC = "E19" ; -NET "adc_oen_b" LOC = "C17" ; -NET "adc_ovf_a" LOC = "F18" ; -NET "adc_ovf_b" LOC = "B17" ; -NET "adc_pdn_a" LOC = "E20" ; -NET "adc_pdn_b" LOC = "D15" ; -NET "clk_fpga_n" LOC = "B11" ; -NET "clk_fpga_p" LOC = "A11" ; -NET "clk_func" LOC = "C12" ; -NET "clk_status" LOC = "B12" ; -NET "clk_to_mac" LOC = "AB12" ; -NET "cpld_clk" LOC = "AB14" ; -NET "cpld_din" LOC = "AA14" ; -NET "cpld_done" LOC = "V12" ; -NET "cpld_mode" LOC = "U12" ; -NET "cpld_start" LOC = "AA9" ; -NET "exp_pps_in_n" LOC = "V4" ; -NET "exp_pps_in_p" LOC = "V3" ; -NET "exp_pps_out_n" LOC = "V2" ; -NET "exp_pps_out_p" LOC = "V1" ; -NET "GMII_COL" LOC = "U16" ; -NET "GMII_CRS" LOC = "U17" ; -NET "GMII_GTX_CLK" LOC = "AA17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_RX_CLK" LOC = "W16" ; -NET "GMII_RX_DV" LOC = "AB16" ; -NET "GMII_RX_ER" LOC = "AA16" ; -NET "GMII_TX_CLK" LOC = "W13" ; -NET "GMII_TX_EN" LOC = "Y17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TX_ER" LOC = "V16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "led1" LOC = "V11" ; -NET "led2" LOC = "Y12" ; -NET "MDC" LOC = "V18" ; -NET "MDIO" LOC = "Y16" | PULLUP ; -NET "PHY_CLK" LOC = "V15" ; -NET "PHY_INTn" LOC = "AB13" ; -NET "PHY_RESETn" LOC = "AA19" ; -NET "pps_in" LOC = "Y11" ; -NET "RAM_CE1n" LOC = "N21" ; -NET "RAM_CENn" LOC = "M18" ; -NET "RAM_CLK" LOC = "M17" ; -NET "RAM_LDn" LOC = "M21" ; -NET "RAM_OEn" LOC = "M19" ; -NET "RAM_WEn" LOC = "M20" ; -NET "SCL" LOC = "A7" ; -NET "SCL_force" LOC = "E8" ; -NET "sclk" LOC = "K5" ; -NET "sclk_rx_adc" LOC = "J17" ; -NET "sclk_rx_dac" LOC = "J19" ; -NET "sclk_rx_db" LOC = "F19" ; -NET "sclk_tx_adc" LOC = "H1" ; -NET "sclk_tx_dac" LOC = "J5" ; -NET "sclk_tx_db" LOC = "D3" ; -NET "SDA" LOC = "D8" ; -NET "SDA_force" LOC = "C11" ; -NET "sdi" LOC = "J1" ; -NET "sdi_rx_adc" LOC = "H22" ; -NET "sdi_rx_dac" LOC = "J21" ; -NET "sdi_rx_db" LOC = "H19" ; -NET "sdi_tx_adc" LOC = "J4" ; -NET "sdi_tx_dac" LOC = "J6" ; -NET "sdi_tx_db" LOC = "G4" ; -NET "sdo" LOC = "J2" ; -NET "sdo_rx_adc" LOC = "H21" ; -NET "sdo_rx_db" LOC = "G20" ; -NET "sdo_tx_adc" LOC = "H2" ; -NET "sdo_tx_db" LOC = "G3" ; -NET "sen_clk" LOC = "K6" ; -NET "sen_dac" LOC = "L1" ; -NET "sen_rx_adc" LOC = "H18" ; -NET "sen_rx_dac" LOC = "J18" ; -NET "sen_rx_db" LOC = "D22" ; -NET "sen_tx_adc" LOC = "G2" ; -NET "sen_tx_dac" LOC = "H4" ; -NET "sen_tx_db" LOC = "C1" ; -NET "ser_enable" LOC = "W11" ; -NET "ser_loopen" LOC = "Y4" ; -NET "ser_prbsen" LOC = "AA3" ; -NET "ser_rklsb" LOC = "V9" ; -NET "ser_rkmsb" LOC = "Y10" ; -NET "ser_rx_clk" LOC = "AA11" ; -NET "ser_rx_en" LOC = "AB9" ; -NET "ser_tklsb" LOC = "U10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_tkmsb" LOC = "U11" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_tx_clk" LOC = "U7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<8>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<9>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<10>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<11>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<12>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<13>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<14>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -NET "ser_t<15>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; -#PACE: Start of PACE Area Constraints - -#PACE: Start of PACE Prohibit Constraints - -#PACE: End of Constraints generated by PACE diff --git a/top/u2_rev1/u2_fpga_top.prj b/top/u2_rev1/u2_fpga_top.prj deleted file mode 100644 index 544415f4d..000000000 --- a/top/u2_rev1/u2_fpga_top.prj +++ /dev/null @@ -1,102 +0,0 @@ -verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v" -verilog work "../../control_lib/ram_2port.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v" -verilog work "../../coregen/fifo_generator_v4_1.v" -verilog work "../../control_lib/shortfifo.v" -verilog work "../../control_lib/longfifo.v" -verilog work "../../sdr_lib/sign_extend.v" -verilog work "../../sdr_lib/cordic_stage.v" -verilog work "../../sdr_lib/cic_int_shifter.v" -verilog work "../../sdr_lib/cic_dec_shifter.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v" -verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" -verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v" -verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v" -verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v" -verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v" -verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v" -verilog work "../../opencores/8b10b/encode_8b10b.v" -verilog work "../../opencores/8b10b/decode_8b10b.v" -verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v" -verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v" -verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v" -verilog work "../../eth/rtl/verilog/Reg_int.v" -verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v" -verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" -verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v" -verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" -verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" -verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" -verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" -verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" -verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" -verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" -verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" -verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" -verilog work "../../control_lib/ss_rcvr.v" -verilog work "../../control_lib/cascadefifo2.v" -verilog work "../../control_lib/CRC16_D16.v" -verilog work "../../timing/time_sender.v" -verilog work "../../timing/time_receiver.v" -verilog work "../../serdes/serdes_tx.v" -verilog work "../../serdes/serdes_rx.v" -verilog work "../../serdes/serdes_fc_tx.v" -verilog work "../../serdes/serdes_fc_rx.v" -verilog work "../../sdr_lib/round.v" -verilog work "../../sdr_lib/cordic.v" -verilog work "../../sdr_lib/cic_interp.v" -verilog work "../../sdr_lib/cic_decim.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v" -verilog work "../../opencores/spi/rtl/verilog/spi_shift.v" -verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v" -verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" -verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v" -verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v" -verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v" -verilog work "../../eth/rtl/verilog/eth_miim.v" -verilog work "../../eth/rtl/verilog/RMON.v" -verilog work "../../eth/rtl/verilog/Phy_int.v" -verilog work "../../eth/rtl/verilog/MAC_tx.v" -verilog work "../../eth/rtl/verilog/MAC_rx.v" -verilog work "../../eth/rtl/verilog/Clk_ctrl.v" -verilog work "../../control_lib/strobe_gen.v" -verilog work "../../control_lib/setting_reg.v" -verilog work "../../control_lib/mux8.v" -verilog work "../../control_lib/mux4.v" -verilog work "../../control_lib/icache.v" -verilog work "../../control_lib/dpram32.v" -verilog work "../../control_lib/decoder_3_8.v" -verilog work "../../control_lib/dcache.v" -verilog work "../../control_lib/buffer_int.v" -verilog work "../../timing/timer.v" -verilog work "../../timing/time_sync.v" -verilog work "../../serdes/serdes.v" -verilog work "../../sdr_lib/tx_control.v" -verilog work "../../sdr_lib/rx_control.v" -verilog work "../../sdr_lib/dsp_core_tx.v" -verilog work "../../sdr_lib/dsp_core_rx.v" -verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v" -verilog work "../../opencores/spi/rtl/verilog/spi_top.v" -verilog work "../../opencores/simple_pic/rtl/simple_pic.v" -verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v" -verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" -verilog work "../../eth/rtl/verilog/MAC_top.v" -verilog work "../../eth/mac_txfifo_int.v" -verilog work "../../eth/mac_rxfifo_int.v" -verilog work "../../control_lib/wb_readback_mux.v" -verilog work "../../control_lib/wb_1master.v" -verilog work "../../control_lib/system_control.v" -verilog work "../../control_lib/settings_bus.v" -verilog work "../../control_lib/ram_loader.v" -verilog work "../../control_lib/ram_harv_cache.v" -verilog work "../../control_lib/nsgpio.v" -verilog work "../../control_lib/extram_interface.v" -verilog work "../../control_lib/buffer_pool.v" -verilog work "../../control_lib/atr_controller.v" -verilog work "../u2_basic/u2_basic.v" -verilog work "u2_fpga_top.v" diff --git a/top/u2_rev1/u2_fpga_top.v b/top/u2_rev1/u2_fpga_top.v deleted file mode 100644 index 63798a0c8..000000000 --- a/top/u2_rev1/u2_fpga_top.v +++ /dev/null @@ -1,393 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u2_fpga_top - ( - // Misc, debug - output led1, - output led2, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in_p, // Diff - input exp_pps_in_n, // Diff - output exp_pps_out_p, // Diff - output exp_pps_out_n, // Diff - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, // AA9 - output cpld_mode, // U12 - output cpld_done, // V12 - input cpld_din, // AA14 Now shared with CFG_Din - input cpld_clk, // AB14 serial clock - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - inout SCL, - inout SDA, - input SCL_force, - input SDA_force, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Clocks - input clk_fpga_p, // Diff - input clk_fpga_n, // Diff - input clk_to_mac, - input pps_in, - - // Generic SPI - output sclk, - output sen_clk, - output sen_dac, - output sdi, - input sdo, - - // TX DBoard - output sen_tx_db, - output sclk_tx_db, - input sdo_tx_db, - output sdi_tx_db, - - output sen_tx_adc, - output sclk_tx_adc, - input sdo_tx_adc, - output sdi_tx_adc, - - output sen_tx_dac, - output sclk_tx_dac, - output sdi_tx_dac, - - inout [15:0] io_tx, - - // RX DBoard - output sen_rx_db, - output sclk_rx_db, - input sdo_rx_db, - output sdi_rx_db, - - output sen_rx_adc, - output sclk_rx_adc, - input sdo_rx_adc, - output sdi_rx_adc, - - output sen_rx_dac, - output sclk_rx_dac, - output sdi_rx_dac, - - inout [15:0] io_rx - ); - - // FPGA-specific pins connections - wire aux_clk = PHY_CLK; - //wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire - wire cpld_detached = SDA_force; // FIXME Hacked on with Blue Wire - - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire exp_pps_in; - IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); - defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_pps_out; - OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); - defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge aux_clk) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - wire clk_muxed = clock_ready ? clk_fpga : aux_clk; - - wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; - assign adc_oen_a = ~adc_oe_a; - assign adc_oen_b = ~adc_oe_b; - assign adc_pdn_a = ~adc_on_a; - assign adc_pdn_b = ~adc_on_b; - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_muxed), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire led1_int, led2_int; - assign led1 = ~led1_int; - assign led2 = ~led2_int; - - // SPI - wire miso, mosi, sclk_int; - assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; - - assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | - (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | - (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - u2_basic u2_basic(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .led1 (led1_int), - .led2 (led2_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .PHY_CLK (PHY_CLK), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (), - .uart_rx_i (), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); - -endmodule // u2_fpga_top diff --git a/top/u2_rev2/.gitignore b/top/u2_rev2/.gitignore deleted file mode 100644 index 432f8fd58..000000000 --- a/top/u2_rev2/.gitignore +++ /dev/null @@ -1,57 +0,0 @@ -/*.ptwx -/*.xrpt -/*.zip -/*_xdb -/templates -/netgen -/_ngo -/_xmsgs -/_pace.ucf -/*.cmd -/*.ibs -/*.lfp -/*.mfp -/*.bit -/*.bin -/*.stx -/*.par -/*.unroutes -/*.ntrc_log -/*.ngr -/*.mrp -/*.html -/*.lso -/*.twr -/*.bld -/*.ncd -/*.txt -/*.cmd_log -/*.drc -/*.map -/*.twr -/*.xml -/*.syr -/*.ngm -/*.xst -/*.csv -/*.html -/*.lock -/*.ncd -/*.twx -/*.ise_ISE_Backup -/*.xml -/*.ut -/*.xpi -/*.ngd -/*.ncd -/*.pad -/*.bgn -/*.ngc -/*.pcf -/*.ngd -/xst -/*.log -/*.rpt -/*.cel -/*.restore -/build diff --git a/top/u2_rev2/Makefile b/top/u2_rev2/Makefile deleted file mode 100644 index 275c24b02..000000000 --- a/top/u2_rev2/Makefile +++ /dev/null @@ -1,248 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev2 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2_rev2/u2_rev2.ucf \ -top/u2_rev2/u2_rev2.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/top/u2_rev2/u2_rev2.ucf b/top/u2_rev2/u2_rev2.ucf deleted file mode 100644 index e18dc6f17..000000000 --- a/top/u2_rev2/u2_rev2.ucf +++ /dev/null @@ -1,337 +0,0 @@ -NET "leds[0]" LOC = "F7" ; -NET "leds[1]" LOC = "E5" ; -NET "leds[2]" LOC = "B7" ; -NET "leds[3]" LOC = "C11" ; -NET "leds[4]" LOC = "AB19" ; -NET "debug[0]" LOC = "N5" ; -NET "debug[1]" LOC = "N6" ; -NET "debug[2]" LOC = "P1" ; -NET "debug[3]" LOC = "P2" ; -NET "debug[4]" LOC = "P4" ; -NET "debug[5]" LOC = "P5" ; -NET "debug[6]" LOC = "R1" ; -NET "debug[7]" LOC = "R2" ; -NET "debug[8]" LOC = "P6" ; -NET "debug[9]" LOC = "R5" ; -NET "debug[10]" LOC = "R4" ; -NET "debug[11]" LOC = "T3" ; -NET "debug[12]" LOC = "U3" ; -NET "debug[13]" LOC = "M2" ; -NET "debug[14]" LOC = "M3" ; -NET "debug[15]" LOC = "M4" ; -NET "debug[16]" LOC = "M5" ; -NET "debug[17]" LOC = "M6" ; -NET "debug[18]" LOC = "N1" ; -NET "debug[19]" LOC = "N2" ; -NET "debug[20]" LOC = "N3" ; -NET "debug[21]" LOC = "T1" ; -NET "debug[22]" LOC = "T2" ; -NET "debug[23]" LOC = "U2" ; -NET "debug[24]" LOC = "T4" ; -NET "debug[25]" LOC = "U4" ; -NET "debug[26]" LOC = "T5" ; -NET "debug[27]" LOC = "T6" ; -NET "debug[28]" LOC = "U5" ; -NET "debug[29]" LOC = "V5" ; -NET "debug[30]" LOC = "W2" ; -NET "debug[31]" LOC = "W3" ; -NET "debug_clk[0]" LOC = "N4" ; -NET "debug_clk[1]" LOC = "M1" ; -NET "uart_tx_o" LOC = "C7" ; -NET "uart_rx_i" LOC = "A3" ; -NET "exp_pps_in_p" LOC = "V3" ; -NET "exp_pps_in_n" LOC = "V4" ; -NET "exp_pps_out_p" LOC = "V1" ; -NET "exp_pps_out_n" LOC = "V2" ; -NET "GMII_COL" LOC = "U16" ; -NET "GMII_CRS" LOC = "U17" ; -NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_CLK" LOC = "W13" ; -NET "GMII_RXD[0]" LOC = "AA15" ; -NET "GMII_RXD[1]" LOC = "AB15" ; -NET "GMII_RXD[2]" LOC = "U14" ; -NET "GMII_RXD[3]" LOC = "V14" ; -NET "GMII_RXD[4]" LOC = "U13" ; -NET "GMII_RXD[5]" LOC = "V13" ; -NET "GMII_RXD[6]" LOC = "Y13" ; -NET "GMII_RXD[7]" LOC = "AA13" ; -NET "GMII_RX_CLK" LOC = "W16" ; -NET "GMII_RX_DV" LOC = "AB16" ; -NET "GMII_RX_ER" LOC = "AA16" ; -NET "MDIO" LOC = "Y16" |PULLUP ; -NET "MDC" LOC = "V18" ; -NET "PHY_INTn" LOC = "AB13" ; -NET "PHY_RESETn" LOC = "AA19" ; -NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" ; -NET "RAM_D[1]" LOC = "N21" ; -NET "RAM_D[2]" LOC = "N22" ; -NET "RAM_D[3]" LOC = "M17" ; -NET "RAM_D[4]" LOC = "M18" ; -NET "RAM_D[5]" LOC = "M19" ; -NET "RAM_D[6]" LOC = "M20" ; -NET "RAM_D[7]" LOC = "M21" ; -NET "RAM_D[8]" LOC = "M22" ; -NET "RAM_D[9]" LOC = "Y22" ; -NET "RAM_D[10]" LOC = "Y21" ; -NET "RAM_D[11]" LOC = "Y20" ; -NET "RAM_D[12]" LOC = "Y19" ; -NET "RAM_D[13]" LOC = "W22" ; -NET "RAM_D[14]" LOC = "W21" ; -NET "RAM_D[15]" LOC = "W20" ; -NET "RAM_D[16]" LOC = "W19" ; -NET "RAM_D[17]" LOC = "V22" ; -NET "RAM_A[0]" LOC = "U21" ; -NET "RAM_A[1]" LOC = "T19" ; -NET "RAM_A[2]" LOC = "V21" ; -NET "RAM_A[3]" LOC = "V20" ; -NET "RAM_A[4]" LOC = "T20" ; -NET "RAM_A[5]" LOC = "T21" ; -NET "RAM_A[6]" LOC = "T22" ; -NET "RAM_A[7]" LOC = "T18" ; -NET "RAM_A[8]" LOC = "R18" ; -NET "RAM_A[9]" LOC = "P19" ; -NET "RAM_A[10]" LOC = "P21" ; -NET "RAM_A[11]" LOC = "P22" ; -NET "RAM_A[12]" LOC = "N19" ; -NET "RAM_A[13]" LOC = "N17" ; -NET "RAM_A[14]" LOC = "N18" ; -NET "RAM_A[15]" LOC = "T17" ; -NET "RAM_A[16]" LOC = "U19" ; -NET "RAM_A[17]" LOC = "U18" ; -NET "RAM_A[18]" LOC = "V19" ; -NET "RAM_CE1n" LOC = "U20" ; -NET "RAM_CENn" LOC = "P18" ; -NET "RAM_CLK" LOC = "P17" ; -NET "RAM_WEn" LOC = "R22" ; -NET "RAM_OEn" LOC = "R21" ; -NET "RAM_LDn" LOC = "R19" ; -NET "ser_enable" LOC = "W11" ; -NET "ser_prbsen" LOC = "AA3" ; -NET "ser_loopen" LOC = "Y4" ; -NET "ser_rx_en" LOC = "AB9" ; -NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_rx_clk" LOC = "AA11" ; -NET "ser_r[0]" LOC = "AB10" ; -NET "ser_r[1]" LOC = "AA10" ; -NET "ser_r[2]" LOC = "U9" ; -NET "ser_r[3]" LOC = "U6" ; -NET "ser_r[4]" LOC = "AB11" ; -NET "ser_r[5]" LOC = "Y7" ; -NET "ser_r[6]" LOC = "W7" ; -NET "ser_r[7]" LOC = "AB7" ; -NET "ser_r[8]" LOC = "AA7" ; -NET "ser_r[9]" LOC = "W9" ; -NET "ser_r[10]" LOC = "W10" ; -NET "ser_r[11]" LOC = "Y1" ; -NET "ser_r[12]" LOC = "Y3" ; -NET "ser_r[13]" LOC = "Y2" ; -NET "ser_r[14]" LOC = "W4" ; -NET "ser_r[15]" LOC = "W1" ; -NET "ser_rklsb" LOC = "V9" ; -NET "ser_rkmsb" LOC = "Y10" ; -NET "cpld_start" LOC = "AA9" ; -NET "cpld_mode" LOC = "U12" ; -NET "cpld_done" LOC = "V12" ; -NET "cpld_din" LOC = "AA14" ; -NET "cpld_clk" LOC = "AB14" ; -NET "cpld_detached" LOC = "V11" ; -NET "cpld_init_b" LOC = "W12" ; -NET "cpld_misc" LOC = "Y12" ; -NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; -NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; -NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; -NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; -NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; -NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; -NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; -NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; -NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; -NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; -NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; -NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; -NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; -NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; -NET "adc_ovf_a" LOC = "F18" ; -NET "adc_oen_a" LOC = "E19" ; -NET "adc_pdn_a" LOC = "E20" ; -NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; -NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; -NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; -NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; -NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; -NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; -NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; -NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; -NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; -NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; -NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; -NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; -NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; -NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; -NET "adc_ovf_b" LOC = "B17" ; -NET "adc_oen_b" LOC = "C17" ; -NET "adc_pdn_b" LOC = "D15" ; -NET "dac_a[0]" LOC = "A5" ; -NET "dac_a[1]" LOC = "B5" ; -NET "dac_a[2]" LOC = "C5" ; -NET "dac_a[3]" LOC = "D5" ; -NET "dac_a[4]" LOC = "A4" ; -NET "dac_a[5]" LOC = "B4" ; -NET "dac_a[6]" LOC = "F6" ; -NET "dac_a[7]" LOC = "D10" ; -NET "dac_a[8]" LOC = "D9" ; -NET "dac_a[9]" LOC = "A10" ; -NET "dac_a[10]" LOC = "L2" ; -NET "dac_a[11]" LOC = "L4" ; -NET "dac_a[12]" LOC = "L3" ; -NET "dac_a[13]" LOC = "L6" ; -NET "dac_a[14]" LOC = "L5" ; -NET "dac_a[15]" LOC = "K2" ; -NET "dac_b[0]" LOC = "D11" ; -NET "dac_b[1]" LOC = "E11" ; -NET "dac_b[2]" LOC = "F11" ; -NET "dac_b[3]" LOC = "B10" ; -NET "dac_b[4]" LOC = "C10" ; -NET "dac_b[5]" LOC = "E10" ; -NET "dac_b[6]" LOC = "F10" ; -NET "dac_b[7]" LOC = "A9" ; -NET "dac_b[8]" LOC = "B9" ; -NET "dac_b[9]" LOC = "E9" ; -NET "dac_b[10]" LOC = "F9" ; -NET "dac_b[11]" LOC = "A8" ; -NET "dac_b[12]" LOC = "B8" ; -NET "dac_b[13]" LOC = "D7" ; -NET "dac_b[14]" LOC = "E7" ; -NET "dac_b[15]" LOC = "B6" ; -NET "dac_lock" LOC = "D6" ; -NET "SCL" LOC = "A7" ; -NET "SDA" LOC = "D8" ; -NET "clk_en[0]" LOC = "C4" ; -NET "clk_en[1]" LOC = "D1" ; -NET "clk_sel[0]" LOC = "C3" ; -NET "clk_sel[1]" LOC = "C2" ; -NET "clk_func" LOC = "C12" ; -NET "clk_status" LOC = "B12" ; -NET "clk_fpga_p" LOC = "A11" ; -NET "clk_fpga_n" LOC = "B11" ; -NET "clk_to_mac" LOC = "AB12" ; -NET "pps_in" LOC = "Y11" ; -NET "sclk" LOC = "K5" ; -NET "sen_clk" LOC = "K6" ; -NET "sen_dac" LOC = "L1" ; -NET "sdi" LOC = "J1" ; -NET "sdo" LOC = "J2" ; -NET "sen_tx_db" LOC = "C1" ; -NET "sclk_tx_db" LOC = "D3" ; -NET "sdo_tx_db" LOC = "G3" ; -NET "sdi_tx_db" LOC = "G4" ; -NET "sen_tx_adc" LOC = "G2" ; -NET "sclk_tx_adc" LOC = "H1" ; -NET "sdo_tx_adc" LOC = "H2" ; -NET "sdi_tx_adc" LOC = "J4" ; -NET "sen_tx_dac" LOC = "H4" ; -NET "sclk_tx_dac" LOC = "J5" ; -NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" ; -NET "io_tx[1]" LOC = "K3" ; -NET "io_tx[2]" LOC = "G1" ; -NET "io_tx[3]" LOC = "G5" ; -NET "io_tx[4]" LOC = "H5" ; -NET "io_tx[5]" LOC = "F3" ; -NET "io_tx[6]" LOC = "F2" ; -NET "io_tx[7]" LOC = "F5" ; -NET "io_tx[8]" LOC = "G6" ; -NET "io_tx[9]" LOC = "E2" ; -NET "io_tx[10]" LOC = "E1" ; -NET "io_tx[11]" LOC = "E3" ; -NET "io_tx[12]" LOC = "F4" ; -NET "io_tx[13]" LOC = "D2" ; -NET "io_tx[14]" LOC = "D4" ; -NET "io_tx[15]" LOC = "E4" ; -NET "sen_rx_db" LOC = "D22" ; -NET "sclk_rx_db" LOC = "F19" ; -NET "sdo_rx_db" LOC = "G20" ; -NET "sdi_rx_db" LOC = "H19" ; -NET "sen_rx_adc" LOC = "H18" ; -NET "sclk_rx_adc" LOC = "J17" ; -NET "sdo_rx_adc" LOC = "H21" ; -NET "sdi_rx_adc" LOC = "H22" ; -NET "sen_rx_dac" LOC = "J18" ; -NET "sclk_rx_dac" LOC = "J19" ; -NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" ; -NET "io_rx[1]" LOC = "L20" ; -NET "io_rx[2]" LOC = "L19" ; -NET "io_rx[3]" LOC = "L18" ; -NET "io_rx[4]" LOC = "L17" ; -NET "io_rx[5]" LOC = "K22" ; -NET "io_rx[6]" LOC = "K21" ; -NET "io_rx[7]" LOC = "K20" ; -NET "io_rx[8]" LOC = "G22" ; -NET "io_rx[9]" LOC = "G21" ; -NET "io_rx[10]" LOC = "F21" ; -NET "io_rx[11]" LOC = "F20" ; -NET "io_rx[12]" LOC = "G19" ; -NET "io_rx[13]" LOC = "G18" ; -NET "io_rx[14]" LOC = "G17" ; -NET "io_rx[15]" LOC = "E22" ; - -NET "clk_to_mac" TNM_NET = "clk_to_mac"; -TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; - -#NET "dsp_clk" TNM_NET = "dsp_clk"; -#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %; - -NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; - -NET "cpld_clk" TNM_NET = "cpld_clk"; -TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; - -NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; -TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; - -NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; -TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; - -#NET "wb_clk" TNM_NET = "wb_clk"; -#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %; - -NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; -NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; - -#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; -#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; -#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; - -#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; -#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/top/u2_rev2/u2_rev2.v b/top/u2_rev2/u2_rev2.v deleted file mode 100644 index 517285e52..000000000 --- a/top/u2_rev2/u2_rev2.v +++ /dev/null @@ -1,417 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u2_rev2 - ( - // Misc, debug - output [4:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - output uart_tx_o, - input uart_rx_i, - - // Expansion - input exp_pps_in_p, // Diff - input exp_pps_in_n, // Diff - output exp_pps_out_p, // Diff - output exp_pps_out_n, // Diff - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, // AA9 - output cpld_mode, // U12 - output cpld_done, // V12 - input cpld_din, // AA14 Now shared with CFG_Din - input cpld_clk, // AB14 serial clock - input cpld_detached,// V11 unused - output cpld_init_b, // W12 unused dual purpose - output cpld_misc, // Y12 - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output reg [15:0] dac_a, - output reg [15:0] dac_b, - input dac_lock, // unused for now - - // I2C - inout SCL, - inout SDA, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Clocks - input clk_fpga_p, // Diff - input clk_fpga_n, // Diff - input clk_to_mac, - input pps_in, - - // Generic SPI - output sclk, - output sen_clk, - output sen_dac, - output sdi, - input sdo, - - // TX DBoard - output sen_tx_db, - output sclk_tx_db, - input sdo_tx_db, - output sdi_tx_db, - - output sen_tx_adc, - output sclk_tx_adc, - input sdo_tx_adc, - output sdi_tx_adc, - - output sen_tx_dac, - output sclk_tx_dac, - output sdi_tx_dac, - - inout [15:0] io_tx, - - // RX DBoard - output sen_rx_db, - output sclk_rx_db, - input sdo_rx_db, - output sdi_rx_db, - - output sen_rx_adc, - output sclk_rx_adc, - input sdo_rx_adc, - output sdi_rx_adc, - - output sen_rx_dac, - output sclk_rx_dac, - output sdi_rx_dac, - - inout [15:0] io_rx - ); - - assign cpld_init_b = 0; - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - wire clk90, clk180, clk270; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire exp_pps_in; - IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); - defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_pps_out; - OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); - defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge clk_fpga) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - - wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; - assign adc_oen_a = ~adc_oe_a; - assign adc_oen_b = ~adc_oe_b; - assign adc_pdn_a = ~adc_on_a; - assign adc_pdn_b = ~adc_on_b; - - reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; - reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; - - always @(posedge dsp_clk) - begin - adc_a_reg1 <= adc_a; - adc_b_reg1 <= adc_b; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_b_reg1 <= adc_ovf_b; - end - - always @(posedge dsp_clk) - begin - adc_a_reg2 <= adc_a_reg1; - adc_b_reg2 <= adc_b_reg1; - adc_ovf_a_reg2 <= adc_ovf_a_reg1; - adc_ovf_b_reg2 <= adc_ovf_b_reg1; - end // always @ (posedge dsp_clk) - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(clk90), - .CLK180(clk180), - .CLK270(clk270), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = 5'b01111 ^ leds_int; // all except eth are active-low - - // SPI - wire miso, mosi, sclk_int; - assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; - - assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | - (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | - (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - wire [15:0] dac_a_int, dac_b_int; - always @(negedge dsp_clk) dac_a <= dac_a_int; - always @(negedge dsp_clk) dac_b <= dac_b_int; - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_misc (cpld_misc), - .cpld_init_b (cpld_init_b), - .por (~POR), - .config_success (config_success), - .adc_a (adc_a_reg2), - .adc_ovf_a (adc_ovf_a_reg2), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b_reg2), - .adc_ovf_b (adc_ovf_b_reg2), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a_int), - .dac_b (dac_b_int), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); - -endmodule // u2_rev2 diff --git a/top/u2_rev3/.gitignore b/top/u2_rev3/.gitignore deleted file mode 100644 index 432f8fd58..000000000 --- a/top/u2_rev3/.gitignore +++ /dev/null @@ -1,57 +0,0 @@ -/*.ptwx -/*.xrpt -/*.zip -/*_xdb -/templates -/netgen -/_ngo -/_xmsgs -/_pace.ucf -/*.cmd -/*.ibs -/*.lfp -/*.mfp -/*.bit -/*.bin -/*.stx -/*.par -/*.unroutes -/*.ntrc_log -/*.ngr -/*.mrp -/*.html -/*.lso -/*.twr -/*.bld -/*.ncd -/*.txt -/*.cmd_log -/*.drc -/*.map -/*.twr -/*.xml -/*.syr -/*.ngm -/*.xst -/*.csv -/*.html -/*.lock -/*.ncd -/*.twx -/*.ise_ISE_Backup -/*.xml -/*.ut -/*.xpi -/*.ngd -/*.ncd -/*.pad -/*.bgn -/*.ngc -/*.pcf -/*.ngd -/xst -/*.log -/*.rpt -/*.cel -/*.restore -/build diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile deleted file mode 100644 index 4358d7c56..000000000 --- a/top/u2_rev3/Makefile +++ /dev/null @@ -1,246 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -control_lib/priority_enc.v \ -control_lib/pic.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/top/u2_rev3/u2_rev3.ucf b/top/u2_rev3/u2_rev3.ucf deleted file mode 100644 index 255a298ac..000000000 --- a/top/u2_rev3/u2_rev3.ucf +++ /dev/null @@ -1,333 +0,0 @@ -NET "leds[0]" LOC = "E8" ; -NET "leds[1]" LOC = "F7" ; -NET "leds[2]" LOC = "E5" ; -NET "leds[3]" LOC = "B7" ; -NET "leds[4]" LOC = "C11" ; -NET "leds[5]" LOC = "AB19" ; -NET "debug[0]" LOC = "N5" ; -NET "debug[1]" LOC = "N6" ; -NET "debug[2]" LOC = "P1" ; -NET "debug[3]" LOC = "P2" ; -NET "debug[4]" LOC = "P4" ; -NET "debug[5]" LOC = "P5" ; -NET "debug[6]" LOC = "R1" ; -NET "debug[7]" LOC = "R2" ; -NET "debug[8]" LOC = "P6" ; -NET "debug[9]" LOC = "R5" ; -NET "debug[10]" LOC = "R4" ; -NET "debug[11]" LOC = "T3" ; -NET "debug[12]" LOC = "U3" ; -NET "debug[13]" LOC = "M2" ; -NET "debug[14]" LOC = "M3" ; -NET "debug[15]" LOC = "M4" ; -NET "debug[16]" LOC = "M5" ; -NET "debug[17]" LOC = "M6" ; -NET "debug[18]" LOC = "N1" ; -NET "debug[19]" LOC = "N2" ; -NET "debug[20]" LOC = "N3" ; -NET "debug[21]" LOC = "T1" ; -NET "debug[22]" LOC = "T2" ; -NET "debug[23]" LOC = "U2" ; -NET "debug[24]" LOC = "T4" ; -NET "debug[25]" LOC = "U4" ; -NET "debug[26]" LOC = "T5" ; -NET "debug[27]" LOC = "T6" ; -NET "debug[28]" LOC = "U5" ; -NET "debug[29]" LOC = "V5" ; -NET "debug[30]" LOC = "W2" ; -NET "debug[31]" LOC = "W3" ; -NET "debug_clk[0]" LOC = "N4" ; -NET "debug_clk[1]" LOC = "M1" ; -NET "uart_tx_o" LOC = "C7" ; -NET "uart_rx_i" LOC = "A3" ; -NET "exp_pps_in_p" LOC = "V3" ; -NET "exp_pps_in_n" LOC = "V4" ; -NET "exp_pps_out_p" LOC = "V1" ; -NET "exp_pps_out_n" LOC = "V2" ; -NET "GMII_COL" LOC = "U16" ; -NET "GMII_CRS" LOC = "U17" ; -NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_CLK" LOC = "W13" ; -NET "GMII_RXD[0]" LOC = "AA15" ; -NET "GMII_RXD[1]" LOC = "AB15" ; -NET "GMII_RXD[2]" LOC = "U14" ; -NET "GMII_RXD[3]" LOC = "V14" ; -NET "GMII_RXD[4]" LOC = "U13" ; -NET "GMII_RXD[5]" LOC = "V13" ; -NET "GMII_RXD[6]" LOC = "Y13" ; -NET "GMII_RXD[7]" LOC = "AA13" ; -NET "GMII_RX_CLK" LOC = "AA12" ; -NET "GMII_RX_DV" LOC = "AB16" ; -NET "GMII_RX_ER" LOC = "AA16" ; -NET "MDIO" LOC = "Y16" |PULLUP ; -NET "MDC" LOC = "V18" ; -NET "PHY_INTn" LOC = "AB13" ; -NET "PHY_RESETn" LOC = "AA19" ; -NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" ; -NET "RAM_D[1]" LOC = "N21" ; -NET "RAM_D[2]" LOC = "N22" ; -NET "RAM_D[3]" LOC = "M17" ; -NET "RAM_D[4]" LOC = "M18" ; -NET "RAM_D[5]" LOC = "M19" ; -NET "RAM_D[6]" LOC = "M20" ; -NET "RAM_D[7]" LOC = "M21" ; -NET "RAM_D[8]" LOC = "M22" ; -NET "RAM_D[9]" LOC = "Y22" ; -NET "RAM_D[10]" LOC = "Y21" ; -NET "RAM_D[11]" LOC = "Y20" ; -NET "RAM_D[12]" LOC = "Y19" ; -NET "RAM_D[13]" LOC = "W22" ; -NET "RAM_D[14]" LOC = "W21" ; -NET "RAM_D[15]" LOC = "W20" ; -NET "RAM_D[16]" LOC = "W19" ; -NET "RAM_D[17]" LOC = "V22" ; -NET "RAM_A[0]" LOC = "U21" ; -NET "RAM_A[1]" LOC = "T19" ; -NET "RAM_A[2]" LOC = "V21" ; -NET "RAM_A[3]" LOC = "V20" ; -NET "RAM_A[4]" LOC = "T20" ; -NET "RAM_A[5]" LOC = "T21" ; -NET "RAM_A[6]" LOC = "T22" ; -NET "RAM_A[7]" LOC = "T18" ; -NET "RAM_A[8]" LOC = "R18" ; -NET "RAM_A[9]" LOC = "P19" ; -NET "RAM_A[10]" LOC = "P21" ; -NET "RAM_A[11]" LOC = "P22" ; -NET "RAM_A[12]" LOC = "N19" ; -NET "RAM_A[13]" LOC = "N17" ; -NET "RAM_A[14]" LOC = "N18" ; -NET "RAM_A[15]" LOC = "T17" ; -NET "RAM_A[16]" LOC = "U19" ; -NET "RAM_A[17]" LOC = "U18" ; -NET "RAM_A[18]" LOC = "V19" ; -NET "RAM_CE1n" LOC = "U20" ; -NET "RAM_CENn" LOC = "P18" ; -NET "RAM_CLK" LOC = "P17" ; -NET "RAM_WEn" LOC = "R22" ; -NET "RAM_OEn" LOC = "R21" ; -NET "RAM_LDn" LOC = "R19" ; -NET "ser_enable" LOC = "W11" ; -NET "ser_prbsen" LOC = "AA3" ; -NET "ser_loopen" LOC = "Y4" ; -NET "ser_rx_en" LOC = "AB9" ; -NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_rx_clk" LOC = "AA11" ; -NET "ser_r[0]" LOC = "AB10" ; -NET "ser_r[1]" LOC = "AA10" ; -NET "ser_r[2]" LOC = "U9" ; -NET "ser_r[3]" LOC = "U6" ; -NET "ser_r[4]" LOC = "AB11" ; -NET "ser_r[5]" LOC = "Y7" ; -NET "ser_r[6]" LOC = "W7" ; -NET "ser_r[7]" LOC = "AB7" ; -NET "ser_r[8]" LOC = "AA7" ; -NET "ser_r[9]" LOC = "W9" ; -NET "ser_r[10]" LOC = "W10" ; -NET "ser_r[11]" LOC = "Y1" ; -NET "ser_r[12]" LOC = "Y3" ; -NET "ser_r[13]" LOC = "Y2" ; -NET "ser_r[14]" LOC = "W4" ; -NET "ser_r[15]" LOC = "W1" ; -NET "ser_rklsb" LOC = "V9" ; -NET "ser_rkmsb" LOC = "Y10" ; -NET "cpld_start" LOC = "AA9" ; -NET "cpld_mode" LOC = "U12" ; -NET "cpld_done" LOC = "V12" ; -NET "cpld_din" LOC = "AA14" ; -NET "cpld_clk" LOC = "AB14" ; -NET "cpld_detached" LOC = "V11" ; -NET "cpld_init_b" LOC = "W12" ; -NET "cpld_misc" LOC = "Y12" ; -NET "POR" LOC = "W18" ; -NET "WDI" LOC = "W15" ; -NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; -NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; -NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; -NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; -NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; -NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; -NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; -NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; -NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; -NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; -NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; -NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; -NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; -NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; -NET "adc_ovf_a" LOC = "F18" ; -NET "adc_oen_a" LOC = "E19" ; -NET "adc_pdn_a" LOC = "E20" ; -NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; -NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; -NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; -NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; -NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; -NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; -NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; -NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; -NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; -NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; -NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; -NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; -NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; -NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; -NET "adc_ovf_b" LOC = "B17" ; -NET "adc_oen_b" LOC = "C17" ; -NET "adc_pdn_b" LOC = "D15" ; -NET "dac_a[0]" LOC = "A5" ; -NET "dac_a[1]" LOC = "B5" ; -NET "dac_a[2]" LOC = "C5" ; -NET "dac_a[3]" LOC = "D5" ; -NET "dac_a[4]" LOC = "A4" ; -NET "dac_a[5]" LOC = "B4" ; -NET "dac_a[6]" LOC = "F6" ; -NET "dac_a[7]" LOC = "D10" ; -NET "dac_a[8]" LOC = "D9" ; -NET "dac_a[9]" LOC = "A10" ; -NET "dac_a[10]" LOC = "L2" ; -NET "dac_a[11]" LOC = "L4" ; -NET "dac_a[12]" LOC = "L3" ; -NET "dac_a[13]" LOC = "L6" ; -NET "dac_a[14]" LOC = "L5" ; -NET "dac_a[15]" LOC = "K2" ; -NET "dac_b[0]" LOC = "D11" ; -NET "dac_b[1]" LOC = "E11" ; -NET "dac_b[2]" LOC = "F11" ; -NET "dac_b[3]" LOC = "B10" ; -NET "dac_b[4]" LOC = "C10" ; -NET "dac_b[5]" LOC = "E10" ; -NET "dac_b[6]" LOC = "F10" ; -NET "dac_b[7]" LOC = "A9" ; -NET "dac_b[8]" LOC = "B9" ; -NET "dac_b[9]" LOC = "E9" ; -NET "dac_b[10]" LOC = "F9" ; -NET "dac_b[11]" LOC = "A8" ; -NET "dac_b[12]" LOC = "B8" ; -NET "dac_b[13]" LOC = "D7" ; -NET "dac_b[14]" LOC = "E7" ; -NET "dac_b[15]" LOC = "B6" ; -NET "dac_lock" LOC = "D6" ; -NET "SCL" LOC = "A7" ; -NET "SDA" LOC = "D8" ; -NET "clk_en[0]" LOC = "C4" ; -NET "clk_en[1]" LOC = "D1" ; -NET "clk_sel[0]" LOC = "C3" ; -NET "clk_sel[1]" LOC = "C2" ; -NET "clk_func" LOC = "C12" ; -NET "clk_status" LOC = "B12" ; -NET "clk_fpga_p" LOC = "A11" ; -NET "clk_fpga_n" LOC = "B11" ; -NET "clk_to_mac" LOC = "AB12" ; -NET "pps_in" LOC = "K1" ; -NET "sclk" LOC = "K5" ; -NET "sen_clk" LOC = "K6" ; -NET "sen_dac" LOC = "L1" ; -NET "sdi" LOC = "J1" ; -NET "sdo" LOC = "J2" ; -NET "sen_tx_db" LOC = "C1" ; -NET "sclk_tx_db" LOC = "D3" ; -NET "sdo_tx_db" LOC = "G3" ; -NET "sdi_tx_db" LOC = "G4" ; -NET "sen_tx_adc" LOC = "G2" ; -NET "sclk_tx_adc" LOC = "H1" ; -NET "sdo_tx_adc" LOC = "H2" ; -NET "sdi_tx_adc" LOC = "J4" ; -NET "sen_tx_dac" LOC = "H4" ; -NET "sclk_tx_dac" LOC = "J5" ; -NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" ; -NET "io_tx[1]" LOC = "K3" ; -NET "io_tx[2]" LOC = "G1" ; -NET "io_tx[3]" LOC = "G5" ; -NET "io_tx[4]" LOC = "H5" ; -NET "io_tx[5]" LOC = "F3" ; -NET "io_tx[6]" LOC = "F2" ; -NET "io_tx[7]" LOC = "F5" ; -NET "io_tx[8]" LOC = "G6" ; -NET "io_tx[9]" LOC = "E2" ; -NET "io_tx[10]" LOC = "E1" ; -NET "io_tx[11]" LOC = "E3" ; -NET "io_tx[12]" LOC = "F4" ; -NET "io_tx[13]" LOC = "D2" ; -NET "io_tx[14]" LOC = "D4" ; -NET "io_tx[15]" LOC = "E4" ; -NET "sen_rx_db" LOC = "D22" ; -NET "sclk_rx_db" LOC = "F19" ; -NET "sdo_rx_db" LOC = "G20" ; -NET "sdi_rx_db" LOC = "H19" ; -NET "sen_rx_adc" LOC = "H18" ; -NET "sclk_rx_adc" LOC = "J17" ; -NET "sdo_rx_adc" LOC = "H21" ; -NET "sdi_rx_adc" LOC = "H22" ; -NET "sen_rx_dac" LOC = "J18" ; -NET "sclk_rx_dac" LOC = "J19" ; -NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" ; -NET "io_rx[1]" LOC = "L20" ; -NET "io_rx[2]" LOC = "L19" ; -NET "io_rx[3]" LOC = "L18" ; -NET "io_rx[4]" LOC = "L17" ; -NET "io_rx[5]" LOC = "K22" ; -NET "io_rx[6]" LOC = "K21" ; -NET "io_rx[7]" LOC = "K20" ; -NET "io_rx[8]" LOC = "G22" ; -NET "io_rx[9]" LOC = "G21" ; -NET "io_rx[10]" LOC = "F21" ; -NET "io_rx[11]" LOC = "F20" ; -NET "io_rx[12]" LOC = "G19" ; -NET "io_rx[13]" LOC = "G18" ; -NET "io_rx[14]" LOC = "G17" ; -NET "io_rx[15]" LOC = "E22" ; - -NET "clk_to_mac" TNM_NET = "clk_to_mac"; -TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; - -NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; - -NET "cpld_clk" TNM_NET = "cpld_clk"; -TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; - -NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; -TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; - -NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; -TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; - -NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; - -#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; -#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; -#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; - -#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; -#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/top/u2_rev3/u2_rev3.v b/top/u2_rev3/u2_rev3.v deleted file mode 100644 index 23a825007..000000000 --- a/top/u2_rev3/u2_rev3.v +++ /dev/null @@ -1,432 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u2_rev3 - ( - // Misc, debug - output [5:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - output uart_tx_o, - input uart_rx_i, - - // Expansion - input exp_pps_in_p, // Diff - input exp_pps_in_n, // Diff - output exp_pps_out_p, // Diff - output exp_pps_out_n, // Diff - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, // AA9 - output cpld_mode, // U12 - output cpld_done, // V12 - input cpld_din, // AA14 Now shared with CFG_Din - input cpld_clk, // AB14 serial clock - input cpld_detached,// V11 unused - output cpld_init_b, // W12 unused dual purpose - output cpld_misc, // Y12 - - // Watchdog interface - input POR, - output WDI, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output reg [15:0] dac_a, - output reg [15:0] dac_b, - input dac_lock, // unused for now - - // I2C - inout SCL, - inout SDA, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Clocks - input clk_fpga_p, // Diff - input clk_fpga_n, // Diff - input clk_to_mac, - input pps_in, - - // Generic SPI - output sclk, - output sen_clk, - output sen_dac, - output sdi, - input sdo, - - // TX DBoard - output sen_tx_db, - output sclk_tx_db, - input sdo_tx_db, - output sdi_tx_db, - - output sen_tx_adc, - output sclk_tx_adc, - input sdo_tx_adc, - output sdi_tx_adc, - - output sen_tx_dac, - output sclk_tx_dac, - output sdi_tx_dac, - - inout [15:0] io_tx, - - // RX DBoard - output sen_rx_db, - output sclk_rx_db, - input sdo_rx_db, - output sdi_rx_db, - - output sen_rx_adc, - output sclk_rx_adc, - input sdo_rx_adc, - output sdi_rx_adc, - - output sen_rx_dac, - output sclk_rx_dac, - output sdi_rx_dac, - - inout [15:0] io_rx - ); - - assign cpld_init_b = 0; - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - wire clk90, clk180, clk270; - - // reset the watchdog continuously - reg [15:0] wd; - wire config_success; - - always @(posedge wb_clk) - if(~config_success) - wd <= 0; - else - wd <= wd + 1; - assign WDI = wd[15]; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire exp_pps_in; - IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); - defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_pps_out; - OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); - defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge clk_fpga) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - - wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; - assign adc_oen_a = ~adc_oe_a; - assign adc_oen_b = ~adc_oe_b; - assign adc_pdn_a = ~adc_on_a; - assign adc_pdn_b = ~adc_on_b; - - reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; - reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; - - always @(posedge dsp_clk) - begin - adc_a_reg1 <= adc_a; - adc_b_reg1 <= adc_b; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_b_reg1 <= adc_ovf_b; - end - - always @(posedge dsp_clk) - begin - adc_a_reg2 <= adc_a_reg1; - adc_b_reg2 <= adc_b_reg1; - adc_ovf_a_reg2 <= adc_ovf_a_reg1; - adc_ovf_b_reg2 <= adc_ovf_b_reg1; - end // always @ (posedge dsp_clk) - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(clk90), - .CLK180(clk180), - .CLK270(clk270), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [5:0] leds_int; - assign leds = 6'b011111 ^ leds_int; // all except eth are active-low - - // SPI - wire miso, mosi, sclk_int; - assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; - - assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | - (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | - (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - wire [15:0] dac_a_int, dac_b_int; - always @(negedge dsp_clk) dac_a <= dac_a_int; - always @(negedge dsp_clk) dac_b <= dac_b_int; - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_misc (cpld_misc), - .cpld_init_b (cpld_init_b), - .por (~POR), - .config_success (config_success), - .adc_a (adc_a_reg2), - .adc_ovf_a (adc_ovf_a_reg2), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b_reg2), - .adc_ovf_b (adc_ovf_b_reg2), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a_int), - .dac_b (dac_b_int), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); - -endmodule // u2_rev2 diff --git a/top/u2_rev3_2rx_iad/Makefile b/top/u2_rev3_2rx_iad/Makefile deleted file mode 100644 index 5b7ed5a8e..000000000 --- a/top/u2_rev3_2rx_iad/Makefile +++ /dev/null @@ -1,254 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/integrate.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v \ -top/u2_rev3_2rx_iad/u2_core.v \ -top/u2_rev3_2rx_iad/dsp_core_rx.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, testbench, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -testbench: - iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v - -clean: - rm -rf $(BUILD_DIR) - rm -f dsp_core_tb - rm -f *.lx2 - rm -f *.dat - rm -f *.vcd diff --git a/top/u2_rev3_2rx_iad/README b/top/u2_rev3_2rx_iad/README deleted file mode 100644 index 3efc5305b..000000000 --- a/top/u2_rev3_2rx_iad/README +++ /dev/null @@ -1,32 +0,0 @@ -This is a custom build for USRP2 FPGA. It allows using a BasicRX or -LFRX board and feed two independent, real signals. In addition, instead -of the CIC/HB decimator, which optimizes frequency response, it uses an -integrate and dump decimator, which optimizes for time-domain impulse -response. - -These changes have been made in dsp_core_rx.v: - -* A second DDC has been added, sharing a frequency register with - the existing DDC. - -* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... - into the receive FIFO. This limits the host configured decimation - to 8 intead of 4. Use gr.deinterleave to recover the streams. - -* The ADCs are hardcoded: - - RX_A ==> DDC #1 I-input - 0 ==> DDC #1 Q-input - RX_B ==> DDC #2 I-input - 0 ==> DDC #2 Q-input - - Thus, the input mux has been disabled. - -* The CIC/HB decimator has been replaced by an integrate and dump at - the decimation rate. - -* To assist with meeting timing, the external RAM has been disabled. - -The basic application is to coherently sample two real IF streams and -downconvert to baseband, while minimizing the impulse response duration -of the resampling filters. diff --git a/top/u2_rev3_2rx_iad/cmdfile b/top/u2_rev3_2rx_iad/cmdfile deleted file mode 100644 index 34373a676..000000000 --- a/top/u2_rev3_2rx_iad/cmdfile +++ /dev/null @@ -1,4 +0,0 @@ --y . --y ../../sdr_lib --y ../../control_lib --y ../../models diff --git a/top/u2_rev3_2rx_iad/dsp_core_rx.v b/top/u2_rev3_2rx_iad/dsp_core_rx.v deleted file mode 100644 index 4a945bd1a..000000000 --- a/top/u2_rev3_2rx_iad/dsp_core_rx.v +++ /dev/null @@ -1,212 +0,0 @@ -`define DSP_CORE_RX_BASE 160 -module dsp_core_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - input [15:0] io_rx, - - output reg [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic_a, q_cordic_a, i_cordic_b, q_cordic_b; - wire [31:0] i_iad_a, q_iad_a, i_iad_b, q_iad_b; - wire [15:0] i_out_a, q_out_a, i_out_b, q_out_b; - - wire enable_hb1, enable_hb2; // Correspond to std firmware settings - wire [7:0] cic_decim; // for combined CIC/HB decimator - wire [9:0] decim_rate; // Reconstructed original decimation setting - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - -`ifdef MUXCTRL - wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); -`endif - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - -`ifdef MUXCTRL - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) -`else // !`ifdef MUXCTRL - always @(posedge clk) - begin - adc_i <= adc_a_ofs; - adc_q <= adc_b_ofs; - end -`endif // !`ifdef MUXCTRL - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - // Route I,0 to first CORDIC - cordic_z24 #(.bitwidth(24)) - cordic_a(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[24:1]),. yi(0), .zi(phase[31:8]), - .xo(i_cordic_a),.yo(q_cordic_a),.zo() ); - - // Route Q,0 to second CORDIC - cordic_z24 #(.bitwidth(24)) - cordic_b(.clock(clk), .reset(rst), .enable(run), - .xi(prod_q[24:1]),. yi(0), .zi(phase[31:8]), - .xo(i_cordic_b),.yo(q_cordic_b),.zo() ); - - // Reconstruct original decimation rate from standard firmware settings - assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : - {1'b0,cic_decim,1'b0 }) : - cic_decim; - - cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_fast(1),.strobe_slow(strobe_iad) ); - - wire strobe_iad_o; - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_a - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic_a), - .stb_o(strobe_iad_o),.integ_o(i_iad_a) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_a - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic_a), - .stb_o(),.integ_o(q_iad_a) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_b - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic_b), - .stb_o(),.integ_o(i_iad_b) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_b - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic_b), - .stb_o(),.integ_o(q_iad_b) ); - - round #(.bits_in(32),.bits_out(16)) round_iout_a (.in(i_iad_a),.out(i_out_a)); - round #(.bits_in(32),.bits_out(16)) round_qout_a (.in(q_iad_a),.out(q_out_a)); - round #(.bits_in(32),.bits_out(16)) round_iout_b (.in(i_iad_b),.out(i_out_b)); - round #(.bits_in(32),.bits_out(16)) round_qout_b (.in(q_iad_b),.out(q_out_b)); - - reg [31:0] sample_out_a, sample_out_b, sample_out; - reg stb_d1, stb_d2, stb_d3, stb_d4, stb_d5; - reg strobe_out; - - // Register samples on strobe_iad - // Output A on d1 - // Output B on d5 - always @(posedge clk) - begin - stb_d1 <= strobe_iad_o; - stb_d2 <= stb_d1; - stb_d3 <= stb_d2; - stb_d4 <= stb_d3; - stb_d5 <= stb_d4; - end - - always @(posedge clk) - if (strobe_iad_o) - begin - // Streaming GPIO - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - sample_out_a <= {i_out_a[15:1], gpio_ena[0] ? io_rx[15] : i_out_a[0], - q_out_a[15:1], gpio_ena[1] ? io_rx[14] : q_out_a[0] }; - sample_out_b <= {i_out_b[15:1], gpio_ena[0] ? io_rx[15] : i_out_b[0], - q_out_b[15:1], gpio_ena[1] ? io_rx[14] : q_out_b[0] }; - end - - always @(posedge clk) - begin - if (stb_d1) - sample <= sample_out_a; - else if (stb_d5) - sample <= sample_out_b; - strobe_out <= stb_d1|stb_d5; - end - - assign strobe = strobe_out; - assign debug = 0; - -endmodule // dsp_core_rx diff --git a/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/top/u2_rev3_2rx_iad/dsp_core_tb.sav deleted file mode 100644 index 12f746860..000000000 --- a/top/u2_rev3_2rx_iad/dsp_core_tb.sav +++ /dev/null @@ -1,106 +0,0 @@ -[size] 1680 975 -[pos] -1 -1 -*-17.007835 70679400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dsp_core_tb. -@200 --SYSCON -@28 -dsp_core_tb.clk -dsp_core_tb.rst -dsp_core_tb.run -@200 -- --Settings Bus -@22 -dsp_core_tb.set_addr[7:0] -@24 -dsp_core_tb.set_data[31:0] -@28 -dsp_core_tb.set_stb -@200 -- --RX DSP CORE -@22 -dsp_core_tb.rx_path.adc_a[13:0] -dsp_core_tb.rx_path.adc_b[13:0] -@28 -dsp_core_tb.rx_path.adc_ovf_a -dsp_core_tb.rx_path.adc_ovf_b -@22 -dsp_core_tb.rx_path.io_rx[15:0] -@200 -- -@22 -dsp_core_tb.rx_path.sample[31:0] -@28 -dsp_core_tb.rx_path.strobe -@200 -- -@22 -dsp_core_tb.rx_path.phase_inc[31:0] -dsp_core_tb.rx_path.scale_i[15:0] -dsp_core_tb.rx_path.scale_q[15:0] -@28 -dsp_core_tb.rx_path.enable_hb1 -dsp_core_tb.rx_path.enable_hb2 -@22 -dsp_core_tb.rx_path.cic_decim[7:0] -dsp_core_tb.rx_path.adc_a_ofs[13:0] -dsp_core_tb.rx_path.adc_b_ofs[13:0] -dsp_core_tb.rx_path.muxctrl[3:0] -@200 -- -@22 -dsp_core_tb.rx_path.adc_i[13:0] -dsp_core_tb.rx_path.adc_q[13:0] -dsp_core_tb.rx_path.phase[31:0] -dsp_core_tb.rx_path.prod_i[35:0] -dsp_core_tb.rx_path.prod_q[35:0] -@8420 -dsp_core_tb.rx_path.i_cordic_a[23:0] -dsp_core_tb.rx_path.q_cordic_a[23:0] -dsp_core_tb.rx_path.i_cordic_b[23:0] -dsp_core_tb.rx_path.q_cordic_b[23:0] -@22 -dsp_core_tb.rx_path.decim_rate[9:0] -@28 -dsp_core_tb.rx_path.strobe_iad -@22 -dsp_core_tb.rx_path.i_iad_a[31:0] -dsp_core_tb.rx_path.q_iad_a[31:0] -@23 -dsp_core_tb.rx_path.i_iad_b[31:0] -@22 -dsp_core_tb.rx_path.q_iad_b[31:0] -@28 -dsp_core_tb.rx_path.strobe_iad_o -@8420 -dsp_core_tb.rx_path.i_out_a[15:0] -dsp_core_tb.rx_path.q_out_a[15:0] -dsp_core_tb.rx_path.i_out_b[15:0] -dsp_core_tb.rx_path.q_out_b[15:0] -@28 -dsp_core_tb.rx_path.gpio_ena[1:0] -@22 -dsp_core_tb.rx_path.sample_out_a[31:0] -dsp_core_tb.rx_path.sample_out_b[31:0] -dsp_core_tb.rx_path.sample[31:0] -@28 -dsp_core_tb.rx_path.strobe_out -dsp_core_tb.rx_path.stb_d1 -dsp_core_tb.rx_path.stb_d2 -dsp_core_tb.rx_path.stb_d3 -dsp_core_tb.rx_path.stb_d4 -dsp_core_tb.rx_path.stb_d5 -@200 -- --FIFO Bus -@22 -dsp_core_tb.master_time[31:0] -dsp_core_tb.wr_dat[31:0] -@28 -dsp_core_tb.wr_done -dsp_core_tb.wr_error -dsp_core_tb.wr_full -dsp_core_tb.wr_ready -dsp_core_tb.wr_write diff --git a/top/u2_rev3_2rx_iad/dsp_core_tb.v b/top/u2_rev3_2rx_iad/dsp_core_tb.v deleted file mode 100644 index d947df40a..000000000 --- a/top/u2_rev3_2rx_iad/dsp_core_tb.v +++ /dev/null @@ -1,233 +0,0 @@ -`timescale 1ns / 100ps - -module dsp_core_tb; - -/////////////////////////////////////////////////////////////////////////////////// -// Sim-wide wires/busses // -/////////////////////////////////////////////////////////////////////////////////// - - // System control bus - reg clk = 0; - reg rst = 1; - - // Configuration bus - reg set_stb = 0; - reg [7:0] set_addr = 0; - reg [31:0] set_data = 0; - - // ADC input bus - wire signed [13:0] adc_a; - wire signed [13:0] adc_b; - wire adc_ovf_a; - wire adc_ovf_b; - - // RX sample bus - reg run = 1; - wire [31:0] sample; - wire stb; - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation control // -/////////////////////////////////////////////////////////////////////////////////// - - // Set up output files - initial begin - $dumpfile("dsp_core_tb.vcd"); - $dumpvars(0,dsp_core_tb); - end - - // Update display every 10 us - always #1000 $monitor("Time in us ",$time/1000); - - // Generate master clock 50% @ 100 MHz - always - #5 clk = ~clk; - -/////////////////////////////////////////////////////////////////////////////////// -// Unit(s) under test // -/////////////////////////////////////////////////////////////////////////////////// - - reg [13:0] amplitude = 13'h1fff; - reg [15:0] impulse_len = 0; - reg [15:0] zero_len = 0; - reg adc_ena = 0; - - initial #500 @(posedge clk) adc_ena = 1; - - impulse adc - (.clk(clk),.rst(rst),.ena(adc_ena), - .dc_offset_a(0),.dc_offset_b(0), - .amplitude(amplitude), - .impulse_len(impulse_len),.zero_len(zero_len), - .adc_a(adc_a),.adc_b(adc_b), - .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); - - initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's - initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset - dsp_core_rx rx_path - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(16'b0), - .run(adc_ena),.sample(sample),.strobe(stb), - .debug() ); - - reg [31:0] master_time = 0; - always @(posedge clk) - master_time <= master_time + 1; - - reg wr_ready = 1; - reg wr_full = 0; - - wire [31:0] wr_dat; - wire wr_write; - wire wr_done; - wire wr_error; - wire [15:0] fifo_occupied; - wire fifo_full; - wire fifo_empty; - - rx_control rx_buffer - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time), - .overrun(), // unconnected output - .wr_dat_o(wr_dat), - .wr_write_o(wr_write), - .wr_done_o(wr_done), - .wr_error_o(wr_error), - .wr_ready_i(wr_ready), - .wr_full_i(wr_full), - .sample(sample), - .run(), // unconnected output, supposed to drive 'run' - .strobe(stb), - .fifo_occupied(fifo_occupied), - .fifo_full(fifo_full), - .fifo_empty(fifo_empty), - .debug_rx() // unconnected output - ); - - - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation output/checking // -/////////////////////////////////////////////////////////////////////////////////// - - integer rx_file; - - initial - rx_file = $fopen("rx.dat", "wb"); - - always @(posedge clk) - begin - // Write RX sample I&Q in format Octave can load - if (stb) - begin - $fwrite(rx_file, sample[31:16]); - $fputc(32, rx_file); - $fwrite(rx_file, sample[15:0]); - $fputc(13, rx_file); - end - end - -/////////////////////////////////////////////////////////////////////////////////// -// Tasks // -/////////////////////////////////////////////////////////////////////////////////// - - task power_on; - begin - @(posedge clk) - rst = #1 1'b1; - @(posedge clk) - rst = #1 1'b0; - end - endtask // power_on - - task set_impulse_len; - input [15:0] len; - @(posedge clk) impulse_len = len-1; - endtask - - task set_zero_len; - input [15:0] len; - @(posedge clk) zero_len = len-1; - endtask - - // Strobe configuration bus with addr, data - task write_cfg_register; - input [7:0] regno; - input [31:0] value; - - begin - @(posedge clk); - set_addr <= regno; - set_data <= value; - set_stb <= 1'b1; - @(posedge clk); - set_stb <= 1'b0; - end - endtask // write_cfg_register - - // Set RX DDC frequency - task set_ddc_freq; - input [31:0] freq; - - write_cfg_register(160, freq); - endtask // set_ddc_freq - - // Set RX IQ scaling registers - task set_rx_scale_iq; - input [15:0] scale_i; - input [15:0] scale_q; - - write_cfg_register(161, {scale_i,scale_q}); - endtask // set_rx_scale_iq - - // Set RX MUX control - task set_rx_muxctrl; - input [3:0] muxctrl; - - write_cfg_register(168, muxctrl); - endtask // set_rx_muxctrl - - // Set RX CIC decim and halfband enables - task set_decim; - input hb1_ena; - input hb2_ena; - input [7:0] decim; - - write_cfg_register(162, {hb1_ena,hb2_ena,decim}); - endtask // set_decim - - -/////////////////////////////////////////////////////////////////////////////////// -// Individual tests // -/////////////////////////////////////////////////////////////////////////////////// - - task test_rx; - begin - set_impulse_len(10); - set_zero_len(990); - set_rx_muxctrl(1); - set_ddc_freq(32'h10000000); - set_rx_scale_iq(1243, 1243); - set_decim(1, 1, 1); - - #100000 $finish; - end - endtask // test_rx - - -/////////////////////////////////////////////////////////////////////////////////// -// Top-level test // -/////////////////////////////////////////////////////////////////////////////////// - - // Execute tests - initial - begin - power_on(); - test_rx(); - end - -endmodule // dsp_core_tb diff --git a/top/u2_rev3_2rx_iad/impulse.v b/top/u2_rev3_2rx_iad/impulse.v deleted file mode 100644 index fc5e3c1ed..000000000 --- a/top/u2_rev3_2rx_iad/impulse.v +++ /dev/null @@ -1,68 +0,0 @@ -module impulse - (input clk, - input rst, - input ena, - - input [13:0] dc_offset_a, - input [13:0] dc_offset_b, - input [13:0] amplitude, - input [15:0] impulse_len, - input [15:0] zero_len, - - output [13:0] adc_a, - output [13:0] adc_b, - output adc_ovf_a, - output adc_ovf_b - ); - - reg [13:0] adc_a_int = 0; - reg [13:0] adc_b_int = 0; - - reg [15:0] count; - - localparam ST_ZERO = 0; - localparam ST_HIGH = 1; - reg state; - - always @(posedge clk) - if (rst | ~ena) - begin - adc_a_int <= 0; - adc_b_int <= 0; - count <= 0; - state <= ST_ZERO; - end - else - case(state) - ST_ZERO: - if (count == zero_len) - begin - adc_a_int <= amplitude; - adc_b_int <= amplitude >> 2; - state <= ST_HIGH; - count <= 0; - end - else - count <= count + 1; - - ST_HIGH: - if (count == impulse_len) - begin - adc_a_int <= 0; - adc_b_int <= 0; - state <= ST_ZERO; - count <= 0; - end - else - count <= count + 1; - - endcase // case (state) - - assign adc_a = adc_a_int + dc_offset_a; - assign adc_b = adc_b_int + dc_offset_b; - - // Ignore for now - assign adc_ovf_a = 0; - assign adc_ovf_b = 0; - -endmodule // impulse diff --git a/top/u2_rev3_2rx_iad/u2_core.v b/top/u2_rev3_2rx_iad/u2_core.v deleted file mode 100755 index 3d96a4e0e..000000000 --- a/top/u2_rev3_2rx_iad/u2_core.v +++ /dev/null @@ -1,789 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=32768) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, - s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc; - wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err; - wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we; - - wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), - .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10), - .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10), - .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10), - .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty), - .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb), - .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty), - .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb), - .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty), - .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb), - .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty), - .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb), - .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty), - .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb), - .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty), - .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // Buffer Pool, slave #1 - wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop; - wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop; - wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop; - wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done), - .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full), - .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done), - .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full), - .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done), - .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full), - .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done), - .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full), - // Read Interfaces - .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done), - .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop), - .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done), - .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop), - .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done), - .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop), - .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done), - .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop) - ); - - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - assign s2_rty = 1'b0; - - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - assign s3_err = 1'b0; - assign s3_rty = 1'b0; - - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - assign s4_err = 1'b0; - assign s4_rty = 1'b0; - - // Buffer Pool Status -- Slave #5 - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), - .wb_rst_i(wb_rst), - .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), - .wb_dat_o(s5_dat_i), - .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) - ); - - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - - // Slave, #6 Ethernet MAC, see below - - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_err = 1'b0; - assign s7_rty = 1'b0; - assign s7_dat_i = 32'd0; - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; - - setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop; - wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err; - wire [31:0] Tx_mac_data, Rx_mac_data; - wire [1:0] Tx_mac_BE, Rx_mac_BE; - wire rst_mac; - - oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac)); - - MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11)) - MAC_top - (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk), - .rst_mac(rst_mac),.rst_user(dsp_rst), - .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]), - .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE), - .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD), - .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD), - .Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2), - .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), - .debug0(debug_mac0),.debug1(debug_mac1) ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - mac_rxfifo_int mac_rxfifo_int - (.clk(dsp_clk),.rst(dsp_rst), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), - .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop), - .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done), - .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full), - .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) ); - - mac_txfifo_int mac_txfifo_int - (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done), - .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop), - .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) ); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; - - simple_pic #(.is(16),.dwidth(32)) simple_pic - (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - assign s8_err = 0; - assign s8_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - assign s9_err = 0; - assign s9_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack), - .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - assign s10_err = 0; - assign s10_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), - .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - assign s11_err = 0; - assign s11_rty = 0; - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps_in; - always @(posedge dsp_clk) pps_posedge <= pps_in; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]), - .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - assign s12_err = 0; - assign s12_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we), - .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i), - .wb_ack_o(s13_ack) ); - assign s13_err = 0; - assign s13_rty = 0; - // ///////////////////////////////////////////////////////////////////////// - // DSP - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error), - .wr_ready_i(wr1_ready), .wr_full_i(wr1_full), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); - - // dummy_rx dsp_core_rx - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop), - .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error), - .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error), - .wr_ready_i(wr0_ready),.wr_full_i(wr0_full), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - -`ifdef EXTRAM - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel), - .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign s14_err = 0; assign s14_rty = 0; - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; -`endif - -`ifdef DEBUG - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = 0; - assign debug_clk[1] = dsp_clk; - - assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; -`endif - -endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/top/u2_rev3_2rx_iad/wave.sh b/top/u2_rev3_2rx_iad/wave.sh deleted file mode 100755 index 626f224e5..000000000 --- a/top/u2_rev3_2rx_iad/wave.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/top/u2_rev3_iad/.gitignore b/top/u2_rev3_iad/.gitignore deleted file mode 100644 index e4daaf1ea..000000000 --- a/top/u2_rev3_iad/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/build -/*.vcd -/dsp_core_tb -/*.dat diff --git a/top/u2_rev3_iad/Makefile b/top/u2_rev3_iad/Makefile deleted file mode 100644 index 5ae8846dd..000000000 --- a/top/u2_rev3_iad/Makefile +++ /dev/null @@ -1,254 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/integrate.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v \ -top/u2_rev3_iad/dsp_core_rx.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, testbench, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -testbench: - iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v - -clean: - rm -rf $(BUILD_DIR) - rm -f dsp_core_tb - rm -f *.lx2 - rm -f *.dat - rm -f *.vcd diff --git a/top/u2_rev3_iad/cmdfile b/top/u2_rev3_iad/cmdfile deleted file mode 100644 index 34373a676..000000000 --- a/top/u2_rev3_iad/cmdfile +++ /dev/null @@ -1,4 +0,0 @@ --y . --y ../../sdr_lib --y ../../control_lib --y ../../models diff --git a/top/u2_rev3_iad/dsp_core_rx.v b/top/u2_rev3_iad/dsp_core_rx.v deleted file mode 100644 index 2882464ba..000000000 --- a/top/u2_rev3_iad/dsp_core_rx.v +++ /dev/null @@ -1,158 +0,0 @@ -`define DSP_CORE_RX_BASE 160 -module dsp_core_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - input [15:0] io_rx, - - output [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic, q_cordic; - wire [31:0] i_iad, q_iad; - wire [15:0] i_out, q_out; - - wire enable_hb1, enable_hb2; // Correspond to std firmware settings - wire [7:0] cic_decim; // for combined CIC/HB decimator - wire [9:0] decim_rate; // Reconstructed original decimation setting - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - - wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - cordic_z24 #(.bitwidth(24)) - cordic(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]), - .xo(i_cordic),.yo(q_cordic),.zo() ); - - // Reconstruct original decimation rate from standard firmware settings - assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : - {1'b0,cic_decim,1'b0 }) : - cic_decim; - - cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_fast(1),.strobe_slow(strobe_iad) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic), - .stb_o(strobe),.integ_o(i_iad) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic), - .stb_o(),.integ_o(q_iad) ); - - round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out)); - round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out)); - - // Streaming GPIO - // - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - - reg [31:0] sample_reg; - always @(posedge clk) - begin - sample_reg[31:17] <= i_out[15:1]; - sample_reg[15:1] <= q_out[15:1]; - sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; - sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; - end - - assign sample = sample_reg; - assign debug = {clk, rst, run, strobe}; - -endmodule // dsp_core_rx diff --git a/top/u2_rev3_iad/dsp_core_tb.sav b/top/u2_rev3_iad/dsp_core_tb.sav deleted file mode 100644 index 17c90cdd7..000000000 --- a/top/u2_rev3_iad/dsp_core_tb.sav +++ /dev/null @@ -1,61 +0,0 @@ -[size] 1680 975 -[pos] -1 -1 -*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dsp_core_tb. -@200 --SYSCON -@28 -dsp_core_tb.clk -dsp_core_tb.rst -dsp_core_tb.run -@200 -- --Settings Bus -@22 -dsp_core_tb.set_addr[7:0] -@24 -dsp_core_tb.set_data[31:0] -@28 -dsp_core_tb.set_stb -@200 -- --RX DSP CORE -- -@24 -dsp_core_tb.rx_path.decim_rate[9:0] -@200 -- -@8420 -dsp_core_tb.adc_a[13:0] -@20000 -- -@200 -- -@8420 -dsp_core_tb.rx_path.adc_a_ofs[13:0] -@20000 -- -@200 -- -@8022 -dsp_core_tb.rx_path.i_cordic[23:0] -@20000 -- -@200 -- -@8022 -dsp_core_tb.rx_path.i_iad[31:0] -@20000 -- -@200 -- -@8420 -dsp_core_tb.rx_path.i_out[15:0] -@20000 -- -@200 -- -@28 -dsp_core_tb.stb -@200 -- diff --git a/top/u2_rev3_iad/dsp_core_tb.v b/top/u2_rev3_iad/dsp_core_tb.v deleted file mode 100644 index 4d5a5b537..000000000 --- a/top/u2_rev3_iad/dsp_core_tb.v +++ /dev/null @@ -1,196 +0,0 @@ -`timescale 1ns / 100ps - -module dsp_core_tb; - -/////////////////////////////////////////////////////////////////////////////////// -// Sim-wide wires/busses // -/////////////////////////////////////////////////////////////////////////////////// - - // System control bus - reg clk = 0; - reg rst = 1; - - // Configuration bus - reg set_stb = 0; - reg [7:0] set_addr = 0; - reg [31:0] set_data = 0; - - // ADC input bus - wire signed [13:0] adc_a; - wire signed [13:0] adc_b; - wire adc_ovf_a; - wire adc_ovf_b; - - // RX sample bus - reg run = 1; - wire [31:0] sample; - wire stb; - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation control // -/////////////////////////////////////////////////////////////////////////////////// - - // Set up output files - initial begin - $dumpfile("dsp_core_tb.vcd"); - $dumpvars(0,dsp_core_tb); - end - - // Update display every 10 us - always #1000 $monitor("Time in us ",$time/1000); - - // Generate master clock 50% @ 100 MHz - always - #5 clk = ~clk; - -/////////////////////////////////////////////////////////////////////////////////// -// Unit(s) under test // -/////////////////////////////////////////////////////////////////////////////////// - - reg [13:0] amplitude = 13'h1fff; - reg [15:0] impulse_len = 0; - reg [15:0] zero_len = 0; - reg adc_ena = 0; - - initial #500 @(posedge clk) adc_ena = 1; - - impulse adc - (.clk(clk),.rst(rst),.ena(adc_ena), - .dc_offset_a(0),.dc_offset_b(0), - .amplitude(amplitude), - .impulse_len(impulse_len),.zero_len(zero_len), - .adc_a(adc_a),.adc_b(adc_b), - .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); - - initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's - initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset - dsp_core_rx rx_path - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(16'b0), - .run(adc_ena),.sample(sample),.strobe(stb), - .debug() ); - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation output/checking // -/////////////////////////////////////////////////////////////////////////////////// - - integer rx_file; - - initial - rx_file = $fopen("rx.dat", "wb"); - - always @(posedge clk) - begin - // Write RX sample I&Q in format Octave can load - if (stb) - begin - $fwrite(rx_file, sample[31:16]); - $fputc(32, rx_file); - $fwrite(rx_file, sample[15:0]); - $fputc(13, rx_file); - end - end - -/////////////////////////////////////////////////////////////////////////////////// -// Tasks // -/////////////////////////////////////////////////////////////////////////////////// - - task power_on; - begin - @(posedge clk) - rst = #1 1'b1; - @(posedge clk) - rst = #1 1'b0; - end - endtask // power_on - - task set_impulse_len; - input [15:0] len; - @(posedge clk) impulse_len = len-1; - endtask - - task set_zero_len; - input [15:0] len; - @(posedge clk) zero_len = len-1; - endtask - - // Strobe configuration bus with addr, data - task write_cfg_register; - input [7:0] regno; - input [31:0] value; - - begin - @(posedge clk); - set_addr <= regno; - set_data <= value; - set_stb <= 1'b1; - @(posedge clk); - set_stb <= 1'b0; - end - endtask // write_cfg_register - - // Set RX DDC frequency - task set_ddc_freq; - input [31:0] freq; - - write_cfg_register(160, freq); - endtask // set_ddc_freq - - // Set RX IQ scaling registers - task set_rx_scale_iq; - input [15:0] scale_i; - input [15:0] scale_q; - - write_cfg_register(161, {scale_i,scale_q}); - endtask // set_rx_scale_iq - - // Set RX MUX control - task set_rx_muxctrl; - input [3:0] muxctrl; - - write_cfg_register(168, muxctrl); - endtask // set_rx_muxctrl - - // Set RX CIC decim and halfband enables - task set_decim; - input hb1_ena; - input hb2_ena; - input [7:0] decim; - - write_cfg_register(162, {hb1_ena,hb2_ena,decim}); - endtask // set_decim - - -/////////////////////////////////////////////////////////////////////////////////// -// Individual tests // -/////////////////////////////////////////////////////////////////////////////////// - - task test_rx; - begin - set_impulse_len(1); - set_zero_len(999); - set_rx_muxctrl(1); - set_ddc_freq(0); - set_rx_scale_iq(1243, 1243); - set_decim(0, 1, 3); - - #100000 $finish; - end - endtask // test_rx - - -/////////////////////////////////////////////////////////////////////////////////// -// Top-level test // -/////////////////////////////////////////////////////////////////////////////////// - - // Execute tests - initial - begin - power_on(); - test_rx(); - end - -endmodule // dsp_core_tb diff --git a/top/u2_rev3_iad/impulse.v b/top/u2_rev3_iad/impulse.v deleted file mode 100644 index 7f0cdc9be..000000000 --- a/top/u2_rev3_iad/impulse.v +++ /dev/null @@ -1,63 +0,0 @@ -module impulse - (input clk, - input rst, - input ena, - - input [13:0] dc_offset_a, - input [13:0] dc_offset_b, - input [13:0] amplitude, - input [15:0] impulse_len, - input [15:0] zero_len, - - output [13:0] adc_a, - output [13:0] adc_b, - output adc_ovf_a, - output adc_ovf_b - ); - - reg [13:0] adc_a_int = 0; - reg [15:0] count; - - localparam ST_ZERO = 0; - localparam ST_HIGH = 1; - reg state; - - always @(posedge clk) - if (rst | ~ena) - begin - adc_a_int <= 0; - count <= 0; - state <= ST_ZERO; - end - else - case(state) - ST_ZERO: - if (count == zero_len) - begin - adc_a_int <= amplitude; - state <= ST_HIGH; - count <= 0; - end - else - count <= count + 1; - - ST_HIGH: - if (count == impulse_len) - begin - adc_a_int <= 0; - state <= ST_ZERO; - count <= 0; - end - else - count <= count + 1; - - endcase // case (state) - - assign adc_a = adc_a_int + dc_offset_a; - - // Ignore for now - assign adc_b = dc_offset_b; - assign adc_ovf_a = 0; - assign adc_ovf_b = 0; - -endmodule // impulse diff --git a/top/u2_rev3_iad/wave.sh b/top/u2_rev3_iad/wave.sh deleted file mode 100755 index 626f224e5..000000000 --- a/top/u2_rev3_iad/wave.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/top/u2plus/u2plus.ucf b/top/u2plus/u2plus.ucf deleted file mode 100755 index 091eb2005..000000000 --- a/top/u2plus/u2plus.ucf +++ /dev/null @@ -1,354 +0,0 @@ -NET "DAC_LOCK" LOC = "P4" ; -NET "ADC_clkout_p" LOC = "P1" ; -NET "ADC_clkout_n" LOC = "P2" ; -NET "io_rx<15>" LOC = "AD1" ; -NET "io_rx<14>" LOC = "AD2" ; -NET "io_rx<13>" LOC = "AC2" ; -NET "io_rx<12>" LOC = "AC3" ; -NET "io_rx<11>" LOC = "W7" ; -NET "io_rx<10>" LOC = "W6" ; -NET "io_rx<09>" LOC = "U9" ; -NET "io_rx<08>" LOC = "V8" ; -NET "io_rx<07>" LOC = "AB1" ; -NET "io_rx<06>" LOC = "AC1" ; -NET "io_rx<05>" LOC = "V7" ; -NET "io_rx<04>" LOC = "V6" ; -NET "io_rx<03>" LOC = "Y5" ; -NET "ADCB_2_3_p" LOC = "U7" ; -NET "ADCB_2_3_n" LOC = "U8" ; -NET "ADCB_0_1_p" LOC = "AA2" ; -NET "ADCB_0_1_n" LOC = "AA3" ; -NET "ADCA_12_13_p" LOC = "Y1" ; -NET "ADCA_12_13_n" LOC = "Y2" ; -NET "ADCA_10_11_p" LOC = "W3" ; -NET "ADCA_10_11_n" LOC = "W4" ; -NET "ADCA_8_9_p" LOC = "T7" ; -NET "ADCA_8_9_n" LOC = "U6" ; -NET "ADCA_6_7_p" LOC = "U5" ; -NET "ADCA_6_7_n" LOC = "V5" ; -NET "ADCA_4_5_p" LOC = "T10" ; -NET "ADCA_4_5_n" LOC = "T9" ; -NET "ADCA_2_3_p" LOC = "V1" ; -NET "ADCA_2_3_n" LOC = "V2" ; -NET "ADCA_0_1_p" LOC = "R8" ; -NET "ADCA_0_1_n" LOC = "R7" ; -NET "TX00_A" LOC = "P8" ; -NET "TX01_A" LOC = "P9" ; -NET "TX02_A" LOC = "R5" ; -NET "TX03_A" LOC = "R6" ; -NET "TX04_A" LOC = "P7" ; -NET "TX05_A" LOC = "P6" ; -NET "TX06_A" LOC = "T3" ; -NET "TX07_A" LOC = "T4" ; -NET "TX08_A" LOC = "R3" ; -NET "TX09_A" LOC = "R4" ; -NET "TX10_A" LOC = "R2" ; -NET "TX11_A" LOC = "N1" ; -NET "TX12_A" LOC = "N2" ; -NET "TX13_A" LOC = "N5" ; -NET "TX14_A" LOC = "N4" ; -NET "TX15_A" LOC = "M2" ; -NET "TX00_B" LOC = "M5" ; -NET "TX01_B" LOC = "M6" ; -NET "TX02_B" LOC = "M4" ; -NET "TX03_B" LOC = "M3" ; -NET "TX04_B" LOC = "M8" ; -NET "TX05_B" LOC = "M7" ; -NET "TX06_B" LOC = "L4" ; -NET "TX07_B" LOC = "L3" ; -NET "TX08_B" LOC = "K3" ; -NET "TX09_B" LOC = "K2" ; -NET "TX10_B" LOC = "K5" ; -NET "TX11_B" LOC = "K4" ; -NET "TX12_B" LOC = "M10" ; -NET "TX13_B" LOC = "M9" ; -NET "TX14_B" LOC = "J5" ; -NET "TX15_B" LOC = "J4" ; -NET "io_tx<15>" LOC = "K6" ; -NET "io_tx<14>" LOC = "L7" ; -NET "io_tx<13>" LOC = "H2" ; -NET "io_tx<12>" LOC = "H1" ; -NET "io_tx<11>" LOC = "L10" ; -NET "io_tx<10>" LOC = "L9" ; -NET "io_tx<09>" LOC = "G3" ; -NET "io_tx<08>" LOC = "F3" ; -NET "io_tx<07>" LOC = "K7" ; -NET "io_tx<06>" LOC = "J6" ; -NET "io_tx<05>" LOC = "E1" ; -NET "io_tx<04>" LOC = "F2" ; -NET "io_tx<03>" LOC = "J7" ; -NET "io_tx<02>" LOC = "H6" ; -NET "io_tx<01>" LOC = "F5" ; -NET "io_tx<00>" LOC = "G4" ; -NET "MOSI_RX_ADC" LOC = "E3" ; -NET "SCLK_RX_ADC" LOC = "F4" ; -NET "SEN_RX_ADC" LOC = "D3" ; -NET "SCLK_RX_DAC" LOC = "E4" ; -NET "SEN_RX_DAC" LOC = "K9" ; -NET "MOSI_RX_DAC" LOC = "K8" ; -NET "SCLK_RX_DB" LOC = "G6" ; -NET "MOSI_RX_DB" LOC = "H7" ; -NET "SEN_RX_DB" LOC = "B2" ; -NET "SCLK_ADC" LOC = "B1" ; -NET "MOSI_ADC" LOC = "J8" ; -NET "SEN_ADC" LOC = "J9" ; -NET "ADCB_4_5_p" LOC = "AE1" ; -NET "ADCB_4_5_n" LOC = "AE2" ; -NET "ADCB_6_7_p" LOC = "W1" ; -NET "ADCB_6_7_n" LOC = "W2" ; -NET "ADCB_8_9_p" LOC = "U3" ; -NET "ADCB_8_9_n" LOC = "V4" ; -NET "ADCB_10_11_p" LOC = "J1" ; -NET "ADCB_10_11_n" LOC = "K1" ; -NET "ADCB_12_13_p" LOC = "J3" ; -NET "ADCB_12_13_n" LOC = "J2" ; -NET "MISO_RX_DB" LOC = "H4" ; -NET "MISO_RX_ADC" LOC = "C1" ; -NET "MISO_TX_DB" LOC = "AA5" ; -NET "MISO_DAC" LOC = "Y3" ; -NET "MISO_TX_ADC" LOC = "G1" ; -NET "io_rx<02>" LOC = "R10" ; -NET "io_rx<01>" LOC = "R1" ; -NET "io_rx<00>" LOC = "M1" ; -NET "exp_user_out_p" LOC = "AF14" ; -NET "exp_user_out_n" LOC = "AE14" ; -NET "exp_time_out_p" LOC = "Y14" ; -NET "exp_time_out_n" LOC = "AA14" ; -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; -NET "leds<5>" LOC = "AF25" ; -NET "leds<4>" LOC = "AE25" ; -NET "leds<3>" LOC = "AF23" ; -NET "leds<2>" LOC = "AE23" ; -NET "leds<1>" LOC = "AB18" ; -NET "SEN_CLK" LOC = "AA18" ; -NET "MOSI_CLK" LOC = "W17" ; -NET "SCLK_CLK" LOC = "V17" ; -NET "CLK_STATUS" LOC = "AD22" ; -NET "CLK_FUNC" LOC = "AC21" ; -NET "clk_sel<0>" LOC = "AE21" ; -NET "clk_sel<1>" LOC = "AD21" ; -NET "clk_en<1>" LOC = "AA17" ; -NET "clk_en<0>" LOC = "Y17" ; -NET "SDA" LOC = "V16" ; -NET "SCL" LOC = "U16" ; -NET "TXD3" LOC = "AD20" ; -NET "TXD2" LOC = "AC20" ; -NET "TXD1" LOC = "AD19" ; -NET "debug<00>" LOC = "AC19" ; -NET "debug<01>" LOC = "AF20" ; -NET "debug<02>" LOC = "AE20" ; -NET "debug<03>" LOC = "AC16" ; -NET "debug<04>" LOC = "AB16" ; -NET "debug<05>" LOC = "AF19" ; -NET "debug<06>" LOC = "AE19" ; -NET "debug<07>" LOC = "V15" ; -NET "debug<08>" LOC = "U15" ; -NET "debug<09>" LOC = "AE17" ; -NET "debug<10>" LOC = "AD17" ; -NET "debug<11>" LOC = "V14" ; -NET "debug<12>" LOC = "W15" ; -NET "debug<13>" LOC = "AC15" ; -NET "debug<14>" LOC = "AD14" ; -NET "debug<15>" LOC = "AC14" ; -NET "debug_clk<1>" LOC = "AD11" ; -NET "debug<16>" LOC = "AC11" ; -NET "debug<17>" LOC = "AB12" ; -NET "debug<18>" LOC = "AC12" ; -NET "debug<19>" LOC = "V13" ; -NET "debug<20>" LOC = "W13" ; -NET "debug<21>" LOC = "AE8" ; -NET "debug<22>" LOC = "AF8" ; -NET "debug<23>" LOC = "V12" ; -NET "debug<24>" LOC = "W12" ; -NET "debug<25>" LOC = "AB9" ; -NET "debug<26>" LOC = "AC9" ; -NET "debug<27>" LOC = "AC8" ; -NET "debug<28>" LOC = "AB7" ; -NET "debug<29>" LOC = "V11" ; -NET "debug<30>" LOC = "U11" ; -NET "debug<31>" LOC = "Y10" ; -NET "debug_clk<0>" LOC = "AA10" ; -NET "SEN_DAC" LOC = "AE7" ; -NET "SCLK_DAC" LOC = "AF5" ; -NET "MOSI_DAC" LOC = "AE6" ; -NET "MOSI_TX_ADC" LOC = "V10" ; -NET "SEN_TX_ADC" LOC = "W10" ; -NET "SCLK_TX_ADC" LOC = "AC6" ; -NET "MOSI_TX_DAC" LOC = "AD6" ; -NET "SEN_TX_DAC" LOC = "AE4" ; -NET "SCLK_TX_DAC" LOC = "AF4" ; -NET "SCLK_TX_DB" LOC = "AE3" ; -NET "MOSI_TX_DB" LOC = "AF3" ; -NET "SEN_TX_DB" LOC = "W9" ; -NET "RXD3" LOC = "AF17" ; -NET "RXD2" LOC = "AF15" ; -NET "RXD1" LOC = "AD12" ; -NET "MISO_CLK" LOC = "AC10" ; -NET "PPS_IN" LOC = "AB6" ; -NET "PPS2_IN" LOC = "AA20" ; -NET "ser_rx_clk" LOC = "P18" ; -NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK -NET "CLK_TO_MAC" LOC = "P26" ; -NET "GMII_TX_CLK" LOC = "P25" ; -NET "GMII_RX_CLK" LOC = "P21" ; -NET "ETH_LED" LOC = "H20" ; -NET "GMII_TXD7" LOC = "G21" ; -NET "GMII_TXD6" LOC = "C26" ; -NET "GMII_TXD5" LOC = "C25" ; -NET "GMII_TXD4" LOC = "J21" ; -NET "GMII_TXD3" LOC = "H21" ; -NET "GMII_TXD2" LOC = "D25" ; -NET "GMII_TXD1" LOC = "D24" ; -NET "GMII_TXD0" LOC = "E26" ; -NET "GMII_TX_EN" LOC = "D26" ; -NET "GMII_TX_ER" LOC = "J19" ; -NET "GMII_GTX_CLK" LOC = "J20" ; -NET "GMII_RXD7" LOC = "G22" ; -NET "GMII_RXD6" LOC = "K19" ; -NET "GMII_RXD5" LOC = "K18" ; -NET "GMII_RXD4" LOC = "E24" ; -NET "GMII_RXD3" LOC = "F23" ; -NET "GMII_RXD2" LOC = "L18" ; -NET "GMII_RXD1" LOC = "L17" ; -NET "GMII_RXD0" LOC = "F25" ; -NET "GMII_RX_DV" LOC = "F24" ; -NET "GMII_RX_ER" LOC = "L20" ; -NET "GMII_CRS" LOC = "K20" ; -NET "GMII_COL" LOC = "G23" ; -NET "PHY_INTn" LOC = "L22" ; -NET "MDIO" LOC = "K21" ; -NET "MDC" LOC = "J23" ; -NET "PHY_RESET" LOC = "J22" ; -NET "exp_time_in_p" LOC = "N18" ; -NET "exp_time_in_n" LOC = "N17" ; -NET "exp_user_in_p" LOC = "L24" ; -NET "exp_user_in_n" LOC = "M23" ; -NET "ser_prbsen" LOC = "U23" ; -NET "ser_loopen" LOC = "R19" ; -NET "ser_enable" LOC = "R20" ; -NET "ser_t<15>" LOC = "V23" ; -NET "ser_t<14>" LOC = "U22" ; -NET "ser_t<13>" LOC = "V24" ; -NET "ser_t<12>" LOC = "V25" ; -NET "ser_t<11>" LOC = "W23" ; -NET "ser_t<10>" LOC = "V22" ; -NET "ser_t<09>" LOC = "T18" ; -NET "ser_t<08>" LOC = "T17" ; -NET "ser_t<07>" LOC = "Y24" ; -NET "ser_t<06>" LOC = "Y25" ; -NET "ser_t<05>" LOC = "U21" ; -NET "ser_t<04>" LOC = "T20" ; -NET "ser_t<03>" LOC = "Y22" ; -NET "ser_t<02>" LOC = "Y23" ; -NET "ser_t<01>" LOC = "U19" ; -NET "ser_t<00>" LOC = "U18" ; -NET "ser_tkmsb" LOC = "AA24" ; -NET "ser_tklsb" LOC = "AA25" ; -NET "ser_r<15>" LOC = "V21" ; -NET "ser_r<14>" LOC = "U20" ; -NET "ser_r<13>" LOC = "AA22" ; -NET "ser_r<12>" LOC = "AA23" ; -NET "ser_r<11>" LOC = "V18" ; -NET "ser_r<10>" LOC = "V19" ; -NET "ser_r<09>" LOC = "AB23" ; -NET "ser_r<08>" LOC = "AC26" ; -NET "ser_r<07>" LOC = "AB26" ; -NET "ser_r<06>" LOC = "AD26" ; -NET "ser_r<05>" LOC = "AC25" ; -NET "ser_r<04>" LOC = "W20" ; -NET "ser_r<03>" LOC = "W21" ; -NET "ser_r<02>" LOC = "AC23" ; -NET "ser_r<01>" LOC = "AC24" ; -NET "ser_r<00>" LOC = "AE26" ; -NET "ser_rkmsb" LOC = "AD25" ; -NET "ser_rklsb" LOC = "Y20" ; -NET "ser_rx_en" LOC = "Y21" ; -NET "FPGA_RESET" LOC = "K24" ; -NET "RAM_D<17>" LOC = "F7" ; -NET "RAM_D<16>" LOC = "E7" ; -NET "RAM_D<15>" LOC = "G9" ; -NET "RAM_D<14>" LOC = "H9" ; -NET "RAM_D<13>" LOC = "G10" ; -NET "RAM_D<12>" LOC = "H10" ; -NET "RAM_D<11>" LOC = "A4" ; -NET "RAM_D<10>" LOC = "B4" ; -NET "RAM_D<09>" LOC = "C5" ; -NET "RAM_D<08>" LOC = "D6" ; -NET "RAM_D<07>" LOC = "J11" ; -NET "RAM_D<06>" LOC = "K11" ; -NET "RAM_D<05>" LOC = "B7" ; -NET "RAM_D<04>" LOC = "C7" ; -NET "RAM_D<03>" LOC = "B6" ; -NET "RAM_D<02>" LOC = "C6" ; -NET "RAM_D<01>" LOC = "C8" ; -NET "RAM_D<00>" LOC = "D8" ; -NET "RAM_ZZ" LOC = "J12" ; -NET "RAM_BWn<3>" LOC = "D9" ; -NET "RAM_BWn<2>" LOC = "A9" ; -NET "RAM_BWn<1>" LOC = "B9" ; -NET "RAM_BWn<0>" LOC = "G12" ; -NET "RAM_LDn" LOC = "H12" ; -NET "RAM_OEn" LOC = "C10" ; -NET "RAM_WEn" LOC = "D10" ; -NET "RAM_CLK" LOC = "A10" ; -NET "RAM_CENn" LOC = "B10" ; -NET "RAM_A<00>" LOC = "C11" ; -NET "RAM_A<01>" LOC = "E12" ; -NET "RAM_A<02>" LOC = "F12" ; -NET "RAM_A<03>" LOC = "D13" ; -NET "RAM_A<04>" LOC = "C12" ; -NET "RAM_A<05>" LOC = "A12" ; -NET "RAM_A<06>" LOC = "B12" ; -NET "RAM_A<07>" LOC = "E14" ; -NET "RAM_A<08>" LOC = "F14" ; -NET "RAM_A<09>" LOC = "B15" ; -NET "RAM_A<10>" LOC = "A15" ; -NET "RAM_A<11>" LOC = "D16" ; -NET "RAM_A<12>" LOC = "C15" ; -NET "RAM_A<13>" LOC = "D17" ; -NET "RAM_A<14>" LOC = "C16" ; -NET "RAM_A<15>" LOC = "F15" ; -NET "RAM_A<16>" LOC = "C17" ; -NET "RAM_A<17>" LOC = "B17" ; -NET "RAM_A<18>" LOC = "B18" ; -NET "RAM_A<19>" LOC = "A18" ; -NET "RAM_A<20>" LOC = "D18" ; -NET "RAM_D<35>" LOC = "K16" ; -NET "RAM_D<34>" LOC = "D20" ; -NET "RAM_D<33>" LOC = "C20" ; -NET "RAM_D<32>" LOC = "E21" ; -NET "RAM_D<31>" LOC = "D21" ; -NET "RAM_D<30>" LOC = "C21" ; -NET "RAM_D<29>" LOC = "B21" ; -NET "RAM_D<28>" LOC = "H17" ; -NET "RAM_D<27>" LOC = "G17" ; -NET "RAM_D<26>" LOC = "B23" ; -NET "RAM_D<25>" LOC = "A22" ; -NET "RAM_D<24>" LOC = "D23" ; -NET "RAM_D<23>" LOC = "C23" ; -NET "RAM_D<22>" LOC = "D22" ; -NET "RAM_D<21>" LOC = "C22" ; -NET "RAM_D<20>" LOC = "F19" ; -NET "RAM_D<19>" LOC = "G20" ; -NET "RAM_D<18>" LOC = "F20" ; -#NET "unnamed_net20" LOC = "V20" ; # SUSPEND -NET "PROG_B" LOC = "A2" ; -NET "PUDC_B" LOC = "G8" ; -NET "DONE" LOC = "AB21" ; -NET "flash_miso" LOC = "AF24" ; -NET "flash_clk" LOC = "AE24" ; -NET "INIT_B" LOC = "AA15" ; -NET "flash_mosi" LOC = "AB15" ; -#NET "unnamed_net19" LOC = "AE9" ; # VS1 -#NET "unnamed_net18" LOC = "AF9" ; # VS0 -#NET "unnamed_net17" LOC = "AA12" ; # VS2 -#NET "unnamed_net16" LOC = "Y7" ; # M2 -NET "flash_cs" LOC = "AA7" ; -#NET "unnamed_net15" LOC = "AC4" ; # M1 -#NET "unnamed_net14" LOC = "AD4" ; # M0 -#NET "unnamed_net13" LOC = "D4" ; # TMS -#NET "unnamed_net12" LOC = "E23" ; # TDO -#NET "unnamed_net11" LOC = "G7" ; # TDI -#NET "unnamed_net10" LOC = "A25" ; # TCK - diff --git a/top/u2plus/u2plus.v b/top/u2plus/u2plus.v deleted file mode 100644 index e95445867..000000000 --- a/top/u2plus/u2plus.v +++ /dev/null @@ -1,377 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u2plus - ( - // Misc, debug - output [4:0] leds, // LED4 is shared w/INIT_B - input [3:0] dipsw, - output [31:0] debug, - output [1:0] debug_clk, - output uart_tx_o, - input uart_rx_i, - - // Expansion - input exp_pps_in_p, // Diff - input exp_pps_in_n, // Diff - output exp_pps_out_p, // Diff - output exp_pps_out_n, // Diff - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - input clk_to_mac, - output eth_led, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - input dac_lock, // unused for now - - // I2C - inout SCL, - inout SDA, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Clocks - input clk_fpga_p, // Diff - input clk_fpga_n, // Diff - input pps_in, - input POR, - - // AD9510 SPI - output sclk, - output sen_clk, - output sdi, - input sdo, - - // TX side SPI -- tx_db, tx_adc, tx_dac, 9777 - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output mosi_tx, - input miso_dac, - input miso_tx_db, - input miso_tx_adc, - output sclk_tx, - - // RX side SPI - output sen_rx_db, - output sclk_rx_db, - input sdo_rx_db, - output sdi_rx_db, - - output sen_rx_adc, - output sclk_rx_adc, - input sdo_rx_adc, - output sdi_rx_adc, - - output sen_rx_dac, - output sclk_rx_dac, - output sdi_rx_dac, - - // DB IO Pins - inout [15:0] io_tx, - inout [15:0] io_rx, - - // SPI Flash - output flash_cs, - output flash_clk, - output flash_mosi, - input flash_miso - ); - - // FPGA-specific pins connections - wire aux_clk = PHY_CLK; - - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire exp_pps_in; - IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); - defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_pps_out; - OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); - defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge aux_clk) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - wire clk_muxed = clock_ready ? clk_fpga : aux_clk; - - wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; - assign adc_oen_a = ~adc_oe_a; - assign adc_oen_b = ~adc_oe_b; - assign adc_pdn_a = ~adc_on_a; - assign adc_pdn_b = ~adc_on_b; - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_muxed), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk_int; - assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; - - assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | - (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | - (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - u2_core u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .PHY_CLK (PHY_CLK), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - //.uart_rx_i (uart_rx_i), - .uart_rx_i (), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); - -endmodule // u2plus diff --git a/usrp2/boot_cpld/.gitignore b/usrp2/boot_cpld/.gitignore new file mode 100644 index 000000000..45cf9a86b --- /dev/null +++ b/usrp2/boot_cpld/.gitignore @@ -0,0 +1,38 @@ +/*_xdb +/*.restore +/*.xrpt +/*.zip +/xst +/_ngo +/_xmsgs +/*.log +/*.stx +/*.tspec +/*.xml +/*.gyd +/*.ngr +/*.tim +/*.err +/*.lso +/*.bld +/*.cmd_log +/*.ise_ISE_Backup +/*.ipf_ISE_Backup +/*.mfd +/*.vm6 +/*.syr +/*.xst +/*.csv +/*.html +/*.jed +/*.pad +/*.ng* +/*.pnx +/*.rpt +/*.prj +/*_html +/*.cel +/_pace.ucf +/*.lock +/*.tfi +/templates diff --git a/usrp2/boot_cpld/_impact.cmd b/usrp2/boot_cpld/_impact.cmd new file mode 100755 index 000000000..4af86cb02 --- /dev/null +++ b/usrp2/boot_cpld/_impact.cmd @@ -0,0 +1,34 @@ +loadProjectFile -file "C:\cygwin\home\matt\usrp2\fpga\boot_cpld/boot_cpld.ipf" +setMode -ss +setMode -sm +setMode -hw140 +setMode -spi +setMode -acecf +setMode -acempm +setMode -pff +setMode -bs +setMode -bs +setMode -bs +setMode -bs +setCable -port auto +Identify +identifyMPM +assignFile -p 1 -file "C:/cygwin/home/matt/usrp2/fpga/boot_cpld/boot_cpld.jed" +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Identify +identifyMPM +Identify +identifyMPM +Identify +identifyMPM +Identify +identifyMPM +Identify +identifyMPM +setMode -bs +deleteDevice -position 1 diff --git a/usrp2/boot_cpld/boot_cpld.ipf b/usrp2/boot_cpld/boot_cpld.ipf new file mode 100755 index 000000000..8acb6821e Binary files /dev/null and b/usrp2/boot_cpld/boot_cpld.ipf differ diff --git a/usrp2/boot_cpld/boot_cpld.ise b/usrp2/boot_cpld/boot_cpld.ise new file mode 100755 index 000000000..7252d3768 Binary files /dev/null and b/usrp2/boot_cpld/boot_cpld.ise differ diff --git a/usrp2/boot_cpld/boot_cpld.lfp b/usrp2/boot_cpld/boot_cpld.lfp new file mode 100755 index 000000000..0f0c8f2e2 --- /dev/null +++ b/usrp2/boot_cpld/boot_cpld.lfp @@ -0,0 +1,5 @@ +# begin LFP file C:\cygwin\home\matt\u2f\boot_cpld\boot_cpld.lfp +designfile boot_cpld.v +parttype xc9572xl-vq44-10 +bus_delimiter 0; +set_busdelim_onsave 1; diff --git a/usrp2/boot_cpld/boot_cpld.ucf b/usrp2/boot_cpld/boot_cpld.ucf new file mode 100755 index 000000000..789bb1d96 --- /dev/null +++ b/usrp2/boot_cpld/boot_cpld.ucf @@ -0,0 +1,34 @@ +NET "CLK_25MHZ" LOC = "P5" ; +NET "CLK_25MHZ_EN" LOC = "P6" ; +NET "LED<0>" LOC = "P12" ; +NET "LED<1>" LOC = "P8" ; +NET "LED<2>" LOC = "P7" ; +NET "DEBUG<0>" LOC = "P1" ; +NET "DEBUG<1>" LOC = "P2" ; +NET "DEBUG<2>" LOC = "P3" ; +NET "DEBUG<3>" LOC = "P29" ; +NET "DEBUG<4>" LOC = "P30" ; +NET "DEBUG<5>" LOC = "P31" ; +NET "DEBUG<6>" LOC = "P32" ; +NET "DEBUG<7>" LOC = "P33" ; +NET "DEBUG<8>" LOC = "P34" ; +NET "POR" LOC = "P42" ; +NET "SD_nCS" LOC = "P20" ; +NET "SD_Din" LOC = "P21" ; +NET "SD_CLK" LOC = "P22" ; +NET "SD_Dout" LOC = "P23" ; +NET "SD_DAT1" LOC = "P27" ; +NET "SD_DAT2" LOC = "P28" ; +NET "SD_prot" LOC = "P19" ; +NET "SD_det" LOC = "P36" ; +NET "CFG_INIT_B" LOC = "P38" ; +NET "CFG_Din" LOC = "P37" ; +NET "CFG_CCLK" LOC = "P41" ; +NET "CFG_DONE" LOC = "P40" ; +NET "CFG_PROG_B" LOC = "P39" ; +NET "CPLD_CLK" LOC = "P13" ; +NET "START" LOC = "P14" ; +NET "MODE" LOC = "P18" ; +NET "DONE" LOC = "P16" ; +NET "detached" LOC = "P43" ; +NET "CPLD_misc" LOC = "P44" ; diff --git a/usrp2/boot_cpld/boot_cpld.v b/usrp2/boot_cpld/boot_cpld.v new file mode 100755 index 000000000..2ffc6daed --- /dev/null +++ b/usrp2/boot_cpld/boot_cpld.v @@ -0,0 +1,95 @@ +`timescale 1ns / 1ps +// //////////////////////////////////////////////////////////////////////////////// +// Boot CPLD design, only for u2_rev2 +// //////////////////////////////////////////////////////////////////////////////// + +module boot_cpld + (input CLK_25MHZ, + output CLK_25MHZ_EN, + output [2:0] LED, + output [8:0] DEBUG, + input POR, + + // To SD Card + output SD_nCS, + output SD_Din, + output SD_CLK, + input SD_Dout, + input SD_DAT1, // Unused + input SD_DAT2, // Unused + input SD_prot, // Write Protect + input SD_det, // Card Detect + + // To FPGA Config Interface + input CFG_INIT_B, + output CFG_Din, // Also used in Data interface + output CFG_CCLK, + input CFG_DONE, + output CFG_PROG_B, + + // To FPGA data interface + output CPLD_CLK, + input START, + input MODE, + input DONE, + output detached, + input CPLD_misc // Unused for now + ); + + assign CLK_25MHZ_EN = 1'b1; + + assign LED[0] = ~CFG_DONE; + assign LED[1] = CFG_INIT_B; + assign LED[2] = ~CFG_PROG_B; + + wire en_outs; + wire [3:0] set_sel = 4'd0; + + assign CPLD_CLK = CFG_CCLK; + assign DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, + START, MODE, DONE, CPLD_misc}; + + // Handle cutover to FPGA control of SD + wire fpga_takeover = ~CPLD_misc; + wire SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int; + + assign SD_CLK = fpga_takeover ? START : SD_CLK_int; + assign SD_nCS = fpga_takeover ? MODE : SD_nCS_int; + assign SD_Din = fpga_takeover ? DONE : SD_Din_int; + assign CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int; + + spi_boot #(.width_set_sel_g(4), // How many sets (16) + .width_bit_cnt_g(6), // Block length (12 is faster, 6 is minimum) + .width_img_cnt_g(2), // How many images per set + .num_bits_per_img_g(20), // Image size, 20 = 1MB + .sd_init_g(1), // SD-specific initialization + .mmc_compat_clk_div_g(0),// No MMC support + .width_mmc_clk_div_g(0), // No MMC support + .reset_level_g(0)) // Active low reset + + spi_boot(.clk_i(CLK_25MHZ), + .reset_i(POR), + + // To SD Card + .spi_clk_o(SD_CLK_int), + .spi_cs_n_o(SD_nCS_int), + .spi_data_in_i(SD_Dout), + .spi_data_out_o(SD_Din_int), + .spi_en_outs_o(en_outs), + + // Data Port + .start_i(START), + .mode_i(MODE), // 0->conf mode, 1->data mode + .detached_o(detached), + .dat_done_i(DONE), + .set_sel_i(set_sel), + + // To FPGA + .config_n_o(CFG_PROG_B), + .cfg_init_n_i(CFG_INIT_B), + .cfg_done_i(CFG_DONE), + .cfg_clk_o(CFG_CCLK), + .cfg_dat_o(CFG_Din_int) + ); + +endmodule // boot_cpld diff --git a/usrp2/control_lib/.gitignore b/usrp2/control_lib/.gitignore new file mode 100644 index 000000000..025385cff --- /dev/null +++ b/usrp2/control_lib/.gitignore @@ -0,0 +1,5 @@ +/a.out +/*.vcd +/*.lxt +/*.sav +/*.log diff --git a/usrp2/control_lib/CRC16_D16.v b/usrp2/control_lib/CRC16_D16.v new file mode 100644 index 000000000..7e2816af1 --- /dev/null +++ b/usrp2/control_lib/CRC16_D16.v @@ -0,0 +1,89 @@ +/////////////////////////////////////////////////////////////////////// +// File: CRC16_D16.v +// Date: Sun Jun 17 06:42:55 2007 +// +// Copyright (C) 1999-2003 Easics NV. +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +// Purpose: Verilog module containing a synthesizable CRC function +// * polynomial: (0 5 12 16) +// * data width: 16 +// +// Info: tools@easics.be +// http://www.easics.com +/////////////////////////////////////////////////////////////////////// + + +module CRC16_D16 + (input [15:0] Data, + input [15:0] CRC, + output [15:0] NewCRC); + + assign NewCRC = nextCRC16_D16(Data,CRC); + + // polynomial: (0 5 12 16) + // data width: 16 + // convention: the first serial data bit is D[15] + function [15:0] nextCRC16_D16; + + input [15:0] Data; + input [15:0] CRC; + + reg [15:0] D; + reg [15:0] C; + reg [15:0] NewCRC; + + begin + + D = Data; + C = CRC; + + NewCRC[0] = D[12] ^ D[11] ^ D[8] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ + C[8] ^ C[11] ^ C[12]; + NewCRC[1] = D[13] ^ D[12] ^ D[9] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ + C[9] ^ C[12] ^ C[13]; + NewCRC[2] = D[14] ^ D[13] ^ D[10] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ + C[10] ^ C[13] ^ C[14]; + NewCRC[3] = D[15] ^ D[14] ^ D[11] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ + C[11] ^ C[14] ^ C[15]; + NewCRC[4] = D[15] ^ D[12] ^ D[8] ^ D[4] ^ C[4] ^ C[8] ^ C[12] ^ + C[15]; + NewCRC[5] = D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ D[4] ^ + D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ + C[13]; + NewCRC[6] = D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[5] ^ + D[1] ^ C[1] ^ C[5] ^ C[6] ^ C[9] ^ C[10] ^ C[12] ^ + C[13] ^ C[14]; + NewCRC[7] = D[15] ^ D[14] ^ D[13] ^ D[11] ^ D[10] ^ D[7] ^ D[6] ^ + D[2] ^ C[2] ^ C[6] ^ C[7] ^ C[10] ^ C[11] ^ C[13] ^ + C[14] ^ C[15]; + NewCRC[8] = D[15] ^ D[14] ^ D[12] ^ D[11] ^ D[8] ^ D[7] ^ D[3] ^ + C[3] ^ C[7] ^ C[8] ^ C[11] ^ C[12] ^ C[14] ^ C[15]; + NewCRC[9] = D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[8] ^ D[4] ^ C[4] ^ + C[8] ^ C[9] ^ C[12] ^ C[13] ^ C[15]; + NewCRC[10] = D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[5] ^ C[5] ^ C[9] ^ + C[10] ^ C[13] ^ C[14]; + NewCRC[11] = D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[6] ^ C[6] ^ C[10] ^ + C[11] ^ C[14] ^ C[15]; + NewCRC[12] = D[15] ^ D[8] ^ D[7] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ C[7] ^ + C[8] ^ C[15]; + NewCRC[13] = D[9] ^ D[8] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ C[8] ^ C[9]; + NewCRC[14] = D[10] ^ D[9] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ C[9] ^ C[10]; + NewCRC[15] = D[11] ^ D[10] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ C[10] ^ + C[11]; + + nextCRC16_D16 = NewCRC; + + end + + endfunction + +endmodule + diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v new file mode 100644 index 000000000..fed2791f9 --- /dev/null +++ b/usrp2/control_lib/atr_controller.v @@ -0,0 +1,57 @@ + +// Automatic transmit/receive switching of control pins to daughterboards +// Store everything in registers for now, but could use a RAM for more +// complex state machines in the future + +module atr_controller + (input clk_i, input rst_i, + input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input run_rx, input run_tx, input [31:0] master_time, + output [31:0] ctrl_lines); + + reg [3:0] state; + reg [31:0] atr_ram [0:15]; // DP distributed RAM + + // WB Interface + always @(posedge clk_i) + if(we_i & stb_i & cyc_i) + begin + if(sel_i[3]) + atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24]; + if(sel_i[2]) + atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16]; + if(sel_i[1]) + atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; + if(sel_i[0]) + atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; + end // if (we_i & stb_i & cyc_i) + + always @(posedge clk_i) + dat_o <= atr_ram[adr_i[5:2]]; + + always @(posedge clk_i) + ack_o <= stb_i & cyc_i & ~ack_o; + + // Control side of DP RAM + assign ctrl_lines = atr_ram[state]; + + // Put a more complex state machine with time delays and multiple states here + // if daughterboard requires more complex sequencing + localparam ATR_IDLE = 4'd0; + localparam ATR_TX = 4'd1; + localparam ATR_RX = 4'd2; + localparam ATR_FULL_DUPLEX = 4'd3; + + always @(posedge clk_i) + if(rst_i) + state <= ATR_IDLE; + else + case ({run_rx,run_tx}) + 2'b00 : state <= ATR_IDLE; + 2'b01 : state <= ATR_TX; + 2'b10 : state <= ATR_RX; + 2'b11 : state <= ATR_FULL_DUPLEX; + endcase // case({run_rx,run_tx}) + +endmodule // atr_controller diff --git a/usrp2/control_lib/bin2gray.v b/usrp2/control_lib/bin2gray.v new file mode 100644 index 000000000..513402163 --- /dev/null +++ b/usrp2/control_lib/bin2gray.v @@ -0,0 +1,10 @@ + + +module bin2gray + #(parameter WIDTH=8) + (input [WIDTH-1:0] bin, + output [WIDTH-1:0] gray); + + assign gray = (bin >> 1) ^ bin; + +endmodule // bin2gray diff --git a/usrp2/control_lib/bootrom.mem b/usrp2/control_lib/bootrom.mem new file mode 100644 index 000000000..d688b4342 --- /dev/null +++ b/usrp2/control_lib/bootrom.mem @@ -0,0 +1,26 @@ +00000C000F03 +101400000000 + // SPI: Set Divider to div by 2 +// Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds +1018_0000_0001 // SPI: Choose AD9510 +1010_0000_3418 // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word +1000_0000_0010 // SPI: AD9510 A:0 D:10 Set up AD9510 SPI +1010_0000_3518 // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word +ffff_ffff_ffff // terminate +#// First 16 bits are address, last 32 are data +#// First 4 bits of address select which slave +// 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on +// 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels +// 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) +// 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal +// 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current +// 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On +// 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) +// 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 +// 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det +// 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... +// 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care +// 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 +// 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 + // default : addr_data = {13'h5A,8'h01}; // Register Update +// @ 55 // Jump to new address 8'h55 diff --git a/usrp2/control_lib/clock_bootstrap_rom.v b/usrp2/control_lib/clock_bootstrap_rom.v new file mode 100644 index 000000000..46563db65 --- /dev/null +++ b/usrp2/control_lib/clock_bootstrap_rom.v @@ -0,0 +1,34 @@ + + +module clock_bootstrap_rom(input [15:0] addr, output [47:0] data); + + reg [47:0] rom [0:15]; + + //initial + // $readmemh("bootrom.mem", rom); + + assign data = rom[addr]; + + initial + begin + // First 16 bits are address, last 32 are data + // First 4 bits of address select which slave + rom[0] = 48'h0000_0C00_0F03; // Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds + rom[1] = 48'h1014_0000_0000; // SPI: Set Divider to div by 2 + rom[2] = 48'h1018_0000_0001; // SPI: Choose AD9510 + rom[3] = 48'h1010_0000_3418; // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word + rom[4] = 48'h1000_0000_0010; // SPI: AD9510 A:0 D:10 Set up AD9510 SPI + rom[5] = 48'h1010_0000_3518; // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word + rom[6] = 48'hffff_ffff_ffff; // terminate + rom[7] = 48'hffff_ffff_ffff; // terminate + rom[8] = 48'hffff_ffff_ffff; // terminate + rom[9] = 48'hffff_ffff_ffff; // terminate + rom[10] = 48'hffff_ffff_ffff; // terminate + rom[11] = 48'hffff_ffff_ffff; // terminate + rom[12] = 48'hffff_ffff_ffff; // terminate + rom[13] = 48'hffff_ffff_ffff; // terminate + rom[14] = 48'hffff_ffff_ffff; // terminate + rom[15] = 48'hffff_ffff_ffff; // terminate + end // initial begin + +endmodule // clock_bootstrap_rom diff --git a/usrp2/control_lib/clock_control.v b/usrp2/control_lib/clock_control.v new file mode 100644 index 000000000..1bbe6bd75 --- /dev/null +++ b/usrp2/control_lib/clock_control.v @@ -0,0 +1,115 @@ + + +// AD9510 Register Map (from datasheet Rev. A) + +/* INSTRUCTION word format (16 bits) + * 15 Read = 1, Write = 0 + * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream + * 12:0 Address + */ + +/* ADDR Contents Value (hex) + * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate + * 04 A Counter + * 05-06 B Counter + * 07-0A PLL Control + * 0B-0C R Divider + * 0D PLL Control + * 34-3A Fine Delay + * 3C-3F LVPECL Outs + * 40-43 LVDS/CMOS Outs + * 45 Clock select, power down + * 48-57 Dividers + * 58 Func and Sync + * 5A Update regs + */ + + +module clock_control + (input reset, + input aux_clk, // 25MHz, for before fpga clock is active + input clk_fpga, // real 100 MHz FPGA clock + output [1:0] clk_en, // controls source of reference clock + output [1:0] clk_sel, // controls source of reference clock + input clk_func, // FIXME needs to be some kind of out SYNC or reset to 9510 + input clk_status, // Monitor PLL or SYNC status + + output sen, // Enable for the AD9510 + output sclk, // FIXME these need to be shared + input sdi, + output sdo + ); + + wire read = 1'b0; // Always write for now + wire [1:0] w = 2'b00; // Always send 1 byte at a time + + assign clk_sel = 2'b00; // Both outputs from External Ref (SMA) + assign clk_en = 2'b11; // Both outputs enabled + + reg [20:0] addr_data; + + reg [5:0] entry; + reg start; + reg [7:0] counter; + reg [23:0] command; + + always @* + case(entry) + 6'd00 : addr_data = {13'h00,8'h10}; // Serial setup + 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on + 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels + 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) + 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal + 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current + 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On + 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) + 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 + 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det + 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... + 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care + 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 + 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 + default : addr_data = {13'h5A,8'h01}; // Register Update + endcase // case(entry) + + wire [5:0] lastentry = 6'd15; + wire done = (counter == 8'd49); + + always @(posedge aux_clk) + if(reset) + begin + entry <= #1 6'd0; + start <= #1 1'b1; + end + else if(start) + start <= #1 1'b0; + else if(done && (entry + // reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1]; + + // Port 1 + always @(posedge clk) + if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]]; + + always @(posedge clk) + if(we1_i & en1_i & sel1_i[3]) + ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24]; + always @(posedge clk) + if(we1_i & en1_i & sel1_i[2]) + ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16]; + always @(posedge clk) + if(we1_i & en1_i & sel1_i[1]) + ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8]; + always @(posedge clk) + if(we1_i & en1_i & sel1_i[0]) + ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0]; + + // Port 2 + always @(posedge clk) + if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]]; + + always @(posedge clk) + if(we2_i & en2_i & sel2_i[3]) + ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24]; + always @(posedge clk) + if(we2_i & en2_i & sel2_i[2]) + ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16]; + always @(posedge clk) + if(we2_i & en2_i & sel2_i[1]) + ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8]; + always @(posedge clk) + if(we2_i & en2_i & sel2_i[0]) + ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0]; + +endmodule // dpram32 + + diff --git a/usrp2/control_lib/fifo_tb.v b/usrp2/control_lib/fifo_tb.v new file mode 100644 index 000000000..616fe4ee7 --- /dev/null +++ b/usrp2/control_lib/fifo_tb.v @@ -0,0 +1,151 @@ +module fifo_tb(); + + reg clk, rst; + wire short_full, short_empty, long_full, long_empty; + wire casc2_full, casc2_empty; + reg read, write; + + wire [7:0] short_do, long_do; + wire [7:0] casc2_do; + reg [7:0] di; + + reg clear = 0; + + shortfifo #(.WIDTH(8)) shortfifo + (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear), + .read(read),.write(write),.full(short_full),.empty(short_empty)); + + longfifo #(.WIDTH(8), .SIZE(4)) longfifo + (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear), + .read(read),.write(write),.full(long_full),.empty(long_empty)); + + cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2 + (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear), + .read(read),.write(write),.full(casc2_full),.empty(casc2_empty)); + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #50 clk = ~clk; + + initial di = 8'hAE; + initial read = 0; + initial write = 0; + + always @(posedge clk) + if(write) + di <= di + 1; + + always @(posedge clk) + begin + if(short_full != long_full) + $display("Error: FULL mismatch"); + if(short_empty != long_empty) + $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)"); + if(read & (short_do != long_do)) + $display("Error: DATA mismatch"); + end + + initial $dumpfile("fifo_tb.vcd"); + initial $dumpvars(0,fifo_tb); + + initial + begin + @(negedge rst); + @(posedge clk); + repeat (10) + @(posedge clk); + write <= 1; + @(posedge clk); + write <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + read <= 1; + @(posedge clk); + read <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + + repeat(10) + begin + write <= 1; + @(posedge clk); + write <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + read <= 1; + @(posedge clk); + read <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + end // repeat (10) + + write <= 1; + repeat (4) + @(posedge clk); + write <= 0; + @(posedge clk); + read <= 1; + repeat (4) + @(posedge clk); + read <= 0; + @(posedge clk); + + + write <= 1; + repeat (4) + @(posedge clk); + write <= 0; + @(posedge clk); + repeat (4) + begin + read <= 1; + @(posedge clk); + read <= 0; + @(posedge clk); + end + + write <= 1; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + read <= 1; + repeat (5) + @(posedge clk); + write <= 0; + @(posedge clk); + @(posedge clk); + read <= 0; + @(posedge clk); + + write <= 1; + repeat (16) + @(posedge clk); + write <= 0; + @(posedge clk); + + read <= 1; + repeat (16) + @(posedge clk); + read <= 0; + @(posedge clk); + + repeat (10) + @(posedge clk); + $finish; + end +endmodule // longfifo_tb diff --git a/usrp2/control_lib/gray2bin.v b/usrp2/control_lib/gray2bin.v new file mode 100644 index 000000000..5df40bd52 --- /dev/null +++ b/usrp2/control_lib/gray2bin.v @@ -0,0 +1,13 @@ + + +module gray2bin + #(parameter WIDTH=8) + (input [WIDTH-1:0] gray, + output reg [WIDTH-1:0] bin); + + integer i; + always @(gray) + for(i = 0;i>i); + +endmodule // gray2bin diff --git a/usrp2/control_lib/gray_send.v b/usrp2/control_lib/gray_send.v new file mode 100644 index 000000000..7fc07d40c --- /dev/null +++ b/usrp2/control_lib/gray_send.v @@ -0,0 +1,29 @@ + + + +module gray_send + #(parameter WIDTH = 8) + (input clk_in, input [WIDTH-1:0] addr_in, + input clk_out, output reg [WIDTH-1:0] addr_out); + + reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1; + wire [WIDTH-1:0] gray, bin; + + bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) ); + + always @(posedge clk_in) + gray_clkin <= gray; + + always @(posedge clk_out) + gray_clkout <= gray_clkin; + + always @(posedge clk_out) + gray_clkout_d1 <= gray_clkout; + + gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) ); + + // FIXME we may not need the next register, but it may help timing + always @(posedge clk_out) + addr_out <= bin; + +endmodule // gray_send diff --git a/usrp2/control_lib/icache.v b/usrp2/control_lib/icache.v new file mode 100644 index 000000000..bd21f47cc --- /dev/null +++ b/usrp2/control_lib/icache.v @@ -0,0 +1,135 @@ + +module icache + #(parameter AWIDTH=14, + parameter CWIDTH=6) + + (input wb_clk_i, + input wb_rst_i, + input [AWIDTH-1:0] iwb_adr_i, + input iwb_stb_i, + output [31:0] iwb_dat_o, + output iwb_ack_o, + input [31:0] iram_dat_i, + output [AWIDTH-1:0] iram_adr_o, + output iram_en_o, + input flush); + + localparam TAGWIDTH = AWIDTH-CWIDTH-2; + reg stb_d1, ack_d1, miss_d1; + reg [AWIDTH-1:0] held_addr; + reg [31:0] idata [0:(1< clear $end +$var wire 1 ? clk $end +$var wire 36 @ datain [35:0] $end +$var wire 36 A dataout [35:0] $end +$var wire 1 $ dst_rdy_i $end +$var wire 1 ! dst_rdy_o $end +$var wire 1 B read $end +$var wire 1 C reset $end +$var wire 1 D src_rdy_i $end +$var wire 1 % src_rdy_o $end +$var wire 1 E write $end +$var reg 4 F a [3:0] $end +$var reg 1 G empty $end +$var reg 1 H full $end +$var reg 5 I occupied [4:0] $end +$var reg 5 J space [4:0] $end +$scope begin gen_srl16[0] $end +$scope module srl16e $end +$var wire 1 K A0 $end +$var wire 1 L A1 $end +$var wire 1 M A2 $end +$var wire 1 N A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 O D $end +$var wire 1 P Q $end +$var reg 16 Q data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[1] $end +$scope module srl16e $end +$var wire 1 R A0 $end +$var wire 1 S A1 $end +$var wire 1 T A2 $end +$var wire 1 U A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 V D $end +$var wire 1 W Q $end +$var reg 16 X data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[2] $end +$scope module srl16e $end +$var wire 1 Y A0 $end +$var wire 1 Z A1 $end +$var wire 1 [ A2 $end +$var wire 1 \ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ] D $end +$var wire 1 ^ Q $end +$var reg 16 _ data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[3] $end +$scope module srl16e $end +$var wire 1 ` A0 $end +$var wire 1 a A1 $end +$var wire 1 b A2 $end +$var wire 1 c A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 d D $end +$var wire 1 e Q $end +$var reg 16 f data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[4] $end +$scope module srl16e $end +$var wire 1 g A0 $end +$var wire 1 h A1 $end +$var wire 1 i A2 $end +$var wire 1 j A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 k D $end +$var wire 1 l Q $end +$var reg 16 m data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[5] $end +$scope module srl16e $end +$var wire 1 n A0 $end +$var wire 1 o A1 $end +$var wire 1 p A2 $end +$var wire 1 q A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 r D $end +$var wire 1 s Q $end +$var reg 16 t data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[6] $end +$scope module srl16e $end +$var wire 1 u A0 $end +$var wire 1 v A1 $end +$var wire 1 w A2 $end +$var wire 1 x A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 y D $end +$var wire 1 z Q $end +$var reg 16 { data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[7] $end +$scope module srl16e $end +$var wire 1 | A0 $end +$var wire 1 } A1 $end +$var wire 1 ~ A2 $end +$var wire 1 !" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 "" D $end +$var wire 1 #" Q $end +$var reg 16 $" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[8] $end +$scope module srl16e $end +$var wire 1 %" A0 $end +$var wire 1 &" A1 $end +$var wire 1 '" A2 $end +$var wire 1 (" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 )" D $end +$var wire 1 *" Q $end +$var reg 16 +" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[9] $end +$scope module srl16e $end +$var wire 1 ," A0 $end +$var wire 1 -" A1 $end +$var wire 1 ." A2 $end +$var wire 1 /" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 0" D $end +$var wire 1 1" Q $end +$var reg 16 2" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[10] $end +$scope module srl16e $end +$var wire 1 3" A0 $end +$var wire 1 4" A1 $end +$var wire 1 5" A2 $end +$var wire 1 6" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 7" D $end +$var wire 1 8" Q $end +$var reg 16 9" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[11] $end +$scope module srl16e $end +$var wire 1 :" A0 $end +$var wire 1 ;" A1 $end +$var wire 1 <" A2 $end +$var wire 1 =" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 >" D $end +$var wire 1 ?" Q $end +$var reg 16 @" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[12] $end +$scope module srl16e $end +$var wire 1 A" A0 $end +$var wire 1 B" A1 $end +$var wire 1 C" A2 $end +$var wire 1 D" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 E" D $end +$var wire 1 F" Q $end +$var reg 16 G" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[13] $end +$scope module srl16e $end +$var wire 1 H" A0 $end +$var wire 1 I" A1 $end +$var wire 1 J" A2 $end +$var wire 1 K" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 L" D $end +$var wire 1 M" Q $end +$var reg 16 N" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[14] $end +$scope module srl16e $end +$var wire 1 O" A0 $end +$var wire 1 P" A1 $end +$var wire 1 Q" A2 $end +$var wire 1 R" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 S" D $end +$var wire 1 T" Q $end +$var reg 16 U" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[15] $end +$scope module srl16e $end +$var wire 1 V" A0 $end +$var wire 1 W" A1 $end +$var wire 1 X" A2 $end +$var wire 1 Y" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 Z" D $end +$var wire 1 [" Q $end +$var reg 16 \" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[16] $end +$scope module srl16e $end +$var wire 1 ]" A0 $end +$var wire 1 ^" A1 $end +$var wire 1 _" A2 $end +$var wire 1 `" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 a" D $end +$var wire 1 b" Q $end +$var reg 16 c" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[17] $end +$scope module srl16e $end +$var wire 1 d" A0 $end +$var wire 1 e" A1 $end +$var wire 1 f" A2 $end +$var wire 1 g" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 h" D $end +$var wire 1 i" Q $end +$var reg 16 j" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[18] $end +$scope module srl16e $end +$var wire 1 k" A0 $end +$var wire 1 l" A1 $end +$var wire 1 m" A2 $end +$var wire 1 n" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 o" D $end +$var wire 1 p" Q $end +$var reg 16 q" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[19] $end +$scope module srl16e $end +$var wire 1 r" A0 $end +$var wire 1 s" A1 $end +$var wire 1 t" A2 $end +$var wire 1 u" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 v" D $end +$var wire 1 w" Q $end +$var reg 16 x" data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[20] $end +$scope module srl16e $end +$var wire 1 y" A0 $end +$var wire 1 z" A1 $end +$var wire 1 {" A2 $end +$var wire 1 |" A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 }" D $end +$var wire 1 ~" Q $end +$var reg 16 !# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[21] $end +$scope module srl16e $end +$var wire 1 "# A0 $end +$var wire 1 ## A1 $end +$var wire 1 $# A2 $end +$var wire 1 %# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 &# D $end +$var wire 1 '# Q $end +$var reg 16 (# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[22] $end +$scope module srl16e $end +$var wire 1 )# A0 $end +$var wire 1 *# A1 $end +$var wire 1 +# A2 $end +$var wire 1 ,# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 -# D $end +$var wire 1 .# Q $end +$var reg 16 /# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[23] $end +$scope module srl16e $end +$var wire 1 0# A0 $end +$var wire 1 1# A1 $end +$var wire 1 2# A2 $end +$var wire 1 3# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 4# D $end +$var wire 1 5# Q $end +$var reg 16 6# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[24] $end +$scope module srl16e $end +$var wire 1 7# A0 $end +$var wire 1 8# A1 $end +$var wire 1 9# A2 $end +$var wire 1 :# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ;# D $end +$var wire 1 <# Q $end +$var reg 16 =# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[25] $end +$scope module srl16e $end +$var wire 1 ># A0 $end +$var wire 1 ?# A1 $end +$var wire 1 @# A2 $end +$var wire 1 A# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 B# D $end +$var wire 1 C# Q $end +$var reg 16 D# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[26] $end +$scope module srl16e $end +$var wire 1 E# A0 $end +$var wire 1 F# A1 $end +$var wire 1 G# A2 $end +$var wire 1 H# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 I# D $end +$var wire 1 J# Q $end +$var reg 16 K# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[27] $end +$scope module srl16e $end +$var wire 1 L# A0 $end +$var wire 1 M# A1 $end +$var wire 1 N# A2 $end +$var wire 1 O# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 P# D $end +$var wire 1 Q# Q $end +$var reg 16 R# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[28] $end +$scope module srl16e $end +$var wire 1 S# A0 $end +$var wire 1 T# A1 $end +$var wire 1 U# A2 $end +$var wire 1 V# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 W# D $end +$var wire 1 X# Q $end +$var reg 16 Y# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[29] $end +$scope module srl16e $end +$var wire 1 Z# A0 $end +$var wire 1 [# A1 $end +$var wire 1 \# A2 $end +$var wire 1 ]# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 ^# D $end +$var wire 1 _# Q $end +$var reg 16 `# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[30] $end +$scope module srl16e $end +$var wire 1 a# A0 $end +$var wire 1 b# A1 $end +$var wire 1 c# A2 $end +$var wire 1 d# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 e# D $end +$var wire 1 f# Q $end +$var reg 16 g# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[31] $end +$scope module srl16e $end +$var wire 1 h# A0 $end +$var wire 1 i# A1 $end +$var wire 1 j# A2 $end +$var wire 1 k# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 l# D $end +$var wire 1 m# Q $end +$var reg 16 n# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[32] $end +$scope module srl16e $end +$var wire 1 o# A0 $end +$var wire 1 p# A1 $end +$var wire 1 q# A2 $end +$var wire 1 r# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 s# D $end +$var wire 1 t# Q $end +$var reg 16 u# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[33] $end +$scope module srl16e $end +$var wire 1 v# A0 $end +$var wire 1 w# A1 $end +$var wire 1 x# A2 $end +$var wire 1 y# A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 z# D $end +$var wire 1 {# Q $end +$var reg 16 |# data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[34] $end +$scope module srl16e $end +$var wire 1 }# A0 $end +$var wire 1 ~# A1 $end +$var wire 1 !$ A2 $end +$var wire 1 "$ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 #$ D $end +$var wire 1 $$ Q $end +$var reg 16 %$ data [15:0] $end +$upscope $end +$upscope $end +$scope begin gen_srl16[35] $end +$scope module srl16e $end +$var wire 1 &$ A0 $end +$var wire 1 '$ A1 $end +$var wire 1 ($ A2 $end +$var wire 1 )$ A3 $end +$var wire 1 E CE $end +$var wire 1 ? CLK $end +$var wire 1 *$ D $end +$var wire 1 +$ Q $end +$var reg 16 ,$ data [15:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module fifo36_to_fifo19 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 -$ f19_dataout [18:0] $end +$var wire 1 ' f19_dst_rdy_i $end +$var wire 1 ( f19_src_rdy_o $end +$var wire 1 .$ f19_xfer $end +$var wire 36 /$ f36_datain [35:0] $end +$var wire 1 $ f36_dst_rdy_o $end +$var wire 1 0$ f36_eof $end +$var wire 1 1$ f36_occ $end +$var wire 1 2$ f36_sof $end +$var wire 1 % f36_src_rdy_i $end +$var wire 1 3$ f36_xfer $end +$var wire 1 4$ half_line $end +$var wire 1 C reset $end +$var reg 1 5$ phase $end +$upscope $end +$scope module fifo19_to_ll8 $end +$var wire 1 6$ advance $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 7$ f19_data [18:0] $end +$var wire 1 ' f19_dst_rdy_o $end +$var wire 1 8$ f19_eof $end +$var wire 1 9$ f19_occ $end +$var wire 1 :$ f19_sof $end +$var wire 1 ( f19_src_rdy_i $end +$var wire 1 ;$ ll_dst_rdy $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 <$ ll_eof $end +$var wire 1 0 ll_eof_n $end +$var wire 1 =$ ll_sof $end +$var wire 1 1 ll_sof_n $end +$var wire 1 >$ ll_src_rdy $end +$var wire 1 2 ll_src_rdy_n $end +$var wire 1 C reset $end +$var reg 8 ?$ ll_data [7:0] $end +$var reg 1 @$ state $end +$upscope $end +$scope module ll8_to_fifo19 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 A$ f19_data [18:0] $end +$var wire 1 * f19_dst_rdy_i $end +$var wire 1 + f19_src_rdy_o $end +$var wire 8 B$ ll_data [7:0] $end +$var wire 1 C$ ll_dst_rdy $end +$var wire 1 / ll_dst_rdy_n $end +$var wire 1 D$ ll_eof $end +$var wire 1 0 ll_eof_n $end +$var wire 1 E$ ll_sof $end +$var wire 1 1 ll_sof_n $end +$var wire 1 F$ ll_src_rdy $end +$var wire 1 2 ll_src_rdy_n $end +$var wire 1 C reset $end +$var wire 1 G$ xfer_out $end +$var reg 8 H$ dat0 [7:0] $end +$var reg 8 I$ dat1 [7:0] $end +$var reg 1 J$ f19_eof $end +$var reg 1 K$ f19_occ $end +$var reg 1 L$ f19_sof $end +$var reg 2 M$ state [1:0] $end +$upscope $end +$scope module fifo19_to_fifo36 $end +$var wire 1 > clear $end +$var wire 1 ? clk $end +$var wire 19 N$ f19_datain [18:0] $end +$var wire 1 * f19_dst_rdy_o $end +$var wire 1 O$ f19_eof $end +$var wire 1 P$ f19_occ $end +$var wire 1 Q$ f19_sof $end +$var wire 1 + f19_src_rdy_i $end +$var wire 36 R$ f36_dataout [35:0] $end +$var wire 1 S$ f36_dst_rdy_i $end +$var wire 1 - f36_src_rdy_o $end +$var wire 1 C reset $end +$var wire 1 T$ xfer_out $end +$var reg 16 U$ dat0 [15:0] $end +$var reg 16 V$ dat1 [15:0] $end +$var reg 1 W$ f36_eof $end +$var reg 1 X$ f36_occ $end +$var reg 1 Y$ f36_sof $end +$var reg 2 Z$ state [1:0] $end +$upscope $end +$scope task PutPacketInFIFO36 $end +$var reg 32 [$ data_len [31:0] $end +$var reg 32 \$ data_start [31:0] $end +$upscope $end +$scope task ReadFromFIFO36 $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx \$ +bx [$ +bx Z$ +xY$ +xX$ +xW$ +bx V$ +bx U$ +0T$ +0S$ +b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx R$ +xQ$ +xP$ +xO$ +bx N$ +bx M$ +xL$ +xK$ +xJ$ +bx I$ +bx H$ +xG$ +xF$ +xE$ +xD$ +xC$ +bx B$ +bx A$ +x@$ +bx ?$ +x>$ +x=$ +x<$ +x;$ +x:$ +x9$ +x8$ +bx 7$ +x6$ +x5$ +x4$ +x3$ +x2$ +x1$ +x0$ +bx /$ +x.$ +bx -$ +b0 ,$ +x+$ +0*$ +x)$ +x($ +x'$ +x&$ +b0 %$ +x$$ +0#$ +x"$ +x!$ +x~# +x}# +b0 |# +x{# +0z# +xy# +xx# +xw# +xv# +b0 u# +xt# +0s# +xr# +xq# +xp# +xo# +b0 n# +xm# +0l# +xk# +xj# +xi# +xh# +b0 g# +xf# +0e# +xd# +xc# +xb# +xa# +b0 `# +x_# +0^# +x]# +x\# +x[# +xZ# +b0 Y# +xX# +0W# +xV# +xU# +xT# +xS# +b0 R# +xQ# +0P# +xO# +xN# +xM# +xL# +b0 K# +xJ# +0I# +xH# +xG# +xF# +xE# +b0 D# +xC# +0B# +xA# +x@# +x?# +x># +b0 =# +x<# +0;# +x:# +x9# +x8# +x7# +b0 6# +x5# +04# +x3# +x2# +x1# +x0# +b0 /# +x.# +0-# +x,# +x+# +x*# +x)# +b0 (# +x'# +0&# +x%# +x$# +x## +x"# +b0 !# +x~" +0}" +x|" +x{" +xz" +xy" +b0 x" +xw" +0v" +xu" +xt" +xs" +xr" +b0 q" +xp" +0o" +xn" +xm" +xl" +xk" +b0 j" +xi" +0h" +xg" +xf" +xe" +xd" +b0 c" +xb" +0a" +x`" +x_" +x^" +x]" +b0 \" +x[" +0Z" +xY" +xX" +xW" +xV" +b0 U" +xT" +0S" +xR" +xQ" +xP" +xO" +b0 N" +xM" +0L" +xK" +xJ" +xI" +xH" +b0 G" +xF" +0E" +xD" +xC" +xB" +xA" +b0 @" +x?" +0>" +x=" +x<" +x;" +x:" +b0 9" +x8" +07" +x6" +x5" +x4" +x3" +b0 2" +x1" +00" +x/" +x." +x-" +x," +b0 +" +x*" +0)" +x(" +x'" +x&" +x%" +b0 $" +x#" +0"" +x!" +x~ +x} +x| +b0 { +xz +0y +xx +xw +xv +xu +b0 t +xs +0r +xq +xp +xo +xn +b0 m +xl +0k +xj +xi +xh +xg +b0 f +xe +0d +xc +xb +xa +x` +b0 _ +x^ +0] +x\ +x[ +xZ +xY +b0 X +xW +0V +xU +xT +xS +xR +b0 Q +xP +0O +xN +xM +xL +xK +bx J +bx I +xH +xG +bx F +0E +0D +1C +xB +bx A +b0 @ +0? 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+#19900000000000000 +04 +0? +#19950000000000000 +14 +1? +#20000000000000000 +04 +0? diff --git a/usrp2/control_lib/newfifo/fifo_short.v b/usrp2/control_lib/newfifo/fifo_short.v new file mode 100644 index 000000000..53a7603c7 --- /dev/null +++ b/usrp2/control_lib/newfifo/fifo_short.v @@ -0,0 +1,95 @@ + +module fifo_short + #(parameter WIDTH=32) + (input clk, input reset, input clear, + input [WIDTH-1:0] datain, + input src_rdy_i, + output dst_rdy_o, + output [WIDTH-1:0] dataout, + output src_rdy_o, + input dst_rdy_i, + + output reg [4:0] space, + output reg [4:0] occupied); + + reg full, empty; + wire write = src_rdy_i & dst_rdy_o; + wire read = dst_rdy_i & src_rdy_o; + + assign dst_rdy_o = ~full; + assign src_rdy_o = ~empty; + + reg [3:0] a; + genvar i; + + generate + for (i=0;i 00 = all 4 bytes + 01 = 1 byte + 10 = 2 bytes + 11 = 3 bytes + +fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]} + OCC same as buffer interface + +fifo19 --> {OCC,EOP,SOP,DATA[15:0]} + Doesn't fit well into BRAM, dist RAM ok + OCC = 1 means last word is half full + = 0 means last word is full + +fifo18 --> {EOP,SOP,DATA[15:0]} + No half-word capability? Should we drop sop instead? + +Control Wires - Data into FIFO + SRC_RDY_i Upstream has data for me + DST_RDY_o I have space + Transfer occurs if SRC_RDI_i && DST_RDY_o + +Control Wires - Data out of FIFO + SRC_RDY_o I have data for downstream + DST_RDY_i Downstream has space + Transfer occurs if SRC_RDI_o && DST_RDY_i + diff --git a/usrp2/control_lib/newfifo/fifo_tb.v b/usrp2/control_lib/newfifo/fifo_tb.v new file mode 100644 index 000000000..f561df7fa --- /dev/null +++ b/usrp2/control_lib/newfifo/fifo_tb.v @@ -0,0 +1,158 @@ +module fifo_new_tb(); + + reg clk = 0; + reg rst = 1; + reg clear = 0; + initial #1000 rst = 0; + always #50 clk = ~clk; + + reg [31:0] f36_data = 0; + reg [1:0] f36_occ = 0; + reg f36_sof = 0, f36_eof = 0; + + wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; + reg src_rdy_f36i = 0; + wire dst_rdy_f36i; + + wire [35:0] f36_out, f36_out2; + wire src_rdy_f36o; + reg dst_rdy_f36o = 0; + + //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36 + //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 + + wire i1_sr, i1_dr; + wire i2_sr, i2_dr; + wire i3_sr, i3_dr; + reg i4_dr = 0; + wire i4_sr; + + wire [35:0] i1, i4; + wire [18:0] i2, i3; + + wire [7:0] ll_data; + wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n; + + fifo_short #(.WIDTH(36)) fifo_short1 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), + .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) ); + + fifo36_to_fifo19 fifo36_to_fifo19 + (.clk(clk),.reset(rst),.clear(clear), + .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr), + .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) ); + + fifo19_to_ll8 fifo19_to_ll8 + (.clk(clk),.reset(rst),.clear(clear), + .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr), + .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n)); + + ll8_to_fifo19 ll8_to_fifo19 + (.clk(clk),.reset(rst),.clear(clear), + .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n), + .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk),.reset(rst),.clear(clear), + .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr), + .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) ); + + task ReadFromFIFO36; + begin + $display("Read from FIFO36"); + #1 i4_dr <= 1; + while(1) + begin + while(~i4_sr) + @(posedge clk); + $display("Read: %h",i4); + @(posedge clk); + end + end + endtask // ReadFromFIFO36 + + reg [15:0] count; + task PutPacketInFIFO36; + input [31:0] data_start; + input [31:0] data_len; + begin + count <= 4; + src_rdy_f36i <= 1; + f36_data <= data_start; + f36_sof <= 1; + f36_eof <= 0; + f36_occ <= 0; + + $display("Put Packet in FIFO36"); + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + $display("PPI_FIFO36: Entered First Line"); + f36_sof <= 0; + while(count+4 < data_len) + begin + f36_data <= f36_data + 32'h01010101; + count <= count + 4; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + $display("PPI_FIFO36: Entered New Line"); + end + f36_data <= f36_data + 32'h01010101; + f36_eof <= 1; + if(count + 4 == data_len) + f36_occ <= 0; + else if(count + 3 == data_len) + f36_occ <= 3; + else if(count + 2 == data_len) + f36_occ <= 2; + else + f36_occ <= 1; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + f36_occ <= 0; + f36_eof <= 0; + f36_data <= 0; + src_rdy_f36i <= 0; + $display("PPI_FIFO36: Entered Last Line"); + end + endtask // PutPacketInFIFO36 + + initial $dumpfile("fifo_new_tb.vcd"); + initial $dumpvars(0,fifo_new_tb); + + initial + begin + @(negedge rst); + //#10000; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + ReadFromFIFO36; + end + + initial + begin + @(negedge rst); + @(posedge clk); + @(posedge clk); + PutPacketInFIFO36(32'hA0B0C0D0,12); + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); + PutPacketInFIFO36(32'hE0F0A0B0,36); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + + initial #20000 $finish; +endmodule // longfifo_tb diff --git a/usrp2/control_lib/newfifo/ll8_shortfifo.v b/usrp2/control_lib/newfifo/ll8_shortfifo.v new file mode 100644 index 000000000..39ada9a4f --- /dev/null +++ b/usrp2/control_lib/newfifo/ll8_shortfifo.v @@ -0,0 +1,13 @@ + + +module ll8_shortfifo + (input clk, input reset, input clear, + input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o, + output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i); + + fifo_short #(.WIDTH(11)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + +endmodule // ll8_shortfifo diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo19.v b/usrp2/control_lib/newfifo/ll8_to_fifo19.v new file mode 100644 index 000000000..c65be5136 --- /dev/null +++ b/usrp2/control_lib/newfifo/ll8_to_fifo19.v @@ -0,0 +1,77 @@ + +module ll8_to_fifo19 + (input clk, input reset, input clear, + input [7:0] ll_data, + input ll_sof_n, + input ll_eof_n, + input ll_src_rdy_n, + output ll_dst_rdy_n, + + output [18:0] f19_data, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + + // Why anybody would use active low in an FPGA is beyond me... + wire ll_sof = ~ll_sof_n; + wire ll_eof = ~ll_eof_n; + wire ll_src_rdy = ~ll_src_rdy_n; + wire ll_dst_rdy; + assign ll_dst_rdy_n = ~ll_dst_rdy; + + wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i; + // wire xfer_in = ll_src_rdy & ll_dst_rdy; Not needed + + reg f19_sof, f19_eof, f19_occ; + + reg [1:0] state; + reg [7:0] dat0, dat1; + + always @(posedge clk) + if(ll_src_rdy & ((state==0)|xfer_out)) + f19_sof <= ll_sof; + + always @(posedge clk) + if(ll_src_rdy & ((state != 2)|xfer_out)) + f19_eof <= ll_eof; + + always @(posedge clk) + if(ll_eof) + f19_occ <= ~state[0]; + else + f19_occ <= 0; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(ll_src_rdy) + case(state) + 0 : + if(ll_eof) + state <= 2; + else + state <= 1; + 1 : + state <= 2; + 2 : + if(xfer_out) + state <= 1; + endcase // case(state) + else + if(xfer_out) + state <= 0; + + always @(posedge clk) + if(ll_src_rdy & (state==1)) + dat1 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & ((state==0) | xfer_out)) + dat0 <= ll_data; + + assign ll_dst_rdy = xfer_out | (state != 2); + assign f19_data = {f19_occ,f19_eof,f19_sof,dat0,dat1}; + assign f19_src_rdy_o = (state == 2); + +endmodule // ll8_to_fifo19 + diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo36.v b/usrp2/control_lib/newfifo/ll8_to_fifo36.v new file mode 100644 index 000000000..108daa903 --- /dev/null +++ b/usrp2/control_lib/newfifo/ll8_to_fifo36.v @@ -0,0 +1,97 @@ + +module ll8_to_fifo36 + (input clk, input reset, input clear, + input [7:0] ll_data, + input ll_sof_n, + input ll_eof_n, + input ll_src_rdy_n, + output ll_dst_rdy_n, + + output [35:0] f36_data, + output f36_src_rdy_o, + input f36_dst_rdy_i ); + + wire f36_write = f36_src_rdy_o & f36_dst_rdy_i; + + // Why anybody would use active low in an FPGA is beyond me... + wire ll_sof = ~ll_sof_n; + wire ll_eof = ~ll_eof_n; + wire ll_src_rdy = ~ll_src_rdy_n; + wire ll_dst_rdy; + assign ll_dst_rdy_n = ~ll_dst_rdy; + + reg f36_sof, f36_eof; + reg [1:0] f36_occ; + + + reg [2:0] state; + reg [7:0] dat0, dat1, dat2, dat3; + + always @(posedge clk) + if(ll_src_rdy & ((state==0)|f36_write)) + f36_sof <= ll_sof; + + always @(posedge clk) + if(ll_src_rdy & ((state !=4)|f36_write)) + f36_eof <= ll_eof; + + always @(posedge clk) + if(ll_eof) + f36_occ <= state[1:0] + 1; + else + f36_occ <= 0; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(ll_src_rdy) + case(state) + 0 : + if(ll_eof) + state <= 4; + else + state <= 1; + 1 : + if(ll_eof) + state <= 4; + else + state <= 2; + 2 : + if(ll_eof) + state <= 4; + else + state <= 3; + 3 : state <= 4; + 4 : + if(f36_dst_rdy_i) + if(ll_eof) + state <= 4; + else + state <= 1; + endcase // case(state) + else + if(f36_write) + state <= 0; + + always @(posedge clk) + if(ll_src_rdy & (state==3)) + dat3 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & (state==2)) + dat2 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & (state==1)) + dat1 <= ll_data; + + always @(posedge clk) + if(ll_src_rdy & ((state==0) | f36_write)) + dat0 <= ll_data; + + assign ll_dst_rdy = f36_dst_rdy_i | (state != 4); + assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess + assign f36_src_rdy_o = (state == 4); + +endmodule // ll8_to_fifo36 diff --git a/usrp2/control_lib/nsgpio.v b/usrp2/control_lib/nsgpio.v new file mode 100644 index 000000000..937ea7020 --- /dev/null +++ b/usrp2/control_lib/nsgpio.v @@ -0,0 +1,107 @@ +// Modified from code originally by Richard Herveille, his copyright is below + +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple General Purpose IO core //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +module nsgpio + (input clk_i, input rst_i, + input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0] dat_i, + output reg [31:0] dat_o, output reg ack_o, + input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, + inout [31:0] gpio + ); + + reg [63:0] ctrl; + reg [31:0] line; + reg [31:0] lgpio; // LatchedGPIO pins + reg [31:0] ddr; + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + begin + ctrl <= 64'h0; + line <= 0; + end + else if (wb_wr) + case( adr_i[3:2] ) + 2'b00 : + line <= dat_i; + 2'b01 : + ddr[31:0] <= dat_i; + 2'b10 : + ctrl[63:32] <= dat_i; + 2'b11 : + ctrl[31:0] <= dat_i; + endcase // case( adr_i[3:2] ) + + always @(posedge clk_i) + case (adr_i[3:2]) + 2'b00 : + dat_o <= lgpio; + 2'b01 : + dat_o <= ddr; + 2'b10 : + dat_o <= ctrl[63:32]; + 2'b11 : + dat_o <= ctrl[31:0]; + endcase // case(adr_i[3:2]) + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + ack_o <= 1'b0; + else + ack_o <= wb_acc & !ack_o; + + // latch GPIO input pins + always @(posedge clk_i) + lgpio <= gpio; + + // assign GPIO outputs + integer n; + reg [31:0] igpio; // temporary internal signal + + always @(ctrl or line or debug_1 or debug_0 or atr) + for(n=0;n<32;n=n+1) + igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : + (ctrl[2*n] ? atr[n] : line[n]) ) + : 1'bz; + + assign gpio = igpio; + +endmodule + diff --git a/usrp2/control_lib/oneshot_2clk.v b/usrp2/control_lib/oneshot_2clk.v new file mode 100644 index 000000000..72f16a4b3 --- /dev/null +++ b/usrp2/control_lib/oneshot_2clk.v @@ -0,0 +1,35 @@ + +// Retime a single bit from one clock domain to another +// Guarantees that no matter what the relative clock rates, if the in signal is high for at least +// one clock cycle in the clk_in domain, then the out signal will be high for at least one +// clock cycle in the clk_out domain. If the in signal goes high again before the process is done +// the behavior is undefined. No other guarantees. Designed for passing reset into a new +// clock domain. + +module oneshot_2clk + (input clk_in, + input in, + input clk_out, + output reg out); + + reg del_in = 0; + reg sendit = 0, gotit = 0; + reg sendit_d = 0, gotit_d = 0; + + always @(posedge clk_in) del_in <= in; + + always @(posedge clk_in) + if(in & ~del_in) // we have a positive edge + sendit <= 1; + else if(gotit) + sendit <= 0; + + always @(posedge clk_out) sendit_d <= sendit; + always @(posedge clk_out) out <= sendit_d; + + always @(posedge clk_in) gotit_d <= out; + always @(posedge clk_in) gotit <= gotit_d; + +endmodule // oneshot_2clk + + diff --git a/usrp2/control_lib/pic.v b/usrp2/control_lib/pic.v new file mode 100644 index 000000000..9b9944d4a --- /dev/null +++ b/usrp2/control_lib/pic.v @@ -0,0 +1,183 @@ + +// Heavily modified by M. Ettus, 2009, little original code remains +// Modified by M. Ettus, 2008 for 32 bit width + +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple Programmable Interrupt Controller //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +// +// This is a simple Programmable Interrupt Controller. +// The number of interrupts is depending on the databus size. +// There's one interrupt input per databit (i.e. 16 interrupts for a 16 +// bit databus). +// All attached devices share the same CPU priority level. +// +// +// +// Registers: +// +// 0x00: EdgeEnable Register +// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source +// '0' = level triggered interrupt source +// 0x01: PolarityRegister +// bits 7:0 R/W Polarity '1' = high level / rising edge +// '0' = low level / falling edge +// 0x02: MaskRegister +// bits 7:0 R/W Mask '1' = interrupt masked (disabled) +// '0' = interrupt not masked (enabled) +// 0x03: PendingRegister +// bits 7:0 R/W Pending '1' = interrupt pending +// '0' = no interrupt pending +// +// A CPU interrupt is generated when an interrupt is pending and its +// MASK bit is cleared. +// +// +// +// HOWTO: +// +// Clearing pending interrupts: +// Writing a '1' to a bit in the interrupt pending register clears the +// interrupt. Make sure to clear the interrupt at the source before +// writing to the interrupt pending register. Otherwise the interrupt +// will be set again. +// +// Priority based interrupts: +// Upon reception of an interrupt, check the interrupt register and +// determine the highest priority interrupt. Mask all interrupts from the +// current level to the lowest level. This negates the interrupt line, and +// makes sure only interrupts with a higher level are triggered. After +// completion of the interrupt service routine, clear the interrupt source, +// the interrupt bit in the pending register, and restore the MASK register +// to it's previous state. +// +// Addapt the core for fewer interrupt sources: +// If less than 8 interrupt sources are required, than the 'is' parameter +// can be set to the amount of required interrupts. Interrupts are mapped +// starting at the LSBs. So only the 'is' LSBs per register are valid. All +// other bits (i.e. the 8-'is' MSBs) are set to zero '0'. +// Codesize is approximately linear to the amount of interrupts. I.e. using +// 4 instead of 8 interrupt sources reduces the size by approx. half. +// + + +module pic + (input clk_i, input rst_i, input cyc_i, input stb_i, + input [2:0] adr_i, + input we_i, + input [31:0] dat_i, + output reg [31:0] dat_o, + output reg ack_o, + output reg int_o, + input [31:0] irq + ); + + reg [31:0] pol, edgen, pending, mask; // register bank + reg [31:0] lirq, dirq; // latched irqs, delayed latched irqs + + // latch interrupt inputs + always @(posedge clk_i) + lirq <= irq; + + // generate delayed latched irqs + always @(posedge clk_i) + dirq <= lirq; + + // generate actual triggers + function trigger; + input edgen, pol, lirq, dirq; + reg edge_irq, level_irq; + begin + edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq); + level_irq = pol ? lirq : ~lirq; + trigger = edgen ? edge_irq : level_irq; + end + endfunction + + reg [31:0] irq_event; + integer n; + always @(posedge clk_i) + for(n = 0; n < 32; n = n+1) + irq_event[n] <= trigger(edgen[n], pol[n], lirq[n], dirq[n]); + + // generate wishbone register bank writes + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i) + if (rst_i) + begin + pol <= 0; // clear polarity register + edgen <= 0; // clear edge enable register + mask <= 0; // mask all interrupts + end + else if(wb_wr) // wishbone write cycle?? + case (adr_i) // synopsys full_case parallel_case + 3'd0 : edgen <= dat_i; // EDGE-ENABLE register + 3'd1 : pol <= dat_i; // POLARITY register + 3'd2 : mask <= dat_i; // MASK register + 3'd3 : ; // PENDING register is a special case (see below) + 3'd4 : ; // Priority encoded live (pending & ~mask) + endcase + + // pending register is a special case + always @(posedge clk_i) + if (rst_i) + pending <= 0; // clear all pending interrupts + else if ( wb_wr & (adr_i == 3'd3) ) + pending <= (pending & ~dat_i) | irq_event; + else + pending <= pending | irq_event; + + wire [31:0] live_enc; + priority_enc priority_enc ( .in(pending & ~mask), .out(live_enc) ); + + always @(posedge clk_i) + case (adr_i) // synopsys full_case parallel_case + 3'd0 : dat_o <= edgen; + 3'd1 : dat_o <= pol; + 3'd2 : dat_o <= mask; + 3'd3 : dat_o <= pending; + 3'd4 : dat_o <= live_enc; + endcase + + always @(posedge clk_i) + ack_o <= wb_acc & !ack_o; + + always @(posedge clk_i) + if(rst_i) + int_o <= 0; + else + int_o <= |(pending & ~mask); + +endmodule diff --git a/usrp2/control_lib/priority_enc.v b/usrp2/control_lib/priority_enc.v new file mode 100644 index 000000000..916192445 --- /dev/null +++ b/usrp2/control_lib/priority_enc.v @@ -0,0 +1,44 @@ + +module priority_enc + (input [31:0] in, + output reg [31:0] out); + + always @* + casex(in) + 32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 31; + 32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 30; + 32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 29; + 32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 28; + 32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 27; + 32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 26; + 32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 25; + 32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 24; + 32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 23; + 32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 22; + 32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 21; + 32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 20; + 32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : out <= 19; + 32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : out <= 18; + 32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : out <= 17; + 32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : out <= 16; + 32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : out <= 15; + 32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : out <= 14; + 32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : out <= 13; + 32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : out <= 12; + 32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : out <= 11; + 32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : out <= 10; + 32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : out <= 9; + 32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : out <= 8; + 32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : out <= 7; + 32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : out <= 6; + 32'b0000_0000_0000_0000_0000_0000_001x_xxxx : out <= 5; + 32'b0000_0000_0000_0000_0000_0000_0001_xxxx : out <= 4; + 32'b0000_0000_0000_0000_0000_0000_0000_1xxx : out <= 3; + 32'b0000_0000_0000_0000_0000_0000_0000_01xx : out <= 2; + 32'b0000_0000_0000_0000_0000_0000_0000_001x : out <= 1; + 32'b0000_0000_0000_0000_0000_0000_0000_0001 : out <= 0; + 32'b0000_0000_0000_0000_0000_0000_0000_0000 : out <= 32'hFFFF_FFFF; + default : out <= 32'hFFFF_FFFF; + endcase // casex (in) + +endmodule // priority_enc diff --git a/usrp2/control_lib/ram_2port.v b/usrp2/control_lib/ram_2port.v new file mode 100644 index 000000000..6c8332b9c --- /dev/null +++ b/usrp2/control_lib/ram_2port.v @@ -0,0 +1,42 @@ + + +module ram_2port + #(parameter DWIDTH=32, + parameter AWIDTH=9) + (input clka, + input ena, + input wea, + input [AWIDTH-1:0] addra, + input [DWIDTH-1:0] dia, + output reg [DWIDTH-1:0] doa, + + input clkb, + input enb, + input web, + input [AWIDTH-1:0] addrb, + input [DWIDTH-1:0] dib, + output reg [DWIDTH-1:0] dob); + + reg [DWIDTH-1:0] ram [(1<>1)); + wire latch_dat = (clk_ctr == (clk_div - 8'd2)); + wire send_clk_lo = (clk_ctr == (clk_div - 8'd1)); + + wire send_bit = (bit_ready && (bit_ctr != 0)); + assign ready = (bit_ctr == 0); + + always @(posedge clk) + if(rst) + clk_ctr <= 0; + else if(bit_done) + clk_ctr <= 0; + else if(bit_busy) + clk_ctr <= clk_ctr + 1; + else if(send_bit) + clk_ctr <= 1; + + always @(posedge clk) + if(rst) + sd_clk <= 0; + else if(send_clk_hi) + sd_clk <= 1; + else if(send_clk_lo) + sd_clk <= 0; + + always @(posedge clk) + if(rst) + bit_ctr <= 0; + else if(bit_done) + if(bit_ctr == 4'd8) + bit_ctr <= 0; + else + bit_ctr <= bit_ctr + 1; + else if(bit_ready & go) + bit_ctr <= 1; + + reg [7:0] shift_reg; + always @(posedge clk) + if(go) + shift_reg <= send_dat; + else if(latch_dat) + shift_reg <= {shift_reg[6:0],sd_miso}; + + assign sd_mosi = shift_reg[7]; + assign rcv_dat = shift_reg; + +endmodule // sd_spi diff --git a/usrp2/control_lib/sd_spi_tb.v b/usrp2/control_lib/sd_spi_tb.v new file mode 100644 index 000000000..e30a5bdf6 --- /dev/null +++ b/usrp2/control_lib/sd_spi_tb.v @@ -0,0 +1,40 @@ + + +module sd_spi_tb; + + reg clk = 0; + always #5 clk = ~clk; + reg rst = 1; + initial #32 rst = 0; + + wire sd_clk, sd_mosi, sd_miso; + wire [7:0] clk_div = 12; + wire [7:0] send_dat = 23; + wire [7:0] rcv_dat; + + wire ready; + reg go = 0; + initial + begin + repeat (100) + @(posedge clk); + go <= 1; + @(posedge clk); + go <= 0; + end + + sd_spi dut(.clk(clk),.rst(rst), + .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat), + .go(go),.ready(ready) ); + + initial + begin + $dumpfile("sd_spi_tb.vcd"); + $dumpvars(0,sd_spi_tb); + end + + initial + #10000 $finish(); + +endmodule // sd_spi_tb diff --git a/usrp2/control_lib/sd_spi_wb.v b/usrp2/control_lib/sd_spi_wb.v new file mode 100644 index 000000000..7a6258b56 --- /dev/null +++ b/usrp2/control_lib/sd_spi_wb.v @@ -0,0 +1,76 @@ + +// Wishbone module for spi communications with an SD Card +// The programming interface is simple -- +// Write the desired clock divider to address 1 (should be 1 or higher) +// Status is in address 0. A 1 indicates the last transaction is done and it is safe to +// send another +// Writing a byte to address 2 sends that byte over SPI. When it is done, +// status (addr 0) goes high again, and the received byte can be read from address 3. + +module sd_spi_wb + (input clk, + input rst, + + // SD Card interface + output sd_clk, + output sd_csn, + output sd_mosi, + input sd_miso, + + input wb_cyc_i, + input wb_stb_i, + input wb_we_i, + input [1:0] wb_adr_i, + input [7:0] wb_dat_i, + output reg [7:0] wb_dat_o, + output reg wb_ack_o); + + localparam ADDR_STATUS = 0; + localparam ADDR_CLKDIV = 1; + localparam ADDR_WRITE = 2; + localparam ADDR_READ = 3; + + wire [7:0] status, rcv_dat; + reg [7:0] clkdiv; + wire ready; + reg ack_d1; + + reg cs_reg; + assign sd_csn = ~cs_reg; // FIXME + + always @(posedge clk) + if(rst) ack_d1 <= 0; + else ack_d1 <= wb_ack_o; + + always @(posedge clk) + if(rst) wb_ack_o <= 0; + else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1; + + always @(posedge clk) + case(wb_adr_i) + ADDR_STATUS : wb_dat_o <= {7'd0,ready}; + ADDR_CLKDIV : wb_dat_o <= clkdiv; + ADDR_READ : wb_dat_o <= rcv_dat; + default : wb_dat_o <= 0; + endcase // case(wb_adr_i) + + always @(posedge clk) + if(rst) + begin + clkdiv <= 200; + cs_reg <= 0; + end + else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o) + case(wb_adr_i) + ADDR_STATUS : cs_reg <= wb_dat_i; + ADDR_CLKDIV : clkdiv <= wb_dat_i; + endcase // case(wb_adr_i) + + wire go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE); + + sd_spi sd_spi(.clk(clk),.rst(rst), + .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat), + .go(go),.ready(ready) ); + +endmodule // sd_spi_wb diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v new file mode 100644 index 000000000..ccbaa3d2e --- /dev/null +++ b/usrp2/control_lib/setting_reg.v @@ -0,0 +1,23 @@ + + +module setting_reg + #(parameter my_addr = 0) + (input clk, input rst, input strobe, input wire [7:0] addr, + input wire [31:0] in, output reg [31:0] out, output reg changed); + + always @(posedge clk) + if(rst) + begin + out <= 32'd0; + changed <= 1'b0; + end + else + if(strobe & (my_addr==addr)) + begin + out <= in; + changed <= 1'b1; + end + else + changed <= 1'b0; + +endmodule // setting_reg diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v new file mode 100644 index 000000000..d01a30ab4 --- /dev/null +++ b/usrp2/control_lib/settings_bus.v @@ -0,0 +1,49 @@ + +// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock + +module settings_bus + #(parameter AWIDTH=16, parameter DWIDTH=32) + (input wb_clk, + input wb_rst, + input [AWIDTH-1:0] wb_adr_i, + input [DWIDTH-1:0] wb_dat_i, + input wb_stb_i, + input wb_we_i, + output reg wb_ack_o, + input sys_clk, + output strobe, + output reg [7:0] addr, + output reg [31:0] data); + + reg stb_int, stb_int_d1; + + always @(posedge wb_clk) + if(wb_rst) + begin + stb_int <= 1'b0; + addr <= 8'd0; + data <= 32'd0; + end + else if(wb_we_i & wb_stb_i) + begin + stb_int <= 1'b1; + addr <= wb_adr_i[9:2]; + data <= wb_dat_i; + end + else + stb_int <= 1'b0; + + always @(posedge wb_clk) + if(wb_rst) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + always @(posedge wb_clk) + stb_int_d1 <= stb_int; + + //assign strobe = stb_int & ~stb_int_d1; + assign strobe = stb_int & wb_ack_o; + +endmodule // settings_bus + diff --git a/usrp2/control_lib/shortfifo.v b/usrp2/control_lib/shortfifo.v new file mode 100644 index 000000000..d8ce1428e --- /dev/null +++ b/usrp2/control_lib/shortfifo.v @@ -0,0 +1,87 @@ + +module shortfifo + #(parameter WIDTH=32) + (input clk, input rst, + input [WIDTH-1:0] datain, + output [WIDTH-1:0] dataout, + input read, + input write, + input clear, + output reg full, + output reg empty, + output reg [4:0] space, + output reg [4:0] occupied); + + reg [3:0] a; + genvar i; + + generate + for (i=0;i>1); + wire stop_now = (bit_ctr == 10) && shift_now; + wire go_now = (bit_ctr == 0) && neg_trans; + + always @(posedge clk) + if(rst) + sr <= 0; + else if(shift_now) + sr <= {rx_d2,sr[7:1]}; + + always @(posedge clk) + if(rst) + baud_ctr <= 0; + else + if(go_now) + baud_ctr <= 1; + else if(stop_now) + baud_ctr <= 0; + else if(baud_ctr >= clkdiv) + baud_ctr <= 1; + else if(baud_ctr != 0) + baud_ctr <= baud_ctr + 1; + + always @(posedge clk) + if(rst) + bit_ctr <= 0; + else + if(go_now) + bit_ctr <= 1; + else if(stop_now) + bit_ctr <= 0; + else if(baud_ctr == clkdiv) + bit_ctr <= bit_ctr + 1; + + wire full; + wire write = ~full & rx_d2 & stop_now; + + medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo + (.clk(clk),.rst(rst), + .datain(sr),.write(write),.full(full), + .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty), + .clear(0),.space(),.occupied(fifo_level) ); + +endmodule // simple_uart_rx diff --git a/usrp2/control_lib/simple_uart_tx.v b/usrp2/control_lib/simple_uart_tx.v new file mode 100644 index 000000000..e11a347ed --- /dev/null +++ b/usrp2/control_lib/simple_uart_tx.v @@ -0,0 +1,60 @@ + +module simple_uart_tx + #(parameter DEPTH=0) + (input clk, input rst, + input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output fifo_full, + input [15:0] clkdiv, output baudclk, output reg tx); + + reg [15:0] baud_ctr; + reg [3:0] bit_ctr; + + wire read, empty; + wire [7:0] char_to_send; + + medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo + (.clk(clk),.rst(rst), + .datain(fifo_in),.write(fifo_write),.full(fifo_full), + .dataout(char_to_send),.read(read),.empty(empty), + .clear(0),.space(fifo_level),.occupied() ); + + always @(posedge clk) + if(rst) + baud_ctr <= 0; + else if (baud_ctr >= clkdiv) + baud_ctr <= 0; + else + baud_ctr <= baud_ctr + 1; + + always @(posedge clk) + if(rst) + bit_ctr <= 0; + else if(baud_ctr == clkdiv) + if(bit_ctr == 9) + bit_ctr <= 0; + else if(bit_ctr != 0) + bit_ctr <= bit_ctr + 1; + else if(~empty) + bit_ctr <= 1; + + always @(posedge clk) + if(rst) + tx <= 1; + else + case(bit_ctr) + 0 : tx <= 1; + 1 : tx <= 0; + 2 : tx <= char_to_send[0]; + 3 : tx <= char_to_send[1]; + 4 : tx <= char_to_send[2]; + 5 : tx <= char_to_send[3]; + 6 : tx <= char_to_send[4]; + 7 : tx <= char_to_send[5]; + 8 : tx <= char_to_send[6]; + 9 : tx <= char_to_send[7]; + default : tx <= 1; + endcase // case(bit_ctr) + + assign read = (bit_ctr == 9) && (baud_ctr == clkdiv); + assign baudclk = (baud_ctr == 1); // Only for debug purposes + +endmodule // simple_uart_tx diff --git a/usrp2/control_lib/spi.v b/usrp2/control_lib/spi.v new file mode 100644 index 000000000..a80c488e9 --- /dev/null +++ b/usrp2/control_lib/spi.v @@ -0,0 +1,84 @@ + + +// AD9510 Register Map (from datasheet Rev. A) + +/* INSTRUCTION word format (16 bits) + * 15 Read = 1, Write = 0 + * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream + * 12:0 Address + */ + +/* ADDR Contents Value (hex) + * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate + * 04 A Counter + * 05-06 B Counter + * 07-0A PLL Control + * 0B-0C R Divider + * 0D PLL Control + * 34-3A Fine Delay + * 3C-3F LVPECL Outs + * 40-43 LVDS/CMOS Outs + * 45 Clock select, power down + * 48-57 Dividers + * 58 Func and Sync + * 5A Update regs + */ + + +module spi + (input reset, + input clk, + + // SPI signals + output sen, + output sclk, + input sdi, + output sdo, + + // Interfaces + input read_1, + input write_1, + input [15:0] command_1, + input [15:0] wdata_1, + output [15:0] rdata_1, + output reg done_1, + input msb_first_1, + input [5:0] command_width_1, + input [5:0] data_width_1, + input [7:0] clkdiv_1 + + ); + + reg [15:0] command, wdata, rdata; + reg done; + + always @(posedge clk) + if(reset) + done_1 <= #1 1'b0; + + always @(posedge clk) + if(reset) + begin + counter <= #1 7'd0; + command <= #1 20'd0; + end + else if(start) + begin + counter <= #1 7'd1; + command <= #1 {read,w,addr_data}; + end + else if( |counter && ~done ) + begin + counter <= #1 counter + 7'd1; + if(~counter[0]) + command <= {command[22:0],1'b0}; + end + + wire done = (counter == 8'd49); + + assign sen = (done | counter == 8'd0); // CSB is high when we're not doing anything + assign sclk = ~counter[0]; + assign sdo = command[23]; + + +endmodule // clock_control diff --git a/usrp2/control_lib/srl.v b/usrp2/control_lib/srl.v new file mode 100644 index 000000000..fa28c7669 --- /dev/null +++ b/usrp2/control_lib/srl.v @@ -0,0 +1,21 @@ + +module srl + #(parameter WIDTH=18) + (input clk, + input write, + input [WIDTH-1:0] in, + input [3:0] addr, + output [WIDTH-1:0] out); + + genvar i; + generate + for (i=0;i 5) + clock_present <= 1; + else + ; + else + if(abs_diff<3) + clock_present <= 0; + else + rd_counter <= rd_counter + 1; + +endmodule // ss_rcvr diff --git a/usrp2/control_lib/system_control.v b/usrp2/control_lib/system_control.v new file mode 100644 index 000000000..5d89f13db --- /dev/null +++ b/usrp2/control_lib/system_control.v @@ -0,0 +1,47 @@ +// System bootup order: +// 0 - Internal POR to reset this block. Maybe control it from CPLD in the future? +// 1 - Everything in reset +// 2 - Take RAM Loader out of reset +// 3 - When RAM Loader done, take processor and wishbone out of reset + +module system_control + (input wb_clk_i, + output reg ram_loader_rst_o, + output reg wb_rst_o, + input ram_loader_done_i + ); + + reg POR = 1'b1; + reg [3:0] POR_ctr; + + initial POR_ctr = 4'd0; + always @(posedge wb_clk_i) + if(POR_ctr == 4'd15) + POR <= 1'b0; + else + POR_ctr <= POR_ctr + 4'd1; + + always @(posedge POR or posedge wb_clk_i) + if(POR) + ram_loader_rst_o <= 1'b1; + else + ram_loader_rst_o <= #1 1'b0; + + // Main system reset + reg delayed_rst; + + always @(posedge POR or posedge wb_clk_i) + if(POR) + begin + wb_rst_o <= 1'b1; + delayed_rst <= 1'b1; + end + else if(ram_loader_done_i) + begin + delayed_rst <= 1'b0; + wb_rst_o <= delayed_rst; + end + +endmodule // system_control + + diff --git a/usrp2/control_lib/system_control_tb.v b/usrp2/control_lib/system_control_tb.v new file mode 100644 index 000000000..a8eff4811 --- /dev/null +++ b/usrp2/control_lib/system_control_tb.v @@ -0,0 +1,57 @@ + + +module system_control_tb(); + + reg aux_clk, clk_fpga; + wire wb_clk, dsp_clk; + wire wb_rst, dsp_rst, rl_rst, proc_rst; + + reg rl_done, clock_ready; + + initial aux_clk = 1'b0; + always #25 aux_clk = ~aux_clk; + + initial clk_fpga = 1'b0; + + initial clock_ready = 1'b0; + initial + begin + @(negedge proc_rst); + #1003 clock_ready <= 1'b1; + end + + always #7 clk_fpga = ~clk_fpga; + + initial begin + $dumpfile("system_control_tb.vcd"); + $dumpvars(0,system_control_tb); + end + + initial #10000 $finish; + + initial + begin + @(negedge rl_rst); + rl_done <= 1'b0; + #1325 rl_done <= 1'b1; + end + + initial + begin + @(negedge proc_rst); + clock_ready <= 1'b0; + #327 clock_ready <= 1'b1; + end + + system_control + system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga), + .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk), + .ram_loader_rst_o(rl_rst), + .processor_rst_o(proc_rst), + .wb_rst_o(wb_rst), + .dsp_rst_o(dsp_rst), + .ram_loader_done_i(rl_done), + .clock_ready_i(clock_ready), + .debug_o()); + +endmodule // system_control_tb diff --git a/usrp2/control_lib/traffic_cop.v b/usrp2/control_lib/traffic_cop.v new file mode 100644 index 000000000..e7579656a --- /dev/null +++ b/usrp2/control_lib/traffic_cop.v @@ -0,0 +1,25 @@ + +module traffic_cop(); + + +endmodule // traffic_cop + + + +/* + + Traffic Cop to control buffer pool + + Inputs + + Commands + + Basic Operations + + Outputs + + + + + + */ diff --git a/usrp2/control_lib/wb_1master.v b/usrp2/control_lib/wb_1master.v new file mode 100644 index 000000000..fb313efae --- /dev/null +++ b/usrp2/control_lib/wb_1master.v @@ -0,0 +1,464 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Bus Top Level //// +//// //// +//// //// +//// Original Author: Johny Chi //// +//// chisuhua@yahoo.com.cn //// +//// Modified By Matt Ettus, matt@ettus.com //// +//// //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Up to 8 slaves share a Wishbone Bus connection to 1 master + + module wb_1master + #(parameter decode_w = 8, // address decode width + parameter s0_addr = 8'h0, // slave 0 address + parameter s0_mask = 8'h0, // slave 0 don't cares + parameter s1_addr = 8'h0, // slave 1 address + parameter s1_mask = 8'h0, // slave 1 don't cares + parameter s2_addr = 8'h0, // slave 2 address + parameter s2_mask = 8'h0, // slave 2 don't cares + parameter s3_addr = 8'h0, // slave 3 address + parameter s3_mask = 8'h0, // slave 3 don't cares + parameter s4_addr = 8'h0, // slave 4 address + parameter s4_mask = 8'h0, // slave 4 don't cares + parameter s5_addr = 8'h0, // slave 5 address + parameter s5_mask = 8'h0, // slave 5 don't cares + parameter s6_addr = 8'h0, // slave 6 address + parameter s6_mask = 8'h0, // slave 6 don't cares + parameter s7_addr = 8'h0, // slave 7 address + parameter s7_mask = 8'h0, // slave 7 don't cares + parameter s8_addr = 8'h0, // slave 8 address + parameter s8_mask = 8'h0, // slave 8 don't cares + parameter s9_addr = 8'h0, // slave 9 address + parameter s9_mask = 8'h0, // slave 9 don't cares + parameter sa_addr = 8'h0, // slave a address + parameter sa_mask = 8'h0, // slave a don't cares + parameter sb_addr = 8'h0, // slave b address + parameter sb_mask = 8'h0, // slave b don't cares + parameter sc_addr = 8'h0, // slave c address + parameter sc_mask = 8'h0, // slave c don't cares + parameter sd_addr = 8'h0, // slave d address + parameter sd_mask = 8'h0, // slave d don't cares + parameter se_addr = 8'h0, // slave e address + parameter se_mask = 8'h0, // slave e don't cares + parameter sf_addr = 8'h0, // slave f address + parameter sf_mask = 8'h0, // slave f don't cares + + parameter dw = 32, // Data bus Width + parameter aw = 32, // Address bus Width + parameter sw = 4) // Number of Select Lines + + (input clk_i, + input rst_i, + + // Master Interface + input [dw-1:0] m0_dat_i, + output [dw-1:0] m0_dat_o, + input [aw-1:0] m0_adr_i, + input [sw-1:0] m0_sel_i, + input m0_we_i, + input m0_cyc_i, + input m0_stb_i, + output m0_ack_o, + output m0_err_o, + output m0_rty_o, + + // Slave Interfaces + input [dw-1:0] s0_dat_i, + output [dw-1:0] s0_dat_o, + output [aw-1:0] s0_adr_o, + output [sw-1:0] s0_sel_o, + output s0_we_o, + output s0_cyc_o, + output s0_stb_o, + input s0_ack_i, + input s0_err_i, + input s0_rty_i, + + input [dw-1:0] s1_dat_i, + output [dw-1:0] s1_dat_o, + output [aw-1:0] s1_adr_o, + output [sw-1:0] s1_sel_o, + output s1_we_o, + output s1_cyc_o, + output s1_stb_o, + input s1_ack_i, + input s1_err_i, + input s1_rty_i, + + input [dw-1:0] s2_dat_i, + output [dw-1:0] s2_dat_o, + output [aw-1:0] s2_adr_o, + output [sw-1:0] s2_sel_o, + output s2_we_o, + output s2_cyc_o, + output s2_stb_o, + input s2_ack_i, + input s2_err_i, + input s2_rty_i, + + input [dw-1:0] s3_dat_i, + output [dw-1:0] s3_dat_o, + output [aw-1:0] s3_adr_o, + output [sw-1:0] s3_sel_o, + output s3_we_o, + output s3_cyc_o, + output s3_stb_o, + input s3_ack_i, + input s3_err_i, + input s3_rty_i, + + input [dw-1:0] s4_dat_i, + output [dw-1:0] s4_dat_o, + output [aw-1:0] s4_adr_o, + output [sw-1:0] s4_sel_o, + output s4_we_o, + output s4_cyc_o, + output s4_stb_o, + input s4_ack_i, + input s4_err_i, + input s4_rty_i, + + input [dw-1:0] s5_dat_i, + output [dw-1:0] s5_dat_o, + output [aw-1:0] s5_adr_o, + output [sw-1:0] s5_sel_o, + output s5_we_o, + output s5_cyc_o, + output s5_stb_o, + input s5_ack_i, + input s5_err_i, + input s5_rty_i, + + input [dw-1:0] s6_dat_i, + output [dw-1:0] s6_dat_o, + output [aw-1:0] s6_adr_o, + output [sw-1:0] s6_sel_o, + output s6_we_o, + output s6_cyc_o, + output s6_stb_o, + input s6_ack_i, + input s6_err_i, + input s6_rty_i, + + input [dw-1:0] s7_dat_i, + output [dw-1:0] s7_dat_o, + output [aw-1:0] s7_adr_o, + output [sw-1:0] s7_sel_o, + output s7_we_o, + output s7_cyc_o, + output s7_stb_o, + input s7_ack_i, + input s7_err_i, + input s7_rty_i, + + input [dw-1:0] s8_dat_i, + output [dw-1:0] s8_dat_o, + output [aw-1:0] s8_adr_o, + output [sw-1:0] s8_sel_o, + output s8_we_o, + output s8_cyc_o, + output s8_stb_o, + input s8_ack_i, + input s8_err_i, + input s8_rty_i, + + input [dw-1:0] s9_dat_i, + output [dw-1:0] s9_dat_o, + output [aw-1:0] s9_adr_o, + output [sw-1:0] s9_sel_o, + output s9_we_o, + output s9_cyc_o, + output s9_stb_o, + input s9_ack_i, + input s9_err_i, + input s9_rty_i, + + input [dw-1:0] sa_dat_i, + output [dw-1:0] sa_dat_o, + output [aw-1:0] sa_adr_o, + output [sw-1:0] sa_sel_o, + output sa_we_o, + output sa_cyc_o, + output sa_stb_o, + input sa_ack_i, + input sa_err_i, + input sa_rty_i, + + input [dw-1:0] sb_dat_i, + output [dw-1:0] sb_dat_o, + output [aw-1:0] sb_adr_o, + output [sw-1:0] sb_sel_o, + output sb_we_o, + output sb_cyc_o, + output sb_stb_o, + input sb_ack_i, + input sb_err_i, + input sb_rty_i, + + input [dw-1:0] sc_dat_i, + output [dw-1:0] sc_dat_o, + output [aw-1:0] sc_adr_o, + output [sw-1:0] sc_sel_o, + output sc_we_o, + output sc_cyc_o, + output sc_stb_o, + input sc_ack_i, + input sc_err_i, + input sc_rty_i, + + input [dw-1:0] sd_dat_i, + output [dw-1:0] sd_dat_o, + output [aw-1:0] sd_adr_o, + output [sw-1:0] sd_sel_o, + output sd_we_o, + output sd_cyc_o, + output sd_stb_o, + input sd_ack_i, + input sd_err_i, + input sd_rty_i, + + input [dw-1:0] se_dat_i, + output [dw-1:0] se_dat_o, + output [aw-1:0] se_adr_o, + output [sw-1:0] se_sel_o, + output se_we_o, + output se_cyc_o, + output se_stb_o, + input se_ack_i, + input se_err_i, + input se_rty_i, + + input [dw-1:0] sf_dat_i, + output [dw-1:0] sf_dat_o, + output [aw-1:0] sf_adr_o, + output [sw-1:0] sf_sel_o, + output sf_we_o, + output sf_cyc_o, + output sf_stb_o, + input sf_ack_i, + input sf_err_i, + input sf_rty_i + ); + + // //////////////////////////////////////////////////////////////// + // + // Local wires + // + + wire [15:0] ssel_dec; + reg [dw-1:0] i_dat_s; // internal share bus , slave data to master + + // Master output Interface + assign m0_dat_o = i_dat_s; + + always @* + case(ssel_dec) + 1 : i_dat_s <= s0_dat_i; + 2 : i_dat_s <= s1_dat_i; + 4 : i_dat_s <= s2_dat_i; + 8 : i_dat_s <= s3_dat_i; + 16 : i_dat_s <= s4_dat_i; + 32 : i_dat_s <= s5_dat_i; + 64 : i_dat_s <= s6_dat_i; + 128 : i_dat_s <= s7_dat_i; + 256 : i_dat_s <= s8_dat_i; + 512 : i_dat_s <= s9_dat_i; + 1024 : i_dat_s <= sa_dat_i; + 2048 : i_dat_s <= sb_dat_i; + 4096 : i_dat_s <= sc_dat_i; + 8192 : i_dat_s <= sd_dat_i; + 16384 : i_dat_s <= se_dat_i; + 32768 : i_dat_s <= sf_dat_i; + default : i_dat_s <= s0_dat_i; + endcase // case(ssel_dec) + + assign {m0_ack_o, m0_err_o, m0_rty_o} + = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i | + s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i , + s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i | + s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i , + s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i | + s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i }; + + // Slave output interfaces + assign s0_adr_o = m0_adr_i; + assign s0_sel_o = m0_sel_i; + assign s0_dat_o = m0_dat_i; + assign s0_we_o = m0_we_i; + assign s0_cyc_o = m0_cyc_i; + assign s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0]; + + assign s1_adr_o = m0_adr_i; + assign s1_sel_o = m0_sel_i; + assign s1_dat_o = m0_dat_i; + assign s1_we_o = m0_we_i; + assign s1_cyc_o = m0_cyc_i; + assign s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1]; + + assign s2_adr_o = m0_adr_i; + assign s2_sel_o = m0_sel_i; + assign s2_dat_o = m0_dat_i; + assign s2_we_o = m0_we_i; + assign s2_cyc_o = m0_cyc_i; + assign s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2]; + + assign s3_adr_o = m0_adr_i; + assign s3_sel_o = m0_sel_i; + assign s3_dat_o = m0_dat_i; + assign s3_we_o = m0_we_i; + assign s3_cyc_o = m0_cyc_i; + assign s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3]; + + assign s4_adr_o = m0_adr_i; + assign s4_sel_o = m0_sel_i; + assign s4_dat_o = m0_dat_i; + assign s4_we_o = m0_we_i; + assign s4_cyc_o = m0_cyc_i; + assign s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4]; + + assign s5_adr_o = m0_adr_i; + assign s5_sel_o = m0_sel_i; + assign s5_dat_o = m0_dat_i; + assign s5_we_o = m0_we_i; + assign s5_cyc_o = m0_cyc_i; + assign s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5]; + + assign s6_adr_o = m0_adr_i; + assign s6_sel_o = m0_sel_i; + assign s6_dat_o = m0_dat_i; + assign s6_we_o = m0_we_i; + assign s6_cyc_o = m0_cyc_i; + assign s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6]; + + assign s7_adr_o = m0_adr_i; + assign s7_sel_o = m0_sel_i; + assign s7_dat_o = m0_dat_i; + assign s7_we_o = m0_we_i; + assign s7_cyc_o = m0_cyc_i; + assign s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7]; + + assign s8_adr_o = m0_adr_i; + assign s8_sel_o = m0_sel_i; + assign s8_dat_o = m0_dat_i; + assign s8_we_o = m0_we_i; + assign s8_cyc_o = m0_cyc_i; + assign s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8]; + + assign s9_adr_o = m0_adr_i; + assign s9_sel_o = m0_sel_i; + assign s9_dat_o = m0_dat_i; + assign s9_we_o = m0_we_i; + assign s9_cyc_o = m0_cyc_i; + assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9]; + + assign sa_adr_o = m0_adr_i; + assign sa_sel_o = m0_sel_i; + assign sa_dat_o = m0_dat_i; + assign sa_we_o = m0_we_i; + assign sa_cyc_o = m0_cyc_i; + assign sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10]; + + assign sb_adr_o = m0_adr_i; + assign sb_sel_o = m0_sel_i; + assign sb_dat_o = m0_dat_i; + assign sb_we_o = m0_we_i; + assign sb_cyc_o = m0_cyc_i; + assign sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11]; + + assign sc_adr_o = m0_adr_i; + assign sc_sel_o = m0_sel_i; + assign sc_dat_o = m0_dat_i; + assign sc_we_o = m0_we_i; + assign sc_cyc_o = m0_cyc_i; + assign sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12]; + + assign sd_adr_o = m0_adr_i; + assign sd_sel_o = m0_sel_i; + assign sd_dat_o = m0_dat_i; + assign sd_we_o = m0_we_i; + assign sd_cyc_o = m0_cyc_i; + assign sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13]; + + assign se_adr_o = m0_adr_i; + assign se_sel_o = m0_sel_i; + assign se_dat_o = m0_dat_i; + assign se_we_o = m0_we_i; + assign se_cyc_o = m0_cyc_i; + assign se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14]; + + assign sf_adr_o = m0_adr_i; + assign sf_sel_o = m0_sel_i; + assign sf_dat_o = m0_dat_i; + assign sf_we_o = m0_we_i; + assign sf_cyc_o = m0_cyc_i; + assign sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15]; + + // Address decode logic + // WARNING -- must make sure these are mutually exclusive! + + + assign ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask); + assign ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask); + assign ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask); + assign ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask); + assign ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask); + assign ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask); + assign ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask); + assign ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask); + assign ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask); + assign ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask); + assign ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask); + assign ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask); + assign ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask); + assign ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask); + assign ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask); + assign ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask); + +/* + assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr); + assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr); + assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr); + assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr); + assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr); + assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr); + assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr); + assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr); + assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr); + assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr); + assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr); + assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr); + assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr); + assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr); + assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr); + assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr); + */ +endmodule // wb_1master diff --git a/usrp2/control_lib/wb_bridge_16_32.v b/usrp2/control_lib/wb_bridge_16_32.v new file mode 100644 index 000000000..405e25c3c --- /dev/null +++ b/usrp2/control_lib/wb_bridge_16_32.v @@ -0,0 +1,36 @@ + + +module wb_bridge_16_32 + #(parameter AWIDTH=16) + (input wb_clk, input wb_rst, + input A_cyc_i, input A_stb_i, input A_we_i, input [3:0] A_sel_i, + input [AWIDTH-1:0] A_adr_i, input [31:0] A_dat_i, output [31:0] A_dat_o, output A_ack_o, + output B_cyc_o, output B_stb_o, output B_we_o, output [1:0] B_sel_o, + output [AWIDTH-1:0] B_adr_o, output [15:0] B_dat_o, input [15:0] B_dat_i, input B_ack_i + ); + + reg [15:0] holding; + reg phase; + + assign B_adr_o = {A_adr_i[AWIDTH-1:2],phase,1'b0}; + assign B_cyc_o = A_cyc_i; + assign B_stb_o = A_stb_i; + assign B_we_o = A_we_i; + + assign B_dat_o = ~phase ? A_dat_i[15:0] : A_dat_i[31:16]; + assign B_sel_o = ~phase ? A_sel_i[1:0] : A_sel_i[3:2]; + + assign A_dat_o = {B_dat_i,holding}; + assign A_ack_o = phase & B_ack_i; + + always @(posedge wb_clk) + if(wb_rst) + phase <= 0; + else if(B_ack_i) + phase <= ~phase; + + always @(posedge wb_clk) + if(~phase & B_ack_i) + holding <= B_dat_i; + +endmodule // wb_bridge_16_32 diff --git a/usrp2/control_lib/wb_bus_writer.v b/usrp2/control_lib/wb_bus_writer.v new file mode 100644 index 000000000..fc148a0ff --- /dev/null +++ b/usrp2/control_lib/wb_bus_writer.v @@ -0,0 +1,57 @@ + +// wb_bus_writer +// +// WB Bus Master device to send a sequence of single-word transactions +// based on a list in a RAM or ROM (FASM interface) +// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]} +// continues until it gets an all-1s entry + +module wb_bus_writer (input start, + output done, + output reg [15:0] rom_addr, + input [47:0] rom_data, + // WB Master Interface, don't need wb_dat_i + input wb_clk_i, + input wb_rst_i, + output [31:0] wb_dat_o, + input wb_ack_i, + output [15:0] wb_adr_o, + output wb_cyc_o, + output [3:0] wb_sel_o, + output wb_stb_o, + output wb_we_o + ); + +`define IDLE 0 +`define READ 1 + + reg [3:0] state; + + assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s + + always @(posedge wb_clk_i) + if(wb_rst_i) + begin + rom_addr <= #1 0; + state <= #1 0; + end + else if(start) + begin + rom_addr <= #1 0; + state <= #1 `READ; + end + else if((state == `READ) && wb_ack_i) + if(done) + state <= #1 `IDLE; + else + rom_addr <= #1 rom_addr + 1; + + assign wb_dat_o = rom_data[31:0]; + assign wb_adr_o = rom_data[47:32]; + assign wb_sel_o = 4'b1111; // All writes are the full 32 bits + + assign wb_cyc_o = !done & (state != `IDLE); + assign wb_stb_o = !done & (state != `IDLE); + assign wb_we_o = !done & (state != `IDLE); + +endmodule // wb_bus_writer diff --git a/usrp2/control_lib/wb_output_pins32.v b/usrp2/control_lib/wb_output_pins32.v new file mode 100644 index 000000000..1517f2066 --- /dev/null +++ b/usrp2/control_lib/wb_output_pins32.v @@ -0,0 +1,49 @@ + + +// Simple 32-bit Wishbone compatible slave output port +// with 8-bit granularity, modeled after the one in the spec +// Allows for readback +// Assumes a 32-bit wishbone bus +// Lowest order bits get sel[0] +// + +module wb_output_pins32 + (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o, + wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i, + port_output); + + input wb_rst_i; + input wb_clk_i; + input wire [31:0] wb_dat_i; + output wire [31:0] wb_dat_o; + input wb_we_i; + input wire [3:0] wb_sel_i; + input wb_stb_i; + output wb_ack_o; + input wb_cyc_i; + + output wire [31:0] port_output; + + reg [31:0] internal_reg; + + always @(posedge wb_clk_i) + if(wb_rst_i) + internal_reg <= #1 32'b0; + else + begin + if(wb_stb_i & wb_we_i & wb_sel_i[0]) + internal_reg[7:0] <= #1 wb_dat_i[7:0]; + if(wb_stb_i & wb_we_i & wb_sel_i[1]) + internal_reg[15:8] <= #1 wb_dat_i[15:8]; + if(wb_stb_i & wb_we_i & wb_sel_i[2]) + internal_reg[23:16] <= #1 wb_dat_i[23:16]; + if(wb_stb_i & wb_we_i & wb_sel_i[3]) + internal_reg[31:24] <= #1 wb_dat_i[31:24]; + end // else: !if(wb_rst_i) + + assign wb_dat_o = internal_reg; + assign port_output = internal_reg; + assign wb_ack_o = wb_stb_i; + +endmodule // wb_output_pins32 + diff --git a/usrp2/control_lib/wb_ram_block.v b/usrp2/control_lib/wb_ram_block.v new file mode 100644 index 000000000..044d34ca4 --- /dev/null +++ b/usrp2/control_lib/wb_ram_block.v @@ -0,0 +1,36 @@ + + +// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency +// These have to be a multiple of 512 lines (2K) long + +module wb_ram_block + #(parameter AWIDTH=9) + (input clk_i, + input stb_i, + input we_i, + input [AWIDTH-1:0] adr_i, + input [31:0] dat_i, + output reg [31:0] dat_o, + output ack_o); + + reg [31:0] distram [0:1<<(AWIDTH-1)]; + + always @(posedge clk_i) + begin + if(stb_i & we_i) + distram[adr_i] <= dat_i; + dat_o <= distram[adr_i]; + end + + reg stb_d1, ack_d1; + always @(posedge clk_i) + stb_d1 <= stb_i; + + always @(posedge clk_i) + ack_d1 <= ack_o; + + assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1)); +endmodule // wb_ram_block + + + diff --git a/usrp2/control_lib/wb_ram_dist.v b/usrp2/control_lib/wb_ram_dist.v new file mode 100644 index 000000000..cffc2f423 --- /dev/null +++ b/usrp2/control_lib/wb_ram_dist.v @@ -0,0 +1,33 @@ + + +module wb_ram_dist + #(parameter AWIDTH=8) + (input clk_i, + input stb_i, + input we_i, + input [AWIDTH-1:0] adr_i, + input [31:0] dat_i, + input [3:0] sel_i, + output [31:0] dat_o, + output ack_o); + + reg [31:0] distram [0:1<<(AWIDTH-1)]; + + always @(posedge clk_i) + begin + if(stb_i & we_i & sel_i[3]) + distram[adr_i][31:24] <= dat_i[31:24]; + if(stb_i & we_i & sel_i[2]) + distram[adr_i][24:16] <= dat_i[24:16]; + if(stb_i & we_i & sel_i[1]) + distram[adr_i][15:8] <= dat_i[15:8]; + if(stb_i & we_i & sel_i[0]) + distram[adr_i][7:0] <= dat_i[7:0]; + end // always @ (posedge clk_i) + + assign dat_o = distram[adr_i]; + assign ack_o = stb_i; + +endmodule // wb_ram_dist + + diff --git a/usrp2/control_lib/wb_readback_mux.v b/usrp2/control_lib/wb_readback_mux.v new file mode 100644 index 000000000..3922b03e3 --- /dev/null +++ b/usrp2/control_lib/wb_readback_mux.v @@ -0,0 +1,60 @@ + + +// Note -- clocks must be synchronous (derived from the same source) +// Assumes alt_clk is running at a multiple of wb_clk + +module wb_readback_mux + (input wb_clk_i, + input wb_rst_i, + input wb_stb_i, + input [15:0] wb_adr_i, + output reg [31:0] wb_dat_o, + output reg wb_ack_o, + + input [31:0] word00, + input [31:0] word01, + input [31:0] word02, + input [31:0] word03, + input [31:0] word04, + input [31:0] word05, + input [31:0] word06, + input [31:0] word07, + input [31:0] word08, + input [31:0] word09, + input [31:0] word10, + input [31:0] word11, + input [31:0] word12, + input [31:0] word13, + input [31:0] word14, + input [31:0] word15 + ); + + always @(posedge wb_clk_i) + if(wb_rst_i) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + always @(posedge wb_clk_i) + case(wb_adr_i[5:2]) + 0 : wb_dat_o <= word00; + 1 : wb_dat_o <= word01; + 2 : wb_dat_o <= word02; + 3 : wb_dat_o <= word03; + 4 : wb_dat_o <= word04; + 5 : wb_dat_o <= word05; + 6 : wb_dat_o <= word06; + 7 : wb_dat_o <= word07; + 8 : wb_dat_o <= word08; + 9 : wb_dat_o <= word09; + 10: wb_dat_o <= word10; + 11: wb_dat_o <= word11; + 12: wb_dat_o <= word12; + 13: wb_dat_o <= word13; + 14: wb_dat_o <= word14; + 15: wb_dat_o <= word15; + endcase // case(addr_reg[3:0]) + +endmodule // wb_readback_mux + + diff --git a/usrp2/control_lib/wb_regfile_2clock.v b/usrp2/control_lib/wb_regfile_2clock.v new file mode 100644 index 000000000..e248e5161 --- /dev/null +++ b/usrp2/control_lib/wb_regfile_2clock.v @@ -0,0 +1,107 @@ + +module wb_regfile_2clock + (input wb_clk_i, + input wb_rst_i, + input wb_stb_i, + input wb_we_i, + input [15:0] wb_adr_i, + input [3:0] wb_sel_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output wb_ack_o, + input alt_clk, + input alt_rst, + + output reg [31:0] reg00, + output reg [31:0] reg01, + output reg [31:0] reg02, + output reg [31:0] reg03, + output reg [31:0] reg04, + output reg [31:0] reg05, + output reg [31:0] reg06, + output reg [31:0] reg07 + ); + + reg [15:0] addr_reg; + reg [3:0] sel_reg; + reg [31:0] dat_reg; + reg wr_ret1, wr_ret2, we_reg, stb_reg; + + always @(posedge wb_clk_i) + if(wb_rst_i) + begin + addr_reg <= 0; + sel_reg <= 0; + dat_reg <= 0; + end + else if(wb_stb_i & wb_we_i) + begin + addr_reg <= wb_adr_i; + sel_reg <= wb_sel_i; + dat_reg <= wb_dat_i; + end + + always @(posedge wb_clk_i) + if(wb_rst_i) + {we_reg,stb_reg} <= 2'b0; + else + {we_reg,stb_reg} <= {wb_we_i,wb_stb_i}; + + assign wb_ack_o = stb_reg; + + always @(posedge alt_clk) + if(alt_rst) + {wr_ret2, wr_ret1} <= 2'b0; + else + {wr_ret2, wr_ret1} <= {wr_ret1, we_reg & stb_reg}; + + always @(posedge alt_clk) + if(alt_rst) + begin + reg00 <= 0; + reg01 <= 0; + reg02 <= 0; + reg03 <= 0; + reg04 <= 0; + reg05 <= 0; + reg06 <= 0; + reg07 <= 0; + end // if (alt_rst) + else if(wr_ret2) + case(addr_reg[4:2]) + 3'd0: reg00 <= { {sel_reg[3] ? dat_reg[31:24] : reg00[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg00[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg00[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg00[7:0]}}; + 3'd1: reg01 <= { {sel_reg[3] ? dat_reg[31:24] : reg01[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg01[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg01[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg01[7:0]}}; + 3'd2: reg02 <= { {sel_reg[3] ? dat_reg[31:24] : reg02[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg02[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg02[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg02[7:0]}}; + 3'd3: reg03 <= { {sel_reg[3] ? dat_reg[31:24] : reg03[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg03[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg03[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg03[7:0]}}; + 3'd4: reg04 <= { {sel_reg[3] ? dat_reg[31:24] : reg04[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg04[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg04[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg04[7:0]}}; + 3'd5: reg05 <= { {sel_reg[3] ? dat_reg[31:24] : reg05[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg05[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg05[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg05[7:0]}}; + 3'd6: reg06 <= { {sel_reg[3] ? dat_reg[31:24] : reg06[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg06[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg06[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg06[7:0]}}; + 3'd7: reg07 <= { {sel_reg[3] ? dat_reg[31:24] : reg07[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg07[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg07[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg07[7:0]}}; + endcase // case(addr_reg[2:0]) + +endmodule // wb_regfile_2clock + diff --git a/usrp2/control_lib/wb_semaphore.v b/usrp2/control_lib/wb_semaphore.v new file mode 100644 index 000000000..a9208e6a1 --- /dev/null +++ b/usrp2/control_lib/wb_semaphore.v @@ -0,0 +1,42 @@ + +// up to 8 semaphores + +// After a read operation, the semaphore is always locked +// If it was already locked before the read (meaning someone else holds the lock) +// then a 1 is returned +// If it was not already locked (meaning the reader now holds the lock) +// then a 0 is returned + +// A write operation clears the lock + +module wb_semaphore + #(parameter count=8, DBUS_WIDTH=32) + (input wb_clk_i, + input wb_rst_i, + input [DBUS_WIDTH-1:0] wb_dat_i, + input [2:0] wb_adr_i, + input wb_cyc_i, + input wb_stb_i, + input wb_we_i, + output wb_ack_o, + output [DBUS_WIDTH-1:0] wb_dat_o); + + reg [count-1:0] locked; + + always @(posedge clock) + if(wb_rst_i) + locked <= {count{1'b0}}; + else if(wb_stb_i) + if(wb_we_i) + locked[adr_i] <= 1'b0; + else + locked[adr_i] <= 1'b1; + + assign wb_dat_o[DBUS_WIDTH-1:1] = {(DBUS_WIDTH-1){1'b0}}; + assign wb_dat_o[0] = locked[adr_i]; + assign wb_ack_o = wb_stb_i; + + +endmodule // wb_semaphore + + diff --git a/usrp2/control_lib/wb_sim.v b/usrp2/control_lib/wb_sim.v new file mode 100644 index 000000000..b324e1457 --- /dev/null +++ b/usrp2/control_lib/wb_sim.v @@ -0,0 +1,79 @@ + + +module wb_sim(); + + wire wb_clk, wb_rst; + wire start; + + reg POR, aux_clk, clk_fpga; + + initial POR = 1'b1; + initial #103 POR = 1'b0; + + initial aux_clk = 1'b0; + always #25 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #7 clk_fpga = ~clk_fpga; + + initial begin + $dumpfile("wb_sim.vcd"); + $dumpvars(0,wb_sim); + end + + initial #10000 $finish; + + wire [15:0] rom_addr; + wire [47:0] rom_data; + wire [31:0] wb_dat; + wire [15:0] wb_adr; + wire wb_cyc,wb_stb,wb_we,wb_ack; + wire [3:0] wb_sel; + + wire [31:0] port_output; + + + system_control system_control(.dsp_clk(dsp_clk), + .reset_out(reset_out), + .wb_clk_o(wb_clk), + .wb_rst_o(wb_rst), + .wb_rst_o_alt(wb_rst_o_alt), + .start (start), + .aux_clk(aux_clk), + .clk_fpga(clk_fpga), + .POR (POR), + .done (done)); + + clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data)); + + wb_bus_writer bus_writer(.rom_addr (rom_addr[15:0]), + .wb_dat_o (wb_dat[31:0]), + .wb_adr_o (wb_adr[15:0]), + .wb_cyc_o (wb_cyc), + .wb_sel_o (wb_sel[3:0]), + .wb_stb_o (wb_stb), + .wb_we_o (wb_we), + .start (start), + .done (done), + .rom_data (rom_data[47:0]), + .wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .wb_ack_i (wb_ack)); + + wb_output_pins32 output_pins(.wb_dat_o(), + .wb_ack_o(wb_ack), + .port_output(port_output[31:0]), + .wb_rst_i(wb_rst), + .wb_clk_i(wb_clk), + .wb_dat_i(wb_dat[31:0]), + .wb_we_i(wb_we), + .wb_sel_i(wb_sel[3:0]), + .wb_stb_i(wb_stb), + .wb_cyc_i(wb_cyc)); + + + + +endmodule // wb_sim + diff --git a/usrp2/coregen/.gitignore b/usrp2/coregen/.gitignore new file mode 100644 index 000000000..956cab52b --- /dev/null +++ b/usrp2/coregen/.gitignore @@ -0,0 +1,3 @@ +/xlnx_auto* +/*log +/tmp diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp new file mode 100644 index 000000000..810d64dac --- /dev/null +++ b/usrp2/coregen/coregen.cgp @@ -0,0 +1,20 @@ +# Date: Thu Sep 3 17:40:48 2009 +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +SET workingdirectory = /home/matt/coregen/tmp + diff --git a/usrp2/coregen/fifo_generator_release_notes.txt b/usrp2/coregen/fifo_generator_release_notes.txt new file mode 100644 index 000000000..554ec87f4 --- /dev/null +++ b/usrp2/coregen/fifo_generator_release_notes.txt @@ -0,0 +1,160 @@ +COPYRIGHT (c) 2006, 2007 XILINX, INC. +ALL RIGHTS RESERVED + +Core name : FIFO Generator +Version : v4.1 +Release Date : August 8, 2007 +File : fifo_generator_release_notes.txt + +Revision History +Date By Version Change Description +======================================================================== +09/2006 Xilinx, Inc. 3.2 Initial creation. +02/2007 Xilinx, Inc. 3.3 Revised for v3.3. +02/2007 Xilinx, Inc. 3.3 Revised for v3.3 rev 1. +08/2007 Xilinx, Inc. 3.4 Revised for v4.1. +======================================================================== + +INTRODUCTION +RELEASE NOTES + 1. General Core Design + 1.1 Enhancements + 1.2 Resolved Issues + 1.3 Outstanding Issues + 2. General Simulation + 2.1 Enhancements + 2.2 Resolved Issues + 2.3 Outstanding Issues + 3. Documentation + 3.1 Enhancements + 3.2 Resolved Issues + 3.3 Outstanding Issues +OTHER GENERAL INFORMATION +TECHNICAL SUPPORT + +======================================================================== + +INTRODUCTION +============ +Thank you using the FIFO Generator core from Xilinx! +In order to obtain the latest core updates and documentation, +please visit the Intellectual Property page located at: +http://www.xilinx.com/ipcenter/index.htm +This document contains the release notes for FIFO Generator v4.1 +which includes enhancements, resolved issues and outstanding known +issues. For release notes and known issues for CORE Generator 9.2i IP +Update 1 and FIFO Generator v4.1 please see Answer Record 25222. + +RELEASE NOTES +============= +This section lists any enhancements, resolved issues and outstanding +known issues. + + +1. General Core Design + 1.1 Enhancements + 1.1.1 Error Correction Checking (ECC) feature support for + Virtex-5 block RAM FIFO configurations + + 1.1.2 Full range data count widths now supported for non-symmetric + aspect ratio configurations + + 1.1.3 Option to define asynchronous reset value for full condition + flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM, + distributed RAM and shift RAM-based FIFO configurations only + + 1.1.4 Support added for use embedded output registers in block RAM + FIFO configurations (Virtex-4 and Virtex-5 only) + + 1.2 Resolved Issues + 1.2.1 Coregen GUI - For built-in FIFOs, GUI reports incorrect + number of built-in FIFO primitives used. + Change request: 4433738 + + 1.2.2 Programmable full flag is always asserted even when FIFO is + empty due to incorrect threshold setting. + Change request: 435835 + + 1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol + .. , these pins should be connected to the same signal" occur + during MAP when targeting Virtex-4 and Virtex-5. + Change request: 338260 + + 1.2.4 Write Data Count and Read Data Count overestimate the number + of words written or read when core is configured with this + combination of options: First-Word-Fall-Through(FWFT), + accurate data count using extra logic, non-symmetric port + aspect ratio. + Change request: 436886 + + 1.2.5 SBITERR and DBITERR outputs are not driven in behavior + models. + Change request: 433637 + + 1.2.6 Maximum programmable empty threshold negate value is + incorrect. + Change request: 433921 + + 1.2.7 Programmable full flag behavior is incorrect when the + core is configured with this combination of options: + FWFT, non-symmetric port aspect ratio, single or + multiple programmable full threshold input port. + Change request: 435874 + + 1.2.8 Programmable empty flag stuck high when the core is + configured with this combination of options: block or + distributed RAM FIFO, single or multiple programmable + empty threshold input port. + Change request: 443569 + + 1.3 Outstanding Issues + 1.3.1 "WARNING:Ngdbuild:452 - logical net + 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during + NgdBuild although programmable empty or full is not selected. + Warnings can be safely ignored. + Change request: 431975 + +2. General Simulation + 2.1 Enhancements + None at this time. + + 2.2 Resolved Issues + None at this time. + + 2.3 Outstanding Issues + 2.3.1 Ncelab warnings during Verilog structural and timing simulations + in ncsim for Virtex5 Block RAM FIFOs. + The simulations will be successful, but there will be warnings + similar to the following in the log file: "memory index out of + declared bounds" in simprims_ver_virtex5_source.v or + unisims_ver_virtex5_source.v. Cadence does not want to fix this + issue. These warning messages can safely be ignored. + Change request: 423374, 423375 + +3. Documentation + 3.1 Enhancements + 3.1.1 Added clarification on FIFO flag latency. + + 3.1.1 Added clarification on actual FIFO depth. + + 3.2 Resolved Issues + None at this time. + + 3.3 Outstanding Issues + None at this time. + + +TECHNICAL SUPPORT +================= +The fastest method for obtaining specific technical support for the +FIFO Generator core is through the http://support.xilinx.com/ +website. Questions are routed to a team of engineers with specific +expertise in using the FIFO Generator core. Xilinx will provide +technical support for use of this product as described in the FIFO +Generator Datasheet. Xilinx cannot guarantee timing, functionality, +or support of this product for designs that do not follow these +guidelines. + + + + diff --git a/usrp2/coregen/fifo_generator_ug175.pdf b/usrp2/coregen/fifo_generator_ug175.pdf new file mode 100644 index 000000000..2c3e3c200 Binary files /dev/null and b/usrp2/coregen/fifo_generator_ug175.pdf differ diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc b/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc new file mode 100644 index 000000000..b12d34d7c --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$3f24g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk.v b/usrp2/coregen/fifo_xlnx_16x19_2clk.v new file mode 100644 index 000000000..1d633384b --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk.v @@ -0,0 +1,169 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating +// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_16x19_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [18 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [18 : 0] dout; +output empty; +output full; +output [4 : 0] rd_data_count; +output [4 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(5), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(19), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(19), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(15), + .C_PROG_FULL_THRESH_NEGATE_VAL(14), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(5), + .C_RD_DEPTH(16), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(4), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(5), + .C_WR_DEPTH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(4), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk.veo b/usrp2/coregen/fifo_xlnx_16x19_2clk.veo new file mode 100644 index 000000000..2e9af1efa --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_16x19_2clk YourInstanceName ( + .din(din), // Bus [18 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [18 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [4 : 0] + .wr_data_count(wr_data_count)); // Bus [4 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating +// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk.xco b/usrp2/coregen/fifo_xlnx_16x19_2clk.xco new file mode 100644 index 000000000..d0f638026 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Fri Sep 11 04:33:27 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_16x19_2clk +CSET data_count=false +CSET data_count_width=5 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=15 +CSET full_threshold_negate_value=14 +CSET input_data_width=19 +CSET input_depth=16 +CSET output_data_width=19 +CSET output_depth=16 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=5 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=5 +# END Parameters +GENERATE +# CRC: 60b85dda + diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..ef33fff67 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,103 @@ + + + + + + +
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+ + + diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt new file mode 100644 index 000000000..5e1a6ed35 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_16x19_2clk.ngc +fifo_xlnx_16x19_2clk.v +fifo_xlnx_16x19_2clk.veo +fifo_xlnx_16x19_2clk.xco +fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_16x19_2clk_flist.txt +fifo_xlnx_16x19_2clk_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt new file mode 100644 index 000000000..1b5976555 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_16x19_2clk' in directory +/home/matt/gnuradio.git/usrp2/fpga/coregen/: + +fifo_xlnx_16x19_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_16x19_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_16x19_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_16x19_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_16x19_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_16x19_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_16x19_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl new file mode 100644 index 000000000..8d633e9c2 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_16x19_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_16x19_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x19_2clk +} +# ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x19_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy new file mode 100644 index 000000000..a87aa2f84 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_xlnx_2Kx36_2clk +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 704 144 672 +PIN 144 704 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[11:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[11:0] +PINATTR Polarity OUT + diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc new file mode 100644 index 000000000..684eb74f4 --- /dev/null +++ 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym new file mode 100644 index 000000000..5d56b5c98 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym @@ -0,0 +1,74 @@ +VERSION 5 +BEGIN SYMBOL fifo_xlnx_2Kx36_2clk +SYMBOLTYPE BLOCK +TIMESTAMP 2009 9 3 17 25 13 +SYMPIN 0 80 Input din[35:0] +SYMPIN 0 144 Input wr_en +SYMPIN 0 176 Input wr_clk +SYMPIN 0 240 Input rd_en +SYMPIN 0 272 Input rd_clk +SYMPIN 144 704 Input rst +SYMPIN 576 80 Output dout[35:0] +SYMPIN 576 208 Output full +SYMPIN 576 368 Output wr_data_count[11:0] +SYMPIN 576 432 Output empty +SYMPIN 576 592 Output rd_data_count[11:0] +BEGIN DISPLAY 32 32 TEXT fifo_xlnx_2Kx36_2clk + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 672 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 176 32 176 +BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 144 704 144 672 +BEGIN DISPLAY 144 668 PIN rst ATTR PinName + ALIGNMENT BCENTER + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 208 544 208 +BEGIN DISPLAY 540 208 PIN full ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 368 544 368 +END LINE +BEGIN DISPLAY 540 368 PIN wr_data_count[11:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 432 544 432 +BEGIN DISPLAY 540 432 PIN empty ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 592 544 592 +END LINE +BEGIN DISPLAY 540 592 PIN rd_data_count[11:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v new file mode 100644 index 000000000..0762b3ae9 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating +// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_2Kx36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [11 : 0] rd_data_count; +output [11 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(12), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("2kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(2047), + .C_PROG_FULL_THRESH_NEGATE_VAL(2046), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(12), + .C_RD_DEPTH(2048), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(11), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(12), + .C_WR_DEPTH(2048), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(11), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box" + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo new file mode 100644 index 000000000..af9191555 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_2Kx36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [11 : 0] + .wr_data_count(wr_data_count)); // Bus [11 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating +// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd new file mode 100644 index 000000000..53033dc97 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating +-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_xlnx_2Kx36_2clk IS + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(11 downto 0); + wr_data_count: OUT std_logic_VECTOR(11 downto 0)); +END fifo_xlnx_2Kx36_2clk; + +ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS +-- synthesis translate_off +component wrapped_fifo_xlnx_2Kx36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(11 downto 0); + wr_data_count: OUT std_logic_VECTOR(11 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 36, + c_has_wr_data_count => 1, + c_full_flags_rst_val => 1, + c_implementation_type => 2, + c_family => "spartan3", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 1, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 0, + c_dout_width => 36, + c_msgon_val => 1, + c_rd_depth => 2048, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 12, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 11, + c_use_fwft_data_count => 1, + c_has_almost_empty => 0, + c_rd_data_count_width => 12, + c_enable_rlocs => 0, + c_wr_pntr_width => 11, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 12, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 2046, + c_wr_depth => 2048, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 2047, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "2kx18", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_xlnx_2Kx36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END fifo_xlnx_2Kx36_2clk_a; + diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho new file mode 100644 index 000000000..5165b0bc4 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_2Kx36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(11 downto 0); + wr_data_count: OUT std_logic_VECTOR(11 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_2Kx36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_2Kx36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating +-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco new file mode 100644 index 000000000..e25ad38da --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Sep 3 17:25:43 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_2Kx36_2clk +CSET data_count=false +CSET data_count_width=12 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=2047 +CSET full_threshold_negate_value=2046 +CSET input_data_width=36 +CSET input_depth=2048 +CSET output_data_width=36 +CSET output_depth=2048 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=12 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=12 +# END Parameters +GENERATE +# CRC: 2ae9f6ef + diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..5108be2c5 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,106 @@ + + + + + + +
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+ + + diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt new file mode 100644 index 000000000..670d84713 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +fifo_xlnx_2Kx36_2clk.asy +fifo_xlnx_2Kx36_2clk.ngc +fifo_xlnx_2Kx36_2clk.sym +fifo_xlnx_2Kx36_2clk.v +fifo_xlnx_2Kx36_2clk.veo +fifo_xlnx_2Kx36_2clk.vhd +fifo_xlnx_2Kx36_2clk.vho +fifo_xlnx_2Kx36_2clk.xco +fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_2Kx36_2clk_flist.txt +fifo_xlnx_2Kx36_2clk_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt new file mode 100644 index 000000000..1879503a9 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt @@ -0,0 +1,55 @@ +The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory +/home/matt/gnuradio.git/usrp2/fpga/coregen/: + +fifo_xlnx_2Kx36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_xlnx_2Kx36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_2Kx36_2clk.sym: + Please see the core data sheet. + +fifo_xlnx_2Kx36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_2Kx36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_2Kx36_2clk.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +fifo_xlnx_2Kx36_2clk.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +fifo_xlnx_2Kx36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_2Kx36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_2Kx36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_2Kx36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl new file mode 100644 index 000000000..cac25efd2 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl @@ -0,0 +1,84 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_2Kx36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_2Kx36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_2Kx36_2clk +} +# ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_2Kx36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk.asy b/usrp2/coregen/fifo_xlnx_512x36_2clk.asy new file mode 100644 index 000000000..ecc80b648 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 704 144 672 +PIN 144 704 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[8:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[8:0] +PINATTR Polarity OUT + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc new file mode 100644 index 000000000..55486485a --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$4g64g<,[o}e~g`n;"2*413&;$>"9 > %17?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk.sym b/usrp2/coregen/fifo_xlnx_512x36_2clk.sym new file mode 100644 index 000000000..13e8af33d --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.sym @@ -0,0 +1,74 @@ +VERSION 5 +BEGIN SYMBOL fifo_xlnx_512x36_2clk +SYMBOLTYPE BLOCK +TIMESTAMP 2008 7 28 22 45 53 +SYMPIN 0 80 Input din[35:0] +SYMPIN 0 144 Input wr_en +SYMPIN 0 176 Input wr_clk +SYMPIN 0 240 Input rd_en +SYMPIN 0 272 Input rd_clk +SYMPIN 144 704 Input rst +SYMPIN 576 80 Output dout[35:0] +SYMPIN 576 208 Output full +SYMPIN 576 368 Output wr_data_count[8:0] +SYMPIN 576 432 Output empty +SYMPIN 576 592 Output rd_data_count[8:0] +BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 672 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 176 32 176 +BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 144 704 144 672 +BEGIN DISPLAY 144 668 PIN rst ATTR PinName + ALIGNMENT BCENTER + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 208 544 208 +BEGIN DISPLAY 540 208 PIN full ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 368 544 368 +END LINE +BEGIN DISPLAY 540 368 PIN wr_data_count[8:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 432 544 432 +BEGIN DISPLAY 540 432 PIN empty ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 592 544 592 +END LINE +BEGIN DISPLAY 540 592 PIN rd_data_count[8:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk.v b/usrp2/coregen/fifo_xlnx_512x36_2clk.v new file mode 100644 index 000000000..905069743 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.v @@ -0,0 +1,169 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating +// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [9 : 0] rd_data_count; +output [9 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(10), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(511), + .C_PROG_FULL_THRESH_NEGATE_VAL(510), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk.veo new file mode 100644 index 000000000..6699ee73b --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [9 : 0] + .wr_data_count(wr_data_count)); // Bus [9 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating +// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd b/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd new file mode 100644 index 000000000..d9c2dd307 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_xlnx_512x36_2clk IS + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +END fifo_xlnx_512x36_2clk; + +ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS +-- synthesis translate_off +component wrapped_fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 36, + c_has_wr_data_count => 1, + c_full_flags_rst_val => 1, + c_implementation_type => 2, + c_family => "spartan3", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 0, + c_dout_width => 36, + c_msgon_val => 1, + c_rd_depth => 512, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 9, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 9, + c_use_fwft_data_count => 0, + c_has_almost_empty => 0, + c_rd_data_count_width => 9, + c_enable_rlocs => 0, + c_wr_pntr_width => 9, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 9, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 510, + c_wr_depth => 512, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 511, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "512x36", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END fifo_xlnx_512x36_2clk_a; + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk.vho b/usrp2/coregen/fifo_xlnx_512x36_2clk.vho new file mode 100644 index 000000000..70eac27a5 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk.xco new file mode 100644 index 000000000..5934ef285 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Sep 3 17:24:24 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_negate_value=510 +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=10 +# END Parameters +GENERATE +# CRC: b7f2a9ba + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..d110a0158 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,109 @@ + + + + + + +
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+ + + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt new file mode 100644 index 000000000..b0975be2d --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_512x36_2clk.ngc +fifo_xlnx_512x36_2clk.v +fifo_xlnx_512x36_2clk.veo +fifo_xlnx_512x36_2clk.xco +fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_flist.txt +fifo_xlnx_512x36_2clk_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt new file mode 100644 index 000000000..a250a74f5 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk' in directory +/home/matt/gnuradio.git/usrp2/fpga/coregen/: + +fifo_xlnx_512x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_512x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl new file mode 100644 index 000000000..8a0c0e3ff --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk +} +# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc b/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc new file mode 100644 index 000000000..e8c55a1af --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$4;14g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk.v b/usrp2/coregen/fifo_xlnx_64x36_2clk.v new file mode 100644 index 000000000..e84237689 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk.v @@ -0,0 +1,169 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating +// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_64x36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [6 : 0] rd_data_count; +output [6 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(7), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(63), + .C_PROG_FULL_THRESH_NEGATE_VAL(62), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(7), + .C_RD_DEPTH(64), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(6), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(7), + .C_WR_DEPTH(64), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(6), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk.veo b/usrp2/coregen/fifo_xlnx_64x36_2clk.veo new file mode 100644 index 000000000..9c761370c --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_64x36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [6 : 0] + .wr_data_count(wr_data_count)); // Bus [6 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating +// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk.xco b/usrp2/coregen/fifo_xlnx_64x36_2clk.xco new file mode 100644 index 000000000..c6e9aae27 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Thu Sep 3 17:22:56 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_64x36_2clk +CSET data_count=false +CSET data_count_width=7 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=63 +CSET full_threshold_negate_value=62 +CSET input_data_width=36 +CSET input_depth=64 +CSET output_data_width=36 +CSET output_depth=64 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=7 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=7 +# END Parameters +GENERATE +# CRC: 2bb925ae + diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..a23402f56 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,104 @@ + + + + + + +
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+ + + diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt new file mode 100644 index 000000000..44e31eb6c --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +fifo_xlnx_64x36_2clk.ngc +fifo_xlnx_64x36_2clk.v +fifo_xlnx_64x36_2clk.veo +fifo_xlnx_64x36_2clk.xco +fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_64x36_2clk_flist.txt +fifo_xlnx_64x36_2clk_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt new file mode 100644 index 000000000..7734c0087 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'fifo_xlnx_64x36_2clk' in directory +/home/matt/gnuradio.git/usrp2/fpga/coregen/: + +fifo_xlnx_64x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_64x36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_64x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_64x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_64x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_64x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_64x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl new file mode 100644 index 000000000..ff5dfd3c2 --- /dev/null +++ b/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_64x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_64x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_64x36_2clk +} +# ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_64x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/extram/.gitignore b/usrp2/extram/.gitignore new file mode 100644 index 000000000..7fc71ccb6 --- /dev/null +++ b/usrp2/extram/.gitignore @@ -0,0 +1 @@ +/a.out diff --git a/usrp2/extram/extram_interface.v b/usrp2/extram/extram_interface.v new file mode 100644 index 000000000..7554592ba --- /dev/null +++ b/usrp2/extram/extram_interface.v @@ -0,0 +1,53 @@ + +// Temporary buffer pool storage, mostly useful for pre-generated data streams or +// for making more space to juggle packets in case of eth frames coming out of order + +module extram_interface + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + // Buffer pool interfaces + input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o, + input rd_sop_i, input rd_eop_i, + output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o, + input wr_ready_i, input wr_full_i, + + // RAM Interface + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + input RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn ); + + // Command format -- + // Read/_Write , start address[17:0] + wire [18:0] cmd_in; + wire cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd; + wire empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd; + + // Dummy logic + assign RAM_OEn = 1; + + setting_reg #(.my_addr(0)) + sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(cmd_in),.changed(cmd_stb)); + + reg cmd_stb_d1; + always @(posedge clk) cmd_stb_d1 <= cmd_stb; + assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1; + assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1; + + shortfifo #(.WIDTH(19)) wr_cmd_fifo + (.clk(clk),.rst(rst),.clear(1'b0), + .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd), + .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) ); + + shortfifo #(.WIDTH(19)) rd_cmd_fifo + (.clk(clk),.rst(rst),.clear(1'b0), + .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd), + .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) ); + +endmodule // extram_interface diff --git a/usrp2/extram/extram_wb.v b/usrp2/extram/extram_wb.v new file mode 100644 index 000000000..c8428783a --- /dev/null +++ b/usrp2/extram/extram_wb.v @@ -0,0 +1,146 @@ + +module extram_wb + #(parameter PAGE_SIZE = 10, + parameter ADDR_WIDTH = 16) + (input clk, input rst, + input wb_clk, input wb_rst, + input cyc_i, input stb_i, + input [ADDR_WIDTH-1:0] adr_i, + input we_i, + input [31:0] dat_i, + output reg [31:0] dat_o, + output reg ack_o, + + inout [17:0] RAM_D, + output [PAGE_SIZE-2:0] RAM_A, + output RAM_CE1n, output RAM_CENn, + output RAM_CLK, output RAM_WEn, + output RAM_OEn, output RAM_LDn ); + + wire read_acc = stb_i & cyc_i & ~we_i; + wire write_acc = stb_i & cyc_i & we_i; + wire acc = stb_i & cyc_i; + + assign RAM_CLK = ~wb_clk; // 50 MHz for now, eventually should be 200 MHz + assign RAM_LDn = 0; // No burst for now + assign RAM_CENn = 0; // Use CE1n as our main CE + + reg [PAGE_SIZE-2:1] RAM_addr_reg; + always @(posedge wb_clk) + if(acc) + RAM_addr_reg[PAGE_SIZE-2:1] <= adr_i[PAGE_SIZE-1:2]; + assign RAM_A[PAGE_SIZE-2:1] = RAM_addr_reg; + + reg [31:0] ram_out; + always @(posedge wb_clk) + if(write_acc) + ram_out <= dat_i; + + // RAM access state machine + localparam RAM_idle = 0; + localparam RAM_read_1 = 1; + localparam RAM_read_2 = 2; + localparam RAM_read_3 = 3; + localparam RAM_read_4 = 4; + localparam RAM_write_1 = 6; + localparam RAM_write_2 = 7; + localparam RAM_write_3 = 8; + localparam RAM_write_4 = 9; + + reg myOE = 0; + reg RAM_OE = 0; + reg RAM_WE = 0; + reg RAM_EN = 0; + reg RAM_A0_reg; + reg [3:0] RAM_state; + + always @(posedge wb_clk) + if(wb_rst) + begin + RAM_state <= RAM_idle; + myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; + end + else + case(RAM_state) + RAM_idle : + if(read_acc & ~ack_o) + begin + RAM_state <= RAM_read_1; + myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 0; + end + else if(write_acc & ~ack_o) + begin + RAM_state <= RAM_write_1; + myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 0; + end + else + begin + myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; + end + RAM_read_1 : + begin + RAM_state <= RAM_read_2; + myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 1; + end + RAM_read_2 : + begin + RAM_state <= RAM_read_3; + myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; + end + RAM_read_3 : + begin + RAM_state <= RAM_read_4; + myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; + end + RAM_read_4 : + begin + RAM_state <= RAM_idle; + myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; + end + RAM_write_1 : + begin + RAM_state <= RAM_write_2; + myOE <= 1; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1; + end + RAM_write_2 : + begin + RAM_state <= RAM_write_3; + myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; + end + RAM_write_3 : + begin + RAM_state <= RAM_write_4; + myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; + end + RAM_write_4 : + begin + RAM_state <= RAM_idle; + myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; + end + default : RAM_state <= RAM_idle; + endcase // case(RAM_state) + + assign RAM_A[0] = RAM_A0_reg; + assign RAM_WEn = ~RAM_WE; // ((RAM_state==RAM_write_1)||(RAM_state==RAM_write_2)); + assign RAM_OEn = ~RAM_OE; + assign RAM_CE1n = ~RAM_EN; // Active low (RAM_state != RAM_idle); + + assign RAM_D[17:16] = 2'bzz; + assign RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_2)?ram_out[15:0]:ram_out[31:16]) + : 16'bzzzz_zzzz_zzzz_zzzz; + + always @(posedge wb_clk) + if(RAM_state == RAM_read_3) + dat_o[15:0] <= RAM_D[15:0]; + else + dat_o[31:16] <= RAM_D[15:0]; + + always @(posedge wb_clk) + if(wb_rst) + ack_o <= 0; + else if((RAM_state == RAM_write_4)||(RAM_state == RAM_read_4)) + ack_o <= 1; + else + ack_o <= 0; + +endmodule // extram_wb diff --git a/usrp2/extram/wb_zbt16_b.v b/usrp2/extram/wb_zbt16_b.v new file mode 100644 index 000000000..d93e21c99 --- /dev/null +++ b/usrp2/extram/wb_zbt16_b.v @@ -0,0 +1,63 @@ + +module wb_zbt16_b + (input clk, + input rst, + // Wishbone bus A, highest priority, with prefetch + input [19:0] wb_adr_i, + input [15:0] wb_dat_i, + output reg [15:0] wb_dat_o, + input [ 1:0] wb_sel_i, + input wb_cyc_i, + input wb_stb_i, + output reg wb_ack_o, + input wb_we_i, + // Memory connection + output sram_clk, + output [18:0] sram_a, + inout [15:0] sram_d, + output sram_we, + output [ 1:0] sram_bw, + output sram_adv, + output sram_ce, + output sram_oe, + output sram_mode, + output sram_zz + ); + + assign sram_clk = ~clk; + //assign sram_oe = 1'b0; + assign sram_ce = 1'b0; + assign sram_adv = 1'b0; + assign sram_mode = 1'b0; + assign sram_zz = 1'b0; + assign sram_bw = 2'b0; + + // need to drive wb_dat_o, wb_ack_o, + // sram_a, sram_d, sram_we + wire myOE; + assign sram_d = myOE ? wb_dat_i : 16'bzzzz; + assign sram_a = wb_adr_i[19:1]; + + reg read_d1, read_d2, read_d3, write_d1, write_d2, write_d3; + wire acc = wb_cyc_i & wb_stb_i; + wire read_acc = wb_cyc_i & wb_stb_i & ~wb_we_i & ~read_d1 & ~read_d2 & ~read_d3; + wire write_acc = wb_cyc_i & wb_stb_i & wb_we_i & ~write_d1 & ~write_d2 & ~write_d3; + + assign sram_we = ~write_acc; + assign sram_oe = ~(read_d2 | read_d3); + assign myOE = write_d1 | write_d2; + wire latch_now = read_d2; + + always @(posedge clk) + if(latch_now) + wb_dat_o <= sram_d; + + always @(posedge clk) wb_ack_o <= read_d2 | write_d2; + always @(posedge clk) read_d1 <= read_acc; + always @(posedge clk) read_d2 <= read_d1; + always @(posedge clk) read_d3 <= read_d2; + always @(posedge clk) write_d1 <= write_acc; + always @(posedge clk) write_d2 <= write_d1; + always @(posedge clk) write_d3 <= write_d2; +endmodule // wb_zbt16_b + diff --git a/usrp2/models/BUFG.v b/usrp2/models/BUFG.v new file mode 100644 index 000000000..a935c6285 --- /dev/null +++ b/usrp2/models/BUFG.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5 2005/03/14 22:32:51 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Buffer +// /___/ /\ Filename : BUFG.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 100 ps / 10 ps + + +module BUFG (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/usrp2/models/CY7C1356C/cy1356.inp b/usrp2/models/CY7C1356C/cy1356.inp new file mode 100644 index 000000000..a55ffac39 --- /dev/null +++ b/usrp2/models/CY7C1356C/cy1356.inp @@ -0,0 +1,140 @@ +/*Address inputs only 0=LOW + "Data is in HEX, four bytes (LSB,MSB)" 1=HIGH + ZZZZZZZZZZZZZZZZ=Tri-state G-WRITE = Global Write + XXXXXXXXXXXXXXXX= Don't care B-WRITE = Byte Write + YYYY=unknown BG-WRITE = BURST GLOBAL WRITE + BB-WRITE = BURST BYTE WRITE + +*/ +// CE3# BW2# ADV/LD# +// CEN# CE2 WE# +// Add IN OUT CE1# BW1# +0000000000000000_XXXXXXXXXXXXXXXX_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 +0000000000000001_XXXXXXXXXXXXXXXX_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 +0000000000000010_0000000000000000_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 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+0000000000000001_xxxxxxxxxxxxxxxx_0001000100010001_0_0_1_0_0_1_1_0 +0000000000000001_0001XXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0_0_1_0_0_0_1_0 +0000000000000001_XXXX0010XXXXXXXX_xxxxxxxxxxxxxxxx_0_0_1_0_0_1_0_0 +0000000000000001_XXXXXXXX0011XXXX_xxxxxxxxxxxxxxxx_0_0_1_0_1_X_X_0 +0000000000000000_XXXXXXXXXXXX0100_xxxxxxxxxxxxxxxx_0_0_1_0_1_X_X_0 +XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0001001000110100_0_X_X_X_X_X_X_1 +XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0110011001100110_0_X_X_X_X_X_X_1 +XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0001001000110100_0_X_X_X_X_X_X_1 +XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0010001000100010_0_1_X_X_X_X_X_0 +xxxxxxxxxxxxxxxx_xxxxxxxxxxxxxxxx_0011001100110011_0_1_x_x_x_x_x_x +xxxxxxxxxxxxxxxx_xxxxxxxxxxxxxxxx_ZZZZZZZZZZZZZZZZ_0_1_x_x_x_x_x_x +//Lines =126 + + diff --git a/usrp2/models/CY7C1356C/cy1356.v b/usrp2/models/CY7C1356C/cy1356.v new file mode 100644 index 000000000..9197eea6d --- /dev/null +++ b/usrp2/models/CY7C1356C/cy1356.v @@ -0,0 +1,485 @@ +`define sb200 +//************************************************************************ +//************************************************************************ +//** This model is the property of Cypress Semiconductor Corp and is ** +//** protected by the US copyright laws, any unauthorized copying and ** +//** distribution is prohibited. Cypress reserves the right to change ** +//** any of the functional specifications without any prior notice. ** +//** Cypress is not liable for any damages which may result from the ** +//** use of this functional model. ** +//** ** +//** File Name : CY7C1356 ** +//** ** +//** Revision : 1.0 - 08/03/2004 ** +//** ** +//** The timings are to be selected by the user depending upon the ** +//** frequency of operation from the datasheet. ** +//** ** +//** Model : CY7C1356C - NoBL Pipelined SRAM ** +//** Queries : MPD Applications ** +//** Website: www.cypress.com/support ** +//************************************************************************ +//************************************************************************ + +`timescale 1ns / 10ps + +// NOTE : Any setup/hold errors will force input signal to x state +// or if results indeterminant (write addr) core is reset x + +// define fixed values + +`define wordsize (18 -1) // +`define no_words (1048576 -1) // 1M x 18 RAM + +module cy1356 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); + +inout [`wordsize:0] d; +input clk, // clock input (R) + we_b, // byte write enable(L) + adv_lb, // burst(H)/load(L) address + ce1b, // chip enable(L) + ce2, // chip enable(H) + ce3b, // chip enable(L) + oeb, // async output enable(L)(read) + cenb, // clock enable(L) + mode; // interleave(H)/linear(L) burst +input [1:0] bws; // byte write select(L) +input [18:0] a; // address bus + +// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK *** +// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT *** + + +//********************************************************************** +// Timings for 225MHz +//********************************************************************** +`ifdef sb225 + `define teohz #2.8 + `define teolz #0 + `define tchz #2.8 + `define tclz #1.25 + + `define tco #2.8 + `define tdoh #1.25 + `define tas 1.4 + `define tah 0.4 +`endif +//*********************************************************************** +// Timings for 200MHz +//********************************************************************** +`ifdef sb200 + `define teohz #3.2 + `define teolz #0 + `define tchz #3.2 + `define tclz #1.5 + + `define tco #3.2 + `define tdoh #1.5 + + `define tas 1.5 + `define tah 0.5 +`endif +//*********************************************************************** + +//********************************************************************** +// This model is configured for 166 MHz Operation (CY7C1356-166). +//********************************************************************** +`ifdef sb166 + `define teohz #3.5 + `define teolz #0 + `define tchz #3.5 + `define tclz #1.5 + + `define tco #3.5 + `define tdoh #1.5 + + `define tas 1.5 + `define tah 0.5 +`endif + +reg notifier; // error support reg's +reg noti1_0; +reg noti1_1; +reg noti1_2; +reg noti1_3; +reg noti1_4; +reg noti1_5; +reg noti1_6; +reg noti2; + + +wire chipen; // combined chip enable (high for an active chip) + +reg chipen_d; // _d = delayed +reg chipen_o; // _o = operational = delayed sig or _d sig + +wire writestate; // holds 1 if any of writebus is low +reg writestate_d; +reg writestate_o; + +wire loadcyc; // holds 1 for load cycles (setup and hold checks) +wire writecyc; // holds 1 for write cycles (setup and hold checks) +wire [1:0] bws; // holds the bws values + +wire [1:0] writebusb; // holds the "internal" bws bus based on we_b +reg [1:0] writebusb_d; +reg [1:0] writebusb_o; + +wire [2:0] operation; // holds chipen, adv_ld and writestate +reg [2:0] operation_d; +reg [2:0] operation_o; + +wire [18:0] a; // address input bus +reg [18:0] a_d; +reg [18:0] a_o; + +reg [`wordsize:0] do; // data output reg +reg [`wordsize:0] di; // data input bus +reg [`wordsize:0] dd; // data delayed bus + +wire tristate; // tristate output (on a bytewise basis) when asserted +reg cetri; // register set by chip disable which sets the tristate +reg oetri; // register set by oe which sets the tristate +reg enable; // register to make the ram enabled when equal to 1 +reg [18:0] addreg; // register to hold the input address +reg [`wordsize:0] pipereg; // register for the output data + +reg [`wordsize:0] mem [0:`no_words]; // RAM array + +reg [`wordsize:0] writeword; // temporary holding register for the write data +reg burstinit; // register to hold a[0] for burst type +reg [18:0] i; // temporary register used to write to all mem locs. +reg writetri; // tristate +reg lw, bw; // pipelined write functions +reg we_bl; + + +wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 18'bz ; // data bus + +assign chipen = (adv_lb == 1 ) ? chipen_d : + ~ce1b & ce2 & ~ce3b ; + +assign writestate = ~& writebusb; + +assign operation = {chipen, adv_lb, writestate}; + +assign writebusb[1:0] = ( we_b ==0 & adv_lb ==0) ? bws[1:0]: + ( we_b ==1 & adv_lb ==0) ? 2'b11 : + ( we_bl ==0 & adv_lb ==1) ? bws[1:0]: + ( we_bl ==1 & adv_lb ==1) ? 2'b11 : + 2'bxx ; + +assign loadcyc = chipen & !cenb; + +assign writecyc = writestate_d & enable & ~cenb & chipen; // check + +assign tristate = cetri | writetri | oetri; + +pullup (mode); + +// formers for notices/errors etc +// +//$display("NOTICE : xxx :"); +//$display("WARNING : xxx :"); +//$display("ERROR *** : xxx :"); + + +// initialize the output to be tri-state, ram to be disabled + +initial + begin +// signals + + writetri = 0; + cetri = 1; + enable = 0; + lw = 0; + bw = 0; + +// error signals + + notifier = 0; + noti1_0 = 0; + noti1_1 = 0; + noti1_2 = 0; + noti1_3 = 0; + noti1_4 = 0; + noti1_5 = 0; + noti1_6 = 0; + noti2 = 0; + +end + + + +// asynchronous OE + +always @(oeb) +begin + if (oeb == 1) + oetri <= `teohz 1; + else + oetri <= `teolz 0; +end + +// *** SETUP / HOLD VIOLATIONS *** + +always @(noti2) +begin +$display("NOTICE : 020 : Data bus corruption"); + force d =18'bx; + #1; + release d; +end + +always @(noti1_0) +begin +$display("NOTICE : 010 : Byte write corruption"); + force bws = 2'bx; + #1; + release bws; +end + +always @(noti1_1) +begin +$display("NOTICE : 011 : Byte enable corruption"); + force we_b = 1'bx; + #1; + release we_b; +end + +always @(noti1_2) +begin +$display("NOTICE : 012 : CE1B corruption"); + force ce1b =1'bx; + #1; + release ce1b; +end + +always @(noti1_3) +begin +$display("NOTICE : 013 : CE2 corruption"); + force ce2 =1'bx; + #1; + release ce2; +end + +always @(noti1_4) +begin +$display("NOTICE : 014 : CE3B corruption"); + force ce3b =1'bx; + #1; + release ce3b; +end + +always @(noti1_5) +begin +$display("NOTICE : 015 : CENB corruption"); + force cenb =1'bx; + #1; + release cenb; +end + +always @(noti1_6) +begin +$display("NOTICE : 016 : ADV_LB corruption"); + force adv_lb = 1'bx; + #1; + release adv_lb; +end + +// synchronous functions from clk edge + +always @(posedge clk) +if (!cenb) +begin +#0.01; + // latch conditions on adv_lb + + if (adv_lb) + we_bl <= we_bl; + else + we_bl <= we_b; + + chipen_d <= chipen; + + + chipen_o <= chipen; + writestate_o <= writestate; + writestate_d <= writestate_o; + writebusb_o <= writebusb; + writebusb_d <= writebusb_o; + operation_o <= operation; + a_o <= a; + a_d <= a_o; + di = d; + + // execute previously pipelined fns + + if (lw) begin + loadwrite; + lw =0; + end + + if (bw) begin + burstwrite; + bw =0; + end + + // decode input/piplined state + + casex (operation_o) + 3'b0?? : turnoff; + 3'b101 : setlw; + 3'b111 : setbw; + 3'b100 : loadread; + 3'b110 : burstread; + default : unknown; // output unknown values and display an error message + endcase + + do <= `tco pipereg; + +end + +// *** task section *** + +task read; +begin + if (enable) cetri <= `tclz 0; + writetri <= `tchz 0; + do <= `tdoh 18'hx; + pipereg = mem[addreg]; +end +endtask + +task write; +begin + if (enable) cetri <= `tclz 0; + writeword = mem[addreg]; // set up a word to hold the data for the current location + /* overwrite the current word for the bytes being written to */ + if (!writebusb_d[1]) writeword[17:9] = di[17:9]; + if (!writebusb_d[0]) writeword[8:0] = di[8:0]; + writeword = writeword & writeword; //convert z to x states + mem[addreg] = writeword; // store the new word into the memory location + //writetri <= `tchz 1; // tristate the outputs +end +endtask + +task setlw; +begin + lw =1; + writetri <= `tchz 1; // tristate the outputs +end +endtask + +task setbw; +begin + bw =1; + writetri <= `tchz 1; // tristate the outputs +end +endtask + +task loadread; +begin + burstinit = a_o[0]; + addreg = a_o; + enable = 1; + read; +end +endtask + +task loadwrite; +begin + burstinit = a_d[0]; + addreg = a_d; + enable = 1; + write; +end +endtask + +task burstread; +begin + burst; + read; +end +endtask + +task burstwrite; +begin + burst; + write; +end +endtask + +task unknown; +begin + do = 18'bx; + // $display ("Unknown function: Operation = %b\n", operation); +end +endtask + +task turnoff; +begin + enable = 0; + cetri <= `tchz 1; + pipereg = 18'h0; +end +endtask + +task burst; +begin + if (burstinit == 0 || mode == 0) + begin + case (addreg[1:0]) + 2'b00: addreg[1:0] = 2'b01; + 2'b01: addreg[1:0] = 2'b10; + 2'b10: addreg[1:0] = 2'b11; + 2'b11: addreg[1:0] = 2'b00; + default: addreg[1:0] = 2'bxx; + endcase + end + else + begin + case (addreg[1:0]) + 2'b00: addreg[1:0] = 2'b11; + 2'b01: addreg[1:0] = 2'b00; + 2'b10: addreg[1:0] = 2'b01; + 2'b11: addreg[1:0] = 2'b10; + default: addreg[1:0] = 2'bxx; + endcase + end +end +endtask + +// IO checks + +specify +// specify the setup and hold checks + +// notifier will wipe memory as result is indeterminent + +$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier); + +// noti1 should make ip = 'bx; + +$setuphold(posedge clk, bws, `tas, `tah, noti1_0); + +$setuphold(posedge clk, we_b, `tas, `tah, noti1_1); +$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2); +$setuphold(posedge clk, ce2, `tas, `tah, noti1_3); +$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4); + +// noti2 should make d = 18'hxxxxx; + +$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2); + +// add extra tests here. + +$setuphold(posedge clk, cenb, `tas, `tah, noti1_5); +$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6); + +endspecify + +endmodule + + diff --git a/usrp2/models/CY7C1356C/readme.txt b/usrp2/models/CY7C1356C/readme.txt new file mode 100644 index 000000000..3578c80dc --- /dev/null +++ b/usrp2/models/CY7C1356C/readme.txt @@ -0,0 +1,33 @@ +*************************** +Cypress Semiconductor +MPD Applications +Verilog model for NoBL SRAM CY7C1356 +Created: August 04, 2004 +Rev: 1.0 +*************************** + +This is the verilog model for the CY7C1356 along with the testbench and test vectors. + +Contact support@cypress.com if you have any questions. + +This directory has 4 files. including this readme. + +1)cy7c1356c.v -> Verilog model for CY7C1356c + +2)cy1356.inp -> Test Vector File used for testing the verilog model + +3)testbench.v -> Test bench used for testing the verilog model + + +COMPILING METHOD : +------------------ + + verilog +define+
+ + Ex: + verilog +define+sb133 CY7C1356c.v testbench.v + +VERIFIED WITH: +-------------- + +VERILOG-XL 2.2 \ No newline at end of file diff --git a/usrp2/models/CY7C1356C/testbench.v b/usrp2/models/CY7C1356C/testbench.v new file mode 100644 index 000000000..5dde89e6c --- /dev/null +++ b/usrp2/models/CY7C1356C/testbench.v @@ -0,0 +1,189 @@ +`timescale 1ns / 10ps + + +// +// CY7C1356 +// Simulatiom of Verilog model +// +// + +// +// test bench for US vector input +// +// + +// define speed 166MHz + +`define tx10 #6 +`define tx08 #4.8 +`define tx05 #3 +`define tx04 #2.4 +`define tx02 #1.2 + +/* +`define tx10 #4.0 // period +`define tx08 #3.2 //0.8 period +`define tx05 #2.0 //0.5 period 250MHZ +`define tx04 #1.6 //0.4 period +`define tx02 #0.8 //0.2 period + +`define tx10 #4.4 // period +`define tx08 #3.52 //0.8 period +`define tx05 #2.2 //0.5 period 225MHZ +`define tx04 #1.76 //0.4 period +`define tx02 #0.88 //0.2 period + +`define tx10 #5 // period +`define tx08 #4 //0.8 period +`define tx05 #2.5 //0.5 period 200MHZ +`define tx04 #2.0 //0.4 period +`define tx02 #1.0 //0.2 period +*/ + + +module rw_test; + +`define num_vectors 126 +`define impi {a[15:0],io[15:0],tsti[15:0],cenb,ce1b,ce2,ce3b,bweb,bwb,adv_lb} + + +reg [57:1] lsim_vectors [1:`num_vectors]; + + +reg clk; +reg adv_lb; +reg ce1b; //cs1b +reg ce2; //cs2 +reg ce3b; //cs3b +reg [1:0] bwb; +reg bweb; +reg oeb; +reg ftb; +reg mode; //lbob +reg cenb; //zz +reg tp42; //sclk +reg tp39; //se +reg tp38; //tm +reg [19:0] a; +reg [17:0] io; +reg [17:0] tsti; +reg vddq; +reg vssqr; +reg iosel; + + +wire [17:0] d = iosel ? io[17:0] : 18'bz; + +reg noti3; +reg strb,j; +integer vector,i; + + + +cy1356 testram ( d, clk, a, bwb, bweb, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); + +initial +begin + $dumpfile("dumpfile.dump"); + $dumpvars(0,rw_test); +end + +initial +begin +io = 18'bz; +ftb = 1; +oeb = 0; +a[19:16] = 4'h0; +mode = 0; +strb = 0; +tp38 = 0; +tp39 = 0; +tp42 = 0; +`tx02; +forever `tx05 strb = ~strb; +end + +initial +begin +clk = 0; +forever `tx05 clk =~clk; +end + +initial + begin + + $readmemb("cy1356.inp", lsim_vectors); //load input vector file + + `impi = lsim_vectors[1]; //apply 1st test vector + + for (vector = 2; vector <= `num_vectors; vector = vector + 1) + @(posedge strb) + begin + + `impi = lsim_vectors[vector]; + + + + io[16:13] = io[07:04]; + io[12:09] = io[07:04]; + io[07:04] = io[03:00]; + io[03:00] = io[03:00]; + + io[17] = io[16] ^^ io[15] ^^ io[14] ^^ io[13] ^^ io[11] ^^ io[11] ^^ io[10] ^^ io[9]; + io[8] = io[7] ^^ io[6] ^^ io[5] ^^ io[4] ^^ io[3] ^^ io[2] ^^ io[1] ^^ io[0]; + + tsti[16:13] = tsti[07:04]; + tsti[12:09] = tsti[07:04]; + tsti[07:04] = tsti[03:00]; + tsti[03:00] = tsti[03:00]; + + tsti[17] = tsti[16] ^^ tsti[15] ^^ tsti[14] ^^ tsti[13] ^^ tsti[11] ^^ tsti[11] ^^ tsti[10] ^^ tsti[9]; + tsti[8] = tsti[7] ^^ tsti[6] ^^ tsti[5] ^^ tsti[4] ^^ tsti[3] ^^ tsti[2] ^^ tsti[1] ^^ tsti[0]; + + if (io === 18'hxxxxx) + iosel = `tx05 0; + else + iosel = `tx05 1; + + end + #15 $finish; // This prevents simulation beyond end of test patterns + end + +always@(posedge clk) +begin + + if (io !== 18'hxxxxx) //input cycle + begin + $display("NOTICE : 001 : line = %d OK",vector -1); + end + else //do the test + begin + if (d == tsti) + begin + $display("NOTICE : 002 : line = %d OK",vector -1); + end + else + begin + j =0; + for (i =0;i< 18; i=i+1) + begin + if(tsti[i] !== 1'bx) + begin + if (d[i] !== tsti[i]) j = 1; + end + else + j = 0; + end + if (j) + $display("ERROR *** : 003 : line = %d data = %b test = %b",vector -1,d,tsti); + else + $display("NOTICE : 003 : line = %d OK",vector -1); + end + end +end + +endmodule + + + + diff --git a/usrp2/models/FIFO_GENERATOR_V4_3.v b/usrp2/models/FIFO_GENERATOR_V4_3.v new file mode 100644 index 000000000..bcb9af8a7 --- /dev/null +++ b/usrp2/models/FIFO_GENERATOR_V4_3.v @@ -0,0 +1,3494 @@ +/* + * $RDCfile: $ $Revision: 1.1.2.15 $ $Date: 2007/07/25 15:58:33 $ + ******************************************************************************* + * + * FIFO Generator v3.3 - Verilog Behavioral Model + * + ******************************************************************************* + * + * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing theis design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard. Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * This copyright and support notice must be retained as part + * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. + * All rights reserved. + * + ******************************************************************************* + * + * Filename: fifo_generator_v4_3_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V4_3 +( + BACKUP, + BACKUP_MARKER, + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, + INT_CLK, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + SBITERR, + DBITERR + ); + + /**************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + + /**************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + + parameter C_FAMILY = "virtex2"; + //Not allowed in Verilog model + + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = 512; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_USE_ECC = 0; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_INT_CLK = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + + //There are 2 Verilog behavioral models + // 0 = Synchronous FIFO/ShiftRam FIFO + // 1 = Asynchronous FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : + (C_IMPLEMENTATION_TYPE==1 ? 0 : + (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + + assign SBITERR = 1'b0; + assign DBITERR = 1'b0; + +// choose the base FIFO implementation for simulation +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + fifo_generator_v4_3_bhv_ver_ss + #( + C_COMMON_CLOCK, + C_COUNT_TYPE, + C_DATA_COUNT_WIDTH, + C_DEFAULT_VALUE, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_ENABLE_RLOCS, + C_FAMILY,//Not allowed in Verilog model + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_BACKUP, + C_HAS_DATA_COUNT, + C_HAS_MEMINIT_FILE, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RD_RST, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_HAS_WR_RST, + C_IMPLEMENTATION_TYPE, + C_INIT_WR_PNTR_VAL, + C_MEMORY_TYPE, + C_MIF_FILE_NAME, + C_OPTIMIZATION_MODE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_WR_RESPONSE_LATENCY, + C_FULL_FLAGS_RST_VAL, + C_USE_EMBEDDED_REG + ) + gen_ss + ( + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end +1 : begin : block1 + fifo_generator_v4_3_bhv_ver_as + #( + C_COMMON_CLOCK, + C_COUNT_TYPE, + C_DATA_COUNT_WIDTH, + C_DEFAULT_VALUE, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_ENABLE_RLOCS, + C_FAMILY,//Not allowed in Verilog model + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_BACKUP, + C_HAS_DATA_COUNT, + C_HAS_MEMINIT_FILE, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RD_RST, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_HAS_WR_RST, + C_IMPLEMENTATION_TYPE, + C_INIT_WR_PNTR_VAL, + C_MEMORY_TYPE, + C_MIF_FILE_NAME, + C_OPTIMIZATION_MODE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_WR_RESPONSE_LATENCY, + C_FULL_FLAGS_RST_VAL, + C_USE_FWFT_DATA_COUNT, + C_USE_EMBEDDED_REG + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +default : begin : block1 + fifo_generator_v4_3_bhv_ver_as + #( + C_COMMON_CLOCK, + C_COUNT_TYPE, + C_DATA_COUNT_WIDTH, + C_DEFAULT_VALUE, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_ENABLE_RLOCS, + C_FAMILY,//Not allowed in Verilog model + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_BACKUP, + C_HAS_DATA_COUNT, + C_HAS_MEMINIT_FILE, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RD_RST, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_HAS_WR_RST, + C_IMPLEMENTATION_TYPE, + C_INIT_WR_PNTR_VAL, + C_MEMORY_TYPE, + C_MIF_FILE_NAME, + C_OPTIMIZATION_MODE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_WR_RESPONSE_LATENCY, + C_FULL_FLAGS_RST_VAL, + C_USE_FWFT_DATA_COUNT, + C_USE_EMBEDDED_REG + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +endcase +endgenerate + + +//************************************************************************** +// Connect Internal Signals +// (Signals labeled internal_*) +// In the normal case, these signals tie directly to the FIFO's inputs and +// outputs. +// In the case of Preload Latency 0 or 1, there are intermediate +// signals between the internal FIFO and the preload logic. +//************************************************************************** + +generate +if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + begin : block2 + +fifo_generator_v4_3_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_VALID_LOW, + C_UNDERFLOW_LOW + ) + fgpl0 +( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT) + ); + + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = RST; + assign RD_EN_P0_IN = RD_EN; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + assign DOUT = DATA_P0_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + always @ (posedge RD_CLK or posedge RST) + begin + if (RST) + begin + EMPTY_P0_OUT_Q <= 1; + ALMOSTEMPTY_P0_OUT_Q <= 1; + end + else + begin + EMPTY_P0_OUT_Q <= EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT; + end + end + + end +else + begin : block2 + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + + end +endgenerate + + +//Connect Data Count Signals +generate +if (C_USE_FWFT_DATA_COUNT==1) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); +end +else begin : block3 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; +end +endgenerate + +generate +if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; +end +else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; +end +endgenerate + + + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + //if (C_IMPLEMENTATION_TYPE == 1) begin //bug in v3.1 + if (C_IMPLEMENTATION_TYPE == 2) begin //fixed in v3.2 (IP2_Im) + $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin + $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + $finish; + end + + end + +endmodule //fifo_generator_v4_3_bhv_ver + + + + + + +/******************************************************************************* + * Declaration of asynchronous FIFO Module + ******************************************************************************/ +module fifo_generator_v4_3_bhv_ver_as + ( + WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID, + UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY + ); + + /***************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_USE_EMBEDDED_REG = 0; + + /***************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RST; + input WR_CLK; + input WR_EN; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + /******************************************************************************* + * Input and output register declarations + ******************************************************************************/ + /******************************************************************************* + * Parameters used as constants + ******************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = + (C_COMMON_CLOCK) ? + C_WR_DEPTH : C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = + (C_COMMON_CLOCK) ? + C_RD_DEPTH : C_RD_DEPTH - 1; + + + // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 + // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) + // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 + // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 + parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); + // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + parameter EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR)? + 2:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + reg [31:0] wr_ptr; + reg [31:0] rd_ptr; + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + wire [31:0] num_read_words = num_rd_bits/C_DOUT_WIDTH; + wire [31:0] num_read_words_dc_i; + wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized + = num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft + = num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + wire [31:0] num_write_words = num_wr_bits/C_DIN_WIDTH; + wire [31:0] num_write_words_dc_i; + wire [31:0] num_write_words_dc = 1+(num_wr_bits-1)/C_DIN_WIDTH;//roof of num_wr_bits/C_DIN_WIDTH + wire [31:0] num_write_words_fwft_dc = + (num_wr_bits/C_DIN_WIDTH*C_DEPTH_RATIO_RD+2*C_DEPTH_RATIO_WR)/C_DEPTH_RATIO_RD; + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized + = num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft + = num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + wire [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + wire [31:0] log2_reads_per_write = log2_val(reads_per_write); + wire [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + wire [31:0] log2_writes_per_read = log2_val(writes_per_read); + + /******************************************************************************* + * Internal Registers and wires + ******************************************************************************/ + wire wr_ack_i; + wire overflow_i; + wire underflow_i; + wire valid_i; + wire valid_out; + reg valid_d1; + /******************************************************************************* + * Internal registers and wires for internal reset logics + ******************************************************************************/ + reg rd_rst_asreg =0; + reg rd_rst_asreg_d1 =0; + reg rd_rst_asreg_d2 =0; + reg rd_rst_reg =0; + reg rd_rst_d1 =0; + reg wr_rst_asreg =0; + reg wr_rst_asreg_d1 =0; + reg wr_rst_asreg_d2 =0; + reg wr_rst_reg =0; + reg wr_rst_d1 =0; + wire rd_rst_comb; + wire rd_rst_i; + wire wr_rst_comb; + wire wr_rst_i; + + + + //Special ideal FIFO signals + reg [C_DOUT_WIDTH-1:0] ideal_dout; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + //MSBs of the counts + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + reg prog_full_d; + reg prog_empty_d; + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + task write_fifo; + begin + memory[wr_ptr] <= DIN; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + begin + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr]; + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial + begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) + //ideal_full = C_FULL_RESET_VAL; //was in v3.1 + ideal_full = 1'b0; //v3.2 + ideal_empty = 1'b1; + //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) + //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 + ideal_almost_full = 1'b0; //v3.2 + ideal_almost_empty = 1'b1; + ideal_wr_count = 0; + ideal_rd_count = 0; + //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) + //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 + ideal_prog_full = 1'b0; //v3.2 + ideal_prog_empty = 1'b1; + //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) + //Therefore, prog_full_d has to start-up at '0' too + //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 + prog_full_d = 1'b0; //v3.2 + prog_empty_d = 1'b1; + end + + + + /************************************************************************* + * Assign Internal ideal signals to output ports + *************************************************************************/ + assign ideal_dout_out= (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + assign FULL = ideal_full; + assign EMPTY = ideal_empty; + assign ALMOST_FULL = ideal_almost_full; + assign ALMOST_EMPTY = ideal_almost_empty; + assign num_write_words_sized_i=C_USE_FWFT_DATA_COUNT? + num_write_words_sized_fwft:num_write_words_sized; + assign num_read_words_sized_i=C_USE_FWFT_DATA_COUNT? + num_read_words_sized_fwft:num_read_words_sized; + assign num_write_words_dc_i = C_USE_FWFT_DATA_COUNT? + num_write_words_fwft_dc: num_write_words_dc; + assign num_read_words_dc_i = C_USE_FWFT_DATA_COUNT? + num_read_words_fwft_dc: num_read_words_dc; + assign WR_DATA_COUNT = ideal_wr_count; + assign RD_DATA_COUNT = ideal_rd_count; + assign PROG_FULL = ideal_prog_full; + assign PROG_EMPTY = ideal_prog_empty; + + //Handshaking signals can be active low, depending on _LOW parameters + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + + assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + assign wr_ack_i = (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : + (WR_EN & !FULL); + assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + assign overflow_i = (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : + (WR_EN & FULL); + + /******************************************************************************* + * Internal reset logics + ******************************************************************************/ + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + assign wr_rst_i = C_HAS_RST ? wr_rst_reg : 0; + assign rd_rst_i = C_HAS_RST ? rd_rst_reg : 0; + + + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= valid_i; + end + end + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + ideal_dout_d1 <= ideal_dout; + end + end + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= 1'b0; + end else begin + wr_rst_asreg <= wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= wr_rst_asreg; + wr_rst_asreg_d2 <= wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= 1'b1; + end else begin + wr_rst_reg <= 1'b0; + end + end + + always @(posedge WR_CLK or posedge wr_rst_i) begin + if (wr_rst_i == 1'b1) begin + wr_rst_d1 <= 1'b1; + end else begin + wr_rst_d1 <= wr_rst_i; + end + end + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= 1'b0; + end else begin + rd_rst_asreg <= rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= rd_rst_asreg; + rd_rst_asreg_d2 <= rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= 1'b1; + end else begin + rd_rst_reg <= 1'b0; + end + end + + //Generate overflow and underflow flags seperately + //because they don't support async rst + always @(posedge WR_CLK) begin + ideal_overflow <= WR_EN & ideal_full; + end + always @(posedge RD_CLK) begin + ideal_underflow <= ideal_empty & RD_EN; + end + + /******************************************************************************* + * Write and Read Logics + ******************************************************************************/ + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= 0; + next_num_wr_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr_wrclk <= C_RD_DEPTH - 1; + ideal_wr_ack <= 0; + ideal_full <= C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= C_FULL_FLAGS_RST_VAL; + ideal_wr_count <= 0; + + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + prog_full_d <= C_FULL_FLAGS_RST_VAL; + + end else begin //wr_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (ideal_full == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + //With DEPTH-1 words in the FIFO, it is almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + //FIFO is really not close to full, so change flag status. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is one from full + end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //This write is CAUSING the FIFO to go full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is 2 from full + end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //Still 2 from full + ideal_full <= 1'b0; + //2 from full, and writing, so set almost_full + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is not close to being full + end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //Not even close to full. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= 0; + + //Implied statements: + //ideal_empty <= ideal_empty; + //ideal_almost_empty <= ideal_almost_empty; + + //Check for full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) + ideal_full <= 1'b1; + else + ideal_full <= 1'b0; + + //Check for almost_full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) + ideal_almost_full <= 1'b1; + else + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + end + + /********************************************************* + * Programmable FULL flags + *********************************************************/ + //Single Programmable Full Constant Threshold + if (C_PROG_FULL_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; + end + + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; + end + + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH; + prog_full_actual_thresh_negate = PROG_FULL_THRESH; + end + + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; + end + end //C_PROG_FULL_TYPE + + if (num_write_words_pf==0) begin + prog_full_d <= 1'b0; + end else begin + if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + == prog_full_actual_thresh_assert-1) && WR_EN) begin + prog_full_d <= 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + >= prog_full_actual_thresh_assert) begin + prog_full_d <= 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + < prog_full_actual_thresh_negate) begin + prog_full_d <= 1'b0; + end + end + + if (wr_rst_d1==1 && wr_rst_i==0) begin + ideal_prog_full <= 0; + end else begin + ideal_prog_full <= prog_full_d; + end + num_wr_bits <= next_num_wr_bits; + rd_ptr_wrclk <= rd_ptr; + + end //wr_rst_i==0 + end // write always + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= 0; + next_num_rd_bits <= 0; + rd_ptr <= C_RD_DEPTH -1; + wr_ptr_rdclk <= C_WR_DEPTH -1; + ideal_dout <= dout_reset_val; + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + ideal_rd_count <= 0; + + ideal_prog_empty <= 1'b1; + prog_empty_d <= 1; + + + end else begin //rd_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + // (Subtract 2 read-sized words when using Preload 0) + + //Single Programmable Empty Constant Threshold + if (C_PROG_EMPTY_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; + end + + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + + //Single Programmable Empty Constant Threshold + end else if (C_PROG_EMPTY_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; + + end + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; + end + end + + if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) + && RD_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + <= prog_empty_actual_thresh_assert) begin + prog_empty_d <= 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + > prog_empty_actual_thresh_negate) begin + prog_empty_d <= 1'b0; + end + + + ideal_prog_empty <= prog_empty_d; + num_rd_bits <= next_num_rd_bits; + wr_ptr_rdclk <= wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v4_3_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v4_3_bhv_ver_ss + ( + CLK, RST, SRST, DIN, WR_EN, RD_EN, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, + ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, + PROG_FULL, PROG_EMPTY + ); + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_USE_EMBEDDED_REG = 0; + + +/****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_EN; + input RST; + input SRST; + input WR_EN; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output UNDERFLOW; + output WR_ACK; + +/******************************************************************************* + * Input and output register declarations + ******************************************************************************/ +/******************************************************************************* + * Parameters used as constants + ******************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = (C_COMMON_CLOCK) ? C_WR_DEPTH : C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = (C_COMMON_CLOCK) ? C_RD_DEPTH : C_RD_DEPTH - 1; + + /**************************************************************************** + * Internal Registers and wires + ***************************************************************************/ + wire wr_ack_i; + wire overflow_i; + wire underflow_i; + wire valid_i; + wire valid_out; + reg valid_d1; + wire srst_i; + /******************************************************************************* + * Internal registers and wires for internal reset logics + ******************************************************************************/ + reg rst_asreg =0; + reg rst_asreg_d1 =0; + reg rst_asreg_d2 =0; + reg rst_reg =0; + reg rst_d1 =0; + wire rst_comb; + wire rst_i; + + + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + reg [31:0] num_bits; + reg [31:0] wr_ptr; + reg [31:0] rd_ptr; + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + reg [31:0] num_read_words_q; + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + reg [31:0] num_write_words_q; + //Removed power_on_timer in v3.2 (IP2_Im). For all reset types (Async, Sync, or no reset), the power-on values of the flags in the core are modified so that the core is ready to use from the very first clock cycle. + //reg [3:0] power_on_timer; + + //Special ideal FIFO signals + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + + //MSBs of the counts + wire [C_DATA_COUNT_WIDTH-1:0] ideal_d_count; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + + //temporary registers for WR_RESPONSE_LATENCY feature + reg ideal_wr_ack_q; + reg ideal_overflow_q; + + reg prog_full_d; + reg prog_empty_d; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + task read_fifo; + begin + ideal_dout <= memory[rd_ptr]; + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /***************************************************************************** + * Initialize Signals + ****************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) + //ideal_full = C_FULL_RESET_VAL; //was in v3.1 + ideal_full = 1'b0; //v3.2 + ideal_empty = 1'b1; + //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) + //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) + //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 + ideal_prog_full = 1'b0; //v3.2 + ideal_prog_empty = 1'b1; + + //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) + //Therefore, prog_full_d is also changed + //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 + prog_full_d = 1'b0; //v3.2 + prog_empty_d = 1'b1; + + //Removed in v3.2 + //power_on_timer = C_HAS_RST ? 4'h3 : 4'h0; + + //Added these initial values in v3.2 to make it consistent with the synchronization flop stages in the core. + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /***************************************************************************** + * Assign Internal ideal signals to output ports + ****************************************************************************/ + assign ideal_dout_out= (C_USE_EMBEDDED_REG==1 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + //was in v3.1 + //assign FULL = (power_on_timer) ? C_FULL_RESET_VAL : ideal_full; + //v3.2 + assign FULL = ideal_full; + + assign EMPTY = ideal_empty; + //was in v3.1 + //assign ALMOST_FULL = (power_on_timer) ? C_ALMOST_FULL_RESET_VAL : ideal_almost_full; + //v3.2 + assign ALMOST_FULL = ideal_almost_full; + + assign ALMOST_EMPTY = ideal_almost_empty; + + assign ideal_d_count = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + assign DATA_COUNT = ideal_d_count; + + //was in v3.1 + //assign PROG_FULL = (power_on_timer) ? C_PROG_FULL_RESET_VAL : ideal_prog_full; + //v3.2 + assign PROG_FULL = ideal_prog_full; + + assign PROG_EMPTY = ideal_prog_empty; + + //Handshaking signals can be active low, depending on _LOW parameters + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + + assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + assign wr_ack_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_wr_ack_q : + (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : + (WR_EN & !FULL); + assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + assign overflow_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_overflow_q : + (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : + (WR_EN & FULL); + + assign srst_i = C_HAS_SRST ? SRST : 0; + + /******************************************************************************* + * Internal reset logics + ******************************************************************************/ + assign rst_comb = !rst_asreg_d2 && rst_asreg; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= valid_i; + end + end + end + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + if (srst_i) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + ideal_dout_d1 <= ideal_dout; + end + end + end + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= 1'b0; + end else begin + rst_asreg <= rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= rst_asreg; + rst_asreg_d2 <= rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= 1'b1; + end else begin + rst_reg <= 1'b0; + end + end + + + /******************************************************************************* + * Write and Read Logics + ******************************************************************************/ + + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= rst_i; + rst_qq <= rst_q; + + //Register output signals to achieve desired WR_RESPONSE latency + if (C_WR_RESPONSE_LATENCY == 2) begin + if (rst_i == 1) begin + ideal_wr_ack_q <= 0; + ideal_overflow_q <= 0; + end else begin + ideal_wr_ack_q <= ideal_wr_ack; + ideal_overflow_q <= ideal_overflow; + end + end + + //Removed in v3.2 + /* + if (rst_i == 1) begin + power_on_timer <= 0; + end else if (power_on_timer > 0) begin + power_on_timer <= power_on_timer -1; + end else begin + power_on_timer <= 0; + end + */ + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. + //if (rst_i || rst_q || rst_qq) begin //was in v3.1 + if (rst_i || rst_q || srst_i) begin //v3.2 + /******Initialize Read Domain Signals************************************/ + if (C_MEMORY_TYPE == 1) begin + ideal_dout <= dout_reset_val; + end + //v3.2 + //end else begin + //if (C_MEMORY_TYPE == 1 && power_on_timer >= 2) begin //was in v3.1 + // if (C_MEMORY_TYPE == 1) begin //v3.2 + // ideal_dout <= dout_reset_val; + // end + end + end + + always @(posedge CLK or posedge rst_i) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset*************************************/ + //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. + //if (rst_i || rst_q || rst_qq) begin //was in v3.1 + //if (rst_i || rst_q) begin //v3.2 + if (rst_i ) begin //v3.2 + /******Initialize Generic FIFO constructs********************************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + + /******Initialize Write Domain Signals***********************************/ + ideal_wr_ack <= 0; + ideal_full <= C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals************************************/ + if (C_MEMORY_TYPE != 1) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + end else begin + if (srst_i) begin + // SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + /******Initialize Generic FIFO constructs********************************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + /******Initialize Write Domain Signals***********************************/ + ideal_wr_ack <= 0; + ideal_full <= 0; //'0' + ideal_almost_full <= 0; //'0' + + /******Initialize Read Domain Signals************************************/ + //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the above always block. + if (C_MEMORY_TYPE == 2) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + end + + end else begin //normal operating conditions + /**********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /**********************************************************************/ + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= 1; + + //FIFO is one from FULL and going FULL + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= 1; + + //2 from full, and writing, so set almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + end // average case + + + /**********************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /**********************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read will fail + ideal_valid <= 1'b0; + + //FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //This read will make FIFO go empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= 0; + + //Not near empty + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + end // average read + + + /**********************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /**********************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read unsuccessful + ideal_valid <= 1'b0; + + //Report empty condition + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + // No read + num_bits <= num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + // Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /**********************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /*** + *******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= num_read_words; + num_write_words_q <= num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + //Generate overflow and underflow flags seperately + //because they don't support async rst + always @(posedge CLK) begin + ideal_overflow <= WR_EN & ideal_full; + ideal_underflow <= ideal_empty & RD_EN; + end + + always @(posedge CLK or posedge rst_i) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be consistent with the core. + //if (rst_i || rst_q) begin //was in v3.1 + if (rst_i) begin //v3.2 + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= 1'b1; + prog_full_d <= C_FULL_FLAGS_RST_VAL; + prog_empty_d <= 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + ideal_prog_full <= 1'b0; + ideal_prog_empty <= 1'b1; + prog_full_d <= 1'b0; + prog_empty_d <= 1'b1; + end + end else begin + + /***************************************************************** + * Programmable FULL flags + ****************************************************************/ + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin //v3.2 + prog_full_d <= 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= 1'b0; + end + end + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + end + + ideal_prog_empty <= prog_empty_d; + if (rst_q && !rst_i) begin + ideal_prog_full <= 1'b0; + end else begin + ideal_prog_full <= prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v4_3_bhv_ver_ss + + +module fifo_generator_v4_3_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + RD_EN, + FIFOEMPTY, + FIFODATA, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN + ); + + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + + + input RD_CLK; + input RD_RST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; //Fix for CR:236270 in v3.2 //prasanna + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + +initial + begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + end + + + //****************************************************************************** + // connect up optional reset + //****************************************************************************** + assign rd_rst_i = C_HAS_RST ? RD_RST : 0; + + + //****************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //****************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //****************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //****************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //****************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //****************************************************************************** + assign ram_regout_en = preloadstage2; + + //****************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which guarantees + // that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is + // replinished by data from the memory. So, as long as the RAM has data in it, + // a read of the RAM should occur. + //****************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //****************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //****************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin // PROCESS regout_valid + if (rd_rst_i) // asynchronous reset (active high) + ram_valid_i <= 1'b0; + else + begin + if (ram_rd_en == 1'b1) + ram_valid_i <= 1'b1; + else + if (ram_regout_en == 1'b1) + ram_valid_i <= 1'b0; + else + ram_valid_i <= ram_valid_i; + end //rd_rst_i + end //always + + //****************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1, + // such that the data in Stage1 is propogated into Stage2. + //****************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) + read_data_valid_i <= 1'b0; + else + read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //***************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //***************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + begin + empty_i <= 1'b1; + empty_q <= 1'b1; + end + else // rising clock edge + begin + empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + empty_q <= empty_i; + end + end //always + + //Fix for CR:236270 //prasanna + //Register RD_EN from user to calculate USERUNDERFLOW. + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + begin + rd_en_q <= 1'b0; + end + else // rising clock edge + begin + rd_en_q <= RD_EN; + end + end //always + + + //***************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //***************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + begin + almost_empty_i <= 1'b1; + almost_empty_q <= 1'b1; + end + else // rising clock edge + begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) + begin + almost_empty_i <= FIFOEMPTY; + end + almost_empty_q <= empty_i; + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + //assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & RD_EN) : empty_q & RD_EN; //Bug in v3.1 (CR:236270) + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //Fix for CR:236270 in v3.2 //prasanna + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + USERDATA <= hexstr_conv(C_DOUT_RST_VAL); + else // rising clock edge + if (ram_regout_en) + USERDATA <= FIFODATA; + end //always + + + + + +endmodule diff --git a/usrp2/models/M24LC024B.v b/usrp2/models/M24LC024B.v new file mode 100644 index 000000000..45e04b450 --- /dev/null +++ b/usrp2/models/M24LC024B.v @@ -0,0 +1,459 @@ +// Modified 11/14/07 to simulate the 24lc024, which responds to the address pins + +// ******************************************************************************************************* +// ** ** +// ** M24LC024B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** +// ** ** +// ******************************************************************************************************* +// ** ** +// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING ** +// ** ALL RIGHTS RESERVED ** +// ** ** +// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR ** +// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS ** +// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN ** +// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. ** +// ** ** +// ******************************************************************************************************* +// ** Revision : 1.1 ** +// ** Modified Date : 07/19/2004 ** +// ** Revision History: ** +// ** ** +// ** 02/01/2003: Initial design ** +// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. ** +// ** ** +// ******************************************************************************************************* +// ** TABLE OF CONTENTS ** +// ******************************************************************************************************* +// **---------------------------------------------------------------------------------------------------** +// ** DECLARATIONS ** +// **---------------------------------------------------------------------------------------------------** +// **---------------------------------------------------------------------------------------------------** +// ** INITIALIZATION ** +// **---------------------------------------------------------------------------------------------------** +// **---------------------------------------------------------------------------------------------------** +// ** CORE LOGIC ** +// **---------------------------------------------------------------------------------------------------** +// ** 1.01: START Bit Detection ** +// ** 1.02: STOP Bit Detection ** +// ** 1.03: Input Shift Register ** +// ** 1.04: Input Bit Counter ** +// ** 1.05: Control Byte Register ** +// ** 1.06: Byte Address Register ** +// ** 1.07: Write Data Buffer ** +// ** 1.08: Acknowledge Generator ** +// ** 1.09: Acknowledge Detect ** +// ** 1.10: Write Cycle Timer ** +// ** 1.11: Write Cycle Processor ** +// ** 1.12: Read Data Multiplexor ** +// ** 1.13: Read Data Processor ** +// ** 1.14: SDA Data I/O Buffer ** +// ** ** +// **---------------------------------------------------------------------------------------------------** +// ** DEBUG LOGIC ** +// **---------------------------------------------------------------------------------------------------** +// ** 2.01: Memory Data Bytes ** +// ** 2.02: Write Data Buffer ** +// ** ** +// **---------------------------------------------------------------------------------------------------** +// ** TIMING CHECKS ** +// **---------------------------------------------------------------------------------------------------** +// ** ** +// ******************************************************************************************************* + + +`timescale 1ns/10ps + +module M24LC024B (A0, A1, A2, WP, SDA, SCL, RESET); + + input A0; // unconnected pin + input A1; // unconnected pin + input A2; // unconnected pin + + input WP; // write protect pin + + inout SDA; // serial data I/O + input SCL; // serial data clock + + input RESET; // system reset + + +// ******************************************************************************************************* +// ** DECLARATIONS ** +// ******************************************************************************************************* + + reg SDA_DO; // serial data - output + reg SDA_OE; // serial data - output enable + + wire SDA_DriveEnable; // serial data output enable + reg SDA_DriveEnableDlyd; // serial data output enable - delayed + + reg [03:00] BitCounter; // serial bit counter + + reg START_Rcvd; // START bit received flag + reg STOP_Rcvd; // STOP bit received flag + reg CTRL_Rcvd; // control byte received flag + reg ADDR_Rcvd; // byte address received flag + reg MACK_Rcvd; // master acknowledge received flag + + reg WrCycle; // memory write cycle + reg RdCycle; // memory read cycle + + reg [07:00] ShiftRegister; // input data shift register + + reg [07:00] ControlByte; // control byte register + wire RdWrBit; // read/write control bit + + reg [07:00] StartAddress; // memory access starting address + reg [02:00] PageAddress; // memory page address + + reg [07:00] WrDataByte [0:7]; // memory write data buffer + wire [07:00] RdDataByte; // memory read data + + reg [15:00] WrCounter; // write buffer counter + + reg [02:00] WrPointer; // write buffer pointer + reg [07:00] RdPointer; // read address pointer + + reg WriteActive; // memory write cycle active + + reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array + + integer LoopIndex; // iterative loop index + + integer tAA; // timing parameter + integer tWC; // timing parameter + + +// ******************************************************************************************************* +// ** INITIALIZATION ** +// ******************************************************************************************************* + + initial tAA = 900; // SCL to SDA output delay + initial tWC = 5000000; // memory write cycle time + //initial tWC = 50000; // shortened memory write cycle time to speed up sims + + initial begin + SDA_DO = 0; + SDA_OE = 0; + end + + initial begin + START_Rcvd = 0; + STOP_Rcvd = 0; + CTRL_Rcvd = 0; + ADDR_Rcvd = 0; + MACK_Rcvd = 0; + end + + initial begin + BitCounter = 0; + ControlByte = 0; + end + + initial begin + WrCycle = 0; + RdCycle = 0; + + WriteActive = 0; + end + + +// ******************************************************************************************************* +// ** CORE LOGIC ** +// ******************************************************************************************************* +// ------------------------------------------------------------------------------------------------------- +// 1.01: START Bit Detection +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SDA) begin + if (SCL == 1) begin + START_Rcvd <= 1; + STOP_Rcvd <= 0; + CTRL_Rcvd <= 0; + ADDR_Rcvd <= 0; + MACK_Rcvd <= 0; + + WrCycle <= #1 0; + RdCycle <= #1 0; + + BitCounter <= 0; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.02: STOP Bit Detection +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SDA) begin + if (SCL == 1) begin + START_Rcvd <= 0; + STOP_Rcvd <= 1; + CTRL_Rcvd <= 0; + ADDR_Rcvd <= 0; + MACK_Rcvd <= 0; + + WrCycle <= #1 0; + RdCycle <= #1 0; + + BitCounter <= 10; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.03: Input Shift Register +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + ShiftRegister[00] <= SDA; + ShiftRegister[01] <= ShiftRegister[00]; + ShiftRegister[02] <= ShiftRegister[01]; + ShiftRegister[03] <= ShiftRegister[02]; + ShiftRegister[04] <= ShiftRegister[03]; + ShiftRegister[05] <= ShiftRegister[04]; + ShiftRegister[06] <= ShiftRegister[05]; + ShiftRegister[07] <= ShiftRegister[06]; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.04: Input Bit Counter +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + if (BitCounter < 10) BitCounter <= BitCounter + 1; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.05: Control Byte Register +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (START_Rcvd & (BitCounter == 8)) begin + if (!WriteActive & (ShiftRegister[07:04] == 4'b1010) + & (ShiftRegister[3:1] == {A2,A1,A0})) begin + if (ShiftRegister[00] == 0) WrCycle <= 1; + if (ShiftRegister[00] == 1) RdCycle <= 1; + + ControlByte <= ShiftRegister[07:00]; + + CTRL_Rcvd <= 1; + end + + START_Rcvd <= 0; + end + end + + assign RdWrBit = ControlByte[00]; + +// ------------------------------------------------------------------------------------------------------- +// 1.06: Byte Address Register +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (CTRL_Rcvd & (BitCounter == 8)) begin + if (RdWrBit == 0) begin + StartAddress <= ShiftRegister[07:00]; + RdPointer <= ShiftRegister[07:00]; + + ADDR_Rcvd <= 1; + end + + WrCounter <= 0; + WrPointer <= 0; + + CTRL_Rcvd <= 0; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.07: Write Data Buffer +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (ADDR_Rcvd & (BitCounter == 8)) begin + if ((WP == 0) & (RdWrBit == 0)) begin + WrDataByte[WrPointer] <= ShiftRegister[07:00]; + + WrCounter <= WrCounter + 1; + WrPointer <= WrPointer + 1; + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.08: Acknowledge Generator +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (!WriteActive) begin + if (BitCounter == 8) begin + if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin + SDA_DO <= 0; + SDA_OE <= 1; + end + end + if (BitCounter == 9) begin + BitCounter <= 0; + + if (!RdCycle) begin + SDA_DO <= 0; + SDA_OE <= 0; + end + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.09: Acknowledge Detect +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + if (RdCycle & (BitCounter == 8)) begin + if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1; + end + end + + always @(negedge SCL) MACK_Rcvd <= 0; + +// ------------------------------------------------------------------------------------------------------- +// 1.10: Write Cycle Timer +// ------------------------------------------------------------------------------------------------------- + + always @(posedge STOP_Rcvd) begin + if (WrCycle & (WP == 0) & (WrCounter > 0)) begin + WriteActive = 1; + #(tWC); + WriteActive = 0; + end + end + + always @(posedge STOP_Rcvd) begin + #(1.0); + STOP_Rcvd = 0; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.11: Write Cycle Processor +// ------------------------------------------------------------------------------------------------------- + + always @(posedge WriteActive) begin + for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin + PageAddress = StartAddress[02:00] + LoopIndex; + + MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]]; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.12: Read Data Multiplexor +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (BitCounter == 8) begin + if (WrCycle & ADDR_Rcvd) begin + RdPointer <= StartAddress + WrPointer + 1; + end + if (RdCycle) begin + RdPointer <= RdPointer + 1; + end + end + end + + assign RdDataByte = MemoryBlock[RdPointer[07:00]]; + +// ------------------------------------------------------------------------------------------------------- +// 1.13: Read Data Processor +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (RdCycle) begin + if (BitCounter == 8) begin + SDA_DO <= 0; + SDA_OE <= 0; + end + else if (BitCounter == 9) begin + SDA_DO <= RdDataByte[07]; + + if (MACK_Rcvd) SDA_OE <= 1; + end + else begin + SDA_DO <= RdDataByte[7-BitCounter]; + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.14: SDA Data I/O Buffer +// ------------------------------------------------------------------------------------------------------- + + bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd); + + assign SDA_DriveEnable = !SDA_DO & SDA_OE; + always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable; + + +// ******************************************************************************************************* +// ** DEBUG LOGIC ** +// ******************************************************************************************************* +// ------------------------------------------------------------------------------------------------------- +// 2.01: Memory Data Bytes +// ------------------------------------------------------------------------------------------------------- + + wire [07:00] MemoryByte00 = MemoryBlock[00]; + wire [07:00] MemoryByte01 = MemoryBlock[01]; + wire [07:00] MemoryByte02 = MemoryBlock[02]; + wire [07:00] MemoryByte03 = MemoryBlock[03]; + wire [07:00] MemoryByte04 = MemoryBlock[04]; + wire [07:00] MemoryByte05 = MemoryBlock[05]; + wire [07:00] MemoryByte06 = MemoryBlock[06]; + wire [07:00] MemoryByte07 = MemoryBlock[07]; + + wire [07:00] MemoryByte08 = MemoryBlock[08]; + wire [07:00] MemoryByte09 = MemoryBlock[09]; + wire [07:00] MemoryByte0A = MemoryBlock[10]; + wire [07:00] MemoryByte0B = MemoryBlock[11]; + wire [07:00] MemoryByte0C = MemoryBlock[12]; + wire [07:00] MemoryByte0D = MemoryBlock[13]; + wire [07:00] MemoryByte0E = MemoryBlock[14]; + wire [07:00] MemoryByte0F = MemoryBlock[15]; + +// ------------------------------------------------------------------------------------------------------- +// 2.02: Write Data Buffer +// ------------------------------------------------------------------------------------------------------- + + wire [07:00] WriteData_0 = WrDataByte[00]; + wire [07:00] WriteData_1 = WrDataByte[01]; + wire [07:00] WriteData_2 = WrDataByte[02]; + wire [07:00] WriteData_3 = WrDataByte[03]; + wire [07:00] WriteData_4 = WrDataByte[04]; + wire [07:00] WriteData_5 = WrDataByte[05]; + wire [07:00] WriteData_6 = WrDataByte[06]; + wire [07:00] WriteData_7 = WrDataByte[07]; + + +// ******************************************************************************************************* +// ** TIMING CHECKS ** +// ******************************************************************************************************* + + wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0); + + specify + specparam + tHI = 600, // SCL pulse width - high + tLO = 1300, // SCL pulse width - low + tSU_STA = 600, // SCL to SDA setup time + tHD_STA = 600, // SCL to SDA hold time + tSU_DAT = 100, // SDA to SCL setup time + tSU_STO = 600; // SCL to SDA setup time + + $width (posedge SCL, tHI); + $width (negedge SCL, tLO); + + $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA); + $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT); + $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO); + + $hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA); + endspecify + +endmodule diff --git a/usrp2/models/M24LC02B.v b/usrp2/models/M24LC02B.v new file mode 100644 index 000000000..4d9e2c6e2 --- /dev/null +++ b/usrp2/models/M24LC02B.v @@ -0,0 +1,455 @@ +// ******************************************************************************************************* +// ** ** +// ** M24LC02B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** +// ** ** +// ******************************************************************************************************* +// ** ** +// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING ** +// ** ALL RIGHTS RESERVED ** +// ** ** +// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR ** +// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS ** +// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN ** +// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. ** +// ** ** +// ******************************************************************************************************* +// ** Revision : 1.1 ** +// ** Modified Date : 07/19/2004 ** +// ** Revision History: ** +// ** ** +// ** 02/01/2003: Initial design ** +// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. ** +// ** ** +// ******************************************************************************************************* +// ** TABLE OF CONTENTS ** +// ******************************************************************************************************* +// **---------------------------------------------------------------------------------------------------** +// ** DECLARATIONS ** +// **---------------------------------------------------------------------------------------------------** +// **---------------------------------------------------------------------------------------------------** +// ** INITIALIZATION ** +// **---------------------------------------------------------------------------------------------------** +// **---------------------------------------------------------------------------------------------------** +// ** CORE LOGIC ** +// **---------------------------------------------------------------------------------------------------** +// ** 1.01: START Bit Detection ** +// ** 1.02: STOP Bit Detection ** +// ** 1.03: Input Shift Register ** +// ** 1.04: Input Bit Counter ** +// ** 1.05: Control Byte Register ** +// ** 1.06: Byte Address Register ** +// ** 1.07: Write Data Buffer ** +// ** 1.08: Acknowledge Generator ** +// ** 1.09: Acknowledge Detect ** +// ** 1.10: Write Cycle Timer ** +// ** 1.11: Write Cycle Processor ** +// ** 1.12: Read Data Multiplexor ** +// ** 1.13: Read Data Processor ** +// ** 1.14: SDA Data I/O Buffer ** +// ** ** +// **---------------------------------------------------------------------------------------------------** +// ** DEBUG LOGIC ** +// **---------------------------------------------------------------------------------------------------** +// ** 2.01: Memory Data Bytes ** +// ** 2.02: Write Data Buffer ** +// ** ** +// **---------------------------------------------------------------------------------------------------** +// ** TIMING CHECKS ** +// **---------------------------------------------------------------------------------------------------** +// ** ** +// ******************************************************************************************************* + + +`timescale 1ns/10ps + +module M24LC02B (A0, A1, A2, WP, SDA, SCL, RESET); + + input A0; // unconnected pin + input A1; // unconnected pin + input A2; // unconnected pin + + input WP; // write protect pin + + inout SDA; // serial data I/O + input SCL; // serial data clock + + input RESET; // system reset + + +// ******************************************************************************************************* +// ** DECLARATIONS ** +// ******************************************************************************************************* + + reg SDA_DO; // serial data - output + reg SDA_OE; // serial data - output enable + + wire SDA_DriveEnable; // serial data output enable + reg SDA_DriveEnableDlyd; // serial data output enable - delayed + + reg [03:00] BitCounter; // serial bit counter + + reg START_Rcvd; // START bit received flag + reg STOP_Rcvd; // STOP bit received flag + reg CTRL_Rcvd; // control byte received flag + reg ADDR_Rcvd; // byte address received flag + reg MACK_Rcvd; // master acknowledge received flag + + reg WrCycle; // memory write cycle + reg RdCycle; // memory read cycle + + reg [07:00] ShiftRegister; // input data shift register + + reg [07:00] ControlByte; // control byte register + wire RdWrBit; // read/write control bit + + reg [07:00] StartAddress; // memory access starting address + reg [02:00] PageAddress; // memory page address + + reg [07:00] WrDataByte [0:7]; // memory write data buffer + wire [07:00] RdDataByte; // memory read data + + reg [15:00] WrCounter; // write buffer counter + + reg [02:00] WrPointer; // write buffer pointer + reg [07:00] RdPointer; // read address pointer + + reg WriteActive; // memory write cycle active + + reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array + + integer LoopIndex; // iterative loop index + + integer tAA; // timing parameter + integer tWC; // timing parameter + + +// ******************************************************************************************************* +// ** INITIALIZATION ** +// ******************************************************************************************************* + + initial tAA = 900; // SCL to SDA output delay + initial tWC = 5000000; // memory write cycle time + + initial begin + SDA_DO = 0; + SDA_OE = 0; + end + + initial begin + START_Rcvd = 0; + STOP_Rcvd = 0; + CTRL_Rcvd = 0; + ADDR_Rcvd = 0; + MACK_Rcvd = 0; + end + + initial begin + BitCounter = 0; + ControlByte = 0; + end + + initial begin + WrCycle = 0; + RdCycle = 0; + + WriteActive = 0; + end + + +// ******************************************************************************************************* +// ** CORE LOGIC ** +// ******************************************************************************************************* +// ------------------------------------------------------------------------------------------------------- +// 1.01: START Bit Detection +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SDA) begin + if (SCL == 1) begin + START_Rcvd <= 1; + STOP_Rcvd <= 0; + CTRL_Rcvd <= 0; + ADDR_Rcvd <= 0; + MACK_Rcvd <= 0; + + WrCycle <= #1 0; + RdCycle <= #1 0; + + BitCounter <= 0; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.02: STOP Bit Detection +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SDA) begin + if (SCL == 1) begin + START_Rcvd <= 0; + STOP_Rcvd <= 1; + CTRL_Rcvd <= 0; + ADDR_Rcvd <= 0; + MACK_Rcvd <= 0; + + WrCycle <= #1 0; + RdCycle <= #1 0; + + BitCounter <= 10; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.03: Input Shift Register +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + ShiftRegister[00] <= SDA; + ShiftRegister[01] <= ShiftRegister[00]; + ShiftRegister[02] <= ShiftRegister[01]; + ShiftRegister[03] <= ShiftRegister[02]; + ShiftRegister[04] <= ShiftRegister[03]; + ShiftRegister[05] <= ShiftRegister[04]; + ShiftRegister[06] <= ShiftRegister[05]; + ShiftRegister[07] <= ShiftRegister[06]; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.04: Input Bit Counter +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + if (BitCounter < 10) BitCounter <= BitCounter + 1; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.05: Control Byte Register +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (START_Rcvd & (BitCounter == 8)) begin + if (!WriteActive & (ShiftRegister[07:04] == 4'b1010)) begin + if (ShiftRegister[00] == 0) WrCycle <= 1; + if (ShiftRegister[00] == 1) RdCycle <= 1; + + ControlByte <= ShiftRegister[07:00]; + + CTRL_Rcvd <= 1; + end + + START_Rcvd <= 0; + end + end + + assign RdWrBit = ControlByte[00]; + +// ------------------------------------------------------------------------------------------------------- +// 1.06: Byte Address Register +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (CTRL_Rcvd & (BitCounter == 8)) begin + if (RdWrBit == 0) begin + StartAddress <= ShiftRegister[07:00]; + RdPointer <= ShiftRegister[07:00]; + + ADDR_Rcvd <= 1; + end + + WrCounter <= 0; + WrPointer <= 0; + + CTRL_Rcvd <= 0; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.07: Write Data Buffer +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (ADDR_Rcvd & (BitCounter == 8)) begin + if ((WP == 0) & (RdWrBit == 0)) begin + WrDataByte[WrPointer] <= ShiftRegister[07:00]; + + WrCounter <= WrCounter + 1; + WrPointer <= WrPointer + 1; + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.08: Acknowledge Generator +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (!WriteActive) begin + if (BitCounter == 8) begin + if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin + SDA_DO <= 0; + SDA_OE <= 1; + end + end + if (BitCounter == 9) begin + BitCounter <= 0; + + if (!RdCycle) begin + SDA_DO <= 0; + SDA_OE <= 0; + end + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.09: Acknowledge Detect +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + if (RdCycle & (BitCounter == 8)) begin + if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1; + end + end + + always @(negedge SCL) MACK_Rcvd <= 0; + +// ------------------------------------------------------------------------------------------------------- +// 1.10: Write Cycle Timer +// ------------------------------------------------------------------------------------------------------- + + always @(posedge STOP_Rcvd) begin + if (WrCycle & (WP == 0) & (WrCounter > 0)) begin + WriteActive = 1; + #(tWC); + WriteActive = 0; + end + end + + always @(posedge STOP_Rcvd) begin + #(1.0); + STOP_Rcvd = 0; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.11: Write Cycle Processor +// ------------------------------------------------------------------------------------------------------- + + always @(posedge WriteActive) begin + for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin + PageAddress = StartAddress[02:00] + LoopIndex; + + MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]]; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.12: Read Data Multiplexor +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (BitCounter == 8) begin + if (WrCycle & ADDR_Rcvd) begin + RdPointer <= StartAddress + WrPointer + 1; + end + if (RdCycle) begin + RdPointer <= RdPointer + 1; + end + end + end + + assign RdDataByte = MemoryBlock[RdPointer[07:00]]; + +// ------------------------------------------------------------------------------------------------------- +// 1.13: Read Data Processor +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (RdCycle) begin + if (BitCounter == 8) begin + SDA_DO <= 0; + SDA_OE <= 0; + end + else if (BitCounter == 9) begin + SDA_DO <= RdDataByte[07]; + + if (MACK_Rcvd) SDA_OE <= 1; + end + else begin + SDA_DO <= RdDataByte[7-BitCounter]; + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.14: SDA Data I/O Buffer +// ------------------------------------------------------------------------------------------------------- + + bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd); + + assign SDA_DriveEnable = !SDA_DO & SDA_OE; + always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable; + + +// ******************************************************************************************************* +// ** DEBUG LOGIC ** +// ******************************************************************************************************* +// ------------------------------------------------------------------------------------------------------- +// 2.01: Memory Data Bytes +// ------------------------------------------------------------------------------------------------------- + + wire [07:00] MemoryByte00 = MemoryBlock[00]; + wire [07:00] MemoryByte01 = MemoryBlock[01]; + wire [07:00] MemoryByte02 = MemoryBlock[02]; + wire [07:00] MemoryByte03 = MemoryBlock[03]; + wire [07:00] MemoryByte04 = MemoryBlock[04]; + wire [07:00] MemoryByte05 = MemoryBlock[05]; + wire [07:00] MemoryByte06 = MemoryBlock[06]; + wire [07:00] MemoryByte07 = MemoryBlock[07]; + + wire [07:00] MemoryByte08 = MemoryBlock[08]; + wire [07:00] MemoryByte09 = MemoryBlock[09]; + wire [07:00] MemoryByte0A = MemoryBlock[10]; + wire [07:00] MemoryByte0B = MemoryBlock[11]; + wire [07:00] MemoryByte0C = MemoryBlock[12]; + wire [07:00] MemoryByte0D = MemoryBlock[13]; + wire [07:00] MemoryByte0E = MemoryBlock[14]; + wire [07:00] MemoryByte0F = MemoryBlock[15]; + +// ------------------------------------------------------------------------------------------------------- +// 2.02: Write Data Buffer +// ------------------------------------------------------------------------------------------------------- + + wire [07:00] WriteData_0 = WrDataByte[00]; + wire [07:00] WriteData_1 = WrDataByte[01]; + wire [07:00] WriteData_2 = WrDataByte[02]; + wire [07:00] WriteData_3 = WrDataByte[03]; + wire [07:00] WriteData_4 = WrDataByte[04]; + wire [07:00] WriteData_5 = WrDataByte[05]; + wire [07:00] WriteData_6 = WrDataByte[06]; + wire [07:00] WriteData_7 = WrDataByte[07]; + + +// ******************************************************************************************************* +// ** TIMING CHECKS ** +// ******************************************************************************************************* + + wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0); + + specify + specparam + tHI = 600, // SCL pulse width - high + tLO = 1300, // SCL pulse width - low + tSU_STA = 600, // SCL to SDA setup time + tHD_STA = 600, // SCL to SDA hold time + tSU_DAT = 100, // SDA to SCL setup time + tSU_STO = 600; // SCL to SDA setup time + + $width (posedge SCL, tHI); + $width (negedge SCL, tLO); + + $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA); + $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT); + $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO); + + $hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA); + endspecify + +endmodule diff --git a/usrp2/models/MULT18X18S.v b/usrp2/models/MULT18X18S.v new file mode 100644 index 000000000..5d39eeaa6 --- /dev/null +++ b/usrp2/models/MULT18X18S.v @@ -0,0 +1,20 @@ + +// Model of the Xilinx mult18x18s for signed 18x18 bit multiplies, +// As in the Spartan 3 series + +module MULT18X18S + (output reg signed [35:0] P, + input signed [17:0] A, + input signed [17:0] B, + input C, // Clock + input CE, // Clock Enable + input R // Synchronous Reset + ); + + always @(posedge C) + if(R) + P <= 36'sd0; + else if(CE) + P <= A * B; + +endmodule // MULT18X18S diff --git a/usrp2/models/RAMB16_S36_S36.v b/usrp2/models/RAMB16_S36_S36.v new file mode 100644 index 000000000..f1a92c7ce --- /dev/null +++ b/usrp2/models/RAMB16_S36_S36.v @@ -0,0 +1,2194 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S36_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DOA; + output [3:0] DOPA; + reg [31:0] doa_out; + reg [3:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31; + wire dopa0_out, dopa1_out, dopa2_out, dopa3_out; + + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [31:0] dia_int; + wire [3:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[31:0]; + assign dopa_out = INIT_A[35:32]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_doa_out8 (doa_out8, doa_out[8]); + buf b_doa_out9 (doa_out9, doa_out[9]); + buf b_doa_out10 (doa_out10, doa_out[10]); + buf b_doa_out11 (doa_out11, doa_out[11]); + buf b_doa_out12 (doa_out12, doa_out[12]); + buf b_doa_out13 (doa_out13, doa_out[13]); + buf b_doa_out14 (doa_out14, doa_out[14]); + buf b_doa_out15 (doa_out15, doa_out[15]); + buf b_doa_out16 (doa_out16, doa_out[16]); + buf b_doa_out17 (doa_out17, doa_out[17]); + buf b_doa_out18 (doa_out18, doa_out[18]); + buf b_doa_out19 (doa_out19, doa_out[19]); + buf b_doa_out20 (doa_out20, doa_out[20]); + buf b_doa_out21 (doa_out21, doa_out[21]); + buf b_doa_out22 (doa_out22, doa_out[22]); + buf b_doa_out23 (doa_out23, doa_out[23]); + buf b_doa_out24 (doa_out24, doa_out[24]); + buf b_doa_out25 (doa_out25, doa_out[25]); + buf b_doa_out26 (doa_out26, doa_out[26]); + buf b_doa_out27 (doa_out27, doa_out[27]); + buf b_doa_out28 (doa_out28, doa_out[28]); + buf b_doa_out29 (doa_out29, doa_out[29]); + buf b_doa_out30 (doa_out30, doa_out[30]); + buf b_doa_out31 (doa_out31, doa_out[31]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dopa_out1 (dopa_out1, dopa_out[1]); + buf b_dopa_out2 (dopa_out2, dopa_out[2]); + buf b_dopa_out3 (dopa_out3, dopa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_doa8 (DOA[8], doa_out8); + buf b_doa9 (DOA[9], doa_out9); + buf b_doa10 (DOA[10], doa_out10); + buf b_doa11 (DOA[11], doa_out11); + buf b_doa12 (DOA[12], doa_out12); + buf b_doa13 (DOA[13], doa_out13); + buf b_doa14 (DOA[14], doa_out14); + buf b_doa15 (DOA[15], doa_out15); + buf b_doa16 (DOA[16], doa_out16); + buf b_doa17 (DOA[17], doa_out17); + buf b_doa18 (DOA[18], doa_out18); + buf b_doa19 (DOA[19], doa_out19); + buf b_doa20 (DOA[20], doa_out20); + buf b_doa21 (DOA[21], doa_out21); + buf b_doa22 (DOA[22], doa_out22); + buf b_doa23 (DOA[23], doa_out23); + buf b_doa24 (DOA[24], doa_out24); + buf b_doa25 (DOA[25], doa_out25); + buf b_doa26 (DOA[26], doa_out26); + buf b_doa27 (DOA[27], doa_out27); + buf b_doa28 (DOA[28], doa_out28); + buf b_doa29 (DOA[29], doa_out29); + buf b_doa30 (DOA[30], doa_out30); + buf b_doa31 (DOA[31], doa_out31); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dopa1 (DOPA[1], dopa_out1); + buf b_dopa2 (DOPA[2], dopa_out2); + buf b_dopa3 (DOPA[3], dopa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dia_8 (dia_int[8], DIA[8]); + buf b_dia_9 (dia_int[9], DIA[9]); + buf b_dia_10 (dia_int[10], DIA[10]); + buf b_dia_11 (dia_int[11], DIA[11]); + buf b_dia_12 (dia_int[12], DIA[12]); + buf b_dia_13 (dia_int[13], DIA[13]); + buf b_dia_14 (dia_int[14], DIA[14]); + buf b_dia_15 (dia_int[15], DIA[15]); + buf b_dia_16 (dia_int[16], DIA[16]); + buf b_dia_17 (dia_int[17], DIA[17]); + buf b_dia_18 (dia_int[18], DIA[18]); + buf b_dia_19 (dia_int[19], DIA[19]); + buf b_dia_20 (dia_int[20], DIA[20]); + buf b_dia_21 (dia_int[21], DIA[21]); + buf b_dia_22 (dia_int[22], DIA[22]); + buf b_dia_23 (dia_int[23], DIA[23]); + buf b_dia_24 (dia_int[24], DIA[24]); + buf b_dia_25 (dia_int[25], DIA[25]); + buf b_dia_26 (dia_int[26], DIA[26]); + buf b_dia_27 (dia_int[27], DIA[27]); + buf b_dia_28 (dia_int[28], DIA[28]); + buf b_dia_29 (dia_int[29], DIA[29]); + buf b_dia_30 (dia_int[30], DIA[30]); + buf b_dia_31 (dia_int[31], DIA[31]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_dipa_1 (dipa_int[1], DIPA[1]); + buf b_dipa_2 (dipa_int[2], DIPA[2]); + buf b_dipa_3 (dipa_int[3], DIPA[3]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 32; + assign data_addra_reg = addra_reg * 32; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addra_int = 16384 + addra_int * 4; + assign parity_addra_reg = 16384 + addra_reg * 4; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 32'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 32'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 32'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 32'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 32'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 32'bX; + end + data_collision_b_a[0] <= 0; + end + + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 4'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 4'bX; + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dopb_out <= 4'bX; + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + doa_out[8] <= SRVAL_A[8]; + doa_out[9] <= SRVAL_A[9]; + doa_out[10] <= SRVAL_A[10]; + doa_out[11] <= SRVAL_A[11]; + doa_out[12] <= SRVAL_A[12]; + doa_out[13] <= SRVAL_A[13]; + doa_out[14] <= SRVAL_A[14]; + doa_out[15] <= SRVAL_A[15]; + doa_out[16] <= SRVAL_A[16]; + doa_out[17] <= SRVAL_A[17]; + doa_out[18] <= SRVAL_A[18]; + doa_out[19] <= SRVAL_A[19]; + doa_out[20] <= SRVAL_A[20]; + doa_out[21] <= SRVAL_A[21]; + doa_out[22] <= SRVAL_A[22]; + doa_out[23] <= SRVAL_A[23]; + doa_out[24] <= SRVAL_A[24]; + doa_out[25] <= SRVAL_A[25]; + doa_out[26] <= SRVAL_A[26]; + doa_out[27] <= SRVAL_A[27]; + doa_out[28] <= SRVAL_A[28]; + doa_out[29] <= SRVAL_A[29]; + doa_out[30] <= SRVAL_A[30]; + doa_out[31] <= SRVAL_A[31]; + dopa_out[0] <= SRVAL_A[32]; + dopa_out[1] <= SRVAL_A[33]; + dopa_out[2] <= SRVAL_A[34]; + dopa_out[3] <= SRVAL_A[35]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + doa_out[16] <= mem[data_addra_int + 16]; + doa_out[17] <= mem[data_addra_int + 17]; + doa_out[18] <= mem[data_addra_int + 18]; + doa_out[19] <= mem[data_addra_int + 19]; + doa_out[20] <= mem[data_addra_int + 20]; + doa_out[21] <= mem[data_addra_int + 21]; + doa_out[22] <= mem[data_addra_int + 22]; + doa_out[23] <= mem[data_addra_int + 23]; + doa_out[24] <= mem[data_addra_int + 24]; + doa_out[25] <= mem[data_addra_int + 25]; + doa_out[26] <= mem[data_addra_int + 26]; + doa_out[27] <= mem[data_addra_int + 27]; + doa_out[28] <= mem[data_addra_int + 28]; + doa_out[29] <= mem[data_addra_int + 29]; + doa_out[30] <= mem[data_addra_int + 30]; + doa_out[31] <= mem[data_addra_int + 31]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + dopa_out[2] <= mem[parity_addra_int + 2]; + dopa_out[3] <= mem[parity_addra_int + 3]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + doa_out[16] <= mem[data_addra_int + 16]; + doa_out[17] <= mem[data_addra_int + 17]; + doa_out[18] <= mem[data_addra_int + 18]; + doa_out[19] <= mem[data_addra_int + 19]; + doa_out[20] <= mem[data_addra_int + 20]; + doa_out[21] <= mem[data_addra_int + 21]; + doa_out[22] <= mem[data_addra_int + 22]; + doa_out[23] <= mem[data_addra_int + 23]; + doa_out[24] <= mem[data_addra_int + 24]; + doa_out[25] <= mem[data_addra_int + 25]; + doa_out[26] <= mem[data_addra_int + 26]; + doa_out[27] <= mem[data_addra_int + 27]; + doa_out[28] <= mem[data_addra_int + 28]; + doa_out[29] <= mem[data_addra_int + 29]; + doa_out[30] <= mem[data_addra_int + 30]; + doa_out[31] <= mem[data_addra_int + 31]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + dopa_out[2] <= mem[parity_addra_int + 2]; + dopa_out[3] <= mem[parity_addra_int + 3]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[data_addra_int + 8] <= dia_int[8]; + mem[data_addra_int + 9] <= dia_int[9]; + mem[data_addra_int + 10] <= dia_int[10]; + mem[data_addra_int + 11] <= dia_int[11]; + mem[data_addra_int + 12] <= dia_int[12]; + mem[data_addra_int + 13] <= dia_int[13]; + mem[data_addra_int + 14] <= dia_int[14]; + mem[data_addra_int + 15] <= dia_int[15]; + mem[data_addra_int + 16] <= dia_int[16]; + mem[data_addra_int + 17] <= dia_int[17]; + mem[data_addra_int + 18] <= dia_int[18]; + mem[data_addra_int + 19] <= dia_int[19]; + mem[data_addra_int + 20] <= dia_int[20]; + mem[data_addra_int + 21] <= dia_int[21]; + mem[data_addra_int + 22] <= dia_int[22]; + mem[data_addra_int + 23] <= dia_int[23]; + mem[data_addra_int + 24] <= dia_int[24]; + mem[data_addra_int + 25] <= dia_int[25]; + mem[data_addra_int + 26] <= dia_int[26]; + mem[data_addra_int + 27] <= dia_int[27]; + mem[data_addra_int + 28] <= dia_int[28]; + mem[data_addra_int + 29] <= dia_int[29]; + mem[data_addra_int + 30] <= dia_int[30]; + mem[data_addra_int + 31] <= dia_int[31]; + mem[parity_addra_int + 0] <= dipa_int[0]; + mem[parity_addra_int + 1] <= dipa_int[1]; + mem[parity_addra_int + 2] <= dipa_int[2]; + mem[parity_addra_int + 3] <= dipa_int[3]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S36_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DOA; + output [3:0] DOPA; + output [31:0] DOB; + output [3:0] DOPB; + + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [31:0] doa_out = INIT_A[31:0]; + reg [3:0] dopa_out = INIT_A[35:32]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [31:0] dia_int; + wire [3:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [31:0] (DOA, doa_out); + buf b_dopa [3:0] (DOPA, dopa_out); + buf b_addra [8:0] (addra_int, ADDRA); + buf b_dia [31:0] (dia_int, DIA); + buf b_dipa [3:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 32; + assign data_addra_reg = addra_reg * 32; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 32'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 32'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 32'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 4'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg] <= 4'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 4'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + memp[addra_int] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/usrp2/models/SRL16E.v b/usrp2/models/SRL16E.v new file mode 100644 index 000000000..e71a419ac --- /dev/null +++ b/usrp2/models/SRL16E.v @@ -0,0 +1,53 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Clock Enable +// /___/ /\ Filename : SRL16E.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + + + assign Q = data[{A3, A2, A1, A0}]; + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) + begin + if (CE == 1'b1) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + end + + +endmodule + diff --git a/usrp2/models/SRLC16E.v b/usrp2/models/SRLC16E.v new file mode 100644 index 000000000..a68bbe9e9 --- /dev/null +++ b/usrp2/models/SRLC16E.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16E.v,v 1.6.158.1 2007/03/09 18:13:20 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable +// /___/ /\ Filename : SRLC16E.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module SRLC16E (Q, Q15, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q, Q15; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + wire [3:0] addr; + wire q_int; + + buf b_a3 (addr[3], A3); + buf b_a2 (addr[2], A2); + buf b_a1 (addr[1], A1); + buf b_a0 (addr[0], A0); + + buf b_q_int (q_int, data[addr]); + buf b_q (Q, q_int); + buf b_q15_int (q15_int, data[15]); + buf b_q15 (Q15, q15_int); + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) begin + if (CE == 1'b1) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + end + + +endmodule + diff --git a/usrp2/models/adc_model.v b/usrp2/models/adc_model.v new file mode 100644 index 000000000..e5a3ee0d8 --- /dev/null +++ b/usrp2/models/adc_model.v @@ -0,0 +1,48 @@ + +module adc_model + (input clk, input rst, + output [13:0] adc_a, + output adc_ovf_a, + input adc_on_a, + input adc_oe_a, + output [13:0] adc_b, + output adc_ovf_b, + input adc_on_b, + input adc_oe_b + ); + + math_real math ( ) ; + + reg [13:0] adc_a_int = 0; + reg [13:0] adc_b_int = 0; + + assign adc_a = adc_oe_a ? adc_a_int : 14'bz; + assign adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz; + assign adc_b = adc_oe_b ? adc_b_int : 14'bz; + assign adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz; + + real phase = 0; + real freq = 330000/100000000; + + real scale = 8190; // math.pow(2,13)-2; + always @(posedge clk) + if(rst) + begin + adc_a_int <= 0; + adc_b_int <= 0; + end + else + begin + if(adc_on_a) + //adc_a_int <= $rtoi(math.round(math.sin(phase*math.MATH_2_PI)*scale)) ; + adc_a_int <= adc_a_int + 3; + if(adc_on_b) + adc_b_int <= adc_b_int - 7; + //adc_b_int <= $rtoi(math.round(math.cos(phase*math.MATH_2_PI)*scale)) ; + if(phase > 1) + phase <= phase + freq - 1; + else + phase <= phase + freq; + end + +endmodule // adc_model diff --git a/usrp2/models/cpld_model.v b/usrp2/models/cpld_model.v new file mode 100644 index 000000000..c886433ae --- /dev/null +++ b/usrp2/models/cpld_model.v @@ -0,0 +1,96 @@ + +module cpld_model + (input aux_clk, input start, input mode, input done, + output dout, output reg sclk, output detached); + + reg [7:0] rom[0:65535]; + + reg [15:0] addr; + reg [7:0] data; + assign dout = data[7]; + + reg [2:0] state, bitcnt; + + localparam IDLE = 3'd0; + localparam READ = 3'd1; + localparam BIT1 = 3'd2; + localparam BIT2 = 3'd3; + localparam DONE = 3'd4; + localparam DETACHED = 3'd5; + localparam ERROR = 3'd7; + + integer i; + reg [1023:0] ROMFile; + + initial begin + for (i=0;i<65536;i=i+1) begin + rom[i] <= 32'h0; + end + if ( !$value$plusargs( "rom=%s", ROMFile ) ) + begin + $display( "Using default ROM file, 'flash.rom'" ); + ROMFile = "flash.rom"; + end + else + $display( "Using %s as ROM file.", ROMFile); + + #1 $readmemh( ROMFile,rom ); + end + + initial addr = 16'd0; + initial data = 8'd0; + initial state = IDLE; + initial bitcnt = 3'd0; + initial sclk = 1'b0; + + always @(posedge aux_clk) + case(state) + IDLE : + if(start) + if(~mode) + state <= READ; + else + state <= ERROR; + READ : + if(done) + state <= DONE; + else + begin + data <= rom[addr]; + addr <= addr + 1; + bitcnt <= 3'd0; + if(addr==16'hFFFF) + state <= ERROR; + else + state <= BIT1; + end // else: !if(start) + BIT1 : + begin + sclk <= 1'b1; + state <= BIT2; + end + BIT2 : + begin + sclk <= 1'b0; + data <= {data[6:0],1'b0}; + bitcnt <= bitcnt + 1; + if(bitcnt==7) + state <= READ; + else + state <=BIT1; + end + DONE : + begin + if(start) + state <= ERROR; + else + state <= DETACHED; + end + DETACHED : + if(start) + state <= ERROR; + endcase // case(state) + + assign detached = (state == DETACHED) || (state == IDLE); + +endmodule // cpld_model diff --git a/usrp2/models/math_real.v b/usrp2/models/math_real.v new file mode 100644 index 000000000..e30f68ee7 --- /dev/null +++ b/usrp2/models/math_real.v @@ -0,0 +1,495 @@ +/* + * This is a general recreation of the VHDL ieee.math_real package. + */ + +module math_real ; + // Constants for use below and for general reference + // TODO: Bring it out to 12 (or more???) places beyond the decimal? + localparam MATH_E = 2.7182818284; + localparam MATH_1_OVER_E = 0.3678794411; + localparam MATH_PI = 3.1415926536; + localparam MATH_2_PI = 6.2831853071; + localparam MATH_1_OVER_PI = 0.3183098861; + localparam MATH_PI_OVER_2 = 1.5707963267; + localparam MATH_PI_OVER_3 = 1.0471975511; + localparam MATH_PI_OVER_4 = 0.7853981633; + localparam MATH_3_PI_OVER_2 = 4.7123889803; + localparam MATH_LOG_OF_2 = 0.6931471805; + localparam MATH_LOG_OF_10 = 2.3025850929; + localparam MATH_LOG2_OF_E = 1.4426950408; + localparam MATH_LOG10_OF_E = 0.4342944819; + localparam MATH_SQRT_2 = 1.4142135623; + localparam MATH_1_OVER_SQRT_2= 0.7071067811; + localparam MATH_SQRT_PI = 1.7724538509; + localparam MATH_DEG_TO_RAD = 0.0174532925; + localparam MATH_RAD_TO_DEG = 57.2957795130; + + // The number of iterations to do for the Taylor series approximations + localparam EXPLOG_ITERATIONS = 19; + localparam COS_ITERATIONS = 8; + + /* Conversion Routines */ + + // Return the sign of a particular number. + function real sign ; + input real x ; + begin + sign = x < 0.0 ? 1.0 : 0.0 ; + end + endfunction + + // Return the trunc function of a number + function real trunc ; + input real x ; + begin + trunc = x - mod(x,1.0) ; + end + endfunction + + // Return the ceiling function of a number. + function real ceil ; + input real x ; + real retval ; + begin + retval = mod(x,1.0) ; + if( retval != 0.0 && x > 0.0 ) retval = x+1.0 ; + else retval = x ; + ceil = trunc(retval) ; + end + endfunction + + // Return the floor function of a number + function real floor ; + input real x ; + real retval ; + begin + retval = mod(x,1.0) ; + if( retval != 0.0 && x < 0.0 ) retval = x - 1.0 ; + else retval = x ; + floor = trunc(retval) ; + end + endfunction + + // Return the round function of a number + function real round ; + input real x ; + real retval ; + begin + retval = x > 0.0 ? x + 0.5 : x - 0.5 ; + round = trunc(retval) ; + end + endfunction + + // Return the fractional remainder of (x mod m) + function real mod ; + input real x ; + input real m ; + real retval ; + begin + retval = x ; + if( retval > m ) begin + while( retval > m ) begin + retval = retval - m ; + end + end + else begin + while( retval < -m ) begin + retval = retval + m ; + end + end + mod = retval ; + end + endfunction + + // Return the max between two real numbers + function real realmax ; + input real x ; + input real y ; + begin + realmax = x > y ? x : y ; + end + endfunction + + // Return the min between two real numbers + function real realmin ; + input real x ; + input real y ; + begin + realmin = x > y ? y : x ; + end + endfunction + + /* Random Numbers */ + + // Generate Gaussian distributed variables + function real gaussian ; + input real mean ; + input real var ; + real u1, u2, v1, v2, s ; + begin + s = 1.0 ; + while( s >= 1.0 ) begin + // Two random numbers between 0 and 1 + u1 = $random/4294967296.0 + 0.5 ; + u2 = $random/4294967296.0 + 0.5 ; + // Adjust to be between -1,1 + v1 = 2*u1-1.0 ; + v2 = 2*u2-1.0 ; + // Polar mag squared + s = (v1*v1 + v2*v2) ; + end + gaussian = mean + sqrt((-2.0*log(s))/s) * v1 * sqrt(var) ; + // gaussian2 = mean + sqrt(-2*log(s)/s)*v2 * sqrt(var) ; + end + endfunction + + /* Roots and Log Functions */ + + // Return the square root of a number + function real sqrt ; + input real x ; + real retval ; + begin + sqrt = (x == 0.0) ? 0.0 : powr(x,0.5) ; + end + endfunction + + // Return the cube root of a number + function real cbrt ; + input real x ; + real retval ; + begin + cbrt = (x == 0.0) ? 0.0 : powr(x,1.0/3.0) ; + end + endfunction + + // Return the absolute value of a real value + function real abs ; + input real x ; + begin + abs = (x > 0.0) ? x : -x ; + end + endfunction + + // Return a real value raised to an integer power + function real pow ; + input real b ; + input integer x ; + integer absx ; + real retval ; + begin + retval = 1.0 ; + absx = abs(x) ; + repeat(absx) begin + retval = b*retval ; + end + pow = x < 0 ? (1.0/retval) : retval ; + end + endfunction + + // Return a real value raised to a real power + function real powr ; + input real b ; + input real x ; + begin + powr = exp(x*log(b)) ; + end + endfunction + + // Return the evaluation of e^x where e is the natural logarithm base + // NOTE: This is the Taylor series expansion of e^x + function real exp ; + input real x ; + real retval ; + integer i ; + real nm1_fact ; + real powm1 ; + begin + nm1_fact = 1.0 ; + powm1 = 1.0 ; + retval = 1.0 ; + for( i = 1 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin + powm1 = x*powm1 ; + nm1_fact = nm1_fact * i ; + retval = retval + powm1/nm1_fact ; + end + exp = retval ; + end + endfunction + + // Return the evaluation log(x) + function real log ; + input real x ; + integer i ; + real whole ; + real xm1oxp1 ; + real retval ; + real newx ; + begin + retval = 0.0 ; + whole = 0.0 ; + newx = x ; + while( newx > MATH_E ) begin + whole = whole + 1.0 ; + newx = newx / MATH_E ; + end + xm1oxp1 = (newx-1.0)/(newx+1.0) ; + for( i = 0 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin + retval = retval + pow(xm1oxp1,2*i+1)/(2.0*i+1.0) ; + end + log = whole+2.0*retval ; + end + endfunction + + // Return the evaluation ln(x) (same as log(x)) + function real ln ; + input real x ; + begin + ln = log(x) ; + end + endfunction + + // Return the evaluation log_2(x) + function real log2 ; + input real x ; + begin + log2 = log(x)/MATH_LOG_OF_2 ; + end + endfunction + + function real log10 ; + input real x ; + begin + log10 = log(x)/MATH_LOG_OF_10 ; + end + endfunction + + function real log_base ; + input real x ; + input real b ; + begin + log_base = log(x)/log(b) ; + end + endfunction + + /* Trigonometric Functions */ + + // Internal function to reduce a value to be between [-pi:pi] + function real reduce ; + input real x ; + real retval ; + begin + retval = x ; + while( abs(retval) > MATH_PI ) begin + retval = retval > MATH_PI ? + (retval - MATH_2_PI) : + (retval + MATH_2_PI) ; + end + reduce = retval ; + end + endfunction + + // Return the cos of a number in radians + function real cos ; + input real x ; + integer i ; + integer sign ; + real newx ; + real retval ; + real xsqnm1 ; + real twonm1fact ; + begin + newx = reduce(x) ; + xsqnm1 = 1.0 ; + twonm1fact = 1.0 ; + retval = 1.0 ; + for( i = 1 ; i < COS_ITERATIONS ; i = i + 1 ) begin + sign = -2*(i % 2)+1 ; + xsqnm1 = xsqnm1*newx*newx ; + twonm1fact = twonm1fact * (2.0*i) * (2.0*i-1.0) ; + retval = retval + sign*(xsqnm1/twonm1fact) ; + end + cos = retval ; + end + endfunction + + // Return the sin of a number in radians + function real sin ; + input real x ; + begin + sin = cos(x - MATH_PI_OVER_2) ; + end + endfunction + + // Return the tan of a number in radians + function real tan ; + input real x ; + begin + tan = sin(x) / cos(x) ; + end + endfunction + + // Return the arcsin in radians of a number + function real arcsin ; + input real x ; + begin + arcsin = 2.0*arctan(x/(1.0+sqrt(1.0-x*x))) ; + end + endfunction + + // Return the arccos in radians of a number + function real arccos ; + input real x ; + begin + arccos = MATH_PI_OVER_2-arcsin(x) ; + end + endfunction + + // Return the arctan in radians of a number + // TODO: Make sure this REALLY does work as it is supposed to! + function real arctan ; + input real x ; + real retval ; + real y ; + real newx ; + real twoiotwoip1 ; + integer i ; + integer mult ; + begin + retval = 1.0 ; + twoiotwoip1 = 1.0 ; + mult = 1 ; + newx = abs(x) ; + while( newx > 1.0 ) begin + mult = mult*2 ; + newx = newx/(1.0+sqrt(1.0+newx*newx)) ; + end + y = 1.0 ; + for( i = 1 ; i < 2*COS_ITERATIONS ; i = i + 1 ) begin + y = y*((newx*newx)/(1+newx*newx)) ; + twoiotwoip1 = twoiotwoip1 * (2.0*i)/(2.0*i+1.0) ; + retval = retval + twoiotwoip1*y ; + end + retval = retval * (newx/(1+newx*newx)) ; + retval = retval * mult ; + + arctan = (x > 0.0) ? retval : -retval ; + end + endfunction + + // Return the arctan in radians of a ratio x/y + // TODO: Test to make sure this works as it is supposed to! + function real arctan_xy ; + input real x ; + input real y ; + real retval ; + begin + retval = 0.0 ; + if( x < 0.0 ) retval = MATH_PI - arctan(-abs(y)/x) ; + else if( x > 0.0 ) retval = arctan(abs(y)/x) ; + else if( x == 0.0 ) retval = MATH_PI_OVER_2 ; + arctan_xy = (y < 0.0) ? -retval : retval ; + end + endfunction + + /* Hyperbolic Functions */ + + // Return the sinh of a number + function real sinh ; + input real x ; + begin + sinh = (exp(x) - exp(-x))/2.0 ; + end + endfunction + + // Return the cosh of a number + function real cosh ; + input real x ; + begin + cosh = (exp(x) + exp(-x))/2.0 ; + end + endfunction + + // Return the tanh of a number + function real tanh ; + input real x ; + real e2x ; + begin + e2x = exp(2.0*x) ; + tanh = (e2x+1.0)/(e2x-1.0) ; + end + endfunction + + // Return the arcsinh of a number + function real arcsinh ; + input real x ; + begin + arcsinh = log(x+sqrt(x*x+1.0)) ; + end + endfunction + + // Return the arccosh of a number + function real arccosh ; + input real x ; + begin + arccosh = ln(x+sqrt(x*x-1.0)) ; + end + endfunction + + // Return the arctanh of a number + function real arctanh ; + input real x ; + begin + arctanh = 0.5*ln((1.0+x)/(1.0-x)) ; + end + endfunction + /* + initial begin + $display( "cos(MATH_PI_OVER_3): %f", cos(MATH_PI_OVER_3) ) ; + $display( "sin(MATH_PI_OVER_3): %f", sin(MATH_PI_OVER_3) ) ; + $display( "sign(-10): %f", sign(-10) ) ; + $display( "realmax(MATH_PI,MATH_E): %f", realmax(MATH_PI,MATH_E) ) ; + $display( "realmin(MATH_PI,MATH_E): %f", realmin(MATH_PI,MATH_E) ) ; + $display( "mod(MATH_PI,MATH_E): %f", mod(MATH_PI,MATH_E) ) ; + $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ; + $display( "ceil(4.0): %f", ceil(4.0) ) ; + $display( "ceil(3.99999999999999): %f", ceil(3.99999999999999) ) ; + $display( "pow(MATH_PI,2): %f", pow(MATH_PI,2) ) ; + $display( "gaussian(1.0,1.0): %f", gaussian(1.0,1.0) ) ; + $display( "round(MATH_PI): %f", round(MATH_PI) ) ; + $display( "trunc(-MATH_PI): %f", trunc(-MATH_PI) ) ; + $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ; + $display( "floor(MATH_PI): %f", floor(MATH_PI) ) ; + $display( "round(e): %f", round(MATH_E)) ; + $display( "ceil(-e): %f", ceil(-MATH_E)) ; + $display( "exp(MATH_PI): %f", exp(MATH_PI) ) ; + $display( "log2(MATH_PI): %f", log2(MATH_PI) ) ; + $display( "log_base(pow(2,32),2): %f", log_base(pow(2,32),2) ) ; + $display( "ln(0.1): %f", log(0.1) ) ; + $display( "cbrt(7): %f", cbrt(7) ) ; + $display( "cos(MATH_2_PI): %f", cos(20*MATH_2_PI) ) ; + $display( "sin(-MATH_2_PI): %f", sin(-50*MATH_2_PI) ) ; + $display( "sinh(MATH_E): %f", sinh(MATH_E) ) ; + $display( "cosh(MATH_2_PI): %f", cosh(MATH_2_PI) ) ; + $display( "arctan_xy(-4,3): %f", arctan_xy(-4,3) ) ; + $display( "arctan(MATH_PI): %f", arctan(MATH_PI) ) ; + $display( "arctan(-MATH_E/2): %f", arctan(-MATH_E/2) ) ; + $display( "arctan(MATH_PI_OVER_2): %f", arctan(MATH_PI_OVER_2) ) ; + $display( "arctan(1/7) = %f", arctan(1.0/7.0) ) ; + $display( "arctan(3/79) = %f", arctan(3.0/79.0) ) ; + $display( "pi/4 ?= %f", 5*arctan(1.0/7.0)+2*arctan(3.0/79.0) ) ; + $display( "arcsin(1.0): %f", arcsin(1.0) ) ; + $display( "cos(pi/2): %f", cos(MATH_PI_OVER_2)) ; + $display( "arccos(cos(pi/2)): %f", arccos(cos(MATH_PI_OVER_2)) ) ; + $display( "cos(0): %f", cos(0) ) ; + $display( "cos(MATH_PI_OVER_4): %f", cos(MATH_PI_OVER_4) ) ; + $display( "cos(MATH_PI_OVER_2): %f", cos(MATH_PI_OVER_2) ) ; + $display( "cos(3*MATH_PI_OVER_4): %f", cos(3*MATH_PI_OVER_4) ) ; + $display( "cos(MATH_PI): %f", cos(MATH_PI) ) ; + $display( "cos(5*MATH_PI_OVER_4): %f", cos(5*MATH_PI_OVER_4) ) ; + $display( "cos(6*MATH_PI_OVER_4): %f", cos(6*MATH_PI_OVER_4) ) ; + $display( "cos(7*MATH_PI_OVER_4): %f", cos(7*MATH_PI_OVER_4) ) ; + $display( "cos(8*MATH_PI_OVER_4): %f", cos(8*MATH_PI_OVER_4) ) ; + end*/ + +endmodule diff --git a/usrp2/models/miim_model.v b/usrp2/models/miim_model.v new file mode 100644 index 000000000..936d99a80 --- /dev/null +++ b/usrp2/models/miim_model.v @@ -0,0 +1,14 @@ + +// Skeleton PHY interface simulator + +module miim_model(input mdc_i, + inout mdio, + input phy_resetn_i, + input phy_clk_i, + output phy_intn_o, + output [2:0] speed_o); + + assign phy_intn_o = 1; // No interrupts + assign speed_o = 3'b100; // 1G mode + +endmodule // miim_model diff --git a/usrp2/models/phy_sim.v b/usrp2/models/phy_sim.v new file mode 100644 index 000000000..b3de19b04 --- /dev/null +++ b/usrp2/models/phy_sim.v @@ -0,0 +1,113 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_sim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Phy_sim.v,v $ +// Revision 1.3 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.2 2006/01/19 14:07:50 maverickist +// verification is complete. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +`timescale 1ns/100ps + +module phy_sim( + input Gtx_clk, // Used only in GMII mode + output Rx_clk, + output Tx_clk, // Used only in MII mode + input Tx_er, + input Tx_en, + input [7:0] Txd, + output Rx_er, + output Rx_dv, + output [7:0] Rxd, + output Crs, + output Col, + input [2:0] Speed, + input Done +); + +////////////////////////////////////////////////////////////////////// +// this file used to simulate Phy. +// generate clk and loop the Tx data to Rx data +// full duplex mode can be verified on loop mode. +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +// internal signals +////////////////////////////////////////////////////////////////////// +reg Clk_25m; // Used for 100 Mbps mode +reg Clk_2_5m; // Used for 10 Mbps mode + +//wire Rx_clk; +//wire Tx_clk; // Used only in MII mode + + initial + begin + #10; + while ( !Done ) + begin + #20 Clk_25m = 0; + #20 Clk_25m = 1; + end + end + + initial + begin + #10; + while ( !Done ) + begin + #200 Clk_2_5m = 0; + #200 Clk_2_5m = 1; + end + end + + assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; + assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; + + assign Rx_dv = Tx_en; + assign Rxd = Txd; + assign Rx_er = Tx_er; + assign Crs = Tx_en; + assign Col = 0; + +endmodule diff --git a/usrp2/models/serdes_model.v b/usrp2/models/serdes_model.v new file mode 100644 index 000000000..f10e55554 --- /dev/null +++ b/usrp2/models/serdes_model.v @@ -0,0 +1,34 @@ + +module serdes_model + (input ser_tx_clk, + input ser_tkmsb, + input ser_tklsb, + input [15:0] ser_t, + + output ser_rx_clk, + output ser_rkmsb, + output ser_rklsb, + output [15:0] ser_r, + + input even, + input error); + + wire [15:0] ser_r_odd; + wire ser_rklsb_odd, ser_rkmsb_odd; + + reg [7:0] hold_dat; + reg hold_k; + + always @(posedge ser_tx_clk) hold_k <= ser_tklsb; + always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8]; + assign ser_rklsb_odd = hold_k; + assign ser_rkmsb_odd = ser_tklsb; + assign ser_r_odd = {ser_t[7:0], hold_dat}; + + // Set outputs + assign ser_rx_clk = ser_tx_clk; + assign ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd; + assign ser_rklsb = even ? ser_tklsb : ser_rklsb_odd; + assign ser_r = error ^ (even ? ser_t : ser_r_odd); + +endmodule // serdes_model diff --git a/usrp2/models/uart_rx.v b/usrp2/models/uart_rx.v new file mode 100644 index 000000000..f698a50fe --- /dev/null +++ b/usrp2/models/uart_rx.v @@ -0,0 +1,48 @@ + + +// Simple printout of characters from the UART +// Only does 8N1, requires the baud clock + +module uart_rx (input baudclk, input rxd); + reg [8:0] sr = 9'b0; + reg [3:0] baud_ctr = 4'b0; + + /* + wire byteclk = baud_ctr[3]; + reg rxd_d1 = 0; + always @(posedge baudclk) + rxd_d1 <= rxd; + + always @(posedge baudclk) + if(rxd_d1 != rxd) + baud_ctr <= 0; + else + baud_ctr <= baud_ctr + 1; +*/ + + wire byteclk = baudclk; + + always @(posedge byteclk) + sr <= { rxd, sr[8:1] }; + + reg [3:0] state = 0; + always @(posedge byteclk) + case(state) + 0 : + if(~sr[8] & sr[7]) // found start bit + state <= 1; + 1, 2, 3, 4, 5, 6, 7, 8 : + state <= state + 1; + 9 : + begin + state <= 0; + $write("%c",sr[7:0]); + if(~sr[8]) + $display("Error, no stop bit\n"); + end + default : + state <= 0; + endcase // case(state) + +endmodule // uart_rx + diff --git a/usrp2/models/xlnx_glbl.v b/usrp2/models/xlnx_glbl.v new file mode 100644 index 000000000..662a60e35 --- /dev/null +++ b/usrp2/models/xlnx_glbl.v @@ -0,0 +1,29 @@ +module xlnx_glbl +( + GSR, + GTS +); + + //-------------------------------------------------------------------------- + // Parameters + //-------------------------------------------------------------------------- + + //-------------------------------------------------------------------------- + // IO declarations + //-------------------------------------------------------------------------- + + output GSR; + output GTS; + + //-------------------------------------------------------------------------- + // Local declarations + //-------------------------------------------------------------------------- + + //-------------------------------------------------------------------------- + // Internal declarations + //-------------------------------------------------------------------------- + + assign GSR = 0; + assign GTS = 0; + +endmodule diff --git a/usrp2/opencores/8b10b/.gitignore b/usrp2/opencores/8b10b/.gitignore new file mode 100644 index 000000000..548539d61 --- /dev/null +++ b/usrp2/opencores/8b10b/.gitignore @@ -0,0 +1,2 @@ +/dump.vcd +/a.out diff --git a/usrp2/opencores/8b10b/8b10b_a.mem b/usrp2/opencores/8b10b/8b10b_a.mem new file mode 100644 index 000000000..1761d74f6 --- /dev/null +++ b/usrp2/opencores/8b10b/8b10b_a.mem @@ -0,0 +1,268 @@ +000000000100111010001100010110 +000000001011101010010001010110 +000000010101101010001001010110 +000000011110001101111000101001 +000000100110101010000101010110 +000000101101001101110100101001 +000000110011001101101100101001 +000000111111000101100011101001 +000001000111001010000011010110 +000001001100101101110010101001 +000001010010101101101010101001 +000001011110100101111010001001 +000001100001101101100110101001 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They are from +Chuck Benz. See http://asics.chuckbenz.com + + diff --git a/usrp2/opencores/8b10b/decode_8b10b.v b/usrp2/opencores/8b10b/decode_8b10b.v new file mode 100644 index 000000000..0b2a8ac59 --- /dev/null +++ b/usrp2/opencores/8b10b/decode_8b10b.v @@ -0,0 +1,165 @@ +// Chuck Benz, Hollis, NH Copyright (c)2002 +// +// The information and description contained herein is the +// property of Chuck Benz. +// +// Permission is granted for any reuse of this information +// and description as long as this copyright notice is +// preserved. Modifications may be made as long as this +// notice is preserved. + +// per Widmer and Franaszek + +module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ; + input [9:0] datain ; + input dispin ; + output [8:0] dataout ; + output dispout ; + output code_err ; + output disp_err ; + + wire ai = datain[0] ; + wire bi = datain[1] ; + wire ci = datain[2] ; + wire di = datain[3] ; + wire ei = datain[4] ; + wire ii = datain[5] ; + wire fi = datain[6] ; + wire gi = datain[7] ; + wire hi = datain[8] ; + wire ji = datain[9] ; + + wire aeqb = (ai & bi) | (!ai & !bi) ; + wire ceqd = (ci & di) | (!ci & !di) ; + wire p22 = (ai & bi & !ci & !di) | + (ci & di & !ai & !bi) | + ( !aeqb & !ceqd) ; + wire p13 = ( !aeqb & !ci & !di) | + ( !ceqd & !ai & !bi) ; + wire p31 = ( !aeqb & ci & di) | + ( !ceqd & ai & bi) ; + + wire p40 = ai & bi & ci & di ; + wire p04 = !ai & !bi & !ci & !di ; + + wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31. + wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits + wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits + + wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 | + (ei & ii & di)) & (ei | ii | di)) ; + + // The 5B/6B decoding special cases where ABCDE != abcde + + wire p22bceeqi = p22 & bi & ci & (ei == ii) ; + wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ; + wire p13in = p13 & !ii ; + wire p31i = p31 & ii ; + wire p13dei = p13 & di & ei & ii ; + wire p22aceeqi = p22 & ai & ci & (ei == ii) ; + wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ; + wire p13en = p13 & !ei ; + wire anbnenin = !ai & !bi & !ei & !ii ; + wire abei = ai & bi & ei & ii ; + wire cdei = ci & di & ei & ii ; + wire cndnenin = !ci & !di & !ei & !ii ; + + // non-zero disparity cases: + wire p22enin = p22 & !ei & !ii ; + wire p22ei = p22 & ei & ii ; + //wire p13in = p12 & !ii ; + //wire p31i = p31 & ii ; + wire p31dnenin = p31 & !di & !ei & !ii ; + //wire p13dei = p13 & di & ei & ii ; + wire p31e = p31 & ei ; + + wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi | + p13en | abei | cndnenin ; + wire compb = p22bceeqi | p31i | p13dei | p22aceeqi | + p13en | abei | cndnenin ; + wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi | + p13en | anbnenin | cndnenin ; + wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi | + p13en | abei | cndnenin ; + wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi | + p13en | anbnenin | cndnenin ; + + wire ao = ai ^ compa ; + wire bo = bi ^ compb ; + wire co = ci ^ compc ; + wire do = di ^ compd ; + wire eo = ei ^ compe ; + + wire feqg = (fi & gi) | (!fi & !gi) ; + wire heqj = (hi & ji) | (!hi & !ji) ; + wire fghj22 = (fi & gi & !hi & !ji) | + (!fi & !gi & hi & ji) | + ( !feqg & !heqj) ; + wire fghjp13 = ( !feqg & !hi & !ji) | + ( !heqj & !fi & !gi) ; + wire fghjp31 = ( (!feqg) & hi & ji) | + ( !heqj & fi & gi) ; + + wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ; + + wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) | + (p13 & !ei & ii & gi & hi & ji) | + (p31 & ei & !ii & !gi & !hi & !ji)) ; + + wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1 + ((dispin & ci & di & !ei & !ii) | ko | + (dispin & !ci & di & !ei & !ii))) | + (!fi & gi & hi & // 0111 cases, where disp6b is 0 + (( !dispin & !ci & !di & ei & ii) | ko | + ( !dispin & ci & !di & ei & ii))) ; + + wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ; + // k28 with positive disp into fghi - .1, .2, .5, and .6 special cases + wire k28p = ! (ci | di | ei | ii) ; + wire fo = (ji & !fi & (hi | !gi | k28p)) | + (fi & !ji & (!hi | gi | !k28p)) | + (k28p & gi & hi) | + (!k28p & !gi & !hi) ; + wire go = (ji & !fi & (hi | !gi | !k28p)) | + (fi & !ji & (!hi | gi |k28p)) | + (!k28p & gi & hi) | + (k28p & !gi & !hi) ; + wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) | + (fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) | + (!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ; + + wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ; + wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ; + wire disp4p = fghjp31 ; + wire disp4n = fghjp13 ; + + assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) | + (p13 & !ei & !ii) | (p31 & ei & ii) | + (ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) | + (ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) | + (!p31 & ei & !ii & !gi & !hi & !ji) | + (!p13 & !ei & ii & gi & hi & ji) | + (((ei & ii & !gi & !hi & !ji) | + (!ei & !ii & gi & hi & ji)) & + ! ((ci & di & ei) | (!ci & !di & !ei))) | + (disp6p & disp4p) | (disp6n & disp4n) | + (ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) | + (!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) | + (fi & gi & !hi & !ji & disp6p) | + (!fi & !gi & hi & ji & disp6n) | + (ci & di & ei & ii & !fi & !gi & !hi) | + (!ci & !di & !ei & !ii & fi & gi & hi) ; + + assign dataout = {ko, ho, go, fo, eo, do, co, bo, ao} ; + + // my disp err fires for any legal codes that violate disparity, may fire for illegal codes + assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) | + (dispin & !disp6n & fi & gi) | + (dispin & ai & bi & ci) | + (dispin & !disp6n & disp4p) | + (!dispin & !disp6p & !fi & !gi) | + (!dispin & !ai & !bi & !ci) | + (!dispin & !disp6p & disp4n) | + (disp6p & disp4p) | (disp6n & disp4n)) ; + +endmodule diff --git a/usrp2/opencores/8b10b/encode_8b10b.v b/usrp2/opencores/8b10b/encode_8b10b.v new file mode 100644 index 000000000..c1f09b9ce --- /dev/null +++ b/usrp2/opencores/8b10b/encode_8b10b.v @@ -0,0 +1,120 @@ +// Chuck Benz, Hollis, NH Copyright (c)2002 +// +// The information and description contained herein is the +// property of Chuck Benz. +// +// Permission is granted for any reuse of this information +// and description as long as this copyright notice is +// preserved. Modifications may be made as long as this +// notice is preserved. + +// per Widmer and Franaszek + +module encode_8b10b (datain, dispin, dataout, dispout) ; + input [8:0] datain ; + input dispin ; // 0 = neg disp; 1 = pos disp + output [9:0] dataout ; + output dispout ; + + + wire ai = datain[0] ; + wire bi = datain[1] ; + wire ci = datain[2] ; + wire di = datain[3] ; + wire ei = datain[4] ; + wire fi = datain[5] ; + wire gi = datain[6] ; + wire hi = datain[7] ; + wire ki = datain[8] ; + + wire aeqb = (ai & bi) | (!ai & !bi) ; + wire ceqd = (ci & di) | (!ci & !di) ; + wire l22 = (ai & bi & !ci & !di) | + (ci & di & !ai & !bi) | + ( !aeqb & !ceqd) ; + wire l40 = ai & bi & ci & di ; + wire l04 = !ai & !bi & !ci & !di ; + wire l13 = ( !aeqb & !ci & !di) | + ( !ceqd & !ai & !bi) ; + wire l31 = ( !aeqb & ci & di) | + ( !ceqd & ai & bi) ; + + // The 5B/6B encoding + + wire ao = ai ; + wire bo = (bi & !l40) | l04 ; + wire co = l04 | ci | (ei & di & !ci & !bi & !ai) ; + wire do = di & ! (ai & bi & ci) ; + wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ; + wire io = (l22 & !ei) | + (ei & !di & !ci & !(ai&bi)) | // D16, D17, D18 + (ei & l40) | + (ki & ei & di & ci & !bi & !ai) | // K.28 + (ei & !di & ci & !bi & !ai) ; + + // pds16 indicates cases where d-1 is assumed + to get our encoded value + wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ; + // nds16 indicates cases where d-1 is assumed - to get our encoded value + wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ; + + // ndos6 is pds16 cases where d-1 is + yields - disp out - all of them + wire ndos6 = pd1s6 ; + // pdos6 is nds16 cases where d-1 is - yields + disp out - all but one + wire pdos6 = ki | (ei & !l22 & !l13) ; + + + // some Dx.7 and all Kx.7 cases result in run length of 5 case unless + // an alternate coding is used (referred to as Dx.A7, normal is Dx.P7) + // specifically, D11, D13, D14, D17, D18, D19. + wire alt7 = fi & gi & hi & (ki | + (dispin ? (!ei & di & l31) : (ei & !di & l13))) ; + + + wire fo = fi & ! alt7 ; + wire go = gi | (!fi & !gi & !hi) ; + wire ho = hi ; + wire jo = (!hi & (gi ^ fi)) | alt7 ; + + // nd1s4 is cases where d-1 is assumed - to get our encoded value + wire nd1s4 = fi & gi ; + // pd1s4 is cases where d-1 is assumed + to get our encoded value + wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ; + + // ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some + wire ndos4 = (!fi & !gi) ; + // pdos4 is nd1s4 cases where d-1 is - yields + disp out + wire pdos4 = fi & gi & hi ; + + // only legal K codes are K28.0->.7, K23/27/29/30.7 + // K28.0->7 is ei=di=ci=1,bi=ai=0 + // K23 is 10111 + // K27 is 11011 + // K29 is 11101 + // K30 is 11110 - so K23/27/29/30 are ei & l31 + wire illegalk = ki & + (ai | bi | !ci | !di | !ei) & // not K28.0->7 + (!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7 + + // now determine whether to do the complementing + // complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set + wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ; + + // disparity out of 5b6b is disp in with pdso6 and ndso6 + // pds16 indicates cases where d-1 is assumed + to get our encoded value + // ndos6 is cases where d-1 is + yields - disp out + // nds16 indicates cases where d-1 is assumed - to get our encoded value + // pdos6 is cases where d-1 is - yields + disp out + // disp toggles in all ndis16 cases, and all but that 1 nds16 case + + wire disp6 = dispin ^ (ndos6 | pdos6) ; + + wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ; + assign dispout = disp6 ^ (ndos4 | pdos4) ; + + assign dataout = {(jo ^ compls4), (ho ^ compls4), + (go ^ compls4), (fo ^ compls4), + (io ^ compls6), (eo ^ compls6), + (do ^ compls6), (co ^ compls6), + (bo ^ compls6), (ao ^ compls6)} ; + +endmodule diff --git a/usrp2/opencores/8b10b/validate_8b10b.v b/usrp2/opencores/8b10b/validate_8b10b.v new file mode 100644 index 000000000..926b1081d --- /dev/null +++ b/usrp2/opencores/8b10b/validate_8b10b.v @@ -0,0 +1,168 @@ +// Chuck Benz, Hollis, NH Copyright (c)2002 +// +// The information and description contained herein is the +// property of Chuck Benz. +// +// Permission is granted for any reuse of this information +// and description as long as this copyright notice is +// preserved. Modifications may be made as long as this +// notice is preserved. + +// 11-OCT-2002: updated with clearer messages, and checking decodeout + +`timescale 1ns / 1ns +module test_8b10b ; + reg [29:0] code8b10b [0:267] ; + reg [8:0] testin ; + reg dispin ; + reg [10:0] i ; + wire [9:0] testout ; + wire dispout, decodedisp, decodeerr, disperr ; + wire [8:0] decodeout ; + // My data file is 30 columns. Column 1 becomes [29], 2 becomes [28], etc.. + // code[0] is last Column (30) + // First column, [29] is K indication + // columns 2:9, [28:21], are data byte, aka 'm' and 'n' of Dm.n + // columns 10:19, [20:11] are 10b symbol if starting disparity was negative, 0 + // columns 20:29, [10:1] are 10b symbol if starting disparity was positive, 1 + // column 30, [0], is a 1 if symbol results in a disparity flip + // 0 for a balanced symbol (5 '1's, 5 '0's). + + wire [29:0] code = code8b10b[i] ; + wire [9:0] expect_0_disp = {code[11], code[12], code[13], code[14], code[15], + code[16], code[17], code[18], code[19], code[20]} ; + wire [9:0] expect_1_disp = {code[1], code[2], code[3], code[4], code[5], + code[6], code[7], code[8], code[9], code[10]} ; + + reg [1023:0] legal ; // mark every used 10b symbol as legal, leave rest marked as not + reg [2047:0] okdisp ; // now mark every used combination of symbol and starting disparity + reg [8:0] mapcode [1023:0] ; + reg [10:0] codedisp0, codedisp1 ; + reg [9:0] decodein ; + reg decdispin ; + integer errors ; + + encode_8b10b DUTE (testin, dispin, testout, dispout) ; + decode_8b10b DUTD (decodein, decdispin, decodeout, decodedisp, decodeerr, disperr) ; + + always @ (code) testin = code[29:21] ; + + initial begin + errors = 0 ; + $readmemb ("8b10b_a.mem", code8b10b) ; + //$vcdpluson ; + $dumpvars (0); + $display ("\n\nFirst, test by trying all 268 (256 Dx.y and 12 Kx.y)") ; + $display ("valid inputs, with both + and - starting disparity."); + $display ("We check that the encoder output and ending disparity is correct."); + $display ("We also check that the decoder matches."); + for (i = 0 ; i < 268 ; i = i + 1) begin + // testin = code[29:21] ; + dispin = 0 ; + #1 + decodein = testout ; + decdispin = dispin ; + #1 +// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ; + if (testout != expect_0_disp) + $display ("bad code0 %b %b %b %b %b", dispin, testin, dispout, testout, expect_0_disp) ; + if (dispout != (dispin ^ code[0])) + $display ("bad disp0 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ; + if (0 != (9'b1_1111_1111 & (testin ^ decodeout))) + $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if (decodedisp != dispout) + $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if ((testout != expect_0_disp) | decodeerr | + (dispout != (dispin ^ code[0])) | (decodedisp != dispout)) + errors = errors + 1 ; + + dispin = 1 ; + #1 + decodein = testout ; + decdispin = dispin ; + #1 +// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2, DUTD.fghjp31, DUTD.feqg, DUTD.heqj, DUTD.fghj22, DUTD.fi, DUTD.gi, DUTD.hi, DUTD.ji, DUTD.dispout}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ; + if (testout != expect_1_disp) + $display ("bad code1 %b %b %b %b %b", dispin, testin, dispout, testout, expect_1_disp) ; + if (dispout != (dispin ^ code[0])) + $display ("bad disp1 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ; + if (0 != (9'b1_1111_1111 & (testin ^ decodeout))) + $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if (decodedisp != dispout) + $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if ((testout != expect_1_disp) | decodeerr | + (dispout != (dispin ^ code[0])) | (decodedisp != dispout)) + errors = errors + 1 ; + end + $display ("%d errors in that testing.\n", errors) ; + + // Now, having verified all legal codes, lets run some illegal codes + // at the decoder... how to figure illegal codes ? 2048 possible cases, + // lets mark the OK ones... + legal = 0 ; + okdisp = 0 ; + for (i = 0 ; i < 268 ; i = i + 1) begin + #1 +// $display ("i=%d: %b %b %d %d %x %x", i, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp) ; + legal[expect_0_disp] = 1 ; + legal[expect_1_disp] = 1 ; + codedisp0 = expect_0_disp ; + codedisp1 = {1'b1, expect_1_disp} ; + okdisp[codedisp0] = 1 ; + okdisp[codedisp1] = 1 ; + mapcode[expect_0_disp] = code[29:21] ; + mapcode[expect_1_disp] = code[29:21] ; + end + + $display ("Now lets test all (legal and illegal) codes into the decoder."); + $display ("checking all possible decode inputs") ; + for (i = 0 ; i < 1024 ; i = i + 1) begin + decodein = i ; + decdispin = 0 ; + codedisp1 = 1024 | i ; + #1 + if (((legal[i] == 0) & (decodeerr != 1)) | + (legal[i] & (mapcode[i] != decodeout)) | + (legal[i] & (disperr != !okdisp[i]))) + $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", + decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i]) ; + if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ; + if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ; + if (legal[i] & (disperr != 1) & !okdisp[i]) $display ("ERR: disp err should be asserted") ; + else if (legal[i] & (disperr != 0) & okdisp[i]) + $display ("ERR: disp err should not be asserted") ; + + if (((legal[i] == 0) & (decodeerr != 1)) | + (legal[i] & !disperr & !okdisp[i]) | + (legal[i] & (mapcode[i] != decodeout)) | + (legal[i] & disperr & okdisp[i])) + errors = errors + 1 ; + + decdispin = 1 ; + #1 + if (((legal[i] == 0) & (decodeerr != 1)) | + (legal[i] & (mapcode[i] != decodeout)) | + (legal[i] & (disperr != !okdisp[i|1024]))) + $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", + decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i|1024]) ; + if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ; + if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ; + if (legal[i] & (disperr != 1) & !okdisp[i|1024]) $display ("ERR: disp err should be asserted") ; + else if (legal[i] & (disperr != 0) & okdisp[i|1024]) + $display ("ERR: disp err should not be asserted") ; + if (((legal[i] == 0) & (decodeerr != 1)) | + (legal[i] & !disperr & !okdisp[i|1024]) | + (legal[i] & (mapcode[i] != decodeout)) | + (legal[i] & disperr & okdisp[i|1024])) + errors = errors + 1 ; + end // for (i = 0 ; i < 1024 ; i = i + 1) + + $display ("\nDone testing decoder.\n") ; + $display ("Total error count: %d", errors); + if (errors == 0) $display ("Congratulations!\n"); + $finish ; + end // initial begin + +endmodule diff --git a/usrp2/opencores/README b/usrp2/opencores/README new file mode 100644 index 000000000..d63b7cbdb --- /dev/null +++ b/usrp2/opencores/README @@ -0,0 +1,11 @@ +All the subdirectories of this directory contain code from the OpenCores +project, checked out directly from the OpenCores CVS server. You can update +any directory to the latest OpenCores code by doing "cvs up" in that. +This is not recommended unless you know what you are doing. + + +Each directory contains its own copyright and licensing information. We +believe that we have the right to distribute all of these files in the form +in which we provide them. If this is not the case, please notify Matt Ettus, +matt@ettus.com. + diff --git a/usrp2/opencores/aemb/CVS/.gitignore b/usrp2/opencores/aemb/CVS/.gitignore new file mode 100644 index 000000000..b693d7c72 --- /dev/null +++ b/usrp2/opencores/aemb/CVS/.gitignore @@ -0,0 +1 @@ +/Entries.Log diff --git a/usrp2/opencores/aemb/CVS/Entries b/usrp2/opencores/aemb/CVS/Entries new file mode 100644 index 000000000..093a9a86a --- /dev/null +++ b/usrp2/opencores/aemb/CVS/Entries @@ -0,0 +1,4 @@ +D/rtl//// +D/sim//// +D/sw//// +D/doc//// diff --git a/usrp2/opencores/aemb/CVS/Repository b/usrp2/opencores/aemb/CVS/Repository new file mode 100644 index 000000000..967f2cedf --- /dev/null +++ b/usrp2/opencores/aemb/CVS/Repository @@ -0,0 +1 @@ +aemb diff --git a/usrp2/opencores/aemb/CVS/Root b/usrp2/opencores/aemb/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/aemb/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/CVS/Template b/usrp2/opencores/aemb/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/aemb/doc/CVS/Entries b/usrp2/opencores/aemb/doc/CVS/Entries new file mode 100644 index 000000000..16bb46ac6 --- /dev/null +++ b/usrp2/opencores/aemb/doc/CVS/Entries @@ -0,0 +1,2 @@ +/aeMB_datasheet.pdf/1.3/Tue Jan 15 18:38:57 2008/-kb/ +D diff --git a/usrp2/opencores/aemb/doc/CVS/Repository b/usrp2/opencores/aemb/doc/CVS/Repository new file mode 100644 index 000000000..41df302a9 --- /dev/null +++ b/usrp2/opencores/aemb/doc/CVS/Repository @@ -0,0 +1 @@ +aemb/doc diff --git a/usrp2/opencores/aemb/doc/CVS/Root b/usrp2/opencores/aemb/doc/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/aemb/doc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/doc/CVS/Template b/usrp2/opencores/aemb/doc/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf b/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf new file mode 100644 index 000000000..5b26ac319 Binary files /dev/null and b/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf differ diff --git a/usrp2/opencores/aemb/rtl/CVS/Entries b/usrp2/opencores/aemb/rtl/CVS/Entries new file mode 100644 index 000000000..428c5622d --- /dev/null +++ b/usrp2/opencores/aemb/rtl/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/opencores/aemb/rtl/CVS/Repository b/usrp2/opencores/aemb/rtl/CVS/Repository new file mode 100644 index 000000000..e2c1eab77 --- /dev/null +++ b/usrp2/opencores/aemb/rtl/CVS/Repository @@ -0,0 +1 @@ +aemb/rtl diff --git a/usrp2/opencores/aemb/rtl/CVS/Root b/usrp2/opencores/aemb/rtl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/aemb/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/rtl/CVS/Template b/usrp2/opencores/aemb/rtl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/aemb/rtl/verilog/.gitignore b/usrp2/opencores/aemb/rtl/verilog/.gitignore new file mode 100644 index 000000000..6b09f5cc9 --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/.gitignore @@ -0,0 +1 @@ +/aeMB2* diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Entries b/usrp2/opencores/aemb/rtl/verilog/CVS/Entries new file mode 100644 index 000000000..f17d70235 --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/CVS/Entries @@ -0,0 +1,38 @@ +/aeMB2_aslu.v/1.10/Tue May 20 18:13:50 2008// +/aeMB2_bpcu.v/1.5/Tue May 20 18:13:50 2008// +/aeMB2_brcc.v/1.3/Tue May 20 18:13:50 2008// +/aeMB2_bsft.v/1.3/Tue May 20 18:13:50 2008// +/aeMB2_ctrl.v/1.7/Tue May 20 18:13:51 2008// +/aeMB2_dparam.v/1.1/Tue May 20 18:13:51 2008// +/aeMB2_dwbif.v/1.7/Tue May 20 18:13:51 2008// +/aeMB2_edk32.v/1.8/Tue May 20 18:13:51 2008// +/aeMB2_edk62.v/1.8/Tue May 20 18:13:51 2008// +/aeMB2_exec.v/1.4/Tue May 20 18:13:51 2008// +/aeMB2_gprf.v/1.4/Tue May 20 18:13:51 2008// +/aeMB2_iche.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_idmx.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_intu.v/1.7/Tue May 20 18:13:51 2008// +/aeMB2_iwbif.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_memif.v/1.3/Tue May 20 18:13:51 2008// +/aeMB2_mult.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_ofid.v/1.2/Tue May 20 18:13:51 2008// +/aeMB2_opmx.v/1.3/Tue May 20 18:13:51 2008// +/aeMB2_pipe.v/1.4/Tue May 20 18:13:51 2008// +/aeMB2_regf.v/1.3/Tue May 20 18:13:51 2008// +/aeMB2_regs.v/1.4/Tue May 20 18:13:51 2008// +/aeMB2_sfrf.v/1.2/Tue May 20 18:13:51 2008// +/aeMB2_sim.v/1.2/Tue May 20 18:13:51 2008// +/aeMB2_sparam.v/1.2/Tue May 20 18:13:51 2008// +/aeMB2_spsram.v/1.1/Tue May 20 18:13:51 2008// +/aeMB2_sysc.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_tpsram.v/1.3/Tue May 20 18:13:51 2008// +/aeMB2_xslif.v/1.7/Tue May 20 18:13:52 2008// +/aeMB_bpcu.v/1.4/Thu Sep 11 02:11:12 2008// +/aeMB_core.v/1.9/Thu Sep 11 02:11:12 2008// +/aeMB_ctrl.v/1.10/Thu Sep 11 02:11:12 2008// +/aeMB_edk32.v/1.14/Thu Sep 11 02:11:12 2008// +/aeMB_ibuf.v/1.10/Thu Sep 11 02:11:12 2008// +/aeMB_regf.v/1.3/Thu Sep 11 02:11:12 2008// +/aeMB_sim.v/1.2/Thu Jan 22 05:50:30 2009// +/aeMB_xecu.v/1.12/Thu Sep 11 02:11:12 2008// +D diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Repository b/usrp2/opencores/aemb/rtl/verilog/CVS/Repository new file mode 100644 index 000000000..a9de19556 --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/CVS/Repository @@ -0,0 +1 @@ +aemb/rtl/verilog diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Root b/usrp2/opencores/aemb/rtl/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Template b/usrp2/opencores/aemb/rtl/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v new file mode 100644 index 000000000..a7c686e7e --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v @@ -0,0 +1,184 @@ +// $Id: aeMB_bpcu.v,v 1.4 2007/11/14 22:14:34 sybreon Exp $ +// +// AEMB BRANCH PROGRAMME COUNTER UNIT +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see . +// +// $Log: aeMB_bpcu.v,v $ +// Revision 1.4 2007/11/14 22:14:34 sybreon +// Changed interrupt handling system (reported by M. Ettus). +// +// Revision 1.3 2007/11/10 16:39:38 sybreon +// Upgraded license to LGPLv3. +// Significant performance optimisations. +// +// Revision 1.2 2007/11/02 19:20:58 sybreon +// Added better (beta) interrupt support. +// Changed MSR_IE to disabled at reset as per MB docs. +// +// Revision 1.1 2007/11/02 03:25:39 sybreon +// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. +// Fixed various minor data hazard bugs. +// Code compatible with -O0/1/2/3/s generated code. +// + +module aeMB_bpcu (/*AUTOARG*/ + // Outputs + iwb_adr_o, rPC, rPCLNK, rBRA, rDLY, + // Inputs + rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, gclk, grst, gena + ); + parameter IW = 24; + + // INST WISHBONE + output [IW-1:2] iwb_adr_o; + + // INTERNAL + output [31:2] rPC, rPCLNK; + output rBRA; + output rDLY; + //output [1:0] rATOM; + //output [1:0] xATOM; + + input [1:0] rMXALT; + input [5:0] rOPC; + input [4:0] rRD, rRA; + input [31:0] rRESULT; // ALU + input [31:0] rDWBDI; // RAM + input [31:0] rREGA; + //input [1:0] rXCE; + + // SYSTEM + input gclk, grst, gena; + + // --- BRANCH CONTROL -------------------------------------------- + // Controls the branch and delay flags + + wire fRTD = (rOPC == 6'o55); + wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57); + wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56); + + wire [31:0] wREGA; + assign wREGA = (rMXALT == 2'o2) ? rDWBDI : + (rMXALT == 2'o1) ? rRESULT : + rREGA; + + wire wBEQ = (wREGA == 32'd0); + wire wBNE = ~wBEQ; + wire wBLT = wREGA[31]; + wire wBLE = wBLT | wBEQ; + wire wBGE = ~wBLT; + wire wBGT = ~wBLE; + + reg xXCC; + always @(/*AUTOSENSE*/rRD or wBEQ or wBGE or wBGT or wBLE or wBLT + or wBNE) + case (rRD[2:0]) + 3'o0: xXCC <= wBEQ; + 3'o1: xXCC <= wBNE; + 3'o2: xXCC <= wBLT; + 3'o3: xXCC <= wBLE; + 3'o4: xXCC <= wBGT; + 3'o5: xXCC <= wBGE; + default: xXCC <= 1'bX; + endcase // case (rRD[2:0]) + + reg rBRA, xBRA; + reg rDLY, xDLY; + wire fSKIP = rBRA & !rDLY; + + always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD + or xXCC) + //if (rBRA | |rXCE) begin + if (rBRA) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xBRA <= 1'h0; + xDLY <= 1'h0; + // End of automatics + end else begin + xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD; + xBRA <= (fRTD | fBRU) ? 1'b1 : + (fBCC) ? xXCC : + 1'b0; + end + + // --- PC PIPELINE ------------------------------------------------ + // PC and related changes + + reg [31:2] rIPC, xIPC; + reg [31:2] rPC, xPC; + reg [31:2] rPCLNK, xPCLNK; + + assign iwb_adr_o = rIPC[IW-1:2]; + + always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin + //xPCLNK <= (^rATOM) ? rPC : rPC; + xPCLNK <= rPC; + //xPC <= (^rATOM) ? rIPC : rRESULT[31:2]; + xPC <= rIPC; + //xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); + /* + case (rXCE) + 2'o1: xIPC <= 30'h2; + 2'o2: xIPC <= 30'h4; + 2'o3: xIPC <= 30'h6; + default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); + endcase // case (rXCE) + */ + xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); + end + + // --- ATOMIC CONTROL --------------------------------------------- + // This is used to indicate 'safe' instruction borders. + + wire wIMM = (rOPC == 6'o54) & !fSKIP; + wire wRTD = (rOPC == 6'o55) & !fSKIP; + wire wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP; + wire wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP; + + wire fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA); + reg [1:0] rATOM, xATOM; + + always @(/*AUTOSENSE*/fATOM or rATOM) + xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)}; + + + // --- SYNC PIPELINE ---------------------------------------------- + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rATOM <= 2'h0; + rBRA <= 1'h0; + rDLY <= 1'h0; + rIPC <= 30'h0; + rPC <= 30'h0; + rPCLNK <= 30'h0; + // End of automatics + end else if (gena) begin + rIPC <= #1 xIPC; + rBRA <= #1 xBRA; + rPC <= #1 xPC; + rPCLNK <= #1 xPCLNK; + rDLY <= #1 xDLY; + rATOM <= #1 xATOM; + end + +endmodule // aeMB_bpcu diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v new file mode 100644 index 000000000..20ce9852e --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v @@ -0,0 +1,137 @@ +// $Id: aeMB_core.v,v 1.9 2007/11/23 14:06:41 sybreon Exp $ +// +// AEMB 32'bit RISC MICROPROCESSOR CORE +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see . +// +// HISTORY +// $Log: aeMB_core.v,v $ +// Revision 1.9 2007/11/23 14:06:41 sybreon +// Old version deprecated. +// +// Revision 1.8 2007/10/22 19:12:59 sybreon +// Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. +// +// Revision 1.7 2007/05/30 18:44:30 sybreon +// Added interrupt support. +// +// Revision 1.6 2007/05/17 09:08:21 sybreon +// Removed asynchronous reset signal. +// +// Revision 1.5 2007/04/27 00:23:55 sybreon +// Added code documentation. +// Improved size & speed of rtl/verilog/aeMB_aslu.v +// +// Revision 1.4 2007/04/25 22:15:04 sybreon +// Added support for 8-bit and 16-bit data types. +// +// Revision 1.3 2007/04/11 04:30:43 sybreon +// Added pipeline stalling from incomplete bus cycles. +// Separated sync and async portions of code. +// +// Revision 1.2 2007/04/04 06:13:23 sybreon +// Removed unused signals +// +// Revision 1.1 2007/03/09 17:52:17 sybreon +// initial import +// + + +module aeMB_core (/*AUTOARG*/ + // Outputs + iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, + fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, + // Inputs + sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, + fsl_ack_i, dwb_dat_i, dwb_ack_i + ); + // Instruction WB address space + parameter ISIZ = 32; + // Data WB address space + parameter DSIZ = 32; + // Multiplier + parameter MUL = 1; + // Barrel Shifter + parameter BSF = 1; + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [DSIZ-1:2] dwb_adr_o; // From edk32 of aeMB_edk32.v + output [31:0] dwb_dat_o; // From edk32 of aeMB_edk32.v + output [3:0] dwb_sel_o; // From edk32 of aeMB_edk32.v + output dwb_stb_o; // From edk32 of aeMB_edk32.v + output dwb_wre_o; // From edk32 of aeMB_edk32.v + output [6:2] fsl_adr_o; // From edk32 of aeMB_edk32.v + output [31:0] fsl_dat_o; // From edk32 of aeMB_edk32.v + output fsl_stb_o; // From edk32 of aeMB_edk32.v + output [1:0] fsl_tag_o; // From edk32 of aeMB_edk32.v + output fsl_wre_o; // From edk32 of aeMB_edk32.v + output [ISIZ-1:2] iwb_adr_o; // From edk32 of aeMB_edk32.v + output iwb_stb_o; // From edk32 of aeMB_edk32.v + // End of automatics + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input dwb_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] dwb_dat_i; // To edk32 of aeMB_edk32.v + input fsl_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] fsl_dat_i; // To edk32 of aeMB_edk32.v + input iwb_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] iwb_dat_i; // To edk32 of aeMB_edk32.v + input sys_clk_i; // To edk32 of aeMB_edk32.v + input sys_int_i; // To edk32 of aeMB_edk32.v + input sys_rst_i; // To edk32 of aeMB_edk32.v + // End of automatics + /*AUTOWIRE*/ + + // INSTANTIATIONS ///////////////////////////////////////////////////////////////// + + /* + aeMB_edk32 AUTO_TEMPLATE ( + .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), + .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), + ); + */ + + aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF) + edk32 (/*AUTOINST*/ + // Outputs + .dwb_adr_o (dwb_adr_o[DSIZ-1:2]), // Templated + .dwb_dat_o (dwb_dat_o[31:0]), + .dwb_sel_o (dwb_sel_o[3:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_wre_o (dwb_wre_o), + .fsl_adr_o (fsl_adr_o[6:2]), + .fsl_dat_o (fsl_dat_o[31:0]), + .fsl_stb_o (fsl_stb_o), + .fsl_tag_o (fsl_tag_o[1:0]), + .fsl_wre_o (fsl_wre_o), + .iwb_adr_o (iwb_adr_o[ISIZ-1:2]), // Templated + .iwb_stb_o (iwb_stb_o), + // Inputs + .dwb_ack_i (dwb_ack_i), + .dwb_dat_i (dwb_dat_i[31:0]), + .fsl_ack_i (fsl_ack_i), + .fsl_dat_i (fsl_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .iwb_dat_i (iwb_dat_i[31:0]), + .sys_int_i (sys_int_i), + .sys_clk_i (sys_clk_i), + .sys_rst_i (sys_rst_i)); + + +endmodule // aeMB_core diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v new file mode 100644 index 000000000..9ffa20ff2 --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v @@ -0,0 +1,62 @@ + +// Wrapper for aeMB core: +// Drive wb_cyc_o (just tied to wb_stb_o for now) +// Make input reset active high (like the signal name makes it sound....) +// No longer needed +// Make it big-endian like the standard MicroBlaze + +module aeMB_core_BE + #(parameter ISIZ=32, parameter DSIZ=32, + parameter MUL=0, parameter BSF=0) + (input sys_clk_i, + input sys_rst_i, + + output iwb_stb_o, + output [ISIZ-1:0] iwb_adr_o, + input [31:0] iwb_dat_i, + input iwb_ack_i, + + output dwb_we_o, + output dwb_stb_o, + output [DSIZ-1:0] dwb_adr_o, + output [31:0] dwb_dat_o, + input [31:0] dwb_dat_i, + input dwb_ack_i, + output [3:0] dwb_sel_o, + output dwb_cyc_o, + + input sys_int_i, + input sys_exc_i); + + assign dwb_cyc_o = dwb_stb_o; + + aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF)) + aeMB_edk32 (.sys_clk_i(sys_clk_i), + .sys_rst_i(sys_rst_i), + + .iwb_stb_o(iwb_stb_o), + .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), + .iwb_ack_i(iwb_ack_i), + .iwb_dat_i(iwb_dat_i), + + .dwb_wre_o(dwb_we_o), + .dwb_stb_o(dwb_stb_o), + .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), + .dwb_ack_i(dwb_ack_i), + .dwb_sel_o(dwb_sel_o), + .dwb_dat_i(dwb_dat_i), + .dwb_dat_o(dwb_dat_o), + + .fsl_wre_o(), + .fsl_tag_o(), + .fsl_stb_o(), + .fsl_dat_o(), + .fsl_adr_o(), + .fsl_dat_i(32'b0), + .fsl_ack_i(1'b0), + .sys_int_i(sys_int_i) ); + + assign iwb_adr_o[1:0] = 2'b0; + assign dwb_adr_o[1:0] = 2'b0; + +endmodule // aeMB_core_BE diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v new file mode 100644 index 000000000..88d4e51ce --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v @@ -0,0 +1,336 @@ +// $Id: aeMB_ctrl.v,v 1.10 2007/11/30 16:44:40 sybreon Exp $ +// +// AEMB CONTROL UNIT +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see . +// +// $Log: aeMB_ctrl.v,v $ +// Revision 1.10 2007/11/30 16:44:40 sybreon +// Minor code cleanup. +// +// Revision 1.9 2007/11/15 09:26:43 sybreon +// Fixed minor typo causing synthesis failure. +// +// Revision 1.8 2007/11/14 23:19:24 sybreon +// Fixed minor typo. +// +// Revision 1.7 2007/11/14 22:14:34 sybreon +// Changed interrupt handling system (reported by M. Ettus). +// +// Revision 1.6 2007/11/10 16:39:38 sybreon +// Upgraded license to LGPLv3. +// Significant performance optimisations. +// +// Revision 1.5 2007/11/09 20:51:52 sybreon +// Added GET/PUT support through a FSL bus. +// +// Revision 1.4 2007/11/08 17:48:14 sybreon +// Fixed data WISHBONE arbitration problem (reported by J Lee). +// +// Revision 1.3 2007/11/08 14:17:47 sybreon +// Parameterised optional components. +// +// Revision 1.2 2007/11/02 19:20:58 sybreon +// Added better (beta) interrupt support. +// Changed MSR_IE to disabled at reset as per MB docs. +// +// Revision 1.1 2007/11/02 03:25:40 sybreon +// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. +// Fixed various minor data hazard bugs. +// Code compatible with -O0/1/2/3/s generated code. +// + +module aeMB_ctrl (/*AUTOARG*/ + // Outputs + rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o, + fsl_stb_o, fsl_wre_o, + // Inputs + rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG, + dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena + ); + // INTERNAL + //output [31:2] rPCLNK; + output [1:0] rMXDST; + output [1:0] rMXSRC, rMXTGT, rMXALT; + output [2:0] rMXALU; + output [4:0] rRW; + + input rDLY; + input [15:0] rIMM; + input [10:0] rALT; + input [5:0] rOPC; + input [4:0] rRD, rRA, rRB; + input [31:2] rPC; + input rBRA; + input rMSR_IE; + input [31:0] xIREG; + + // DATA WISHBONE + output dwb_stb_o; + output dwb_wre_o; + input dwb_ack_i; + + // INST WISHBONE + input iwb_ack_i; + + // FSL WISHBONE + output fsl_stb_o; + output fsl_wre_o; + input fsl_ack_i; + + // SYSTEM + input gclk, grst, gena; + + // --- DECODE INSTRUCTIONS + // TODO: Simplify + + wire [5:0] wOPC; + wire [4:0] wRD, wRA, wRB; + wire [10:0] wALT; + + assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian + + wire fSFT = (rOPC == 6'o44); + wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4); + + wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30); + wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31); + wire fDIV = (rOPC == 6'o22); + + wire fRTD = (rOPC == 6'o55); + wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57); + wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56); + wire fBRA = fBRU & rRA[3]; + + wire fIMM = (rOPC == 6'o54); + wire fMOV = (rOPC == 6'o45); + + wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6); + wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7); + wire fLDST = (&rOPC[5:4]); + + wire fPUT = (rOPC == 6'o33) & rRB[4]; + wire fGET = (rOPC == 6'o33) & !rRB[4]; + + + wire wSFT = (wOPC == 6'o44); + wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4); + + wire wMUL = (wOPC == 6'o20) | (wOPC == 6'o30); + wire wBSF = (wOPC == 6'o21) | (wOPC == 6'o31); + wire wDIV = (wOPC == 6'o22); + + wire wRTD = (wOPC == 6'o55); + wire wBCC = (wOPC == 6'o47) | (wOPC == 6'o57); + wire wBRU = (wOPC == 6'o46) | (wOPC == 6'o56); + wire wBRA = wBRU & wRA[3]; + + wire wIMM = (wOPC == 6'o54); + wire wMOV = (wOPC == 6'o45); + + wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6); + wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7); + wire wLDST = (&wOPC[5:4]); + + wire wPUT = (wOPC == 6'o33) & wRB[4]; + wire wGET = (wOPC == 6'o33) & !wRB[4]; + + + // --- BRANCH SLOT REGISTERS --------------------------- + + reg [31:2] rPCLNK, xPCLNK; + reg [1:0] rMXDST, xMXDST; + reg [4:0] rRW, xRW; + + reg [1:0] rMXSRC, xMXSRC; + reg [1:0] rMXTGT, xMXTGT; + reg [1:0] rMXALT, xMXALT; + + + // --- OPERAND SELECTOR --------------------------------- + + wire wRDWE = |xRW; + wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE; + wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE; + wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE; + wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE; + + always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M + or wBFWD_R or wBRU or wOPC) + //if (rBRA | |rXCE) begin + if (rBRA) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xMXALT <= 2'h0; + xMXSRC <= 2'h0; + xMXTGT <= 2'h0; + // End of automatics + end else begin + xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC + (wAFWD_M) ? 2'o2 : // RAM + (wAFWD_R) ? 2'o1 : // FWD + 2'o0; // REG + xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM + (wBFWD_M) ? 2'o2 : // RAM + (wBFWD_R) ? 2'o1 : // FWD + 2'o0; // REG + xMXALT <= (wAFWD_M) ? 2'o2 : // RAM + (wAFWD_R) ? 2'o1 : // FWD + 2'o0; // REG + end // else: !if(rBRA) + + // --- ALU CONTROL --------------------------------------- + + reg [2:0] rMXALU, xMXALU; + + always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV + or wMUL or wSFT) + //if (rBRA | |rXCE) begin + if (rBRA) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xMXALU <= 3'h0; + // End of automatics + end else begin + xMXALU <= (wBRA | wMOV) ? 3'o3 : + (wSFT) ? 3'o2 : + (wLOG) ? 3'o1 : + (wMUL) ? 3'o4 : + (wBSF) ? 3'o5 : + (wDIV) ? 3'o6 : + 3'o0; + end // else: !if(rBRA) + + // --- DELAY SLOT REGISTERS ------------------------------ + + wire fSKIP = (rBRA & !rDLY); + + always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP + or fSTR or rRD) + if (fSKIP) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xMXDST <= 2'h0; + xRW <= 5'h0; + // End of automatics + end else begin + xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 : + (fLOD | fGET) ? 2'o2 : + (fBRU) ? 2'o1 : + 2'o0; + xRW <= rRD; + end // else: !if(fSKIP) + + + // --- DATA WISHBONE ---------------------------------- + + wire fDACK = !(dwb_stb_o ^ dwb_ack_i); + + reg rDWBSTB, xDWBSTB; + reg rDWBWRE, xDWBWRE; + + assign dwb_stb_o = rDWBSTB; + assign dwb_wre_o = rDWBWRE; + + + always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i) + //if (fSKIP | |rXCE) begin + if (fSKIP) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xDWBSTB <= 1'h0; + xDWBWRE <= 1'h0; + // End of automatics + end else begin + xDWBSTB <= (fLOD | fSTR) & iwb_ack_i; + xDWBWRE <= fSTR & iwb_ack_i; + end + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rDWBSTB <= 1'h0; + rDWBWRE <= 1'h0; + // End of automatics + end else if (fDACK) begin + rDWBSTB <= #1 xDWBSTB; + rDWBWRE <= #1 xDWBWRE; + end + + + // --- FSL WISHBONE ----------------------------------- + + wire fFACK = !(fsl_stb_o ^ fsl_ack_i); + + reg rFSLSTB, xFSLSTB; + reg rFSLWRE, xFSLWRE; + + assign fsl_stb_o = rFSLSTB; + assign fsl_wre_o = rFSLWRE; + + always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i) + //if (fSKIP | |rXCE) begin + if (fSKIP) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xFSLSTB <= 1'h0; + xFSLWRE <= 1'h0; + // End of automatics + end else begin + xFSLSTB <= (fPUT | fGET) & iwb_ack_i; + xFSLWRE <= fPUT & iwb_ack_i; + end + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rFSLSTB <= 1'h0; + rFSLWRE <= 1'h0; + // End of automatics + end else if (fFACK) begin + rFSLSTB <= #1 xFSLSTB; + rFSLWRE <= #1 xFSLWRE; + end + + // --- PIPELINE CONTROL DELAY ---------------------------- + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rMXALT <= 2'h0; + rMXALU <= 3'h0; + rMXDST <= 2'h0; + rMXSRC <= 2'h0; + rMXTGT <= 2'h0; + rRW <= 5'h0; + // End of automatics + end else if (gena) begin // if (grst) + //rPCLNK <= #1 xPCLNK; + rMXDST <= #1 xMXDST; + rRW <= #1 xRW; + rMXSRC <= #1 xMXSRC; + rMXTGT <= #1 xMXTGT; + rMXALT <= #1 xMXALT; + rMXALU <= #1 xMXALU; + end + + +endmodule // aeMB_ctrl diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v new file mode 100644 index 000000000..8bf4f7cac --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v @@ -0,0 +1,289 @@ +/* $Id: aeMB_edk32.v,v 1.14 2008/01/19 16:01:22 sybreon Exp $ +** +** AEMB EDK 3.2 Compatible Core +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aeMB_edk32 (/*AUTOARG*/ + // Outputs + iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, + fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, + // Inputs + sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i, + dwb_ack_i, sys_clk_i, sys_rst_i + ); + // Bus widths + parameter IW = 32; /// Instruction bus address width + parameter DW = 32; /// Data bus address width + + // Optional functions + parameter MUL = 0; // Multiplier + parameter BSF = 1; // Barrel Shifter + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v + output [31:0] dwb_dat_o; // From regf of aeMB_regf.v + output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v + output dwb_stb_o; // From ctrl of aeMB_ctrl.v + output dwb_wre_o; // From ctrl of aeMB_ctrl.v + output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v + output [31:0] fsl_dat_o; // From regf of aeMB_regf.v + output fsl_stb_o; // From ctrl of aeMB_ctrl.v + output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v + output fsl_wre_o; // From ctrl of aeMB_ctrl.v + output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v + output iwb_stb_o; // From ibuf of aeMB_ibuf.v + // End of automatics + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input dwb_ack_i; // To ctrl of aeMB_ctrl.v + input [31:0] dwb_dat_i; // To regf of aeMB_regf.v + input fsl_ack_i; // To ctrl of aeMB_ctrl.v + input [31:0] fsl_dat_i; // To regf of aeMB_regf.v + input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ... + input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v + input sys_int_i; // To ibuf of aeMB_ibuf.v + // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [10:0] rALT; // From ibuf of aeMB_ibuf.v + wire rBRA; // From bpcu of aeMB_bpcu.v + wire rDLY; // From bpcu of aeMB_bpcu.v + wire [31:0] rDWBDI; // From regf of aeMB_regf.v + wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v + wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v + wire rMSR_BIP; // From xecu of aeMB_xecu.v + wire rMSR_IE; // From xecu of aeMB_xecu.v + wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v + wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v + wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v + wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v + wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v + wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v + wire [31:2] rPC; // From bpcu of aeMB_bpcu.v + wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v + wire [4:0] rRA; // From ibuf of aeMB_ibuf.v + wire [4:0] rRB; // From ibuf of aeMB_ibuf.v + wire [4:0] rRD; // From ibuf of aeMB_ibuf.v + wire [31:0] rREGA; // From regf of aeMB_regf.v + wire [31:0] rREGB; // From regf of aeMB_regf.v + wire [31:0] rRESULT; // From xecu of aeMB_xecu.v + wire [4:0] rRW; // From ctrl of aeMB_ctrl.v + wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v + wire rSTALL; // From ibuf of aeMB_ibuf.v + wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v + // End of automatics + + input sys_clk_i; + input sys_rst_i; + + wire grst = sys_rst_i; + wire gclk = sys_clk_i; + wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL; + wire oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i); + + // --- INSTANTIATIONS ------------------------------------- + + aeMB_ibuf + ibuf (/*AUTOINST*/ + // Outputs + .rIMM (rIMM[15:0]), + .rRA (rRA[4:0]), + .rRD (rRD[4:0]), + .rRB (rRB[4:0]), + .rALT (rALT[10:0]), + .rOPC (rOPC[5:0]), + .rSIMM (rSIMM[31:0]), + .xIREG (xIREG[31:0]), + .rSTALL (rSTALL), + .iwb_stb_o (iwb_stb_o), + // Inputs + .rBRA (rBRA), + .rMSR_IE (rMSR_IE), + .rMSR_BIP (rMSR_BIP), + .iwb_dat_i (iwb_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .sys_int_i (sys_int_i), + .gclk (gclk), + .grst (grst), + .gena (gena), + .oena (oena)); + + aeMB_ctrl + ctrl (/*AUTOINST*/ + // Outputs + .rMXDST (rMXDST[1:0]), + .rMXSRC (rMXSRC[1:0]), + .rMXTGT (rMXTGT[1:0]), + .rMXALT (rMXALT[1:0]), + .rMXALU (rMXALU[2:0]), + .rRW (rRW[4:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_wre_o (dwb_wre_o), + .fsl_stb_o (fsl_stb_o), + .fsl_wre_o (fsl_wre_o), + // Inputs + .rDLY (rDLY), + .rIMM (rIMM[15:0]), + .rALT (rALT[10:0]), + .rOPC (rOPC[5:0]), + .rRD (rRD[4:0]), + .rRA (rRA[4:0]), + .rRB (rRB[4:0]), + .rPC (rPC[31:2]), + .rBRA (rBRA), + .rMSR_IE (rMSR_IE), + .xIREG (xIREG[31:0]), + .dwb_ack_i (dwb_ack_i), + .iwb_ack_i (iwb_ack_i), + .fsl_ack_i (fsl_ack_i), + .gclk (gclk), + .grst (grst), + .gena (gena)); + + aeMB_bpcu #(IW) + bpcu (/*AUTOINST*/ + // Outputs + .iwb_adr_o (iwb_adr_o[IW-1:2]), + .rPC (rPC[31:2]), + .rPCLNK (rPCLNK[31:2]), + .rBRA (rBRA), + .rDLY (rDLY), + // Inputs + .rMXALT (rMXALT[1:0]), + .rOPC (rOPC[5:0]), + .rRD (rRD[4:0]), + .rRA (rRA[4:0]), + .rRESULT (rRESULT[31:0]), + .rDWBDI (rDWBDI[31:0]), + .rREGA (rREGA[31:0]), + .gclk (gclk), + .grst (grst), + .gena (gena)); + + aeMB_regf + regf (/*AUTOINST*/ + // Outputs + .rREGA (rREGA[31:0]), + .rREGB (rREGB[31:0]), + .rDWBDI (rDWBDI[31:0]), + .dwb_dat_o (dwb_dat_o[31:0]), + .fsl_dat_o (fsl_dat_o[31:0]), + // Inputs + .rOPC (rOPC[5:0]), + .rRA (rRA[4:0]), + .rRB (rRB[4:0]), + .rRW (rRW[4:0]), + .rRD (rRD[4:0]), + .rMXDST (rMXDST[1:0]), + .rPCLNK (rPCLNK[31:2]), + .rRESULT (rRESULT[31:0]), + .rDWBSEL (rDWBSEL[3:0]), + .rBRA (rBRA), + .rDLY (rDLY), + .dwb_dat_i (dwb_dat_i[31:0]), + .fsl_dat_i (fsl_dat_i[31:0]), + .gclk (gclk), + .grst (grst), + .gena (gena)); + + aeMB_xecu #(DW, MUL, BSF) + xecu (/*AUTOINST*/ + // Outputs + .dwb_adr_o (dwb_adr_o[DW-1:2]), + .dwb_sel_o (dwb_sel_o[3:0]), + .fsl_adr_o (fsl_adr_o[6:2]), + .fsl_tag_o (fsl_tag_o[1:0]), + .rRESULT (rRESULT[31:0]), + .rDWBSEL (rDWBSEL[3:0]), + .rMSR_IE (rMSR_IE), + .rMSR_BIP (rMSR_BIP), + // Inputs + .rREGA (rREGA[31:0]), + .rREGB (rREGB[31:0]), + .rMXSRC (rMXSRC[1:0]), + .rMXTGT (rMXTGT[1:0]), + .rRA (rRA[4:0]), + .rRB (rRB[4:0]), + .rMXALU (rMXALU[2:0]), + .rBRA (rBRA), + .rDLY (rDLY), + .rALT (rALT[10:0]), + .rSTALL (rSTALL), + .rSIMM (rSIMM[31:0]), + .rIMM (rIMM[15:0]), + .rOPC (rOPC[5:0]), + .rRD (rRD[4:0]), + .rDWBDI (rDWBDI[31:0]), + .rPC (rPC[31:2]), + .gclk (gclk), + .grst (grst), + .gena (gena)); + + +endmodule // aeMB_edk32 + +/* + $Log: aeMB_edk32.v,v $ + Revision 1.14 2008/01/19 16:01:22 sybreon + Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) + + Revision 1.13 2007/12/25 22:15:09 sybreon + Stalls pipeline on MUL/BSF instructions results in minor speed improvements. + + Revision 1.12 2007/12/23 20:40:44 sybreon + Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. + + Revision 1.11 2007/11/30 17:08:29 sybreon + Moved simulation kernel into code. + + Revision 1.10 2007/11/16 21:52:03 sybreon + Added fsl_tag_o to FSL bus (tag either address or data). + + Revision 1.9 2007/11/14 23:19:24 sybreon + Fixed minor typo. + + Revision 1.8 2007/11/14 22:14:34 sybreon + Changed interrupt handling system (reported by M. Ettus). + + Revision 1.7 2007/11/10 16:39:38 sybreon + Upgraded license to LGPLv3. + Significant performance optimisations. + + Revision 1.6 2007/11/09 20:51:52 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.5 2007/11/08 17:48:14 sybreon + Fixed data WISHBONE arbitration problem (reported by J Lee). + + Revision 1.4 2007/11/08 14:17:47 sybreon + Parameterised optional components. + + Revision 1.3 2007/11/03 08:34:55 sybreon + Minor code cleanup. + + Revision 1.2 2007/11/02 19:20:58 sybreon + Added better (beta) interrupt support. + Changed MSR_IE to disabled at reset as per MB docs. + + Revision 1.1 2007/11/02 03:25:40 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. +*/ \ No newline at end of file diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v new file mode 100644 index 000000000..a4edf1d90 --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v @@ -0,0 +1,192 @@ +/* $Id: aeMB_ibuf.v,v 1.10 2008/01/21 01:02:26 sybreon Exp $ +** +** AEMB INSTRUCTION BUFFER +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aeMB_ibuf (/*AUTOARG*/ + // Outputs + rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o, + // Inputs + rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk, + grst, gena, oena + ); + // INTERNAL + output [15:0] rIMM; + output [4:0] rRA, rRD, rRB; + output [10:0] rALT; + output [5:0] rOPC; + output [31:0] rSIMM; + output [31:0] xIREG; + output rSTALL; + + input rBRA; + //input [1:0] rXCE; + input rMSR_IE; + input rMSR_BIP; + + // INST WISHBONE + output iwb_stb_o; + input [31:0] iwb_dat_i; + input iwb_ack_i; + + // SYSTEM + input sys_int_i; + + // SYSTEM + input gclk, grst, gena, oena; + + reg [15:0] rIMM; + reg [4:0] rRA, rRD; + reg [5:0] rOPC; + + // FIXME: Endian + wire [31:0] wIDAT = iwb_dat_i; + assign {rRB, rALT} = rIMM; + + // TODO: Assign to FIFO not full. + assign iwb_stb_o = 1'b1; + + reg [31:0] rSIMM, xSIMM; + reg rSTALL; + + wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08 + wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10 + wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18 + wire [31:0] wBRAOP = 32'h88000000; // NOP for branches + + wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT}; + reg [31:0] xIREG; + + + // --- INTERRUPT LATCH -------------------------------------- + // Debounce and latch onto the positive level. This is independent + // of the pipeline so that stalls do not affect it. + + reg rFINT; + reg [1:0] rDINT; + wire wSHOT = rDINT[0]; + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rDINT <= 2'h0; + rFINT <= 1'h0; + // End of automatics + end else begin + if (rMSR_IE) + rDINT <= #1 + {rDINT[0], sys_int_i}; + + rFINT <= #1 + //(wIREG == wINTOP) ? 1'b0 : + (rFINT | wSHOT) & rMSR_IE; + end + + wire fIMM = (rOPC == 6'o54); + wire fRTD = (rOPC == 6'o55); + wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)); + wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57)); + + // --- DELAY SLOT ------------------------------------------- + + always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT + or wBRAOP or wIDAT or wINTOP) begin + xIREG <= (rBRA) ? wBRAOP : + (!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP : + wIDAT; + end + + always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin + xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} : + {rIMM, wIDAT[15:0]}; + end + + // --- PIPELINE -------------------------------------------- + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rIMM <= 16'h0; + rOPC <= 6'h0; + rRA <= 5'h0; + rRD <= 5'h0; + rSIMM <= 32'h0; + // End of automatics + end else if (gena) begin + {rOPC, rRD, rRA, rIMM} <= #1 xIREG; + rSIMM <= #1 xSIMM; + end + + // --- STALL FOR MUL/BSF ----------------------------------- + + wire [5:0] wOPC = xIREG[31:26]; + + wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30); + wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31); + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rSTALL <= 1'h0; + // End of automatics + end else begin + rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL); + end + +endmodule // aeMB_ibuf + +/* + $Log: aeMB_ibuf.v,v $ + Revision 1.10 2008/01/21 01:02:26 sybreon + Patch interrupt bug. + + Revision 1.9 2008/01/19 16:01:22 sybreon + Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) + + Revision 1.8 2007/12/25 22:15:09 sybreon + Stalls pipeline on MUL/BSF instructions results in minor speed improvements. + + Revision 1.7 2007/11/22 15:11:15 sybreon + Change interrupt to positive level triggered interrupts. + + Revision 1.6 2007/11/14 23:39:51 sybreon + Fixed interrupt signal synchronisation. + + Revision 1.5 2007/11/14 22:14:34 sybreon + Changed interrupt handling system (reported by M. Ettus). + + Revision 1.4 2007/11/10 16:39:38 sybreon + Upgraded license to LGPLv3. + Significant performance optimisations. + + Revision 1.3 2007/11/03 08:34:55 sybreon + Minor code cleanup. + + Revision 1.2 2007/11/02 19:20:58 sybreon + Added better (beta) interrupt support. + Changed MSR_IE to disabled at reset as per MB docs. + + Revision 1.1 2007/11/02 03:25:40 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. +*/ diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v new file mode 100644 index 000000000..9ac45299b --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v @@ -0,0 +1,241 @@ +// $Id: aeMB_regf.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $ +// +// AEMB REGISTER FILE +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see . +// +// $Log: aeMB_regf.v,v $ +// Revision 1.3 2007/11/10 16:39:38 sybreon +// Upgraded license to LGPLv3. +// Significant performance optimisations. +// +// Revision 1.2 2007/11/09 20:51:52 sybreon +// Added GET/PUT support through a FSL bus. +// +// Revision 1.1 2007/11/02 03:25:41 sybreon +// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. +// Fixed various minor data hazard bugs. +// Code compatible with -O0/1/2/3/s generated code. +// + +module aeMB_regf (/*AUTOARG*/ + // Outputs + rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o, + // Inputs + rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA, + rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena + ); + // INTERNAL + output [31:0] rREGA, rREGB; + output [31:0] rDWBDI; + input [5:0] rOPC; + input [4:0] rRA, rRB, rRW, rRD; + input [1:0] rMXDST; + input [31:2] rPCLNK; + input [31:0] rRESULT; + input [3:0] rDWBSEL; + input rBRA, rDLY; + + // DATA WISHBONE + output [31:0] dwb_dat_o; + input [31:0] dwb_dat_i; + + // FSL WISHBONE + output [31:0] fsl_dat_o; + input [31:0] fsl_dat_i; + + // SYSTEM + input gclk, grst, gena; + + // --- LOAD SIZER ---------------------------------------------- + // Moves the data bytes around depending on the size of the + // operation. + + wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian + wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian + + reg [31:0] rDWBDI; + reg [1:0] rSIZ; + + always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin + /* 51.2 + case (rSIZ) + // FSL + 2'o3: rDWBDI <= wFSLDI; + // 32'bit + 2'o2: rDWBDI <= wDWBDI; + // 16'bit + 2'o1: case (rRESULT[1]) + 1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]}; + 1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]}; + endcase // case (rRESULT[1]) + // 8'bit + 2'o0: case (rRESULT[1:0]) + 2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]}; + 2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]}; + 2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]}; + 2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]}; + endcase // case (rRESULT[1:0]) + endcase // case (rSIZ) + */ + + /* 50.6 + case ({rSIZ, rRESULT[1:0]}) + // FSL + 4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI; + // 32'bit + 4'h8: rDWBDI <= wDWBDI; + // 16'bit + 4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]}; + 4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]}; + // 8'bit + 4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]}; + 4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]}; + 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]}; + 4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]}; + default: rDWBDI <= 32'hX; + endcase // case (rSIZ) + */ + + // 52.0 + case (rDWBSEL) + // 8'bit + 4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]}; + 4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]}; + 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]}; + 4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]}; + // 16'bit + 4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]}; + 4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]}; + // 32'bit + 4'hF: rDWBDI <= wDWBDI; + // FSL + 4'h0: rDWBDI <= wFSLDI; + // Undefined + default: rDWBDI <= 32'hX; + endcase + + end + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rSIZ <= 2'h0; + // End of automatics + end else if (gena) begin + rSIZ <= rOPC[1:0]; + end + + // --- GENERAL PURPOSE REGISTERS (R0-R31) ----------------------- + // LUT RAM implementation is smaller and faster. R0 gets written + // during reset with 0x00 and doesn't change after. + + reg [31:0] mARAM[0:31], + mBRAM[0:31], + mDRAM[0:31]; + + wire [31:0] rREGW = mDRAM[rRW]; + wire [31:0] rREGD = mDRAM[rRD]; + assign rREGA = mARAM[rRA]; + assign rREGB = mBRAM[rRB]; + + wire fRDWE = |rRW; + + reg [31:0] xWDAT; + + always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW + or rRESULT) + case (rMXDST) + 2'o2: xWDAT <= rDWBDI; + 2'o1: xWDAT <= {rPCLNK, 2'o0}; + 2'o0: xWDAT <= rRESULT; + 2'o3: xWDAT <= rREGW; // No change + endcase // case (rMXDST) + + always @(posedge gclk) + if (grst | fRDWE) begin + mARAM[rRW] <= xWDAT; + mBRAM[rRW] <= xWDAT; + mDRAM[rRW] <= xWDAT; + end + + // --- STORE SIZER --------------------------------------------- + // Replicates the data bytes across depending on the size of the + // operation. + + reg [31:0] rDWBDO, xDWBDO; + + wire [31:0] xFSL; + wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE; + wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE; + + assign fsl_dat_o = rDWBDO; + assign xFSL = (fFFWD_M) ? rDWBDI : + (fFFWD_R) ? rRESULT : + rREGA; + + wire [31:0] xDST; + wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE; + wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE; + + assign dwb_dat_o = rDWBDO; + assign xDST = (fDFWD_M) ? rDWBDI : + (fDFWD_R) ? rRESULT : + rREGD; + + always @(/*AUTOSENSE*/rOPC or xDST or xFSL) + case (rOPC[1:0]) + // 8'bit + 2'h0: xDWBDO <= {(4){xDST[7:0]}}; + // 16'bit + 2'h1: xDWBDO <= {(2){xDST[15:0]}}; + // 32'bit + 2'h2: xDWBDO <= xDST; + // FSL + 2'h3: xDWBDO <= xFSL; + //default: xDWBDO <= 32'hX; + endcase // case (rOPC[1:0]) + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rDWBDO <= 32'h0; + // End of automatics + end else if (gena) begin + rDWBDO <= #1 xDWBDO; + end + + // --- SIMULATION ONLY ------------------------------------------ + // Randomise memory to simulate real-world memory + // synopsys translate_off + + integer i; + initial begin + for (i=0; i<32; i=i+1) begin + mARAM[i] <= $random; + mBRAM[i] <= $random; + mDRAM[i] <= $random; + end + end + + // synopsys translate_on + + +endmodule // aeMB_regf diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v new file mode 100644 index 000000000..83248e4ba --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v @@ -0,0 +1,312 @@ +/* $Id: aeMB_sim.v,v 1.2 2008/06/06 09:36:02 sybreon Exp $ +** +** AEMB EDK 3.2 Compatible Core +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aeMB_sim (/*AUTOARG*/ + // Outputs + iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, + fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, + // Inputs + sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, + fsl_ack_i, dwb_dat_i, dwb_ack_i + ); + // Bus widths + parameter IW = 32; /// Instruction bus address width + parameter DW = 32; /// Data bus address width + + // Optional functions + parameter MUL = 1; // Multiplier + parameter BSF = 1; // Barrel Shifter + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [DW-1:2] dwb_adr_o; // From cpu of aeMB_edk32.v + output [31:0] dwb_dat_o; // From cpu of aeMB_edk32.v + output [3:0] dwb_sel_o; // From cpu of aeMB_edk32.v + output dwb_stb_o; // From cpu of aeMB_edk32.v + output dwb_wre_o; // From cpu of aeMB_edk32.v + output [6:2] fsl_adr_o; // From cpu of aeMB_edk32.v + output [31:0] fsl_dat_o; // From cpu of aeMB_edk32.v + output fsl_stb_o; // From cpu of aeMB_edk32.v + output [1:0] fsl_tag_o; // From cpu of aeMB_edk32.v + output fsl_wre_o; // From cpu of aeMB_edk32.v + output [IW-1:2] iwb_adr_o; // From cpu of aeMB_edk32.v + output iwb_stb_o; // From cpu of aeMB_edk32.v + // End of automatics + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input dwb_ack_i; // To cpu of aeMB_edk32.v + input [31:0] dwb_dat_i; // To cpu of aeMB_edk32.v + input fsl_ack_i; // To cpu of aeMB_edk32.v + input [31:0] fsl_dat_i; // To cpu of aeMB_edk32.v + input iwb_ack_i; // To cpu of aeMB_edk32.v + input [31:0] iwb_dat_i; // To cpu of aeMB_edk32.v + input sys_clk_i; // To cpu of aeMB_edk32.v + input sys_int_i; // To cpu of aeMB_edk32.v + input sys_rst_i; // To cpu of aeMB_edk32.v + // End of automatics + /*AUTOWIRE*/ + + aeMB_edk32 + #(/*AUTOINSTPARAM*/ + // Parameters + .IW (IW), + .DW (DW), + .MUL (MUL), + .BSF (BSF)) + cpu + (/*AUTOINST*/ + // Outputs + .dwb_adr_o (dwb_adr_o[DW-1:2]), + .dwb_dat_o (dwb_dat_o[31:0]), + .dwb_sel_o (dwb_sel_o[3:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_wre_o (dwb_wre_o), + .fsl_adr_o (fsl_adr_o[6:2]), + .fsl_dat_o (fsl_dat_o[31:0]), + .fsl_stb_o (fsl_stb_o), + .fsl_tag_o (fsl_tag_o[1:0]), + .fsl_wre_o (fsl_wre_o), + .iwb_adr_o (iwb_adr_o[IW-1:2]), + .iwb_stb_o (iwb_stb_o), + // Inputs + .dwb_ack_i (dwb_ack_i), + .dwb_dat_i (dwb_dat_i[31:0]), + .fsl_ack_i (fsl_ack_i), + .fsl_dat_i (fsl_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .iwb_dat_i (iwb_dat_i[31:0]), + .sys_int_i (sys_int_i), + .sys_clk_i (sys_clk_i), + .sys_rst_i (sys_rst_i)); + + // --- SIMULATION KERNEL ---------------------------------- + // synopsys translate_off + + wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0}; + wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0}; + wire [1:0] wBRA = {cpu.rBRA, cpu.rDLY}; + wire [3:0] wMSR = {cpu.xecu.rMSR_BIP, cpu.xecu.rMSR_C, cpu.xecu.rMSR_IE, cpu.xecu.rMSR_BE}; + + + `ifdef AEMB_SIM_KERNEL + always @(posedge cpu.gclk) begin + if (cpu.gena) begin + + $write ("\n", ($stime/10)); + $writeh (" PC=", iwb_adr ); + $writeh ("\t"); + + case (wBRA) + 2'b00: $write(" "); + 2'b01: $write("."); + 2'b10: $write("-"); + 2'b11: $write("+"); + endcase // case (cpu.wBRA) + + case (cpu.rOPC) + 6'o00: if (cpu.rRD == 0) $write(" "); else $write("ADD"); + 6'o01: $write("RSUB"); + 6'o02: $write("ADDC"); + 6'o03: $write("RSUBC"); + 6'o04: $write("ADDK"); + 6'o05: case (cpu.rIMM[1:0]) + 2'o0: $write("RSUBK"); + 2'o1: $write("CMP"); + 2'o3: $write("CMPU"); + default: $write("XXX"); + endcase // case (cpu.rIMM[1:0]) + 6'o06: $write("ADDKC"); + 6'o07: $write("RSUBKC"); + + 6'o10: $write("ADDI"); + 6'o11: $write("RSUBI"); + 6'o12: $write("ADDIC"); + 6'o13: $write("RSUBIC"); + 6'o14: $write("ADDIK"); + 6'o15: $write("RSUBIK"); + 6'o16: $write("ADDIKC"); + 6'o17: $write("RSUBIKC"); + + 6'o20: $write("MUL"); + 6'o21: case (cpu.rALT[10:9]) + 2'o0: $write("BSRL"); + 2'o1: $write("BSRA"); + 2'o2: $write("BSLL"); + default: $write("XXX"); + endcase // case (cpu.rALT[10:9]) + 6'o22: $write("IDIV"); + + 6'o30: $write("MULI"); + 6'o31: case (cpu.rALT[10:9]) + 2'o0: $write("BSRLI"); + 2'o1: $write("BSRAI"); + 2'o2: $write("BSLLI"); + default: $write("XXX"); + endcase // case (cpu.rALT[10:9]) + 6'o33: case (cpu.rRB[4:2]) + 3'o0: $write("GET"); + 3'o4: $write("PUT"); + 3'o2: $write("NGET"); + 3'o6: $write("NPUT"); + 3'o1: $write("CGET"); + 3'o5: $write("CPUT"); + 3'o3: $write("NCGET"); + 3'o7: $write("NCPUT"); + endcase // case (cpu.rRB[4:2]) + + 6'o40: $write("OR"); + 6'o41: $write("AND"); + 6'o42: if (cpu.rRD == 0) $write(" "); else $write("XOR"); + 6'o43: $write("ANDN"); + 6'o44: case (cpu.rIMM[6:5]) + 2'o0: $write("SRA"); + 2'o1: $write("SRC"); + 2'o2: $write("SRL"); + 2'o3: if (cpu.rIMM[0]) $write("SEXT16"); else $write("SEXT8"); + endcase // case (cpu.rIMM[6:5]) + + 6'o45: $write("MOV"); + 6'o46: case (cpu.rRA[3:2]) + 3'o0: $write("BR"); + 3'o1: $write("BRL"); + 3'o2: $write("BRA"); + 3'o3: $write("BRAL"); + endcase // case (cpu.rRA[3:2]) + + 6'o47: case (cpu.rRD[2:0]) + 3'o0: $write("BEQ"); + 3'o1: $write("BNE"); + 3'o2: $write("BLT"); + 3'o3: $write("BLE"); + 3'o4: $write("BGT"); + 3'o5: $write("BGE"); + default: $write("XXX"); + endcase // case (cpu.rRD[2:0]) + + 6'o50: $write("ORI"); + 6'o51: $write("ANDI"); + 6'o52: $write("XORI"); + 6'o53: $write("ANDNI"); + 6'o54: $write("IMMI"); + 6'o55: case (cpu.rRD[1:0]) + 2'o0: $write("RTSD"); + 2'o1: $write("RTID"); + 2'o2: $write("RTBD"); + default: $write("XXX"); + endcase // case (cpu.rRD[1:0]) + 6'o56: case (cpu.rRA[3:2]) + 3'o0: $write("BRI"); + 3'o1: $write("BRLI"); + 3'o2: $write("BRAI"); + 3'o3: $write("BRALI"); + endcase // case (cpu.rRA[3:2]) + 6'o57: case (cpu.rRD[2:0]) + 3'o0: $write("BEQI"); + 3'o1: $write("BNEI"); + 3'o2: $write("BLTI"); + 3'o3: $write("BLEI"); + 3'o4: $write("BGTI"); + 3'o5: $write("BGEI"); + default: $write("XXX"); + endcase // case (cpu.rRD[2:0]) + + 6'o60: $write("LBU"); + 6'o61: $write("LHU"); + 6'o62: $write("LW"); + 6'o64: $write("SB"); + 6'o65: $write("SH"); + 6'o66: $write("SW"); + + 6'o70: $write("LBUI"); + 6'o71: $write("LHUI"); + 6'o72: $write("LWI"); + 6'o74: $write("SBI"); + 6'o75: $write("SHI"); + 6'o76: $write("SWI"); + + default: $write("XXX"); + endcase // case (cpu.rOPC) + + case (cpu.rOPC[3]) + 1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM); + 1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," "); + endcase // case (cpu.rOPC[3]) + + + // ALU + $write("\t"); + $writeh(" A=",cpu.xecu.rOPA); + $writeh(" B=",cpu.xecu.rOPB); + + case (cpu.rMXALU) + 3'o0: $write(" ADD"); + 3'o1: $write(" LOG"); + 3'o2: $write(" SFT"); + 3'o3: $write(" MOV"); + 3'o4: $write(" MUL"); + 3'o5: $write(" BSF"); + default: $write(" XXX"); + endcase // case (cpu.rMXALU) + $writeh("=h",cpu.xecu.xRESULT); + + // WRITEBACK + $writeh("\tSR=", wMSR," "); + + if (cpu.regf.fRDWE) begin + case (cpu.rMXDST) + 2'o2: begin + if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")"); + if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")"); + end + 2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")"); + 2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")"); + endcase // case (cpu.rMXDST) + end + + // STORE + if (dwb_stb_o & dwb_wre_o) begin + $writeh("RAM(", dwb_adr ,")=", dwb_dat_o); + case (dwb_sel_o) + 4'hF: $write(":L"); + 4'h3,4'hC: $write(":W"); + 4'h1,4'h2,4'h4,4'h8: $write(":B"); + endcase // case (dwb_sel_o) + + end + + end // if (cpu.gena) + + end // always @ (posedge cpu.gclk) + `endif // `ifdef AEMB_SIM_KERNEL + + // synopsys translate_on + +endmodule // aeMB_sim + +/* + $Log: aeMB_sim.v,v $ + Revision 1.2 2008/06/06 09:36:02 sybreon + single thread design + + Revision 1.1 2007/12/23 20:40:45 sybreon + Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. + + */ \ No newline at end of file diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v new file mode 100644 index 000000000..5de2ea619 --- /dev/null +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v @@ -0,0 +1,412 @@ +/* $Id: aeMB_xecu.v,v 1.12 2008/05/11 13:48:46 sybreon Exp $ +** +** AEMB MAIN EXECUTION ALU +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aeMB_xecu (/*AUTOARG*/ + // Outputs + dwb_adr_o, dwb_sel_o, fsl_adr_o, fsl_tag_o, rRESULT, rDWBSEL, + rMSR_IE, rMSR_BIP, + // Inputs + rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT, + rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena + ); + parameter DW=32; + + parameter MUL=0; + parameter BSF=0; + + // DATA WISHBONE + output [DW-1:2] dwb_adr_o; + output [3:0] dwb_sel_o; + + // FSL WISHBONE + output [6:2] fsl_adr_o; + output [1:0] fsl_tag_o; + + // INTERNAL + output [31:0] rRESULT; + output [3:0] rDWBSEL; + output rMSR_IE; + output rMSR_BIP; + input [31:0] rREGA, rREGB; + input [1:0] rMXSRC, rMXTGT; + input [4:0] rRA, rRB; + input [2:0] rMXALU; + input rBRA, rDLY; + input [10:0] rALT; + + input rSTALL; + input [31:0] rSIMM; + input [15:0] rIMM; + input [5:0] rOPC; + input [4:0] rRD; + input [31:0] rDWBDI; + input [31:2] rPC; + + // SYSTEM + input gclk, grst, gena; + + reg rMSR_C, xMSR_C; + reg rMSR_IE, xMSR_IE; + reg rMSR_BE, xMSR_BE; + reg rMSR_BIP, xMSR_BIP; + + wire fSKIP = rBRA & !rDLY; + + // --- OPERAND SELECT + + reg [31:0] rOPA, rOPB; + always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT) + case (rMXSRC) + 2'o0: rOPA <= rREGA; + 2'o1: rOPA <= rRESULT; + 2'o2: rOPA <= rDWBDI; + 2'o3: rOPA <= {rPC, 2'o0}; + endcase // case (rMXSRC) + + always @(/*AUTOSENSE*/rDWBDI or rMXTGT or rREGB or rRESULT or rSIMM) + case (rMXTGT) + 2'o0: rOPB <= rREGB; + 2'o1: rOPB <= rRESULT; + 2'o2: rOPB <= rDWBDI; + 2'o3: rOPB <= rSIMM; + endcase // case (rMXTGT) + + // --- ADD/SUB SELECTOR ---- + + reg rRES_ADDC; + reg [31:0] rRES_ADD; + + wire [31:0] wADD; + wire wADC; + + wire fCCC = !rOPC[5] & rOPC[1]; // & !rOPC[4] + wire fSUB = !rOPC[5] & rOPC[0]; // & !rOPC[4] + wire fCMP = !rOPC[3] & rIMM[1]; // unsigned only + wire wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust + + wire [31:0] wOPA = (fSUB) ? ~rOPA : rOPA; + wire wOPC = (fCCC) ? rMSR_C : fSUB; + + assign {wADC, wADD} = (rOPB + wOPA) + wOPC; // add carry + + always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin + {rRES_ADDC, rRES_ADD} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry + end + + // --- LOGIC SELECTOR -------------------------------------- + + reg [31:0] rRES_LOG; + always @(/*AUTOSENSE*/rOPA or rOPB or rOPC) + case (rOPC[1:0]) + 2'o0: rRES_LOG <= #1 rOPA | rOPB; + 2'o1: rRES_LOG <= #1 rOPA & rOPB; + 2'o2: rRES_LOG <= #1 rOPA ^ rOPB; + 2'o3: rRES_LOG <= #1 rOPA & ~rOPB; + endcase // case (rOPC[1:0]) + + // --- SHIFTER SELECTOR ------------------------------------ + + reg [31:0] rRES_SFT; + reg rRES_SFTC; + + always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA) + case (rIMM[6:5]) + 2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]}; + 2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]}; + 2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]}; + 2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} : + { {(24){rOPA[7]}}, rOPA[7:0], rMSR_C}; + endcase // case (rIMM[6:5]) + + // --- MOVE SELECTOR --------------------------------------- + + wire [31:0] wMSR = {rMSR_C, 3'o0, + 20'h0ED32, + 4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE}; + wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0]; + wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0]; + reg [31:0] rRES_MOV; + always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA + or wMSR) + rRES_MOV <= (fMFSR) ? wMSR : + (fMFPC) ? rPC : + (rRA[3]) ? rOPB : + rOPA; + + // --- MULTIPLIER ------------------------------------------ + // TODO: 2 stage multiplier + + reg [31:0] rRES_MUL, rRES_MUL0, xRES_MUL; + always @(/*AUTOSENSE*/rOPA or rOPB) begin + xRES_MUL <= (rOPA * rOPB); + end + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rRES_MUL <= 32'h0; + // End of automatics + end else if (rSTALL) begin + rRES_MUL <= #1 xRES_MUL; + end + + + // --- BARREL SHIFTER -------------------------------------- + + reg [31:0] rRES_BSF; + reg [31:0] xBSRL, xBSRA, xBSLL; + + // Infer a logical left barrel shifter. + always @(/*AUTOSENSE*/rOPA or rOPB) + xBSLL <= rOPA << rOPB[4:0]; + + // Infer a logical right barrel shifter. + always @(/*AUTOSENSE*/rOPA or rOPB) + xBSRL <= rOPA >> rOPB[4:0]; + + // Infer a arithmetic right barrel shifter. + always @(/*AUTOSENSE*/rOPA or rOPB) + case (rOPB[4:0]) + 5'd00: xBSRA <= rOPA; + 5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]}; + 5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]}; + 5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]}; + 5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]}; + 5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]}; + 5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]}; + 5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]}; + 5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]}; + 5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]}; + 5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]}; + 5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]}; + 5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]}; + 5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]}; + 5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]}; + 5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]}; + 5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]}; + 5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]}; + 5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]}; + 5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]}; + 5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]}; + 5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]}; + 5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]}; + 5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]}; + 5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]}; + 5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]}; + 5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]}; + 5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]}; + 5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]}; + 5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]}; + 5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]}; + 5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]}; + endcase // case (rOPB[4:0]) + + reg [31:0] rBSRL, rBSRA, rBSLL; + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rBSLL <= 32'h0; + rBSRA <= 32'h0; + rBSRL <= 32'h0; + // End of automatics + end else if (rSTALL) begin + rBSRL <= #1 xBSRL; + rBSRA <= #1 xBSRA; + rBSLL <= #1 xBSLL; + end + + always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL) + case (rALT[10:9]) + 2'd0: rRES_BSF <= rBSRL; + 2'd1: rRES_BSF <= rBSRA; + 2'd2: rRES_BSF <= rBSLL; + default: rRES_BSF <= 32'hX; + endcase // case (rALT[10:9]) + + + // --- MSR REGISTER ----------------- + + // C + wire fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP; + wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0); + + always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU + or rOPA or rRES_ADDC or rRES_SFTC) + //if (fSKIP | |rXCE) begin + if (fSKIP) begin + xMSR_C <= rMSR_C; + end else + case (rMXALU) + 3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; + 3'o1: xMSR_C <= rMSR_C; // LOGIC + 3'o2: xMSR_C <= rRES_SFTC; // SHIFT + 3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C; + 3'o4: xMSR_C <= rMSR_C; + 3'o5: xMSR_C <= rMSR_C; + default: xMSR_C <= 1'hX; + endcase // case (rMXALU) + + // IE/BIP/BE + wire fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP; + wire fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP; + wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC); + wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE); + + always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA) + xMSR_IE <= (fINT) ? 1'b0 : + (fRTID) ? 1'b1 : + (fMTS) ? rOPA[1] : + rMSR_IE; + + always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA) + xMSR_BIP <= (fBRK) ? 1'b1 : + (fRTBD) ? 1'b0 : + (fMTS) ? rOPA[3] : + rMSR_BIP; + + always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA) + xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE; + + // --- RESULT SELECTOR ------------------------------------------- + // Selects results from functional units. + reg [31:0] rRESULT, xRESULT; + + // RESULT + always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF + or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT) + if (fSKIP) + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xRESULT <= 32'h0; + // End of automatics + else + case (rMXALU) + 3'o0: xRESULT <= rRES_ADD; + 3'o1: xRESULT <= rRES_LOG; + 3'o2: xRESULT <= rRES_SFT; + 3'o3: xRESULT <= rRES_MOV; + 3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX; + 3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX; + default: xRESULT <= 32'hX; + endcase // case (rMXALU) + + // --- DATA WISHBONE ----- + + reg [3:0] rDWBSEL, xDWBSEL; + assign dwb_adr_o = rRESULT[DW-1:2]; + assign dwb_sel_o = rDWBSEL; + + always @(/*AUTOSENSE*/rOPC or wADD) + case (rOPC[1:0]) + 2'o0: case (wADD[1:0]) // 8'bit + 2'o0: xDWBSEL <= 4'h8; + 2'o1: xDWBSEL <= 4'h4; + 2'o2: xDWBSEL <= 4'h2; + 2'o3: xDWBSEL <= 4'h1; + endcase // case (wADD[1:0]) + 2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit + 2'o2: xDWBSEL <= 4'hF; // 32'bit + 2'o3: xDWBSEL <= 4'h0; // FSL + endcase // case (rOPC[1:0]) + + // --- FSL WISHBONE -------------------- + + reg [14:2] rFSLADR, xFSLADR; + + assign {fsl_adr_o, fsl_tag_o} = rFSLADR[8:2]; + + always @(/*AUTOSENSE*/rALT or rRB) begin + xFSLADR <= {rALT, rRB[3:2]}; + end + + // --- SYNC --- + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rDWBSEL <= 4'h0; + rFSLADR <= 13'h0; + rMSR_BE <= 1'h0; + rMSR_BIP <= 1'h0; + rMSR_C <= 1'h0; + rMSR_IE <= 1'h0; + rRESULT <= 32'h0; + // End of automatics + end else if (gena) begin // if (grst) + rRESULT <= #1 xRESULT; + rDWBSEL <= #1 xDWBSEL; + rMSR_C <= #1 xMSR_C; + rMSR_IE <= #1 xMSR_IE; + rMSR_BE <= #1 xMSR_BE; + rMSR_BIP <= #1 xMSR_BIP; + rFSLADR <= #1 xFSLADR; + end + +endmodule // aeMB_xecu + +/* + $Log: aeMB_xecu.v,v $ + Revision 1.12 2008/05/11 13:48:46 sybreon + Backported Adder from AEMB2_EDK62. + Fixes 64-bit math problem reported by M. Ettus. + + Revision 1.11 2008/01/19 15:57:36 sybreon + Fix MTS during interrupt vectoring bug (reported by M. Ettus). + + Revision 1.10 2007/12/25 22:15:09 sybreon + Stalls pipeline on MUL/BSF instructions results in minor speed improvements. + + Revision 1.9 2007/11/30 16:42:51 sybreon + Minor code cleanup. + + Revision 1.8 2007/11/16 21:52:03 sybreon + Added fsl_tag_o to FSL bus (tag either address or data). + + Revision 1.7 2007/11/14 22:14:34 sybreon + Changed interrupt handling system (reported by M. Ettus). + + Revision 1.6 2007/11/10 16:39:38 sybreon + Upgraded license to LGPLv3. + Significant performance optimisations. + + Revision 1.5 2007/11/09 20:51:52 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.4 2007/11/08 14:17:47 sybreon + Parameterised optional components. + + Revision 1.3 2007/11/03 08:34:55 sybreon + Minor code cleanup. + + Revision 1.2 2007/11/02 19:20:58 sybreon + Added better (beta) interrupt support. + Changed MSR_IE to disabled at reset as per MB docs. + + Revision 1.1 2007/11/02 03:25:41 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. + +*/ \ No newline at end of file diff --git a/usrp2/opencores/aemb/sim/.gitignore b/usrp2/opencores/aemb/sim/.gitignore new file mode 100644 index 000000000..4ef5da542 --- /dev/null +++ b/usrp2/opencores/aemb/sim/.gitignore @@ -0,0 +1,4 @@ +/*.bin +/*.dump +/*.vcd +/*.rom diff --git a/usrp2/opencores/aemb/sim/CODE_DEBUG.sav b/usrp2/opencores/aemb/sim/CODE_DEBUG.sav new file mode 100644 index 000000000..f777173c4 --- /dev/null +++ b/usrp2/opencores/aemb/sim/CODE_DEBUG.sav @@ -0,0 +1,16 @@ +[size] 1400 971 +[pos] -1 -1 +*-5.188574 2727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +testbench.dut.dwb_we_o +@22 +testbench.dut.dwb_sel_o[3:0] +testbench.dut.dwb_adr_o[15:0] +@28 +testbench.dut.sys_clk_i +@22 +testbench.dut.dwb_dat_o[31:0] +@821 +testbench.dut.dwb_dat_i[31:0] +@22 +testbench.dut.dwb_dat_i[31:0] diff --git a/usrp2/opencores/aemb/sim/CVS/Entries b/usrp2/opencores/aemb/sim/CVS/Entries new file mode 100644 index 000000000..bf457ae67 --- /dev/null +++ b/usrp2/opencores/aemb/sim/CVS/Entries @@ -0,0 +1,3 @@ +D/verilog//// +/cversim/1.5/Tue Jan 15 18:38:57 2008// +/iversim/1.5/Tue Jan 15 18:38:57 2008// diff --git a/usrp2/opencores/aemb/sim/CVS/Repository b/usrp2/opencores/aemb/sim/CVS/Repository new file mode 100644 index 000000000..c6bd1aa80 --- /dev/null +++ b/usrp2/opencores/aemb/sim/CVS/Repository @@ -0,0 +1 @@ +aemb/sim diff --git a/usrp2/opencores/aemb/sim/CVS/Root b/usrp2/opencores/aemb/sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/aemb/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/sim/CVS/Template b/usrp2/opencores/aemb/sim/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/aemb/sim/cversim b/usrp2/opencores/aemb/sim/cversim new file mode 100755 index 000000000..0dbb7aea1 --- /dev/null +++ b/usrp2/opencores/aemb/sim/cversim @@ -0,0 +1,22 @@ +#!/bin/sh +# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ +# $Log: cversim,v $ +# Revision 1.5 2007/12/11 00:44:30 sybreon +# Modified for AEMB2 +# +# Revision 1.4 2007/11/30 17:08:30 sybreon +# Moved simulation kernel into code. +# +# Revision 1.3 2007/11/05 10:59:31 sybreon +# Added random seed for simulation. +# +# Revision 1.2 2007/04/12 20:21:33 sybreon +# Moved testbench into /sim/verilog. +# Simulation cleanups. +# +# Revision 1.1 2007/03/09 17:41:55 sybreon +# initial import +# +RANDOM=$(date +%s) +echo "parameter randseed = $RANDOM;" > random.v +cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v diff --git a/usrp2/opencores/aemb/sim/iversim b/usrp2/opencores/aemb/sim/iversim new file mode 100755 index 000000000..9d2384b5a --- /dev/null +++ b/usrp2/opencores/aemb/sim/iversim @@ -0,0 +1,21 @@ +#!/bin/sh +# $Id: iversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ +# $Log: iversim,v $ +# Revision 1.5 2007/12/11 00:44:30 sybreon +# Modified for AEMB2 +# +# Revision 1.4 2007/11/30 17:08:30 sybreon +# Moved simulation kernel into code. +# +# Revision 1.3 2007/11/09 20:50:51 sybreon +# Added log output to iverilog.log +# +# Revision 1.2 2007/11/05 10:59:31 sybreon +# Added random seed for simulation. +# +# Revision 1.1 2007/03/09 17:41:55 sybreon +# initial import +# +RANDOM=$(date +%s) +echo "parameter randseed = $RANDOM;" > random.v +iverilog $@ -DAEMBX_SIMULATION_KERNEL ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out diff --git a/usrp2/opencores/aemb/sim/verilog/CVS/Entries b/usrp2/opencores/aemb/sim/verilog/CVS/Entries new file mode 100644 index 000000000..34e896e80 --- /dev/null +++ b/usrp2/opencores/aemb/sim/verilog/CVS/Entries @@ -0,0 +1,3 @@ +/aemb2.v/1.3/Tue Jan 15 18:38:57 2008// +/edk32.v/1.12/Tue Jan 15 18:38:57 2008// +D diff --git a/usrp2/opencores/aemb/sim/verilog/CVS/Repository b/usrp2/opencores/aemb/sim/verilog/CVS/Repository new file mode 100644 index 000000000..ff3eabf2d --- /dev/null +++ b/usrp2/opencores/aemb/sim/verilog/CVS/Repository @@ -0,0 +1 @@ +aemb/sim/verilog diff --git a/usrp2/opencores/aemb/sim/verilog/CVS/Root b/usrp2/opencores/aemb/sim/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/aemb/sim/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/sim/verilog/CVS/Template b/usrp2/opencores/aemb/sim/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/aemb/sim/verilog/aemb2.v b/usrp2/opencores/aemb/sim/verilog/aemb2.v new file mode 100644 index 000000000..bda1704e3 --- /dev/null +++ b/usrp2/opencores/aemb/sim/verilog/aemb2.v @@ -0,0 +1,242 @@ +/* $Id: aemb2.v,v 1.3 2007/12/28 21:44:50 sybreon Exp $ +** +** AEMB2 TEST BENCH +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aemb2 (); + parameter IWB=16; + parameter DWB=16; + + parameter TXE = 0; ///< thread execution enable + + parameter MUL = 1; ///< enable hardware multiplier + parameter BSF = 1; ///< enable barrel shifter + parameter FSL = 1; ///< enable FSL bus + parameter DIV = 0; ///< enable hardware divider + +`include "random.v" + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [6:2] cwb_adr_o; // From dut of aeMB2_sim.v + wire [31:0] cwb_dat_o; // From dut of aeMB2_sim.v + wire [3:0] cwb_sel_o; // From dut of aeMB2_sim.v + wire cwb_stb_o; // From dut of aeMB2_sim.v + wire [1:0] cwb_tga_o; // From dut of aeMB2_sim.v + wire cwb_wre_o; // From dut of aeMB2_sim.v + wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_sim.v + wire dwb_cyc_o; // From dut of aeMB2_sim.v + wire [31:0] dwb_dat_o; // From dut of aeMB2_sim.v + wire [3:0] dwb_sel_o; // From dut of aeMB2_sim.v + wire dwb_stb_o; // From dut of aeMB2_sim.v + wire dwb_tga_o; // From dut of aeMB2_sim.v + wire dwb_wre_o; // From dut of aeMB2_sim.v + wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_sim.v + wire iwb_stb_o; // From dut of aeMB2_sim.v + wire iwb_tga_o; // From dut of aeMB2_sim.v + wire iwb_wre_o; // From dut of aeMB2_sim.v + // End of automatics + /*AUTOREGINPUT*/ + // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) + reg cwb_ack_i; // To dut of aeMB2_sim.v + reg dwb_ack_i; // To dut of aeMB2_sim.v + reg iwb_ack_i; // To dut of aeMB2_sim.v + reg sys_clk_i; // To dut of aeMB2_sim.v + reg sys_int_i; // To dut of aeMB2_sim.v + reg sys_rst_i; // To dut of aeMB2_sim.v + // End of automatics + + // INITIAL SETUP ////////////////////////////////////////////////////// + + //reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i; + reg svc; + integer inttime; + integer seed; + integer theend; + + always #5 sys_clk_i = ~sys_clk_i; + + initial begin + //$dumpfile("dump.vcd"); + //$dumpvars(1,dut, dut.bpcu); + end + + initial begin + seed = randseed; + theend = 0; + svc = 0; + sys_clk_i = $random(seed); + sys_rst_i = 1; + sys_int_i = 0; + #50 sys_rst_i = 0; + #3500000 $finish; + end + + // FAKE MEMORY //////////////////////////////////////////////////////// + + reg [31:0] rom [0:65535]; + reg [31:0] ram[0:65535]; + reg [31:0] dwblat; + reg [15:2] dadr, iadr; + + wire [31:0] dwb_dat_t = ram[dwb_adr_o]; + wire [31:0] iwb_dat_i = rom[iadr]; + wire [31:0] dwb_dat_i = ram[dadr]; + wire [31:0] cwb_dat_i = cwb_adr_o; + +`ifdef POSEDGE +`else // !`ifdef POSEDGE + + always @(negedge sys_clk_i) + if (sys_rst_i) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + cwb_ack_i <= 1'h0; + dwb_ack_i <= 1'h0; + iwb_ack_i <= 1'h0; + // End of automatics + end else begin + iwb_ack_i <= #1 iwb_stb_o; + dwb_ack_i <= #1 dwb_stb_o; + cwb_ack_i <= #1 cwb_stb_o; + end // else: !if(sys_rst_i) + + always @(negedge sys_clk_i) begin + iadr <= #1 iwb_adr_o; + dadr <= #1 dwb_adr_o; + + if (dwb_wre_o & dwb_stb_o) begin + case (dwb_sel_o) + 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; + 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; + 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; + 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; + 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; + 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; + 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; + endcase // case (dwb_sel_o) + end // if (dwb_we_o & dwb_stb_o) + end // always @ (negedge sys_clk_i) + +`endif // !`ifdef POSEDGE + + + integer i; + initial begin + for (i=0;i<65535;i=i+1) begin + ram[i] <= $random; + end + #1 $readmemh("dump.vmem",rom); + #1 $readmemh("dump.vmem",ram); + end + + // DISPLAY OUTPUTS /////////////////////////////////////////////////// + + integer rnd; + + always @(posedge sys_clk_i) begin + + // Interrupt Monitors + if (!dut.sim.rMSR_IE) begin + rnd = $random % 30; + inttime = $stime + 1000 + (rnd*rnd * 10); + end + if ($stime > inttime) begin + sys_int_i = 1; + svc = 0; + end + if (($stime > inttime + 500) && !svc) begin + $display("\n\t*** INTERRUPT TIMEOUT ***", inttime); + $finish; + end + if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; + /* + if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin + svc = 1; + //$display("\nLATENCY: ", ($stime - inttime)/10); + end + */ + + // Pass/Fail Monitors + if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin + $display("\n\tFAIL"); + $finish; + end + + if (iwb_dat_i == 32'hb8000000) begin + theend = theend + 1; + end + + if (theend == 5) begin + $display("\n\t*** PASSED ALL TESTS ***"); + $finish; + end + + end // always @ (posedge sys_clk_i) + + // INTERNAL WIRING //////////////////////////////////////////////////// + + aeMB2_sim + #(/*AUTOINSTPARAM*/ + // Parameters + .IWB (IWB), + .DWB (DWB), + .TXE (TXE), + .MUL (MUL), + .BSF (BSF), + .FSL (FSL), + .DIV (DIV)) + dut (/*AUTOINST*/ + // Outputs + .cwb_adr_o (cwb_adr_o[6:2]), + .cwb_dat_o (cwb_dat_o[31:0]), + .cwb_sel_o (cwb_sel_o[3:0]), + .cwb_stb_o (cwb_stb_o), + .cwb_tga_o (cwb_tga_o[1:0]), + .cwb_wre_o (cwb_wre_o), + .dwb_adr_o (dwb_adr_o[DWB-1:2]), + .dwb_cyc_o (dwb_cyc_o), + .dwb_dat_o (dwb_dat_o[31:0]), + .dwb_sel_o (dwb_sel_o[3:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_tga_o (dwb_tga_o), + .dwb_wre_o (dwb_wre_o), + .iwb_adr_o (iwb_adr_o[IWB-1:2]), + .iwb_stb_o (iwb_stb_o), + .iwb_tga_o (iwb_tga_o), + .iwb_wre_o (iwb_wre_o), + // Inputs + .cwb_ack_i (cwb_ack_i), + .cwb_dat_i (cwb_dat_i[31:0]), + .dwb_ack_i (dwb_ack_i), + .dwb_dat_i (dwb_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .iwb_dat_i (iwb_dat_i[31:0]), + .sys_clk_i (sys_clk_i), + .sys_int_i (sys_int_i), + .sys_rst_i (sys_rst_i)); + +endmodule // edk32 + +/* $Log $ */ + +// Local Variables: +// verilog-library-directories:("." "../../rtl/verilog/") +// verilog-library-files:("") +// End: diff --git a/usrp2/opencores/aemb/sim/verilog/edk32.v b/usrp2/opencores/aemb/sim/verilog/edk32.v new file mode 100644 index 000000000..68465e9e0 --- /dev/null +++ b/usrp2/opencores/aemb/sim/verilog/edk32.v @@ -0,0 +1,288 @@ +/* $Id: edk32.v,v 1.12 2007/12/23 20:40:51 sybreon Exp $ +** +** AEMB EDK 3.2 Compatible Core TEST +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +`define AEMB_SIMULATION_KERNEL + +module edk32 (); + +`include "random.v" + + // INITIAL SETUP ////////////////////////////////////////////////////// + + reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i; + reg svc; + integer inttime; + integer seed; + integer theend; + + always #5 sys_clk_i = ~sys_clk_i; + + initial begin + //$dumpfile("dump.vcd"); + //$dumpvars(1,dut); + end + + initial begin + seed = randseed; + theend = 0; + svc = 0; + sys_clk_i = $random(seed); + sys_rst_i = 1; + sys_int_i = 0; + sys_exc_i = 0; + #50 sys_rst_i = 0; + end + + initial fork + //inttime $display("FSADFASDFSDAF"); + //#10000 sys_int_i = 1; + //#1100 sys_int_i = 0; + //#100000 $displayh("\nTest Completed."); + //#4000 $finish; + join + + + // FAKE MEMORY //////////////////////////////////////////////////////// + + wire fsl_stb_o; + wire fsl_wre_o; + wire [31:0] fsl_dat_o; + wire [31:0] fsl_dat_i; + wire [6:2] fsl_adr_o; + + wire [15:2] iwb_adr_o; + wire iwb_stb_o; + wire dwb_stb_o; + reg [31:0] rom [0:65535]; + wire [31:0] iwb_dat_i; + reg iwb_ack_i, dwb_ack_i, fsl_ack_i; + + reg [31:0] ram[0:65535]; + wire [31:0] dwb_dat_i; + reg [31:0] dwblat; + wire dwb_we_o; + reg [15:2] dadr,iadr; + wire [3:0] dwb_sel_o; + wire [31:0] dwb_dat_o; + wire [15:2] dwb_adr_o; + wire [31:0] dwb_dat_t; + + initial begin + dwb_ack_i = 0; + iwb_ack_i = 0; + fsl_ack_i = 0; + end + + assign dwb_dat_t = ram[dwb_adr_o]; + assign iwb_dat_i = ram[iadr]; + assign dwb_dat_i = ram[dadr]; + assign fsl_dat_i = fsl_adr_o; + +`ifdef POSEDGE + + always @(posedge sys_clk_i) + if (sys_rst_i) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + dwb_ack_i <= 1'h0; + fsl_ack_i <= 1'h0; + iwb_ack_i <= 1'h0; + // End of automatics + end else begin + iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i; + dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i; + fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i; + end // else: !if(sys_rst_i) + + always @(posedge sys_clk_i) begin + iadr <= #1 iwb_adr_o; + dadr <= #1 dwb_adr_o; + + if (dwb_we_o & dwb_stb_o) begin + case (dwb_sel_o) + 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; + 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; + 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; + 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; + 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; + 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; + 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; + endcase // case (dwb_sel_o) + end // if (dwb_we_o & dwb_stb_o) + end // always @ (posedge sys_clk_i) + +`else // !`ifdef POSEDGE + + always @(negedge sys_clk_i) + if (sys_rst_i) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + dwb_ack_i <= 1'h0; + fsl_ack_i <= 1'h0; + iwb_ack_i <= 1'h0; + // End of automatics + end else begin + iwb_ack_i <= #1 iwb_stb_o; + dwb_ack_i <= #1 dwb_stb_o; + fsl_ack_i <= #1 fsl_stb_o; + end // else: !if(sys_rst_i) + + always @(negedge sys_clk_i) begin + iadr <= #1 iwb_adr_o; + dadr <= #1 dwb_adr_o; + + if (dwb_we_o & dwb_stb_o) begin + case (dwb_sel_o) + 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; + 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; + 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; + 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; + 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; + 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; + 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; + endcase // case (dwb_sel_o) + end // if (dwb_we_o & dwb_stb_o) + end // always @ (negedge sys_clk_i) + +`endif // !`ifdef POSEDGE + + + integer i; + initial begin + for (i=0;i<65535;i=i+1) begin + ram[i] <= $random; + end + #1 $readmemh("dump.vmem",ram); + end + + // DISPLAY OUTPUTS /////////////////////////////////////////////////// + + integer rnd; + + always @(posedge sys_clk_i) begin + + // Interrupt Monitors + if (!dut.cpu.rMSR_IE) begin + rnd = $random % 30; + inttime = $stime + 1000 + (rnd*rnd * 10); + end + if ($stime > inttime) begin + sys_int_i = 1; + svc = 0; + end + if (($stime > inttime + 500) && !svc) begin + $display("\n\t*** INTERRUPT TIMEOUT ***", inttime); + $finish; + end + if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; + if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin + svc = 1; + //$display("\nLATENCY: ", ($stime - inttime)/10); + end + + // Pass/Fail Monitors + if (dwb_we_o & (dwb_dat_o == "FAIL")) begin + $display("\n\tFAIL"); + $finish; + end + + if (iwb_dat_i == 32'hb8000000) begin + theend = theend + 1; + end + + if (theend == 5) begin + $display("\n\t*** PASSED ALL TESTS ***"); + $finish; + end + end // always @ (posedge sys_clk_i) + + // INTERNAL WIRING //////////////////////////////////////////////////// + + aeMB_sim #(16,16) + dut ( + .sys_int_i(sys_int_i), + .dwb_ack_i(dwb_ack_i), + .dwb_stb_o(dwb_stb_o), + .dwb_adr_o(dwb_adr_o), + .dwb_dat_o(dwb_dat_o), + .dwb_dat_i(dwb_dat_i), + .dwb_wre_o(dwb_we_o), + .dwb_sel_o(dwb_sel_o), + + .fsl_ack_i(fsl_ack_i), + .fsl_stb_o(fsl_stb_o), + .fsl_adr_o(fsl_adr_o), + .fsl_dat_o(fsl_dat_o), + .fsl_dat_i(fsl_dat_i), + .fsl_wre_o(fsl_we_o), + + .iwb_adr_o(iwb_adr_o), + .iwb_dat_i(iwb_dat_i), + .iwb_stb_o(iwb_stb_o), + .iwb_ack_i(iwb_ack_i), + .sys_clk_i(sys_clk_i), + .sys_rst_i(sys_rst_i) + ); + +endmodule // edk32 + +/* + $Log: edk32.v,v $ + Revision 1.12 2007/12/23 20:40:51 sybreon + Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. + + Revision 1.11 2007/12/11 00:44:31 sybreon + Modified for AEMB2 + + Revision 1.10 2007/11/30 17:08:30 sybreon + Moved simulation kernel into code. + + Revision 1.9 2007/11/20 18:36:00 sybreon + Removed unnecessary byte acrobatics with VMEM data. + + Revision 1.8 2007/11/18 19:41:45 sybreon + Minor simulation fixes. + + Revision 1.7 2007/11/14 22:11:41 sybreon + Added posedge/negedge bus interface. + Modified interrupt test system. + + Revision 1.6 2007/11/13 23:37:28 sybreon + Updated simulation to also check BRI 0x00 instruction. + + Revision 1.5 2007/11/09 20:51:53 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.4 2007/11/08 14:18:00 sybreon + Parameterised optional components. + + Revision 1.3 2007/11/05 10:59:31 sybreon + Added random seed for simulation. + + Revision 1.2 2007/11/02 19:16:10 sybreon + Added interrupt simulation. + Changed "human readable" simulation output. + + Revision 1.1 2007/11/02 03:25:45 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. + */ \ No newline at end of file diff --git a/usrp2/opencores/aemb/sw/CVS/Entries b/usrp2/opencores/aemb/sw/CVS/Entries new file mode 100644 index 000000000..45725bed9 --- /dev/null +++ b/usrp2/opencores/aemb/sw/CVS/Entries @@ -0,0 +1,2 @@ +D/c//// +/gccrom/1.13/Sun Jan 20 19:47:57 2008// diff --git a/usrp2/opencores/aemb/sw/CVS/Repository b/usrp2/opencores/aemb/sw/CVS/Repository new file mode 100644 index 000000000..6de31b8b0 --- /dev/null +++ b/usrp2/opencores/aemb/sw/CVS/Repository @@ -0,0 +1 @@ +aemb/sw diff --git a/usrp2/opencores/aemb/sw/CVS/Root b/usrp2/opencores/aemb/sw/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/aemb/sw/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/sw/CVS/Template b/usrp2/opencores/aemb/sw/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/aemb/sw/c/CVS/Entries b/usrp2/opencores/aemb/sw/c/CVS/Entries new file mode 100644 index 000000000..4867b6318 --- /dev/null +++ b/usrp2/opencores/aemb/sw/c/CVS/Entries @@ -0,0 +1,3 @@ +/aeMB_testbench.c/1.14/Tue Jan 15 18:38:57 2008// +/libaemb.h/1.3/Tue Jan 15 18:38:57 2008// +D diff --git a/usrp2/opencores/aemb/sw/c/CVS/Repository b/usrp2/opencores/aemb/sw/c/CVS/Repository new file mode 100644 index 000000000..86c411d03 --- /dev/null +++ b/usrp2/opencores/aemb/sw/c/CVS/Repository @@ -0,0 +1 @@ +aemb/sw/c diff --git a/usrp2/opencores/aemb/sw/c/CVS/Root b/usrp2/opencores/aemb/sw/c/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/aemb/sw/c/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/aemb/sw/c/CVS/Template b/usrp2/opencores/aemb/sw/c/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/aemb/sw/c/aeMB_testbench.c b/usrp2/opencores/aemb/sw/c/aeMB_testbench.c new file mode 100644 index 000000000..c3402e0ef --- /dev/null +++ b/usrp2/opencores/aemb/sw/c/aeMB_testbench.c @@ -0,0 +1,385 @@ +/* $Id: aeMB_testbench.c,v 1.14 2007/12/28 21:44:04 sybreon Exp $ +** +** AEMB Function Verification C Testbench +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU General Public License as published by +** the Free Software Foundation, either version 3 of the License, or +** (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +** License for more details. +** +** You should have received a copy of the GNU General Public License +** along with AEMB. If not, see . +*/ + +#include +#include +#include + +#include "libaemb.h" + +/** + INTERRUPT TEST + + This tests for the following: + - Pointer addressing + - Interrupt handling + */ + +void __attribute__ ((interrupt_handler)) int_handler(); +volatile int service = 0xDEADDEAD; + +void int_service() +{ + int* pio = (int*)0xFFFFFFFC; + *pio = 0x52544E49; // "INTR" + service = 0; +} + +void int_handler() +{ + int_service(); +} + +/** + INTERRUPT TEST ROUTINE +*/ +int int_test () +{ + // Delay loop until hardware interrupt triggers + volatile int i; + for (i=0; i < 999; i++) { + if (service == 0) return 0; + }; + + return -1; +} + +/** + FIBONACCI TEST + http://en.literateprograms.org/Fibonacci_numbers_(C) + + This tests for the following: + - Recursion & Iteration + - 32/16/8-bit data handling +*/ + +unsigned int fib_slow(unsigned int n) +{ + return n < 2 ? n : fib_slow(n-1) + fib_slow(n-2); +} + +unsigned int fib_fast(unsigned int n) +{ + unsigned int a[3]; + unsigned int *p=a; + unsigned int i; + + for(i=0; i<=n; ++i) { + if(i<2) *p=i; + else { + if(p==a) *p=*(a+1)+*(a+2); + else if(p==a+1) *p=*a+*(a+2); + else *p=*a+*(a+1); + } + if(++p>a+2) p=a; + } + + return p==a?*(p+2):*(p-1); +} + +int fib_test(int max) { + unsigned int n; + unsigned int fast, slow; + // 32-bit LUT + unsigned int fib_lut32[] = { + 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 + }; + // 16-bit LUT + unsigned short fib_lut16[] = { + 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 + }; + // 8-bit LUT + unsigned char fib_lut8[] = { + 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 + }; + + for (n=0;n a) goto b_larger; + while (1) { + a = a % b; + if (a == 0) return b; + b_larger: + b = b % a; + if (b == 0) return a; + } +} + +int euclid_test(int max) +{ + int n; + int euclid; + // Random Numbers + int euclid_a[] = { + 1804289383, 1681692777, 1957747793, 719885386, 596516649, + 1025202362, 783368690, 2044897763, 1365180540, 304089172, + 35005211, 294702567, 336465782, 278722862 + }; + int euclid_b[] = { + 846930886, 1714636915, 424238335, 1649760492, 1189641421, + 1350490027, 1102520059, 1967513926, 1540383426, 1303455736, + 521595368, 1726956429, 861021530, 233665123 + }; + + // GCD + int euclid_lut[] = { + 1, 1, 1, 2, 1, 1, 1, 1, 6, 4, 1, 3, 2, 1 + }; + + for (n=0;n 0.0) + { + xn = (i+(i-1))/2.0; + break; + } + } + while (!(iters++ >= 100 + || x == xn)) + { + x = xn; + xn = x - (x * x - n) / (2 * x); + } + return xn; +} + +int newton_test (int max) { + int n; + float newt; + // 32-bit LUT + float newt_lut[] = { + 0.000000000000000000000000, + 1.000000000000000000000000, + 1.414213538169860839843750, + 1.732050776481628417968750, + 2.000000000000000000000000, + 2.236068010330200195312500, + 2.449489831924438476562500, + 2.645751237869262695312500, + 2.828427076339721679687500, + 3.000000000000000000000000, + 3.162277698516845703125000, + 3.316624879837036132812500, + 3.464101552963256835937500, + 3.605551242828369140625000, + 3.741657495498657226562500 + }; + + for (n=0;n_errno; + // return &errnum; +} +*/ + +int malloc_test() +{ + void *alloc; + + alloc = (void *)malloc(256); // allocate 32 bytes + + if (alloc == NULL) + return -1; + else + return (int) alloc; +} + +/** + MAIN TEST PROGRAMME + + This is the main test procedure. It will output signals onto the + MPI port that is checked by the testbench. + */ + +int main () +{ + // Message Passing Port + int* mpi = (int*)0xFFFFFFFF; + + // Number of each test to run + int max = 10; + + // lock T0 if it's multi-threaded + /* + if ((aemb_isthreaded() == 0) && (aemb_isthread1() != 0)) { + while (1) { + asm volatile ("nop;"); + } + } + */ + + // Enable Global Interrupts + aemb_enable_interrupt(); + + // INT TEST + //if (int_test() == -1) { *mpi = 0x4641494C; } + + // TEST MALLOC + if (malloc_test() == -1) { *mpi = 0x4641494C; } + + // FSL TEST + //if (fsl_test() == -1) { *mpi = 0x4641494C; } + + // Fibonacci Test + if (fib_test(max) == -1) { *mpi = 0x4641494C; } + + // Euclid Test + if (euclid_test(max) == -1) { *mpi = 0x4641494C; } + + // Newton-Rhapson Test + if (newton_test(max) == -1) { *mpi = 0x4641494C; } + + // Disable Global Interrupts + aemb_disable_interrupt(); + + // ALL PASSED + return 0; +} + +/* + HISTORY + $Log: aeMB_testbench.c,v $ + Revision 1.14 2007/12/28 21:44:04 sybreon + Added malloc() test + + Revision 1.13 2007/12/11 00:44:31 sybreon + Modified for AEMB2 + + Revision 1.12 2007/11/18 19:41:45 sybreon + Minor simulation fixes. + + Revision 1.11 2007/11/14 23:41:06 sybreon + Fixed minor interrupt test typo. + + Revision 1.10 2007/11/14 22:12:02 sybreon + Added interrupt test routine. + + Revision 1.9 2007/11/09 20:51:53 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.8 2007/11/03 08:40:18 sybreon + Minor code cleanup. + + Revision 1.7 2007/11/02 18:32:19 sybreon + Enable MSR_IE with software. + + Revision 1.6 2007/04/30 15:57:10 sybreon + Removed byte acrobatics. + + Revision 1.5 2007/04/27 15:17:59 sybreon + Added code documentation. + Added new tests that test floating point, modulo arithmetic and multiplication/division. + + Revision 1.4 2007/04/25 22:15:05 sybreon + Added support for 8-bit and 16-bit data types. + + Revision 1.3 2007/04/04 14:09:04 sybreon + Added initial interrupt/exception support. + + Revision 1.2 2007/04/04 06:07:45 sybreon + Fixed C code bug which passes the test + + Revision 1.1 2007/03/09 17:41:57 sybreon + initial import +*/ diff --git a/usrp2/opencores/aemb/sw/c/endian-test.c b/usrp2/opencores/aemb/sw/c/endian-test.c new file mode 100644 index 000000000..b585f7a30 --- /dev/null +++ b/usrp2/opencores/aemb/sw/c/endian-test.c @@ -0,0 +1,86 @@ + +#include "memory_map.h" + +int main() { + char *p = (char *)0x4000; + short *q = (short *)0x5000; + int *r= (int *)0x6000; + + int *output = (int *)0x7000; + + char s; + short t; + int u; + + // Write + // Bytes + *p = (char)1; + p++; + *p = (char)2; + p++; + *p = (char)3; + p++; + *p = (char)4; + p++; + *p = (char)5; + + // Words + *q = (short) 0x1112; + q++; + *q = (short) 0x1314; + q++; + *q = (short) 0x1516; + + // Double Words + *r = 0x21222324; + r++; + *r = 0x25262728; + r++; + *r = 0x292a2b2c; + + + // Read + p = (char *)0x6000; + s = *p; + if(s == 0x21) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + p = (char *)0x6001; + s = *p; + if(s == 0x22) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + p = (char *)0x6002; + s = *p; + if(s == 0x23) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + + p = (char *)0x6003; + s = *p; + if(s == 0x24) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + q = (short *)0x4000; + t = *q; + if(t == 0x0102) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + r = (int *)0x4000; + u = *r; + if(u == 0x01020304) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + +} diff --git a/usrp2/opencores/aemb/sw/c/libaemb.h b/usrp2/opencores/aemb/sw/c/libaemb.h new file mode 100644 index 000000000..329a327a1 --- /dev/null +++ b/usrp2/opencores/aemb/sw/c/libaemb.h @@ -0,0 +1,218 @@ +/* $Id: libaemb.h,v 1.3 2007/12/16 03:26:37 sybreon Exp $ +** +** AEMB2 CUSTOM LIBRARY +** +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +#ifndef LIBAEMB_H +#define LIBAEMB_H + +#define AEMB_TXE 0x0100 +#define AEMB_TXP 0x0400 +#define AEMB_TX0 0x0300 +#define AEMB_TX1 0x0700 +#define AEMB_MSK 0x0F00 + +#define AEMB_BIP 0x0008 +#define AEMB_CCC 0x0004 +#define AEMB_ITE 0x0002 +#define AEMB_BLE 0x0001 + + +// Linker symbols +extern void* _STACK_SIZE; +extern void* _stack_end; + + +void aemb_hook_init () asm ("_program_init"); +void aemb_hook_clean () asm ("_program_clean"); + +inline void aemb_enable_interrupt (); +inline void aemb_disable_interrupt (); +inline int aemb_isthread1(); +inline int aemb_isthread0(); +inline int aemb_isthreaded(); + +/*! +* Assembly macro to enable MSR_IE +*/ +void aemb_enable_interrupt () +{ + int msr, tmp; + asm volatile ("mfs %0, rmsr;" + "ori %1, %0, 0x02;" + "mts rmsr, %1;" + : "=r"(msr) + : "r" (tmp) + ); +} + +/*! +* Assembly macro to disable MSR_IE +*/ +void aemb_disable_interrupt () +{ + int msr, tmp; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, 0xFD;" + "mts rmsr, %1;" + : "=r"(msr) + : "r" (tmp) + ); +} + +/*! +* Bootstrap Hook Override +*/ + +void aemb_hook_init () +{ + int msr, tmp; + int stk_end, stk_siz; + + /* + // Check to see if hardware threads are enabled + if (((msr & AEMB_TXE) != AEMB_TXE) || + // Check to see if second thread is started + ((msr & AEMB_TX1) == AEMB_TX1)) return; + */ + //return; + asm volatile ("mfs %0, rmsr;" + // Check for BIP + "andi %1, %0, %5;" + "xori %1, %1, %5;" + "beqi %1, 44;" + + // Check for TXE + "andi %1, %0, %2;" + "xori %1, %1, %2;" + "bnei %1, 36;" + + // Check for TX1 + "andi %1, %0, %3;" + "xori %1, %1, %3;" + "beqi %1, 20;" + + // reallocate stack pointer for T0 + "ori %1, r0, %4;" + "sra %1, %1;" + "rsubk r1, %1, r1;" + + // reboot the machine + //"brki r0, _crtinit;" + "brid 0;" + "nop;" + + // clear BIP + "andni %1, %0, %5;" + "mts rmsr, %1;" + + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE), "i"(AEMB_BIP) + ); + +} + +/*! + Undo the changes made by programme init +*/ + +void aemb_hook_clean () +{ + int msr, tmp; + int stk_end, stk_siz; + + /* + // Check to see if hardware threads are enabled + if (((msr & AEMB_TXE) != AEMB_TXE) || + // Check to see if second thread is started + ((msr & AEMB_TX1) == AEMB_TX1)) return; + */ + return; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, %2;" + "xori %1, %1, %2;" + "bnei %1, 28;" + "andi %1, %0, %3;" + "xori %1, %1, %3;" + "beqi %1, 16;" + + // reallocate stack pointer for T0 + "ori %1, r0, %4;" + "sra %1, %1;" + "addk r1, %1, r1;" + + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE) + ); + + +} + +/* Checks if it's T1, and returns 0 if true */ + +int aemb_isthread1 () +{ + int msr, tmp, res; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, %3;" + "xori %1, %1, %3;" + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXE), "i"(AEMB_TXP) + ); + return tmp; +} + +/* Checks if it's T0, and returns 0 if true */ + +int aemb_isthread0 () +{ + int msr, tmp, res; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, %3;" + "xori %1, %1, %2;" + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXP), "i"(AEMB_MSK) + ); + return tmp; +} + +/* Checks if TXE is available, and returns 0 if true */ + +int aemb_isthreaded () +{ + int msr, tmp, res; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, %2;" + "xori %1, %1, %2;" + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXE), "i"(AEMB_MSK) + ); + return tmp; +} + +#endif + +/* $Log: libaemb.h,v $ +/* Revision 1.3 2007/12/16 03:26:37 sybreon +/* Made T0 loop. +/* +/* Revision 1.1 2007/12/11 00:44:04 sybreon +/* initial import +/* */ diff --git a/usrp2/opencores/aemb/sw/gccrom b/usrp2/opencores/aemb/sw/gccrom new file mode 100755 index 000000000..f6e581f1f --- /dev/null +++ b/usrp2/opencores/aemb/sw/gccrom @@ -0,0 +1,62 @@ +#!/bin/sh +# $Id: gccrom,v 1.13 2008/01/19 16:42:54 sybreon Exp $ + +# Compile using C++ pre-processor +mb-g++ -g -Wl,-defsym -Wl,_HEAP_SIZE=0x800 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul -mno-clearbss $@ -o rom.elf -lc_m_bs -lm_m_bs && \ + +# Create a text listing of the compiled code +mb-objdump -DSC rom.elf > rom.dump && \ + +# Convert the ELF file to an SREC file +mb-objcopy -O srec rom.elf rom.srec && \ + +# Generate a Verilog VMEM file from the SREC file +srec_cat rom.srec -o ../sim/dump.vmem -vmem 32 && \ + +# Cleanup code +rm rom.srec && \ + +# Say Cheeze! +echo "ROM generated" + +# $Log: gccrom,v $ +# Revision 1.13 2008/01/19 16:42:54 sybreon +# Uses multiplier + barrel shifter as default. +# +# Revision 1.12 2007/12/11 00:44:32 sybreon +# Modified for AEMB2 +# +# Revision 1.11 2007/11/30 17:09:27 sybreon +# Minor code cleanup. +# +# Revision 1.10 2007/11/20 18:35:34 sybreon +# Generate VMEM instead of HEX dumps of programme. +# +# Revision 1.9 2007/11/18 19:41:46 sybreon +# Minor simulation fixes. +# +# Revision 1.8 2007/11/09 20:52:37 sybreon +# Added some compilation optimisations. +# +# Revision 1.7 2007/11/04 05:16:25 sybreon +# Added -msoft-float and -mxl-soft-div compiler flags. +# +# Revision 1.6 2007/11/02 03:25:46 sybreon +# New EDK 3.2 compatible design with optional barrel-shifter and multiplier. +# Fixed various minor data hazard bugs. +# Code compatible with -O0/1/2/3/s generated code. +# +# Revision 1.5 2007/10/22 19:14:38 sybreon +# Recommended to compile code with -O2/3/s +# +# Revision 1.4 2007/04/30 15:57:31 sybreon +# Modified compilation sequence. +# +# Revision 1.3 2007/04/25 22:15:06 sybreon +# Added support for 8-bit and 16-bit data types. +# +# Revision 1.2 2007/04/04 06:14:39 sybreon +# Minor changes +# +# Revision 1.1 2007/03/09 17:41:56 sybreon +# initial import diff --git a/usrp2/opencores/i2c/CVS/Entries b/usrp2/opencores/i2c/CVS/Entries new file mode 100644 index 000000000..d6947544a --- /dev/null +++ b/usrp2/opencores/i2c/CVS/Entries @@ -0,0 +1,8 @@ +D/bench//// +D/doc//// +D/documentation//// +D/rtl//// +D/sim//// +D/software//// +D/verilog//// +D/vhdl//// diff --git a/usrp2/opencores/i2c/CVS/Repository b/usrp2/opencores/i2c/CVS/Repository new file mode 100644 index 000000000..1a9fe8960 --- /dev/null +++ b/usrp2/opencores/i2c/CVS/Repository @@ -0,0 +1 @@ +i2c diff --git a/usrp2/opencores/i2c/CVS/Root b/usrp2/opencores/i2c/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/CVS/Template b/usrp2/opencores/i2c/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/bench/CVS/Entries b/usrp2/opencores/i2c/bench/CVS/Entries new file mode 100644 index 000000000..428c5622d --- /dev/null +++ b/usrp2/opencores/i2c/bench/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/opencores/i2c/bench/CVS/Repository b/usrp2/opencores/i2c/bench/CVS/Repository new file mode 100644 index 000000000..5597c8aac --- /dev/null +++ b/usrp2/opencores/i2c/bench/CVS/Repository @@ -0,0 +1 @@ +i2c/bench diff --git a/usrp2/opencores/i2c/bench/CVS/Root b/usrp2/opencores/i2c/bench/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/bench/CVS/Template b/usrp2/opencores/i2c/bench/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/bench/verilog/CVS/Entries b/usrp2/opencores/i2c/bench/verilog/CVS/Entries new file mode 100644 index 000000000..2dd779100 --- /dev/null +++ b/usrp2/opencores/i2c/bench/verilog/CVS/Entries @@ -0,0 +1,5 @@ +/i2c_slave_model.v/1.7/Mon Sep 4 09:08:51 2006// +/spi_slave_model.v/1.1/Sat Feb 28 15:32:54 2004// +/tst_bench_top.v/1.8/Mon Sep 4 09:08:51 2006// +/wb_master_model.v/1.4/Sat Feb 28 15:40:42 2004// +D diff --git a/usrp2/opencores/i2c/bench/verilog/CVS/Repository b/usrp2/opencores/i2c/bench/verilog/CVS/Repository new file mode 100644 index 000000000..b37c379e9 --- /dev/null +++ b/usrp2/opencores/i2c/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +i2c/bench/verilog diff --git a/usrp2/opencores/i2c/bench/verilog/CVS/Root b/usrp2/opencores/i2c/bench/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/bench/verilog/CVS/Template b/usrp2/opencores/i2c/bench/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v b/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v new file mode 100644 index 000000000..0c8ecae0d --- /dev/null +++ b/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v @@ -0,0 +1,360 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant synthesizable I2C Slave model //// +//// //// +//// //// +//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// +//// John Sheahan (jrsheahan@optushome.com.au) //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001,2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_slave_model.v,v 1.7 2006/09/04 09:08:51 rherveille Exp $ +// +// $Date: 2006/09/04 09:08:51 $ +// $Revision: 1.7 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_slave_model.v,v $ +// Revision 1.7 2006/09/04 09:08:51 rherveille +// fixed (n)ack generation +// +// Revision 1.6 2005/02/28 11:33:48 rherveille +// Fixed Tsu:sta timing check. +// Added Thd:sta timing check. +// +// Revision 1.5 2003/12/05 11:05:19 rherveille +// Fixed slave address MSB='1' bug +// +// Revision 1.4 2003/09/11 08:25:37 rherveille +// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. +// +// Revision 1.3 2002/10/30 18:11:06 rherveille +// Added timing tests to i2c_model. +// Updated testbench. +// +// Revision 1.2 2002/03/17 10:26:38 rherveille +// Fixed some race conditions in the i2c-slave model. +// Added debug information. +// Added headers. +// + +`include "timescale.v" + +module i2c_slave_model (scl, sda); + + // + // parameters + // + parameter I2C_ADR = 7'b001_0000; + + // + // input && outpus + // + input scl; + inout sda; + + // + // Variable declaration + // + wire debug = 1'b1; + + reg [7:0] mem [3:0]; // initiate memory + reg [7:0] mem_adr; // memory address + reg [7:0] mem_do; // memory data output + + reg sta, d_sta; + reg sto, d_sto; + + reg [7:0] sr; // 8bit shift register + reg rw; // read/write direction + + wire my_adr; // my address called ?? + wire i2c_reset; // i2c-statemachine reset + reg [2:0] bit_cnt; // 3bit downcounter + wire acc_done; // 8bits transfered + reg ld; // load downcounter + + reg sda_o; // sda-drive level + wire sda_dly; // delayed version of sda + + // statemachine declaration + parameter idle = 3'b000; + parameter slave_ack = 3'b001; + parameter get_mem_adr = 3'b010; + parameter gma_ack = 3'b011; + parameter data = 3'b100; + parameter data_ack = 3'b101; + + reg [2:0] state; // synopsys enum_state + + // + // module body + // + + initial + begin + sda_o = 1'b1; + state = idle; + end + + // generate shift register + always @(posedge scl) + sr <= #1 {sr[6:0],sda}; + + //detect my_address + assign my_adr = (sr[7:1] == I2C_ADR); + // FIXME: This should not be a generic assign, but rather + // qualified on address transfer phase and probably reset by stop + + //generate bit-counter + always @(posedge scl) + if(ld) + bit_cnt <= #1 3'b111; + else + bit_cnt <= #1 bit_cnt - 3'h1; + + //generate access done signal + assign acc_done = !(|bit_cnt); + + // generate delayed version of sda + // this model assumes a hold time for sda after the falling edge of scl. + // According to the Phillips i2c spec, there s/b a 0 ns hold time for sda + // with regards to scl. If the data changes coincident with the clock, the + // acknowledge is missed + // Fix by Michael Sosnoski + assign #1 sda_dly = sda; + + + //detect start condition + always @(negedge sda) + if(scl) + begin + sta <= #1 1'b1; + d_sta <= #1 1'b0; + sto <= #1 1'b0; + + if(debug) + $display("DEBUG i2c_slave; start condition detected at %t", $time); + end + else + sta <= #1 1'b0; + + always @(posedge scl) + d_sta <= #1 sta; + + // detect stop condition + always @(posedge sda) + if(scl) + begin + sta <= #1 1'b0; + sto <= #1 1'b1; + + if(debug) + $display("DEBUG i2c_slave; stop condition detected at %t", $time); + end + else + sto <= #1 1'b0; + + //generate i2c_reset signal + assign i2c_reset = sta || sto; + + // generate statemachine + always @(negedge scl or posedge sto) + if (sto || (sta && !d_sta) ) + begin + state <= #1 idle; // reset statemachine + + sda_o <= #1 1'b1; + ld <= #1 1'b1; + end + else + begin + // initial settings + sda_o <= #1 1'b1; + ld <= #1 1'b0; + + case(state) // synopsys full_case parallel_case + idle: // idle state + if (acc_done && my_adr) + begin + state <= #1 slave_ack; + rw <= #1 sr[0]; + sda_o <= #1 1'b0; // generate i2c_ack + + #2; + if(debug && rw) + $display("DEBUG i2c_slave; command byte received (read) at %t", $time); + if(debug && !rw) + $display("DEBUG i2c_slave; command byte received (write) at %t", $time); + + if(rw) + begin + mem_do <= #1 mem[mem_adr]; + + if(debug) + begin + #2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr); + #2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]); + end + end + end + + slave_ack: + begin + if(rw) + begin + state <= #1 data; + sda_o <= #1 mem_do[7]; + end + else + state <= #1 get_mem_adr; + + ld <= #1 1'b1; + end + + get_mem_adr: // wait for memory address + if(acc_done) + begin + state <= #1 gma_ack; + mem_adr <= #1 sr; // store memory address + sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address + + if(debug) + #1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o); + end + + gma_ack: + begin + state <= #1 data; + ld <= #1 1'b1; + end + + data: // receive or drive data + begin + if(rw) + sda_o <= #1 mem_do[7]; + + if(acc_done) + begin + state <= #1 data_ack; + mem_adr <= #2 mem_adr + 8'h1; + sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read + + if(rw) + begin + #3 mem_do <= mem[mem_adr]; + + if(debug) + #5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr); + end + + if(!rw) + begin + mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory + + if(debug) + #2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr); + end + end + end + + data_ack: + begin + ld <= #1 1'b1; + + if(rw) + if(sr[0]) // read operation && master send NACK + begin + state <= #1 idle; + sda_o <= #1 1'b1; + end + else + begin + state <= #1 data; + sda_o <= #1 mem_do[7]; + end + else + begin + state <= #1 data; + sda_o <= #1 1'b1; + end + end + + endcase + end + + // read data from memory + always @(posedge scl) + if(!acc_done && rw) + mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation + + // generate tri-states + assign sda = sda_o ? 1'bz : 1'b0; + + + // + // Timing checks + // + + wire tst_sto = sto; + wire tst_sta = sta; + + specify + specparam normal_scl_low = 4700, + normal_scl_high = 4000, + normal_tsu_sta = 4700, + normal_thd_sta = 4000, + normal_tsu_sto = 4000, + normal_tbuf = 4700, + + fast_scl_low = 1300, + fast_scl_high = 600, + fast_tsu_sta = 1300, + fast_thd_sta = 600, + fast_tsu_sto = 600, + fast_tbuf = 1300; + + $width(negedge scl, normal_scl_low); // scl low time + $width(posedge scl, normal_scl_high); // scl high time + + $setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start + $setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start + $setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop + + $setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time + endspecify + +endmodule + + diff --git a/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v b/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v new file mode 100644 index 000000000..7d2f436f9 --- /dev/null +++ b/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v @@ -0,0 +1,128 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SPI Slave Model //// +//// //// +//// //// +//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// +//// //// +//// http://www.opencores.org/projects/simple_spi/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: spi_slave_model.v,v 1.1 2004/02/28 15:32:54 rherveille Exp $ +// +// $Date: 2004/02/28 15:32:54 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: spi_slave_model.v,v $ +// Revision 1.1 2004/02/28 15:32:54 rherveille +// Added testbench +// +// +// + + +// Requires: Verilog2001 + +`include "timescale.v" + +module spi_slave_model ( + input wire csn; + input wire sck + input wire di; + output wire do +); + + // + // Variable declaration + // + wire debug = 1'b1; + + wire cpol = 1'b0; + wire cpha = 1'b0; + + reg [7:0] mem [7:0]; // initiate memory + reg [2:0] mem_adr; // memory address + reg [7:0] mem_do; // memory data output + + reg [7:0] sri, sro; // 8bit shift register + + reg [2:0] bit_cnt; + reg ld; + + wire clk; + + // + // module body + // + + assign clk = cpol ^ cpha ^ sck; + + // generate shift registers + always @(posedge clk) + sri <= #1 {sri[6:0],di}; + + always @(posedge clk) + if (&bit_cnt) + sro <= #1 mem[mem_adr]; + else + sro <= #1 {sro[6:0],1'bx}; + + assign do = sro[7]; + + //generate bit-counter + always @(posedge clk, posedge csn) + if(csn) + bit_cnt <= #1 3'b111; + else + bit_cnt <= #1 bit_cnt - 3'h1; + + //generate access done signal + always @(posedge clk) + ld <= #1 ~(|bit_cnt); + + always @(negedge clk) + if (ld) begin + mem[mem_adr] <= #1 sri; + mem_adr <= #1 mem_adr + 1'b1; + end + + initial + begin + bit_cnt=3'b111; + mem_adr = 0; + sro = mem[mem_adr]; + end +endmodule + + diff --git a/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v b/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v new file mode 100644 index 000000000..66284e4d4 --- /dev/null +++ b/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v @@ -0,0 +1,467 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master controller Testbench //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: tst_bench_top.v,v 1.8 2006/09/04 09:08:51 rherveille Exp $ +// +// $Date: 2006/09/04 09:08:51 $ +// $Revision: 1.8 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: tst_bench_top.v,v $ +// Revision 1.8 2006/09/04 09:08:51 rherveille +// fixed (n)ack generation +// +// Revision 1.7 2005/02/27 09:24:18 rherveille +// Fixed scl, sda delay. +// +// Revision 1.6 2004/02/28 15:40:42 rherveille +// *** empty log message *** +// +// Revision 1.4 2003/12/05 11:04:38 rherveille +// Added slave address configurability +// +// Revision 1.3 2002/10/30 18:11:06 rherveille +// Added timing tests to i2c_model. +// Updated testbench. +// +// Revision 1.2 2002/03/17 10:26:38 rherveille +// Fixed some race conditions in the i2c-slave model. +// Added debug information. +// Added headers. +// + +`include "timescale.v" + +module tst_bench_top(); + + // + // wires && regs + // + reg clk; + reg rstn; + + wire [31:0] adr; + wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i; + wire we; + wire stb; + wire cyc; + wire ack; + wire inta; + + reg [7:0] q, qq; + + wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen; + wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen; + + parameter PRER_LO = 3'b000; + parameter PRER_HI = 3'b001; + parameter CTR = 3'b010; + parameter RXR = 3'b011; + parameter TXR = 3'b011; + parameter CR = 3'b100; + parameter SR = 3'b100; + + parameter TXR_R = 3'b101; // undocumented / reserved output + parameter CR_R = 3'b110; // undocumented / reserved output + + parameter RD = 1'b1; + parameter WR = 1'b0; + parameter SADR = 7'b0010_000; + + // + // Module body + // + + // generate clock + always #5 clk = ~clk; + + // hookup wishbone master model + wb_master_model #(8, 32) u0 ( + .clk(clk), + .rst(rstn), + .adr(adr), + .din(dat_i), + .dout(dat_o), + .cyc(cyc), + .stb(stb), + .we(we), + .sel(), + .ack(ack), + .err(1'b0), + .rty(1'b0) + ); + + wire stb0 = stb & ~adr[3]; + wire stb1 = stb & adr[3]; + + assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i); + + // hookup wishbone_i2c_master core + i2c_master_top i2c_top ( + + // wishbone interface + .wb_clk_i(clk), + .wb_rst_i(1'b0), + .arst_i(rstn), + .wb_adr_i(adr[2:0]), + .wb_dat_i(dat_o), + .wb_dat_o(dat0_i), + .wb_we_i(we), + .wb_stb_i(stb0), + .wb_cyc_i(cyc), + .wb_ack_o(ack), + .wb_inta_o(inta), + + // i2c signals + .scl_pad_i(scl), + .scl_pad_o(scl0_o), + .scl_padoen_o(scl0_oen), + .sda_pad_i(sda), + .sda_pad_o(sda0_o), + .sda_padoen_o(sda0_oen) + ), + i2c_top2 ( + + // wishbone interface + .wb_clk_i(clk), + .wb_rst_i(1'b0), + .arst_i(rstn), + .wb_adr_i(adr[2:0]), + .wb_dat_i(dat_o), + .wb_dat_o(dat1_i), + .wb_we_i(we), + .wb_stb_i(stb1), + .wb_cyc_i(cyc), + .wb_ack_o(ack), + .wb_inta_o(inta), + + // i2c signals + .scl_pad_i(scl), + .scl_pad_o(scl1_o), + .scl_padoen_o(scl1_oen), + .sda_pad_i(sda), + .sda_pad_o(sda1_o), + .sda_padoen_o(sda1_oen) + ); + + + // hookup i2c slave model + i2c_slave_model #(SADR) i2c_slave ( + .scl(scl), + .sda(sda) + ); + + // create i2c lines + delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl), + m1_scl (scl1_oen ? 1'bz : scl1_o, scl), + m0_sda (sda0_oen ? 1'bz : sda0_o, sda), + m1_sda (sda1_oen ? 1'bz : sda1_o, sda); + + pullup p1(scl); // pullup scl line + pullup p2(sda); // pullup sda line + + initial + begin + `ifdef WAVES + $shm_open("waves"); + $shm_probe("AS",tst_bench_top,"AS"); + $display("INFO: Signal dump enabled ...\n\n"); + `endif + +// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information + force i2c_slave.debug = 1'b0; // disable i2c_slave debug information + + $display("\nstatus: %t Testbench started\n\n", $time); + +// $dumpfile("bench.vcd"); +// $dumpvars(1, tst_bench_top); +// $dumpvars(1, tst_bench_top.i2c_slave); + + // initially values + clk = 0; + + // reset system + rstn = 1'b1; // negate reset + #2; + rstn = 1'b0; // assert reset + repeat(1) @(posedge clk); + rstn = 1'b1; // negate reset + + $display("status: %t done reset", $time); + + @(posedge clk); + + // + // program core + // + + // program internal registers + u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte + u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte + u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte + $display("status: %t programmed registers", $time); + + u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte + u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte + $display("status: %t verified registers", $time); + + u0.wb_write(1, CTR, 8'h80); // enable core + $display("status: %t core enabled", $time); + + // + // access slave (write) + // + + // drive slave address + u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit + u0.wb_write(0, CR, 8'h90 ); // set command (start, write) + $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} ); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(0, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory address + u0.wb_write(1, TXR, 8'h01); // present slave's memory address + u0.wb_write(0, CR, 8'h10); // set command (write) + $display("status: %t write slave memory address 01", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(0, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory contents + u0.wb_write(1, TXR, 8'ha5); // present data + u0.wb_write(0, CR, 8'h10); // set command (write) + $display("status: %t write data a5", $time); + +while (scl) #1; +force scl= 1'b0; +#100000; +release scl; + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory contents for next memory address (auto_inc) + u0.wb_write(1, TXR, 8'h5a); // present data + u0.wb_write(0, CR, 8'h50); // set command (stop, write) + $display("status: %t write next data 5a, generate 'stop'", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // + // delay + // +// #100000; // wait for 100us. +// $display("status: %t wait 100us", $time); + + // + // access slave (read) + // + + // drive slave address + u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit + u0.wb_write(0, CR, 8'h90 ); // set command (start, write) + $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} ); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory address + u0.wb_write(1, TXR, 8'h01); // present slave's memory address + u0.wb_write(0, CR, 8'h10); // set command (write) + $display("status: %t write slave address 01", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // drive slave address + u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit + u0.wb_write(0, CR, 8'h90 ); // set command (start, write) + $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} ); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // read data from slave + u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) + $display("status: %t read + ack", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // check data just received + u0.wb_read(1, RXR, qq); + if(qq !== 8'ha5) + $display("\nERROR: Expected a5, received %x at time %t", qq, $time); + else + $display("status: %t received %x", $time, qq); + + // read data from slave + u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) + $display("status: %t read + ack", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // check data just received + u0.wb_read(1, RXR, qq); + if(qq !== 8'h5a) + $display("\nERROR: Expected 5a, received %x at time %t", qq, $time); + else + $display("status: %t received %x", $time, qq); + + // read data from slave + u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) + $display("status: %t read + ack", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // check data just received + u0.wb_read(1, RXR, qq); + $display("status: %t received %x from 3rd read address", $time, qq); + + // read data from slave + u0.wb_write(1, CR, 8'h28); // set command (read, nack_read) + $display("status: %t read + nack", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // check data just received + u0.wb_read(1, RXR, qq); + $display("status: %t received %x from 4th read address", $time, qq); + + // + // check invalid slave memory address + // + + // drive slave address + u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit + u0.wb_write(0, CR, 8'h90 ); // set command (start, write) + $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} ); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory address + u0.wb_write(1, TXR, 8'h10); // present slave's memory address + u0.wb_write(0, CR, 8'h10); // set command (write) + $display("status: %t write slave memory address 10", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // slave should have send NACK + $display("status: %t Check for nack", $time); + if(!q[7]) + $display("\nERROR: Expected NACK, received ACK\n"); + + // read data from slave + u0.wb_write(1, CR, 8'h40); // set command (stop) + $display("status: %t generate 'stop'", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + #250000; // wait 250us + $display("\n\nstatus: %t Testbench done", $time); + $finish; + end + +endmodule + +module delay (in, out); + input in; + output out; + + assign out = in; + + specify + (in => out) = (600,600); + endspecify +endmodule + + diff --git a/usrp2/opencores/i2c/bench/verilog/wb_master_model.v b/usrp2/opencores/i2c/bench/verilog/wb_master_model.v new file mode 100644 index 000000000..14ed6cbf5 --- /dev/null +++ b/usrp2/opencores/i2c/bench/verilog/wb_master_model.v @@ -0,0 +1,205 @@ +/////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 Wishbone Master model //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/mem_ctrl //// +//// //// +/////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +/////////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $ +// +// $Date: 2004/02/28 15:40:42 $ +// $Revision: 1.4 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// +`include "timescale.v" + +module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); + +parameter dwidth = 32; +parameter awidth = 32; + +input clk, rst; +output [awidth -1:0] adr; +input [dwidth -1:0] din; +output [dwidth -1:0] dout; +output cyc, stb; +output we; +output [dwidth/8 -1:0] sel; +input ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [awidth -1:0] adr; +reg [dwidth -1:0] dout; +reg cyc, stb; +reg we; +reg [dwidth/8 -1:0] sel; + +reg [dwidth -1:0] q; + +//////////////////////////////////////////////////////////////////// +// +// Memory Logic +// + +initial + begin + //adr = 32'hxxxx_xxxx; + //adr = 0; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + cyc = 1'b0; + stb = 1'bx; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + #1; + $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); + end + +//////////////////////////////////////////////////////////////////// +// +// Wishbone write cycle +// + +task wb_write; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signal + #1; + adr = a; + dout = d; + cyc = 1'b1; + stb = 1'b1; + we = 1'b1; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + + end +endtask + +//////////////////////////////////////////////////////////////////// +// +// Wishbone read cycle +// + +task wb_read; + input delay; + integer delay; + + input [awidth -1:0] a; + output [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signals + #1; + adr = a; + dout = {dwidth{1'bx}}; + cyc = 1'b1; + stb = 1'b1; + we = 1'b0; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + d = din; + + end +endtask + +//////////////////////////////////////////////////////////////////// +// +// Wishbone compare cycle (read data from location and compare with expected data) +// + +task wb_cmp; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d_exp; + + begin + wb_read (delay, a, q); + + if (d_exp !== q) + $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); + end +endtask + +endmodule + + diff --git a/usrp2/opencores/i2c/doc/CVS/Entries b/usrp2/opencores/i2c/doc/CVS/Entries new file mode 100644 index 000000000..ec323c90b --- /dev/null +++ b/usrp2/opencores/i2c/doc/CVS/Entries @@ -0,0 +1,2 @@ +/i2c_specs.pdf/1.3/Thu Jul 3 15:20:47 2003/-kb/ +D/src//// diff --git a/usrp2/opencores/i2c/doc/CVS/Repository b/usrp2/opencores/i2c/doc/CVS/Repository new file mode 100644 index 000000000..2ee10951a --- /dev/null +++ b/usrp2/opencores/i2c/doc/CVS/Repository @@ -0,0 +1 @@ +i2c/doc diff --git a/usrp2/opencores/i2c/doc/CVS/Root b/usrp2/opencores/i2c/doc/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/doc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/doc/CVS/Template b/usrp2/opencores/i2c/doc/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/doc/i2c_specs.pdf b/usrp2/opencores/i2c/doc/i2c_specs.pdf new file mode 100644 index 000000000..72021df11 Binary files /dev/null and b/usrp2/opencores/i2c/doc/i2c_specs.pdf differ diff --git a/usrp2/opencores/i2c/doc/src/CVS/Entries b/usrp2/opencores/i2c/doc/src/CVS/Entries new file mode 100644 index 000000000..5eeda5738 --- /dev/null +++ b/usrp2/opencores/i2c/doc/src/CVS/Entries @@ -0,0 +1,2 @@ +/I2C_specs.doc/1.7/Thu Jul 3 15:21:23 2003/-kb/ +D diff --git a/usrp2/opencores/i2c/doc/src/CVS/Repository b/usrp2/opencores/i2c/doc/src/CVS/Repository new file mode 100644 index 000000000..74dd64858 --- /dev/null +++ b/usrp2/opencores/i2c/doc/src/CVS/Repository @@ -0,0 +1 @@ +i2c/doc/src diff --git a/usrp2/opencores/i2c/doc/src/CVS/Root b/usrp2/opencores/i2c/doc/src/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/doc/src/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/doc/src/CVS/Template b/usrp2/opencores/i2c/doc/src/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/doc/src/I2C_specs.doc b/usrp2/opencores/i2c/doc/src/I2C_specs.doc new file mode 100644 index 000000000..31ab2684f Binary files /dev/null and b/usrp2/opencores/i2c/doc/src/I2C_specs.doc differ diff --git a/usrp2/opencores/i2c/documentation/CVS/Entries b/usrp2/opencores/i2c/documentation/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/usrp2/opencores/i2c/documentation/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/opencores/i2c/documentation/CVS/Repository b/usrp2/opencores/i2c/documentation/CVS/Repository new file mode 100644 index 000000000..1ccd8f6ce --- /dev/null +++ b/usrp2/opencores/i2c/documentation/CVS/Repository @@ -0,0 +1 @@ +i2c/documentation diff --git a/usrp2/opencores/i2c/documentation/CVS/Root b/usrp2/opencores/i2c/documentation/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/documentation/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/documentation/CVS/Template b/usrp2/opencores/i2c/documentation/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/rtl/CVS/Entries b/usrp2/opencores/i2c/rtl/CVS/Entries new file mode 100644 index 000000000..354f0dfb5 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/CVS/Entries @@ -0,0 +1,2 @@ +D/verilog//// +D/vhdl//// diff --git a/usrp2/opencores/i2c/rtl/CVS/Repository b/usrp2/opencores/i2c/rtl/CVS/Repository new file mode 100644 index 000000000..cfb83efd3 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/CVS/Repository @@ -0,0 +1 @@ +i2c/rtl diff --git a/usrp2/opencores/i2c/rtl/CVS/Root b/usrp2/opencores/i2c/rtl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/rtl/CVS/Template b/usrp2/opencores/i2c/rtl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/rtl/verilog/CVS/Entries b/usrp2/opencores/i2c/rtl/verilog/CVS/Entries new file mode 100644 index 000000000..441bd81af --- /dev/null +++ b/usrp2/opencores/i2c/rtl/verilog/CVS/Entries @@ -0,0 +1,6 @@ +/i2c_master_bit_ctrl.v/1.12/Mon Sep 4 09:08:13 2006// +/i2c_master_byte_ctrl.v/1.7/Wed Feb 18 11:40:46 2004// +/i2c_master_defines.v/1.3/Mon Nov 5 11:59:25 2001// +/i2c_master_top.v/1.11/Sun Feb 27 09:26:24 2005// +/timescale.v/1.1/Mon Sep 24 12:21:50 2001// +D diff --git a/usrp2/opencores/i2c/rtl/verilog/CVS/Repository b/usrp2/opencores/i2c/rtl/verilog/CVS/Repository new file mode 100644 index 000000000..49cc6cce0 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/verilog/CVS/Repository @@ -0,0 +1 @@ +i2c/rtl/verilog diff --git a/usrp2/opencores/i2c/rtl/verilog/CVS/Root b/usrp2/opencores/i2c/rtl/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/rtl/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/rtl/verilog/CVS/Template b/usrp2/opencores/i2c/rtl/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v b/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v new file mode 100644 index 000000000..edab94f61 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v @@ -0,0 +1,538 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master bit-controller //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_bit_ctrl.v,v 1.12 2006/09/04 09:08:13 rherveille Exp $ +// +// $Date: 2006/09/04 09:08:13 $ +// $Revision: 1.12 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_bit_ctrl.v,v $ +// Revision 1.12 2006/09/04 09:08:13 rherveille +// fixed short scl high pulse after clock stretch +// fixed slave model not returning correct '(n)ack' signal +// +// Revision 1.11 2004/05/07 11:02:26 rherveille +// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. +// +// Revision 1.10 2003/08/09 07:01:33 rherveille +// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +// Fixed a potential bug in the byte controller's host-acknowledge generation. +// +// Revision 1.9 2003/03/10 14:26:37 rherveille +// Fixed cmd_ack generation item (no bug). +// +// Revision 1.8 2003/02/05 00:06:10 rherveille +// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. +// +// Revision 1.7 2002/12/26 16:05:12 rherveille +// Small code simplifications +// +// Revision 1.6 2002/12/26 15:02:32 rherveille +// Core is now a Multimaster I2C controller +// +// Revision 1.5 2002/11/30 22:24:40 rherveille +// Cleaned up code +// +// Revision 1.4 2002/10/30 18:10:07 rherveille +// Fixed some reported minor start/stop generation timing issuess. +// +// Revision 1.3 2002/06/15 07:37:03 rherveille +// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. +// +// Revision 1.2 2001/11/05 11:59:25 rherveille +// Fixed wb_ack_o generation bug. +// Fixed bug in the byte_controller statemachine. +// Added headers. +// + +// +///////////////////////////////////// +// Bit controller section +///////////////////////////////////// +// +// Translate simple commands into SCL/SDA transitions +// Each command has 5 states, A/B/C/D/idle +// +// start: SCL ~~~~~~~~~~\____ +// SDA ~~~~~~~~\______ +// x | A | B | C | D | i +// +// repstart SCL ____/~~~~\___ +// SDA __/~~~\______ +// x | A | B | C | D | i +// +// stop SCL ____/~~~~~~~~ +// SDA ==\____/~~~~~ +// x | A | B | C | D | i +// +//- write SCL ____/~~~~\____ +// SDA ==X=========X= +// x | A | B | C | D | i +// +//- read SCL ____/~~~~\____ +// SDA XXXX=====XXXX +// x | A | B | C | D | i +// + +// Timing: Normal mode Fast mode +/////////////////////////////////////////////////////////////////////// +// Fscl 100KHz 400KHz +// Th_scl 4.0us 0.6us High period of SCL +// Tl_scl 4.7us 1.3us Low period of SCL +// Tsu:sta 4.7us 0.6us setup time for a repeated start condition +// Tsu:sto 4.0us 0.6us setup time for a stop conditon +// Tbuf 4.7us 1.3us Bus free time between a stop and start condition +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "i2c_master_defines.v" + +module i2c_master_bit_ctrl( + clk, rst, nReset, + clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout, + scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen + ); + + // + // inputs & outputs + // + input clk; + input rst; + input nReset; + input ena; // core enable signal + + input [15:0] clk_cnt; // clock prescale value + + input [3:0] cmd; + output cmd_ack; // command complete acknowledge + reg cmd_ack; + output busy; // i2c bus busy + reg busy; + output al; // i2c bus arbitration lost + reg al; + + input din; + output dout; + reg dout; + + // I2C lines + input scl_i; // i2c clock line input + output scl_o; // i2c clock line output + output scl_oen; // i2c clock line output enable (active low) + reg scl_oen; + input sda_i; // i2c data line input + output sda_o; // i2c data line output + output sda_oen; // i2c data line output enable (active low) + reg sda_oen; + + + // + // variable declarations + // + + reg sSCL, sSDA; // synchronized SCL and SDA inputs + reg dscl_oen; // delayed scl_oen + reg sda_chk; // check SDA output (Multi-master arbitration) + reg clk_en; // clock generation signals + wire slave_wait; +// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation) + reg [15:0] cnt; // clock divider counter (synthesis) + + // state machine variable + reg [16:0] c_state; // synopsys enum_state + + // + // module body + // + + // whenever the slave is not ready it can delay the cycle by pulling SCL low + // delay scl_oen + always @(posedge clk) + dscl_oen <= #1 scl_oen; + + assign slave_wait = dscl_oen && !sSCL; + + + // generate clk enable signal + always @(posedge clk or negedge nReset) + if(~nReset) + begin + cnt <= #1 16'h0; + clk_en <= #1 1'b1; + end + else if (rst) + begin + cnt <= #1 16'h0; + clk_en <= #1 1'b1; + end + else if ( ~|cnt || !ena) + begin + cnt <= #1 clk_cnt; + clk_en <= #1 1'b1; + end + else if (slave_wait) + begin + cnt <= #1 cnt; + clk_en <= #1 1'b0; + end + else + begin + cnt <= #1 cnt - 16'h1; + clk_en <= #1 1'b0; + end + + + // generate bus status controller + reg dSCL, dSDA; + reg sta_condition; + reg sto_condition; + + // synchronize SCL and SDA inputs + // reduce metastability risc + always @(posedge clk or negedge nReset) + if (~nReset) + begin + sSCL <= #1 1'b1; + sSDA <= #1 1'b1; + + dSCL <= #1 1'b1; + dSDA <= #1 1'b1; + end + else if (rst) + begin + sSCL <= #1 1'b1; + sSDA <= #1 1'b1; + + dSCL <= #1 1'b1; + dSDA <= #1 1'b1; + end + else + begin + sSCL <= #1 scl_i; + sSDA <= #1 sda_i; + + dSCL <= #1 sSCL; + dSDA <= #1 sSDA; + end + + // detect start condition => detect falling edge on SDA while SCL is high + // detect stop condition => detect rising edge on SDA while SCL is high + always @(posedge clk or negedge nReset) + if (~nReset) + begin + sta_condition <= #1 1'b0; + sto_condition <= #1 1'b0; + end + else if (rst) + begin + sta_condition <= #1 1'b0; + sto_condition <= #1 1'b0; + end + else + begin + sta_condition <= #1 ~sSDA & dSDA & sSCL; + sto_condition <= #1 sSDA & ~dSDA & sSCL; + end + + // generate i2c bus busy signal + always @(posedge clk or negedge nReset) + if(!nReset) + busy <= #1 1'b0; + else if (rst) + busy <= #1 1'b0; + else + busy <= #1 (sta_condition | busy) & ~sto_condition; + + // generate arbitration lost signal + // aribitration lost when: + // 1) master drives SDA high, but the i2c bus is low + // 2) stop detected while not requested + reg cmd_stop; + always @(posedge clk or negedge nReset) + if (~nReset) + cmd_stop <= #1 1'b0; + else if (rst) + cmd_stop <= #1 1'b0; + else if (clk_en) + cmd_stop <= #1 cmd == `I2C_CMD_STOP; + + always @(posedge clk or negedge nReset) + if (~nReset) + al <= #1 1'b0; + else if (rst) + al <= #1 1'b0; + else + al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop); + + + // generate dout signal (store SDA on rising edge of SCL) + always @(posedge clk) + if(sSCL & ~dSCL) + dout <= #1 sSDA; + + // generate statemachine + + // nxt_state decoder + parameter [16:0] idle = 17'b0_0000_0000_0000_0000; + parameter [16:0] start_a = 17'b0_0000_0000_0000_0001; + parameter [16:0] start_b = 17'b0_0000_0000_0000_0010; + parameter [16:0] start_c = 17'b0_0000_0000_0000_0100; + parameter [16:0] start_d = 17'b0_0000_0000_0000_1000; + parameter [16:0] start_e = 17'b0_0000_0000_0001_0000; + parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000; + parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000; + parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000; + parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000; + parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000; + parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000; + parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000; + parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000; + parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000; + parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000; + parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000; + parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000; + + always @(posedge clk or negedge nReset) + if (!nReset) + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b0; + scl_oen <= #1 1'b1; + sda_oen <= #1 1'b1; + sda_chk <= #1 1'b0; + end + else if (rst | al) + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b0; + scl_oen <= #1 1'b1; + sda_oen <= #1 1'b1; + sda_chk <= #1 1'b0; + end + else + begin + cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle + + if (clk_en) + case (c_state) // synopsys full_case parallel_case + // idle state + idle: + begin + case (cmd) // synopsys full_case parallel_case + `I2C_CMD_START: + c_state <= #1 start_a; + + `I2C_CMD_STOP: + c_state <= #1 stop_a; + + `I2C_CMD_WRITE: + c_state <= #1 wr_a; + + `I2C_CMD_READ: + c_state <= #1 rd_a; + + default: + c_state <= #1 idle; + endcase + + scl_oen <= #1 scl_oen; // keep SCL in same state + sda_oen <= #1 sda_oen; // keep SDA in same state + sda_chk <= #1 1'b0; // don't check SDA output + end + + // start + start_a: + begin + c_state <= #1 start_b; + scl_oen <= #1 scl_oen; // keep SCL in same state + sda_oen <= #1 1'b1; // set SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_b: + begin + c_state <= #1 start_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b1; // keep SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_c: + begin + c_state <= #1 start_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // set SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_d: + begin + c_state <= #1 start_e; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_e: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + // stop + stop_a: + begin + c_state <= #1 stop_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 1'b0; // set SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_b: + begin + c_state <= #1 stop_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_c: + begin + c_state <= #1 stop_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b1; // set SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + // read + rd_a: + begin + c_state <= #1 rd_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 1'b1; // tri-state SDA + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_b: + begin + c_state <= #1 rd_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_c: + begin + c_state <= #1 rd_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + // write + wr_a: + begin + c_state <= #1 wr_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 din; // set SDA + sda_chk <= #1 1'b0; // don't check SDA output (SCL low) + end + + wr_b: + begin + c_state <= #1 wr_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 din; // keep SDA + sda_chk <= #1 1'b1; // check SDA output + end + + wr_c: + begin + c_state <= #1 wr_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 din; + sda_chk <= #1 1'b1; // check SDA output + end + + wr_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 din; + sda_chk <= #1 1'b0; // don't check SDA output (SCL low) + end + + endcase + end + + + // assign scl and sda output (always gnd) + assign scl_o = 1'b0; + assign sda_o = 1'b0; + +endmodule diff --git a/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v b/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v new file mode 100644 index 000000000..d091d1e36 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v @@ -0,0 +1,344 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master byte-controller //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $ +// +// $Date: 2004/02/18 11:40:46 $ +// $Revision: 1.7 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_byte_ctrl.v,v $ +// Revision 1.7 2004/02/18 11:40:46 rherveille +// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. +// +// Revision 1.6 2003/08/09 07:01:33 rherveille +// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +// Fixed a potential bug in the byte controller's host-acknowledge generation. +// +// Revision 1.5 2002/12/26 15:02:32 rherveille +// Core is now a Multimaster I2C controller +// +// Revision 1.4 2002/11/30 22:24:40 rherveille +// Cleaned up code +// +// Revision 1.3 2001/11/05 11:59:25 rherveille +// Fixed wb_ack_o generation bug. +// Fixed bug in the byte_controller statemachine. +// Added headers. +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "i2c_master_defines.v" + +module i2c_master_byte_ctrl ( + clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din, + cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen ); + + // + // inputs & outputs + // + input clk; // master clock + input rst; // synchronous active high reset + input nReset; // asynchronous active low reset + input ena; // core enable signal + + input [15:0] clk_cnt; // 4x SCL + + // control inputs + input start; + input stop; + input read; + input write; + input ack_in; + input [7:0] din; + + // status outputs + output cmd_ack; + reg cmd_ack; + output ack_out; + reg ack_out; + output i2c_busy; + output i2c_al; + output [7:0] dout; + + // I2C signals + input scl_i; + output scl_o; + output scl_oen; + input sda_i; + output sda_o; + output sda_oen; + + + // + // Variable declarations + // + + // statemachine + parameter [4:0] ST_IDLE = 5'b0_0000; + parameter [4:0] ST_START = 5'b0_0001; + parameter [4:0] ST_READ = 5'b0_0010; + parameter [4:0] ST_WRITE = 5'b0_0100; + parameter [4:0] ST_ACK = 5'b0_1000; + parameter [4:0] ST_STOP = 5'b1_0000; + + // signals for bit_controller + reg [3:0] core_cmd; + reg core_txd; + wire core_ack, core_rxd; + + // signals for shift register + reg [7:0] sr; //8bit shift register + reg shift, ld; + + // signals for state machine + wire go; + reg [2:0] dcnt; + wire cnt_done; + + // + // Module body + // + + // hookup bit_controller + i2c_master_bit_ctrl bit_controller ( + .clk ( clk ), + .rst ( rst ), + .nReset ( nReset ), + .ena ( ena ), + .clk_cnt ( clk_cnt ), + .cmd ( core_cmd ), + .cmd_ack ( core_ack ), + .busy ( i2c_busy ), + .al ( i2c_al ), + .din ( core_txd ), + .dout ( core_rxd ), + .scl_i ( scl_i ), + .scl_o ( scl_o ), + .scl_oen ( scl_oen ), + .sda_i ( sda_i ), + .sda_o ( sda_o ), + .sda_oen ( sda_oen ) + ); + + // generate go-signal + assign go = (read | write | stop) & ~cmd_ack; + + // assign dout output to shift-register + assign dout = sr; + + // generate shift register + always @(posedge clk or negedge nReset) + if (!nReset) + sr <= #1 8'h0; + else if (rst) + sr <= #1 8'h0; + else if (ld) + sr <= #1 din; + else if (shift) + sr <= #1 {sr[6:0], core_rxd}; + + // generate counter + always @(posedge clk or negedge nReset) + if (!nReset) + dcnt <= #1 3'h0; + else if (rst) + dcnt <= #1 3'h0; + else if (ld) + dcnt <= #1 3'h7; + else if (shift) + dcnt <= #1 dcnt - 3'h1; + + assign cnt_done = ~(|dcnt); + + // + // state machine + // + reg [4:0] c_state; // synopsis enum_state + + always @(posedge clk or negedge nReset) + if (!nReset) + begin + core_cmd <= #1 `I2C_CMD_NOP; + core_txd <= #1 1'b0; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + c_state <= #1 ST_IDLE; + ack_out <= #1 1'b0; + end + else if (rst | i2c_al) + begin + core_cmd <= #1 `I2C_CMD_NOP; + core_txd <= #1 1'b0; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + c_state <= #1 ST_IDLE; + ack_out <= #1 1'b0; + end + else + begin + // initially reset all signals + core_txd <= #1 sr[7]; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + + case (c_state) // synopsys full_case parallel_case + ST_IDLE: + if (go) + begin + if (start) + begin + c_state <= #1 ST_START; + core_cmd <= #1 `I2C_CMD_START; + end + else if (read) + begin + c_state <= #1 ST_READ; + core_cmd <= #1 `I2C_CMD_READ; + end + else if (write) + begin + c_state <= #1 ST_WRITE; + core_cmd <= #1 `I2C_CMD_WRITE; + end + else // stop + begin + c_state <= #1 ST_STOP; + core_cmd <= #1 `I2C_CMD_STOP; + end + + ld <= #1 1'b1; + end + + ST_START: + if (core_ack) + begin + if (read) + begin + c_state <= #1 ST_READ; + core_cmd <= #1 `I2C_CMD_READ; + end + else + begin + c_state <= #1 ST_WRITE; + core_cmd <= #1 `I2C_CMD_WRITE; + end + + ld <= #1 1'b1; + end + + ST_WRITE: + if (core_ack) + if (cnt_done) + begin + c_state <= #1 ST_ACK; + core_cmd <= #1 `I2C_CMD_READ; + end + else + begin + c_state <= #1 ST_WRITE; // stay in same state + core_cmd <= #1 `I2C_CMD_WRITE; // write next bit + shift <= #1 1'b1; + end + + ST_READ: + if (core_ack) + begin + if (cnt_done) + begin + c_state <= #1 ST_ACK; + core_cmd <= #1 `I2C_CMD_WRITE; + end + else + begin + c_state <= #1 ST_READ; // stay in same state + core_cmd <= #1 `I2C_CMD_READ; // read next bit + end + + shift <= #1 1'b1; + core_txd <= #1 ack_in; + end + + ST_ACK: + if (core_ack) + begin + if (stop) + begin + c_state <= #1 ST_STOP; + core_cmd <= #1 `I2C_CMD_STOP; + end + else + begin + c_state <= #1 ST_IDLE; + core_cmd <= #1 `I2C_CMD_NOP; + + // generate command acknowledge signal + cmd_ack <= #1 1'b1; + end + + // assign ack_out output to bit_controller_rxd (contains last received bit) + ack_out <= #1 core_rxd; + + core_txd <= #1 1'b1; + end + else + core_txd <= #1 ack_in; + + ST_STOP: + if (core_ack) + begin + c_state <= #1 ST_IDLE; + core_cmd <= #1 `I2C_CMD_NOP; + + // generate command acknowledge signal + cmd_ack <= #1 1'b1; + end + + endcase + end +endmodule diff --git a/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v b/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v new file mode 100644 index 000000000..ee3b694fa --- /dev/null +++ b/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v @@ -0,0 +1,64 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master controller defines //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $ +// +// $Date: 2001/11/05 11:59:25 $ +// $Revision: 1.3 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_defines.v,v $ +// Revision 1.3 2001/11/05 11:59:25 rherveille +// Fixed wb_ack_o generation bug. +// Fixed bug in the byte_controller statemachine. +// Added headers. +// + + +// I2C registers wishbone addresses + +// bitcontroller states +`define I2C_CMD_NOP 4'b0000 +`define I2C_CMD_START 4'b0001 +`define I2C_CMD_STOP 4'b0010 +`define I2C_CMD_WRITE 4'b0100 +`define I2C_CMD_READ 4'b1000 diff --git a/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v b/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v new file mode 100644 index 000000000..30689bd70 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v @@ -0,0 +1,301 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE revB.2 compliant I2C Master controller Top-level //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $ +// +// $Date: 2005/02/27 09:26:24 $ +// $Revision: 1.11 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_top.v,v $ +// Revision 1.11 2005/02/27 09:26:24 rherveille +// Fixed register overwrite issue. +// Removed full_case pragma, replaced it by a default statement. +// +// Revision 1.10 2003/09/01 10:34:38 rherveille +// Fix a blocking vs. non-blocking error in the wb_dat output mux. +// +// Revision 1.9 2003/01/09 16:44:45 rherveille +// Fixed a bug in the Command Register declaration. +// +// Revision 1.8 2002/12/26 16:05:12 rherveille +// Small code simplifications +// +// Revision 1.7 2002/12/26 15:02:32 rherveille +// Core is now a Multimaster I2C controller +// +// Revision 1.6 2002/11/30 22:24:40 rherveille +// Cleaned up code +// +// Revision 1.5 2001/11/10 10:52:55 rherveille +// Changed PRER reset value from 0x0000 to 0xffff, conform specs. +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "i2c_master_defines.v" + +module i2c_master_top( + wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, + scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); + + // parameters + parameter ARST_LVL = 1'b0; // asynchronous reset level + + // + // inputs & outputs + // + + // wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input arst_i; // asynchronous reset + input [2:0] wb_adr_i; // lower address bits + input [7:0] wb_dat_i; // databus input + output [7:0] wb_dat_o; // databus output + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + output wb_inta_o; // interrupt request signal output + + reg [7:0] wb_dat_o; + reg wb_ack_o; + reg wb_inta_o; + + // I2C signals + // i2c clock line + input scl_pad_i; // SCL-line input + output scl_pad_o; // SCL-line output (always 1'b0) + output scl_padoen_o; // SCL-line output enable (active low) + + // i2c data line + input sda_pad_i; // SDA-line input + output sda_pad_o; // SDA-line output (always 1'b0) + output sda_padoen_o; // SDA-line output enable (active low) + + + // + // variable declarations + // + + // registers + reg [15:0] prer; // clock prescale register + reg [ 7:0] ctr; // control register + reg [ 7:0] txr; // transmit register + wire [ 7:0] rxr; // receive register + reg [ 7:0] cr; // command register + wire [ 7:0] sr; // status register + + // done signal: command completed, clear command register + wire done; + + // core enable signal + wire core_en; + wire ien; + + // status register signals + wire irxack; + reg rxack; // received aknowledge from slave + reg tip; // transfer in progress + reg irq_flag; // interrupt pending flag + wire i2c_busy; // bus busy (start signal detected) + wire i2c_al; // i2c bus arbitration lost + reg al; // status register arbitration lost bit + + // + // module body + // + + // generate internal reset + wire rst_i = arst_i ^ ARST_LVL; + + // generate wishbone signals + wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i; + + // generate acknowledge output signal + always @(posedge wb_clk_i) + wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored + + // assign DAT_O + always @(posedge wb_clk_i) + begin + case (wb_adr_i) // synopsis parallel_case + 3'b000: wb_dat_o <= #1 prer[ 7:0]; + 3'b001: wb_dat_o <= #1 prer[15:8]; + 3'b010: wb_dat_o <= #1 ctr; + 3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr) + 3'b100: wb_dat_o <= #1 sr; // write is command register (cr) + 3'b101: wb_dat_o <= #1 txr; + 3'b110: wb_dat_o <= #1 cr; + 3'b111: wb_dat_o <= #1 0; // reserved + endcase + end + + // generate registers + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + begin + prer <= #1 16'hffff; + ctr <= #1 8'h0; + txr <= #1 8'h0; + end + else if (wb_rst_i) + begin + prer <= #1 16'hffff; + ctr <= #1 8'h0; + txr <= #1 8'h0; + end + else + if (wb_wacc) + case (wb_adr_i) // synopsis parallel_case + 3'b000 : prer [ 7:0] <= #1 wb_dat_i; + 3'b001 : prer [15:8] <= #1 wb_dat_i; + 3'b010 : ctr <= #1 wb_dat_i; + 3'b011 : txr <= #1 wb_dat_i; + default: ; + endcase + + // generate command register (special case) + always @(posedge wb_clk_i or negedge rst_i) + if (~rst_i) + cr <= #1 8'h0; + else if (wb_rst_i) + cr <= #1 8'h0; + else if (wb_wacc) + begin + if (core_en & (wb_adr_i == 3'b100) ) + cr <= #1 wb_dat_i; + end + else + begin + if (done | i2c_al) + cr[7:4] <= #1 4'h0; // clear command bits when done + // or when aribitration lost + cr[2:1] <= #1 2'b0; // reserved bits + cr[0] <= #1 2'b0; // clear IRQ_ACK bit + end + + + // decode command register + wire sta = cr[7]; + wire sto = cr[6]; + wire rd = cr[5]; + wire wr = cr[4]; + wire ack = cr[3]; + wire iack = cr[0]; + + // decode control register + assign core_en = ctr[7]; + assign ien = ctr[6]; + + // hookup byte controller block + i2c_master_byte_ctrl byte_controller ( + .clk ( wb_clk_i ), + .rst ( wb_rst_i ), + .nReset ( rst_i ), + .ena ( core_en ), + .clk_cnt ( prer ), + .start ( sta ), + .stop ( sto ), + .read ( rd ), + .write ( wr ), + .ack_in ( ack ), + .din ( txr ), + .cmd_ack ( done ), + .ack_out ( irxack ), + .dout ( rxr ), + .i2c_busy ( i2c_busy ), + .i2c_al ( i2c_al ), + .scl_i ( scl_pad_i ), + .scl_o ( scl_pad_o ), + .scl_oen ( scl_padoen_o ), + .sda_i ( sda_pad_i ), + .sda_o ( sda_pad_o ), + .sda_oen ( sda_padoen_o ) + ); + + // status register block + interrupt request signal + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + begin + al <= #1 1'b0; + rxack <= #1 1'b0; + tip <= #1 1'b0; + irq_flag <= #1 1'b0; + end + else if (wb_rst_i) + begin + al <= #1 1'b0; + rxack <= #1 1'b0; + tip <= #1 1'b0; + irq_flag <= #1 1'b0; + end + else + begin + al <= #1 i2c_al | (al & ~sta); + rxack <= #1 irxack; + tip <= #1 (rd | wr); + irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated + end + + // generate interrupt request signals + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + wb_inta_o <= #1 1'b0; + else if (wb_rst_i) + wb_inta_o <= #1 1'b0; + else + wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set) + + // assign status register bits + assign sr[7] = rxack; + assign sr[6] = i2c_busy; + assign sr[5] = al; + assign sr[4:2] = 3'h0; // reserved + assign sr[1] = tip; + assign sr[0] = irq_flag; + +endmodule diff --git a/usrp2/opencores/i2c/rtl/verilog/timescale.v b/usrp2/opencores/i2c/rtl/verilog/timescale.v new file mode 100644 index 000000000..60d4ecbd1 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/verilog/timescale.v @@ -0,0 +1,2 @@ +`timescale 1ns / 10ps + diff --git a/usrp2/opencores/i2c/rtl/vhdl/CVS/Entries b/usrp2/opencores/i2c/rtl/vhdl/CVS/Entries new file mode 100644 index 000000000..2a33278f7 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/CVS/Entries @@ -0,0 +1,7 @@ +/I2C.VHD/1.1/Mon Sep 24 12:21:51 2001// +/i2c_master_bit_ctrl.vhd/1.14/Wed Oct 11 12:10:13 2006// +/i2c_master_byte_ctrl.vhd/1.5/Wed Feb 18 11:41:48 2004// +/i2c_master_top.vhd/1.7/Sun Mar 14 10:17:03 2004// +/readme/1.2/Sat Nov 30 22:25:47 2002// +/tst_ds1621.vhd/1.1/Mon Sep 24 12:21:51 2001// +D diff --git a/usrp2/opencores/i2c/rtl/vhdl/CVS/Repository b/usrp2/opencores/i2c/rtl/vhdl/CVS/Repository new file mode 100644 index 000000000..c210ff4e3 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/CVS/Repository @@ -0,0 +1 @@ +i2c/rtl/vhdl diff --git a/usrp2/opencores/i2c/rtl/vhdl/CVS/Root b/usrp2/opencores/i2c/rtl/vhdl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/rtl/vhdl/CVS/Template b/usrp2/opencores/i2c/rtl/vhdl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD b/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD new file mode 100644 index 000000000..64d1eb656 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD @@ -0,0 +1,620 @@ +-- +-- Simple I2C controller +-- +-- 1) No multimaster +-- 2) No slave mode +-- 3) No fifo's +-- +-- notes: +-- Every command is acknowledged. Do not set a new command before previous is acknowledged. +-- Dout is available 1 clock cycle later as cmd_ack +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +package I2C is + component simple_i2c is + port ( + clk : in std_logic; + ena : in std_logic; + nReset : in std_logic; + + clk_cnt : in unsigned(7 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + Din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; + ack_out : out std_logic; + Dout : out std_logic_vector(7 downto 0); + + -- i2c signals + SCL : inout std_logic; + SDA : inout std_logic + ); + end component simple_i2c; +end package I2C; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity simple_i2c is + port ( + clk : in std_logic; + ena : in std_logic; + nReset : in std_logic; + + clk_cnt : in unsigned(7 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + Din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; + ack_out : out std_logic; + Dout : out std_logic_vector(7 downto 0); + + -- i2c signals + SCL : inout std_logic; + SDA : inout std_logic + ); +end entity simple_i2c; + +architecture structural of simple_i2c is + component i2c_core is + port ( + clk : in std_logic; + nReset : in std_logic; + + clk_cnt : in unsigned(7 downto 0); + + cmd : in std_logic_vector(2 downto 0); + cmd_ack : out std_logic; + busy : out std_logic; + + Din : in std_logic; + Dout : out std_logic; + + SCL : inout std_logic; + SDA : inout std_logic + ); + end component i2c_core; + + -- commands for i2c_core + constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; + constant CMD_START : std_logic_vector(2 downto 0) := "010"; + constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; + constant CMD_READ : std_logic_vector(2 downto 0) := "100"; + constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; + + -- signals for i2c_core + signal core_cmd : std_logic_vector(2 downto 0); + signal core_ack, core_busy, core_txd, core_rxd : std_logic; + + -- signals for shift register + signal sr : std_logic_vector(7 downto 0); -- 8bit shift register + signal shift, ld : std_logic; + + -- signals for state machine + signal go, host_ack : std_logic; +begin + -- hookup i2c core + u1: i2c_core port map (clk, nReset, clk_cnt, core_cmd, core_ack, core_busy, core_txd, core_rxd, SCL, SDA); + + -- generate host-command-acknowledge + cmd_ack <= host_ack; + + -- generate go-signal + go <= (read or write) and not host_ack; + + -- assign Dout output to shift-register + Dout <= sr; + + -- assign ack_out output to core_rxd (contains last received bit) + ack_out <= core_rxd; + + -- generate shift register + shift_register: process(clk) + begin + if (clk'event and clk = '1') then + if (ld = '1') then + sr <= din; + elsif (shift = '1') then + sr <= (sr(6 downto 0) & core_rxd); + end if; + end if; + end process shift_register; + + -- + -- state machine + -- + statemachine : block + type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); + signal state : states; + signal dcnt : unsigned(2 downto 0); + begin + -- + -- command interpreter, translate complex commands into simpler I2C commands + -- + nxt_state_decoder: process(clk, nReset, state) + variable nxt_state : states; + variable idcnt : unsigned(2 downto 0); + variable ihost_ack : std_logic; + variable icore_cmd : std_logic_vector(2 downto 0); + variable icore_txd : std_logic; + variable ishift, iload : std_logic; + begin + -- 8 databits (1byte) of data to shift-in/out + idcnt := dcnt; + + -- no acknowledge (until command complete) + ihost_ack := '0'; + + icore_txd := core_txd; + + -- keep current command to i2c_core + icore_cmd := core_cmd; + + -- no shifting or loading of shift-register + ishift := '0'; + iload := '0'; + + -- keep current state; + nxt_state := state; + case state is + when st_idle => + if (go = '1') then + if (start = '1') then + nxt_state := st_start; + icore_cmd := CMD_START; + elsif (read = '1') then + nxt_state := st_read; + icore_cmd := CMD_READ; + idcnt := "111"; + else + nxt_state := st_write; + icore_cmd := CMD_WRITE; + idcnt := "111"; + iload := '1'; + end if; + end if; + + when st_start => + if (core_ack = '1') then + if (read = '1') then + nxt_state := st_read; + icore_cmd := CMD_READ; + idcnt := "111"; + else + nxt_state := st_write; + icore_cmd := CMD_WRITE; + idcnt := "111"; + iload := '1'; + end if; + end if; + + when st_write => + if (core_ack = '1') then + idcnt := dcnt -1; -- count down Data_counter + icore_txd := sr(7); + if (dcnt = 0) then + nxt_state := st_ack; + icore_cmd := CMD_READ; + else + ishift := '1'; +-- icore_txd := sr(7); + end if; + end if; + + when st_read => + if (core_ack = '1') then + idcnt := dcnt -1; -- count down Data_counter + ishift := '1'; + if (dcnt = 0) then + nxt_state := st_ack; + icore_cmd := CMD_WRITE; + icore_txd := ack_in; + end if; + end if; + + when st_ack => + if (core_ack = '1') then + -- generate command acknowledge signal + ihost_ack := '1'; + + -- Perform an additional shift, needed for 'read' (store last received bit in shift register) + ishift := '1'; + + -- check for stop; Should a STOP command be generated ? + if (stop = '1') then + nxt_state := st_stop; + icore_cmd := CMD_STOP; + else + nxt_state := st_idle; + icore_cmd := CMD_NOP; + end if; + end if; + + when st_stop => + if (core_ack = '1') then + nxt_state := st_idle; + icore_cmd := CMD_NOP; + end if; + + when others => -- illegal states + nxt_state := st_idle; + icore_cmd := CMD_NOP; + end case; + + -- generate registers + if (nReset = '0') then + core_cmd <= CMD_NOP; + core_txd <= '0'; + + shift <= '0'; + ld <= '0'; + + dcnt <= "111"; + host_ack <= '0'; + + state <= st_idle; + elsif (clk'event and clk = '1') then + if (ena = '1') then + state <= nxt_state; + + dcnt <= idcnt; + shift <= ishift; + ld <= iload; + + core_cmd <= icore_cmd; + core_txd <= icore_txd; + + host_ack <= ihost_ack; + end if; + end if; + end process nxt_state_decoder; + + end block statemachine; + +end architecture structural; + + +-- +-- +-- I2C Core +-- +-- Translate simple commands into SCL/SDA transitions +-- Each command has 5 states, A/B/C/D/idle +-- +-- start: SCL ~~~~~~~~~~\____ +-- SDA ~~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- repstart SCL ____/~~~~\___ +-- SDA __/~~~\______ +-- x | A | B | C | D | i +-- +-- stop SCL ____/~~~~~~~~ +-- SDA ==\____/~~~~~ +-- x | A | B | C | D | i +-- +--- write SCL ____/~~~~\____ +-- SDA ==X=========X= +-- x | A | B | C | D | i +-- +--- read SCL ____/~~~~\____ +-- SDA XXXX=====XXXX +-- x | A | B | C | D | i +-- + +-- Timing: Normal mode Fast mode +----------------------------------------------------------------- +-- Fscl 100KHz 400KHz +-- Th_scl 4.0us 0.6us High period of SCL +-- Tl_scl 4.7us 1.3us Low period of SCL +-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition +-- Tsu:sto 4.0us 0.6us setup time for a stop conditon +-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity i2c_core is + port ( + clk : in std_logic; + nReset : in std_logic; + + clk_cnt : in unsigned(7 downto 0); + + cmd : in std_logic_vector(2 downto 0); + cmd_ack : out std_logic; + busy : out std_logic; + + Din : in std_logic; + Dout : out std_logic; + + SCL : inout std_logic; + SDA : inout std_logic + ); +end entity i2c_core; + +architecture structural of i2c_core is + constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; + constant CMD_START : std_logic_vector(2 downto 0) := "010"; + constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; + constant CMD_READ : std_logic_vector(2 downto 0) := "100"; + constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; + + type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); + signal state : cmds; + signal SDAo, SCLo : std_logic; + signal txd : std_logic; + signal clk_en, slave_wait :std_logic; + signal cnt : unsigned(7 downto 0) := clk_cnt; +begin + -- whenever the slave is not ready it can delay the cycle by pulling SCL low + slave_wait <= '1' when ((SCLo = '1') and (SCL = '0')) else '0'; + + -- generate clk enable signal + gen_clken: process(clk, nReset) + begin + if (nReset = '0') then + cnt <= (others => '0'); + clk_en <= '1'; --'0'; + elsif (clk'event and clk = '1') then + if (cnt = 0) then + clk_en <= '1'; + cnt <= clk_cnt; + else + if (slave_wait = '0') then + cnt <= cnt -1; + end if; + clk_en <= '0'; + end if; + end if; + end process gen_clken; + + -- generate statemachine + nxt_state_decoder : process (clk, nReset, state, cmd, SDA) + variable nxt_state : cmds; + variable icmd_ack, ibusy, store_sda : std_logic; + variable itxd : std_logic; + begin + + nxt_state := state; + + icmd_ack := '0'; -- default no acknowledge + ibusy := '1'; -- default busy + + store_sda := '0'; + + itxd := txd; + + case (state) is + -- idle + when idle => + case cmd is + when CMD_START => + nxt_state := start_a; + icmd_ack := '1'; -- command completed + + when CMD_STOP => + nxt_state := stop_a; + icmd_ack := '1'; -- command completed + + when CMD_WRITE => + nxt_state := wr_a; + icmd_ack := '1'; -- command completed + itxd := Din; + + when CMD_READ => + nxt_state := rd_a; + icmd_ack := '1'; -- command completed + + when others => + nxt_state := idle; +-- don't acknowledge NOP command icmd_ack := '1'; -- command completed + ibusy := '0'; + end case; + + -- start + when start_a => + nxt_state := start_b; + + when start_b => + nxt_state := start_c; + + when start_c => + nxt_state := start_d; + + when start_d => + nxt_state := idle; + ibusy := '0'; -- not busy when idle + + + -- stop + when stop_a => + nxt_state := stop_b; + + when stop_b => + nxt_state := stop_c; + + when stop_c => +-- nxt_state := stop_d; + +-- when stop_d => + nxt_state := idle; + ibusy := '0'; -- not busy when idle + + -- read + when rd_a => + nxt_state := rd_b; + + when rd_b => + nxt_state := rd_c; + + when rd_c => + nxt_state := rd_d; + store_sda := '1'; + + when rd_d => + nxt_state := idle; + ibusy := '0'; -- not busy when idle + + -- write + when wr_a => + nxt_state := wr_b; + + when wr_b => + nxt_state := wr_c; + + when wr_c => + nxt_state := wr_d; + + when wr_d => + nxt_state := idle; + ibusy := '0'; -- not busy when idle + + end case; + + -- generate regs + if (nReset = '0') then + state <= idle; + cmd_ack <= '0'; + busy <= '0'; + txd <= '0'; + Dout <= '0'; + elsif (clk'event and clk = '1') then + if (clk_en = '1') then + state <= nxt_state; + busy <= ibusy; + + txd <= itxd; + if (store_sda = '1') then + Dout <= SDA; + end if; + end if; + + cmd_ack <= icmd_ack and clk_en; + end if; + end process nxt_state_decoder; + + -- + -- convert states to SCL and SDA signals + -- + output_decoder: process (clk, nReset, state) + variable iscl, isda : std_logic; + begin + case (state) is + when idle => + iscl := SCLo; -- keep SCL in same state + isda := SDA; -- keep SDA in same state + + -- start + when start_a => + iscl := SCLo; -- keep SCL in same state (for repeated start) + isda := '1'; -- set SDA high + + when start_b => + iscl := '1'; -- set SCL high + isda := '1'; -- keep SDA high + + when start_c => + iscl := '1'; -- keep SCL high + isda := '0'; -- sel SDA low + + when start_d => + iscl := '0'; -- set SCL low + isda := '0'; -- keep SDA low + + -- stop + when stop_a => + iscl := '0'; -- keep SCL disabled + isda := '0'; -- set SDA low + + when stop_b => + iscl := '1'; -- set SCL high + isda := '0'; -- keep SDA low + + when stop_c => + iscl := '1'; -- keep SCL high + isda := '1'; -- set SDA high + + -- write + when wr_a => + iscl := '0'; -- keep SCL low +-- isda := txd; -- set SDA + isda := Din; + + when wr_b => + iscl := '1'; -- set SCL high +-- isda := txd; -- set SDA + isda := Din; + + when wr_c => + iscl := '1'; -- keep SCL high +-- isda := txd; -- set SDA + isda := Din; + + when wr_d => + iscl := '0'; -- set SCL low +-- isda := txd; -- set SDA + isda := Din; + + -- read + when rd_a => + iscl := '0'; -- keep SCL low + isda := '1'; -- tri-state SDA + + when rd_b => + iscl := '1'; -- set SCL high + isda := '1'; -- tri-state SDA + + when rd_c => + iscl := '1'; -- keep SCL high + isda := '1'; -- tri-state SDA + + when rd_d => + iscl := '0'; -- set SCL low + isda := '1'; -- tri-state SDA + end case; + + -- generate registers + if (nReset = '0') then + SCLo <= '1'; + SDAo <= '1'; + elsif (clk'event and clk = '1') then + if (clk_en = '1') then + SCLo <= iscl; + SDAo <= isda; + end if; + end if; + end process output_decoder; + + SCL <= '0' when (SCLo = '0') else 'Z'; -- since SCL is externally pulled-up convert a '1' to a 'Z'(tri-state) + SDA <= '0' when (SDAo = '0') else 'Z'; -- since SDA is externally pulled-up convert a '1' to a 'Z'(tri-state) +-- SCL <= SCLo; +-- SDA <= SDAo; + +end architecture structural; + + + + diff --git a/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd b/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd new file mode 100644 index 000000000..1b8eb96d2 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd @@ -0,0 +1,495 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 I2C Master Core; bit-controller ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $ +-- +-- $Date: 2006/10/11 12:10:13 $ +-- $Revision: 1.14 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: i2c_master_bit_ctrl.vhd,v $ +-- Revision 1.14 2006/10/11 12:10:13 rherveille +-- Added missing semicolons ';' on endif +-- +-- Revision 1.13 2006/10/06 10:48:24 rherveille +-- fixed short scl high pulse after clock stretch +-- +-- Revision 1.12 2004/05/07 11:53:31 rherveille +-- Fixed previous fix :) Made a variable vs signal mistake. +-- +-- Revision 1.11 2004/05/07 11:04:00 rherveille +-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. +-- +-- Revision 1.10 2004/02/27 07:49:43 rherveille +-- Fixed a bug in the arbitration-lost signal generation. VHDL version only. +-- +-- Revision 1.9 2003/08/12 14:48:37 rherveille +-- Forgot an 'end if' :-/ +-- +-- Revision 1.8 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.7 2003/02/05 00:06:02 rherveille +-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. +-- +-- Revision 1.6 2003/02/01 02:03:06 rherveille +-- Fixed a few 'arbitration lost' bugs. VHDL version only. +-- +-- Revision 1.5 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.4 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.3 2002/10/30 18:09:53 rherveille +-- Fixed some reported minor start/stop generation timing issuess. +-- +-- Revision 1.2 2002/06/15 07:37:04 rherveille +-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. +-- +-- Revision 1.1 2001/11/05 12:02:33 rherveille +-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. +-- Code updated, is now up-to-date to doc. rev.0.4. +-- Added headers. +-- + + +-- +------------------------------------- +-- Bit controller section +------------------------------------ +-- +-- Translate simple commands into SCL/SDA transitions +-- Each command has 5 states, A/B/C/D/idle +-- +-- start: SCL ~~~~~~~~~~~~~~\____ +-- SDA XX/~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- repstart SCL ______/~~~~~~~\___ +-- SDA __/~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- stop SCL _______/~~~~~~~~~~~ +-- SDA ==\___________/~~~~~ +-- x | A | B | C | D | i +-- +--- write SCL ______/~~~~~~~\____ +-- SDA XXX===============XX +-- x | A | B | C | D | i +-- +--- read SCL ______/~~~~~~~\____ +-- SDA XXXXXXX=XXXXXXXXXXX +-- x | A | B | C | D | i +-- + +-- Timing: Normal mode Fast mode +----------------------------------------------------------------- +-- Fscl 100KHz 400KHz +-- Th_scl 4.0us 0.6us High period of SCL +-- Tl_scl 4.7us 1.3us Low period of SCL +-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition +-- Tsu:sto 4.0us 0.6us setup time for a stop conditon +-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity i2c_master_bit_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; + nReset : in std_logic; + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- clock prescale value + + cmd : in std_logic_vector(3 downto 0); + cmd_ack : out std_logic; -- command completed + busy : out std_logic; -- i2c bus busy + al : out std_logic; -- arbitration lost + + din : in std_logic; + dout : out std_logic; + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_bit_ctrl; + +architecture structural of i2c_master_bit_ctrl is + constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; + constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; + constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; + constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; + constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; + + type states is (idle, start_a, start_b, start_c, start_d, start_e, + stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); + signal c_state : states; + + signal iscl_oen, isda_oen : std_logic; -- internal I2C lines + signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) + signal dscl_oen : std_logic; -- delayed scl_oen signals + signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs + signal clk_en, slave_wait : std_logic; -- clock generation signals + signal ial : std_logic; -- internal arbitration lost signal +-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation) + signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) + +begin + -- whenever the slave is not ready it can delay the cycle by pulling SCL low + -- delay scl_oen + process (clk) + begin + if (clk'event and clk = '1') then + dscl_oen <= iscl_oen; + end if; + end process; + slave_wait <= dscl_oen and not sSCL; + + -- generate clk enable signal + gen_clken: process(clk, nReset) + begin + if (nReset = '0') then + cnt <= (others => '0'); + clk_en <= '1'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + cnt <= (others => '0'); + clk_en <= '1'; + elsif ( (cnt = 0) or (ena = '0') ) then + cnt <= clk_cnt; + clk_en <= '1'; + elsif (slave_wait = '1') then + cnt <= cnt; + clk_en <= '0'; + else + cnt <= cnt -1; + clk_en <= '0'; + end if; + end if; + end process gen_clken; + + + -- generate bus status controller + bus_status_ctrl: block + signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA + signal sta_condition : std_logic; -- start detected + signal sto_condition : std_logic; -- stop detected + signal cmd_stop : std_logic; -- STOP command + signal ibusy : std_logic; -- internal busy signal + begin + -- synchronize SCL and SDA inputs + synch_scl_sda: process(clk, nReset) + begin + if (nReset = '0') then + sSCL <= '1'; + sSDA <= '1'; + + dSCL <= '1'; + dSDA <= '1'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + sSCL <= '1'; + sSDA <= '1'; + + dSCL <= '1'; + dSDA <= '1'; + else + sSCL <= scl_i; + sSDA <= sda_i; + + dSCL <= sSCL; + dSDA <= sSDA; + end if; + end if; + end process synch_SCL_SDA; + + -- detect start condition => detect falling edge on SDA while SCL is high + -- detect stop condition => detect rising edge on SDA while SCL is high + detect_sta_sto: process(clk, nReset) + begin + if (nReset = '0') then + sta_condition <= '0'; + sto_condition <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + sta_condition <= '0'; + sto_condition <= '0'; + else + sta_condition <= (not sSDA and dSDA) and sSCL; + sto_condition <= (sSDA and not dSDA) and sSCL; + end if; + end if; + end process detect_sta_sto; + + -- generate i2c-bus busy signal + gen_busy: process(clk, nReset) + begin + if (nReset = '0') then + ibusy <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + ibusy <= '0'; + else + ibusy <= (sta_condition or ibusy) and not sto_condition; + end if; + end if; + end process gen_busy; + busy <= ibusy; + + + -- generate arbitration lost signal + -- aribitration lost when: + -- 1) master drives SDA high, but the i2c bus is low + -- 2) stop detected while not requested (detect during 'idle' state) + gen_al: process(clk, nReset) + begin + if (nReset = '0') then + cmd_stop <= '0'; + ial <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + cmd_stop <= '0'; + ial <= '0'; + else + if (clk_en = '1') then + if (cmd = I2C_CMD_STOP) then + cmd_stop <= '1'; + else + cmd_stop <= '0'; + end if; + end if; + + if (c_state = idle) then + ial <= (sda_chk and not sSDA and isda_oen); + else + ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop); + end if; + + end if; + end if; + end process gen_al; + al <= ial; + + -- generate dout signal, store dout on rising edge of SCL + gen_dout: process(clk) + begin + if (clk'event and clk = '1') then + if (sSCL = '1' and dSCL = '0') then + dout <= sSDA; + end if; + end if; + end process gen_dout; + end block bus_status_ctrl; + + + -- generate statemachine + nxt_state_decoder : process (clk, nReset, c_state, cmd) + begin + if (nReset = '0') then + c_state <= idle; + cmd_ack <= '0'; + iscl_oen <= '1'; + isda_oen <= '1'; + sda_chk <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1' or ial = '1') then + c_state <= idle; + cmd_ack <= '0'; + iscl_oen <= '1'; + isda_oen <= '1'; + sda_chk <= '0'; + else + cmd_ack <= '0'; -- default no acknowledge + + if (clk_en = '1') then + case (c_state) is + -- idle + when idle => + case cmd is + when I2C_CMD_START => c_state <= start_a; + when I2C_CMD_STOP => c_state <= stop_a; + when I2C_CMD_WRITE => c_state <= wr_a; + when I2C_CMD_READ => c_state <= rd_a; + when others => c_state <= idle; -- NOP command + end case; + + iscl_oen <= iscl_oen; -- keep SCL in same state + isda_oen <= isda_oen; -- keep SDA in same state + sda_chk <= '0'; -- don't check SDA + + -- start + when start_a => + c_state <= start_b; + iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start) + isda_oen <= '1'; -- set SDA high + sda_chk <= '0'; -- don't check SDA + + when start_b => + c_state <= start_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '1'; -- keep SDA high + sda_chk <= '0'; -- don't check SDA + + when start_c => + c_state <= start_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- set SDA low + sda_chk <= '0'; -- don't check SDA + + when start_d => + c_state <= start_e; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when start_e => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + -- stop + when stop_a => + c_state <= stop_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= '0'; -- set SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_b => + c_state <= stop_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_c => + c_state <= stop_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '1'; -- set SDA high + sda_chk <= '0'; -- don't check SDA + + -- read + when rd_a => + c_state <= rd_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_b => + c_state <= rd_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_c => + c_state <= rd_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + -- write + when wr_a => + c_state <= wr_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= din; -- set SDA + sda_chk <= '0'; -- don't check SDA (SCL low) + + when wr_b => + c_state <= wr_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= din; -- keep SDA + sda_chk <= '1'; -- check SDA + + when wr_c => + c_state <= wr_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= din; -- keep SDA + sda_chk <= '1'; -- check SDA + + when wr_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= din; -- keep SDA + sda_chk <= '0'; -- don't check SDA (SCL low) + + when others => + + end case; + end if; + end if; + end if; + end process nxt_state_decoder; + + + -- assign outputs + scl_o <= '0'; + scl_oen <= iscl_oen; + sda_o <= '0'; + sda_oen <= isda_oen; +end architecture structural; + diff --git a/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd b/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd new file mode 100644 index 000000000..bdb2a881e --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd @@ -0,0 +1,370 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $ +-- +-- $Date: 2004/02/18 11:41:48 $ +-- $Revision: 1.5 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: i2c_master_byte_ctrl.vhd,v $ +-- Revision 1.5 2004/02/18 11:41:48 rherveille +-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. +-- +-- Revision 1.4 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.3 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.2 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.1 2001/11/05 12:02:33 rherveille +-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. +-- Code updated, is now up-to-date to doc. rev.0.4. +-- Added headers. +-- + + + + +-- +------------------------------------------ +-- Byte controller section +------------------------------------------ +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity i2c_master_byte_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) + nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; -- command done + ack_out : out std_logic; + i2c_busy : out std_logic; -- arbitration lost + i2c_al : out std_logic; -- i2c bus busy + dout : out std_logic_vector(7 downto 0); + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_byte_ctrl; + +architecture structural of i2c_master_byte_ctrl is + component i2c_master_bit_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; + nReset : in std_logic; + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- clock prescale value + + cmd : in std_logic_vector(3 downto 0); + cmd_ack : out std_logic; -- command done + busy : out std_logic; -- i2c bus busy + al : out std_logic; -- arbitration lost + + din : in std_logic; + dout : out std_logic; + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); + end component i2c_master_bit_ctrl; + + -- commands for bit_controller block + constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; + constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; + constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; + constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; + constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; + + -- signals for bit_controller + signal core_cmd : std_logic_vector(3 downto 0); + signal core_ack, core_txd, core_rxd : std_logic; + signal al : std_logic; + + -- signals for shift register + signal sr : std_logic_vector(7 downto 0); -- 8bit shift register + signal shift, ld : std_logic; + + -- signals for state machine + signal go, host_ack : std_logic; + signal dcnt : unsigned(2 downto 0); -- data counter + signal cnt_done : std_logic; + +begin + -- hookup bit_controller + bit_ctrl: i2c_master_bit_ctrl port map( + clk => clk, + rst => rst, + nReset => nReset, + ena => ena, + clk_cnt => clk_cnt, + cmd => core_cmd, + cmd_ack => core_ack, + busy => i2c_busy, + al => al, + din => core_txd, + dout => core_rxd, + scl_i => scl_i, + scl_o => scl_o, + scl_oen => scl_oen, + sda_i => sda_i, + sda_o => sda_o, + sda_oen => sda_oen + ); + i2c_al <= al; + + -- generate host-command-acknowledge + cmd_ack <= host_ack; + + -- generate go-signal + go <= (read or write or stop) and not host_ack; + + -- assign Dout output to shift-register + dout <= sr; + + -- generate shift register + shift_register: process(clk, nReset) + begin + if (nReset = '0') then + sr <= (others => '0'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + sr <= (others => '0'); + elsif (ld = '1') then + sr <= din; + elsif (shift = '1') then + sr <= (sr(6 downto 0) & core_rxd); + end if; + end if; + end process shift_register; + + -- generate data-counter + data_cnt: process(clk, nReset) + begin + if (nReset = '0') then + dcnt <= (others => '0'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + dcnt <= (others => '0'); + elsif (ld = '1') then + dcnt <= (others => '1'); -- load counter with 7 + elsif (shift = '1') then + dcnt <= dcnt -1; + end if; + end if; + end process data_cnt; + + cnt_done <= '1' when (dcnt = 0) else '0'; + + -- + -- state machine + -- + statemachine : block + type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); + signal c_state : states; + begin + -- + -- command interpreter, translate complex commands into simpler I2C commands + -- + nxt_state_decoder: process(clk, nReset) + begin + if (nReset = '0') then + core_cmd <= I2C_CMD_NOP; + core_txd <= '0'; + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + c_state <= st_idle; + ack_out <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1' or al = '1') then + core_cmd <= I2C_CMD_NOP; + core_txd <= '0'; + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + c_state <= st_idle; + ack_out <= '0'; + else + -- initialy reset all signal + core_txd <= sr(7); + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + + case c_state is + when st_idle => + if (go = '1') then + if (start = '1') then + c_state <= st_start; + core_cmd <= I2C_CMD_START; + elsif (read = '1') then + c_state <= st_read; + core_cmd <= I2C_CMD_READ; + elsif (write = '1') then + c_state <= st_write; + core_cmd <= I2C_CMD_WRITE; + else -- stop + c_state <= st_stop; + core_cmd <= I2C_CMD_STOP; + end if; + + ld <= '1'; + end if; + + when st_start => + if (core_ack = '1') then + if (read = '1') then + c_state <= st_read; + core_cmd <= I2C_CMD_READ; + else + c_state <= st_write; + core_cmd <= I2C_CMD_WRITE; + end if; + + ld <= '1'; + end if; + + when st_write => + if (core_ack = '1') then + if (cnt_done = '1') then + c_state <= st_ack; + core_cmd <= I2C_CMD_READ; + else + c_state <= st_write; -- stay in same state + core_cmd <= I2C_CMD_WRITE; -- write next bit + shift <= '1'; + end if; + end if; + + when st_read => + if (core_ack = '1') then + if (cnt_done = '1') then + c_state <= st_ack; + core_cmd <= I2C_CMD_WRITE; + else + c_state <= st_read; -- stay in same state + core_cmd <= I2C_CMD_READ; -- read next bit + end if; + + shift <= '1'; + core_txd <= ack_in; + end if; + + when st_ack => + if (core_ack = '1') then + -- check for stop; Should a STOP command be generated ? + if (stop = '1') then + c_state <= st_stop; + core_cmd <= I2C_CMD_STOP; + else + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + + -- generate command acknowledge signal + host_ack <= '1'; + end if; + + -- assign ack_out output to core_rxd (contains last received bit) + ack_out <= core_rxd; + + core_txd <= '1'; + else + core_txd <= ack_in; + end if; + + when st_stop => + if (core_ack = '1') then + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + + -- generate command acknowledge signal + host_ack <= '1'; + end if; + + when others => -- illegal states + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + report ("Byte controller entered illegal state."); + + end case; + + end if; + end if; + end process nxt_state_decoder; + + end block statemachine; + +end architecture structural; + diff --git a/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd b/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd new file mode 100644 index 000000000..a2557120f --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd @@ -0,0 +1,359 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 compl. I2C Master Core; top level ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $ +-- +-- $Date: 2004/03/14 10:17:03 $ +-- $Revision: 1.7 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: i2c_master_top.vhd,v $ +-- Revision 1.7 2004/03/14 10:17:03 rherveille +-- Fixed simulation issue when writing to CR register +-- +-- Revision 1.6 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.5 2003/02/01 02:03:06 rherveille +-- Fixed a few 'arbitration lost' bugs. VHDL version only. +-- +-- Revision 1.4 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.3 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.2 2001/11/10 10:52:44 rherveille +-- Changed PRER reset value from 0x0000 to 0xffff, conform specs. +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity i2c_master_top is + generic( + ARST_LVL : std_logic := '0' -- asynchronous reset level + ); + port ( + -- wishbone signals + wb_clk_i : in std_logic; -- master clock input + wb_rst_i : in std_logic := '0'; -- synchronous active high reset + arst_i : in std_logic := not ARST_LVL; -- asynchronous reset + wb_adr_i : in unsigned(2 downto 0); -- lower address bits + wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input + wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output + wb_we_i : in std_logic; -- Write enable input + wb_stb_i : in std_logic; -- Strobe signals / core select signal + wb_cyc_i : in std_logic; -- Valid bus cycle input + wb_ack_o : out std_logic; -- Bus cycle acknowledge output + wb_inta_o : out std_logic; -- interrupt request output signal + + -- i2c lines + scl_pad_i : in std_logic; -- i2c clock line input + scl_pad_o : out std_logic; -- i2c clock line output + scl_padoen_o : out std_logic; -- i2c clock line output enable, active low + sda_pad_i : in std_logic; -- i2c data line input + sda_pad_o : out std_logic; -- i2c data line output + sda_padoen_o : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_top; + +architecture structural of i2c_master_top is + component i2c_master_byte_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) + nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; + ack_out : out std_logic; + i2c_busy : out std_logic; + i2c_al : out std_logic; + dout : out std_logic_vector(7 downto 0); + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); + end component i2c_master_byte_ctrl; + + -- registers + signal prer : unsigned(15 downto 0); -- clock prescale register + signal ctr : std_logic_vector(7 downto 0); -- control register + signal txr : std_logic_vector(7 downto 0); -- transmit register + signal rxr : std_logic_vector(7 downto 0); -- receive register + signal cr : std_logic_vector(7 downto 0); -- command register + signal sr : std_logic_vector(7 downto 0); -- status register + + -- internal reset signal + signal rst_i : std_logic; + + -- wishbone write access + signal wb_wacc : std_logic; + + -- internal acknowledge signal + signal iack_o : std_logic; + + -- done signal: command completed, clear command register + signal done : std_logic; + + -- command register signals + signal sta, sto, rd, wr, ack, iack : std_logic; + + signal core_en : std_logic; -- core enable signal + signal ien : std_logic; -- interrupt enable signal + + -- status register signals + signal irxack, rxack : std_logic; -- received aknowledge from slave + signal tip : std_logic; -- transfer in progress + signal irq_flag : std_logic; -- interrupt pending flag + signal i2c_busy : std_logic; -- i2c bus busy (start signal detected) + signal i2c_al, al : std_logic; -- arbitration lost + +begin + -- generate internal reset signal + rst_i <= arst_i xor ARST_LVL; + + -- generate acknowledge output signal + gen_ack_o : process(wb_clk_i) + begin + if (wb_clk_i'event and wb_clk_i = '1') then + iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored + end if; + end process gen_ack_o; + wb_ack_o <= iack_o; + + + -- generate wishbone write access signal + wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i; + + -- assign wb_dat_o + assign_dato : process(wb_clk_i) + begin + if (wb_clk_i'event and wb_clk_i = '1') then + case wb_adr_i is + when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0)); + when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8)); + when "010" => wb_dat_o <= ctr; + when "011" => wb_dat_o <= rxr; -- write is transmit register TxR + when "100" => wb_dat_o <= sr; -- write is command register CR + + -- Debugging registers: + -- These registers are not documented. + -- Functionality could change in future releases + when "101" => wb_dat_o <= txr; + when "110" => wb_dat_o <= cr; + when "111" => wb_dat_o <= (others => '0'); + when others => wb_dat_o <= (others => 'X'); -- for simulation only + end case; + end if; + end process assign_dato; + + + -- generate registers (CR, SR see below) + gen_regs: process(rst_i, wb_clk_i) + begin + if (rst_i = '0') then + prer <= (others => '1'); + ctr <= (others => '0'); + txr <= (others => '0'); + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + prer <= (others => '1'); + ctr <= (others => '0'); + txr <= (others => '0'); + elsif (wb_wacc = '1') then + case wb_adr_i is + when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i); + when "001" => prer(15 downto 8) <= unsigned(wb_dat_i); + when "010" => ctr <= wb_dat_i; + when "011" => txr <= wb_dat_i; + when "100" => null; --write to CR, avoid executing the others clause + + -- illegal cases, for simulation only + when others => + report ("Illegal write address, setting all registers to unknown."); + prer <= (others => 'X'); + ctr <= (others => 'X'); + txr <= (others => 'X'); + end case; + end if; + end if; + end process gen_regs; + + + -- generate command register + gen_cr: process(rst_i, wb_clk_i) + begin + if (rst_i = '0') then + cr <= (others => '0'); + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + cr <= (others => '0'); + elsif (wb_wacc = '1') then + if ( (core_en = '1') and (wb_adr_i = 4) ) then + -- only take new commands when i2c core enabled + -- pending commands are finished + cr <= wb_dat_i; + end if; + else + if (done = '1' or i2c_al = '1') then + cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost + end if; + + cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' + cr(0) <= '0'; -- clear IRQ_ACK bit + end if; + end if; + end process gen_cr; + + -- decode command register + sta <= cr(7); + sto <= cr(6); + rd <= cr(5); + wr <= cr(4); + ack <= cr(3); + iack <= cr(0); + + -- decode control register + core_en <= ctr(7); + ien <= ctr(6); + + -- hookup byte controller block + byte_ctrl: i2c_master_byte_ctrl port map ( + clk => wb_clk_i, + rst => wb_rst_i, + nReset => rst_i, + ena => core_en, + clk_cnt => prer, + start => sta, + stop => sto, + read => rd, + write => wr, + ack_in => ack, + i2c_busy => i2c_busy, + i2c_al => i2c_al, + din => txr, + cmd_ack => done, + ack_out => irxack, + dout => rxr, + scl_i => scl_pad_i, + scl_o => scl_pad_o, + scl_oen => scl_padoen_o, + sda_i => sda_pad_i, + sda_o => sda_pad_o, + sda_oen => sda_padoen_o + ); + + + -- status register block + interrupt request signal + st_irq_block : block + begin + -- generate status register bits + gen_sr_bits: process (wb_clk_i, rst_i) + begin + if (rst_i = '0') then + al <= '0'; + rxack <= '0'; + tip <= '0'; + irq_flag <= '0'; + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + al <= '0'; + rxack <= '0'; + tip <= '0'; + irq_flag <= '0'; + else + al <= i2c_al or (al and not sta); + rxack <= irxack; + tip <= (rd or wr); + + -- interrupt request flag is always generated + irq_flag <= (done or i2c_al or irq_flag) and not iack; + end if; + end if; + end process gen_sr_bits; + + -- generate interrupt request signals + gen_irq: process (wb_clk_i, rst_i) + begin + if (rst_i = '0') then + wb_inta_o <= '0'; + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + wb_inta_o <= '0'; + else + -- interrupt signal is only generated when IEN (interrupt enable bit) is set + wb_inta_o <= irq_flag and ien; + end if; + end if; + end process gen_irq; + + -- assign status register bits + sr(7) <= rxack; + sr(6) <= i2c_busy; + sr(5) <= al; + sr(4 downto 2) <= (others => '0'); -- reserved + sr(1) <= tip; + sr(0) <= irq_flag; + end block; + +end architecture structural; diff --git a/usrp2/opencores/i2c/rtl/vhdl/readme b/usrp2/opencores/i2c/rtl/vhdl/readme new file mode 100644 index 000000000..0d049f736 --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/readme @@ -0,0 +1,25 @@ + + +-- This code is provided for free and may be used and -- +-- distributed without restriction provided that the -- +-- copyright statement is not removed from the file and -- +-- that any derivative work contains the original -- +-- copyright notice and the associated disclaimer. -- + +-- Comments and suggestions are always welcome -- + +The i2c_master core consists of three files: + +- i2c_master_top -- top level +- i2c_master_byte_ctrl -- byte controller +- i2c_master_bit_ctrl -- bit controller + +VHDL needs to be compiled in order. The files are listed +above in descending order. + +I2C.VHD and tst_ds1621.vhd are not supported anymore. +They remain mostly for historical purposes, altough they +might prove usefull. + +Richard Herveille +rherveille@opencores.org diff --git a/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd b/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd new file mode 100644 index 000000000..ccf50460c --- /dev/null +++ b/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd @@ -0,0 +1,283 @@ +-- +-- +-- State machine for reading data from Dallas 1621 +-- +-- Testsystem for i2c controller +-- +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.i2c.all; + +entity DS1621_interface is + port ( + clk : in std_logic; + nReset : in std_logic; + + Dout : out std_logic_vector(7 downto 0); -- data read from ds1621 + + error : out std_logic; -- no correct ack received + + SCL : inout std_logic; + SDA : inout std_logic + ); +end entity DS1621_interface; + +architecture structural of DS1621_interface is + constant SLAVE_ADDR : std_logic_vector(6 downto 0) := "1001000"; + constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(20, 8); + + signal cmd_ack : std_logic; + signal D : std_logic_vector(7 downto 0); + signal lack, store_dout : std_logic; + + signal start, read, write, ack, stop : std_logic; + signal i2c_dout : std_logic_vector(7 downto 0); + +begin + -- hookup I2C controller + u1: simple_i2c port map (clk => clk, ena => '1', clk_cnt => clk_cnt, nReset => nReset, + read => read, write => write, start => start, stop => stop, ack_in => ack, cmd_ack => cmd_ack, + Din => D, Dout => i2c_dout, ack_out => lack, SCL => SCL, SDA => SDA); + + init_statemachine : block + type states is (i1, i2, i3, i4, i5, t1, t2, t3, t4, t5); + signal state : states; + begin + nxt_state_decoder: process(clk, nReset, state) + variable nxt_state : states; + variable iD : std_logic_vector(7 downto 0); + variable ierr : std_logic; + variable istart, iread, iwrite, iack, istop : std_logic; + variable istore_dout : std_logic; + begin + nxt_state := state; + ierr := '0'; + istore_dout := '0'; + + istart := start; + iread := read; + iwrite := write; + iack := ack; + istop := stop; + iD := D; + + case (state) is + -- init DS1621 + -- 1) send start condition + -- 2) send slave address + write + -- 3) check ack + -- 4) send "access config" command (0xAC) + -- 5) check ack + -- 6) send config register data (0x00) + -- 7) check ack + -- 8) send stop condition + -- 9) send start condition + -- 10) send slave address + write + -- 11) check ack + -- 12) send "start conversion" command (0xEE) + -- 13) check ack + -- 14) send stop condition + + when i1 => -- send start condition, sent slave address + write + nxt_state := i2; + istart := '1'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := (slave_addr & '0'); -- write to slave (R/W = '0') + + when i2 => -- send "access config" command + if (cmd_ack = '1') then + nxt_state := i3; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := x"AC"; + end if; + + when i3 => -- send config register data, sent stop condition + if (cmd_ack = '1') then + nxt_state := i4; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '1'; + iD := x"00"; + end if; + + when i4 => -- send start condition, sent slave address + write + if (cmd_ack = '1') then + nxt_state := i5; + + istart := '1'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := (slave_addr & '0'); -- write to slave (R/W = '0') + end if; + + when i5 => -- send "start conversion" command + stop condition + if (cmd_ack = '1') then + nxt_state := t1; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '1'; + iD := x"EE"; + end if; + -- read temperature + -- 1) sent start condition + -- 2) sent slave address + write + -- 3) check ack + -- 4) sent "read temperature" command (0xAA) + -- 5) check ack + -- 6) sent start condition + -- 7) sent slave address + read + -- 8) check ack + -- 9) read msb + -- 10) send ack + -- 11) read lsb + -- 12) send nack + -- 13) send stop condition + + when t1 => -- send start condition, sent slave address + write + if (cmd_ack = '1') then + nxt_state := t2; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '1'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := (slave_addr & '0'); -- write to slave (R/W = '0') + end if; + + when t2 => -- send read temperature command + if (cmd_ack = '1') then + nxt_state := t3; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := x"AA"; + end if; + + when t3 => -- send (repeated) start condition, send slave address + read + if (cmd_ack = '1') then + nxt_state := t4; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received, expected ACK + end if; + + istart := '1'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := (slave_addr & '1'); -- read from slave (R/W = '1') + end if; + + when t4 => -- read MSB (hi-byte), send acknowledge + if (cmd_ack = '1') then + nxt_state := t5; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '1'; + iwrite := '0'; + iack := '0'; --ACK + istop := '0'; + end if; + + when t5 => -- read LSB (lo-byte), send acknowledge, sent stop + if (cmd_ack = '1') then + nxt_state := t1; + + istart := '0'; + iread := '1'; + iwrite := '0'; + iack := '1'; --NACK + istop := '1'; + + istore_dout := '1'; + end if; + end case; + + -- genregs + if (nReset = '0') then + state <= i1; + error <= '0'; + store_dout <= '0'; + + start <= '0'; + read <= '0'; + write <= '0'; + ack <= '0'; + stop <= '0'; + D <= (others => '0'); + elsif (clk'event and clk = '1') then + state <= nxt_state; + error <= ierr; + store_dout <= istore_dout; + + start <= istart; + read <= iread; + write <= iwrite; + ack <= iack; + stop <= istop; + D <= iD; + end if; + end process nxt_state_decoder; + end block init_statemachine; + + -- store temp + gen_dout : process(clk) + begin + if (clk'event and clk = '1') then + if (store_dout = '1') then + Dout <= i2c_dout; + end if; + end if; + end process gen_dout; + +end architecture structural; + + diff --git a/usrp2/opencores/i2c/sim/CVS/Entries b/usrp2/opencores/i2c/sim/CVS/Entries new file mode 100644 index 000000000..d08a896a5 --- /dev/null +++ b/usrp2/opencores/i2c/sim/CVS/Entries @@ -0,0 +1 @@ +D/i2c_verilog//// diff --git a/usrp2/opencores/i2c/sim/CVS/Repository b/usrp2/opencores/i2c/sim/CVS/Repository new file mode 100644 index 000000000..500d85906 --- /dev/null +++ b/usrp2/opencores/i2c/sim/CVS/Repository @@ -0,0 +1 @@ +i2c/sim diff --git a/usrp2/opencores/i2c/sim/CVS/Root b/usrp2/opencores/i2c/sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/sim/CVS/Template b/usrp2/opencores/i2c/sim/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Entries b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Entries new file mode 100644 index 000000000..8ab9f73a7 --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Entries @@ -0,0 +1 @@ +D/run//// diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Repository new file mode 100644 index 000000000..b97ee33c8 --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Repository @@ -0,0 +1 @@ +i2c/sim/i2c_verilog diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Entries b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Entries new file mode 100644 index 000000000..ddea0baae --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Entries @@ -0,0 +1,6 @@ +/bench.vcd/1.1/Sat Jun 15 07:37:05 2002// +/ncverilog.key/1.1/Sat Jun 15 07:37:11 2002// +/ncverilog.log/1.1/Sat Jun 15 07:37:11 2002// +/run/1.2/Fri Apr 6 09:02:38 2007// +D/INCA_libs//// +D/waves//// diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Repository new file mode 100644 index 000000000..bdd990e7c --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Repository @@ -0,0 +1 @@ +i2c/sim/i2c_verilog/run diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository new file mode 100644 index 000000000..6b760e397 --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository @@ -0,0 +1 @@ +i2c/sim/i2c_verilog/run/INCA_libs diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd b/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd new file mode 100644 index 000000000..9a364415f --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd @@ -0,0 +1,1496812 @@ +$date + Jun 15, 2002 13:36:37 +$end +$version + ncsim: v03.40.(b001) +$end +$timescale + 10 ps +$end + +$scope module tst_bench_top $end +$var reg 1 ! clk $end +$var reg 1 " rstn $end +$var wire 1 # adr [31] $end +$var wire 1 $ adr [30] $end +$var wire 1 % adr [29] $end +$var wire 1 & adr [28] $end +$var wire 1 ' adr [27] $end +$var wire 1 ( adr [26] $end +$var wire 1 ) adr [25] $end +$var wire 1 * adr [24] $end +$var wire 1 + adr [23] $end +$var wire 1 , adr [22] $end +$var wire 1 - adr [21] $end +$var wire 1 . adr [20] $end +$var wire 1 / adr [19] $end +$var wire 1 0 adr [18] $end +$var wire 1 1 adr [17] $end +$var wire 1 2 adr [16] $end +$var wire 1 3 adr [15] $end +$var wire 1 4 adr [14] $end +$var wire 1 5 adr [13] $end +$var wire 1 6 adr [12] $end +$var wire 1 7 adr [11] $end +$var wire 1 8 adr [10] $end +$var wire 1 9 adr [9] $end +$var wire 1 : adr [8] $end +$var wire 1 ; adr [7] $end +$var wire 1 < adr [6] $end +$var wire 1 = adr [5] $end +$var wire 1 > adr [4] $end +$var wire 1 ? adr [3] $end +$var wire 1 @ adr [2] $end +$var wire 1 A adr [1] $end +$var wire 1 B adr [0] $end +$var wire 8 C dat_i [7:0] $end +$var wire 8 D dat_o [7:0] $end +$var wire 1 E we $end +$var wire 1 F stb $end +$var wire 1 G cyc $end +$var wire 1 H ack $end +$var wire 1 I inta $end +$var reg 8 J q [7:0] $end +$var reg 8 K qq [7:0] $end +$var wire 1 L scl $end +$var wire 1 M scl_o $end +$var wire 1 N scl_oen $end +$var wire 1 O sda $end +$var wire 1 P sda_o $end +$var wire 1 Q sda_oen $end +$var parameter 3 R PRER_LO $end +$var parameter 3 S PRER_HI $end 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+#43363000 +0! +#43363500 +1! +#43364000 +0! +#43364500 +1! +#43365000 +0! +#43365500 +1! +#43366000 +0! +#43366500 +1! +#43367000 +0! +#43367500 +1! +#43368000 +0! +#43368500 +1! +#43369000 +0! +#43369500 +1! +#43370000 +0! +#43370500 +1! +#43371000 +0! +#43371500 +1! +#43372000 +0! +#43372500 +1! +#43373000 +0! +#43373500 +1! +#43374000 +0! +#43374500 +1! +#43375000 +0! +#43375500 +1! +#43376000 +0! +#43376500 +1! +#43377000 +0! +#43377500 +1! +#43378000 +0! +#43378500 +1! +#43379000 +0! +#43379500 +1! +#43380000 +0! +#43380500 +1! +#43381000 +0! +#43381500 +1! +#43382000 +0! +#43382500 +1! +#43383000 +0! +#43383500 +1! +#43384000 +0! +#43384500 +1! +#43385000 +0! +#43385500 +1! +#43386000 +0! +#43386500 +1! +#43387000 +0! +#43387500 +1! +#43388000 +0! +#43388500 +1! +#43388600 diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key b/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key new file mode 100644 index 000000000..a3abe5090 --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key @@ -0,0 +1 @@ +exit diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/run b/usrp2/opencores/i2c/sim/i2c_verilog/run/run new file mode 100755 index 000000000..41bcaab30 --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/run @@ -0,0 +1,25 @@ +#!/bin/csh + +set i2c = ../../.. +set bench = $i2c/bench +set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves + +ncverilog \ + \ + +access+rwc \ + +define+WAVES \ + \ + +incdir+$bench/verilog \ + +incdir+$i2c/rtl/verilog \ + \ + $i2c/rtl/verilog/i2c_master_bit_ctrl.v \ + $i2c/rtl/verilog/i2c_master_byte_ctrl.v \ + $i2c/rtl/verilog/i2c_master_top.v \ + \ + $bench/verilog/i2c_slave_model.v \ + $bench/verilog/wb_master_model.v \ + $bench/verilog/tst_bench_top.v + + + + diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository new file mode 100644 index 000000000..94d106eb0 --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository @@ -0,0 +1 @@ +i2c/sim/i2c_verilog/run/waves diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/software/CVS/Entries b/usrp2/opencores/i2c/software/CVS/Entries new file mode 100644 index 000000000..934613477 --- /dev/null +++ b/usrp2/opencores/i2c/software/CVS/Entries @@ -0,0 +1,2 @@ +D/drivers//// +D/include//// diff --git a/usrp2/opencores/i2c/software/CVS/Repository b/usrp2/opencores/i2c/software/CVS/Repository new file mode 100644 index 000000000..1b4c9f0bb --- /dev/null +++ b/usrp2/opencores/i2c/software/CVS/Repository @@ -0,0 +1 @@ +i2c/software diff --git a/usrp2/opencores/i2c/software/CVS/Root b/usrp2/opencores/i2c/software/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/software/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/software/CVS/Template b/usrp2/opencores/i2c/software/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/software/drivers/CVS/Entries b/usrp2/opencores/i2c/software/drivers/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/usrp2/opencores/i2c/software/drivers/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/opencores/i2c/software/drivers/CVS/Repository b/usrp2/opencores/i2c/software/drivers/CVS/Repository new file mode 100644 index 000000000..260d7873c --- /dev/null +++ b/usrp2/opencores/i2c/software/drivers/CVS/Repository @@ -0,0 +1 @@ +i2c/software/drivers diff --git a/usrp2/opencores/i2c/software/drivers/CVS/Root b/usrp2/opencores/i2c/software/drivers/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/software/drivers/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/software/drivers/CVS/Template b/usrp2/opencores/i2c/software/drivers/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/software/include/CVS/Entries b/usrp2/opencores/i2c/software/include/CVS/Entries new file mode 100644 index 000000000..ef11b0c73 --- /dev/null +++ b/usrp2/opencores/i2c/software/include/CVS/Entries @@ -0,0 +1,2 @@ +/oc_i2c_master.h/1.1/Thu Nov 22 10:02:19 2001// +D diff --git a/usrp2/opencores/i2c/software/include/CVS/Repository b/usrp2/opencores/i2c/software/include/CVS/Repository new file mode 100644 index 000000000..2ea08eeec --- /dev/null +++ b/usrp2/opencores/i2c/software/include/CVS/Repository @@ -0,0 +1 @@ +i2c/software/include diff --git a/usrp2/opencores/i2c/software/include/CVS/Root b/usrp2/opencores/i2c/software/include/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/software/include/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/software/include/CVS/Template b/usrp2/opencores/i2c/software/include/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/software/include/oc_i2c_master.h b/usrp2/opencores/i2c/software/include/oc_i2c_master.h new file mode 100644 index 000000000..7f7cfc417 --- /dev/null +++ b/usrp2/opencores/i2c/software/include/oc_i2c_master.h @@ -0,0 +1,102 @@ +/* +///////////////////////////////////////////////////////////////////// +//// //// +//// Include file for OpenCores I2C Master core //// +//// //// +//// File : oc_i2c_master.h //// +//// Function: c-include file //// +//// //// +//// Authors: Richard Herveille (richard@asics.ws) //// +//// Filip Miletic //// +//// //// +//// www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// Filip Miletic //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +*/ + +/* + * Definitions for the Opencores i2c master core + */ + +/* --- Definitions for i2c master's registers --- */ + +/* ----- Read-write access */ + +#define OC_I2C_PRER_LO 0x00 /* Low byte clock prescaler register */ +#define OC_I2C_PRER_HI 0x01 /* High byte clock prescaler register */ +#define OC_I2C_CTR 0x02 /* Control register */ + +/* ----- Write-only registers */ + +#define OC_I2C_TXR 0x03 /* Transmit byte register */ +#define OC_I2C_CR 0x04 /* Command register */ + +/* ----- Read-only registers */ + +#define OC_I2C_RXR 0x03 /* Receive byte register */ +#define OC_I2C_SR 0x04 /* Status register */ + +/* ----- Bits definition */ + +/* ----- Control register */ + +#define OC_I2C_EN (1<<7) /* Core enable bit: */ + /* 1 - core is enabled */ + /* 0 - core is disabled */ +#define OC_I2C_IEN (1<<6) /* Interrupt enable bit */ + /* 1 - Interrupt enabled */ + /* 0 - Interrupt disabled */ + /* Other bits in CR are reserved */ + +/* ----- Command register bits */ + +#define OC_I2C_STA (1<<7) /* Generate (repeated) start condition*/ +#define OC_I2C_STO (1<<6) /* Generate stop condition */ +#define OC_I2C_RD (1<<5) /* Read from slave */ +#define OC_I2C_WR (1<<4) /* Write to slave */ +#define OC_I2C_ACK (1<<3) /* Acknowledge from slave */ + /* 1 - ACK */ + /* 0 - NACK */ +#define OC_I2C_IACK (1<<0) /* Interrupt acknowledge */ + +/* ----- Status register bits */ + +#define OC_I2C_RXACK (1<<7) /* ACK received from slave */ + /* 1 - ACK */ + /* 0 - NACK */ +#define OC_I2C_BUSY (1<<6) /* Busy bit */ +#define OC_I2C_TIP (1<<1) /* Transfer in progress */ +#define OC_I2C_IF (1<<0) /* Interrupt flag */ + +/* bit testing and setting macros */ + +#define OC_ISSET(reg,bitmask) ((reg)&(bitmask)) +#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask))) +#define OC_BITSET(reg,bitmask) ((reg)|(bitmask)) +#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask))) +#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask)) +#define OC_REGMOVE(reg,value) ((reg)=(value)) \ No newline at end of file diff --git a/usrp2/opencores/i2c/verilog/CVS/Entries b/usrp2/opencores/i2c/verilog/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/usrp2/opencores/i2c/verilog/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/opencores/i2c/verilog/CVS/Repository b/usrp2/opencores/i2c/verilog/CVS/Repository new file mode 100644 index 000000000..acc23265f --- /dev/null +++ b/usrp2/opencores/i2c/verilog/CVS/Repository @@ -0,0 +1 @@ +i2c/verilog diff --git a/usrp2/opencores/i2c/verilog/CVS/Root b/usrp2/opencores/i2c/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/verilog/CVS/Template b/usrp2/opencores/i2c/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/i2c/vhdl/CVS/Entries b/usrp2/opencores/i2c/vhdl/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/usrp2/opencores/i2c/vhdl/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/opencores/i2c/vhdl/CVS/Repository b/usrp2/opencores/i2c/vhdl/CVS/Repository new file mode 100644 index 000000000..8ee00a788 --- /dev/null +++ b/usrp2/opencores/i2c/vhdl/CVS/Repository @@ -0,0 +1 @@ +i2c/vhdl diff --git a/usrp2/opencores/i2c/vhdl/CVS/Root b/usrp2/opencores/i2c/vhdl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/i2c/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/i2c/vhdl/CVS/Template b/usrp2/opencores/i2c/vhdl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/simple_gpio/CVS/Entries b/usrp2/opencores/simple_gpio/CVS/Entries new file mode 100644 index 000000000..df1462bb9 --- /dev/null +++ b/usrp2/opencores/simple_gpio/CVS/Entries @@ -0,0 +1 @@ +D/rtl//// diff --git a/usrp2/opencores/simple_gpio/CVS/Repository b/usrp2/opencores/simple_gpio/CVS/Repository new file mode 100644 index 000000000..b869a0de8 --- /dev/null +++ b/usrp2/opencores/simple_gpio/CVS/Repository @@ -0,0 +1 @@ +simple_gpio diff --git a/usrp2/opencores/simple_gpio/CVS/Root b/usrp2/opencores/simple_gpio/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/simple_gpio/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/simple_gpio/CVS/Template b/usrp2/opencores/simple_gpio/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/simple_gpio/rtl/CVS/Entries b/usrp2/opencores/simple_gpio/rtl/CVS/Entries new file mode 100644 index 000000000..8c6258130 --- /dev/null +++ b/usrp2/opencores/simple_gpio/rtl/CVS/Entries @@ -0,0 +1,2 @@ +/simple_gpio.v/1.2/Sun Dec 22 16:10:17 2002// +D diff --git a/usrp2/opencores/simple_gpio/rtl/CVS/Repository b/usrp2/opencores/simple_gpio/rtl/CVS/Repository new file mode 100644 index 000000000..955303d8a --- /dev/null +++ b/usrp2/opencores/simple_gpio/rtl/CVS/Repository @@ -0,0 +1 @@ +simple_gpio/rtl diff --git a/usrp2/opencores/simple_gpio/rtl/CVS/Root b/usrp2/opencores/simple_gpio/rtl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/simple_gpio/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/simple_gpio/rtl/CVS/Template b/usrp2/opencores/simple_gpio/rtl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/simple_gpio/rtl/simple_gpio.v b/usrp2/opencores/simple_gpio/rtl/simple_gpio.v new file mode 100644 index 000000000..0b78f9921 --- /dev/null +++ b/usrp2/opencores/simple_gpio/rtl/simple_gpio.v @@ -0,0 +1,193 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple General Purpose IO core //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: simple_gpio.v,v 1.2 2002/12/22 16:10:17 rherveille Exp $ +// +// $Date: 2002/12/22 16:10:17 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: simple_gpio.v,v $ +// Revision 1.2 2002/12/22 16:10:17 rherveille +// Fixed some typos in the documentation section. +// +// + + + +// +// Very basic 8bit GPIO core +// +// +// Registers: +// +// 0x00: Control Register +// bits 7:0 R/W Input/Output '1' = output mode +// '0' = input mode +// 0x01: Line Register +// bits 7:0 R Status Current GPIO pin level +// W Output GPIO pin output level +// +// +// HOWTO: +// +// Use a pin as an input: +// Program the corresponding bit in the control register to 'input mode' ('0'). +// The pin's state (input level) can be checked by reading the Line Register. +// Writing to the GPIO pin's Line Register bit while in input mode has no effect. +// +// Use a pin as an output: +// Program the corresponding bit in the control register to 'output mode' ('1'). +// Program the GPIO pin's output level by writing to the corresponding bit in +// the Line Register. +// Reading the GPIO pin's Line Register bit while in output mode returns the +// current output level. +// +// Addapt the core for fewer GPIOs: +// If less than 8 GPIOs are required, than the 'io' parameter can be set to +// the amount of required interrupts. GPIOs are mapped starting at the LSBs. +// So only the 'io' LSBs per register are valid. +// All other bits (i.e. the 8-'io' MSBs) are set to zero '0'. +// Codesize is approximately linear to the amount of interrupts. I.e. using +// 4 instead of 8 GPIO sources reduces the size by approx. half. +// + + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module simple_gpio( + clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, + gpio +); + + // + // Inputs & outputs + // + parameter io = 8; // number of GPIOs + + // 8bit WISHBONE bus slave interface + input clk_i; // clock + input rst_i; // reset (asynchronous active low) + input cyc_i; // cycle + input stb_i; // strobe + input adr_i; // address adr_i[1] + input we_i; // write enable + input [ 7:0] dat_i; // data output + output [ 7:0] dat_o; // data input + output ack_o; // normal bus termination + + // GPIO pins + inout [io:1] gpio; + + // + // Module body + // + reg [io:1] ctrl, line; // ControlRegister, LineRegister + reg [io:1] lgpio, llgpio; // LatchedGPIO pins + + // + // perform parameter checks + // + // synopsys translate_off + initial + begin + if(io > 8) + $display("simple_gpio: max. 8 GPIOs supported."); + end + // synopsys translate_on + + // + // WISHBONE interface + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i or negedge rst_i) + if (~rst_i) + begin + ctrl <= #1 {io{1'b0}}; + line <= #1 {io{1'b0}}; + end + else if (wb_wr) + if ( adr_i ) + line <= #1 dat_i[io-1:0]; + else + ctrl <= #1 dat_i[io-1:0]; + + + reg [7:0] dat_o; + always @(posedge clk_i) + if ( adr_i ) + dat_o <= #1 { {(8-io){1'b0}}, llgpio}; + else + dat_o <= #1 { {(8-io){1'b0}}, ctrl}; + + reg ack_o; + always @(posedge clk_i or negedge rst_i) + if (~rst_i) + ack_o <= #1 1'b0; + else + ack_o <= #1 wb_acc & !ack_o; + + + // + // GPIO section + + // latch GPIO input pins + always @(posedge clk_i) + lgpio <= #1 gpio; + + // latch again (reduce meta-stability risc) + always @(posedge clk_i) + llgpio <= #1 lgpio; + + // assign GPIO outputs + integer n; + reg [io:1] igpio; // temporary internal signal + + always @(ctrl or line) + for(n=1;n<=io;n=n+1) + igpio[n] <= ctrl[n] ? line[n] : 1'bz; + + assign gpio = igpio; + +endmodule + diff --git a/usrp2/opencores/simple_pic/CVS/Entries b/usrp2/opencores/simple_pic/CVS/Entries new file mode 100644 index 000000000..df1462bb9 --- /dev/null +++ b/usrp2/opencores/simple_pic/CVS/Entries @@ -0,0 +1 @@ +D/rtl//// diff --git a/usrp2/opencores/simple_pic/CVS/Repository b/usrp2/opencores/simple_pic/CVS/Repository new file mode 100644 index 000000000..73de5bf2b --- /dev/null +++ b/usrp2/opencores/simple_pic/CVS/Repository @@ -0,0 +1 @@ +simple_pic diff --git a/usrp2/opencores/simple_pic/CVS/Root b/usrp2/opencores/simple_pic/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/simple_pic/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/simple_pic/CVS/Template b/usrp2/opencores/simple_pic/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/simple_pic/rtl/CVS/Entries b/usrp2/opencores/simple_pic/rtl/CVS/Entries new file mode 100644 index 000000000..e5e641097 --- /dev/null +++ b/usrp2/opencores/simple_pic/rtl/CVS/Entries @@ -0,0 +1,2 @@ +/simple_pic.v/1.3/Tue Dec 24 10:26:51 2002// +D diff --git a/usrp2/opencores/simple_pic/rtl/CVS/Repository b/usrp2/opencores/simple_pic/rtl/CVS/Repository new file mode 100644 index 000000000..2639a29e2 --- /dev/null +++ b/usrp2/opencores/simple_pic/rtl/CVS/Repository @@ -0,0 +1 @@ +simple_pic/rtl diff --git a/usrp2/opencores/simple_pic/rtl/CVS/Root b/usrp2/opencores/simple_pic/rtl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/simple_pic/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/simple_pic/rtl/CVS/Template b/usrp2/opencores/simple_pic/rtl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/simple_pic/rtl/simple_pic.v b/usrp2/opencores/simple_pic/rtl/simple_pic.v new file mode 100644 index 000000000..28184cbe2 --- /dev/null +++ b/usrp2/opencores/simple_pic/rtl/simple_pic.v @@ -0,0 +1,228 @@ + +// Modified by M. Ettus, 2008 for 32 bit width + +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple Programmable Interrupt Controller //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +// +// This is a simple Programmable Interrupt Controller. +// The number of interrupts is depending on the databus size. +// There's one interrupt input per databit (i.e. 16 interrupts for a 16 +// bit databus). +// All attached devices share the same CPU priority level. +// +// +// +// Registers: +// +// 0x00: EdgeEnable Register +// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source +// '0' = level triggered interrupt source +// 0x01: PolarityRegister +// bits 7:0 R/W Polarity '1' = high level / rising edge +// '0' = low level / falling edge +// 0x02: MaskRegister +// bits 7:0 R/W Mask '1' = interrupt masked (disabled) +// '0' = interrupt not masked (enabled) +// 0x03: PendingRegister +// bits 7:0 R/W Pending '1' = interrupt pending +// '0' = no interrupt pending +// +// A CPU interrupt is generated when an interrupt is pending and its +// MASK bit is cleared. +// +// +// +// HOWTO: +// +// Clearing pending interrupts: +// Writing a '1' to a bit in the interrupt pending register clears the +// interrupt. Make sure to clear the interrupt at the source before +// writing to the interrupt pending register. Otherwise the interrupt +// will be set again. +// +// Priority based interrupts: +// Upon reception of an interrupt, check the interrupt register and +// determine the highest priority interrupt. Mask all interrupts from the +// current level to the lowest level. This negates the interrupt line, and +// makes sure only interrupts with a higher level are triggered. After +// completion of the interrupt service routine, clear the interrupt source, +// the interrupt bit in the pending register, and restore the MASK register +// to it's previous state. +// +// Addapt the core for fewer interrupt sources: +// If less than 8 interrupt sources are required, than the 'is' parameter +// can be set to the amount of required interrupts. Interrupts are mapped +// starting at the LSBs. So only the 'is' LSBs per register are valid. All +// other bits (i.e. the 8-'is' MSBs) are set to zero '0'. +// Codesize is approximately linear to the amount of interrupts. I.e. using +// 4 instead of 8 interrupt sources reduces the size by approx. half. +// + + +module simple_pic( + clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o, + irq +); + parameter is = 8; // Number of interrupt sources + parameter dwidth = 32; + // + // Inputs & outputs + // + + // 8bit WISHBONE bus slave interface + input clk_i; // clock + input rst_i; // reset (asynchronous active low) + input cyc_i; // cycle + input stb_i; // strobe (cycle and strobe are the same signal) + input [ 2:1] adr_i; // address + input we_i; // write enable + input [ dwidth-1:0] dat_i; // data output + output [ dwidth-1:0] dat_o; // data input + output ack_o; // normal bus termination + + output int_o; // interrupt output + + // + // Interrupt sources + // + input [is:1] irq; // interrupt request inputs + + + // + // Module body + // + reg [is:1] pol, edgen, pending, mask; // register bank + reg [is:1] lirq, dirq; // latched irqs, delayed latched irqs + + + // + // perform parameter checks + // + // synopsys translate_off + initial + begin + if(is > dwidth) + $display("simple_pic: max number of interrupts = data bus width."); + end + // synopsys translate_on + + // + // latch interrupt inputs + always @(posedge clk_i) + lirq <= #1 irq; + + // + // generate delayed latched irqs + always @(posedge clk_i) + dirq <= #1 lirq; + + + // + // generate actual triggers + function trigger; + input edgen, pol, lirq, dirq; + + reg edge_irq, level_irq; + begin + edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq); + level_irq = pol ? lirq : ~lirq; + + trigger = edgen ? edge_irq : level_irq; + end + endfunction + + reg [is:1] irq_event; + integer n; + always @(posedge clk_i) + for(n=1; n<=is; n=n+1) + irq_event[n] <= #1 trigger(edgen[n], pol[n], lirq[n], dirq[n]); + + // + // generate wishbone register bank writes + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i) + if (rst_i) + begin + pol <= #1 {is{1'b0}}; // clear polarity register + edgen <= #1 {is{1'b0}}; // clear edge enable register + mask <= #1 {is{1'b1}}; // mask all interrupts + end + else if(wb_wr) // wishbone write cycle?? + case (adr_i) // synopsys full_case parallel_case + 2'b00: edgen <= #1 dat_i[is-1:0]; // EDGE-ENABLE register + 2'b01: pol <= #1 dat_i[is-1:0]; // POLARITY register + 2'b10: mask <= #1 dat_i[is-1:0]; // MASK register + 2'b11: ; // PENDING register is a special case (see below) + endcase + + + // pending register is a special case + always @(posedge clk_i) + if (rst_i) + pending <= #1 {is{1'b0}}; // clear all pending interrupts + else if ( wb_wr & (&adr_i) ) + pending <= #1 (pending & ~dat_i[is-1:0]) | irq_event; + else + pending <= #1 pending | irq_event; + + // + // generate dat_o + reg [dwidth-1:0] dat_o; + always @(posedge clk_i) + case (adr_i) // synopsys full_case parallel_case + 2'b00: dat_o <= #1 { {(dwidth-is){1'b0}}, edgen}; + 2'b01: dat_o <= #1 { {(dwidth-is){1'b0}}, pol}; + 2'b10: dat_o <= #1 { {(dwidth-is){1'b0}}, mask}; + 2'b11: dat_o <= #1 { {(dwidth-is){1'b0}}, pending}; + endcase + + // + // generate ack_o + reg ack_o; + always @(posedge clk_i) + ack_o <= #1 wb_acc & !ack_o; + + // + // generate CPU interrupt signal + reg int_o; + always @(posedge clk_i) + if(rst_i) + int_o <= #1 0; + else + int_o <= #1 |(pending & ~mask); + +endmodule + diff --git a/usrp2/opencores/spi/CVS/Entries b/usrp2/opencores/spi/CVS/Entries new file mode 100644 index 000000000..62011c465 --- /dev/null +++ b/usrp2/opencores/spi/CVS/Entries @@ -0,0 +1,4 @@ +D/bench//// +D/doc//// +D/rtl//// +D/sim//// diff --git a/usrp2/opencores/spi/CVS/Repository b/usrp2/opencores/spi/CVS/Repository new file mode 100644 index 000000000..c928c4b77 --- /dev/null +++ b/usrp2/opencores/spi/CVS/Repository @@ -0,0 +1 @@ +spi diff --git a/usrp2/opencores/spi/CVS/Root b/usrp2/opencores/spi/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/CVS/Template b/usrp2/opencores/spi/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/bench/CVS/Entries b/usrp2/opencores/spi/bench/CVS/Entries new file mode 100644 index 000000000..428c5622d --- /dev/null +++ b/usrp2/opencores/spi/bench/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/opencores/spi/bench/CVS/Repository b/usrp2/opencores/spi/bench/CVS/Repository new file mode 100644 index 000000000..f45728d0f --- /dev/null +++ b/usrp2/opencores/spi/bench/CVS/Repository @@ -0,0 +1 @@ +spi/bench diff --git a/usrp2/opencores/spi/bench/CVS/Root b/usrp2/opencores/spi/bench/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/bench/CVS/Template b/usrp2/opencores/spi/bench/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Entries b/usrp2/opencores/spi/bench/verilog/CVS/Entries new file mode 100644 index 000000000..68404f871 --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/CVS/Entries @@ -0,0 +1,4 @@ +/spi_slave_model.v/1.2/Wed Mar 26 16:00:03 2003// +/tb_spi_top.v/1.6/Mon Mar 15 17:46:04 2004// +/wb_master_model.v/1.1.1.1/Wed Jun 12 15:45:23 2002// +D diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Repository b/usrp2/opencores/spi/bench/verilog/CVS/Repository new file mode 100644 index 000000000..78a3c4a9f --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +spi/bench/verilog diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Root b/usrp2/opencores/spi/bench/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Template b/usrp2/opencores/spi/bench/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/bench/verilog/spi_slave_model.v b/usrp2/opencores/spi/bench/verilog/spi_slave_model.v new file mode 100644 index 000000000..dfdaed929 --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/spi_slave_model.v @@ -0,0 +1,73 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_slave_model.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module spi_slave_model (rst, ss, sclk, mosi, miso); + + input rst; // reset + input ss; // slave select + input sclk; // serial clock + input mosi; // master out slave in + output miso; // master in slave out + + reg miso; + + reg rx_negedge; // slave receiving on negedge + reg tx_negedge; // slave transmiting on negedge + reg [31:0] data; // data register + + parameter Tp = 1; + + always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst) + begin + if (rst) + data <= #Tp 32'b0; + else if (!ss) + data <= #Tp {data[30:0], mosi}; + end + + always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge)) + begin + miso <= #Tp data[31]; + end + +endmodule + diff --git a/usrp2/opencores/spi/bench/verilog/tb_spi_top.v b/usrp2/opencores/spi/bench/verilog/tb_spi_top.v new file mode 100644 index 000000000..529c0aca1 --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/tb_spi_top.v @@ -0,0 +1,339 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// tb_spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// Based on: //// +//// - i2c/bench/verilog/tst_bench_top.v //// +//// Copyright (C) 2001 Richard Herveille //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module tb_spi_top(); + + reg clk; + reg rst; + wire [31:0] adr; + wire [31:0] dat_i, dat_o; + wire we; + wire [3:0] sel; + wire stb; + wire cyc; + wire ack; + wire err; + wire int; + + wire [7:0] ss; + wire sclk; + wire mosi; + wire miso; + + reg [31:0] q; + reg [31:0] q1; + reg [31:0] q2; + reg [31:0] q3; + reg [31:0] result; + + parameter SPI_RX_0 = 5'h0; + parameter SPI_RX_1 = 5'h4; + parameter SPI_RX_2 = 5'h8; + parameter SPI_RX_3 = 5'hc; + parameter SPI_TX_0 = 5'h0; + parameter SPI_TX_1 = 5'h4; + parameter SPI_TX_2 = 5'h8; + parameter SPI_TX_3 = 5'hc; + parameter SPI_CTRL = 5'h10; + parameter SPI_DIVIDE = 5'h14; + parameter SPI_SS = 5'h18; + + // Generate clock + always #5 clk = ~clk; + + // Wishbone master model + wb_master_model #(32, 32) i_wb_master ( + .clk(clk), .rst(rst), + .adr(adr), .din(dat_i), .dout(dat_o), + .cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0) + ); + + // SPI master core + spi_top i_spi_top ( + .wb_clk_i(clk), .wb_rst_i(rst), + .wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i), + .wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb), + .wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int), + .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) + ); + + // SPI slave model + spi_slave_model i_spi_slave ( + .rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso) + ); + + initial + begin + $display("\nstatus: %t Testbench started\n\n", $time); + + $dumpfile("bench.vcd"); + $dumpvars(1, tb_spi_top); + $dumpvars(1, tb_spi_top.i_spi_slave); + + // Initial values + clk = 0; + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b0; + + result = 32'h0; + + // Reset system + rst = 1'b0; // negate reset + #2; + rst = 1'b1; // assert reset + repeat(20) @(posedge clk); + rst = 1'b0; // negate reset + + $display("status: %t done reset", $time); + + @(posedge clk); + + // Program core + i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register + i_wb_master.wb_write(0, SPI_TX_0, 32'h5a); // set tx register to 0x5a + i_wb_master.wb_write(0, SPI_CTRL, 32'h208); // set 8 bit transfer + i_wb_master.wb_write(0, SPI_SS, 32'h01); // set ss 0 + + $display("status: %t programmed registers", $time); + + i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00); // verify devider register + i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a); // verify tx register + i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208); // verify tx register + i_wb_master.wb_cmp(0, SPI_SS, 32'h01); // verify ss register + + $display("status: %t verified registers", $time); + + i_spi_slave.rx_negedge = 1'b1; + i_spi_slave.tx_negedge = 1'b0; + i_spi_slave.data[31:0] = 32'ha5967e5a; + i_wb_master.wb_write(0, SPI_CTRL, 32'h308); // set 8 bit transfer, start transfer + + $display("status: %t generate transfer: 8 bit, msb first, tx posedge, rx negedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b1; + i_wb_master.wb_write(0, SPI_TX_0, 32'ha5); + i_wb_master.wb_write(0, SPI_CTRL, 32'h408); // set 8 bit transfer, tx negedge + i_wb_master.wb_write(0, SPI_CTRL, 32'h508); // set 8 bit transfer, tx negedge, start transfer + + $display("status: %t generate transfer: 8 bit, msb first, tx negedge, rx posedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b1; + i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5); + i_wb_master.wb_write(0, SPI_CTRL, 32'hc10); // set 16 bit transfer, tx negedge, lsb + i_wb_master.wb_write(0, SPI_CTRL, 32'hd10); // set 16 bit transfer, tx negedge, start transfer + + $display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b1; + i_spi_slave.tx_negedge = 1'b0; + i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210); + i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98); + i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40); // set 64 bit transfer, rx negedge, lsb + i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40); // set 64 bit transfer, rx negedge, start transfer + + $display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + i_wb_master.wb_read(1, SPI_RX_1, q1); + result = result + q1; + + if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b1; + i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff); + i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb); + i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677); + i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233); + i_wb_master.wb_write(0, SPI_CTRL, 32'h400); + i_wb_master.wb_write(0, SPI_CTRL, 32'h500); + + $display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + i_wb_master.wb_read(1, SPI_RX_1, q1); + result = result + q1; + i_wb_master.wb_read(1, SPI_RX_2, q2); + result = result + q2; + i_wb_master.wb_read(1, SPI_RX_3, q3); + result = result + q3; + + if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b1; + i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5); + i_wb_master.wb_write(0, SPI_CTRL, 32'h1420); + i_wb_master.wb_write(0, SPI_CTRL, 32'h1520); + + $display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time); + + // Check interrupt signal + while (!int) + @(posedge clk); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + @(posedge clk); + if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b1; + i_spi_slave.tx_negedge = 1'b0; + i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421); + i_wb_master.wb_write(0, SPI_CTRL, 32'h3220); + i_wb_master.wb_write(0, SPI_CTRL, 32'h3320); + + $display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time); + + while (!int) + @(posedge clk); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + @(posedge clk); + if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b1; + i_spi_slave.tx_negedge = 1'b0; + i_wb_master.wb_write(0, SPI_TX_0, 32'h1); + i_wb_master.wb_write(0, SPI_CTRL, 32'h3201); + i_wb_master.wb_write(0, SPI_CTRL, 32'h3301); + + $display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time); + + while (!int) + @(posedge clk); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + @(posedge clk); + if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + $display("\n\nstatus: %t Testbench done", $time); + + #25000; // wait 25us + + $display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead); + $display("exit (%h)", result ^ 32'h2e8b36ab); + + $stop; + end + +endmodule + + diff --git a/usrp2/opencores/spi/bench/verilog/wb_master_model.v b/usrp2/opencores/spi/bench/verilog/wb_master_model.v new file mode 100644 index 000000000..3f8b7ee6a --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/wb_master_model.v @@ -0,0 +1,176 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_master_model.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// Based on: //// +//// - i2c/bench/verilog/wb_master_model.v //// +//// Copyright (C) 2001 Richard Herveille //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); + + parameter dwidth = 32; + parameter awidth = 32; + + input clk, rst; + output [awidth -1:0] adr; + input [dwidth -1:0] din; + output [dwidth -1:0] dout; + output cyc, stb; + output we; + output [dwidth/8 -1:0] sel; + input ack, err, rty; + + // Internal signals + reg [awidth -1:0] adr; + reg [dwidth -1:0] dout; + reg cyc, stb; + reg we; + reg [dwidth/8 -1:0] sel; + + reg [dwidth -1:0] q; + + // Memory Logic + initial + begin + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + cyc = 1'b0; + stb = 1'bx; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + #1; + end + + // Wishbone write cycle + task wb_write; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signal + #1; + adr = a; + dout = d; + cyc = 1'b1; + stb = 1'b1; + we = 1'b1; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + + end + endtask + + // Wishbone read cycle + task wb_read; + input delay; + integer delay; + + input [awidth -1:0] a; + output [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signals + #1; + adr = a; + dout = {dwidth{1'bx}}; + cyc = 1'b1; + stb = 1'b1; + we = 1'b0; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + d = din; + + end + endtask + + // Wishbone compare cycle (read data from location and compare with expected data) + task wb_cmp; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d_exp; + + begin + wb_read (delay, a, q); + + if (d_exp !== q) + $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); + end + endtask + +endmodule + diff --git a/usrp2/opencores/spi/doc/CVS/Entries b/usrp2/opencores/spi/doc/CVS/Entries new file mode 100644 index 000000000..ff33fa590 --- /dev/null +++ b/usrp2/opencores/spi/doc/CVS/Entries @@ -0,0 +1,2 @@ +/spi.pdf/1.5/Mon Mar 15 17:46:05 2004/-kb/ +D/src//// diff --git a/usrp2/opencores/spi/doc/CVS/Repository b/usrp2/opencores/spi/doc/CVS/Repository new file mode 100644 index 000000000..772adcef5 --- /dev/null +++ b/usrp2/opencores/spi/doc/CVS/Repository @@ -0,0 +1 @@ +spi/doc diff --git a/usrp2/opencores/spi/doc/CVS/Root b/usrp2/opencores/spi/doc/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/doc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/doc/CVS/Template b/usrp2/opencores/spi/doc/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/doc/spi.pdf b/usrp2/opencores/spi/doc/spi.pdf new file mode 100644 index 000000000..d88ee2807 Binary files /dev/null and b/usrp2/opencores/spi/doc/spi.pdf differ diff --git a/usrp2/opencores/spi/doc/src/CVS/Entries b/usrp2/opencores/spi/doc/src/CVS/Entries new file mode 100644 index 000000000..adcbf083d --- /dev/null +++ b/usrp2/opencores/spi/doc/src/CVS/Entries @@ -0,0 +1,2 @@ +/spi.doc/1.7/Mon Mar 15 17:46:06 2004/-kb/ +D diff --git a/usrp2/opencores/spi/doc/src/CVS/Repository b/usrp2/opencores/spi/doc/src/CVS/Repository new file mode 100644 index 000000000..09b1f4a98 --- /dev/null +++ b/usrp2/opencores/spi/doc/src/CVS/Repository @@ -0,0 +1 @@ +spi/doc/src diff --git a/usrp2/opencores/spi/doc/src/CVS/Root b/usrp2/opencores/spi/doc/src/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/doc/src/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/doc/src/CVS/Template b/usrp2/opencores/spi/doc/src/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/doc/src/spi.doc b/usrp2/opencores/spi/doc/src/spi.doc new file mode 100755 index 000000000..b04700177 Binary files /dev/null and b/usrp2/opencores/spi/doc/src/spi.doc differ diff --git a/usrp2/opencores/spi/rtl/CVS/Entries b/usrp2/opencores/spi/rtl/CVS/Entries new file mode 100644 index 000000000..428c5622d --- /dev/null +++ b/usrp2/opencores/spi/rtl/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/opencores/spi/rtl/CVS/Repository b/usrp2/opencores/spi/rtl/CVS/Repository new file mode 100644 index 000000000..5fd79b19b --- /dev/null +++ b/usrp2/opencores/spi/rtl/CVS/Repository @@ -0,0 +1 @@ +spi/rtl diff --git a/usrp2/opencores/spi/rtl/CVS/Root b/usrp2/opencores/spi/rtl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/rtl/CVS/Template b/usrp2/opencores/spi/rtl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Entries b/usrp2/opencores/spi/rtl/verilog/CVS/Entries new file mode 100644 index 000000000..d125a1657 --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/CVS/Entries @@ -0,0 +1,6 @@ +/spi_clgen.v/1.3/Thu Jul 3 17:32:15 2003// +/spi_defines.v/1.8/Mon Mar 15 17:46:08 2004// +/spi_shift.v/1.7/Tue Jul 8 15:36:37 2003// +/spi_top.v/1.8/Tue Jul 8 15:36:37 2003// +/timescale.v/1.1.1.1/Wed Jun 12 15:45:23 2002// +D diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Repository b/usrp2/opencores/spi/rtl/verilog/CVS/Repository new file mode 100644 index 000000000..361b93bf8 --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/CVS/Repository @@ -0,0 +1 @@ +spi/rtl/verilog diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Root b/usrp2/opencores/spi/rtl/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Template b/usrp2/opencores/spi/rtl/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v new file mode 100644 index 000000000..7bc4f6e5e --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_clgen.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); + + parameter Tp = 1; + + input clk_in; // input clock (system clock) + input rst; // reset + input enable; // clock enable + input go; // start transfer + input last_clk; // last clock + input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value) + output clk_out; // output clock + output pos_edge; // pulse marking positive edge of clk_out + output neg_edge; // pulse marking negative edge of clk_out + + reg clk_out; + reg pos_edge; + reg neg_edge; + + reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter + wire cnt_zero; // conter is equal to zero + wire cnt_one; // conter is equal to one + + + assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}}; + assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; + + // Counter counts half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}}; + else + begin + if(!enable || cnt_zero) + cnt <= #Tp divider; + else + cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; + end + end + + // clk_out is asserted every other half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + clk_out <= #Tp 1'b0; + else + clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + end + + // Pos and neg edge signals + always @(posedge clk_in or posedge rst) + begin + if(rst) + begin + pos_edge <= #Tp 1'b0; + neg_edge <= #Tp 1'b0; + end + else + begin + pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + end + end +endmodule + diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v new file mode 100644 index 000000000..a6925918e --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -0,0 +1,159 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_define.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// +// Number of bits used for devider register. If used in system with +// low frequency of system clock this can be reduced. +// Use SPI_DIVIDER_LEN for fine tuning theexact number. +// +//`define SPI_DIVIDER_LEN_8 +`define SPI_DIVIDER_LEN_16 +//`define SPI_DIVIDER_LEN_24 +//`define SPI_DIVIDER_LEN_32 + +`ifdef SPI_DIVIDER_LEN_8 + `define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8 +`endif +`ifdef SPI_DIVIDER_LEN_16 + `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 +`endif +`ifdef SPI_DIVIDER_LEN_24 + `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 +`endif +`ifdef SPI_DIVIDER_LEN_32 + `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 +`endif + +// +// Maximum nuber of bits that can be send/received at once. +// Use SPI_MAX_CHAR for fine tuning the exact number, when using +// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. +// +`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_64 +//`define SPI_MAX_CHAR_32 +//`define SPI_MAX_CHAR_24 +//`define SPI_MAX_CHAR_16 +//`define SPI_MAX_CHAR_8 + +`ifdef SPI_MAX_CHAR_128 + `define SPI_MAX_CHAR 128 // Can only be set to 128 + `define SPI_CHAR_LEN_BITS 7 +`endif +`ifdef SPI_MAX_CHAR_64 + `define SPI_MAX_CHAR 64 // Can only be set to 64 + `define SPI_CHAR_LEN_BITS 6 +`endif +`ifdef SPI_MAX_CHAR_32 + `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 + `define SPI_CHAR_LEN_BITS 5 +`endif +`ifdef SPI_MAX_CHAR_24 + `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 + `define SPI_CHAR_LEN_BITS 5 +`endif +`ifdef SPI_MAX_CHAR_16 + `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 + `define SPI_CHAR_LEN_BITS 4 +`endif +`ifdef SPI_MAX_CHAR_8 + `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 + `define SPI_CHAR_LEN_BITS 3 +`endif + +// +// Number of device select signals. Use SPI_SS_NB for fine tuning the +// exact number. +// +`define SPI_SS_NB_8 +//`define SPI_SS_NB_16 +//`define SPI_SS_NB_24 +//`define SPI_SS_NB_32 + +`ifdef SPI_SS_NB_8 + `define SPI_SS_NB 8 // Can be set from 1 to 8 +`endif +`ifdef SPI_SS_NB_16 + `define SPI_SS_NB 16 // Can be set from 9 to 16 +`endif +`ifdef SPI_SS_NB_24 + `define SPI_SS_NB 24 // Can be set from 17 to 24 +`endif +`ifdef SPI_SS_NB_32 + `define SPI_SS_NB 32 // Can be set from 25 to 32 +`endif + +// +// Bits of WISHBONE address used for partial decoding of SPI registers. +// +`define SPI_OFS_BITS 4:2 + +// +// Register offset +// +`define SPI_RX_0 0 +`define SPI_RX_1 1 +`define SPI_RX_2 2 +`define SPI_RX_3 3 +`define SPI_TX_0 0 +`define SPI_TX_1 1 +`define SPI_TX_2 2 +`define SPI_TX_3 3 +`define SPI_CTRL 4 +`define SPI_DEVIDE 5 +`define SPI_SS 6 + +// +// Number of bits in ctrl register +// +`define SPI_CTRL_BIT_NB 14 + +// +// Control register bit position +// +`define SPI_CTRL_ASS 13 +`define SPI_CTRL_IE 12 +`define SPI_CTRL_LSB 11 +`define SPI_CTRL_TX_NEGEDGE 10 +`define SPI_CTRL_RX_NEGEDGE 9 +`define SPI_CTRL_GO 8 +`define SPI_CTRL_RES_1 7 +`define SPI_CTRL_CHAR_LEN 6:0 + diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v new file mode 100644 index 000000000..b17ac8b1f --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v @@ -0,0 +1,238 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_shift.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, + pos_edge, neg_edge, rx_negedge, tx_negedge, + tip, last, + p_in, p_out, s_clk, s_in, s_out); + + parameter Tp = 1; + + input clk; // system clock + input rst; // reset + input [3:0] latch; // latch signal for storing the data in shift register + input [3:0] byte_sel; // byte select signals for storing the data in shift register + input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one) + input lsb; // lbs first on the line + input go; // start stansfer + input pos_edge; // recognize posedge of sclk + input neg_edge; // recognize negedge of sclk + input rx_negedge; // s_in is sampled on negative edge + input tx_negedge; // s_out is driven on negative edge + output tip; // transfer in progress + output last; // last bit + input [31:0] p_in; // parallel in + output [`SPI_MAX_CHAR-1:0] p_out; // parallel out + input s_clk; // serial clock + input s_in; // serial in + output s_out; // serial out + + reg s_out; + reg tip; + + reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count + reg [`SPI_MAX_CHAR-1:0] data; // shift register + wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position + wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position + wire rx_clk; // rx clock enable + wire tx_clk; // tx clock enable + + assign p_out = data; + + assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}; + assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : + (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}); + + assign last = !(|cnt); + + assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk); + assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; + + // Character bit counter + always @(posedge clk or posedge rst) + begin + if(rst) + cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + else + begin + if(tip) + cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + else + cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + end + end + + // Transfer in progress + always @(posedge clk or posedge rst) + begin + if(rst) + tip <= #Tp 1'b0; + else if(go && ~tip) + tip <= #Tp 1'b1; + else if(tip && last && pos_edge) + tip <= #Tp 1'b0; + end + + // Sending bits to the line + always @(posedge clk or posedge rst) + begin + if (rst) + s_out <= #Tp 1'b0; + else + s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + end + + // Receiving bits from the line + always @(posedge clk or posedge rst) + begin + if (rst) + data <= #Tp {`SPI_MAX_CHAR{1'b0}}; +`ifdef SPI_MAX_CHAR_128 + else if (latch[0] && !tip) + begin + if (byte_sel[3]) + data[31:24] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + end + else if (latch[1] && !tip) + begin + if (byte_sel[3]) + data[63:56] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[55:48] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[47:40] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[39:32] <= #Tp p_in[7:0]; + end + else if (latch[2] && !tip) + begin + if (byte_sel[3]) + data[95:88] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[87:80] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[79:72] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[71:64] <= #Tp p_in[7:0]; + end + else if (latch[3] && !tip) + begin + if (byte_sel[3]) + data[127:120] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[119:112] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[111:104] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[103:96] <= #Tp p_in[7:0]; + end +`else +`ifdef SPI_MAX_CHAR_64 + else if (latch[0] && !tip) + begin + if (byte_sel[3]) + data[31:24] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + end + else if (latch[1] && !tip) + begin + if (byte_sel[3]) + data[63:56] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[55:48] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[47:40] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[39:32] <= #Tp p_in[7:0]; + end +`else + else if (latch[0] && !tip) + begin + `ifdef SPI_MAX_CHAR_8 + if (byte_sel[0]) + data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0]; + `endif + `ifdef SPI_MAX_CHAR_16 + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8]; + `endif + `ifdef SPI_MAX_CHAR_24 + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[2]) + data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16]; + `endif + `ifdef SPI_MAX_CHAR_32 + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[3]) + data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24]; + `endif + end +`endif +`endif + else + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + end + +endmodule + diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v new file mode 100644 index 000000000..09b2e50e1 --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v @@ -0,0 +1,287 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" +`include "timescale.v" + +module spi_top +( + // Wishbone signals + wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, + + // SPI signals + ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i +); + + parameter Tp = 1; + + // Wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input [4:0] wb_adr_i; // lower address bits + input [32-1:0] wb_dat_i; // databus input + output [32-1:0] wb_dat_o; // databus output + input [3:0] wb_sel_i; // byte select inputs + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + output wb_err_o; // termination w/ error + output wb_int_o; // interrupt request signal output + + // SPI signals + output [`SPI_SS_NB-1:0] ss_pad_o; // slave select + output sclk_pad_o; // serial clock + output mosi_pad_o; // master out slave in + input miso_pad_i; // master in slave out + + reg [32-1:0] wb_dat_o; + reg wb_ack_o; + reg wb_int_o; + + // Internal signals + reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register + reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [`SPI_SS_NB-1:0] ss; // Slave select register + reg [32-1:0] wb_dat; // wb data out + wire [`SPI_MAX_CHAR-1:0] rx; // Rx register + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len + wire go; // go + wire lsb; // lsb first on line + wire ie; // interrupt enable + wire ass; // automatic slave select + wire spi_divider_sel; // divider register select + wire spi_ctrl_sel; // ctrl register select + wire [3:0] spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + // Address decoder + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE); + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); + assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); + assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); + assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_2); + assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_3); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); + + // Read from registers + always @(wb_adr_i or rx or ctrl or divider or ss) + begin + case (wb_adr_i[`SPI_OFS_BITS]) +`ifdef SPI_MAX_CHAR_128 + `SPI_RX_0: wb_dat = rx[31:0]; + `SPI_RX_1: wb_dat = rx[63:32]; + `SPI_RX_2: wb_dat = rx[95:64]; + `SPI_RX_3: wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]}; +`else +`ifdef SPI_MAX_CHAR_64 + `SPI_RX_0: wb_dat = rx[31:0]; + `SPI_RX_1: wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]}; + `SPI_RX_2: wb_dat = 32'b0; + `SPI_RX_3: wb_dat = 32'b0; +`else + `SPI_RX_0: wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]}; + `SPI_RX_1: wb_dat = 32'b0; + `SPI_RX_2: wb_dat = 32'b0; + `SPI_RX_3: wb_dat = 32'b0; +`endif +`endif + `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; + `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; + `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; + default: wb_dat = 32'bx; + endcase + end + + // Wb data out + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_dat_o <= #Tp 32'b0; + else + wb_dat_o <= #Tp wb_dat; + end + + // Wb acknowledge + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_ack_o <= #Tp 1'b0; + else + wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + end + + // Wb error + assign wb_err_o = 1'b0; + + // Interrupt + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_int_o <= #Tp 1'b0; + else if (ie && tip && last_bit && pos_edge) + wb_int_o <= #Tp 1'b1; + else if (wb_ack_o) + wb_int_o <= #Tp 1'b0; + end + + // Divider register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}}; + else if (spi_divider_sel && wb_we_i && !tip) + begin + `ifdef SPI_DIVIDER_LEN_8 + if (wb_sel_i[0]) + divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0]; + `endif + `ifdef SPI_DIVIDER_LEN_16 + if (wb_sel_i[0]) + divider[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8]; + `endif + `ifdef SPI_DIVIDER_LEN_24 + if (wb_sel_i[0]) + divider[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + divider[15:8] <= #Tp wb_dat_i[15:8]; + if (wb_sel_i[2]) + divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16]; + `endif + `ifdef SPI_DIVIDER_LEN_32 + if (wb_sel_i[0]) + divider[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + divider[15:8] <= #Tp wb_dat_i[15:8]; + if (wb_sel_i[2]) + divider[23:16] <= #Tp wb_dat_i[23:16]; + if (wb_sel_i[3]) + divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24]; + `endif + end + end + + // Ctrl register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}}; + else if(spi_ctrl_sel && wb_we_i && !tip) + begin + if (wb_sel_i[0]) + ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; + if (wb_sel_i[1]) + ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + end + else if(tip && last_bit && pos_edge) + ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; + end + + assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; + assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; + assign go = ctrl[`SPI_CTRL_GO]; + assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; + assign lsb = ctrl[`SPI_CTRL_LSB]; + assign ie = ctrl[`SPI_CTRL_IE]; + assign ass = ctrl[`SPI_CTRL_ASS]; + + // Slave select register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + ss <= #Tp {`SPI_SS_NB{1'b0}}; + else if(spi_ss_sel && wb_we_i && !tip) + begin + `ifdef SPI_SS_NB_8 + if (wb_sel_i[0]) + ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + `endif + `ifdef SPI_SS_NB_16 + if (wb_sel_i[0]) + ss[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8]; + `endif + `ifdef SPI_SS_NB_24 + if (wb_sel_i[0]) + ss[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[15:8] <= #Tp wb_dat_i[15:8]; + if (wb_sel_i[2]) + ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16]; + `endif + `ifdef SPI_SS_NB_32 + if (wb_sel_i[0]) + ss[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[15:8] <= #Tp wb_dat_i[15:8]; + if (wb_sel_i[2]) + ss[23:16] <= #Tp wb_dat_i[23:16]; + if (wb_sel_i[3]) + ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24]; + `endif + end + end + + assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); + + spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), + .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), + .neg_edge(neg_edge)); + + spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb), + .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), + .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), + .tip(tip), .last(last_bit), + .p_in(wb_dat_i), .p_out(rx), + .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); +endmodule + diff --git a/usrp2/opencores/spi/rtl/verilog/timescale.v b/usrp2/opencores/spi/rtl/verilog/timescale.v new file mode 100644 index 000000000..60d4ecbd1 --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/timescale.v @@ -0,0 +1,2 @@ +`timescale 1ns / 10ps + diff --git a/usrp2/opencores/spi/sim/CVS/Entries b/usrp2/opencores/spi/sim/CVS/Entries new file mode 100644 index 000000000..545533337 --- /dev/null +++ b/usrp2/opencores/spi/sim/CVS/Entries @@ -0,0 +1,2 @@ +D/rtl_sim//// +D/run//// diff --git a/usrp2/opencores/spi/sim/CVS/Repository b/usrp2/opencores/spi/sim/CVS/Repository new file mode 100644 index 000000000..9ec769309 --- /dev/null +++ b/usrp2/opencores/spi/sim/CVS/Repository @@ -0,0 +1 @@ +spi/sim diff --git a/usrp2/opencores/spi/sim/CVS/Root b/usrp2/opencores/spi/sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/sim/CVS/Template b/usrp2/opencores/spi/sim/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries b/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries new file mode 100644 index 000000000..8ab9f73a7 --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries @@ -0,0 +1 @@ +D/run//// diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository b/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository new file mode 100644 index 000000000..c8c6a94c6 --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository @@ -0,0 +1 @@ +spi/sim/rtl_sim diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Root b/usrp2/opencores/spi/sim/rtl_sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/sim/rtl_sim/CVS/Template b/usrp2/opencores/spi/sim/rtl_sim/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries new file mode 100644 index 000000000..8947f64a0 --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries @@ -0,0 +1,4 @@ +/rtl.fl/1.1/Mon Mar 15 17:46:08 2004// +/run_sim/1.1/Mon Mar 15 17:46:08 2004// +/sim.fl/1.1/Mon Mar 15 17:46:08 2004// +D diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository new file mode 100644 index 000000000..5200bb196 --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository @@ -0,0 +1 @@ +spi/sim/rtl_sim/run diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl b/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl new file mode 100644 index 000000000..d84a0840d --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl @@ -0,0 +1,3 @@ +spi_top.v +spi_clgen.v +spi_shift.v diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/run_sim b/usrp2/opencores/spi/sim/rtl_sim/run/run_sim new file mode 100755 index 000000000..1b13a35b9 --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/run/run_sim @@ -0,0 +1,108 @@ +#!/bin/csh -f + +set current_par = 0 +set output_waveform = 0 +while ( $current_par < $# ) + @ current_par = $current_par + 1 + case wave: + @ output_waveform = 1 + breaksw + default: + echo 'Unknown option "'$argv[$current_par]'"!' + exit + breaksw + endsw +end + +echo "TEST: spi" + +#echo "-CDSLIB ./cds.lib" > ncvlog.args +#echo "-HDLVAR ./hdl.var" >> ncvlog.args +echo "-MESSAGES" > ncvlog.args +echo "-INCDIR ../../../bench/verilog" >> ncvlog.args +echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args +echo "-NOCOPYRIGHT" >> ncvlog.args +echo "-UPDATE" >> ncvlog.args +echo "-LOGFILE ncvlog.log" >> ncvlog.args + +foreach filename ( `cat ./rtl.fl` ) + echo "../../../rtl/verilog/"$filename >> ncvlog.args +end + +foreach filename ( `cat ./sim.fl` ) + echo "../../../bench/verilog/"$filename >> ncvlog.args +end + +ncvlog -f ncvlog.args +if ($status != 0) then + echo "STATUS: failed" + exit +endif + + +echo "-MESSAGES" > ncelab.args +echo "-NOCOPYRIGHT" >> ncelab.args +#echo "-CDSLIB ./cds.lib" >> ncelab.args +#echo "-HDLVAR ./hdl.var" >> ncelab.args +echo "-LOGFILE ncelab.log" >> ncelab.args +echo "-SNAPSHOT worklib.tb_spi_top:v" >> ncelab.args +echo "-NOTIMINGCHECKS" >> ncelab.args +echo "-ACCESS +RWC" >> ncelab.args +echo "tb_spi_top" >> ncelab.args + +ncelab -f ncelab.args +if ($status != 0) then + echo "STATUS: failed" + exit +endif + + +echo "-MESSAGES" > ncsim.args +echo "-NOCOPYRIGHT" >> ncsim.args +#echo "-CDSLIB ./cds.lib" >> ncsim.args +#echo "-HDLVAR ./hdl.var" >> ncsim.args +echo "-INPUT ncsim.tcl" >> ncsim.args +echo "-LOGFILE ncsim.log" >> ncsim.args +echo "worklib.tb_spi_top:v" >> ncsim.args + +if ( $output_waveform ) then + echo "database -open waves -shm -into ../out/wav" > ./ncsim.tcl + echo "probe -create -database waves -shm tb_spi_top -all -depth all" >> ./ncsim.tcl + echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl + echo "run" >> ./ncsim.tcl +else + echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl + echo "run" > ./ncsim.tcl +endif + +echo "exit" >> ncsim.tcl + +ncsim -LICQUEUE -f ./ncsim.args + +set exit_line_nb = `sed -n '/exit/=' < ./ncsim.log` + +set dead_line_nb = 0 + +if ( $exit_line_nb ) then + + @ dead_line_nb = $exit_line_nb - 1 + set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ./ncsim.log` + set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ./ncsim.log` + + if ( "$dead_line" == "report (deaddead)" ) then + if ( "$exit_line" == "exit (00000000)" ) then + echo "STATUS: passed" #|tee -a ./run_sim.log 2>&1 + else + echo "STATUS: failed" #|tee -a ./run_sim.log 2>&1 + endif + else + echo "STATUS: failed" + endif + +endif + +exit + + + + diff --git a/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl b/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl new file mode 100644 index 000000000..283aad1f8 --- /dev/null +++ b/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl @@ -0,0 +1,3 @@ +tb_spi_top.v +wb_master_model.v +spi_slave_model.v diff --git a/usrp2/opencores/spi/sim/run/CVS/Entries b/usrp2/opencores/spi/sim/run/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/usrp2/opencores/spi/sim/run/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/opencores/spi/sim/run/CVS/Repository b/usrp2/opencores/spi/sim/run/CVS/Repository new file mode 100644 index 000000000..e8646e70d --- /dev/null +++ b/usrp2/opencores/spi/sim/run/CVS/Repository @@ -0,0 +1 @@ +spi/sim/run diff --git a/usrp2/opencores/spi/sim/run/CVS/Root b/usrp2/opencores/spi/sim/run/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/sim/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/sim/run/CVS/Template b/usrp2/opencores/spi/sim/run/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/COMPILE_LIST b/usrp2/opencores/spi_boot/COMPILE_LIST new file mode 100644 index 000000000..fc8f7d418 --- /dev/null +++ b/usrp2/opencores/spi_boot/COMPILE_LIST @@ -0,0 +1,33 @@ + +Compile list for the spi_boot core +================================== +Version: $Date: 2005/04/14 21:26:22 $ + +bench/vhdl/tb.vhd +rtl/vhdl/spi_boot_pack-p.vhd +bench/vhdl/tb_pack-p.vhd +bench/vhdl/tb_elem.vhd +rtl/vhdl/chip-e.vhd +rtl/vhdl/chip-full-a.vhd +rtl/vhdl/spi_boot.vhd +rtl/vhdl/spi_counter.vhd +rtl/vhdl/spi_counter-c.vhd +rtl/vhdl/spi_boot-c.vhd +rtl/vhdl/chip-full-c.vhd +bench/vhdl/card.vhd +bench/vhdl/card-c.vhd +bench/vhdl/tb_elem-full-c.vhd +rtl/vhdl/chip-mmc-a.vhd +rtl/vhdl/chip-mmc-c.vhd +bench/vhdl/tb_elem-mmc-c.vhd +rtl/vhdl/chip-sd-a.vhd +rtl/vhdl/chip-sd-c.vhd +bench/vhdl/tb_elem-sd-c.vhd +rtl/vhdl/chip-minimal-a.vhd +rtl/vhdl/chip-minimal-c.vhd +bench/vhdl/tb_elem-minimal-c.vhd +bench/vhdl/tb-c.vhd +bench/vhdl/tb_rl.vhd +rtl/vhdl/sample/ram_loader.vhd +rtl/vhdl/sample/ram_loader-c.vhd +bench/vhdl/tb_rl-c.vhd diff --git a/usrp2/opencores/spi_boot/COPYING b/usrp2/opencores/spi_boot/COPYING new file mode 100644 index 000000000..60549be51 --- /dev/null +++ b/usrp2/opencores/spi_boot/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of 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You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) 19yy + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/usrp2/opencores/spi_boot/CVS/Entries b/usrp2/opencores/spi_boot/CVS/Entries new file mode 100644 index 000000000..d339433f3 --- /dev/null +++ b/usrp2/opencores/spi_boot/CVS/Entries @@ -0,0 +1,9 @@ +/COMPILE_LIST/1.2/Thu Apr 14 21:26:22 2005// +/COPYING/1.1/Tue Feb 8 20:14:49 2005// +/KNOWN_BUGS/1.1/Sun Feb 13 18:28:35 2005// +/README/1.12/Thu Apr 14 21:32:58 2005// +D/bench//// +D/doc//// +D/rtl//// +D/sim//// +D/sw//// diff --git a/usrp2/opencores/spi_boot/CVS/Repository b/usrp2/opencores/spi_boot/CVS/Repository new file mode 100644 index 000000000..6aa579d49 --- /dev/null +++ b/usrp2/opencores/spi_boot/CVS/Repository @@ -0,0 +1 @@ +spi_boot diff --git a/usrp2/opencores/spi_boot/CVS/Root b/usrp2/opencores/spi_boot/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/CVS/Template b/usrp2/opencores/spi_boot/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/KNOWN_BUGS b/usrp2/opencores/spi_boot/KNOWN_BUGS new file mode 100644 index 000000000..298e4ba2e --- /dev/null +++ b/usrp2/opencores/spi_boot/KNOWN_BUGS @@ -0,0 +1,4 @@ + +Known bugs of the spi_boot core +=============================== +Version: $Date: 2005/02/13 18:28:35 $ diff --git a/usrp2/opencores/spi_boot/README b/usrp2/opencores/spi_boot/README new file mode 100644 index 000000000..926b35bff --- /dev/null +++ b/usrp2/opencores/spi_boot/README @@ -0,0 +1,170 @@ + +README for the spi_boot core +============================ +Version: $Date: 2005/04/14 21:32:58 $ + + +Description +----------- + +The SD/MMC Bootloader is a CPLD design that manages configuration and +bootstrapping of FPGAs. It is able to retrieve the required data from +SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA +configuration process. SD cards as well as MMCs are operated in SPI mode which +is part of both standards thus eliminating the need for dedicated +implementations. The SD/MMC Bootloader fits both. Beyond configuration, this +core supports a bootstrapping strategy where multiple images are stored on one +single memory card. +For example consider a system completely based on SRAM. The bootloader +provides the initial configuration data from the first image to the FPGA. This +image contains a design which pulls the next image from the memory card and +transfers this data to SRAM. In the third step the final FPGA design is loaded +from the third image. +These images are clustered in sets which can be selected by external switches +for example. Several configuration sets can be stored on one memory card +allowing you to provide a number of applications which are downloaded quickly +to the FPGA. +The schematic (rev. B) shows how the core can be used with an FPGA board. I +use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300 +board. SV2 fits the "SERIAL MODE" connector on this board but you will have to +add a separate wire from R6 to attach INIT. Please check the proper use of the +pull-up resistors for your specific board. + + +Features +-------- + +* Configuration mode: configures SRAM based FPGAs via slave serial mode + (Xilinx and Altera) +* Data mode: provides stored data over a simple synchronous serial interface +* Broad compatability using SPI mode + + SecureDigital cards using dedicated initialization command + + MultiMediaCards (see below) +* Operation triggerd by power-up or card insertion +* Multiple configuration sets stored on on single memory card + + +Compatability +------------- + +These cards have been tested with the SD/MMC Bootloader: + + * Hama 64 MB SD + * SanDisk 128 MB SD + * SanDisk 64 MB MMC + * Panasonic 32 MB SD + +Some MMC might fail with this core as not all cards support CMD18 +(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific +model. In case your MMC does not implement CMD18 you might want to have a look +at the FPGA MMC-Card Config project. + + +Tools +----- + +Downloading the configuration data to the card is a straight forward +process. The images have to be written starting at dedicated locations. For +the provided toplevel designs, these locations are multiples of 256 K. I.e. 0, +0x40000, 0x80000 and so forth. + +dd (part of the GNU coreutils) serves this purpose: +$ dd if=ram_loader.bin of=/dev/sdX bs=512 +$ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512 +$ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024 + +The name of the device node depends on how the card reader is attached to the +kernel. For Linux systems this is most often something like /dev/sdX with X +ranging from a-z. Please note that it is essential to use the device without +any trailing numbers as they refer to partitions leading to wrong offsets for +data written to the card. +All this works perfectly for my Spartan IIe device as this FPGA expects the +configuration data as it is delivered from the card: Consecutive bytes each +with its most significant bit first. Altera devices like the FLEX family are +different here. They expect the bytes with least significant bit +first. Therefore, the configuration data has to be swapped bitwise before it +is written to the card. + + +Verification +------------ + +The spi_boot core comes with a simple testbench that simulates an SD/MMC +card. All four implementations of the core are verified there in parallel +while transferring the data for several sets. +You should normally not need to run the testbench. But in case you modified +the VHDL code the testbench gives some hints if the design has been broken. + + +Directory Structure +------------------- + +The core's directory structure follows the proposal of OpenCores.org. + +spi_boot + | + \--+-- doc : Documentation + | | + | \-- src : Source files of documentation + | + +-- rtl + | | + | \-- vhdl : VHDL code containing the RTL description + | of the core. + | + +-- bench + | | + | \-- vhdl : VHDL testbench code. + | + \-- sim + | + \-- rtl_sim : Directory for running simulations. + + +RAM Loader +---------- + +Directory rtl/vhdl/ram_loader contains the sample design which loads the next +image from the card and stores its contents to external asynchronous +RAM. After reading 64 KB it triggers a new configuration process for the final +FPGA design. +Refer to the code for the mechanisms involved. + + +Compiling the VHDL Code +----------------------- + +VHDL compilation and simulation tasks take place inside in sim/rtl_sim +directory. The project setup supports only the GHDL simulator (see +http://ghdl.free.fr). + +To compile the code simply type at the shell + +$ make + +This should result in a file called tb_behav_c0 which can be executed as any +other executable. + +The basic simple sequence list can be found in COMPILE_LIST. This can be +useful to quickly set up the analyze stage of any compiler or +synthesizer. Especially when synthesizing the code, you want to skip the VHDL +configurations in *-c.vhd and everything below the bench/ directory. + + +References +---------- + + * SanDisk SD Card Product Manual + http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf + + * SanDisk MMC Product Manual + http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf + + * Toshiba SD Card Specification + http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf + + * BurchED + http://burched.biz/ + + * FPGA MMC-Card Config project + http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview diff --git a/usrp2/opencores/spi_boot/bench/CVS/Entries b/usrp2/opencores/spi_boot/bench/CVS/Entries new file mode 100644 index 000000000..a4756ee6f --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/CVS/Entries @@ -0,0 +1 @@ +D/vhdl//// diff --git a/usrp2/opencores/spi_boot/bench/CVS/Repository b/usrp2/opencores/spi_boot/bench/CVS/Repository new file mode 100644 index 000000000..ac45542a6 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/CVS/Repository @@ -0,0 +1 @@ +spi_boot/bench diff --git a/usrp2/opencores/spi_boot/bench/CVS/Root b/usrp2/opencores/spi_boot/bench/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/bench/CVS/Template b/usrp2/opencores/spi_boot/bench/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries new file mode 100644 index 000000000..8649c9f90 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries @@ -0,0 +1,13 @@ +/card-c.vhd/1.1/Tue Feb 8 21:09:18 2005// +/card.vhd/1.2/Sun Feb 13 17:06:22 2005// +/tb-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem-full-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem-minimal-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem-mmc-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem-sd-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem.vhd/1.7/Thu Apr 7 20:43:36 2005// +/tb_pack-p.vhd/1.2/Tue Mar 8 22:06:39 2005// +/tb_rl-c.vhd/1.1/Sun Apr 10 18:07:26 2005// +/tb_rl.vhd/1.1/Sun Apr 10 18:07:25 2005// +D diff --git a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository new file mode 100644 index 000000000..ce62c2b8e --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository @@ -0,0 +1 @@ +spi_boot/bench/vhdl diff --git a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd new file mode 100644 index 000000000..797eb1c90 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd @@ -0,0 +1,14 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: card-c.vhd,v 1.1 2005/02/08 21:09:18 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration card_behav_c0 of card is + + for behav + end for; + +end card_behav_c0; diff --git a/usrp2/opencores/spi_boot/bench/vhdl/card.vhd b/usrp2/opencores/spi_boot/bench/vhdl/card.vhd new file mode 100644 index 000000000..dcd676095 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/card.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Simple SD and MMC model +-- +-- $Id: card.vhd,v 1.2 2005/02/13 17:06:22 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity card is + + generic ( + card_type_g : string := "none"; + is_sd_card_g : integer := 1 + ); + + port ( + spi_clk_i : in std_logic; + spi_cs_n_i : in std_logic; + spi_data_i : in std_logic; + spi_data_o : out std_logic + ); + +end card; + + +library ieee; +use ieee.numeric_std.all; +library std; +use std.textio.all; + +use work.tb_pack.all; + +architecture behav of card is + + signal power_on_n_s : std_logic; + signal soft_res_n_s : std_logic; + signal res_n_s : std_logic; + + signal rx_s : std_logic_vector(47 downto 0); + + signal set_spi_mode_s, + spi_mode_q : boolean; + signal set_idle_mode_s, + poll_idle_mode_s : boolean; + signal idle_mode_q : natural; + + signal block_len_q, + block_len_s : unsigned(31 downto 0); + signal set_block_len_s : boolean; + + signal new_read_addr_s, + read_addr_q : unsigned(31 downto 0); + signal set_read_addr_s, + inc_read_addr_s : boolean; + + signal cmd_spi_data_s, + read_spi_data_s : std_logic; + signal start_read_s : boolean; + signal reading_s : boolean; + + procedure rise_clk is + begin + wait until spi_clk_i'event and to_X01(spi_clk_i) = '1'; + end rise_clk; + +-- procedure rise_clk(num : natural) is +-- begin +-- for i in 1 to num loop +-- rise_clk; +-- end loop; +-- end rise_clk; + + procedure fall_clk is + begin + wait until spi_clk_i'event and to_X01(spi_clk_i) = '0'; + end fall_clk; + + procedure fall_clk(num : natural) is + begin + for i in 1 to num loop + fall_clk; + end loop; + end fall_clk; + +begin + + res_n_s <= power_on_n_s and soft_res_n_s; + + ----------------------------------------------------------------------------- + -- Power on reset + ----------------------------------------------------------------------------- + por: process + begin + power_on_n_s <= '0'; + wait for 200 ns; + power_on_n_s <= '1'; + wait; + end process por; + + + ----------------------------------------------------------------------------- + -- + ctrl: process + + function check_crc(payload : in std_logic_vector(47 downto 0)) + return boolean is + + begin + + return calc_crc(payload(47 downto 8)) = payload(7 downto 1); + end check_crc; + + variable rx_v : std_logic_vector(47 downto 0); + variable cmd_v : std_logic_vector( 5 downto 0); + variable arg_v : std_logic_vector(31 downto 0); + variable crc_v : std_logic_vector( 6 downto 0); + variable wrong_v : std_logic; + variable read_data_v : boolean; + + begin + rx_s <= (others => '0'); + set_spi_mode_s <= false; + set_idle_mode_s <= false; + poll_idle_mode_s <= false; + cmd_spi_data_s <= '1'; + soft_res_n_s <= '1'; + set_block_len_s <= false; + block_len_s <= (others => '0'); + new_read_addr_s <= (others => '0'); + set_read_addr_s <= false; + start_read_s <= false; + read_data_v := false; + + loop + + rise_clk; + -- wait for startbit of command + while to_X01(spi_data_i) = '1' loop + rise_clk; + end loop; + rx_v(47) := '0'; + + -- read remaining 47 bits of command + for i in 46 downto 0 loop + rise_clk; + rx_v(i) := to_X01(spi_data_i); + end loop; + rx_s <= rx_v; + + -- dissect received data + cmd_v := rx_v(45 downto 40); + arg_v := rx_v(39 downto 8); + crc_v := rx_v( 7 downto 1); + + assert spi_mode_q or check_crc(payload => rx_v) + report "CRC mismatch" + severity error; + + wrong_v := '0'; + case cmd_v is + -- CMD0: GO_IDLE_STATE ------------------------------------------------ + when "000000" => + set_spi_mode_s <= true; + set_idle_mode_s <= true; + -- CMD1: SEND_OP_COND ------------------------------------------------- + when "000001" => + poll_idle_mode_s <= true; + -- CMD12: STOP_TRANSMISSION ------------------------------------------- + when "001100" => + start_read_s <= false; + read_data_v := false; + -- CMD16: SET_BLOCKLEN ------------------------------------------------ + when "010000" => + block_len_s <= unsigned(arg_v); + set_block_len_s <= true; + -- CMD18: READ_MULTIPLE_BLOCK ----------------------------------------- + when "010010" => + new_read_addr_s <= unsigned(arg_v); + set_read_addr_s <= true; + read_data_v := true; + -- CMD55: APPL_CMD ---------------------------------------------------- + when "110111" => + -- command only available for SD card + if is_sd_card_g /= 1 then + wrong_v := '1'; + end if; + -- ACMD41: SEND_OP_COND ----------------------------------------------- + when "101001" => + -- command only available for SD card + if is_sd_card_g /= 1 then + wrong_v := '1'; + else + poll_idle_mode_s <= true; + end if; + + when others => + wrong_v := '1'; + null; + end case; + + + -- spend some time before removing control signals + fall_clk(2); + poll_idle_mode_s <= false; + set_idle_mode_s <= false; + fall_clk(6); + set_spi_mode_s <= false; + set_block_len_s <= false; + set_read_addr_s <= false; + + if reading_s then + wait until not reading_s; + end if; + + + -- wait for a total two "bytes" before sending out response + for i in 1 to 8 loop + fall_clk; + end loop; + + for i in 7 downto 0 loop + fall_clk; + case i is + when 2 => + cmd_spi_data_s <= wrong_v; + when 0 => + if idle_mode_q = 0 then + cmd_spi_data_s <= '0'; + else + cmd_spi_data_s <= '1'; + end if; + when others => + cmd_spi_data_s <= '0'; + end case; + end loop; + fall_clk; + cmd_spi_data_s <= '1'; + + -- transmit data if requested + start_read_s <= read_data_v; + + end loop; + end process ctrl; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- + seq: process (res_n_s, + spi_clk_i, + set_spi_mode_s, + set_idle_mode_s, + poll_idle_mode_s, + set_block_len_s, + block_len_s) + + begin + if res_n_s = '0' then + spi_mode_q <= false; + idle_mode_q <= 5; + block_len_q <= (others => '0'); + read_addr_q <= (others => '0'); + + elsif spi_clk_i'event and spi_clk_i = '1' then + if set_spi_mode_s then + spi_mode_q <= true; + end if; + + if set_idle_mode_s then + idle_mode_q <= 5; + elsif poll_idle_mode_s then + if idle_mode_q > 0 then + idle_mode_q <= idle_mode_q - 1; + end if; + end if; + + if set_block_len_s then + block_len_q <= block_len_s; + end if; + + if set_read_addr_s then + read_addr_q <= new_read_addr_s; + elsif inc_read_addr_s then + read_addr_q <= read_addr_q + 1; + end if; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- + read_block: process + + variable t_v : unsigned(7 downto 0); + + begin + -- default assignments + inc_read_addr_s <= false; + reading_s <= false; + read_spi_data_s <= '1'; + + loop + if not start_read_s then + wait until start_read_s; + end if; + + reading_s <= true; + + fall_clk(8); -- delay for one "byte" + + -- send data token + fall_clk(7); -- 7 ones in a data token + read_spi_data_s <= '0'; + + -- send payload + payload: for i in 0 to to_integer(block_len_q)-1 loop + t_v := read_addr_q(0) & calc_crc(read_addr_q); + for bit in 7 downto 0 loop + fall_clk; + read_spi_data_s <= t_v(bit); + + exit payload when not start_read_s; + end loop; + inc_read_addr_s <= true; + rise_clk; + inc_read_addr_s <= false; + wait for 10 ns; + end loop; + + if start_read_s then + -- send crc + for i in 0 to 15 loop + fall_clk; + t_v := to_unsigned(i, 8); + read_spi_data_s <= t_v(0); + end loop; + fall_clk; + end if; + + read_spi_data_s <= '1'; + reading_s <= false; + -- loop for one "byte" + fall_clk(8); + + end loop; + end process read_block; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- + clk_check: process (spi_clk_i) + + variable last_rising_v : time := 0 ns; + variable dump_line : line; + + begin + if spi_clk_i'event and spi_clk_i = '1' then + if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and + idle_mode_q > 0 then + if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then + write(dump_line, card_type_g); + write(dump_line, string'(" @ ")); + write(dump_line, now); + write(dump_line, string'(": Last rising edge of SPI clock ")); + write(dump_line, now - last_rising_v); + write(dump_line, string'(" ago.")); + writeline(output, dump_line); + end if; + + last_rising_v := now; + end if; + end if; + end process clk_check; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + spi_data_o <= cmd_spi_data_s and read_spi_data_s + when spi_cs_n_i = '0' else + 'Z'; + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: card.vhd,v $ +-- Revision 1.2 2005/02/13 17:06:22 arniml +-- handle termination properly +-- +-- Revision 1.1 2005/02/08 21:09:20 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd new file mode 100644 index 000000000..caa171362 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd @@ -0,0 +1,31 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_behav_c0 of tb is + + for behav + + for tb_elem_full_b : tb_elem + use configuration work.tb_elem_behav_full; + end for; + + for tb_elem_mmc_b : tb_elem + use configuration work.tb_elem_behav_mmc; + end for; + + for tb_elem_sd_b : tb_elem + use configuration work.tb_elem_behav_sd; + end for; + + for tb_elem_minimal_b : tb_elem + use configuration work.tb_elem_behav_minimal; + end for; + + end for; + +end tb_behav_c0; diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd new file mode 100644 index 000000000..b359fa7c5 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd @@ -0,0 +1,201 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Testbench +-- +-- $Id: tb.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +entity tb is + +end tb; + + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb is + + component tb_elem + generic ( + chip_type_g : string := "none"; + has_sd_card_g : integer := 1 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + eos_o : out boolean + ); + end component; + + constant period_c : time := 100 ns; + constant reset_level_c : integer := 0; + + signal clk_s : std_logic; + signal reset_s : std_logic; + + signal eos_full_s, + eos_mmc_s, + eos_sd_s, + eos_minimal_s : boolean; + +begin + + + ----------------------------------------------------------------------------- + -- Testbench element including full featured chip + ----------------------------------------------------------------------------- + tb_elem_full_b : tb_elem + generic map ( + chip_type_g => "Full Chip", + has_sd_card_g => 1 + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + eos_o => eos_full_s + ); + + + ----------------------------------------------------------------------------- + -- Testbench element including MMC chip + ----------------------------------------------------------------------------- + tb_elem_mmc_b : tb_elem + generic map ( + chip_type_g => "MMC Chip", + has_sd_card_g => 0 + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + eos_o => eos_mmc_s + ); + + + ----------------------------------------------------------------------------- + -- Testbench element including SD chip + ----------------------------------------------------------------------------- + tb_elem_sd_b : tb_elem + generic map ( + chip_type_g => "SD Chip", + has_sd_card_g => 1 + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + eos_o => eos_sd_s + ); + + + ----------------------------------------------------------------------------- + -- Testbench element including cip with minimal features + ----------------------------------------------------------------------------- + tb_elem_minimal_b : tb_elem + generic map ( + chip_type_g => "Minimal Chip", + has_sd_card_g => 0 + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + eos_o => eos_minimal_s + ); + + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk: process + begin + clk_s <= '0'; + wait for period_c / 2; + clk_s <= '1'; + wait for period_c / 2; + end process clk; + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + reset: process + begin + if reset_level_c = 0 then + reset_s <= '0'; + else + reset_s <= '1'; + end if; + + wait for period_c * 4 + 10 ns; + + reset_s <= not reset_s; + + wait; + end process reset; + + + ----------------------------------------------------------------------------- + -- End Of Simulation Detection + ----------------------------------------------------------------------------- + eos: process (eos_full_s, + eos_mmc_s, + eos_sd_s, + eos_minimal_s) + begin + + if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then + assert false + report "End of Simulation." + severity failure; + end if; + + end process eos; + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: tb.vhd,v $ +-- Revision 1.1 2005/02/08 21:09:20 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd new file mode 100644 index 000000000..3c0fb902f --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_elem-full-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_elem_behav_full of tb_elem is + + for behav + + for dut_b : chip + use configuration work.chip_full_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + end for; + +end tb_elem_behav_full; diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd new file mode 100644 index 000000000..1c33ac3d0 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_elem-minimal-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_elem_behav_minimal of tb_elem is + + for behav + + for dut_b : chip + use configuration work.chip_minimal_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + end for; + +end tb_elem_behav_minimal; diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd new file mode 100644 index 000000000..b5baf604e --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_elem-mmc-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_elem_behav_mmc of tb_elem is + + for behav + + for dut_b : chip + use configuration work.chip_mmc_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + end for; + +end tb_elem_behav_mmc; diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd new file mode 100644 index 000000000..9cdf3eaa1 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_elem-sd-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_elem_behav_sd of tb_elem is + + for behav + + for dut_b : chip + use configuration work.chip_sd_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + end for; + +end tb_elem_behav_sd; diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd new file mode 100644 index 000000000..689cec037 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd @@ -0,0 +1,376 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Generic testbench element for a specific feature set +-- +-- $Id: tb_elem.vhd,v 1.7 2005/04/07 20:43:36 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity tb_elem is + + generic ( + chip_type_g : string := "none"; + has_sd_card_g : integer := 1 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + eos_o : out boolean + ); + +end tb_elem; + + +library ieee; +use ieee.numeric_std.all; +library std; +use std.textio.all; + +use work.spi_boot_pack.all; +use work.tb_pack.all; + +architecture behav of tb_elem is + + component chip + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_n_i : in std_logic_vector(3 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + component card + generic ( + card_type_g : string := "none"; + is_sd_card_g : integer := 1 + ); + port ( + spi_clk_i : in std_logic; + spi_cs_n_i : in std_logic; + spi_data_i : in std_logic; + spi_data_o : out std_logic + ); + end component; + + signal reset_s : std_logic; + + -- SPI interface signals + signal spi_clk_s : std_logic; + signal spi_data_to_card_s : std_logic; + signal spi_data_from_card_s : std_logic; + signal spi_cs_n_s : std_logic; + + -- config related signals + signal start_s : std_logic; + signal mode_s : std_logic; + signal config_n_s : std_logic; + signal cfg_init_n_s : std_logic; + signal cfg_done_s : std_logic; + signal dat_done_s : std_logic; + signal cfg_clk_s : std_logic; + signal cfg_dat_s : std_logic; + signal data_s : unsigned(7 downto 0); + + signal set_sel_n_s : std_logic_vector(3 downto 0); + + constant verbose_c : boolean := false; + +begin + + -- weak pull-ups + spi_clk_s <= 'H'; + spi_cs_n_s <= 'H'; + spi_data_to_card_s <= 'H'; + + ----------------------------------------------------------------------------- + -- DUT + ----------------------------------------------------------------------------- + dut_b : chip + port map ( + clk_i => clk_i, + reset_i => reset_s, + set_sel_n_i => set_sel_n_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_from_card_s, + spi_data_out_o => spi_data_to_card_s, + start_i => start_s, + mode_i => mode_s, + config_n_o => config_n_s, + detached_o => open, + cfg_init_n_i => cfg_init_n_s, + cfg_done_i => cfg_done_s, + dat_done_i => dat_done_s, + cfg_clk_o => cfg_clk_s, + cfg_dat_o => cfg_dat_s + ); + + card_b : card + generic map ( + card_type_g => chip_type_g, + is_sd_card_g => has_sd_card_g + ) + port map ( + spi_clk_i => spi_clk_s, + spi_cs_n_i => spi_cs_n_s, + spi_data_i => spi_data_to_card_s, + spi_data_o => spi_data_from_card_s + ); + + + ----------------------------------------------------------------------------- + -- DUT Stimuli + -- + stim: process + + procedure rise_cfg_clk(num : integer) is + begin + for i in 1 to num loop + wait until cfg_clk_s'event and cfg_clk_s = '1'; + end loop; + end rise_cfg_clk; + +-- procedure fall_cfg_clk(num : integer) is +-- begin +-- for i in 1 to num loop +-- wait until cfg_clk_s'event and cfg_clk_s = '0'; +-- end loop; +-- end fall_cfg_clk; + + procedure rise_clk(num : integer) is + begin + for i in 1 to num loop + wait until clk_i'event and clk_i = '1'; + end loop; + end rise_clk; + + procedure read_check_byte(ref : unsigned(7 downto 0)) is + variable byte_v : unsigned(7 downto 0); + variable dump_line : line; + begin + for bit in 7 downto 0 loop + rise_cfg_clk(1); + byte_v(bit) := cfg_dat_s; + end loop; + data_s <= byte_v; + + if byte_v /= ref then + write(dump_line, chip_type_g); + write(dump_line, string'(" at ")); + write(dump_line, now); + write(dump_line, string'(": read_check_byte failed ")); + write(dump_line, to_integer(byte_v)); + write(dump_line, string'(" ")); + write(dump_line, to_integer(ref)); + writeline(output, dump_line); + end if; + end read_check_byte; + + variable dump_line : line; + variable addr_v : unsigned(31 downto 0); + variable temp_v : unsigned( 7 downto 0); + variable set_sel_v : unsigned(3 downto 0); + + begin + -- default assignments + -- these defaults show the required pull resistors + -- except start_i as this must be pulled high for automatic start + start_s <= '0'; + mode_s <= '1'; + cfg_init_n_s <= '1'; + cfg_done_s <= '0'; + dat_done_s <= '1'; + data_s <= (others => '1'); + addr_v := (others => '0'); + eos_o <= false; + set_sel_n_s <= (others => '1'); + reset_s <= '0'; + + -- loop through some sets + for set in 0 to 3 loop + set_sel_v := to_unsigned(set, 4); + addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g + -- plus width_img_cnt_g + set_sel_n_s <= not std_logic_vector(set_sel_v); + + assert not verbose_c + report chip_type_g & ": Processing set " & to_string(set) + severity note; + + wait for 100 us; + reset_s <= '1'; + + assert not verbose_c + report chip_type_g & ": Requesting image 0" + severity note; + + -- signal start + start_s <= '1'; + mode_s <= '1'; + cfg_done_s <= '0'; + addr_v(19 downto 0) := (others => '0'); + wait until config_n_s = '0'; + -- run through configuration sequence + rise_clk(1); + cfg_init_n_s <= '0'; + rise_clk(3); + cfg_init_n_s <= '1'; + + -- and receive 32 bytes from image 0 + for i in 1 to 32 loop + temp_v := addr_v(0) & calc_crc(addr_v); + read_check_byte(temp_v); + addr_v := addr_v + 1; + end loop; + start_s <= '0'; + cfg_done_s <= '1'; + + rise_clk(10); + + assert not verbose_c + report chip_type_g & ": Requesting image 1" + severity note; + + -- request next image + mode_s <= '0'; + start_s <= '1'; + addr_v(17 downto 0) := (others => '0'); + addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd + dat_done_s <= '0'; + + -- receive another 32 bytes from image 1 + for i in 1 to 32 loop + temp_v := addr_v(0) & calc_crc(addr_v); + read_check_byte(temp_v); + addr_v := addr_v + 1; + end loop; + start_s <= '0'; + dat_done_s <= '1'; + + + rise_clk(10); + + assert not verbose_c + report chip_type_g & ": Requesting image 2" + severity note; + + -- request next image + mode_s <= '1'; + start_s <= '1'; + addr_v(17 downto 0) := (others => '0'); + addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd + + wait until config_n_s = '0'; + -- run through configuration sequence + rise_clk(1); + cfg_done_s <= '0'; + cfg_init_n_s <= '0'; + rise_clk(3); + cfg_init_n_s <= '1'; + + -- receive another 32 bytes from image 2 + for i in 1 to 32 loop + temp_v := addr_v(0) & calc_crc(addr_v); + read_check_byte(temp_v); + addr_v := addr_v + 1; + end loop; + start_s <= '0'; + cfg_done_s <= '1'; + + -- give dut a chance to stop current transfer + wait until spi_cs_n_s = '1'; + rise_clk(10); + + reset_s <= '0'; + end loop; + + eos_o <= true; + wait; + end process stim; + -- + ----------------------------------------------------------------------------- + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: tb_elem.vhd,v $ +-- Revision 1.7 2005/04/07 20:43:36 arniml +-- add new port detached_o +-- +-- Revision 1.6 2005/03/09 19:48:04 arniml +-- make verbosity level switchable +-- +-- Revision 1.5 2005/03/08 22:06:21 arniml +-- added set selection +-- +-- Revision 1.4 2005/02/17 18:59:23 arniml +-- clarify wording for images +-- +-- Revision 1.3 2005/02/16 19:34:56 arniml +-- add weak pull-ups for SPI lines +-- +-- Revision 1.2 2005/02/13 17:14:03 arniml +-- change dat_done handling +-- +-- Revision 1.1 2005/02/08 21:09:20 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd new file mode 100644 index 000000000..7534aafdc --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd @@ -0,0 +1,93 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_pack-p.vhd,v 1.2 2005/03/08 22:06:39 arniml Exp $ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package tb_pack is + + function calc_crc(payload : in std_logic_vector) return std_logic_vector; + function calc_crc(payload : in unsigned) return unsigned; + + function to_string(value : in integer) return string; + +end tb_pack; + + +package body tb_pack is + + function calc_crc(payload : in std_logic_vector) return std_logic_vector is + + variable crc_v : std_logic_vector(6 downto 0); + variable temp_v : std_logic; + + begin + + crc_v := (others => '0'); + + for i in payload'high downto payload'low loop + temp_v := payload(i) xor crc_v(6); + + crc_v(6 downto 4) := crc_v(5 downto 3); + crc_v(3) := crc_v(2) xor temp_v; + crc_v(2 downto 1) := crc_v(1 downto 0); + crc_v(0) := temp_v; + end loop; + + return crc_v; + end calc_crc; + + function calc_crc(payload : in unsigned) return unsigned is + begin + return unsigned(calc_crc(std_logic_vector(payload))); + end calc_crc; + + function to_string(value : in integer) return string is + variable str: string (11 downto 1); + variable val: integer := value; + variable digit: natural; + variable index: natural := 0; + begin + -- Taken from: + -- textio package body. This file is part of GHDL. + -- Copyright (C) 2002 Tristan Gingold. + -- Note: the absolute value of VAL cannot be directly taken, since + -- it may be greather that the maximum value of an INTEGER. + loop + -- LRM93 7.2.6 + -- (A rem B) has the sign of A and an absolute value less then + -- the absoulte value of B. + digit := abs (val rem 10); + val := val / 10; + index := index + 1; + str (index) := character'val(48 + digit); + exit when val = 0; + end loop; + if value < 0 then + index := index + 1; + str(index) := '-'; + end if; + + return str; + end to_string; + +end tb_pack; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: tb_pack-p.vhd,v $ +-- Revision 1.2 2005/03/08 22:06:39 arniml +-- added integer->string conversion function +-- +-- Revision 1.1 2005/02/08 21:09:20 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd new file mode 100644 index 000000000..84273abc5 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd @@ -0,0 +1,27 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_rl-c.vhd,v 1.1 2005/04/10 18:07:26 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_rl_behav_c0 of tb_rl is + + for behav + + for dut_b : chip + use configuration work.chip_full_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + for rl_b : ram_loader + use configuration work.ram_loader_rtl_c0; + end for; + + end for; + +end tb_rl_behav_c0; diff --git a/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd new file mode 100644 index 000000000..9f28e62b4 --- /dev/null +++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd @@ -0,0 +1,259 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Testbench for ram_loader +-- +-- $Id: tb_rl.vhd,v 1.1 2005/04/10 18:07:25 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +entity tb_rl is + +end tb_rl; + + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_rl is + + component chip + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_n_i : in std_logic_vector(3 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + component card + generic ( + card_type_g : string := "none"; + is_sd_card_g : integer := 1 + ); + port ( + spi_clk_i : in std_logic; + spi_cs_n_i : in std_logic; + spi_data_i : in std_logic; + spi_data_o : out std_logic + ); + end component; + + component ram_loader + port ( + clk_i : in std_logic; + reset_i : in std_logic; + lamp_o : out std_logic; + cfg_clk_i : in std_logic; + cfg_data_i : in std_logic; + start_o : out std_logic; + mode_o : out std_logic; + done_o : out std_logic; + detached_i : in std_logic; + ram_addr_o : out std_logic_vector(15 downto 0); + ram_data_b : out std_logic_vector( 7 downto 0); + ram_ce_no : out std_logic_vector( 3 downto 0); + ram_oe_no : out std_logic; + ram_we_no : out std_logic + ); + end component; + + constant period_c : time := 100 ns; + constant rl_period_c : time := 20 ns; + constant reset_level_c : integer := 0; + + signal clk_s : std_logic; + signal rl_clk_s: std_logic; + signal reset_s : std_logic; + + -- SPI interface signals + signal spi_clk_s : std_logic; + signal spi_data_to_card_s : std_logic; + signal spi_data_from_card_s : std_logic; + signal spi_cs_n_s : std_logic; + + -- config related signals + signal start_s : std_logic; + signal mode_s : std_logic; + signal config_n_s : std_logic; + signal cfg_init_n_s : std_logic; + signal cfg_done_s : std_logic; + signal dat_done_s : std_logic; + signal cfg_clk_s : std_logic; + signal cfg_dat_s : std_logic; + signal detached_s : std_logic; + + signal set_sel_n_s : std_logic_vector(3 downto 0); + +begin + + set_sel_n_s <= (others => '1'); + cfg_init_n_s <= '1'; + cfg_done_s <= '1'; + + ----------------------------------------------------------------------------- + -- DUT + ----------------------------------------------------------------------------- + dut_b : chip + port map ( + clk_i => clk_s, + reset_i => reset_s, + set_sel_n_i => set_sel_n_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_from_card_s, + spi_data_out_o => spi_data_to_card_s, + start_i => start_s, + mode_i => mode_s, + config_n_o => config_n_s, + detached_o => detached_s, + cfg_init_n_i => cfg_init_n_s, + cfg_done_i => cfg_done_s, + dat_done_i => dat_done_s, + cfg_clk_o => cfg_clk_s, + cfg_dat_o => cfg_dat_s + ); + + card_b : card + generic map ( + card_type_g => "Full Chip", + is_sd_card_g => 1 + ) + port map ( + spi_clk_i => spi_clk_s, + spi_cs_n_i => spi_cs_n_s, + spi_data_i => spi_data_to_card_s, + spi_data_o => spi_data_from_card_s + ); + + rl_b : ram_loader + port map ( + clk_i => rl_clk_s, + reset_i => reset_s, + lamp_o => open, + cfg_clk_i => cfg_clk_s, + cfg_data_i => cfg_dat_s, + start_o => start_s, + mode_o => mode_s, + done_o => dat_done_s, + detached_i => detached_s, + ram_addr_o => open, + ram_data_b => open, + ram_ce_no => open, + ram_oe_no => open, + ram_we_no => open + ); + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk: process + begin + clk_s <= '0'; + wait for period_c / 2; + clk_s <= '1'; + wait for period_c / 2; + end process clk; + + rl_clk: process + begin + rl_clk_s <= '0'; + wait for rl_period_c / 2; + rl_clk_s <= '1'; + wait for rl_period_c / 2; + end process rl_clk; + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + reset: process + begin + if reset_level_c = 0 then + reset_s <= '0'; + else + reset_s <= '1'; + end if; + + wait for period_c * 4 + 10 ns; + + reset_s <= not reset_s; + + wait; + end process reset; + + + ----------------------------------------------------------------------------- + -- End of Simulation + ----------------------------------------------------------------------------- + eos: process + begin + wait for 4 ms; + assert false + report "No checks have been performed. Investigate waveforms." + severity note; + assert false + report "End of simulation." + severity failure; + end process eos; + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: tb_rl.vhd,v $ +-- Revision 1.1 2005/04/10 18:07:25 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/doc/CVS/Entries b/usrp2/opencores/spi_boot/doc/CVS/Entries new file mode 100644 index 000000000..630615f41 --- /dev/null +++ b/usrp2/opencores/spi_boot/doc/CVS/Entries @@ -0,0 +1,3 @@ +/spi_boot.pdf/1.6/Thu Mar 16 17:09:56 2006/-kb/ +/spi_boot_schematic.pdf/1.3/Thu Apr 14 21:20:35 2005/-kb/ +D/src//// diff --git a/usrp2/opencores/spi_boot/doc/CVS/Repository b/usrp2/opencores/spi_boot/doc/CVS/Repository new file mode 100644 index 000000000..07fb78846 --- /dev/null +++ b/usrp2/opencores/spi_boot/doc/CVS/Repository @@ -0,0 +1 @@ +spi_boot/doc diff --git a/usrp2/opencores/spi_boot/doc/CVS/Root b/usrp2/opencores/spi_boot/doc/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/doc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/doc/CVS/Template b/usrp2/opencores/spi_boot/doc/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/doc/spi_boot.pdf b/usrp2/opencores/spi_boot/doc/spi_boot.pdf new file mode 100644 index 000000000..a889c3f22 Binary files /dev/null and b/usrp2/opencores/spi_boot/doc/spi_boot.pdf differ diff --git a/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf b/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf new file mode 100644 index 000000000..92755d5f3 Binary files /dev/null and b/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf differ diff --git a/usrp2/opencores/spi_boot/doc/src/CVS/Entries b/usrp2/opencores/spi_boot/doc/src/CVS/Entries new file mode 100644 index 000000000..b2d32af23 --- /dev/null +++ b/usrp2/opencores/spi_boot/doc/src/CVS/Entries @@ -0,0 +1,10 @@ +/architecture.eps/1.4/Thu Apr 14 21:18:11 2005/-kb/ +/architecture.fig/1.4/Thu Apr 14 21:18:11 2005/-kb/ +/initialization.eps/1.2/Thu Mar 16 15:41:16 2006/-kb/ +/initialization.fig/1.2/Thu Mar 16 15:41:16 2006/-kb/ +/memory_organization.eps/1.2/Thu Mar 16 16:50:57 2006/-kb/ +/memory_organization.fig/1.2/Thu Mar 16 16:50:57 2006/-kb/ +/spi_boot.sxw/1.6/Thu Mar 16 17:09:31 2006/-kb/ +/transfer.eps/1.1/Sun Feb 27 19:24:30 2005/-kb/ +/transfer.fig/1.1/Sun Feb 27 19:24:35 2005/-kb/ +D diff --git a/usrp2/opencores/spi_boot/doc/src/CVS/Repository b/usrp2/opencores/spi_boot/doc/src/CVS/Repository new file mode 100644 index 000000000..5f8aafef8 --- /dev/null +++ b/usrp2/opencores/spi_boot/doc/src/CVS/Repository @@ -0,0 +1 @@ +spi_boot/doc/src diff --git a/usrp2/opencores/spi_boot/doc/src/CVS/Root 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-1 roll mul add + 4 -2 roll dup 1 exch sub 3 -1 roll mul add srgb} + bind def +/shd {dup dup currentrgbcolor 4 -2 roll mul 4 -2 roll mul + 4 -2 roll mul srgb} bind def +/$F2psBegin {$F2psDict begin /$F2psEnteredState save def} def +/$F2psEnd {$F2psEnteredState restore end} def + +$F2psBegin +10 setmiterlimit + 0.04094 0.04094 sc +% +% Fig objects follow +% +/Helvetica ff 150.00 scf sf +3780 5017 m +gs 1 -1 sc (CMD18) dup sw pop 2 div neg 0 rm col0 sh gr +/Helvetica ff 150.00 scf sf +3780 5242 m +gs 1 -1 sc (READ_MULTIPLE_BLOCKS) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +15.000 slw +n 2745 4770 m 4815 4770 l 4815 5400 l 2745 5400 l + cp gs col0 s gr +% Polyline +n 3060 2790 m 4500 2790 l 4500 3420 l 3060 3420 l + cp gs col0 s gr +/Helvetica ff 150.00 scf sf +3780 3150 m +gs 1 -1 sc (Wait for start) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 3780 3780 m 4500 4050 l 3780 4410 l 3060 4050 l + cp gs col0 s gr +/Helvetica ff 150.00 scf sf +3780 4132 m +gs 1 -1 sc (mode = 1?) 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+6660 6112 m +gs 1 -1 sc (cfg_init_n low?) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 5940 6750 m 7380 6750 l 7380 7380 l 5940 7380 l + cp gs col0 s gr +/Helvetica ff 150.00 scf sf +6660 7110 m +gs 1 -1 sc (Deactivate config_n) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 6660 7740 m 7380 8010 l 6660 8370 l 5940 8010 l + cp gs col0 s gr +/Helvetica ff 150.00 scf sf +6660 8092 m +gs 1 -1 sc (cfg_init_n high?) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +7.500 slw +gs clippath +3757 3795 m 3802 3795 l 3802 3674 l 3780 3764 l 3757 3674 l cp +eoclip +n 3780 3420 m + 3780 3780 l gs col0 s gr gr + +% arrowhead +n 3757 3674 m 3780 3764 l 3802 3674 l 3757 3674 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3757 4785 m 3802 4785 l 3802 4664 l 3780 4754 l 3757 4664 l cp +eoclip +n 3780 4410 m + 3780 4770 l gs col0 s gr gr + +% arrowhead +n 3757 4664 m 3780 4754 l 3802 4664 l 3757 4664 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3757 5775 m 3802 5775 l 3802 5654 l 3780 5744 l 3757 5654 l cp +eoclip +n 3780 5400 m + 3780 5760 l gs col0 s gr gr + +% arrowhead +n 3757 5654 m 3780 5744 l 3802 5654 l 3757 5654 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3757 6765 m 3802 6765 l 3802 6644 l 3780 6734 l 3757 6644 l cp +eoclip +n 3780 6390 m + 3780 6750 l gs col0 s gr gr + +% arrowhead +n 3757 6644 m 3780 6734 l 3802 6644 l 3757 6644 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3757 7755 m 3802 7755 l 3802 7634 l 3780 7724 l 3757 7634 l cp +eoclip +n 3780 7380 m + 3780 7740 l gs col0 s gr gr + +% arrowhead +n 3757 7634 m 3780 7724 l 3802 7634 l 3757 7634 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3765 5512 m 3765 5557 l 3886 5557 l 3796 5535 l 3886 5512 l cp +eoclip +n 4545 7020 m 5130 7020 l 5130 5535 l + 3780 5535 l gs col0 s gr gr + +% arrowhead +n 3886 5512 m 3796 5535 l 3886 5557 l 3886 5512 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3757 2805 m 3802 2805 l 3802 2684 l 3780 2774 l 3757 2684 l cp +eoclip +n 3780 8370 m 3780 8640 l 2520 8640 l 2520 2520 l 3780 2520 l + 3780 2790 l gs col0 s gr gr + +% arrowhead +n 3757 2684 m 3780 2774 l 3802 2684 l 3757 2684 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3765 3532 m 3765 3577 l 3886 3577 l 3796 3555 l 3886 3532 l cp +eoclip +n 4680 3555 m + 3780 3555 l gs col0 s gr gr + +% arrowhead +n 3886 3532 m 3796 3555 l 3886 3577 l 3886 3532 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6637 4785 m 6682 4785 l 6682 4664 l 6660 4754 l 6637 4664 l cp +eoclip +n 4500 4050 m 6660 4050 l + 6660 4770 l gs col0 s gr gr + +% arrowhead +n 6637 4664 m 6660 4754 l 6682 4664 l 6637 4664 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6645 4027 m 6645 4072 l 6766 4072 l 6676 4050 l 6766 4027 l cp +eoclip +n 7380 6030 m 7920 6030 l 7920 4050 l + 6660 4050 l gs col0 s gr gr + +% arrowhead +n 6766 4027 m 6676 4050 l 6766 4072 l 6766 4027 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6645 6502 m 6645 6547 l 6766 6547 l 6676 6525 l 6766 6502 l cp +eoclip +n 7380 8010 m 7920 8010 l 7920 6525 l + 6660 6525 l gs col0 s gr gr + +% arrowhead +n 6766 6502 m 6676 6525 l 6766 6547 l 6766 6502 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3765 4522 m 3765 4567 l 3886 4567 l 3796 4545 l 3886 4522 l cp +eoclip +n 6660 8370 m 6660 8640 l 5310 8640 l 5310 4545 l + 3780 4545 l gs col0 s gr gr + +% arrowhead +n 3886 4522 m 3796 4545 l 3886 4567 l 3886 4522 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6637 5775 m 6682 5775 l 6682 5654 l 6660 5744 l 6637 5654 l cp +eoclip +n 6660 5400 m + 6660 5760 l gs col0 s gr gr + +% arrowhead +n 6637 5654 m 6660 5744 l 6682 5654 l 6637 5654 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6637 6765 m 6682 6765 l 6682 6644 l 6660 6734 l 6637 6644 l cp +eoclip +n 6660 6390 m + 6660 6750 l gs col0 s gr gr + +% arrowhead +n 6637 6644 m 6660 6734 l 6682 6644 l 6637 6644 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6637 7755 m 6682 7755 l 6682 7634 l 6660 7724 l 6637 7634 l cp +eoclip +n 6660 7380 m + 6660 7740 l gs col0 s gr gr + +% arrowhead +n 6637 7634 m 6660 7724 l 6682 7634 l 6637 7634 l cp gs 0.00 setgray ef gr col0 s +/Helvetica ff 150.00 scf sf +3870 7560 m +gs 1 -1 sc (Yes) col0 sh gr +/Helvetica ff 150.00 scf sf +4590 6930 m +gs 1 -1 sc (No) col0 sh gr +/Helvetica ff 150.00 scf sf +4770 3600 m +gs 1 -1 sc (start) col0 sh gr +/Helvetica ff 150.00 scf sf +3690 4590 m +gs 1 -1 sc (No) dup sw pop neg 0 rm col0 sh gr +/Helvetica ff 150.00 scf sf +4590 3960 m +gs 1 -1 sc (Yes) col0 sh gr +/Helvetica ff 150.00 scf sf +7470 5940 m +gs 1 -1 sc (No) col0 sh gr +/Helvetica ff 150.00 scf sf +6570 6570 m +gs 1 -1 sc (Yes) dup sw pop neg 0 rm col0 sh gr +/Helvetica ff 150.00 scf sf +7470 7920 m +gs 1 -1 sc (No) col0 sh gr +/Helvetica ff 150.00 scf sf +6750 8550 m +gs 1 -1 sc (Yes) col0 sh gr +$F2psEnd +rs diff --git a/usrp2/opencores/spi_boot/doc/src/transfer.fig b/usrp2/opencores/spi_boot/doc/src/transfer.fig new file mode 100644 index 000000000..3d1724050 --- /dev/null +++ b/usrp2/opencores/spi_boot/doc/src/transfer.fig @@ -0,0 +1,119 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +65.00 +Single +-2 +1200 2 +6 2700 4725 4860 5445 +6 2970 4860 4590 5265 +4 1 0 50 0 16 10 0.0000 4 120 435 3780 5017 CMD18\001 +4 1 0 50 0 16 10 0.0000 4 120 1560 3780 5242 READ_MULTIPLE_BLOCKS\001 +-6 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 2745 4770 4815 4770 4815 5400 2745 5400 2745 4770 +-6 +6 3015 2745 4545 3465 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3060 2790 4500 2790 4500 3420 3060 3420 3060 2790 +4 1 0 50 0 16 10 0.0000 4 120 705 3780 3150 Wait for start\001 +-6 +6 3015 3735 4545 4455 +2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3780 3780 4500 4050 3780 4410 3060 4050 3780 3780 +4 1 0 50 0 16 10 0.0000 4 135 615 3780 4132 mode = 1?\001 +-6 +6 3015 5715 4545 6435 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3060 5760 4500 5760 4500 6390 3060 6390 3060 5760 +4 1 0 50 0 16 10 0.0000 4 120 645 3780 6120 Read block\001 +-6 +6 3015 6705 4545 7425 +2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3780 6750 4500 7020 3780 7380 3060 7020 3780 6750 +4 1 0 50 0 16 10 0.0000 4 120 675 3780 7102 ???_done?\001 +-6 +6 2835 7695 4725 8415 +6 3105 7830 4455 8235 +4 1 0 50 0 16 10 0.0000 4 120 435 3780 7987 CMD12\001 +4 1 0 50 0 16 10 0.0000 4 120 1290 3780 8212 STOP_TRANSMISSION\001 +-6 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 2880 7740 4680 7740 4680 8370 2880 8370 2880 7740 +-6 +6 5895 4725 7425 5445 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 5940 4770 7380 4770 7380 5400 5940 5400 5940 4770 +4 1 0 50 0 16 10 0.0000 4 135 960 6660 5130 Activate config_n\001 +-6 +6 5895 5715 7425 6435 +2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 6660 5760 7380 6030 6660 6390 5940 6030 6660 5760 +4 1 0 50 0 16 10 0.0000 4 135 855 6660 6112 cfg_init_n low?\001 +-6 +6 5895 6705 7425 7425 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 5940 6750 7380 6750 7380 7380 5940 7380 5940 6750 +4 1 0 50 0 16 10 0.0000 4 135 1125 6660 7110 Deactivate config_n\001 +-6 +6 5895 7695 7425 8415 +2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 6660 7740 7380 8010 6660 8370 5940 8010 6660 7740 +4 1 0 50 0 16 10 0.0000 4 135 915 6660 8092 cfg_init_n high?\001 +-6 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 3420 3780 3780 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 4410 3780 4770 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 5400 3780 5760 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 6390 3780 6750 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 7380 3780 7740 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 + 1 1 1.00 45.00 90.00 + 4545 7020 5130 7020 5130 5535 3780 5535 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 6 + 1 1 1.00 45.00 90.00 + 3780 8370 3780 8640 2520 8640 2520 2520 3780 2520 3780 2790 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 4680 3555 3780 3555 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 3 + 1 1 1.00 45.00 90.00 + 4500 4050 6660 4050 6660 4770 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 + 1 1 1.00 45.00 90.00 + 7380 6030 7920 6030 7920 4050 6660 4050 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 + 1 1 1.00 45.00 90.00 + 7380 8010 7920 8010 7920 6525 6660 6525 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 5 + 1 1 1.00 45.00 90.00 + 6660 8370 6660 8640 5310 8640 5310 4545 3780 4545 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 6660 5400 6660 5760 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 6660 6390 6660 6750 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 6660 7380 6660 7740 +4 0 0 50 0 16 10 0.0000 4 105 210 3870 7560 Yes\001 +4 0 0 50 0 16 10 0.0000 4 105 165 4590 6930 No\001 +4 0 0 50 0 16 10 0.0000 4 105 240 4770 3600 start\001 +4 2 0 50 0 16 10 0.0000 4 105 165 3690 4590 No\001 +4 0 0 50 0 16 10 0.0000 4 105 210 4590 3960 Yes\001 +4 0 0 50 0 16 10 0.0000 4 105 165 7470 5940 No\001 +4 2 0 50 0 16 10 0.0000 4 105 210 6570 6570 Yes\001 +4 0 0 50 0 16 10 0.0000 4 105 165 7470 7920 No\001 +4 0 0 50 0 16 10 0.0000 4 105 210 6750 8550 Yes\001 diff --git a/usrp2/opencores/spi_boot/rtl/CVS/Entries b/usrp2/opencores/spi_boot/rtl/CVS/Entries new file mode 100644 index 000000000..a4756ee6f --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/CVS/Entries @@ -0,0 +1 @@ +D/vhdl//// diff --git a/usrp2/opencores/spi_boot/rtl/CVS/Repository b/usrp2/opencores/spi_boot/rtl/CVS/Repository new file mode 100644 index 000000000..dcb0a69bc --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/CVS/Repository @@ -0,0 +1 @@ +spi_boot/rtl diff --git a/usrp2/opencores/spi_boot/rtl/CVS/Root b/usrp2/opencores/spi_boot/rtl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/rtl/CVS/Template b/usrp2/opencores/spi_boot/rtl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries new file mode 100644 index 000000000..880f353ca --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries @@ -0,0 +1,15 @@ +/chip-e.vhd/1.3/Thu Apr 7 20:44:23 2005// +/chip-full-a.vhd/1.6/Thu Apr 7 20:44:23 2005// +/chip-full-c.vhd/1.1/Tue Feb 8 20:41:31 2005// +/chip-minimal-a.vhd/1.6/Thu Apr 7 20:44:23 2005// +/chip-minimal-c.vhd/1.1/Tue Feb 8 20:41:32 2005// +/chip-mmc-a.vhd/1.6/Thu Apr 7 20:44:23 2005// +/chip-mmc-c.vhd/1.1/Tue Feb 8 20:41:32 2005// +/chip-sd-a.vhd/1.6/Thu Apr 7 20:44:23 2005// +/chip-sd-c.vhd/1.1/Tue Feb 8 20:41:33 2005// +/spi_boot-c.vhd/1.2/Fri Feb 18 06:42:11 2005// +/spi_boot.vhd/1.9/Sun Feb 25 18:24:12 2007// +/spi_boot_pack-p.vhd/1.1/Tue Feb 8 20:41:33 2005// +/spi_counter-c.vhd/1.1/Tue Feb 8 20:41:33 2005// +/spi_counter.vhd/1.2/Sun Feb 25 18:24:12 2007// +D/sample//// diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository new file mode 100644 index 000000000..a09f391ea --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository @@ -0,0 +1 @@ +spi_boot/rtl/vhdl diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd new file mode 100644 index 000000000..0bdd05aff --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel +-- +-- $Id: chip-e.vhd,v 1.3 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity chip is + + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_n_i : in std_logic_vector(3 downto 0); + -- SD Card Interface ------------------------------------------------------ + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + -- FPGA Configuration Interface ------------------------------------------- + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + +end chip; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-e.vhd,v $ +-- Revision 1.3 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.2 2005/03/08 22:07:11 arniml +-- added set selection +-- +-- Revision 1.1 2005/02/08 20:41:30 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd new file mode 100644 index 000000000..e43ecb3c4 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel design with full feature set +-- +-- $Id: chip-full-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +architecture full of chip is + + component spi_boot + generic ( + width_set_sel_g : integer := 4; + width_bit_cnt_g : integer := 6; + width_img_cnt_g : integer := 2; + num_bits_per_img_g : integer := 18; + sd_init_g : integer := 0; + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + signal spi_clk_s : std_logic; + signal spi_cs_n_s : std_logic; + signal spi_data_out_s : std_logic; + signal spi_en_outs_s : std_logic; + + signal set_sel_s : std_logic_vector(3 downto 0); + +begin + + set_sel_s <= not set_sel_n_i; + + spi_boot_b : spi_boot + generic map ( + width_set_sel_g => 4, -- 16 sets + width_bit_cnt_g => 12, -- 512 bytes per block + width_img_cnt_g => 2, -- 4 images + num_bits_per_img_g => 18, -- 256 kByte per image + sd_init_g => 1, -- use SD specific initialization + mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2) + width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + set_sel_i => set_sel_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_in_i, + spi_data_out_o => spi_data_out_s, + spi_en_outs_o => spi_en_outs_s, + start_i => start_i, + mode_i => mode_i, + config_n_o => config_n_o, + detached_o => detached_o, + cfg_init_n_i => cfg_init_n_i, + cfg_done_i => cfg_done_i, + dat_done_i => dat_done_i, + cfg_clk_o => cfg_clk_o, + cfg_dat_o => cfg_dat_o + ); + + ----------------------------------------------------------------------------- + -- Three state drivers for SPI outputs. + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_s + when spi_en_outs_s = '1' else + 'Z'; + spi_cs_n_o <= spi_cs_n_s + when spi_en_outs_s = '1' else + 'Z'; + spi_data_out_o <= spi_data_out_s + when spi_en_outs_s = '1' else + 'Z'; + +end full; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-full-a.vhd,v $ +-- Revision 1.6 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.5 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.4 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.3 2005/02/18 06:42:11 arniml +-- clarify wording for images +-- +-- Revision 1.2 2005/02/16 18:54:37 arniml +-- added tri-state drivers for spi outputs +-- +-- Revision 1.1 2005/02/08 20:41:31 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd new file mode 100644 index 000000000..da88552c4 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: chip-full-c.vhd,v 1.1 2005/02/08 20:41:31 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration chip_full_c0 of chip is + + for full + + for spi_boot_b : spi_boot + use configuration work.spi_boot_rtl_c0; + end for; + + end for; + +end chip_full_c0; diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd new file mode 100644 index 000000000..090d0b79c --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel design with minimal feature set +-- +-- $Id: chip-minimal-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +architecture minimal of chip is + + component spi_boot + generic ( + width_set_sel_g : integer := 4; + width_bit_cnt_g : integer := 6; + width_img_cnt_g : integer := 2; + num_bits_per_img_g : integer := 18; + sd_init_g : integer := 0; + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + signal spi_clk_s : std_logic; + signal spi_cs_n_s : std_logic; + signal spi_data_out_s : std_logic; + signal spi_en_outs_s : std_logic; + + signal set_sel_s : std_logic_vector(3 downto 0); + +begin + + set_sel_s <= not set_sel_n_i; + + spi_boot_b : spi_boot + generic map ( + width_set_sel_g => 4, -- 16 sets + width_bit_cnt_g => 6, -- 8 bytes per block + width_img_cnt_g => 2, -- 4 images + num_bits_per_img_g => 18, -- 256 kByte per image + sd_init_g => 0, -- no SD specific initialization + mmc_compat_clk_div_g => 0, -- no MMC compatibility + width_mmc_clk_div_g => 0 -- no MMC compatibility + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + set_sel_i => set_sel_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_in_i, + spi_data_out_o => spi_data_out_s, + spi_en_outs_o => spi_en_outs_s, + start_i => start_i, + mode_i => mode_i, + config_n_o => config_n_o, + detached_o => detached_o, + cfg_init_n_i => cfg_init_n_i, + cfg_done_i => cfg_done_i, + dat_done_i => dat_done_i, + cfg_clk_o => cfg_clk_o, + cfg_dat_o => cfg_dat_o + ); + + ----------------------------------------------------------------------------- + -- Three state drivers for SPI outputs. + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_s + when spi_en_outs_s = '1' else + 'Z'; + spi_cs_n_o <= spi_cs_n_s + when spi_en_outs_s = '1' else + 'Z'; + spi_data_out_o <= spi_data_out_s + when spi_en_outs_s = '1' else + 'Z'; + +end minimal; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-minimal-a.vhd,v $ +-- Revision 1.6 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.5 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.4 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.3 2005/02/18 06:42:12 arniml +-- clarify wording for images +-- +-- Revision 1.2 2005/02/16 18:54:39 arniml +-- added tri-state drivers for spi outputs +-- +-- Revision 1.1 2005/02/08 20:41:31 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd new file mode 100644 index 000000000..5547747b2 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: chip-minimal-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration chip_minimal_c0 of chip is + + for minimal + + for spi_boot_b : spi_boot + use configuration work.spi_boot_rtl_c0; + end for; + + end for; + +end chip_minimal_c0; diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd new file mode 100644 index 000000000..cef42d268 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel design with MMC feature set +-- +-- $Id: chip-mmc-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +architecture mmc of chip is + + component spi_boot + generic ( + width_set_sel_g : integer := 4; + width_bit_cnt_g : integer := 6; + width_img_cnt_g : integer := 2; + num_bits_per_img_g : integer := 18; + sd_init_g : integer := 0; + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + signal spi_clk_s : std_logic; + signal spi_cs_n_s : std_logic; + signal spi_data_out_s : std_logic; + signal spi_en_outs_s : std_logic; + + signal set_sel_s : std_logic_vector(3 downto 0); + +begin + + set_sel_s <= not set_sel_n_i; + + spi_boot_b : spi_boot + generic map ( + width_set_sel_g => 4, -- 16 sets + width_bit_cnt_g => 12, -- 512 bytes per block + width_img_cnt_g => 2, -- 4 images + num_bits_per_img_g => 18, -- 256 kByte per image + sd_init_g => 0, -- no SD specific initialization + mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2) + width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + set_sel_i => set_sel_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_in_i, + spi_data_out_o => spi_data_out_s, + spi_en_outs_o => spi_en_outs_s, + start_i => start_i, + mode_i => mode_i, + config_n_o => config_n_o, + detached_o => detached_o, + cfg_init_n_i => cfg_init_n_i, + cfg_done_i => cfg_done_i, + dat_done_i => dat_done_i, + cfg_clk_o => cfg_clk_o, + cfg_dat_o => cfg_dat_o + ); + + ----------------------------------------------------------------------------- + -- Three state drivers for SPI outputs. + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_s + when spi_en_outs_s = '1' else + 'Z'; + spi_cs_n_o <= spi_cs_n_s + when spi_en_outs_s = '1' else + 'Z'; + spi_data_out_o <= spi_data_out_s + when spi_en_outs_s = '1' else + 'Z'; + +end mmc; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-mmc-a.vhd,v $ +-- Revision 1.6 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.5 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.4 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.3 2005/02/18 06:42:13 arniml +-- clarify wording for images +-- +-- Revision 1.2 2005/02/16 18:54:39 arniml +-- added tri-state drivers for spi outputs +-- +-- Revision 1.1 2005/02/08 20:41:32 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd new file mode 100644 index 000000000..6131013e4 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: chip-mmc-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration chip_mmc_c0 of chip is + + for mmc + + for spi_boot_b : spi_boot + use configuration work.spi_boot_rtl_c0; + end for; + + end for; + +end chip_mmc_c0; diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd new file mode 100644 index 000000000..c955a5f3a --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel design with SD feature set +-- +-- $Id: chip-sd-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +architecture sd of chip is + + component spi_boot + generic ( + width_set_sel_g : integer := 4; + width_bit_cnt_g : integer := 6; + width_img_cnt_g : integer := 2; + num_bits_per_img_g : integer := 18; + sd_init_g : integer := 0; + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + signal spi_clk_s : std_logic; + signal spi_cs_n_s : std_logic; + signal spi_data_out_s : std_logic; + signal spi_en_outs_s : std_logic; + + signal set_sel_s : std_logic_vector(3 downto 0); + +begin + + set_sel_s <= not set_sel_n_i; + + spi_boot_b : spi_boot + generic map ( + width_set_sel_g => 4, -- 16 sets + width_bit_cnt_g => 12, -- 512 bytes per block + width_img_cnt_g => 2, -- 4 images + num_bits_per_img_g => 18, -- 256 kByte per image + sd_init_g => 1, -- SD specific initialization + mmc_compat_clk_div_g => 0, -- no MMC compatibility + width_mmc_clk_div_g => 0 -- no MMC compatibility + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + set_sel_i => set_sel_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_in_i, + spi_data_out_o => spi_data_out_s, + spi_en_outs_o => spi_en_outs_s, + start_i => start_i, + mode_i => mode_i, + config_n_o => config_n_o, + detached_o => detached_o, + cfg_init_n_i => cfg_init_n_i, + cfg_done_i => cfg_done_i, + dat_done_i => dat_done_i, + cfg_clk_o => cfg_clk_o, + cfg_dat_o => cfg_dat_o + ); + + ----------------------------------------------------------------------------- + -- Three state drivers for SPI outputs. + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_s + when spi_en_outs_s = '1' else + 'Z'; + spi_cs_n_o <= spi_cs_n_s + when spi_en_outs_s = '1' else + 'Z'; + spi_data_out_o <= spi_data_out_s + when spi_en_outs_s = '1' else + 'Z'; + +end sd; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-sd-a.vhd,v $ +-- Revision 1.6 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.5 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.4 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.3 2005/02/18 06:42:14 arniml +-- clarify wording for images +-- +-- Revision 1.2 2005/02/16 18:54:39 arniml +-- added tri-state drivers for spi outputs +-- +-- Revision 1.1 2005/02/08 20:41:32 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd new file mode 100644 index 000000000..91e41ddfb --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: chip-sd-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration chip_sd_c0 of chip is + + for sd + + for spi_boot_b : spi_boot + use configuration work.spi_boot_rtl_c0; + end for; + + end for; + +end chip_sd_c0; diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries new file mode 100644 index 000000000..552a7baad --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries @@ -0,0 +1,3 @@ +/ram_loader-c.vhd/1.1/Sun Apr 10 18:02:32 2005// +/ram_loader.vhd/1.2/Sun Apr 10 17:17:23 2005// +D diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository new file mode 100644 index 000000000..026a73983 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository @@ -0,0 +1 @@ +spi_boot/rtl/vhdl/sample diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd new file mode 100644 index 000000000..8b26c4d57 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------- +-- $Id: ram_loader-c.vhd,v 1.1 2005/04/10 18:02:32 arniml Exp $ +------------------------------------------------------------------------------- + +configuration ram_loader_rtl_c0 of ram_loader is + + for rtl + end for; + +end ram_loader_rtl_c0; diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd new file mode 100644 index 000000000..c604876d7 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd @@ -0,0 +1,355 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Sample client for loading an image to asynchronous SRAM +-- +-- $Id: ram_loader.vhd,v 1.2 2005/04/10 17:17:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity ram_loader is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + lamp_o : out std_logic; + -- Config Interface ------------------------------------------------------- + cfg_clk_i : in std_logic; + cfg_data_i : in std_logic; + start_o : out std_logic; + mode_o : out std_logic; + done_o : out std_logic; + detached_i : in std_logic; + -- Asynchronous RAM Interface --------------------------------------------- + ram_addr_o : out std_logic_vector(15 downto 0); + ram_data_b : out std_logic_vector( 7 downto 0); + ram_ce_no : out std_logic_vector( 3 downto 0); + ram_oe_no : out std_logic; + ram_we_no : out std_logic + ); + +end ram_loader; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ram_loader is + + signal addr_q : unsigned(17 downto 0); + signal inc_addr_s : boolean; + + signal shift_dat_q : std_logic_vector(7 downto 0); + signal ser_dat_q : std_logic_vector(7 downto 0); + signal bit_q : unsigned(2 downto 0); + signal bit_ovfl_q : boolean; + + type fsm_t is (IDLE, + WE_ON, + WE_OFF, + INC_ADDR1, INC_ADDR2, + FINISHED); + signal fsm_s, + fsm_q : fsm_t; + signal done_q : std_logic; + signal done_s : boolean; + signal mode_q, + mode_s : std_logic; + + signal ram_we_n_q, + ram_we_n_s : std_logic; + signal ram_ce_n_q, + ram_ce_n_s : std_logic_vector(3 downto 0); + + type start_fsm_t is (WAIT_DETACH, + CHECK_NO_DONE, + WAIT_DONE); + signal start_fsm_s, + start_fsm_q : start_fsm_t; + + signal start_s, + start_q : std_logic; + signal enable_s, + enable_q : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements clocked with cfg_clk_i. + -- + seq: process (cfg_clk_i, reset_i) + begin + if reset_i = '0' then + addr_q <= (others => '0'); + shift_dat_q <= (others => '0'); + ser_dat_q <= (others => '0'); + bit_q <= (others => '0'); + bit_ovfl_q <= false; + fsm_q <= IDLE; + ram_we_n_q <= '1'; + ram_ce_n_q <= (others => '1'); + done_q <= '0'; + mode_q <= '0'; + + elsif cfg_clk_i'event and cfg_clk_i = '1' then + if inc_addr_s then + addr_q <= addr_q + 1; + end if; + + if enable_q then + bit_q <= bit_q + 1; + bit_ovfl_q <= bit_q = 7; + + shift_dat_q(0) <= cfg_data_i; + shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0); + end if; + + -- update register when 8 serial bits have been shifted in + if bit_ovfl_q then + ser_dat_q <= shift_dat_q; + end if; + + fsm_q <= fsm_s; + + ram_we_n_q <= ram_we_n_s; + ram_ce_n_q <= ram_ce_n_s; + + -- done only settable once + if done_s then + done_q <= '1'; + end if; + + mode_q <= mode_s; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process fsm + -- + -- Purpose: + -- Implements the combinational logic of the RAM loader FSM. + -- + fsm: process (fsm_q, + bit_ovfl_q, + start_q, + addr_q) + begin + -- default assignments + inc_addr_s <= false; + ram_we_n_s <= '1'; + done_s <= false; + fsm_s <= IDLE; + lamp_o <= '1'; + mode_s <= '0'; + + case fsm_q is + when IDLE => + lamp_o <= '0'; + if start_q = '1' then + if bit_ovfl_q then + fsm_s <= WE_ON; + end if; + end if; + + when WE_ON => + ram_we_n_s <= '0'; + fsm_s <= WE_OFF; + + when WE_OFF => + fsm_s <= INC_ADDR1; + + when INC_ADDR1 => + fsm_s <= INC_ADDR2; + + when INC_ADDR2 => + if addr_q = "001111111111111111" then -- load only 64k + fsm_s <= FINISHED; + done_s <= true; + mode_s <= '1'; + else + inc_addr_s <= true; + fsm_s <= IDLE; + end if; + + when FINISHED => + fsm_s <= FINISHED; + lamp_o <= '1'; + mode_s <= '1'; + + when others => + end case; + + end process fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ce_gen + -- + -- Purpose: + -- Generates the four CE signals for the external RAM chips. + -- + ce_gen: process (addr_q) + begin + ram_ce_n_s <= (others => '1'); + ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0'; + end process ce_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process start_seq + -- + -- Purpose: + -- Implements the sequential elements clocked with clk_i. + -- + start_seq: process (clk_i, reset_i) + begin + if reset_i = '0' then + start_fsm_q <= WAIT_DETACH; + start_q <= '0'; + enable_q <= false; + + elsif clk_i'event and clk_i = '1' then + start_fsm_q <= start_fsm_s; + + enable_q <= enable_s; + + start_q <= start_s; + + end if; + end process start_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process start_comb + -- + -- Purpose: + -- Implements the combinational logic of the start FSM. + -- + start_comb: process (start_fsm_q, + detached_i, + done_q, + enable_q, + start_q) + begin + -- default assignments + start_fsm_s <= WAIT_DETACH; + enable_s <= enable_q; + start_s <= start_q; + + case start_fsm_q is + -- Wait for detached_i to become '1' + -- This state is entered/left twice: + -- 1. after reset to start the data download + -- 2. after data download to start the next configuration cycle + when WAIT_DETACH => + if detached_i = '1' then + start_fsm_s <= CHECK_NO_DONE; + enable_s <= true; + start_s <= '1'; + + else + start_fsm_s <= WAIT_DETACH; + end if; + + -- Wait until done_q is '0' + -- This ensures that the FSM stalls when it has started the configuration + -- download. There must be no further action in this case. + when CHECK_NO_DONE => + if done_q = '0' then + start_fsm_s <= WAIT_DONE; + else + start_fsm_s <= CHECK_NO_DONE; + end if; + + -- Wait until done_q is '1' + -- done_q is the signal that the main FSM has finished its work. We + -- need to start the configuration download. + when WAIT_DONE => + if done_q = '1' then + start_fsm_s <= WAIT_DETACH; + enable_s <= false; + start_s <= '0'; + else + start_fsm_s <= WAIT_DONE; + end if; + + when others => + null; + + end case; + + end process start_comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + start_o <= start_q; + mode_o <= mode_q; + done_o <= done_q + when start_q = '1' else + '1'; + ram_addr_o <= std_logic_vector(addr_q(15 downto 0)); + ram_data_b <= ser_dat_q; + ram_oe_no <= '1'; + ram_ce_no <= ram_ce_n_q; + ram_we_no <= ram_we_n_q; + +end rtl; diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd new file mode 100644 index 000000000..6f11ed34b --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd @@ -0,0 +1,27 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: spi_boot-c.vhd,v 1.2 2005/02/18 06:42:11 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration spi_boot_rtl_c0 of spi_boot is + + for rtl + + for img_cnt + for img_cnt_b : spi_counter + use configuration work.spi_counter_rtl_c0; + end for; + end for; + + for mmc_cnt + for mmc_cnt_b : spi_counter + use configuration work.spi_counter_rtl_c0; + end for; + end for; + + end for; + +end spi_boot_rtl_c0; diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd new file mode 100644 index 000000000..3d2b81da7 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd @@ -0,0 +1,979 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity spi_boot is + + generic ( + -- width of set selection + width_set_sel_g : integer := 4; + -- width of bit counter: minimum 6, maximum 12 + width_bit_cnt_g : integer := 6; + -- width of image counter: minimum 0, maximum n + width_img_cnt_g : integer := 2; + -- number of bits required to address one image + num_bits_per_img_g : integer := 18; + -- SD specific initialization + sd_init_g : integer := 0; + -- clock divider to reach 400 kHz for MMC compatibility + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + -- active level of reset_i + reset_level_g : integer := 0 + ); + + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + -- Card Interface --------------------------------------------------------- + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + -- FPGA Configuration Interface ------------------------------------------- + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + +end spi_boot; + + +library ieee; +use ieee.numeric_std.all; +use work.spi_boot_pack.all; + +architecture rtl of spi_boot is + + component spi_counter + generic ( + cnt_width_g : integer := 4; + cnt_max_g : integer := 15 + ); + port ( + clk_i : in std_logic; + reset_i : in boolean; + cnt_en_i : in boolean; + cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); + cnt_ovfl_o : out boolean + ); + end component; + + + ----------------------------------------------------------------------------- + -- States of the controller FSM + -- + type ctrl_states_t is (POWER_UP1, POWER_UP2, + CMD0, + CMD1, + CMD55, ACMD41, + CMD16, + WAIT_START, + WAIT_INIT_LOW, WAIT_INIT_HIGH, + CMD18, CMD18_DATA, + CMD12, + INC_IMG_CNT); + -- + signal ctrl_fsm_q, + ctrl_fsm_s : ctrl_states_t; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- States of the command FSM + -- + type cmd_states_t is (CMD, START, R1, PAUSE); + -- + signal cmd_fsm_q, + cmd_fsm_s : cmd_states_t; + -- + ----------------------------------------------------------------------------- + + subtype op_r is integer range 5 downto 0; + type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7); + signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0); + signal res_bc_s : res_bc_t; + signal upper_bitcnt_zero_s : boolean; + + signal cfg_dat_q : std_logic; + + signal spi_clk_q : std_logic; + signal spi_clk_rising_q : boolean; + signal spi_clk_falling_q : boolean; + signal spi_dat_q, + spi_dat_s : std_logic; + signal spi_cs_n_q, + spi_cs_n_s : std_logic; + + signal cfg_clk_q : std_logic; + + signal start_q : std_logic; + + signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0); + signal cnt_en_img_s : boolean; + signal mmc_cnt_ovfl_s : boolean; + signal mmc_compat_s : boolean; + + signal cmd_finished_s : boolean; + + signal r1_result_q : std_logic; + signal done_q, + send_cmd12_q : boolean; + + signal en_outs_s, + en_outs_q : boolean; + + signal reset_s : boolean; + + signal true_s : boolean; + +begin + + true_s <= true; + + reset_s <= true + when (reset_level_g = 1 and reset_i = '1') or + (reset_level_g = 0 and reset_i = '0') else + false; + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements several sequential elements. + -- + seq: process (clk_i, reset_s) + + variable bit_cnt_v : unsigned(1 downto 0); + + begin + if reset_s then + -- reset bit counter to 63 for power up + bit_cnt_q <= (others => '0'); + bit_cnt_q(op_r) <= "111111"; + spi_dat_q <= '1'; + spi_cs_n_q <= '1'; + cfg_dat_q <= '1'; + start_q <= '0'; + done_q <= false; + send_cmd12_q <= false; + ctrl_fsm_q <= POWER_UP1; + cmd_fsm_q <= CMD; + r1_result_q <= '0'; + en_outs_q <= false; + + elsif clk_i'event and clk_i = '1' then + -- bit counter control + if spi_clk_rising_q then + case res_bc_s is + when NONE => + bit_cnt_q <= bit_cnt_q - 1; + when RES_MAX => + bit_cnt_q <= (others => '1'); + when RES_47 => + bit_cnt_q <= (others => '0'); + bit_cnt_q(op_r) <= "101111"; + when RES_15 => + bit_cnt_q <= (others => '0'); + bit_cnt_q(op_r) <= "001111"; + when RES_7 => + bit_cnt_q <= (others => '0'); + bit_cnt_q(op_r) <= "000111"; + when others => + bit_cnt_q <= (others => '0'); + end case; + end if; + + -- Card data output register + -- spi_clk_falling_q acts as enable during MMC clock compatibility mode. + -- As soon as this mode is left, the register must start latching. + -- There is no explicit relation to spi_clk_q anymore in normal mode. + -- Instead, spi_dat_s is operated by bit_cnt_q above which changes its + -- value after the rising edge of spi_clk_q. + -- -> spi_dat_q changes upon falling edge of spi_clk_q + if spi_clk_falling_q or not mmc_compat_s then + spi_dat_q <= spi_dat_s; + end if; + + -- config data output register + -- a new value is loaded when config clock is high, + -- i.e. input data is sampled with rising spi_clk + -- while output value changes on falling edge of cfg_clk + if cfg_clk_q = '1' and spi_clk_rising_q then + cfg_dat_q <= spi_data_in_i; + end if; + + -- Controller FSM state + ctrl_fsm_q <= ctrl_fsm_s; + + -- Command FSM state + cmd_fsm_q <= cmd_fsm_s; + + -- CS signal for SPI card + if spi_clk_q = '1' then + spi_cs_n_q <= spi_cs_n_s; + end if; + + -- Extract flags from R1 response + if cmd_fsm_q = R1 then + bit_cnt_v := bit_cnt_q(1 downto 0); + case bit_cnt_v(1 downto 0) is + when "10" => + -- always save "Illegal Command" flag + r1_result_q <= to_X01(spi_data_in_i); + when "00" => + -- overwrite with "Idle State" flag when not in CMD55 + if ctrl_fsm_q /= CMD55 then + r1_result_q <= to_X01(spi_data_in_i); + end if; + when others => + null; + end case; + end if; + + -- Start trigger register for rising edge detection + -- the reset value is '0' thus a rising edge will always be detected + -- after reset even though start_i is tied to '1' + if start_i = '0' then + start_q <= '0'; + elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then + start_q <= start_i; + end if; + + -- Marker for cfg_done and dat_done + if ctrl_fsm_q = CMD18_DATA then + if cfg_done_i = '1' and dat_done_i = '1' then + done_q <= true; + end if; + + if done_q and + (not upper_bitcnt_zero_s or cmd_fsm_q = START) then + -- activate sending of CMD12 when it is safe: + -- * upper bits of bit counter are not zero + -- -> transmission of CMD12 is not running + -- * cmd FSM is in START state + -- -> also no transmission running + send_cmd12_q <= true; + end if; + elsif ctrl_fsm_q = WAIT_START then + -- reset done_q when WAIT_START has been reached + -- this is necessary to let the stop transmission process come to + -- an end without interruption or generation of unwanted cfg_clk_q + done_q <= false; + send_cmd12_q <= false; + end if; + + -- output enable + if spi_clk_rising_q then + en_outs_q <= en_outs_s; + end if; + + end if; + + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process upper_bits + -- + -- Purpose: + -- Detects that the upper bits of the bit counter are zero. + -- Upper bits = n downto 6, i.e. the optional part that is not required for + -- commands but for extension of data blocks. + -- + upper_bits: process (bit_cnt_q) + variable zero_v : boolean; + begin + + zero_v := true; + for i in bit_cnt_q'high downto 6 loop + if bit_cnt_q(i) = '1' then + zero_v := false; + end if; + end loop; + + upper_bitcnt_zero_s <= zero_v; + + end process upper_bits; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process clk_gen + -- + -- Purpose: + -- Generates clocks for card and FPGA configuration. + -- The card clock is free running with a divide by two of clk_i. + -- The clock for FPGA config has an enable and is stopped on high level. + -- There is a phase shift of half a period between spi_clk and cfg_clk. + -- + clk_gen: process (clk_i, reset_s) + begin + if reset_s then + spi_clk_q <= '0'; + cfg_clk_q <= '1'; + + elsif clk_i'event and clk_i = '1' then + + -- spi_clk_q rises according to the flag + -- it falls with overflow indication + -- the resulting duty cycle is not exactly 50:50, + -- high time is a bit longer + if mmc_compat_s then + -- MMC clock compatibility mode: + -- spi_clk_q rises when flagged by spi_clk_rising_q + if spi_clk_rising_q then + spi_clk_q <= '1'; + elsif mmc_cnt_ovfl_s then + -- upon counter overflow spi_clk_q falls in case it does not rise + spi_clk_q <= '0'; + end if; + else + -- normal mode + -- spi_clk_q follows spi_clk_rising_q + if spi_clk_rising_q then + spi_clk_q <= '1'; + else + spi_clk_q <= '0'; + end if; + end if; + + -- clock for FPGA config must be enabled and follows spi_clk + if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and + not done_q then + cfg_clk_q <= spi_clk_q; + else + cfg_clk_q <= '1'; + end if; + + end if; + + end process clk_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Indication flags for rising and falling spi_clk_q. + -- Essential for MMC clock compatibility mode. + ----------------------------------------------------------------------------- + mmc_comap: if mmc_compat_clk_div_g > 0 generate + mmc_compat_sig: process (clk_i, reset_s) + begin + if reset_s then + spi_clk_rising_q <= false; + spi_clk_falling_q <= false; + + elsif clk_i'event and clk_i = '1' then + if mmc_compat_s then + -- MMC clock compatibility mode: + -- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q + -- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q + if mmc_cnt_ovfl_s then + spi_clk_rising_q <= spi_clk_q = '0'; + spi_clk_falling_q <= spi_clk_q = '1'; + else + spi_clk_rising_q <= false; + spi_clk_falling_q <= false; + end if; + else + -- normal mode + spi_clk_rising_q <= not spi_clk_rising_q; + spi_clk_falling_q <= true; + end if; + + end if; + end process mmc_compat_sig; + end generate; + + no_mmc_compat: if mmc_compat_clk_div_g = 0 generate + -- SPI clock rising whenever spi_clk_q is '0' + spi_clk_rising_q <= spi_clk_q = '0'; + -- SPI clock falling whenever spi_clk_q is '1' + spi_clk_falling_q <= spi_clk_q = '1'; + end generate; + + + ----------------------------------------------------------------------------- + -- Process ctrl_fsm + -- + -- Purpose: + -- Implements the controller FSM. + -- + ctrl_fsm: process (ctrl_fsm_q, + cmd_finished_s, r1_result_q, + start_i, start_q, mode_i, + cfg_init_n_i) + + variable mmc_compat_v : boolean; + + begin + -- default assignments + ctrl_fsm_s <= POWER_UP1; + config_n_o <= '1'; + cnt_en_img_s <= false; + spi_cs_n_s <= '0'; + mmc_compat_v := false; + en_outs_s <= true; + + case ctrl_fsm_q is + -- Let card finish power up, step 1 ------------------------------------- + when POWER_UP1 => + mmc_compat_v := true; + spi_cs_n_s <= '1'; + if cmd_finished_s then + ctrl_fsm_s <= POWER_UP2; + else + ctrl_fsm_s <= POWER_UP1; + end if; + + + -- Let card finish power up, step 2 ------------------------------------- + when POWER_UP2 => + mmc_compat_v := true; + if cmd_finished_s then + ctrl_fsm_s <= CMD0; + else + spi_cs_n_s <= '1'; + ctrl_fsm_s <= POWER_UP2; + end if; + + + -- Issue CMD0: GO_IDLE_STATE -------------------------------------------- + when CMD0 => + mmc_compat_v := true; + if cmd_finished_s then + if sd_init_g = 1 then + ctrl_fsm_s <= CMD55; + else + ctrl_fsm_s <= CMD1; + end if; + else + ctrl_fsm_s <= CMD0; + end if; + + + -- Issue CMD55: APP_CMD ------------------------------------------------- + when CMD55 => + if sd_init_g = 1 then + + mmc_compat_v := true; + if cmd_finished_s then + if r1_result_q = '0' then + -- command accepted, it's an SD card + ctrl_fsm_s <= ACMD41; + else + -- command rejected, it's an MMC card + ctrl_fsm_s <= CMD1; + end if; + else + ctrl_fsm_s <= CMD55; + end if; + + end if; + + + -- Issue ACMD41: SEND_OP_COND ------------------------------------------- + when ACMD41 => + if sd_init_g = 1 then + + mmc_compat_v := true; + if cmd_finished_s then + if r1_result_q = '0' then + ctrl_fsm_s <= CMD16; + else + ctrl_fsm_s <= CMD55; + end if; + else + ctrl_fsm_s <= ACMD41; + end if; + + end if; + + + -- Issue CMD1: SEND_OP_COND --------------------------------------------- + when CMD1 => + mmc_compat_v := true; + if cmd_finished_s then + if r1_result_q = '0' then + ctrl_fsm_s <= CMD16; + else + ctrl_fsm_s <= CMD1; + end if; + else + ctrl_fsm_s <= CMD1; + end if; + + + -- Issue CMD16: SET_BLOCKLEN -------------------------------------------- + when CMD16 => + if cmd_finished_s then + ctrl_fsm_s <= WAIT_START; + else + ctrl_fsm_s <= CMD16; + end if; + + + -- Wait for configuration start request --------------------------------- + when WAIT_START => + spi_cs_n_s <= '1'; + + -- detect rising edge of start_i + if start_i = '1' and start_q = '0' then + -- decide which mode is requested + if cmd_finished_s then + if mode_i = '0' then + ctrl_fsm_s <= CMD18; + else + ctrl_fsm_s <= WAIT_INIT_LOW; + end if; + else + en_outs_s <= false; + ctrl_fsm_s <= WAIT_START; + end if; + else + en_outs_s <= false; + ctrl_fsm_s <= WAIT_START; + end if; + + + -- Wait for INIT to become low ------------------------------------------ + when WAIT_INIT_LOW => + spi_cs_n_s <= '1'; + -- activate FPGA configuration + config_n_o <= '0'; + + if cfg_init_n_i = '0' then + ctrl_fsm_s <= WAIT_INIT_HIGH; + else + ctrl_fsm_s <= WAIT_INIT_LOW; + end if; + + + -- Wait for INIT to become high ----------------------------------------- + when WAIT_INIT_HIGH => + spi_cs_n_s <= '1'; + + if cfg_init_n_i = '1' and cmd_finished_s then + ctrl_fsm_s <= CMD18; + else + ctrl_fsm_s <= WAIT_INIT_HIGH; + end if; + + + -- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------ + when CMD18 => + if cmd_finished_s then + ctrl_fsm_s <= CMD18_DATA; + else + ctrl_fsm_s <= CMD18; + end if; + -- + -- receive a data block + when CMD18_DATA => + if cmd_finished_s then + ctrl_fsm_s <= CMD12; + else + ctrl_fsm_s <= CMD18_DATA; + end if; + + + -- Issued CMD12: STOP_TRANSMISSION -------------------------------------- + when CMD12 => + if cmd_finished_s then + ctrl_fsm_s <= INC_IMG_CNT; + else + ctrl_fsm_s <= CMD12; + end if; + + + -- Increment Image Counter ---------------------------------------------- + when INC_IMG_CNT => + spi_cs_n_s <= '1'; + ctrl_fsm_s <= WAIT_START; + cnt_en_img_s <= true; + + + + when others => + null; + + end case; + + -- mmc_compat_s is suppressed if MMC clock compatibility is not required + if mmc_compat_clk_div_g > 0 then + mmc_compat_s <= mmc_compat_v; + else + mmc_compat_s <= false; + end if; + + end process ctrl_fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cmd_fsm + -- + -- Purpose: + -- Implements the command FSM. + -- + cmd_fsm: process (spi_clk_rising_q, + spi_data_in_i, + bit_cnt_q, + ctrl_fsm_q, + cmd_fsm_q, + send_cmd12_q) + + variable cnt_zero_v : boolean; + variable spi_data_low_v : boolean; + variable no_startbit_v : boolean; + + begin + -- default assignments + cmd_finished_s <= false; + cmd_fsm_s <= CMD; + res_bc_s <= NONE; + + cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0; + spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0'; + + -- these are no real commands thus there will be no startbit + case ctrl_fsm_q is + when POWER_UP1 | POWER_UP2 | + WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW => + no_startbit_v := true; + when others => + no_startbit_v := false; + end case; + + + case cmd_fsm_q is + -- Send the command ----------------------------------------------------- + when CMD => + if cnt_zero_v then + if ctrl_fsm_q /= CMD18_DATA then + -- normal commands including CMD12 require startbit of R1 response + cmd_fsm_s <= START; + else + if not send_cmd12_q then + -- CMD18_DATA needs to read CRC + cmd_fsm_s <= R1; + res_bc_s <= RES_15; + else + -- CMD18_DATA finished, scan for startbit of response + cmd_finished_s <= true; + cmd_fsm_s <= START; + end if; + end if; + else + cmd_fsm_s <= CMD; + end if; + + -- Wait for startbit of response ---------------------------------------- + when START => + -- startbit detection or skip of this check + if no_startbit_v and spi_clk_rising_q then + cmd_fsm_s <= R1; + res_bc_s <= RES_7; + elsif spi_data_low_v then + if ctrl_fsm_q /= CMD18_DATA then + cmd_fsm_s <= R1; + else + -- CMD18_DATA startbit detected, read payload + cmd_fsm_s <= CMD; + res_bc_s <= RES_MAX; + end if; + else + cmd_fsm_s <= START; + res_bc_s <= RES_7; + end if; + + -- Read R1 response ----------------------------------------------------- + when R1 => + if cnt_zero_v then + res_bc_s <= RES_7; + + if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then + cmd_fsm_s <= PAUSE; + else + -- CMD18 needs another startbit detection for the data token. + -- CMD18_DATA needs a startbit after having received the CRC, either + -- * next data token + -- * R1 response of CMD12 + cmd_fsm_s <= START; + + if ctrl_fsm_q = CMD18 then + -- CMD18 response received -> advance to CMD18_DATA + cmd_finished_s <= true; + end if; + end if; + else + cmd_fsm_s <= R1; + end if; + + -- PAUSE state -> required for Nrc, card response to host command ------- + when PAUSE => + if cnt_zero_v then + cmd_fsm_s <= CMD; + res_bc_s <= RES_47; + cmd_finished_s <= true; + else + cmd_fsm_s <= PAUSE; + end if; + + when others => + null; + + end case; + + end process cmd_fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process transmit + -- + -- Purpose: + -- Generates the serial data output values based on the current FSM state + -- + -- The local variable cmd_v is 64 bits wide in contrast to an SPI command + -- with 48 bits. There are two reasons for this: + -- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit + -- counter will start from 3F on its lowest 6 bits. Therefore, it is + -- necessary to provide all 64 positions in cmd_v. + -- * Reduces logic. + -- + transmit: process (ctrl_fsm_q, + cmd_fsm_q, + bit_cnt_q, + img_cnt_s, + send_cmd12_q, + set_sel_i, + upper_bitcnt_zero_s) + + subtype cmd_r is natural range 47 downto 0; + subtype cmd_t is std_logic_vector(cmd_r); + subtype ext_cmd_t is std_logic_vector(63 downto 0); + -- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS + constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101"; + constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1"; + constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1"; + constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1"; + constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1"; + constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1"; + constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1"; + + variable cmd_v : ext_cmd_t; + variable tx_v : boolean; + + begin + -- default assignments + spi_dat_s <= '1'; + cmd_v := (others => '1'); + tx_v := false; + + if cmd_fsm_q = CMD then + case ctrl_fsm_q is + when CMD0 => + cmd_v(cmd_r) := cmd0_c; + tx_v := true; + when CMD1 => + cmd_v(cmd_r) := cmd1_c; + tx_v := true; + when CMD16 => + cmd_v(cmd_r) := cmd16_c; + cmd_v(8 + width_bit_cnt_g-3) := '1'; + tx_v := true; + when CMD18 => + cmd_v(cmd_r) := cmd18_c; + -- insert image counter + cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + downto 8 + num_bits_per_img_g) := img_cnt_s; + -- insert set selection + cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1 + downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i; + tx_v := true; + when CMD18_DATA => + cmd_v(cmd_r) := cmd12_c; + + if send_cmd12_q and upper_bitcnt_zero_s then + tx_v := true; + end if; + when CMD55 => + cmd_v(cmd_r) := cmd55_c; + tx_v := true; + when ACMD41 => + cmd_v(cmd_r) := acmd41_c; + tx_v := true; + + when others => + null; + end case; + end if; + + if tx_v then + spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0))); + end if; + + end process transmit; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Optional Image Counter + ----------------------------------------------------------------------------- + img_cnt: if width_img_cnt_g > 0 generate + img_cnt_b : spi_counter + generic map ( + cnt_width_g => width_img_cnt_g, + cnt_max_g => 2**width_img_cnt_g - 1 + ) + port map ( + clk_i => clk_i, + reset_i => reset_s, + cnt_en_i => cnt_en_img_s, + cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0), + cnt_ovfl_o => open + ); + img_cnt_s(width_img_cnt_g) <= '0'; + end generate; + + no_img_cnt: if width_img_cnt_g = 0 generate + img_cnt_s <= (others => '0'); + end generate; + + + ----------------------------------------------------------------------------- + -- Optional MMC compatibility counter + ----------------------------------------------------------------------------- + mmc_cnt: if mmc_compat_clk_div_g > 0 generate + mmc_cnt_b : spi_counter + generic map ( + cnt_width_g => width_mmc_clk_div_g, + cnt_max_g => mmc_compat_clk_div_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_s, + cnt_en_i => true_s, + cnt_o => open, + cnt_ovfl_o => mmc_cnt_ovfl_s + ); + end generate; + + no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate + mmc_cnt_ovfl_s <= true; + end generate; + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_q; + spi_cs_n_o <= spi_cs_n_q; + spi_data_out_o <= spi_dat_q; + spi_en_outs_o <= '1' + when en_outs_q else + '0'; + cfg_clk_o <= cfg_clk_q; + cfg_dat_o <= cfg_dat_q; + detached_o <= '0' + when en_outs_q else + '1'; + +end rtl; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: spi_boot.vhd,v $ +-- Revision 1.9 2007/02/25 18:24:12 arniml +-- fix type handling of resets +-- +-- Revision 1.8 2006/09/11 23:03:36 arniml +-- disable outputs with reset +-- +-- Revision 1.7 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.6 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.5 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.4 2005/02/18 06:42:08 arniml +-- clarify wording for images +-- +-- Revision 1.3 2005/02/16 18:59:10 arniml +-- include output enable control for SPI outputs +-- +-- Revision 1.2 2005/02/13 17:25:51 arniml +-- major update to fix several problems +-- configuration/data download of multiple sets works now +-- +-- Revision 1.1 2005/02/08 20:41:33 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd new file mode 100644 index 000000000..ac8b544f9 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: spi_boot_pack-p.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package spi_boot_pack is + + function "=" (a : std_logic; b : integer) return boolean; + +end spi_boot_pack; + +package body spi_boot_pack is + + function "=" (a : std_logic; b : integer) return boolean is + variable result_v : boolean; + begin + result_v := false; + + case a is + when '0' => + if b = 0 then + result_v := true; + end if; + + when '1' => + if b = 1 then + result_v := true; + end if; + + when others => + null; + + end case; + + return result_v; + end; + +end spi_boot_pack; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: spi_boot_pack-p.vhd,v $ +-- Revision 1.1 2005/02/08 20:41:33 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd new file mode 100644 index 000000000..d81e20db6 --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd @@ -0,0 +1,14 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: spi_counter-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration spi_counter_rtl_c0 of spi_counter is + + for rtl + end for; + +end spi_counter_rtl_c0; diff --git a/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd new file mode 100644 index 000000000..8ec7357ea --- /dev/null +++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd @@ -0,0 +1,118 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Generic counter module +-- +-- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity spi_counter is + + generic ( + cnt_width_g : integer := 4; + cnt_max_g : integer := 15 + ); + + port ( + clk_i : in std_logic; + reset_i : in boolean; + cnt_en_i : in boolean; + cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); + cnt_ovfl_o : out boolean + ); + +end spi_counter; + + +library ieee; +use ieee.numeric_std.all; +use work.spi_boot_pack.all; + +architecture rtl of spi_counter is + + signal cnt_q : unsigned(cnt_width_g-1 downto 0); + signal cnt_ovfl_s : boolean; + +begin + + cnt: process (clk_i, reset_i) + begin + if reset_i then + cnt_q <= (others => '0'); + + elsif clk_i'event and clk_i = '1' then + if cnt_en_i then + if not cnt_ovfl_s then + cnt_q <= cnt_q + 1; + else + cnt_q <= (others => '0'); + end if; + end if; + end if; + end process cnt; + + cnt_ovfl_s <= cnt_q = cnt_max_g; + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + cnt_ovfl_o <= cnt_ovfl_s; + cnt_o <= std_logic_vector(cnt_q); + +end rtl; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: spi_counter.vhd,v $ +-- Revision 1.2 2007/02/25 18:24:12 arniml +-- fix type handling of resets +-- +-- Revision 1.1 2005/02/08 20:41:33 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/opencores/spi_boot/sim/CVS/Entries b/usrp2/opencores/spi_boot/sim/CVS/Entries new file mode 100644 index 000000000..9487498ad --- /dev/null +++ b/usrp2/opencores/spi_boot/sim/CVS/Entries @@ -0,0 +1 @@ +D/rtl_sim//// diff --git a/usrp2/opencores/spi_boot/sim/CVS/Repository b/usrp2/opencores/spi_boot/sim/CVS/Repository new file mode 100644 index 000000000..4e2e09740 --- /dev/null +++ b/usrp2/opencores/spi_boot/sim/CVS/Repository @@ -0,0 +1 @@ +spi_boot/sim diff --git a/usrp2/opencores/spi_boot/sim/CVS/Root b/usrp2/opencores/spi_boot/sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/sim/CVS/Template b/usrp2/opencores/spi_boot/sim/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries new file mode 100644 index 000000000..e3d0dc145 --- /dev/null +++ b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries @@ -0,0 +1,2 @@ +/Makefile/1.2/Sun Apr 10 18:14:19 2005// +D diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository new file mode 100644 index 000000000..114ab862f --- /dev/null +++ b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository @@ -0,0 +1 @@ +spi_boot/sim/rtl_sim diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile b/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile new file mode 100644 index 000000000..46fb3c635 --- /dev/null +++ b/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile @@ -0,0 +1,159 @@ +############################################################################## +# +# Makefile for the spi_boot project. +# +# The dependencies for all VHDL source files are stored here. +# +# Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +# +# All rights reserved +# +############################################################################## + + +PROJECT_DIR = ../.. +RTL_DIR = $(PROJECT_DIR)/rtl/vhdl +BENCH_DIR = $(PROJECT_DIR)/bench/vhdl + + + +ANALYZE=ghdl -a --std=87 --workdir=work +ELABORATE=ghdl -e --std=87 --workdir=work + +.PHONY: all +all: work elaborate + +work: + mkdir work + +work/spi_boot_pack-p.o: $(RTL_DIR)/spi_boot_pack-p.vhd + $(ANALYZE) $(RTL_DIR)/spi_boot_pack-p.vhd + +work/spi_counter.o: $(RTL_DIR)/spi_counter.vhd \ + work/spi_boot_pack-p.o + $(ANALYZE) $(RTL_DIR)/spi_counter.vhd +work/spi_counter-c.o: $(RTL_DIR)/spi_counter-c.vhd \ + work/spi_counter.o + $(ANALYZE) $(RTL_DIR)/spi_counter-c.vhd + +work/spi_boot.o: $(RTL_DIR)/spi_boot.vhd \ + work/spi_boot_pack-p.o + $(ANALYZE) $(RTL_DIR)/spi_boot.vhd +work/spi_boot-c.o: $(RTL_DIR)/spi_boot-c.vhd \ + work/spi_boot.o \ + work/spi_counter-c.o + $(ANALYZE) $(RTL_DIR)/spi_boot-c.vhd + +work/chip-e.o: $(RTL_DIR)/chip-e.vhd + $(ANALYZE) $(RTL_DIR)/chip-e.vhd + +work/chip-full-a.o: $(RTL_DIR)/chip-full-a.vhd \ + work/chip-e.o + $(ANALYZE) $(RTL_DIR)/chip-full-a.vhd +work/chip-full-c.o: $(RTL_DIR)/chip-full-c.vhd \ + work/chip-full-a.o \ + work/spi_boot-c.o + $(ANALYZE) $(RTL_DIR)/chip-full-c.vhd + +work/chip-mmc-a.o: $(RTL_DIR)/chip-mmc-a.vhd \ + work/chip-e.o + $(ANALYZE) $(RTL_DIR)/chip-mmc-a.vhd +work/chip-mmc-c.o: $(RTL_DIR)/chip-mmc-c.vhd \ + work/chip-mmc-a.o \ + work/spi_boot-c.o + $(ANALYZE) $(RTL_DIR)/chip-mmc-c.vhd + +work/chip-sd-a.o: $(RTL_DIR)/chip-sd-a.vhd \ + work/chip-e.o + $(ANALYZE) $(RTL_DIR)/chip-sd-a.vhd +work/chip-sd-c.o: $(RTL_DIR)/chip-sd-c.vhd \ + work/chip-sd-a.o \ + work/spi_boot-c.o + $(ANALYZE) $(RTL_DIR)/chip-sd-c.vhd + +work/chip-minimal-a.o: $(RTL_DIR)/chip-minimal-a.vhd \ + work/chip-e.o + $(ANALYZE) $(RTL_DIR)/chip-minimal-a.vhd +work/chip-minimal-c.o: $(RTL_DIR)/chip-minimal-c.vhd \ + work/chip-minimal-a.o \ + work/spi_boot-c.o + $(ANALYZE) $(RTL_DIR)/chip-minimal-c.vhd + +work/ram_loader.o: $(RTL_DIR)/sample/ram_loader.vhd + $(ANALYZE) $(RTL_DIR)/sample/ram_loader.vhd +work/ram_loader-c.o: $(RTL_DIR)/sample/ram_loader-c.vhd \ + work/ram_loader.o + $(ANALYZE) $(RTL_DIR)/sample/ram_loader-c.vhd + +work/tb_pack-p.o: $(BENCH_DIR)/tb_pack-p.vhd + $(ANALYZE) $(BENCH_DIR)/tb_pack-p.vhd + +work/card.o: $(BENCH_DIR)/card.vhd \ + work/tb_pack-p.o + $(ANALYZE) $(BENCH_DIR)/card.vhd +work/card-c.o: $(BENCH_DIR)/card-c.vhd \ + work/card.o + $(ANALYZE) $(BENCH_DIR)/card-c.vhd + +work/tb_elem.o: $(BENCH_DIR)/tb_elem.vhd \ + work/spi_boot_pack-p.o \ + work/tb_pack-p.o + $(ANALYZE) $(BENCH_DIR)/tb_elem.vhd +work/tb_elem-full-c.o: $(BENCH_DIR)/tb_elem-full-c.vhd \ + work/tb_elem.o \ + work/chip-full-c.o \ + work/card-c.o + $(ANALYZE) $(BENCH_DIR)/tb_elem-full-c.vhd +work/tb_elem-mmc-c.o: $(BENCH_DIR)/tb_elem-mmc-c.vhd \ + work/tb_elem.o \ + work/chip-mmc-c.o \ + work/card-c.o + $(ANALYZE) $(BENCH_DIR)/tb_elem-mmc-c.vhd +work/tb_elem-sd-c.o: $(BENCH_DIR)/tb_elem-sd-c.vhd \ + work/tb_elem.o \ + work/chip-sd-c.o \ + work/card-c.o + $(ANALYZE) $(BENCH_DIR)/tb_elem-sd-c.vhd +work/tb_elem-minimal-c.o: $(BENCH_DIR)/tb_elem-minimal-c.vhd \ + work/tb_elem.o \ + work/chip-minimal-c.o \ + work/card-c.o + $(ANALYZE) $(BENCH_DIR)/tb_elem-minimal-c.vhd + +work/tb.o: $(BENCH_DIR)/tb.vhd + $(ANALYZE) $(BENCH_DIR)/tb.vhd +work/tb-c.o: $(BENCH_DIR)/tb-c.vhd \ + work/tb.o \ + work/tb_elem-full-c.o \ + work/tb_elem-mmc-c.o \ + work/tb_elem-sd-c.o \ + work/tb_elem-minimal-c.o + $(ANALYZE) $(BENCH_DIR)/tb-c.vhd + +work/tb_rl.o: $(BENCH_DIR)/tb_rl.vhd + $(ANALYZE) $(BENCH_DIR)/tb_rl.vhd +work/tb_rl-c.o: $(BENCH_DIR)/tb_rl-c.vhd \ + work/tb_rl.o \ + work/chip-full-c.o \ + work/card-c.o \ + work/ram_loader-c.o + $(ANALYZE) $(BENCH_DIR)/tb_rl-c.vhd + + +.PHONY: elaborate +elaborate: tb_behav_c0 tb_rl_behav_c0 + +tb_behav_c0: work/tb-c.o + $(ELABORATE) tb_behav_c0; \ + strip tb_behav_c0 + +tb_rl_behav_c0: work/tb_rl-c.o + $(ELABORATE) tb_rl_behav_c0; \ + strip tb_rl_behav_c0 + +.PHONY: analyze +analyze: work/tb-c.o work/tb_rl-c.o + +.PHONY: clean +clean: + rm -rf work tb_behav_c0 tb_rl_behav_c0 *~ diff --git a/usrp2/opencores/spi_boot/sw/CVS/Entries b/usrp2/opencores/spi_boot/sw/CVS/Entries new file mode 100644 index 000000000..0f2bd88d4 --- /dev/null +++ b/usrp2/opencores/spi_boot/sw/CVS/Entries @@ -0,0 +1 @@ +D/misc//// diff --git a/usrp2/opencores/spi_boot/sw/CVS/Repository b/usrp2/opencores/spi_boot/sw/CVS/Repository new file mode 100644 index 000000000..98d181ecb --- /dev/null +++ b/usrp2/opencores/spi_boot/sw/CVS/Repository @@ -0,0 +1 @@ +spi_boot/sw diff --git a/usrp2/opencores/spi_boot/sw/CVS/Root b/usrp2/opencores/spi_boot/sw/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/sw/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/sw/CVS/Template b/usrp2/opencores/spi_boot/sw/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/sw/misc/CVS/Entries b/usrp2/opencores/spi_boot/sw/misc/CVS/Entries new file mode 100644 index 000000000..e46425fde --- /dev/null +++ b/usrp2/opencores/spi_boot/sw/misc/CVS/Entries @@ -0,0 +1,2 @@ +/bit_reverse.c/1.1/Sun May 21 11:58:00 2006/-ko/ +D diff --git a/usrp2/opencores/spi_boot/sw/misc/CVS/Repository b/usrp2/opencores/spi_boot/sw/misc/CVS/Repository new file mode 100644 index 000000000..0519f4b59 --- /dev/null +++ b/usrp2/opencores/spi_boot/sw/misc/CVS/Repository @@ -0,0 +1 @@ +spi_boot/sw/misc diff --git a/usrp2/opencores/spi_boot/sw/misc/CVS/Root b/usrp2/opencores/spi_boot/sw/misc/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi_boot/sw/misc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi_boot/sw/misc/CVS/Template b/usrp2/opencores/spi_boot/sw/misc/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c b/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c new file mode 100644 index 000000000..9defb106a --- /dev/null +++ b/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c @@ -0,0 +1,74 @@ +// Altera requires configuration bytes to be sent LSB first but the +// SD Card reads bytes MSB first +// This code reverses the bits of the altera bitstream so +// it will come out correct when read from the SD card +// $Log: bit_reverse.c,v $ +// Revision 1.1 2006/01/06 14:44:17 mbl +// initial version +// + + + +#include "stdio.h" +#include "string.h" + +FILE* fileOut; +FILE* fileIn; + +void outIOerror(char* pfn); +void inIOerror(char* pfn); + +int main(int argc, char* arg[]) +{ + unsigned char input, output; + unsigned char in_mask, out_mask; + int i; + + fileOut = fopen(arg[2],"wb"); + if (fileOut == NULL) + { + outIOerror(arg[2]); + exit(-1); + } + + printf("Opening input file %s\n", arg[1]); + fileIn = fopen(arg[1],"rb"); + if (fileIn == NULL) + { + inIOerror(arg[1]); + exit(-1); + } + + while (!feof(fileIn) && fgets((char*)&input, 2 ,fileIn) != NULL) + { + in_mask = 1; + out_mask = 0x80; + output = 0; + + for ( i=0; i < 8; ++i ) + { + if (input & in_mask) + { + output |= out_mask; + } + out_mask = out_mask >> 1; + in_mask = in_mask << 1; + } + fwrite((void*)&output,sizeof(char),1,fileOut); + } + + fclose(fileIn); + fclose(fileOut); + printf("\n%s has been created\n", arg[2]); + exit(0); +} + +void outIOerror(char *pfn) +{ + printf("I/O Error while writing to file=%s\n",pfn); +} + +void inIOerror(char *pfn) +{ + printf("I/O Error while reading file=%s\n",pfn); +} diff --git a/usrp2/opencores/wb_zbt/CVS/Entries b/usrp2/opencores/wb_zbt/CVS/Entries new file mode 100644 index 000000000..ef78b4f27 --- /dev/null +++ b/usrp2/opencores/wb_zbt/CVS/Entries @@ -0,0 +1,2 @@ +/wb_zbt.v/1.1/Tue Feb 5 22:31:22 2008// +D diff --git a/usrp2/opencores/wb_zbt/CVS/Repository b/usrp2/opencores/wb_zbt/CVS/Repository new file mode 100644 index 000000000..ca9c641d0 --- /dev/null +++ b/usrp2/opencores/wb_zbt/CVS/Repository @@ -0,0 +1 @@ +wb_zbt diff --git a/usrp2/opencores/wb_zbt/CVS/Root b/usrp2/opencores/wb_zbt/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/wb_zbt/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/wb_zbt/CVS/Template b/usrp2/opencores/wb_zbt/CVS/Template new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/opencores/wb_zbt/wb_zbt.v b/usrp2/opencores/wb_zbt/wb_zbt.v new file mode 100644 index 000000000..8f9232752 --- /dev/null +++ b/usrp2/opencores/wb_zbt/wb_zbt.v @@ -0,0 +1,149 @@ +/* + * Multi-port ZBT SRAM WISHBONE controller + * Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net + * This file is part of Milkymist. + * + * Milkymist is free software; you can redistribute it and/or modify it + * under the terms of the GNU Library General Public License as published + * by the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Library General Public License for more details. + * + * You should have received a copy of the GNU Library General Public + * License along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, + * USA. + */ + +module wb_zbt( + input clk, + input rst, + // Wishbone bus A, highest priority, with prefetch + input [31:0] wbA_adr_i, + input [31:0] wbA_dat_i, + output [31:0] wbA_dat_o, + input [ 3:0] wbA_sel_i, + input wbA_cyc_i, + input wbA_stb_i, + output wbA_ack_o, + input wbA_we_i, + // Wishbone bus B, lower priority + input [31:0] wbB_adr_i, + input [31:0] wbB_dat_i, + output [31:0] wbB_dat_o, + input [ 3:0] wbB_sel_i, + input wbB_cyc_i, + input wbB_stb_i, + output wbB_ack_o, + input wbB_we_i, + // Memory connection + output sram_clk, + output [17:0] sram_a, + inout [31:0] sram_d, + output sram_we, + output [ 3:0] sram_bw, + output sram_adv, + output sram_ce, + output sram_oe, + output sram_mode, + output sram_zz +); + +assign sram_clk = clk; +assign sram_oe = 1'b0; +assign sram_ce = 1'b0; +assign sram_adv = 1'b0; +assign sram_mode = 1'b0; +assign sram_zz = 1'b0; + +/* Wishbone decoding */ + +wire busA_active; +wire busB_active; + +assign busA_active = wbA_cyc_i & wbA_stb_i; +assign busB_active = wbB_cyc_i & wbB_stb_i; + +/* Those are used to represent the state of the SRAM pipeline + * Bit 0 = Write Enable + * Bits 18..1 = Address + */ +wire [18:0] pipeline_in; +reg [18:0] pipeline_internal; +reg [18:0] pipeline_out; + +always @(posedge clk or posedge rst) begin + if(rst) begin + pipeline_internal <= 0; + pipeline_out <= 0; + end else begin + pipeline_internal <= pipeline_in; + pipeline_out <= pipeline_internal; + end +end + +/* Pipeline contents decode */ + +wire inprogressA; +wire inprogressB; + +assign inprogressA = (pipeline_internal[18:1] == wbA_adr_i[19:2]) & (pipeline_internal[0] == wbA_we_i); +assign inprogressB = (pipeline_internal[18:1] == wbB_adr_i[19:2]) & (pipeline_internal[0] == wbB_we_i); + +wire hitA; +wire hitB; + +assign hitA = (pipeline_out[18:1] == wbA_adr_i[19:2]) & (pipeline_out[0] == wbA_we_i); +assign hitB = (pipeline_out[18:1] == wbB_adr_i[19:2]) & (pipeline_out[0] == wbB_we_i); + +/* Access arbitration */ + +wire [1:0] bus_request; + +assign bus_request[0] = busA_active & ~inprogressA & ~hitA; +assign bus_request[1] = busB_active & ~inprogressB & ~hitB; + +wire prefetch_enable; +reg [17:0] prefetch_address; + +assign prefetch_enable = ~bus_request[0] & ~bus_request[1]; +always @(posedge clk) begin + if(prefetch_enable) + prefetch_address <= wbA_adr_i[19:2] + 2; + else + prefetch_address <= wbA_adr_i[19:2] + 1; +end + +wire [1:0] bus_selected; + +assign bus_selected[0] = bus_request[0]; +assign bus_selected[1] = bus_request[1] & ~bus_request[0]; + +assign pipeline_in[18:1] = ({18{bus_selected[0]}} & wbA_adr_i[19:2]) + | ({18{bus_selected[1]}} & wbB_adr_i[19:2]) + | ({18{prefetch_enable}} & prefetch_address); +assign pipeline_in[0] = (bus_selected[0] & wbA_we_i)|(bus_selected[1] & wbB_we_i); + +/* SRAM control */ + +assign sram_a = pipeline_in[18:1]; +assign sram_bw = ~(({4{bus_selected[0]}} & wbA_sel_i)|({4{bus_selected[1]}} & wbB_sel_i)); +assign sram_we = ~pipeline_in[0]; + +/* SRAM data */ + +wire [31:0] bus_wdata; + +assign wbA_ack_o = busA_active & hitA; +assign wbB_ack_o = busB_active & hitB; + +assign bus_wdata = ({32{hitA}} & wbA_dat_i)|({32{hitB}} & wbB_dat_i); +assign sram_d = pipeline_out[0] ? bus_wdata : 32'hzzzzzzzz; +assign wbA_dat_o = sram_d; +assign wbB_dat_o = sram_d; + +endmodule diff --git a/usrp2/sdr_lib/.gitignore b/usrp2/sdr_lib/.gitignore new file mode 100644 index 000000000..3c782d589 --- /dev/null +++ b/usrp2/sdr_lib/.gitignore @@ -0,0 +1,3 @@ +/a.out +/db +/*.vcd diff --git a/usrp2/sdr_lib/HB.sav b/usrp2/sdr_lib/HB.sav new file mode 100644 index 000000000..c5087e8a6 --- /dev/null +++ b/usrp2/sdr_lib/HB.sav @@ -0,0 +1,56 @@ +[size] 1400 967 +[pos] -1 -1 +*-46.395245 2565000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] hb_dec_tb. +@420 +hb_dec_tb.data_in[17:0] +@28 +hb_dec_tb.strobe_in +hb_dec_tb.strobe_out +hb_dec_tb.uut.write_even +@22 +hb_dec_tb.uut.addr_even[3:0] +@420 +hb_dec_tb.uut.data_even[17:0] +hb_dec_tb.uut.data_odd_a[17:0] +hb_dec_tb.uut.data_odd_b[17:0] +hb_dec_tb.uut.data_odd_c[17:0] +hb_dec_tb.uut.data_odd_d[17:0] +@28 +hb_dec_tb.uut.write_odd +@420 +hb_dec_tb.uut.prod1[35:0] +hb_dec_tb.uut.prod2[35:0] +@24 +hb_dec_tb.uut.phase[2:0] +@28 +hb_dec_tb.uut.stb_in +hb_dec_tb.uut.stb_out +@420 +hb_dec_tb.uut.sum2[17:0] +hb_dec_tb.uut.stb_out_pre[15:0] +@28 +hb_dec_tb.uut.do_acc +hb_dec_tb.uut.clear +@420 +hb_dec_tb.uut.sum1[17:0] +hb_dec_tb.uut.coeff1[17:0] +hb_dec_tb.uut.prod1[35:0] +hb_dec_tb.uut.prod2[35:0] +hb_dec_tb.uut.final_sum[17:0] +hb_dec_tb.uut.coeff2[17:0] +hb_dec_tb.uut.sum_of_prod[21:0] +hb_dec_tb.data_out[17:0] +@28 +hb_dec_tb.uut.do_acc +hb_dec_tb.uut.clear +@24 +hb_dec_tb.uut.addr_odd_a[3:0] +hb_dec_tb.uut.addr_odd_b[3:0] +hb_dec_tb.uut.addr_odd_c[3:0] +hb_dec_tb.uut.addr_odd_d[3:0] +@28 +hb_dec_tb.uut.write_odd +hb_dec_tb.uut.write_even +@22 +hb_dec_tb.uut.data_even[17:0] diff --git a/usrp2/sdr_lib/SMALL_HB.sav b/usrp2/sdr_lib/SMALL_HB.sav new file mode 100644 index 000000000..96ba00636 --- /dev/null +++ b/usrp2/sdr_lib/SMALL_HB.sav @@ -0,0 +1,40 @@ +[size] 1400 967 +[pos] -1 -1 +*-11.608687 1834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] small_hb_dec_tb. +[treeopen] small_hb_dec_tb.uut. +@28 +small_hb_dec_tb.uut.clk +small_hb_dec_tb.uut.phase +@10421 +small_hb_dec_tb.uut.data_in[17:0] +@420 +small_hb_dec_tb.uut.d1[17:0] +small_hb_dec_tb.uut.d2[17:0] +small_hb_dec_tb.uut.d3[17:0] +small_hb_dec_tb.uut.d4[17:0] +small_hb_dec_tb.uut.d5[17:0] +small_hb_dec_tb.uut.d6[17:0] +small_hb_dec_tb.uut.coeff[17:0] +small_hb_dec_tb.uut.sum[17:0] +small_hb_dec_tb.uut.prod[35:0] +small_hb_dec_tb.uut.accum_rnd[17:0] +@28 +small_hb_dec_tb.uut.stb_in +@420 +small_hb_dec_tb.uut.final_sum[17:0] +@28 +small_hb_dec_tb.uut.go +small_hb_dec_tb.uut.go_d1 +small_hb_dec_tb.uut.go_d2 +small_hb_dec_tb.uut.go_d3 +small_hb_dec_tb.uut.go_d4 +small_hb_dec_tb.uut.stb_out +@420 +small_hb_dec_tb.uut.data_out[17:0] +small_hb_dec_tb.uut.prod[35:0] +small_hb_dec_tb.uut.accum_rnd[17:0] +small_hb_dec_tb.uut.final_sum[17:0] +@10421 +small_hb_dec_tb.uut.round_acc.out[17:0] +small_hb_dec_tb.uut.data_out[17:0] diff --git a/usrp2/sdr_lib/acc.v b/usrp2/sdr_lib/acc.v new file mode 100644 index 000000000..a2da9c86d --- /dev/null +++ b/usrp2/sdr_lib/acc.v @@ -0,0 +1,28 @@ + +module acc + #(parameter IWIDTH=16, OWIDTH=30) + (input clk, + input clear, + input acc, + input [IWIDTH-1:0] in, + output reg [OWIDTH-1:0] out); + + wire [OWIDTH-1:0] in_signext; + sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) + acc_signext (.in(in),.out(in_signext)); + + // CLEAR & ~ACC --> clears the accumulator + // CLEAR & ACC --> loads the accumulator + // ~CLEAR & ACC --> accumulates + // ~CLEAR & ~ACC --> hold + + wire [OWIDTH-1:0] addend1 = clear ? 0 : out; + wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext; + wire [OWIDTH-1:0] sum_int = addend1 + addend2; + + always @(posedge clk) + out <= sum_int; + +endmodule // acc + + diff --git a/usrp2/sdr_lib/add2.v b/usrp2/sdr_lib/add2.v new file mode 100644 index 000000000..13fff803e --- /dev/null +++ b/usrp2/sdr_lib/add2.v @@ -0,0 +1,11 @@ + +module add2 + #(parameter WIDTH=16) + (input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output [WIDTH-1:0] sum); + + wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; + assign sum = sum_int[WIDTH:1]; // Note -- will have some bias + +endmodule // add2 diff --git a/usrp2/sdr_lib/add2_and_round.v b/usrp2/sdr_lib/add2_and_round.v new file mode 100644 index 000000000..146af28da --- /dev/null +++ b/usrp2/sdr_lib/add2_and_round.v @@ -0,0 +1,11 @@ + +module add2_and_round + #(parameter WIDTH=16) + (input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output [WIDTH-1:0] sum); + + wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; + assign sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]); + +endmodule // add2_and_round diff --git a/usrp2/sdr_lib/add2_and_round_reg.v b/usrp2/sdr_lib/add2_and_round_reg.v new file mode 100644 index 000000000..e7fcbf1a1 --- /dev/null +++ b/usrp2/sdr_lib/add2_and_round_reg.v @@ -0,0 +1,16 @@ + +module add2_and_round_reg + #(parameter WIDTH=16) + (input clk, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output reg [WIDTH-1:0] sum); + + wire [WIDTH-1:0] sum_int; + + add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + sum <= sum_int; + +endmodule // add2_and_round_reg diff --git a/usrp2/sdr_lib/add2_reg.v b/usrp2/sdr_lib/add2_reg.v new file mode 100644 index 000000000..456cf315b --- /dev/null +++ b/usrp2/sdr_lib/add2_reg.v @@ -0,0 +1,17 @@ + +module add2_reg + #(parameter WIDTH=16) + (input clk, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output reg [WIDTH-1:0] sum); + + wire [WIDTH-1:0] sum_int; + + add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + sum <= sum_int; + +endmodule // add2_reg + diff --git a/usrp2/sdr_lib/cic_dec_shifter.v b/usrp2/sdr_lib/cic_dec_shifter.v new file mode 100644 index 000000000..aa5ac895b --- /dev/null +++ b/usrp2/sdr_lib/cic_dec_shifter.v @@ -0,0 +1,106 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// NOTE This only works for N=4, max decim rate of 128 +// NOTE signal "rate" is EQUAL TO the actual rate, no more -1 BS + +module cic_dec_shifter(rate,signal_in,signal_out); + parameter bw = 16; + parameter maxbitgain = 28; + + input [7:0] rate; + input wire [bw+maxbitgain-1:0] signal_in; + output reg [bw-1:0] signal_out; + + function [4:0] bitgain; + input [7:0] rate; + case(rate) + // Exact Cases -- N*log2(rate) + 8'd1 : bitgain = 0; + 8'd2 : bitgain = 4; + 8'd4 : bitgain = 8; + 8'd8 : bitgain = 12; + 8'd16 : bitgain = 16; + 8'd32 : bitgain = 20; + 8'd64 : bitgain = 24; + 8'd128 : bitgain = 28; + + // Nearest without overflow -- ceil(N*log2(rate)) + 8'd3 : bitgain = 7; + 8'd5 : bitgain = 10; + 8'd6 : bitgain = 11; + 8'd7 : bitgain = 12; + 8'd9 : bitgain = 13; + 8'd10,8'd11 : bitgain = 14; + 8'd12,8'd13 : bitgain = 15; + 8'd14,8'd15 : bitgain = 16; + 8'd17,8'd18,8'd19 : bitgain = 17; + 8'd20,8'd21,8'd22 : bitgain = 18; + 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; + 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; + 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; + 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; + 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; + 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; + 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; + 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; + 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; + default : bitgain = 28; + endcase // case(rate) + endfunction // bitgain + + wire [4:0] shift = bitgain(rate); + + // We should be able to do this, but can't .... + // assign signal_out = signal_in[shift+bw-1:shift]; + + always @* + case(shift) + 5'd0 : signal_out = signal_in[0+bw-1:0]; + 5'd4 : signal_out = signal_in[4+bw-1:4]; + 5'd7 : signal_out = signal_in[7+bw-1:7]; + 5'd8 : signal_out = signal_in[8+bw-1:8]; + 5'd10 : signal_out = signal_in[10+bw-1:10]; + 5'd11 : signal_out = signal_in[11+bw-1:11]; + 5'd12 : signal_out = signal_in[12+bw-1:12]; + 5'd13 : signal_out = signal_in[13+bw-1:13]; + 5'd14 : signal_out = signal_in[14+bw-1:14]; + 5'd15 : signal_out = signal_in[15+bw-1:15]; + 5'd16 : signal_out = signal_in[16+bw-1:16]; + 5'd17 : signal_out = signal_in[17+bw-1:17]; + 5'd18 : signal_out = signal_in[18+bw-1:18]; + 5'd19 : signal_out = signal_in[19+bw-1:19]; + 5'd20 : signal_out = signal_in[20+bw-1:20]; + 5'd21 : signal_out = signal_in[21+bw-1:21]; + 5'd22 : signal_out = signal_in[22+bw-1:22]; + 5'd23 : signal_out = signal_in[23+bw-1:23]; + 5'd24 : signal_out = signal_in[24+bw-1:24]; + 5'd25 : signal_out = signal_in[25+bw-1:25]; + 5'd26 : signal_out = signal_in[26+bw-1:26]; + 5'd27 : signal_out = signal_in[27+bw-1:27]; + 5'd28 : signal_out = signal_in[28+bw-1:28]; + + default : signal_out = signal_in[28+bw-1:28]; + endcase // case(shift) + +endmodule // cic_dec_shifter + diff --git a/usrp2/sdr_lib/cic_decim.v b/usrp2/sdr_lib/cic_decim.v new file mode 100755 index 000000000..9a03081b0 --- /dev/null +++ b/usrp2/sdr_lib/cic_decim.v @@ -0,0 +1,88 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +module cic_decim + #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7) + (input clock, + input reset, + input enable, + input [7:0] rate, + input strobe_in, + input strobe_out, + input [bw-1:0] signal_in, + output reg [bw-1:0] signal_out); + + localparam maxbitgain = N * log2_of_max_rate; + + wire [bw+maxbitgain-1:0] signal_in_ext; + reg [bw+maxbitgain-1:0] integrator [0:N-1]; + reg [bw+maxbitgain-1:0] differentiator [0:N-1]; + reg [bw+maxbitgain-1:0] pipeline [0:N-1]; + reg [bw+maxbitgain-1:0] sampler; + + integer i; + + sign_extend #(bw,bw+maxbitgain) + ext_input (.in(signal_in),.out(signal_in_ext)); + + always @(posedge clock) + if(reset) + for(i=0;i "the real A" (as determined by the TVRX) + // 1 -> "the real B" + // 2 -> const zero + + always @(posedge clk) + case(muxctrl[1:0]) // The I mapping + 0: adc_i <= adc_b_ofs; // "the real A" + 1: adc_i <= adc_a_ofs; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case(muxctrl[1:0]) + + always @(posedge clk) + case(muxctrl[3:2]) // The Q mapping + 0: adc_q <= adc_b_ofs; // "the real A" + 1: adc_q <= adc_a_ofs; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case(muxctrl[3:2]) + + always @(posedge clk) + if(rst) + phase <= 0; + else if(~run) + phase <= 0; + else + phase <= phase + phase_inc; + + MULT18X18S mult_i + (.P(prod_i), // 36-bit multiplier output + .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + MULT18X18S mult_q + (.P(prod_q), // 36-bit multiplier output + .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + + cordic_z24 #(.bitwidth(24)) + cordic(.clock(clk), .reset(rst), .enable(run), + .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]), + .xo(i_cordic),.yo(q_cordic),.zo() ); + + cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate), + .strobe_fast(1),.strobe_slow(strobe_cic) ); + + cic_decim #(.bw(24)) + decim_i (.clock(clk),.reset(rst),.enable(run), + .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), + .signal_in(i_cordic),.signal_out(i_cic)); + + cic_decim #(.bw(24)) + decim_q (.clock(clk),.reset(rst),.enable(run), + .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), + .signal_in(q_cordic),.signal_out(q_cic)); + + round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled)); + round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled)); + reg strobe_cic_d1; + always @(posedge clk) strobe_cic_d1 <= strobe_cic; + + small_hb_dec #(.WIDTH(18)) small_hb_i + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), + .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1)); + + small_hb_dec #(.WIDTH(18)) small_hb_q + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), + .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1)); + + wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate}; + hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), + .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2)); + + hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), + .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); + + round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); + round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); + + // Streaming GPIO + // + // io_rx[15] => I channel LSB if gpio_ena[0] high + // io_rx[14] => Q channel LSB if gpio_ena[1] high + + reg [31:0] sample_reg; + always @(posedge clk) + begin + sample_reg[31:17] <= i_out[15:1]; + sample_reg[15:1] <= q_out[15:1]; + sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; + sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; + end + + assign sample = sample_reg; + assign strobe = strobe_hb2; + assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; + +endmodule // dsp_core_rx diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v new file mode 100644 index 000000000..346d65ced --- /dev/null +++ b/usrp2/sdr_lib/dsp_core_tx.v @@ -0,0 +1,152 @@ + +`define DSP_CORE_TX_BASE 128 + +module dsp_core_tx + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + output reg [15:0] dac_a, + output reg [15:0] dac_b, + + // To tx_control + input [31:0] sample, + input run, + output strobe, + output [31:0] debug + ); + + wire [15:0] i, q, scale_i, scale_q; + wire [31:0] phase_inc; + reg [31:0] phase; + wire [7:0] interp_rate; + wire [3:0] dacmux_a, dacmux_b; + wire enable_hb1, enable_hb2; + + setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_TX_BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_TX_BASE+4)) sr_4 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({dacmux_b,dacmux_a}),.changed()); + + // Strobes are all now delayed by 1 cycle for timing reasons + wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre; + reg strobe_cic = 1; + reg strobe_hb1 = 1; + reg strobe_hb2 = 1; + + cic_strober #(.WIDTH(8)) + cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + .strobe_fast(1),.strobe_slow(strobe_cic_pre) ); + cic_strober #(.WIDTH(2)) + hb2_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb2 ? 2 : 1), + .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) ); + cic_strober #(.WIDTH(2)) + hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb1 ? 2 : 1), + .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) ); + + always @(posedge clk) strobe_hb1 <= strobe_hb1_pre; + always @(posedge clk) strobe_hb2 <= strobe_hb2_pre; + always @(posedge clk) strobe_cic <= strobe_cic_pre; + + // NCO + always @(posedge clk) + if(rst) + phase <= 0; + else if(~run) + phase <= 0; + else + phase <= phase + phase_inc; + + wire signed [17:0] da, db; + wire signed [35:0] prod_i, prod_q; + + wire [17:0] bb_i = {sample[31:16],2'b0}; + wire [17:0] bb_q = {sample[15:0],2'b0}; + wire [17:0] i_interp, q_interp; + + wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q; + + wire [7:0] cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate; + // Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true, + // but the default case inside hb_interp handles this + + hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_i + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_i),.stb_out(strobe_hb2),.data_out(hb1_i)); + hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_q + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_q),.stb_out(strobe_hb2),.data_out(hb1_q)); + + small_hb_int #(.WIDTH(18)) small_hb_interp_i + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i), + .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i)); + small_hb_int #(.WIDTH(18)) small_hb_interp_q + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q), + .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q)); + + cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) + cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + .strobe_in(strobe_cic),.strobe_out(1), + .signal_in(hb2_i),.signal_out(i_interp)); + + cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) + cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + .strobe_in(strobe_cic),.strobe_out(1), + .signal_in(hb2_q),.signal_out(q_interp)); + + assign strobe = strobe_hb1; + + localparam cwidth = 24; // was 18 + localparam zwidth = 24; // was 16 + + wire [cwidth-1:0] da_c, db_c; + + cordic_z24 #(.bitwidth(cwidth)) + cordic(.clock(clk), .reset(rst), .enable(run), + .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}), + .zi(phase[31:32-zwidth]), + .xo(da_c),.yo(db_c),.zo() ); + + MULT18X18S MULT18X18S_inst + (.P(prod_i), // 36-bit multiplier output + .A(da_c[cwidth-1:cwidth-18]), // 18-bit multiplier input + .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + MULT18X18S MULT18X18S_inst_2 + (.P(prod_q), // 36-bit multiplier output + .A(db_c[cwidth-1:cwidth-18]), // 18-bit multiplier input + .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + always @(posedge clk) + case(dacmux_a) + 0 : dac_a <= prod_i[28:13]; + 1 : dac_a <= prod_q[28:13]; + default : dac_a <= 0; + endcase // case(dacmux_a) + + always @(posedge clk) + case(dacmux_b) + 0 : dac_b <= prod_i[28:13]; + 1 : dac_b <= prod_q[28:13]; + default : dac_b <= 0; + endcase // case(dacmux_b) + + assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run}; + +endmodule // dsp_core diff --git a/usrp2/sdr_lib/duc.v b/usrp2/sdr_lib/duc.v new file mode 100755 index 000000000..6dac95b49 --- /dev/null +++ b/usrp2/sdr_lib/duc.v @@ -0,0 +1,95 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// DUC block + +module duc(input clock, + input reset, + input enable, + input [3:0] rate1, + input [3:0] rate2, + output strobe, + input [31:0] freq, + input [15:0] i_in, + input [15:0] q_in, + output [15:0] i_out, + output [15:0] q_out + ); + parameter bw = 16; + parameter zw = 16; + + wire [15:0] i_interp_out, q_interp_out; + wire [31:0] phase; + + wire strobe1, strobe2; + reg [3:0] strobe_ctr1,strobe_ctr2; + + always @(posedge clock) + if(reset | ~enable) + strobe_ctr2 <= #1 4'd0; + else if(strobe2) + strobe_ctr2 <= #1 4'd0; + else + strobe_ctr2 <= #1 strobe_ctr2 + 4'd1; + + always @(posedge clock) + if(reset | ~enable) + strobe_ctr1 <= #1 4'd0; + else if(strobe1) + strobe_ctr1 <= #1 4'd0; + else if(strobe2) + strobe_ctr1 <= #1 strobe_ctr1 + 4'd1; + + + assign strobe2 = enable & ( strobe_ctr2 == rate2 ); + assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 ); + + assign strobe = strobe1; + + function [2:0] log_ceil; + input [3:0] val; + + log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; + endfunction + + wire [2:0] shift1 = log_ceil(rate1); + wire [2:0] shift2 = log_ceil(rate2); + + cordic #(.bitwidth(bw),.zwidth(zw),.stages(16)) + cordic(.clock(clock), .reset(reset), .enable(enable), + .xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]), + .xo(i_out), .yo(q_out), .zo() ); + + cic_interp_2stage #(.bw(bw),.N(4)) + interp_i(.clock(clock),.reset(reset),.enable(enable), + .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), + .signal_in(i_in),.signal_out(i_interp_out)); + + cic_interp_2stage #(.bw(bw),.N(4)) + interp_q(.clock(clock),.reset(reset),.enable(enable), + .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), + .signal_in(q_in),.signal_out(q_interp_out)); + + phase_acc #(.resolution(32)) + nco (.clk(clock),.reset(reset),.enable(enable), + .freq(freq),.phase(phase)); + +endmodule diff --git a/usrp2/sdr_lib/dummy_rx.v b/usrp2/sdr_lib/dummy_rx.v new file mode 100644 index 000000000..99290ecec --- /dev/null +++ b/usrp2/sdr_lib/dummy_rx.v @@ -0,0 +1,62 @@ + +`define DSP_CORE_RX_BASE 160 +module dummy_rx + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [13:0] adc_a, input adc_ovf_a, + input [13:0] adc_b, input adc_ovf_b, + + output [31:0] sample, + input run, + output strobe + ); + + wire [15:0] scale_i, scale_q; + wire [31:0] phase_inc; + reg [31:0] phase; + + wire [23:0] i_decim, q_decim; + wire [7:0] decim_rate; + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(decim_rate),.changed()); + + strobe_gen strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), + .strobe_in(1),.strobe(strobe) ); + + reg [15:0] i_out, q_out; + assign sample = {i_out,q_out}; + + always @(posedge clk) + if(rst) + i_out <= 0; + else if(~run) + i_out <= 0; + else if(strobe) + i_out <= i_out + 1; + + reg run_d1; + always @(posedge clk) + if(rst) + run_d1 <= 0; + else + run_d1 <= run; + + always @(posedge clk) + if(rst) + q_out <= 0; + else if (run & ~run_d1) + q_out <= q_out + 1; + + +endmodule // dsp_core_rx diff --git a/usrp2/sdr_lib/gen_cordic_consts.py b/usrp2/sdr_lib/gen_cordic_consts.py new file mode 100755 index 000000000..261e8c223 --- /dev/null +++ b/usrp2/sdr_lib/gen_cordic_consts.py @@ -0,0 +1,10 @@ +#!/usr/bin/env python + +import math + +zwidth = 24 + +for i in range(24): + c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth) + print "localparam c%02d = %d'd%d;" % (i, zwidth, round (c)) + diff --git a/usrp2/sdr_lib/halfband_ideal.v b/usrp2/sdr_lib/halfband_ideal.v new file mode 100644 index 000000000..484cfff2a --- /dev/null +++ b/usrp2/sdr_lib/halfband_ideal.v @@ -0,0 +1,84 @@ +module halfband_ideal ( + input clock, + input reset, + input enable, + input strobe_in, + input wire signed [17:0] data_in, + output reg strobe_out, + output reg signed [17:0] data_out +) ; + + parameter decim = 1 ; + parameter rate = 2 ; + + reg signed [40:0] temp ; + reg signed [17:0] delay[30:0] ; + reg signed [17:0] coeffs[30:0] ; + reg [7:0] count ; + integer i ; + + initial begin + for( i = 0 ; i < 31 ; i = i + 1 ) begin + coeffs[i] = 18'd0 ; + end + coeffs[0] = -1390 ; + coeffs[2] = 1604 ; + coeffs[4] = -1896 ; + coeffs[6] = 2317 ; + coeffs[8] = -2979 ; + coeffs[10] = 4172 ; + coeffs[12] = -6953 ; + coeffs[14] = 20860 ; + coeffs[15] = 32768 ; + coeffs[16] = 20860 ; + coeffs[18] = -6953 ; + coeffs[20] = 4172 ; + coeffs[22] = -2979 ; + coeffs[24] = 2317 ; + coeffs[26] = -1896 ; + coeffs[28] = 1604 ; + coeffs[30] = -1390 ; + end + + always @(posedge clock) begin + if( reset ) begin + count <= 0 ; + for( i = 0 ; i < 31 ; i = i + 1 ) begin + delay[i] <= 18'd0 ; + end + temp <= 41'd0 ; + data_out <= 18'd0 ; + strobe_out <= 1'b0 ; + end else if( enable ) begin + + if( (decim && (count == rate-1)) || !decim ) + strobe_out <= strobe_in ; + else + strobe_out <= 1'b0 ; + + + if( strobe_in ) begin + // Increment decimation count + count <= count + 1 ; + + // Shift the input + for( i = 30 ; i > 0 ; i = i - 1 ) begin + delay[i] = delay[i-1] ; + end + delay[0] = data_in ; + + // clear the temp reg + temp = 18'd0 ; + if( (decim && (count == rate-1)) || !decim ) begin + count <= 0 ; + for( i = 0 ; i < 31 ; i = i + 1 ) begin + // Multiply Accumulate + temp = temp + delay[i]*coeffs[i] ; + end + // Assign data output + data_out <= temp >>> 15 ; + end + end + end + end +endmodule diff --git a/usrp2/sdr_lib/halfband_tb.v b/usrp2/sdr_lib/halfband_tb.v new file mode 100644 index 000000000..231dd00d7 --- /dev/null +++ b/usrp2/sdr_lib/halfband_tb.v @@ -0,0 +1,120 @@ +module halfband_tb( ) ; + + // Parameters for instantiation + parameter clocks = 2 ; // Number of clocks per input + parameter decim = 0 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + reg strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #100 reset = 1'b0 ; + + // Enable the entire system + initial enable = 1'b1 ; + + // Instantiate UUT + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + + integer i, ri, ro, infile, outfile ; + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + strobe_in <= 1'd0 ; + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( posedge clock ) begin + #1 ; + strobe_in <= 1'b1 ; + if( !$feof(infile) ) + ri = $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + + // Clocked in - set the strobe to 0 if the number of + // clocks per sample is greater than 1 + if( clocks > 1 ) begin + @(posedge clock) begin + strobe_in <= 1'b0 ; + end + + // Wait for the specified number of cycles + for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin + @(posedge clock) #1 ; + end + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $stop ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + $display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + endofsim <= 1'b1 ; + end + end + end + +endmodule diff --git a/usrp2/sdr_lib/hb/acc.v b/usrp2/sdr_lib/hb/acc.v new file mode 100644 index 000000000..195d5ea94 --- /dev/null +++ b/usrp2/sdr_lib/hb/acc.v @@ -0,0 +1,22 @@ + + +module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, + input signed [30:0] addend, output reg signed [33:0] sum ); + + always @(posedge clock) + if(reset) + sum <= #1 34'd0; + //else if(clear & enable_in) + // sum <= #1 addend; + //else if(clear) + // sum <= #1 34'd0; + else if(clear) + sum <= #1 addend; + else if(enable_in) + sum <= #1 sum + addend; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // acc + diff --git a/usrp2/sdr_lib/hb/coeff_ram.v b/usrp2/sdr_lib/hb/coeff_ram.v new file mode 100644 index 000000000..65460822f --- /dev/null +++ b/usrp2/sdr_lib/hb/coeff_ram.v @@ -0,0 +1,26 @@ + + +module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data); + + always @(posedge clock) + case (rd_addr) + 4'd0 : rd_data <= #1 -16'd16; + 4'd1 : rd_data <= #1 16'd74; + 4'd2 : rd_data <= #1 -16'd254; + 4'd3 : rd_data <= #1 16'd669; + 4'd4 : rd_data <= #1 -16'd1468; + 4'd5 : rd_data <= #1 16'd2950; + 4'd6 : rd_data <= #1 -16'd6158; + 4'd7 : rd_data <= #1 16'd20585; + 4'd8 : rd_data <= #1 16'd20585; + 4'd9 : rd_data <= #1 -16'd6158; + 4'd10 : rd_data <= #1 16'd2950; + 4'd11 : rd_data <= #1 -16'd1468; + 4'd12 : rd_data <= #1 16'd669; + 4'd13 : rd_data <= #1 -16'd254; + 4'd14 : rd_data <= #1 16'd74; + 4'd15 : rd_data <= #1 -16'd16; + default : rd_data <= #1 16'd0; + endcase // case(rd_addr) + +endmodule // ram diff --git a/usrp2/sdr_lib/hb/coeff_rom.v b/usrp2/sdr_lib/hb/coeff_rom.v new file mode 100644 index 000000000..7f8886b4e --- /dev/null +++ b/usrp2/sdr_lib/hb/coeff_rom.v @@ -0,0 +1,19 @@ + + +module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); + + always @(posedge clock) + case (addr) + 3'd0 : data <= #1 -16'd49; + 3'd1 : data <= #1 16'd165; + 3'd2 : data <= #1 -16'd412; + 3'd3 : data <= #1 16'd873; + 3'd4 : data <= #1 -16'd1681; + 3'd5 : data <= #1 16'd3135; + 3'd6 : data <= #1 -16'd6282; + 3'd7 : data <= #1 16'd20628; + endcase // case(addr) + +endmodule // coeff_rom + + diff --git a/usrp2/sdr_lib/hb/halfband_decim.v b/usrp2/sdr_lib/hb/halfband_decim.v new file mode 100644 index 000000000..dff4d902c --- /dev/null +++ b/usrp2/sdr_lib/hb/halfband_decim.v @@ -0,0 +1,163 @@ +/* -*- verilog -*- + * + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2005 Matt Ettus + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA + */ + +/* + * This implements a 31-tap halfband filter that decimates by two. + * The coefficients are symmetric, and with the exception of the middle tap, + * every other coefficient is zero. The middle section of taps looks like this: + * + * ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ... + * | + * middle tap -------+ + * + * See coeff_rom.v for the full set. The taps are scaled relative to 32768, + * thus the middle tap equals 1.0. Not counting the middle tap, there are 8 + * non-zero taps on each side, and they are symmetric. A naive implementation + * requires a mulitply for each non-zero tap. Because of symmetry, we can + * replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output + * sample, we need to perform 8 multiplications. Since the middle tap is 1.0, + * we just add the corresponding delay line value. + * + * About timing: We implement this with a single multiplier, so it takes + * 8 cycles to compute a single output. However, since we're decimating by two + * we can accept a new input value every 4 cycles. strobe_in is asserted when + * there's a new input sample available. Depending on the overall decimation + * rate, strobe_in may be asserted less frequently than once every 4 clocks. + * On the output side, we assert strobe_out when output contains a new sample. + * + * Implementation: Every time strobe_in is asserted we store the new data into + * the delay line. We split the delay line into two components, one for the + * even samples, and one for the odd samples. ram16_odd is the delay line for + * the odd samples. This ram is written on each odd assertion of strobe_in, and + * is read on each clock when we're computing the dot product. ram16_even is + * similar, although because it holds the even samples we must be able to read + * two samples from different addresses at the same time, while writing the incoming + * even samples. Thus it's "triple-ported". + */ + +module halfband_decim + (input clock, input reset, input enable, input strobe_in, output wire strobe_out, + input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl); + + reg [3:0] rd_addr1; + reg [3:0] rd_addr2; + reg [3:0] phase; + reg [3:0] base_addr; + + wire signed [15:0] mac_out,middle_data, sum, coeff; + wire signed [30:0] product; + wire signed [33:0] sum_even; + wire clear; + reg store_odd; + + always @(posedge clock) + if(reset) + store_odd <= #1 1'b0; + else + if(strobe_in) + store_odd <= #1 ~store_odd; + + wire start = strobe_in & store_odd; + always @(posedge clock) + if(reset) + base_addr <= #1 4'd0; + else if(start) + base_addr <= #1 base_addr + 4'd1; + + always @(posedge clock) + if(reset) + phase <= #1 4'd8; + else if (start) + phase <= #1 4'd0; + else if(phase != 4'd8) + phase <= #1 phase + 4'd1; + + reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD; + always @(posedge clock) + begin + start_d1 <= #1 start; + start_d2 <= #1 start_d1; + start_d3 <= #1 start_d2; + start_d4 <= #1 start_d3; + start_d5 <= #1 start_d4; + start_d6 <= #1 start_d5; + start_d7 <= #1 start_d6; + start_d8 <= #1 start_d7; + start_d9 <= #1 start_d8; + start_dA <= #1 start_d9; + start_dB <= #1 start_dA; + start_dC <= #1 start_dB; + start_dD <= #1 start_dC; + end // always @ (posedge clock) + + reg mult_en, mult_en_pre; + always @(posedge clock) + begin + mult_en_pre <= #1 phase!=8; + mult_en <= #1 mult_en_pre; + end + + assign clear = start_d4; // was dC + wire latch_result = start_d4; // was dC + assign strobe_out = start_d5; // was dD + wire acc_en; + + always @* + case(phase[2:0]) + 3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end + 3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end + 3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end + 3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end + 3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end + 3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end + 3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end + 3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end + default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end + endcase // case(phase) + + coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff)); + + ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), + .wr_addr(base_addr),.wr_data(data_in), + .rd_addr1(rd_addr1),.rd_addr2(rd_addr2), + .sum(sum)); + + ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items + .wr_addr(base_addr),.wr_data(data_in), + //.rd_addr(base_addr+4'd7),.rd_data(middle_data)); + .rd_addr(base_addr+4'd6),.rd_data(middle_data)); + + mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en)); + + acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(), + .clear(clear),.addend(product),.sum(sum_even)); + + wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!! + + always @(posedge clock) + if(reset) + data_out <= #1 16'd0; + else if(latch_result) + data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]); + + assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase}; + +endmodule // halfband_decim diff --git a/usrp2/sdr_lib/hb/halfband_interp.v b/usrp2/sdr_lib/hb/halfband_interp.v new file mode 100644 index 000000000..cdb11c1f6 --- /dev/null +++ b/usrp2/sdr_lib/hb/halfband_interp.v @@ -0,0 +1,121 @@ + + +module halfband_interp + (input clock, input reset, input enable, + input strobe_in, input strobe_out, + input [15:0] signal_in_i, input [15:0] signal_in_q, + output reg [15:0] signal_out_i, output reg [15:0] signal_out_q, + output wire [12:0] debug); + + wire [15:0] coeff_ram_out; + wire [15:0] data_ram_out_i; + wire [15:0] data_ram_out_q; + + wire [3:0] data_rd_addr; + reg [3:0] data_wr_addr; + reg [2:0] coeff_rd_addr; + + wire filt_done; + + wire [15:0] mac_out_i; + wire [15:0] mac_out_q; + reg [15:0] delayed_middle_i, delayed_middle_q; + wire [7:0] shift = 8'd9; + + reg stb_out_happened; + + wire [15:0] data_ram_out_i_b; + + always @(posedge clock) + if(strobe_in) + stb_out_happened <= #1 1'b0; + else if(strobe_out) + stb_out_happened <= #1 1'b1; + +assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr}; + + wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i; + wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q; + +/* always @(posedge clock) + if(reset) + begin + signal_out_i <= #1 16'd0; + signal_out_q <= #1 16'd0; + end + else if(strobe_in) + begin + signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff + signal_out_q <= #1 delayed_middle_q; + end + //else if(filt_done&stb_out_happened) + else if(stb_out_happened) + begin + signal_out_i <= #1 mac_out_i; + signal_out_q <= #1 mac_out_q; + end +*/ + + always @(posedge clock) + if(reset) + coeff_rd_addr <= #1 3'd0; + else if(coeff_rd_addr != 3'd0) + coeff_rd_addr <= #1 coeff_rd_addr + 3'd1; + else if(strobe_in) + coeff_rd_addr <= #1 3'd1; + + reg filt_done_d1; + always@(posedge clock) + filt_done_d1 <= #1 filt_done; + + always @(posedge clock) + if(reset) + data_wr_addr <= #1 4'd0; + //else if(strobe_in) + else if(filt_done & ~filt_done_d1) + data_wr_addr <= #1 data_wr_addr + 4'd1; + + always @(posedge clock) + if(coeff_rd_addr == 3'd7) + begin + delayed_middle_i <= #1 data_ram_out_i_b; + // delayed_middle_q <= #1 data_ram_out_q_b; + end + +// always @(posedge clock) +// if(reset) +// data_rd_addr <= #1 4'd0; +// else if(strobe_in) +// data_rd_addr <= #1 data_wr_addr + 4'd1; +// else if(!filt_done) +// data_rd_addr <= #1 data_rd_addr + 4'd1; +// else +// data_rd_addr <= #1 data_wr_addr; + + wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr}; + wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr}; +// always @(posedge clock) +// if(reset) +// filt_done <= #1 1'b1; +// else if(strobe_in) + // filt_done <= #1 1'b0; +// else if(coeff_rd_addr == 4'd0) +// filt_done <= #1 1'b1; + + assign filt_done = (coeff_rd_addr == 3'd0); + + coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) ); + + ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i), + .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i)); + + ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q), + .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q)); + + mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), + .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) ); + + mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), + .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) ); + +endmodule // halfband_interp diff --git a/usrp2/sdr_lib/hb/hbd_tb/HBD b/usrp2/sdr_lib/hb/hbd_tb/HBD new file mode 100644 index 000000000..574fbba91 --- /dev/null +++ b/usrp2/sdr_lib/hb/hbd_tb/HBD @@ -0,0 +1,80 @@ +*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +test_hbd.clock +test_hbd.reset +@420 +test_hbd.halfband_decim.middle_data[15:0] +@22 +test_hbd.halfband_decim.sum_even[33:0] +test_hbd.halfband_decim.base_addr[3:0] +@420 +test_hbd.i_in[15:0] +@24 +test_hbd.halfband_decim.phase[3:0] +test_hbd.halfband_decim.ram16_even.rd_addr1[3:0] +test_hbd.halfband_decim.ram16_even.rd_addr2[3:0] +test_hbd.halfband_decim.ram16_even.wr_addr[3:0] +test_hbd.halfband_decim.ram16_even.wr_data[15:0] +@28 +test_hbd.halfband_decim.ram16_even.write +@420 +test_hbd.halfband_decim.sum[15:0] +test_hbd.halfband_decim.product[30:0] +test_hbd.halfband_decim.dout[33:0] +test_hbd.halfband_decim.sum_even[33:0] +@22 +test_hbd.halfband_decim.acc.addend[30:0] +@28 +test_hbd.halfband_decim.acc.reset +@420 +test_hbd.halfband_decim.acc.sum[33:0] +test_hbd.halfband_decim.mult.x[15:0] +test_hbd.halfband_decim.mult.y[15:0] +@28 +test_hbd.halfband_decim.acc.clear +test_hbd.strobe_in +test_hbd.strobe_out +test_hbd.halfband_decim.acc_en +@420 +test_hbd.i_out[15:0] +@28 +test_hbd.halfband_decim.mult_en +test_hbd.halfband_decim.latch_result +@420 +test_hbd.halfband_decim.sum[15:0] +test_hbd.halfband_decim.sum_even[33:0] +test_hbd.halfband_decim.dout[33:0] +test_hbd.halfband_decim.data_out[15:0] +@22 +test_hbd.halfband_decim.data_out[15:0] +@28 +test_hbd.halfband_decim.dout[33:0] +@29 +test_hbd.halfband_decim.acc_en +@22 +test_hbd.halfband_decim.base_addr[3:0] +@28 +test_hbd.halfband_decim.clear +test_hbd.halfband_decim.latch_result +test_hbd.halfband_decim.mult_en +test_hbd.halfband_decim.mult_en_pre +@22 +test_hbd.halfband_decim.phase[3:0] +@28 +test_hbd.halfband_decim.start +test_hbd.halfband_decim.start_d1 +test_hbd.halfband_decim.start_d2 +test_hbd.halfband_decim.start_d3 +test_hbd.halfband_decim.start_d4 +test_hbd.halfband_decim.start_d5 +test_hbd.halfband_decim.start_d6 +test_hbd.halfband_decim.start_d7 +test_hbd.halfband_decim.start_d8 +test_hbd.halfband_decim.start_d9 +test_hbd.halfband_decim.start_dA +test_hbd.halfband_decim.start_dB +test_hbd.halfband_decim.start_dC +test_hbd.halfband_decim.start_dD +test_hbd.halfband_decim.store_odd +test_hbd.halfband_decim.strobe_in +test_hbd.halfband_decim.strobe_out diff --git a/usrp2/sdr_lib/hb/hbd_tb/really_golden b/usrp2/sdr_lib/hb/hbd_tb/really_golden new file mode 100644 index 000000000..2d24a9e14 --- /dev/null +++ b/usrp2/sdr_lib/hb/hbd_tb/really_golden @@ -0,0 +1,142 @@ +VCD info: dumpfile test_hbd.vcd opened for output. + x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8192 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 +- 4 + 18 +- 63 + 167 +- 367 + 737 +- 1539 + 5146 + 5146 +- 1539 + 737 +- 367 + 167 +- 63 + 18 +- 4 + 0 + 0 + 0 + 0 + 0 +- 4 + 14 +- 49 + 118 +- 249 + 488 + 7141 +12287 +17433 +15894 +16631 +16264 +16432 +16368 +16387 +16383 +16383 +16383 +16383 +16383 +16387 +16368 +16432 +16264 +16631 +15894 + 9241 + 4095 +- 1051 + 488 +- 249 + 118 +- 49 + 14 +- 4 + 0 + 0 + 0 + 0 + 0 +- 4 + 14 +- 49 + 118 +- 249 + 488 +- 1051 +12287 +17433 +15894 +16631 +16264 +16432 +16368 +16387 +16383 +16383 +16383 +16383 +16383 +16387 +16368 +16432 +16264 +16631 +15894 +17433 + 4095 +- 1051 + 488 +- 249 + 118 +- 49 + 14 +- 4 + 0 + 0 + 0 + 0 diff --git a/usrp2/sdr_lib/hb/hbd_tb/regression b/usrp2/sdr_lib/hb/hbd_tb/regression new file mode 100644 index 000000000..fc279c2f2 --- /dev/null +++ b/usrp2/sdr_lib/hb/hbd_tb/regression @@ -0,0 +1,95 @@ +echo "Baseline 1000" +iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden +diff golden really_golden + +echo +echo "Test 100" +iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 50" +iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 40" +iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 30" +iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 25" +iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 20" +iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 19" +iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 18" +iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 17" +iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 16" +iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 15" +iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 14" +iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 13" +iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 12" +iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 11" +iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 10" +iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 9" +iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 8" +iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 7" +iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 6" +iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 5" +iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 4" +iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 3" +iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden diff --git a/usrp2/sdr_lib/hb/hbd_tb/run_hbd b/usrp2/sdr_lib/hb/hbd_tb/run_hbd new file mode 100755 index 000000000..b8aec7574 --- /dev/null +++ b/usrp2/sdr_lib/hb/hbd_tb/run_hbd @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog -y .. -o test_hbd test_hbd.v +./test_hbd diff --git a/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v b/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v new file mode 100644 index 000000000..01ab5e7e0 --- /dev/null +++ b/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v @@ -0,0 +1,75 @@ + + +module test_hbd(); + + reg clock; + initial clock = 1'b0; + always #5 clock <= ~clock; + + reg reset; + initial reset = 1'b1; + initial #1000 reset = 1'b0; + + initial $dumpfile("test_hbd.vcd"); + initial $dumpvars(0,test_hbd); + + reg [15:0] i_in, q_in; + wire [15:0] i_out, q_out; + + reg strobe_in; + wire strobe_out; + reg coeff_write; + reg [15:0] coeff_data; + reg [4:0] coeff_addr; + + halfband_decim halfband_decim + ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), + .data_in(i_in),.data_out(i_out) ); + + always @(posedge strobe_out) + if(i_out[15]) + $display("-%d",65536-i_out); + else + $display("%d",i_out); + + initial + begin + strobe_in = 1'b0; + @(negedge reset); + @(posedge clock); + while(1) + begin + strobe_in <= #1 1'b1; + @(posedge clock); + strobe_in <= #1 1'b0; + repeat (`RATE) + @(posedge clock); + end + end + + initial #10000000 $finish; // Just in case... + + initial + begin + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (41) @(posedge strobe_in); + i_in <= #1 16'd16384; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + repeat (7) @(posedge clock); + $finish; + end // initial begin +endmodule // test_hb diff --git a/usrp2/sdr_lib/hb/mac.v b/usrp2/sdr_lib/hb/mac.v new file mode 100644 index 000000000..5a270bc73 --- /dev/null +++ b/usrp2/sdr_lib/hb/mac.v @@ -0,0 +1,58 @@ + + +module mac (input clock, input reset, input enable, input clear, + input signed [15:0] x, input signed [15:0] y, + input [7:0] shift, output [15:0] z ); + + reg signed [30:0] product; + reg signed [39:0] z_int; + reg signed [15:0] z_shift; + + reg enable_d1; + always @(posedge clock) + enable_d1 <= #1 enable; + + always @(posedge clock) + if(reset | clear) + z_int <= #1 40'd0; + else if(enable_d1) + z_int <= #1 z_int + {{9{product[30]}},product}; + + always @(posedge clock) + product <= #1 x*y; + + always @* // FIXME full case? parallel case? + case(shift) + //8'd0 : z_shift <= z_int[39:24]; + //8'd1 : z_shift <= z_int[38:23]; + //8'd2 : z_shift <= z_int[37:22]; + //8'd3 : z_shift <= z_int[36:21]; + //8'd4 : z_shift <= z_int[35:20]; + //8'd5 : z_shift <= z_int[34:19]; + 8'd6 : z_shift <= z_int[33:18]; + 8'd7 : z_shift <= z_int[32:17]; + 8'd8 : z_shift <= z_int[31:16]; + 8'd9 : z_shift <= z_int[30:15]; + 8'd10 : z_shift <= z_int[29:14]; + 8'd11 : z_shift <= z_int[28:13]; + //8'd12 : z_shift <= z_int[27:12]; + //8'd13 : z_shift <= z_int[26:11]; + //8'd14 : z_shift <= z_int[25:10]; + //8'd15 : z_shift <= z_int[24:9]; + //8'd16 : z_shift <= z_int[23:8]; + //8'd17 : z_shift <= z_int[22:7]; + //8'd18 : z_shift <= z_int[21:6]; + //8'd19 : z_shift <= z_int[20:5]; + //8'd20 : z_shift <= z_int[19:4]; + //8'd21 : z_shift <= z_int[18:3]; + //8'd22 : z_shift <= z_int[17:2]; + //8'd23 : z_shift <= z_int[16:1]; + //8'd24 : z_shift <= z_int[15:0]; + default : z_shift <= z_int[15:0]; + endcase // case(shift) + + // FIXME do we need to saturate? + //assign z = z_shift; + assign z = z_int[15:0]; + +endmodule // mac diff --git a/usrp2/sdr_lib/hb/mult.v b/usrp2/sdr_lib/hb/mult.v new file mode 100644 index 000000000..a8d4cb1b7 --- /dev/null +++ b/usrp2/sdr_lib/hb/mult.v @@ -0,0 +1,16 @@ + + +module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, + input enable_in, output reg enable_out ); + + always @(posedge clock) + if(enable_in) + product <= #1 x*y; + else + product <= #1 31'd0; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // mult + diff --git a/usrp2/sdr_lib/hb/ram16_2port.v b/usrp2/sdr_lib/hb/ram16_2port.v new file mode 100644 index 000000000..e1761a926 --- /dev/null +++ b/usrp2/sdr_lib/hb/ram16_2port.v @@ -0,0 +1,22 @@ + + +module ram16_2port (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr1, output reg [15:0] rd_data1, + input [3:0] rd_addr2, output reg [15:0] rd_data2); + + reg [15:0] ram_array [0:31]; + + always @(posedge clock) + rd_data1 <= #1 ram_array[rd_addr1]; + + always @(posedge clock) + rd_data2 <= #1 ram_array[rd_addr2]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram16_2port + + diff --git a/usrp2/sdr_lib/hb/ram16_2sum.v b/usrp2/sdr_lib/hb/ram16_2sum.v new file mode 100644 index 000000000..559b06fd5 --- /dev/null +++ b/usrp2/sdr_lib/hb/ram16_2sum.v @@ -0,0 +1,27 @@ + + +module ram16_2sum (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr1, input [3:0] rd_addr2, + output reg [15:0] sum); + + reg signed [15:0] ram_array [0:15]; + reg signed [15:0] a,b; + wire signed [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + always @(posedge clock) + begin + a <= #1 ram_array[rd_addr1]; + b <= #1 ram_array[rd_addr2]; + end + + assign sum_int = {a[15],a} + {b[15],b}; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + +endmodule // ram16_2sum diff --git a/usrp2/sdr_lib/hb/ram32_2sum.v b/usrp2/sdr_lib/hb/ram32_2sum.v new file mode 100644 index 000000000..d1f55b7d0 --- /dev/null +++ b/usrp2/sdr_lib/hb/ram32_2sum.v @@ -0,0 +1,22 @@ + + +module ram32_2sum (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr1, input [4:0] rd_addr2, + output reg [15:0] sum); + + reg [15:0] ram_array [0:31]; + wire [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + + +endmodule // ram32_2sum + diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v new file mode 100644 index 000000000..8fb5ba222 --- /dev/null +++ b/usrp2/sdr_lib/hb_dec.v @@ -0,0 +1,171 @@ +// Final halfband decimator +// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] +// Strobe in cannot come faster than every 2nd clock cycle +// These taps designed by halfgen4 from ldoolittle +// myfilt = round(2^18 * halfgen4(.7/4,8)) + +module hb_dec + #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=24) + (input clk, + input rst, + input bypass, + input run, + input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block + input stb_in, + input [IWIDTH-1:0] data_in, + output reg stb_out, + output reg [OWIDTH-1:0] data_out); + + // Control + reg [3:0] addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d; + wire write_odd, write_even, do_mult; + reg odd; + reg [2:0] phase, phase_d1; + reg stb_out_int; + wire clear, do_acc; + assign do_mult = 1; + + always @(posedge clk) + if(rst | ~run) + odd <= 0; + else if(stb_in) + odd <= ~odd; + + assign write_odd = stb_in & odd; + assign write_even = stb_in & ~odd; + + always @(posedge clk) + if(rst | ~run) + phase <= 0; + else if(stb_in & odd) + phase <= 1; + else if(phase == 4) + phase <= 0; + else if(phase != 0) + phase <= phase + 1; + + always @(posedge clk) + phase_d1 <= phase; + + reg [15:0] stb_out_pre; + always @(posedge clk) + if(rst) + stb_out_pre <= 0; + else + stb_out_pre <= {stb_out_pre[14:0],(stb_in & odd)}; + + always @* + case(phase) + 1 : begin addr_odd_a = 0; addr_odd_b = 15; end + 2 : begin addr_odd_a = 1; addr_odd_b = 14; end + 3 : begin addr_odd_a = 2; addr_odd_b = 13; end + 4 : begin addr_odd_a = 3; addr_odd_b = 12; end + default : begin addr_odd_a = 0; addr_odd_b = 15; end + endcase // case(phase) + + always @* + case(phase) + 1 : begin addr_odd_c = 4; addr_odd_d = 11; end + 2 : begin addr_odd_c = 5; addr_odd_d = 10; end + 3 : begin addr_odd_c = 6; addr_odd_d = 9; end + 4 : begin addr_odd_c = 7; addr_odd_d = 8; end + default : begin addr_odd_c = 4; addr_odd_d = 11; end + endcase // case(phase) + + assign do_acc = |stb_out_pre[6:3]; + assign clear = stb_out_pre[3]; + + // Data + wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d; + wire [IWIDTH-1:0] sum1, sum2; + wire [OWIDTH-1:0] final_sum; + reg [CWIDTH-1:0] coeff1, coeff2; + wire [35:0] prod1, prod2; + + always @* // Outer coeffs + case(phase_d1) + 1 : coeff1 = -107; + 2 : coeff1 = 445; + 3 : coeff1 = -1271; + 4 : coeff1 = 2959; + default : coeff1 = -107; + endcase // case(phase) + + always @* // Inner coeffs + case(phase_d1) + 1 : coeff2 = -6107; + 2 : coeff2 = 11953; + 3 : coeff2 = -24706; + 4 : coeff2 = 82359; + default : coeff2 = -6107; + endcase // case(phase) + + srl #(.WIDTH(IWIDTH)) srl_odd_a + (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_a),.out(data_odd_a)); + srl #(.WIDTH(IWIDTH)) srl_odd_b + (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_b),.out(data_odd_b)); + srl #(.WIDTH(IWIDTH)) srl_odd_c + (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_c),.out(data_odd_c)); + srl #(.WIDTH(IWIDTH)) srl_odd_d + (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d)); + + add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1)); + add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2)); + + wire [IWIDTH-1:0] data_even; + reg [3:0] addr_even; + + always @(posedge clk) + case(cpi) + // 1 is an error + 2 : addr_even <= 9; // Maximum speed (overall decim by 4) + 3, 4, 5, 6, 7 : addr_even <= 8; + default : addr_even <= 7; + endcase // case(cpi) + + srl #(.WIDTH(IWIDTH)) srl_even + (.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even)); + + localparam MWIDTH = ACCWIDTH-2; + wire [MWIDTH-1:0] sum_of_prod; + + MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); + MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); + add2_and_round_reg #(.WIDTH(MWIDTH)) + add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod)); + + wire [ACCWIDTH-1:0] acc_out; + + acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) + acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out)); + + localparam SHIFT_FACTOR = ACCWIDTH-IWIDTH-5; + wire [ACCWIDTH-1:0] data_even_signext; + wire [ACCWIDTH:0] final_sum_unrounded; + + sign_extend #(.bits_in(IWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) + signext_data_even (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR])); + assign data_even_signext[SHIFT_FACTOR-1:0] = 0; + + add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1)) + final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded)); + + round_reg #(.bits_in(ACCWIDTH-4),.bits_out(OWIDTH)) + final_round (.clk(clk),.in(final_sum_unrounded[ACCWIDTH-5:0]),.out(final_sum)); + + // Output + always @(posedge clk) + if(bypass) + data_out <= data_in; + else if(stb_out_pre[9]) + data_out <= final_sum; + + always @(posedge clk) + if(rst) + stb_out <= 0; + else if(bypass) + stb_out <= stb_in; + else + stb_out <= stb_out_pre[9]; + +endmodule // hb_dec diff --git a/usrp2/sdr_lib/hb_dec_tb.v b/usrp2/sdr_lib/hb_dec_tb.v new file mode 100644 index 000000000..3e5faa80a --- /dev/null +++ b/usrp2/sdr_lib/hb_dec_tb.v @@ -0,0 +1,140 @@ +module hb_dec_tb( ) ; + + // Parameters for instantiation + parameter clocks = 9'd2 ; // Number of clocks per input + parameter decim = 1 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + reg strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + initial + begin + $dumpfile("hb_dec_tb.vcd"); + $dumpvars(0,hb_dec_tb); + end + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #1000 reset = 1'b0 ; + + // Enable the entire system + initial enable = 1'b1 ; + + // Instantiate UUT + /* + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + */ + + + hb_dec #(.IWIDTH(18),.OWIDTH(18),.CWIDTH(18),.ACCWIDTH(24)) uut + (.clk(clock),.rst(reset),.bypass(0),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in), + .stb_out(strobe_out),.data_out(data_out) ); + + integer i, ri, ro, infile, outfile ; + + always @(posedge clock) + begin + if(strobe_out) + $display(data_out); + end + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + strobe_in <= 1'd0 ; + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( posedge clock ) begin + //#1 ; + strobe_in <= 1'b1 ; + if( !$feof(infile) ) + ri = $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + + // Clocked in - set the strobe to 0 if the number of + // clocks per sample is greater than 1 + if( clocks > 1 ) begin + @(posedge clock) begin + strobe_in <= 1'b0 ; + end + + // Wait for the specified number of cycles + for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin + @(posedge clock) #1 ; + end + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $finish ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + //$display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + endofsim <= 1'b1 ; + end + end + end + +endmodule // hb_dec_tb + diff --git a/usrp2/sdr_lib/hb_interp.v b/usrp2/sdr_lib/hb_interp.v new file mode 100644 index 000000000..d16807e15 --- /dev/null +++ b/usrp2/sdr_lib/hb_interp.v @@ -0,0 +1,157 @@ +// First halfband iterpolator +// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] +// Strobe in cannot come faster than every 4th clock cycle, +// Strobe out cannot come faster than every 2nd clock cycle + +// These taps designed by halfgen4 from ldoolittle +// myfilt = round(2^18 * halfgen4(.7/4,8)) + +module hb_interp + #(parameter IWIDTH=18, OWIDTH=18, ACCWIDTH=24) + (input clk, + input rst, + input bypass, + input [7:0] cpo, // Clocks per output, must be at least 2 + input stb_in, + input [IWIDTH-1:0] data_in, + input stb_out, + output reg [OWIDTH-1:0] data_out); + + localparam MWIDTH = ACCWIDTH-2; + localparam CWIDTH = 18; + + reg [CWIDTH-1:0] coeff1, coeff2; + reg [3:0] addr_a, addr_b, addr_c, addr_d, addr_e; + wire [IWIDTH-1:0] data_a, data_b, data_c, data_d, data_e, sum1, sum2; + wire [35:0] prod1, prod2; + + reg [2:0] phase, phase_d1, phase_d2, phase_d3, phase_d4, phase_d5; + + always @(posedge clk) + if(rst) + phase <= 0; + else + if(stb_in) + phase <= 1; + else if(phase==4) + phase <= 0; + else if(phase!=0) + phase <= phase + 1; + always @(posedge clk) phase_d1 <= phase; + always @(posedge clk) phase_d2 <= phase_d1; + always @(posedge clk) phase_d3 <= phase_d2; + always @(posedge clk) phase_d4 <= phase_d3; + always @(posedge clk) phase_d5 <= phase_d4; + + srl #(.WIDTH(IWIDTH)) srl_a + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_a),.out(data_a)); + srl #(.WIDTH(IWIDTH)) srl_b + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_b),.out(data_b)); + srl #(.WIDTH(IWIDTH)) srl_c + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_c),.out(data_c)); + srl #(.WIDTH(IWIDTH)) srl_d + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_d),.out(data_d)); + srl #(.WIDTH(IWIDTH)) srl_e + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_e),.out(data_e)); + + always @* + case(phase) + 1 : begin addr_a = 0; addr_b = 15; end + 2 : begin addr_a = 1; addr_b = 14; end + 3 : begin addr_a = 2; addr_b = 13; end + 4 : begin addr_a = 3; addr_b = 12; end + default : begin addr_a = 0; addr_b = 15; end + endcase // case(phase) + + always @* + case(phase) + 1 : begin addr_c = 4; addr_d = 11; end + 2 : begin addr_c = 5; addr_d = 10; end + 3 : begin addr_c = 6; addr_d = 9; end + 4 : begin addr_c = 7; addr_d = 8; end + default : begin addr_c = 4; addr_d = 11; end + endcase // case(phase) + + always @* + case(cpo) + 2 : addr_e <= 9; + 3,4,5,6,7,8 : addr_e <= 8; + default : addr_e <= 7; // This case works for 256, which = 0 due to overflow outside this block + endcase // case(cpo) + + always @* // Outer coeffs + case(phase_d1) + 1 : coeff1 = -107; + 2 : coeff1 = 445; + 3 : coeff1 = -1271; + 4 : coeff1 = 2959; + default : coeff1 = -107; + endcase // case(phase) + + always @* // Inner coeffs + case(phase_d1) + 1 : coeff2 = -6107; + 2 : coeff2 = 11953; + 3 : coeff2 = -24706; + 4 : coeff2 = 82359; + default : coeff2 = -6107; + endcase // case(phase) + + add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_a),.in2(data_b),.sum(sum1)); + add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_c),.in2(data_d),.sum(sum2)); + // sum1, sum2 available on phase_d1 + + wire do_mult = 1; + MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); + MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); + // prod1, prod2 available on phase_d2 + + wire [MWIDTH-1:0] sum_of_prod; + + add2_and_round_reg #(.WIDTH(MWIDTH)) + add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod)); + // sum_of_prod available on phase_d3 + + wire [ACCWIDTH-1:0] acc_out; + wire [OWIDTH-1:0] acc_round; + + wire clear = (phase_d3 == 1); + wire do_acc = (phase_d3 != 0); + + acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) + acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out)); + // acc_out available on phase_d4 + + wire [ACCWIDTH-6:0] clipped_acc; + clip #(.bits_in(ACCWIDTH),.bits_out(ACCWIDTH-5)) final_clip(.in(acc_out),.out(clipped_acc)); + + reg [ACCWIDTH-6:0] clipped_reg; + always @(posedge clk) + if(phase_d4 == 4) + clipped_reg <= clipped_acc; + // clipped_reg available on phase_d5 + + wire [OWIDTH-1:0] data_out_round; + round #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH)) final_round (.in(clipped_reg),.out(data_out_round)); + + reg odd; + always @(posedge clk) + if(rst) + odd <= 0; + else if(stb_in) + odd <= 0; + else if(stb_out) + odd <= 1; + + always @(posedge clk) + if(bypass) + data_out <= data_in; + else if(stb_out) + if(odd) + data_out <= data_e; + else + data_out <= data_out_round; + + // data_out available on phase_d6 + +endmodule // hb_interp diff --git a/usrp2/sdr_lib/hb_interp_tb.v b/usrp2/sdr_lib/hb_interp_tb.v new file mode 100644 index 000000000..52f137f28 --- /dev/null +++ b/usrp2/sdr_lib/hb_interp_tb.v @@ -0,0 +1,132 @@ +module hb_interp_tb( ) ; + + // Parameters for instantiation + parameter clocks = 8'd2 ; // Number of clocks per output + parameter decim = 1 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + wire strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + initial + begin + $dumpfile("hb_interp_tb.vcd"); + $dumpvars(0,hb_interp_tb); + end + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #1000 reset = 1'b0 ; + + always @(posedge clock) + enable <= ~reset; + + // Instantiate UUT + /* + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + */ + + cic_strober #(.WIDTH(8)) + out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks), + .strobe_fast(1),.strobe_slow(strobe_out) ); + + cic_strober #(.WIDTH(8)) + in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2), + .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); + + hb_interp #() uut + (.clk(clock),.rst(reset),.bypass(0),.cpo(clocks),.stb_in(strobe_in),.data_in(data_in), + .stb_out(strobe_out),/* .output_rate(clocks), */ .data_out(data_out) ); + + integer i, ri, ro, infile, outfile ; + + always @(posedge clock) + begin + if(strobe_out) + $display(data_out); + end + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( negedge clock ) begin + if(strobe_in) + if( !$feof(infile) ) + ri <= #1 $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $finish ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + //$display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + if($feof(infile)) + endofsim <= 1'b1 ; + end + end + end + +endmodule // small_hb_int_tb diff --git a/usrp2/sdr_lib/hb_tb.v b/usrp2/sdr_lib/hb_tb.v new file mode 100644 index 000000000..7e960fd13 --- /dev/null +++ b/usrp2/sdr_lib/hb_tb.v @@ -0,0 +1,155 @@ + +module hb_tb(); + + localparam SWIDTH = 17; + localparam CWIDTH = 18; + localparam TWIDTH = 20; + localparam ACC_WIDTH = 40; + + reg clk = 0, rst = 1; + wire strobe_in, strobe_out; + reg [SWIDTH-1:0] sample_in; + wire signed [SWIDTH:0] sample_out; + + reg set_stb; + reg [7:0] set_addr; + reg [31:0] set_data; + + localparam DECIM = 3; + + initial $dumpfile("hb_tb.vcd"); + initial $dumpvars(0,hb_tb); + + always #5 clk <= ~clk; + initial + begin + @(posedge clk); + @(negedge clk); + rst <= 0; + end + + reg [7:0] stb_counter; + always @(posedge clk) + if(rst) + stb_counter <= 0; + else + if(stb_counter == 0) + stb_counter <= DECIM; + else + stb_counter <= stb_counter - 1; + assign strobe_in = (stb_counter == 0); + + hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH), + .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim + (.clk(clk), .rst(rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .sample_in(sample_in), + .strobe_in(strobe_in), + .sample_out(sample_out), + .strobe_out(strobe_out) + ); + + initial + begin : load_coeffs + @(negedge rst); + @(posedge clk); + set_addr <= 124; // load coeffs + set_stb <= 1; + set_data <= -18'd49; + @(posedge clk); + set_data <= 18'd165; + @(posedge clk); + set_data <= -18'd412; + @(posedge clk); + set_data <= 18'd873; + @(posedge clk); + set_data <= -18'd1681; + @(posedge clk); + set_data <= 18'd3135; + @(posedge clk); + set_data <= -18'd6282; + @(posedge clk); + set_data <= 18'd20628; + @(posedge clk); + set_addr <=125; // load table + // { stb_out, accum, load_accum, done, even_addr, odd_addr_a, odd_addr_b, coeff_addr } + set_data <= {1'b1,1'b1,1'b0,1'b1,4'd15,4'd15,4'd0,4'd0}; // Phase 8 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd14,4'd1,4'd1}; // Phase 7 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd13,4'd2,4'd2}; // Phase 6 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd12,4'd3,4'd3}; // Phase 5 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd11,4'd4,4'd4}; // Phase 4 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd10,4'd5,4'd5}; // Phase 3 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd9,4'd6,4'd6}; // Phase 2 + @(posedge clk); + set_data <= {1'b0,1'b0,1'b1,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 1 + @(posedge clk); + set_data <= {1'b0,1'b0,1'b0,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 0 + @(posedge clk); + set_stb <= 0; + end // block: load_coeffs + + initial + begin + sample_in <= 0; + repeat(40) + @(posedge strobe_in); + $display("EVEN"); + sample_in <= 0; + repeat(10) + @(posedge strobe_in); + sample_in <= 1; + @(posedge strobe_in); + sample_in <= 0; + repeat(40) + @(posedge strobe_in); + sample_in <= 1; + repeat(40) + @(posedge strobe_in); + sample_in <= 0; + repeat(60) + @(posedge strobe_in); + sample_in <= 1; + repeat(2) + @(posedge strobe_in); + sample_in <= 0; + repeat(60) + @(posedge strobe_in); + $display("ODD"); + sample_in <= 0; + repeat(10) + @(posedge strobe_in); + sample_in <= 1; + @(posedge strobe_in); + sample_in <= 0; + repeat(40) + @(posedge strobe_in); + sample_in <= 1; + repeat(40) + @(posedge strobe_in); + sample_in <= 0; + repeat(60) + @(posedge strobe_in); + sample_in <= 1; + repeat(2) + @(posedge strobe_in); + sample_in <= 0; + repeat(60) + @(posedge strobe_in); + $finish; + end + + always @(posedge clk) + if(strobe_in) + $display(sample_in); + + always @(posedge clk) + if(strobe_out) + $display("\t",sample_out); + +endmodule // hb_tb diff --git a/usrp2/sdr_lib/input.dat b/usrp2/sdr_lib/input.dat new file mode 100644 index 000000000..1e649ac2e --- /dev/null +++ b/usrp2/sdr_lib/input.dat @@ -0,0 +1,341 @@ +0 +0 +0 +0 +0 +0 +0 +0 +-131072 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +131071 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +100000 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +-131072 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/usrp2/sdr_lib/integrate.v b/usrp2/sdr_lib/integrate.v new file mode 100644 index 000000000..db33de979 --- /dev/null +++ b/usrp2/sdr_lib/integrate.v @@ -0,0 +1,38 @@ +module integrate + #(parameter INPUTW = 16, + parameter ACCUMW = 32, + parameter OUTPUTW = 16) + + (input clk_i, + input rst_i, + input ena_i, + + input dump_i, + input [INPUTW-1:0] data_i, + + output reg stb_o, + output reg [OUTPUTW-1:0] integ_o + ); + + wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i}; + reg [ACCUMW-1:0] accum; + + always @(posedge clk_i) + if (rst_i | ~ena_i) + begin + accum <= 0; + integ_o <= 0; + end + else + if (dump_i) + begin + integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW]; + accum <= data_ext; + end + else + accum <= accum + data_ext; + + always @(posedge clk_i) + stb_o <= dump_i; + +endmodule // integrate diff --git a/usrp2/sdr_lib/med_hb_int.v b/usrp2/sdr_lib/med_hb_int.v new file mode 100644 index 000000000..bc8066509 --- /dev/null +++ b/usrp2/sdr_lib/med_hb_int.v @@ -0,0 +1,95 @@ +// Medium halfband decimator (intended to be followed by another stage) +// Implements impulse responses of the form [A 0 B 0 C 0 D 0.5 D 0 C 0 B 0 A] +// +// These taps designed by halfgen_test: +// 2 * 131072 * halfgen_test(.8/8,4,1) +// -597, 0, 4283, 0, -17516, 0, 79365, 131072, 79365, 0, -17516, 0, 4283, 0, -597 + + +module med_hb_int + #(parameter WIDTH=18) + (input clk, + input rst, + input bypass, + input stb_in, + input [WIDTH-1:0] data_in, + input [7:0] output_rate, + input stb_out, + output reg [WIDTH-1:0] data_out); + + localparam coeff_a = -597; + localparam coeff_b = 4283; + localparam coeff_c = -17516; + localparam coeff_d = 79365; + + reg phase; + reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6, d7, d8; + + localparam MWIDTH = 36; + wire [MWIDTH-1:0] prod; + + reg [6:0] stbin_d; + + always @(posedge clk) + stbin_d <= {stbin_d[5:0],stb_in}; + + always @(posedge clk) + if(stb_in) + begin + d1 <= data_in; + d2 <= d1; + d3 <= d2; + d4 <= d3; + d5 <= d4; + d6 <= d5; + d7 <= d6; + d8 <= d7; + end + + wire [WIDTH-1:0] sum_a, sum_b, sum_c, sum_d; + add2_and_round_reg #(.WIDTH(WIDTH)) add_a (.clk(clk),.in1(d1),.in2(d8),.sum(sum_a)); + add2_and_round_reg #(.WIDTH(WIDTH)) add_b (.clk(clk),.in1(d2),.in2(d7),.sum(sum_b)); + add2_and_round_reg #(.WIDTH(WIDTH)) add_c (.clk(clk),.in1(d3),.in2(d6),.sum(sum_c)); + add2_and_round_reg #(.WIDTH(WIDTH)) add_d (.clk(clk),.in1(d4),.in2(d5),.sum(sum_d)); + + MULT18X18S mult1(.C(clk), .CE(1), .R(rst), .P(prod1), .A(stbin_d[1] ? coeff_a : coeff_b), + .B(stbin_d[1] ? sum_a : sum_b) ); + MULT18X18S mult2(.C(clk), .CE(1), .R(rst), .P(prod2), .A(stbin_d[1] ? coeff_c : coeff_d), + .B(stbin_d[1] ? sum_c : sum_d) ); + + wire [MWIDTH:0] accum; + acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) + acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum)); + + wire [WIDTH+2:0] accum_rnd; + round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3)) + final_round (.clk(clk),.in(accum),.out(accum_rnd)); + + wire [WIDTH-1:0] clipped; + clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) + final_clip (.clk(clk),.in(accum_rnd),.out(clipped)); + + reg [WIDTH-1:0] saved, saved_d3; + always @(posedge clk) + if(stbin_d[6]) + saved <= clipped; + + always @(posedge clk) + if(stbin_d[3]) + saved_d3 <= d3; + + always @(posedge clk) + if(bypass) + data_out <= data_in; + else if(stb_in & stb_out) + case(output_rate) + 1 : data_out <= d6; + 2 : data_out <= d4; + 3, 4, 5, 6, 7 : data_out <= d3; + default : data_out <= d2; + endcase // case(output_rate) + else if(stb_out) + data_out <= saved; + +endmodule // small_hb_int + diff --git a/usrp2/sdr_lib/output.dat b/usrp2/sdr_lib/output.dat new file mode 100644 index 000000000..15db3ced4 --- /dev/null +++ b/usrp2/sdr_lib/output.dat @@ -0,0 +1,130 @@ +-1390 +0 +1604 +0 +-1896 +0 +2317 +0 +-2979 +0 +4172 +0 +-6953 +0 +20860 +32768 +20860 +0 +-6953 +0 +4172 +0 +-2979 +0 +2317 +0 +-1896 +0 +1604 +0 +-1390 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 + diff --git a/usrp2/sdr_lib/round.v b/usrp2/sdr_lib/round.v new file mode 100644 index 000000000..c4f9ec9cd --- /dev/null +++ b/usrp2/sdr_lib/round.v @@ -0,0 +1,33 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Rounding "macro" +// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation) + +module round + #(parameter bits_in=0, + parameter bits_out=0) + (input [bits_in-1:0] in, + output [bits_out-1:0] out); + + assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]); + +endmodule // round diff --git a/usrp2/sdr_lib/round_reg.v b/usrp2/sdr_lib/round_reg.v new file mode 100644 index 000000000..aa0972dab --- /dev/null +++ b/usrp2/sdr_lib/round_reg.v @@ -0,0 +1,39 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2008 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Rounding "macro" +// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero) + +module round_reg + #(parameter bits_in=0, + parameter bits_out=0) + (input clk, + input [bits_in-1:0] in, + output reg [bits_out-1:0] out); + + wire [bits_out-1:0] temp; + + round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp)); + + always @(posedge clk) + out <= temp; + +endmodule // round diff --git a/usrp2/sdr_lib/rssi.v b/usrp2/sdr_lib/rssi.v new file mode 100644 index 000000000..e45e2148c --- /dev/null +++ b/usrp2/sdr_lib/rssi.v @@ -0,0 +1,30 @@ + + +module rssi (input clock, input reset, input enable, + input [11:0] adc, output [15:0] rssi, output [15:0] over_count); + + wire over_hi = (adc == 12'h7FF); + wire over_lo = (adc == 12'h800); + wire over = over_hi | over_lo; + + reg [25:0] over_count_int; + always @(posedge clock) + if(reset | ~enable) + over_count_int <= #1 26'd0; + else + over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10]; + + assign over_count = over_count_int[25:10]; + + wire [11:0] abs_adc = adc[11] ? ~adc : adc; + + reg [25:0] rssi_int; + always @(posedge clock) + if(reset | ~enable) + rssi_int <= #1 26'd0; + else + rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10]; + + assign rssi = rssi_int[25:10]; + +endmodule // rssi diff --git a/usrp2/sdr_lib/rx_control.v b/usrp2/sdr_lib/rx_control.v new file mode 100644 index 000000000..0adeb0794 --- /dev/null +++ b/usrp2/sdr_lib/rx_control.v @@ -0,0 +1,180 @@ + +`define DSP_CORE_RX_BASE 160 + +module rx_control + #(parameter FIFOSIZE = 10) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [31:0] master_time, + output overrun, + + // To FIFO interface of Buffer Pool + output [31:0] wr_dat_o, + output [3:0] wr_flags_o, + input wr_ready_i, + output wr_ready_o, + + // From DSP Core + input [31:0] sample, + output run, + input strobe, + + // FIFO Levels + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty, + + // Debug + output [31:0] debug_rx + ); + + wire [31:0] new_time, new_command; + wire sc_pre1, clear_overrun; + wire [31:0] rcvtime_pre; + reg [31:0] rcvtime; + wire [8:0] lines_per_frame; + wire [20:0] numlines; + wire send_imm_pre, chain_pre; + reg send_imm, chain; + wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl; + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(new_time),.changed(sc_pre1)); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+4)) sr_4 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(new_command),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+5)) sr_5 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_overrun)); + + reg sc_pre2; + always @(posedge clk) + sc_pre2 <= sc_pre1; + assign write_ctrl = sc_pre1 & ~sc_pre2; + + shortfifo #(.WIDTH(64)) commandfifo + (.clk(clk),.rst(rst),.clear(clear_overrun), + .datain({new_command,new_time}), .write(write_ctrl), .full(full_ctrl), + .dataout({send_imm_pre,chain_pre,numlines,lines_per_frame,rcvtime_pre}), + .read(read_ctrl), .empty(empty_ctrl) ); + + // Buffer interface to internal FIFO + wire have_space, write; + wire [35:0] fifo_line; + + // Internal FIFO, size 9 is 2K, size 10 is 4K + fifo_cascade #(.WIDTH(36),.SIZE(FIFOSIZE)) rxfifo + (.clk(clk),.reset(rst),.clear(clear_overrun), + .datain(fifo_line), .src_rdy_i(write), .dst_rdy_o(have_space), + .dataout({wr_flags_o,wr_dat_o}), .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), + .space(),.occupied(fifo_occupied) ); + assign fifo_full = ~have_space; + assign fifo_empty = ~wr_ready_o; + + // Internal FIFO to DSP interface + reg [22:0] lines_left; + reg [8:0] lines_left_frame; + localparam IBS_IDLE = 0; + localparam IBS_WAITING = 1; + localparam IBS_FIRSTLINE = 2; + localparam IBS_RUNNING = 3; + localparam IBS_OVERRUN = 4; + + reg [2:0] ibs_state; + + wire [32:0] delta_time = {1'b0,rcvtime}-{1'b0,master_time}; + wire too_late = (delta_time[32:31] == 2'b11) & ~send_imm; + wire go_now = send_imm | ( master_time == rcvtime ); + + always @(posedge clk) + if(rst) + begin + ibs_state <= IBS_IDLE; + lines_left <= 0; + lines_left_frame <= 0; + rcvtime <= 0; + send_imm <= 0; + chain <= 0; + end + else + if(clear_overrun) + begin + ibs_state <= IBS_IDLE; + lines_left <= 0; + lines_left_frame <= 0; + rcvtime <= 0; + send_imm <= 0; + chain <= 0; + end + else + case(ibs_state) + IBS_IDLE : + if(~empty_ctrl) + begin + lines_left <= numlines; + lines_left_frame <= lines_per_frame; + rcvtime <= rcvtime_pre; + ibs_state <= IBS_WAITING; + send_imm <= send_imm_pre; + chain <= chain_pre; + end + IBS_WAITING : + if(go_now) + ibs_state <= IBS_FIRSTLINE; + else if(too_late) + ibs_state <= IBS_OVERRUN; + IBS_FIRSTLINE : + if(~have_space | strobe) + ibs_state <= IBS_OVERRUN; + else + ibs_state <= IBS_RUNNING; + IBS_RUNNING : + if(strobe) + if(~have_space) + ibs_state <= IBS_OVERRUN; + else + begin + lines_left <= lines_left - 1; + if(lines_left == 1) + if(~chain) + ibs_state <= IBS_IDLE; + else if(empty_ctrl) + ibs_state <= IBS_OVERRUN; + else + begin + lines_left <= numlines; + lines_left_frame <= lines_per_frame; + rcvtime <= rcvtime_pre; + ibs_state <= IBS_FIRSTLINE; + send_imm <= send_imm_pre; + chain <= chain_pre; + end + else if(lines_left_frame == 1) + begin + lines_left_frame <= lines_per_frame; + ibs_state <= IBS_FIRSTLINE; + end + else + lines_left_frame <= lines_left_frame - 1; + end // else: !if(~have_space) + endcase // case(ibs_state) + + assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {2'b0,1'b0,1'b1,master_time} : + {2'b0,((lines_left==1)|(lines_left_frame==1)),1'b0,sample}; + + assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & have_space; // & (ibs_state == IBS_RUNNING) should strobe only when running + assign overrun = (ibs_state == IBS_OVERRUN); + assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE); + assign read_ctrl = ( (ibs_state == IBS_IDLE) | + ((ibs_state == IBS_RUNNING) & strobe & have_space & (lines_left==1) & chain) ) + & ~empty_ctrl; + + assign debug_rx = { 8'd0, + 1'd0, send_imm, chain, wr_ready_i,wr_ready_o, 2'b0, run, + write,have_space,wr_flags_o[1:0],write_ctrl,full_ctrl,read_ctrl,empty_ctrl, + sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] }; +endmodule // rx_control diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v new file mode 100644 index 000000000..bedbd40e6 --- /dev/null +++ b/usrp2/sdr_lib/rx_dcoffset.v @@ -0,0 +1,43 @@ + + +module rx_dcoffset + #(parameter WIDTH=14, + parameter ADDR=8'd0) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out); + + // Because of some extra delays to make timing easier, the transfer function is: + // (z-1)/(z^2-z-alpha) where alpha is 1/2^n + + wire set_now = set_stb & (ADDR == set_addr); + + reg fixed; // uses fixed offset + wire signed [WIDTH-1:0] fixed_dco; + reg signed [31:0] integrator; + + always @(posedge clk) + if(rst) + begin + fixed <= 0; + integrator <= 32'd0; + end + else if(set_now) + begin + integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}}; + fixed <= set_data[31]; + end + else if(~fixed) + integrator <= integrator + adc_out; + + wire [WIDTH:0] scaled_integrator; + + round #(.bits_in(33),.bits_out(15)) round (.in({integrator[31],integrator}),.out(scaled_integrator)); + + wire [WIDTH:0] adc_out_int = {adc_in[WIDTH-1],adc_in} - scaled_integrator; + + clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc + (.clk(clk),.in(adc_out_int),.out(adc_out)); + + +endmodule // rx_dcoffset diff --git a/usrp2/sdr_lib/rx_dcoffset_tb.v b/usrp2/sdr_lib/rx_dcoffset_tb.v new file mode 100644 index 000000000..a8b4ec20f --- /dev/null +++ b/usrp2/sdr_lib/rx_dcoffset_tb.v @@ -0,0 +1,25 @@ + +`timescale 1ns/1ns +module rx_dcoffset_tb(); + + reg clk, rst; + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #5 clk = ~clk; + + initial $dumpfile("rx_dcoffset_tb.vcd"); + initial $dumpvars(0,rx_dcoffset_tb); + + reg [13:0] adc_in = 7; + wire [13:0] adc_out; + + always @(posedge clk) + $display("%d\t%d",adc_in,adc_out); + + rx_dcoffset #(.WIDTH(14),.ADDR(0)) + rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0), + .adc_in(adc_in),.adc_out(adc_out)); + +endmodule // longfifo_tb diff --git a/usrp2/sdr_lib/sign_extend.v b/usrp2/sdr_lib/sign_extend.v new file mode 100644 index 000000000..eae67faf2 --- /dev/null +++ b/usrp2/sdr_lib/sign_extend.v @@ -0,0 +1,35 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// Sign extension "macro" +// bits_out should be greater than bits_in + +module sign_extend (in,out); + parameter bits_in=0; // FIXME Quartus insists on a default + parameter bits_out=0; + + input [bits_in-1:0] in; + output [bits_out-1:0] out; + + assign out = {{(bits_out-bits_in){in[bits_in-1]}},in}; + +endmodule diff --git a/usrp2/sdr_lib/small_hb_dec.v b/usrp2/sdr_lib/small_hb_dec.v new file mode 100644 index 000000000..8519b628a --- /dev/null +++ b/usrp2/sdr_lib/small_hb_dec.v @@ -0,0 +1,111 @@ +// Short halfband decimator (intended to be followed by another stage) +// Implements impulse responses of the form [A 0 B 0.5 B 0 A] +// +// These taps designed by halfgen4 from ldoolittle: +// 2 * 131072 * halfgen4(.75/8,2) +module small_hb_dec + #(parameter WIDTH=18) + (input clk, + input rst, + input bypass, + input run, + input stb_in, + input [WIDTH-1:0] data_in, + output reg stb_out, + output [WIDTH-1:0] data_out); + + reg stb_in_d1; + reg [WIDTH-1:0] data_in_d1; + always @(posedge clk) stb_in_d1 <= stb_in; + always @(posedge clk) data_in_d1 <= data_in; + + wire go; + reg phase, go_d1, go_d2, go_d3, go_d4; + always @(posedge clk) + if(rst | ~run) + phase <= 0; + else if(stb_in_d1) + phase <= ~phase; + assign go = stb_in_d1 & phase; + always @(posedge clk) + if(rst | ~run) + begin + go_d1 <= 0; + go_d2 <= 0; + go_d3 <= 0; + go_d4 <= 0; + end + else + begin + go_d1 <= go; + go_d2 <= go_d1; + go_d3 <= go_d2; + go_d4 <= go_d3; + end + + wire [17:0] coeff_a = -10690; + wire [17:0] coeff_b = 75809; + + reg [WIDTH-1:0] d1, d2, d3, d4 , d5, d6; + always @(posedge clk) + if(stb_in_d1 | rst) + begin + d1 <= data_in_d1; + d2 <= d1; + d3 <= d2; + d4 <= d3; + d5 <= d4; + d6 <= d5; + end + + reg [17:0] sum_a, sum_b, middle, middle_d1; + wire [17:0] sum_a_unreg, sum_b_unreg; + add2 #(.WIDTH(18)) add2_a (.in1(data_in_d1),.in2(d6),.sum(sum_a_unreg)); + add2 #(.WIDTH(18)) add2_b (.in1(d2),.in2(d4),.sum(sum_b_unreg)); + + always @(posedge clk) + if(go) + begin + sum_a <= sum_a_unreg; + sum_b <= sum_b_unreg; + middle <= d3; + end + + always @(posedge clk) + if(go_d1) + middle_d1 <= middle; + + wire [17:0] sum = go_d1 ? sum_b : sum_a; + wire [17:0] coeff = go_d1 ? coeff_b : coeff_a; + wire [35:0] prod; + MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) ); + + reg [35:0] accum; + always @(posedge clk) + if(rst) + accum <= 0; + else if(go_d2) + accum <= {middle_d1[17],middle_d1[17],middle_d1,16'd0} + {prod}; + else if(go_d3) + accum <= accum + {prod}; + + wire [17:0] accum_rnd; + round #(.bits_in(36),.bits_out(18)) round_acc (.in(accum),.out(accum_rnd)); + + reg [17:0] final_sum; + always @(posedge clk) + if(bypass) + final_sum <= data_in_d1; + else if(go_d4) + final_sum <= accum_rnd; + + assign data_out = final_sum; + + always @(posedge clk) + if(rst) + stb_out <= 0; + else if(bypass) + stb_out <= stb_in_d1; + else + stb_out <= go_d4; +endmodule // small_hb_dec diff --git a/usrp2/sdr_lib/small_hb_dec_tb.v b/usrp2/sdr_lib/small_hb_dec_tb.v new file mode 100644 index 000000000..0d6a0689e --- /dev/null +++ b/usrp2/sdr_lib/small_hb_dec_tb.v @@ -0,0 +1,140 @@ +module hb_dec_tb( ) ; + + // Parameters for instantiation + parameter clocks = 9'd2 ; // Number of clocks per input + parameter decim = 1 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + reg strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + initial + begin + $dumpfile("hb_dec_tb.vcd"); + $dumpvars(0,hb_dec_tb); + end + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #1000 reset = 1'b0 ; + + // Enable the entire system + initial enable = 1'b1 ; + + // Instantiate UUT + /* + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + */ + + + small_hb_dec #(.WIDTH(18)) uut + (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), + .stb_out(strobe_out),.data_out(data_out) ); + + integer i, ri, ro, infile, outfile ; + + always @(posedge clock) + begin + if(strobe_out) + $display(data_out); + end + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + strobe_in <= 1'd0 ; + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( posedge clock ) begin + //#1 ; + strobe_in <= 1'b1 ; + if( !$feof(infile) ) + ri = $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + + // Clocked in - set the strobe to 0 if the number of + // clocks per sample is greater than 1 + if( clocks > 1 ) begin + @(posedge clock) begin + strobe_in <= 1'b0 ; + end + + // Wait for the specified number of cycles + for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin + @(posedge clock) #1 ; + end + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $finish ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + //$display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + endofsim <= 1'b1 ; + end + end + end + +endmodule // hb_dec_tb + diff --git a/usrp2/sdr_lib/small_hb_int.v b/usrp2/sdr_lib/small_hb_int.v new file mode 100644 index 000000000..f80d3cac3 --- /dev/null +++ b/usrp2/sdr_lib/small_hb_int.v @@ -0,0 +1,85 @@ +// Short halfband decimator (intended to be followed by another stage) +// Implements impulse responses of the form [A 0 B 0.5 B 0 A] +// +// These taps designed by halfgen4 from ldoolittle: +// 2 * 131072 * halfgen4(.75/8,2) + +module small_hb_int + #(parameter WIDTH=18) + (input clk, + input rst, + input bypass, + input stb_in, + input [WIDTH-1:0] data_in, + input [7:0] output_rate, + input stb_out, + output reg [WIDTH-1:0] data_out); + + reg phase; + reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6; + + localparam MWIDTH = 36; + wire [MWIDTH-1:0] prod; + + reg [6:0] stbin_d; + + always @(posedge clk) + stbin_d <= {stbin_d[5:0],stb_in}; + + always @(posedge clk) + if(stb_in) + begin + d1 <= data_in; + d2 <= d1; + d3 <= d2; + d4 <= d3; + d5 <= d4; + d6 <= d5; + end + + wire [WIDTH-1:0] sum_outer, sum_inner; + add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer)); + add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner)); + + wire [17:0] coeff_outer = -10690; + wire [17:0] coeff_inner = 75809; + + MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner), + .B(stbin_d[1] ? sum_outer : sum_inner) ); + + wire [MWIDTH:0] accum; + acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) + acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum)); + + wire [WIDTH+2:0] accum_rnd; + round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3)) + final_round (.clk(clk),.in(accum),.out(accum_rnd)); + + wire [WIDTH-1:0] clipped; + clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) + final_clip (.clk(clk),.in(accum_rnd),.out(clipped)); + + reg [WIDTH-1:0] saved, saved_d3; + always @(posedge clk) + if(stbin_d[6]) + saved <= clipped; + + always @(posedge clk) + if(stbin_d[3]) + saved_d3 <= d3; + + always @(posedge clk) + if(bypass) + data_out <= data_in; + else if(stb_in & stb_out) + case(output_rate) + 1 : data_out <= d6; + 2 : data_out <= d4; + 3, 4, 5, 6, 7 : data_out <= d3; + default : data_out <= d2; + endcase // case(output_rate) + else if(stb_out) + data_out <= saved; + +endmodule // small_hb_int + diff --git a/usrp2/sdr_lib/small_hb_int_tb.v b/usrp2/sdr_lib/small_hb_int_tb.v new file mode 100644 index 000000000..71d77f0a8 --- /dev/null +++ b/usrp2/sdr_lib/small_hb_int_tb.v @@ -0,0 +1,132 @@ +module small_hb_int_tb( ) ; + + // Parameters for instantiation + parameter clocks = 8'd1 ; // Number of clocks per output + parameter decim = 1 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + wire strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + initial + begin + $dumpfile("small_hb_int_tb.vcd"); + $dumpvars(0,small_hb_int_tb); + end + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #1000 reset = 1'b0 ; + + always @(posedge clock) + enable <= ~reset; + + // Instantiate UUT + /* + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + */ + + cic_strober #(.WIDTH(8)) + out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks), + .strobe_fast(1),.strobe_slow(strobe_out) ); + + cic_strober #(.WIDTH(8)) + in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2), + .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); + + small_hb_int #(.WIDTH(18)) uut + (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), + .stb_out(strobe_out),.output_rate(clocks),.data_out(data_out) ); + + integer i, ri, ro, infile, outfile ; + + always @(posedge clock) + begin + if(strobe_out) + $display(data_out); + end + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( negedge clock ) begin + if(strobe_in) + if( !$feof(infile) ) + ri <= #1 $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $finish ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + //$display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + if($feof(infile)) + endofsim <= 1'b1 ; + end + end + end + +endmodule // small_hb_int_tb diff --git a/usrp2/sdr_lib/tx_control.v b/usrp2/sdr_lib/tx_control.v new file mode 100644 index 000000000..e5fed0b93 --- /dev/null +++ b/usrp2/sdr_lib/tx_control.v @@ -0,0 +1,168 @@ + +`define DSP_CORE_TX_BASE 128 + +module tx_control + #(parameter FIFOSIZE = 10) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [31:0] master_time, + output underrun, + + // To FIFO interface from Buffer Pool + input [31:0] rd_dat_i, + input [3:0] rd_flags_i, + input rd_ready_i, + output rd_ready_o, + + // To DSP Core + output [31:0] sample, + output run, + input strobe, + + // FIFO Levels + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty, + + // Debug + output [31:0] debug + ); + + wire rd_sop_i = rd_flags_i[0]; // Unused + wire rd_eop_i = rd_flags_i[1]; + wire rd_occ_i = rd_flags_i[3:2]; // Unused, should always be 0 + + // Buffer interface to internal FIFO + wire write_data, write_ctrl, full_data, full_ctrl; + wire read_data, read_ctrl, empty_data, empty_ctrl; + wire clear_state; + reg [1:0] xfer_state; + reg [2:0] held_flags; + + localparam XFER_IDLE = 0; + localparam XFER_CTRL = 1; + localparam XFER_PKT = 2; + // Add underrun state? + + always @(posedge clk) + if(rst) + xfer_state <= XFER_IDLE; + else if(clear_state) + xfer_state <= XFER_IDLE; + else + if(rd_ready_i & rd_ready_o) + case(xfer_state) + XFER_IDLE : + begin + xfer_state <= XFER_CTRL; + held_flags <= rd_dat_i[2:0]; + end + XFER_CTRL : + xfer_state <= XFER_PKT; + XFER_PKT : + if(rd_eop_i) + xfer_state <= XFER_IDLE; + endcase // case(xfer_state) + + wire have_data_space; + assign full_data = ~have_data_space; + + assign write_data = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o; + assign write_ctrl = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o; + + assign rd_ready_o = ~full_data & ~full_ctrl; + + wire [31:0] data_o; + wire eop_o, eob, sob, send_imm; + wire [31:0] sendtime; + wire [4:0] occ_ctrl; +/* + cascadefifo2 #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo + (.clk(clk),.rst(rst),.clear(clear_state), + .datain({rd_eop_i,rd_dat_i[31:0]}), .write(write_data), .full(full_data), + .dataout({eop_o,data_o}), .read(read_data), .empty(empty_data), + .space(), .occupied(fifo_occupied) ); +*/ + wire have_data; + assign empty_data = ~have_data; + + fifo_cascade #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo + (.clk(clk),.reset(rst),.clear(clear_state), + .datain({rd_eop_i,rd_dat_i[31:0]}), .src_rdy_i(write_data), .dst_rdy_o(have_data_space), + .dataout({eop_o,data_o}), .src_rdy_o(have_data), .dst_rdy_i(read_data), + .space(), .occupied(fifo_occupied) ); + assign fifo_full = full_data; + assign fifo_empty = empty_data; + + shortfifo #(.WIDTH(35)) ctrlfifo + (.clk(clk),.rst(rst),.clear(clear_state), + .datain({held_flags[2:0],rd_dat_i[31:0]}), .write(write_ctrl), .full(full_ctrl), + .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), .empty(empty_ctrl), + .space(), .occupied(occ_ctrl) ); + + // Internal FIFO to DSP interface + reg [2:0] ibs_state; + + localparam IBS_IDLE = 0; + localparam IBS_WAIT = 1; + localparam IBS_RUNNING = 2; + localparam IBS_CONT_BURST = 3; + localparam IBS_UNDERRUN = 7; + + wire [32:0] delta_time = {1'b0,sendtime}-{1'b0,master_time}; + + wire too_late = (delta_time[32:31] == 2'b11); + wire go_now = ( master_time == sendtime ); + + always @(posedge clk) + if(rst) + ibs_state <= IBS_IDLE; + else + case(ibs_state) + IBS_IDLE : + if(~empty_ctrl & ~empty_data) + ibs_state <= IBS_WAIT; + IBS_WAIT : + if(send_imm) + ibs_state <= IBS_RUNNING; + else if(too_late) + ibs_state <= IBS_UNDERRUN; + else if(go_now) + ibs_state <= IBS_RUNNING; + IBS_RUNNING : + if(strobe) + if(empty_data) + ibs_state <= IBS_UNDERRUN; + else if(eop_o) + if(eob) + ibs_state <= IBS_IDLE; + else + ibs_state <= IBS_CONT_BURST; + IBS_CONT_BURST : + if(~empty_ctrl) // & ~empty_data) + ibs_state <= IBS_RUNNING; + else if(strobe) + ibs_state <= IBS_UNDERRUN; + IBS_UNDERRUN : // FIXME Should probably clean everything out + if(clear_state) + ibs_state <= IBS_IDLE; + endcase // case(ibs_state) + + assign read_ctrl = (ibs_state == IBS_RUNNING) & strobe & eop_o; // & ~empty_ctrl; + assign read_data = (ibs_state == IBS_RUNNING) & strobe & ~empty_data; + assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_CONT_BURST); + assign underrun = (ibs_state == IBS_UNDERRUN); + + wire [7:0] interp_rate; + setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_state)); + + assign sample = data_o; + + assign debug = { {16'b0}, + { read_data, write_data, read_ctrl, write_ctrl, xfer_state[1:0],full_ctrl,empty_ctrl }, + { occ_ctrl, eop_o, clear_state, underrun} }; + +endmodule // tx_control diff --git a/usrp2/serdes/serdes.v b/usrp2/serdes/serdes.v new file mode 100644 index 000000000..17049bfe6 --- /dev/null +++ b/usrp2/serdes/serdes.v @@ -0,0 +1,63 @@ + +// SERDES TX and RX along with all flow control logic + +module serdes + #(parameter TXFIFOSIZE = 9, + parameter RXFIFOSIZE = 9) + (input clk, input rst, + // TX side + output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb, + input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input rd_ready_i, + // RX side + input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb, + output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input wr_ready_i, + + output [15:0] tx_occupied, output tx_full, output tx_empty, + output [15:0] rx_occupied, output rx_full, output rx_empty, + + output serdes_link_up, + + output [31:0] debug0, + output [31:0] debug1); + + wire [15:0] fifo_space; + wire xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent; + wire [31:0] debug_rx, debug_tx; + + serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx + (.clk(clk),.rst(rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i), + .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent), + .fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty), + .debug(debug_tx) ); + + serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx + (.clk(clk),.rst(rst), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i), + .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd), + .fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty), + .serdes_link_up(serdes_link_up), .debug(debug_rx) ); + + serdes_fc_tx serdes_fc_tx + (.clk(clk),.rst(rst), + .xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) ); + + serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx + (.clk(clk),.rst(rst), + .fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) ); + + //assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] }; + //assign debug = debug_rx; + + assign debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]}, + { debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb}, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug1 = { { debug_rx[7:0] }, /* odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */ + { wr_flags_o[1:0], wr_ready_i, wr_ready_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb }, + { ser_r[15:8] }, + { ser_r[7:0] } }; +endmodule // serdes diff --git a/usrp2/serdes/serdes_fc_rx.v b/usrp2/serdes/serdes_fc_rx.v new file mode 100644 index 000000000..4dd46e27f --- /dev/null +++ b/usrp2/serdes/serdes_fc_rx.v @@ -0,0 +1,62 @@ + + +module serdes_fc_rx + #(parameter LWMARK = 64, + parameter HWMARK = 320) + (input clk, input rst, + input [15:0] fifo_space, + output reg send_xon, + output reg send_xoff, + input sent); + + reg [15:0] countdown; + reg send_xon_int, send_xoff_int; + + always @(posedge clk) + if(rst) + begin + send_xon_int <= 0; + send_xoff_int <= 0; + countdown <= 0; + end + else + begin + send_xon_int <= 0; + send_xoff_int <= 0; + if(countdown == 0) + if(fifo_space < LWMARK) + begin + send_xoff_int <= 1; + countdown <= 240; + end + else + ; + else + if(fifo_space > HWMARK) + begin + send_xon_int <= 1; + countdown <= 0; + end + else + countdown <= countdown - 1; + end // else: !if(rst) + + // If we are between the high and low water marks, we let the countdown expire + + always @(posedge clk) + if(rst) + send_xon <= 0; + else if(send_xon_int) + send_xon <= 1; + else if(sent) + send_xon <= 0; + + always @(posedge clk) + if(rst) + send_xoff <= 0; + else if(send_xoff_int) + send_xoff <= 1; + else if(sent) + send_xoff <= 0; + +endmodule // serdes_fc_rx diff --git a/usrp2/serdes/serdes_fc_tx.v b/usrp2/serdes/serdes_fc_tx.v new file mode 100644 index 000000000..2fe967c8d --- /dev/null +++ b/usrp2/serdes/serdes_fc_tx.v @@ -0,0 +1,24 @@ + + +module serdes_fc_tx + (input clk, input rst, + input xon_rcvd, input xoff_rcvd, output reg inhibit_tx); + + // XOFF means stop sending, XON means start sending + // clock domain stuff happens elsewhere, everything here is on main clk + + reg [15:0] state; + always @(posedge clk) + if(rst) + state <= 0; + else if(xoff_rcvd) + state <= 255; + else if(xon_rcvd) + state <= 0; + else if(state !=0) + state <= state - 1; + + always @(posedge clk) + inhibit_tx <= (state != 0); + +endmodule // serdes_fc_tx diff --git a/usrp2/serdes/serdes_rx.v b/usrp2/serdes/serdes_rx.v new file mode 100644 index 000000000..afefccaa1 --- /dev/null +++ b/usrp2/serdes/serdes_rx.v @@ -0,0 +1,292 @@ + +// SERDES Interface + +// LS-Byte is sent first, MS-Byte is second +// Invalid K Codes +// K0.0 000-00000 Error detected +// K31.7 111-11111 Loss of input signal + +// Valid K Codes +// K28.0 000-11100 +// K28.1 001-11100 Alternate COMMA? +// K28.2 010-11100 +// K28.3 011-11100 +// K28.4 100-11100 +// K28.5 101-11100 Standard COMMA? +// K28.6 110-11100 +// K28.7 111-11100 Bad COMMA? +// K23.7 111-10111 +// K27.7 111-11011 +// K29.7 111-11101 +// K30.7 111-11110 + +module serdes_rx + #(parameter FIFOSIZE = 9) + (input clk, + input rst, + + // RX HW Interface + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + output [31:0] wr_dat_o, + output [3:0] wr_flags_o, + input wr_ready_i, + output wr_ready_o, + + output [15:0] fifo_space, + output xon_rcvd, output xoff_rcvd, + + output [15:0] fifo_occupied, output fifo_full, output fifo_empty, + output reg serdes_link_up, + output [31:0] debug + ); + + localparam K_COMMA = 8'b101_11100; // 0xBC K28.5 + localparam K_IDLE = 8'b001_11100; // 0x3C K28.1 + localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6 + localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4 + localparam K_XON = 8'b010_11100; // 0x5C K28.2 + localparam K_XOFF = 8'b011_11100; // 0x7C K28.3 + localparam K_LOS = 8'b111_11111; // 0xFF K31.7 + localparam K_ERROR = 8'b000_00000; // 0x00 K00.0 + localparam D_56 = 8'b110_00101; // 0xC5 D05.6 + + localparam IDLE = 3'd0; + localparam FIRSTLINE1 = 3'd1; + localparam FIRSTLINE2 = 3'd2; + localparam PKT1 = 3'd3; + localparam PKT2 = 3'd4; + localparam CRC_CHECK = 3'd5; + localparam ERROR = 3'd6; + localparam DONE = 3'd7; + + wire [17:0] even_data; + reg [17:0] odd_data; + wire [17:0] chosen_data; + reg odd; + + reg [31:0] line_i; + reg sop_i, eop_i, error_i; + wire error_o, sop_o, eop_o, write; + reg [15:0] halfline; + reg [8:0] holder; + wire [31:0] line_o; + + reg [2:0] state; + + reg [15:0] CRC; + wire [15:0] nextCRC; + reg write_d; + + wire rst_rxclk; + wire have_space; + + oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk)); + + assign even_data = {ser_rkmsb,ser_rklsb,ser_r}; + + always @(posedge ser_rx_clk) + if(rst_rxclk) + holder <= 9'd0; + else + holder <= {even_data[17],even_data[15:8]}; + + always @(posedge ser_rx_clk) + if(rst_rxclk) + odd_data <= 18'd0; + else + odd_data <= {even_data[16],holder[8],even_data[7:0],holder[7:0]}; + + assign chosen_data = odd ? odd_data : even_data; + + // Transfer xon and xoff info to the main system clock for flow control purposes + reg xon_rcvd_rxclk, xoff_rcvd_rxclk; + always @(posedge ser_rx_clk) + xon_rcvd_rxclk = ({1'b1,K_XON} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XON} == {ser_rklsb,ser_r[7:0]} ); + always @(posedge ser_rx_clk) + xoff_rcvd_rxclk = ({1'b1,K_XOFF} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XOFF} == {ser_rklsb,ser_r[7:0]} ); + + oneshot_2clk xon_1s(.clk_in(ser_rx_clk),.in(xon_rcvd_rxclk),.clk_out(clk),.out(xon_rcvd)); + oneshot_2clk xoff_1s(.clk_in(ser_rx_clk),.in(xoff_rcvd_rxclk),.clk_out(clk),.out(xoff_rcvd)); + + // If the other side is sending xon or xoff, or is flow controlled (b/c we told them to be), don't fill the fifos + wire wait_here = ((chosen_data == {2'b10,K_COMMA,D_56})|| + (chosen_data == {2'b11,K_XON,K_XON})|| + (chosen_data == {2'b11,K_XOFF,K_XOFF}) ); + + always @(posedge ser_rx_clk) + if(rst_rxclk) sop_i <= 0; + else if(state == FIRSTLINE1) sop_i <= 1; + else if(write_d) sop_i <= 0; + + reg write_pre; + always @(posedge ser_rx_clk) + if(rst_rxclk) + begin + state <= IDLE; + odd <= 0; + halfline <= 0; + line_i <= 0; + eop_i <= 0; + error_i <= 0; + write_pre <= 0; + end + else + case(state) + IDLE : + begin + error_i <= 0; + write_pre <= 0; + if(even_data == {2'b11,K_PKT_START,K_PKT_START}) + begin + state <= FIRSTLINE1; + odd <= 0; + end + else if(odd_data == {2'b11,K_PKT_START,K_PKT_START}) + begin + state <= FIRSTLINE1; + odd <= 1; + end + end + + FIRSTLINE1 : + if(chosen_data[17:16] == 0) + begin + halfline <= chosen_data[15:0]; + state <= FIRSTLINE2; + end + else if(wait_here) + ; // Flow Controlled, so wait here and do nothing + else + state <= ERROR; + + FIRSTLINE2 : + if(chosen_data[17:16] == 0) + begin + line_i <= {chosen_data[15:0],halfline}; + if(~have_space) // No space to write to! Should have been avoided by flow control + state <= ERROR; + else + begin + state <= PKT1; + write_pre <= 1; + end + end // if (chosen_data[17:16] == 0) + else if(wait_here) + ; // Flow Controlled, so wait here and do nothing + else + state <= ERROR; + + PKT1 : + begin + write_pre <= 0; + if(chosen_data[17:16] == 0) + begin + halfline <= chosen_data[15:0]; + state <= PKT2; + end + else if(wait_here) + ; // Flow Controlled + else if(chosen_data == {2'b11,K_PKT_END,K_PKT_END}) + state <= CRC_CHECK; + else + state <= ERROR; + end // case: PKT1 + + PKT2 : + if(chosen_data[17:16] == 0) + begin + line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline}; + if(~have_space) // No space to write to! + state <= ERROR; + else + begin + state <= PKT1; + write_pre <= 1; + end + end // if (chosen_data[17:16] == 0) + else if(wait_here) + ; // Flow Controlled + else + state <= ERROR; + + CRC_CHECK : + if(chosen_data[17:0] == {2'b00,CRC}) + begin + if(~have_space) + state <= ERROR; + else + begin + eop_i <= 1; + state <= DONE; + end + end + else if(wait_here) + ; + else + state <= ERROR; + + ERROR : + begin + error_i <= 1; + if(have_space) + state <= IDLE; + end + DONE : + begin + state <= IDLE; + eop_i <= 0; + end + + endcase // case(state) + + + always @(posedge ser_rx_clk) + if(rst_rxclk) + CRC <= 16'hFFFF; + else if(state == IDLE) + CRC <= 16'hFFFF; + else if(chosen_data[17:16] == 2'b00) + CRC <= nextCRC; + + CRC16_D16 crc_blk(chosen_data[15:0],CRC,nextCRC); + + always @(posedge ser_rx_clk) + if(rst_rxclk) write_d <= 0; + else write_d <= write_pre; + + // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes + assign write = eop_i | (error_i & have_space) | (write_d & (state != CRC_CHECK)); + + fifo_2clock_cascade #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo + (.arst(rst), + .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), + .src_rdy_i(write), .dst_rdy_o(have_space), .space(fifo_space), + .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), + .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), .occupied(fifo_occupied) ); + + assign fifo_full = ~have_space; // Note -- in the wrong clock domain + assign fifo_empty = ~wr_ready_o; + + // Internal FIFO to Buffer interface + assign wr_dat_o = line_o; + assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o }; + + wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) || + ({2'b11,K_LOS,K_LOS}=={ser_rkmsb,ser_rklsb,ser_r})); + + reg [3:0] slu_reg; + + always @(posedge clk) + if(rst) slu_reg <= 0; + else slu_reg <= {slu_reg[2:0],slu}; + + always @(posedge clk) + serdes_link_up <= &slu_reg[3:1]; + + assign debug = { have_space, wr_ready_o, odd, sop_i, eop_i, error_i, state[2:0] }; + +endmodule // serdes_rx diff --git a/usrp2/serdes/serdes_tb.v b/usrp2/serdes/serdes_tb.v new file mode 100644 index 000000000..eb8e019fc --- /dev/null +++ b/usrp2/serdes/serdes_tb.v @@ -0,0 +1,328 @@ + +// FIXME need to add flow control + +module serdes_tb(); + + reg clk, rst; + wire ser_rx_clk, ser_tx_clk; + wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb; + wire [15:0] ser_r, ser_t; + + initial clk = 0; + initial rst = 1; + initial #1000 rst = 0; + always #100 clk = ~clk; + + // Wishbone + reg [31:0] wb_dat_i; + wire [31:0] wb_dat_o_rx, wb_dat_o_tx; + reg wb_we, wb_en_rx, wb_en_tx; + reg [8:0] wb_adr; + + // Buffer Control + reg go, clear, read, write; + reg [3:0] buf_num; + wire [31:0] ctrl_word = {buf_num,3'b0,clear,write,read,step,lastline,firstline}; + reg [8:0] firstline = 0, lastline = 0; + reg [3:0] step = 1; + reg first_tx = 1, first_rx = 1; // for verif + + // TX Side + reg wb_we_tx; + wire en_tx, we_tx; + wire [8:0] addr_tx; + wire [31:0] f2r_tx, r2f_tx; + wire [31:0] data_tx; + wire read_tx, done_tx, error_tx, sop_tx, eop_tx; + + wire fdone_tx, ferror_tx; + + reg even; + reg channel_error = 0; + + serdes_tx serdes_tx + (.clk(clk),.rst(rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(data_tx),.rd_read_o(read_tx),.rd_done_o(done_tx), + .rd_error_o(error_tx),.rd_sop_i(sop_tx),.rd_eop_i(eop_tx) ); + + ram_2port #(.DWIDTH(32),.AWIDTH(9)) + ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we_tx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx), + .clkb(clk),.enb(en_tx),.web(we_tx),.addrb(addr_tx),.dib(f2r_tx),.dob(r2f_tx)); + + buffer_int #(.BUFF_NUM(1)) buffer_int_tx + (.clk(clk),.rst(rst), + .ctrl_word(ctrl_word),.go(go), + .done(fdone_tx),.error(ferror_tx), + + .en_o(en_tx),.we_o(we_tx),.addr_o(addr_tx),.dat_to_buf(f2r_tx),.dat_from_buf(r2f_tx), + + .wr_dat_i(0),.wr_write_i(0),.wr_done_i(0), + .wr_error_i(0),.wr_ready_o(),.wr_full_o(), + + .rd_dat_o(data_tx),.rd_read_i(read_tx),.rd_done_i(done_tx), + .rd_error_i(error_tx),.rd_sop_o(sop_tx),.rd_eop_o(eop_tx) ); + + + // RX Side + reg wb_we_rx; + wire en_rx, we_rx; + wire [8:0] addr_rx; + wire [31:0] f2r_rx, r2f_rx; + wire [31:0] data_rx; + wire write_rx, done_rx, error_rx, ready_rx, empty_rx; + + wire fdone_rx, ferror_rx; + + serdes_rx serdes_rx + (.clk(clk),.rst(rst), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(data_rx),.wr_write_o(write_rx),.wr_done_o(done_rx), + .wr_error_o(error_rx),.wr_ready_i(ready_rx),.wr_full_i(full_rx) ); + + ram_2port #(.DWIDTH(32),.AWIDTH(9)) + ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we_rx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx), + .clkb(clk),.enb(en_rx),.web(we_rx),.addrb(addr_rx),.dib(f2r_rx),.dob(r2f_rx) ); + + buffer_int #(.BUFF_NUM(0)) buffer_int_rx + (.clk(clk),.rst(rst), + .ctrl_word(ctrl_word),.go(go), + .done(fdone_rx),.error(ferror_rx), + + .en_o(en_rx),.we_o(we_rx),.addr_o(addr_rx),.dat_to_buf(f2r_rx),.dat_from_buf(r2f_rx), + + .wr_dat_i(data_rx),.wr_write_i(write_rx),.wr_done_i(done_rx), + .wr_error_i(error_rx),.wr_ready_o(ready_rx),.wr_full_o(full_rx), + + .rd_dat_o(),.rd_read_i(0),.rd_done_i(0), + .rd_error_i(0),.rd_sop_o(),.rd_eop_o() ); + + // Simulate the connection + serdes_model serdes_model + (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), + .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), + .even(even), .error(channel_error) ); + + initial begin + wb_en_rx <= 0; + wb_en_tx <=0; + wb_we_tx <= 0; + wb_we_rx <= 0; + wb_adr <= 0; + wb_dat_i <= 0; + go <= 0; + even <= 0; + @(negedge rst); + @(posedge clk); + FillTXRAM; + ClearRXRAM; + ResetBuffer(0); + ResetBuffer(1); + + // receive a full buffer + ReceiveSERDES(0,10); + SendSERDES(0,10); + + // Receive a partial buffer + SendSERDES(11,20); + ReceiveSERDES(11,50); + + // Receive too many for buffer + SendSERDES(21,100); + ReceiveSERDES(21,30); + + // Send 3 packets, then wait to receive them, so they stack up in the rx fifo + SendSERDES(31,40); + SendSERDES(41,50); + SendSERDES(51,60); + repeat (10) + @(posedge clk); + ReceiveSERDES(31,40); + ReceiveSERDES(41,50); + repeat (1000) + @(posedge clk); + ReceiveSERDES(51,60); + + // Overfill the FIFO, should get an error on 3rd packet + SendSERDES(1,400); + SendSERDES(1,400); + + + WaitForTX; + //WaitForRX; + + + repeat(1000) + @(posedge clk); + ReceiveSERDES(101,500); + ReceiveSERDES(101,500); + ReadRAM(80); + $finish; + end // initial begin + + always @(posedge clk) + if(write_rx) + $display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO FULL %d",data_rx, ready_rx, full_rx); + + always @(posedge clk) + if(read_tx) + $display("SERDES TX, FIFO READ %x, SOP %d, EOP %d",data_tx, sop_tx, eop_tx); + + initial begin + $dumpfile("serdes_tb.vcd"); + $dumpvars(0,serdes_tb); + end + + initial #10000000 $finish; + + initial #259300 channel_error <= 1; + initial #259500 channel_error <= 0; + + task FillTXRAM; + begin + wb_adr <= 0; + wb_dat_i <= 32'h10802000; + wb_we_tx <= 1; + wb_en_tx <= 1; + @(posedge clk); + repeat(511) begin + wb_dat_i <= wb_dat_i + 32'h00010001; + wb_adr <= wb_adr + 1; + @(posedge clk); + end // repeat (511) + wb_we_tx <= 0; + wb_en_tx <= 0; + @(posedge clk); + $display("Done entering Data into TX RAM\n"); + end + endtask // FillTXRAM + + task ClearRXRAM; + begin + wb_adr <= 0; + wb_dat_i <= 0; + wb_we_rx <= 1; + wb_en_rx <= 1; + wb_dat_i <= 0; + @(posedge clk); + repeat(511) begin + wb_adr <= wb_adr + 1; + @(posedge clk); + end // repeat (511) + wb_we_rx <= 0; + wb_en_rx <= 0; + @(posedge clk); + $display("Done clearing RX RAM\n"); + end + endtask // FillRAM + + task ReadRAM; + input [8:0] lastline; + begin + wb_en_rx <= 1; + wb_adr <= 0; + @(posedge clk); + @(posedge clk); + repeat(lastline) begin + $display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx); + wb_adr <= wb_adr + 1; + @(posedge clk); + @(posedge clk); + end // repeat (511) + $display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx); + wb_en_rx <= 0; + @(posedge clk); + $display("Done reading out RX RAM\n"); + end + endtask // FillRAM + + task ResetBuffer; + input [3:0] buffer_num; + begin + buf_num <= buffer_num; + clear <= 1; read <= 0; write <= 0; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Reset"); + end + endtask // ClearBuffer + + task SetBufferWrite; + input [3:0] buffer_num; + input [8:0] start; + input [8:0] stop; + begin + buf_num <= buffer_num; + clear <= 0; read <= 0; write <= 1; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Write"); + end + endtask // SetBufferWrite + + task SetBufferRead; + input [3:0] buffer_num; + input [8:0] start; + input [8:0] stop; + begin + buf_num <= buffer_num; + clear <= 0; read <= 1; write <= 0; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Read"); + end + endtask // SetBufferRead + + task WaitForTX; + begin + while (!(fdone_tx | ferror_tx)) + @(posedge clk); + end + endtask // WaitForTX + + task WaitForRX; + begin + while (!(fdone_rx | ferror_rx)) + @(posedge clk); + end + endtask // WaitForRX + + task SendSERDES; + input [8:0] start; + input [8:0] stop; + begin + if(~first_tx) + WaitForTX; + else + first_tx <= 0; + ResetBuffer(1); + SetBufferRead(1,start,stop); + $display("Here"); + end + endtask // SendSERDES + + task ReceiveSERDES; + input [8:0] start; + input [8:0] stop; + begin + if(~first_rx) + WaitForRX; + else + first_rx <= 0; + ResetBuffer(0); + SetBufferWrite(0,start,stop); + $display("Here2"); + end + endtask // ReceiveSERDES + +endmodule // serdes_tb diff --git a/usrp2/serdes/serdes_tx.v b/usrp2/serdes/serdes_tx.v new file mode 100644 index 000000000..2e5e3bd80 --- /dev/null +++ b/usrp2/serdes/serdes_tx.v @@ -0,0 +1,186 @@ + +// SERDES Interface + +// LS-Byte is sent first, MS-Byte is second +// Invalid K Codes +// K0.0 000-00000 Error detected +// K31.7 111-11111 Loss of input signal + +// Valid K Codes +// K28.0 000-11100 +// K28.1 001-11100 Alternate COMMA? +// K28.2 010-11100 +// K28.3 011-11100 +// K28.4 100-11100 +// K28.5 101-11100 Standard COMMA? +// K28.6 110-11100 +// K28.7 111-11100 Bad COMMA? +// K23.7 111-10111 +// K27.7 111-11011 +// K29.7 111-11101 +// K30.7 111-11110 + +module serdes_tx + #(parameter FIFOSIZE = 9) + (input clk, + input rst, + + // TX HW Interface + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + // TX Stream Interface + input [31:0] rd_dat_i, + input [3:0] rd_flags_i, + output rd_ready_o, + input rd_ready_i, + + // Flow control interface + input inhibit_tx, + input send_xon, + input send_xoff, + output sent, + + // FIFO Levels + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty, + + // DEBUG + output [31:0] debug + ); + + localparam K_COMMA = 8'b101_11100; // 0xBC K28.5 + localparam K_IDLE = 8'b001_11100; // 0x3C K28.1 + localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6 + localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4 + localparam K_XON = 8'b010_11100; // 0x5C K28.2 + localparam K_XOFF = 8'b011_11100; // 0x7C K28.3 + localparam K_LOS = 8'b111_11111; // 0xFF K31.7 + localparam K_ERROR = 8'b000_00000; // 0x00 K00.0 + localparam D_56 = 8'b110_00101; // 0xC5 D05.6 + assign ser_tx_clk = clk; + + localparam IDLE = 3'd0; + localparam RUN1 = 3'd1; + localparam RUN2 = 3'd2; + localparam DONE = 3'd3; + localparam SENDCRC = 3'd4; + localparam WAIT = 3'd5; + + reg [2:0] state; + + reg [15:0] CRC; + wire [15:0] nextCRC; + reg [3:0] wait_count; + + // Internal FIFO, size 9 is 2K, size 10 is 4K bytes + wire sop_o, eop_o; + wire [31:0] data_o; + + wire rd_sop_i = rd_flags_i[0]; + wire rd_eop_i = rd_flags_i[1]; + wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused + + wire have_data, empty, read; + fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo + (.clk(clk),.reset(rst),.clear(0), + .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o), + .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data), + .space(), .occupied(fifo_occupied) ); + + assign fifo_full = ~rd_ready_o; + assign empty = ~have_data; + assign fifo_empty = empty; + + // FIXME Implement flow control + reg [15:0] second_word; + reg [33:0] pipeline; + + assign read = (~send_xon & ~send_xoff & (state==RUN2)) | ((state==IDLE) & ~empty & ~sop_o); + assign sent = send_xon | send_xoff; + // 2nd half of above probably not necessary. Just in case we get junk between packets + + always @(posedge clk) + if(rst) + begin + state <= IDLE; + wait_count <= 0; + {ser_tkmsb,ser_tklsb,ser_t} <= 18'd0; + //{2'b10,K_COMMA,K_COMMA}; + // make tkmsb and tklsb different so they can go in IOFFs + end + else + if(send_xon) + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XON,K_XON}; + else if(send_xoff) + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XOFF,K_XOFF}; + else + case(state) + IDLE : + begin + if(sop_o & ~empty & ~inhibit_tx) + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_START,K_PKT_START}; + state <= RUN1; + end + else + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; + end + RUN1 : + begin + if(empty | inhibit_tx) + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; + else + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[15:0]}; + state <= RUN2; + end + end + RUN2 : + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[31:16]}; + if(eop_o) + state <= DONE; + else + state <= RUN1; + end + DONE : + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_END,K_PKT_END}; + state <= SENDCRC; + end + SENDCRC : + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC}; + state <= WAIT; + wait_count <= 4'd15; + end + WAIT : + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; + if(wait_count == 0) + state <= IDLE; + else + wait_count <= wait_count - 1; + end + default + state <= IDLE; + endcase // case(state) + + always @(posedge clk) + if(rst) + CRC <= 16'hFFFF; + else if(state == IDLE) + CRC <= 16'hFFFF; + else if( (~empty & ~inhibit_tx & (state==RUN1)) || (state==RUN2) ) + CRC <= nextCRC; + + CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC); + + assign debug = { 28'd0, state[2:0] }; + +endmodule // serdes_tx + diff --git a/usrp2/simple_gemac/.gitignore b/usrp2/simple_gemac/.gitignore new file mode 100644 index 000000000..17f35e962 --- /dev/null +++ b/usrp2/simple_gemac/.gitignore @@ -0,0 +1,4 @@ +/a.out +/*.vcd +simple_gemac_wrapper_tb + diff --git a/usrp2/simple_gemac/address_filter.v b/usrp2/simple_gemac/address_filter.v new file mode 100644 index 000000000..50a52b954 --- /dev/null +++ b/usrp2/simple_gemac/address_filter.v @@ -0,0 +1,35 @@ + + +module address_filter + (input clk, + input reset, + input go, + input [7:0] data, + input [47:0] address, + output match, + output done); + + reg [2:0] af_state; + + always @(posedge clk) + if(reset) + af_state <= 0; + else + if(go) + af_state <= (data == address[47:40]) ? 1 : 7; + else + case(af_state) + 1 : af_state <= (data == address[39:32]) ? 2 : 7; + 2 : af_state <= (data == address[31:24]) ? 3 : 7; + 3 : af_state <= (data == address[23:16]) ? 4 : 7; + 4 : af_state <= (data == address[15:8]) ? 5 : 7; + 5 : af_state <= (data == address[7:0]) ? 6 : 7; + 6, 7 : af_state <= 0; + endcase // case (af_state) + + assign match = (af_state==6); + assign done = (af_state==6)|(af_state==7); + +endmodule // address_filter + + diff --git a/usrp2/simple_gemac/crc.v b/usrp2/simple_gemac/crc.v new file mode 100644 index 000000000..ac019083a --- /dev/null +++ b/usrp2/simple_gemac/crc.v @@ -0,0 +1,66 @@ + +module crc + (input clk, + input reset, + input clear, + input [7:0] data, + input calc, + output [31:0] crc_out, + output match); + + function[31:0] NextCRC; + input[7:0] D; + input[31:0] C; + reg[31:0] NewCRC; + begin + NewCRC[0] = C[24]^C[30]^D[1]^D[7]; + NewCRC[1] = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[2] = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[3] = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[4] = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; + NewCRC[5] = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[6] = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[7] = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[8] = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[9] = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; + NewCRC[10] = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[11] = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[12] = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[13] = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[14] = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; + NewCRC[15] = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; + NewCRC[16] = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; + NewCRC[17] = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; + NewCRC[18] = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; + NewCRC[19] = C[11]^C[31]^D[0]^C[27]^D[4]; + NewCRC[20] = C[12]^C[28]^D[3]; + NewCRC[21] = C[13]^C[29]^D[2]; + NewCRC[22] = C[14]^C[24]^D[7]; + NewCRC[23] = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[24] = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[25] = C[17]^C[27]^D[4]^C[26]^D[5]; + NewCRC[26] = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; + NewCRC[27] = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; + NewCRC[28] = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; + NewCRC[29] = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; + NewCRC[30] = C[22]^C[31]^D[0]^C[28]^D[3]; + NewCRC[31] = C[23]^C[29]^D[2]; + NextCRC = NewCRC; + end + endfunction + + reg [31:0] crc_reg; + always @ (posedge clk) + if (reset | clear) + crc_reg <= 32'hffffffff; + else if (calc) + crc_reg <= NextCRC(data,crc_reg); + + assign crc_out = ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31], + crc_reg[16],crc_reg[17],crc_reg[18],crc_reg[19],crc_reg[20],crc_reg[21],crc_reg[22],crc_reg[23], + crc_reg[8],crc_reg[9],crc_reg[10],crc_reg[11],crc_reg[12],crc_reg[13],crc_reg[14],crc_reg[15], + crc_reg[0],crc_reg[1],crc_reg[2],crc_reg[3],crc_reg[4],crc_reg[5],crc_reg[6],crc_reg[7] }; + + assign match = (crc_reg == 32'hc704_dd7b); + +endmodule // crc diff --git a/usrp2/simple_gemac/delay_line.v b/usrp2/simple_gemac/delay_line.v new file mode 100644 index 000000000..d371bb9c5 --- /dev/null +++ b/usrp2/simple_gemac/delay_line.v @@ -0,0 +1,21 @@ + + +module delay_line + #(parameter WIDTH=32) + (input clk, + input [3:0] delay, + input [WIDTH-1:0] din, + output [WIDTH-1:0] dout); + + genvar i; + generate + for (i=0;i pause_hi_thresh)); + + always @(posedge rx_clk) + if(rx_reset) + countdown <= 0; + else if(xoff) + countdown <= pq_reduced; + else if(xon) + countdown <= 0; + else if(countdown != 0) + countdown <= countdown - 1; + + // Cross clock domains + wire xon_tx, xoff_tx; + oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx)); + oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx)); + + always @(posedge tx_clk) + if(xoff_tx) + pause_time_req <= pause_time; + else if(xon_tx) + pause_time_req <= 0; + + always @(posedge tx_clk) + if(tx_reset) + pause_req <= 0; + else + pause_req <= xon_tx | xoff_tx; + +endmodule // flow_ctrl_rx diff --git a/usrp2/simple_gemac/flow_ctrl_tx.v b/usrp2/simple_gemac/flow_ctrl_tx.v new file mode 100644 index 000000000..f80f5a76d --- /dev/null +++ b/usrp2/simple_gemac/flow_ctrl_tx.v @@ -0,0 +1,39 @@ + +// TX side of flow control -- when other side sends PAUSE, we wait + +module flow_ctrl_tx + (input rst, + input tx_clk, + //host processor + input tx_pause_en, + // From MAC_rx_ctrl + input [15:0] pause_quanta, + input pause_quanta_val, + // MAC_tx_ctrl + output pause_apply, + input paused); + + // ****************************************************************************** + // Inhibit our TX from transmitting because they sent us a PAUSE frame + // ****************************************************************************** + + // Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be + // as big as 16 bits, so 22 bits are needed for the counter + + reg [15+6:0] pause_quanta_counter; + reg pqval_d1, pqval_d2; + + always @(posedge tx_clk) pqval_d1 <= pause_quanta_val; + always @(posedge tx_clk) pqval_d2 <= pqval_d1; + + always @ (posedge tx_clk or posedge rst) + if (rst) + pause_quanta_counter <= 0; + else if (pqval_d1 & ~pqval_d2) + pause_quanta_counter <= {pause_quanta, 6'b0}; + else if((pause_quanta_counter!=0) & paused) + pause_quanta_counter <= pause_quanta_counter - 1; + + assign pause_apply = tx_pause_en & (pause_quanta_counter != 0); + +endmodule // flow_ctrl diff --git a/usrp2/simple_gemac/ll8_shortfifo.v b/usrp2/simple_gemac/ll8_shortfifo.v new file mode 100644 index 000000000..e69de29bb diff --git a/usrp2/simple_gemac/ll8_to_txmac.v b/usrp2/simple_gemac/ll8_to_txmac.v new file mode 100644 index 000000000..3530a0c59 --- /dev/null +++ b/usrp2/simple_gemac/ll8_to_txmac.v @@ -0,0 +1,43 @@ + +module ll8_to_txmac + (input clk, input reset, input clear, + input [7:0] ll_data, input ll_sof, input ll_eof, input ll_src_rdy, output ll_dst_rdy, + output [7:0] tx_data, output tx_valid, output tx_error, input tx_ack ); + + reg [2:0] xfer_state; + + localparam XFER_IDLE = 0; + localparam XFER_ACTIVE = 1; + localparam XFER_WAIT1 = 2; + localparam XFER_UNDERRUN = 3; + localparam XFER_DROP = 4; + + always @(posedge clk) + if(reset | clear) + xfer_state <= XFER_IDLE; + else + case(xfer_state) + XFER_IDLE : + if(tx_ack) + xfer_state <= XFER_ACTIVE; + XFER_ACTIVE : + if(~ll_src_rdy) + xfer_state <= XFER_UNDERRUN; + else if(ll_eof) + xfer_state <= XFER_WAIT1; + XFER_WAIT1 : + xfer_state <= XFER_IDLE; + XFER_UNDERRUN : + xfer_state <= XFER_DROP; + XFER_DROP : + if(ll_eof) + xfer_state <= XFER_IDLE; + endcase // case (xfer_state) + + assign ll_dst_rdy = (xfer_state == XFER_ACTIVE) | tx_ack | (xfer_state == XFER_DROP); + assign tx_valid = (ll_src_rdy & (xfer_state == XFER_IDLE))|(xfer_state == XFER_ACTIVE); + assign tx_data = ll_data; + assign tx_error = (xfer_state == XFER_UNDERRUN); + +endmodule // ll8_to_txmac + diff --git a/usrp2/simple_gemac/miim/eth_clockgen.v b/usrp2/simple_gemac/miim/eth_clockgen.v new file mode 100644 index 000000000..9da732f7f --- /dev/null +++ b/usrp2/simple_gemac/miim/eth_clockgen.v @@ -0,0 +1,141 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_clockgen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_clockgen.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:45 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:55 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); + +//parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) + +output Mdc; // Output clock +output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. +output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. + +reg Mdc; +reg [7:0] Counter; + +wire CountEq0; +wire [7:0] CounterPreset; +wire [7:0] TempDivider; + + +assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 +assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period + + +// Counter counts half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Counter[7:0] <= 8'h1; + else + begin + if(CountEq0) + begin + Counter[7:0] <= CounterPreset[7:0]; + end + else + Counter[7:0] <= Counter - 8'h1; + end +end + + +// Mdc is asserted every other half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Mdc <= 1'b0; + else + begin + if(CountEq0) + Mdc <= ~Mdc; + end +end + + +assign CountEq0 = Counter == 8'h0; +assign MdcEn = CountEq0 & ~Mdc; +assign MdcEn_n = CountEq0 & Mdc; + +endmodule + + diff --git a/usrp2/simple_gemac/miim/eth_miim.v b/usrp2/simple_gemac/miim/eth_miim.v new file mode 100644 index 000000000..a15c94205 --- /dev/null +++ b/usrp2/simple_gemac/miim/eth_miim.v @@ -0,0 +1,470 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_miim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_miim.v,v $ +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +// Revision 1.4 2005/08/16 12:07:57 Administrator +// no message +// +// Revision 1.3 2005/05/19 07:04:29 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2003/05/16 10:08:27 mohor +// Busy was set 2 cycles too late. Reported by Dennis Scott. +// +// Revision 1.4 2002/08/14 18:32:10 mohor +// - Busy signal was not set on time when scan status operation was performed +// and clock was divided with more than 2. +// - Nvalid remains valid two more clocks (was previously cleared too soon). +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.2 2001/08/02 09:25:31 mohor +// Unconnected signals are now connected. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +module eth_miim +( + Clk, + Reset, + Divider, + NoPre, + CtrlData, + Rgad, + Fiad, + WCtrlData, + RStat, + ScanStat, + Mdio, + Mdc, + Busy, + Prsd, + LinkFail, + Nvalid, + WCtrlDataStart, + RStatStart, + UpdateMIIRX_DATAReg +); + +input Clk; // Host Clock +input Reset; // General Reset +input [7:0] Divider; // Divider for the host clock +input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) +input [4:0] Rgad; // Register Address (within the PHY) +input [4:0] Fiad; // PHY Address +input NoPre; // No Preamble (no 32-bit preamble) +input WCtrlData; // Write Control Data operation +input RStat; // Read Status operation +input ScanStat; // Scan Status operation +inout Mdio; // MII Management Data In + +output Mdc; // MII Management Data Clock + +output Busy; // Busy Signal +output LinkFail; // Link Integrity Signal +output Nvalid; // Invalid Status (qualifier for the valid scan result) + +output [15:0] Prsd; // Read Status Data (data read from the PHY) + +output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register +output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register +output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + +//parameter Tp = 1; + + +reg Nvalid; +reg EndBusy_d; // Pre-end Busy signal +reg EndBusy; // End Busy signal (stops the operation in progress) + +reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle +reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles +reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles +reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) +reg WCtrlDataStart_q; +reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle +reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles + +reg RStat_q1; // Read Status operation delayed 1 Clk cycle +reg RStat_q2; // Read Status operation delayed 2 Clk cycles +reg RStat_q3; // Read Status operation delayed 3 Clk cycles +reg RStatStart; // Start Read Status Command (positive edge detected) +reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle +reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles + +reg ScanStat_q1; // Scan Status operation delayed 1 cycle +reg ScanStat_q2; // Scan Status operation delayed 2 cycles +reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn + +wire WriteDataOp; // Write Data Operation (positive edge detected) +wire ReadStatusOp; // Read Status Operation (positive edge detected) +wire ScanStatusOp; // Scan Status Operation (positive edge detected) +wire StartOp; // Start Operation (start of any of the preceding operations) +wire EndOp; // End of Operation + +reg InProgress; // Operation in progress +reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle +reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles +reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles + +reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +reg [6:0] BitCounter; // Bit Counter + + +wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. +wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. +wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal + + +wire LatchByte1_d2; +wire LatchByte0_d2; +reg LatchByte1_d; +reg LatchByte0_d; +reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register + +reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + +wire Mdo; // MII Management Data Output +wire MdoEn; // MII Management Data Output Enable +wire Mdi; + +assign Mdi=Mdio; +assign Mdio=MdoEn?Mdo:1'bz; + + + +// Generation of the EndBusy signal. It is used for ending the MII Management operation. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + EndBusy_d <= 1'b0; + EndBusy <= 1'b0; + end + else + begin + EndBusy_d <= ~InProgress_q2 & InProgress_q3; + EndBusy <= EndBusy_d; + end +end + + +// Update MII RX_DATA register +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + UpdateMIIRX_DATAReg <= 0; + else + if(EndBusy & ~WCtrlDataStart_q) + UpdateMIIRX_DATAReg <= 1; + else + UpdateMIIRX_DATAReg <= 0; +end + + + +// Generation of the delayed signals used for positive edge triggering. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlData_q1 <= 1'b0; + WCtrlData_q2 <= 1'b0; + WCtrlData_q3 <= 1'b0; + + RStat_q1 <= 1'b0; + RStat_q2 <= 1'b0; + RStat_q3 <= 1'b0; + + ScanStat_q1 <= 1'b0; + ScanStat_q2 <= 1'b0; + SyncStatMdcEn <= 1'b0; + end + else + begin + WCtrlData_q1 <= WCtrlData; + WCtrlData_q2 <= WCtrlData_q1; + WCtrlData_q3 <= WCtrlData_q2; + + RStat_q1 <= RStat; + RStat_q2 <= RStat_q1; + RStat_q3 <= RStat_q2; + + ScanStat_q1 <= ScanStat; + ScanStat_q2 <= ScanStat_q1; + if(MdcEn) + SyncStatMdcEn <= ScanStat_q2; + end +end + + +// Generation of the Start Commands (Write Control Data or Read Status) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart <= 1'b0; + WCtrlDataStart_q <= 1'b0; + RStatStart <= 1'b0; + end + else + begin + if(EndBusy) + begin + WCtrlDataStart <= 1'b0; + RStatStart <= 1'b0; + end + else + begin + if(WCtrlData_q2 & ~WCtrlData_q3) + WCtrlDataStart <= 1'b1; + if(RStat_q2 & ~RStat_q3) + RStatStart <= 1'b1; + WCtrlDataStart_q <= WCtrlDataStart; + end + end +end + + +// Generation of the Nvalid signal (indicates when the status is invalid) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Nvalid <= 1'b0; + else + begin + if(~InProgress_q2 & InProgress_q3) + begin + Nvalid <= 1'b0; + end + else + begin + if(ScanStat_q2 & ~SyncStatMdcEn) + Nvalid <= 1'b1; + end + end +end + +// Signals used for the generation of the Operation signals (positive edge) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart_q1 <= 1'b0; + WCtrlDataStart_q2 <= 1'b0; + + RStatStart_q1 <= 1'b0; + RStatStart_q2 <= 1'b0; + + InProgress_q1 <= 1'b0; + InProgress_q2 <= 1'b0; + InProgress_q3 <= 1'b0; + + LatchByte0_d <= 1'b0; + LatchByte1_d <= 1'b0; + + LatchByte <= 2'b00; + end + else + begin + if(MdcEn) + begin + WCtrlDataStart_q1 <= WCtrlDataStart; + WCtrlDataStart_q2 <= WCtrlDataStart_q1; + + RStatStart_q1 <= RStatStart; + RStatStart_q2 <= RStatStart_q1; + + LatchByte[0] <= LatchByte0_d; + LatchByte[1] <= LatchByte1_d; + + LatchByte0_d <= LatchByte0_d2; + LatchByte1_d <= LatchByte1_d2; + + InProgress_q1 <= InProgress; + InProgress_q2 <= InProgress_q1; + InProgress_q3 <= InProgress_q2; + end + end +end + + +// Generation of the Operation signals +assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; +assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; +assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; +assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; + +// Busy +reg Busy; +always @ (posedge Clk or posedge Reset) + if (Reset) + Busy <=0; + else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid) + Busy <=1; + else + Busy <=0; + +//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; + + +// Generation of the InProgress signal (indicates when an operation is in progress) +// Generation of the WriteOp signal (indicates when a write is in progress) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + InProgress <= 1'b0; + WriteOp <= 1'b0; + end + else + begin + if(MdcEn) + begin + if(StartOp) + begin + if(~InProgress) + WriteOp <= WriteDataOp; + InProgress <= 1'b1; + end + else + begin + if(EndOp) + begin + InProgress <= 1'b0; + WriteOp <= 1'b0; + end + end + end + end +end + + + +// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + BitCounter[6:0] <= 7'h0; + else + begin + if(MdcEn) + begin + if(InProgress) + begin + if(NoPre & ( BitCounter == 7'h0 )) + BitCounter[6:0] <= 7'h21; + else + BitCounter[6:0] <= BitCounter[6:0] + 1'b1; + end + else + BitCounter[6:0] <= 7'h0; + end + end +end + + +// Operation ends when the Bit Counter reaches 63 +assign EndOp = BitCounter==63; + +assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); +assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); +assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); +assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); + + +// Latch Byte selects which part of Read Status Data is updated from the shift register +assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; +assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; + +wire MdcEn_n; + +// Connecting the Clock Generator Module +eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) + ); + +// Connecting the Shift Register Module +eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), + .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), + .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) + ); + +// Connecting the Output Control Module +eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), + .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), + .Mdo(Mdo), .MdoEn(MdoEn) + ); + +endmodule diff --git a/usrp2/simple_gemac/miim/eth_outputcontrol.v b/usrp2/simple_gemac/miim/eth_outputcontrol.v new file mode 100644 index 000000000..3df6c560a --- /dev/null +++ b/usrp2/simple_gemac/miim/eth_outputcontrol.v @@ -0,0 +1,158 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_outputcontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_outputcontrol.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.4 2002/07/09 20:11:59 mohor +// Comment removed. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); + +input Clk; // Host Clock +input Reset; // General Reset +input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +input NoPre; // No Preamble (no 32-bit preamble) +input InProgress; // Operation in progress +input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal +input [6:0] BitCounter; // Bit Counter +input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. + +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable + +wire SerialEn; + +reg MdoEn_2d; +reg MdoEn_d; +reg MdoEn; + +reg Mdo_2d; +reg Mdo_d; +reg Mdo; // MII Management Data Output + + + +// Generation of the Serial Enable signal (enables the serialization of the data) +assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) + | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); + + +// Generation of the MdoEn signal +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + MdoEn_2d <= 1'b0; + MdoEn_d <= 1'b0; + MdoEn <= 1'b0; + end + else + begin + if(MdcEn_n) + begin + MdoEn_2d <= SerialEn | InProgress & BitCounter<32; + MdoEn_d <= MdoEn_2d; + MdoEn <= MdoEn_d; + end + end +end + + +// Generation of the Mdo signal. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + Mdo_2d <= 1'b0; + Mdo_d <= 1'b0; + Mdo <= 1'b0; + end + else + begin + if(MdcEn_n) + begin + Mdo_2d <= ~SerialEn & BitCounter<32; + Mdo_d <= ShiftedBit | Mdo_2d; + Mdo <= Mdo_d; + end + end +end + + + +endmodule diff --git a/usrp2/simple_gemac/miim/eth_shiftreg.v b/usrp2/simple_gemac/miim/eth_shiftreg.v new file mode 100644 index 000000000..0b97bb7bc --- /dev/null +++ b/usrp2/simple_gemac/miim/eth_shiftreg.v @@ -0,0 +1,159 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_shiftreg.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_shiftreg.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:47 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2002/08/14 18:16:59 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.4 2002/03/02 21:06:01 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, + LatchByte, ShiftedBit, Prsd, LinkFail); + + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. +input Mdi; // MII input data +input [4:0] Fiad; // PHY address +input [4:0] Rgad; // Register address (within the selected PHY) +input [15:0]CtrlData; // Control data (data to be written to the PHY) +input WriteOp; // The current operation is a PHY register write operation +input [3:0] ByteSelect; // Byte select +input [1:0] LatchByte; // Byte select for latching (read operation) + +output ShiftedBit; // Bit shifted out of the shift register +output[15:0]Prsd; // Read Status Data (data read from the PHY) +output LinkFail; // Link Integrity Signal + +reg [7:0] ShiftReg; // Shift register for shifting the data in and out +reg [15:0]Prsd; +reg LinkFail; + + + + +// ShiftReg[7:0] :: Shift Register Data +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + ShiftReg[7:0] <= 8'h0; + Prsd[15:0] <= 16'h0; + LinkFail <= 1'b0; + end + else + begin + if(MdcEn_n) + begin + if(|ByteSelect) + begin + case (ByteSelect[3:0]) + 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; + 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10}; + 4'h4 : ShiftReg[7:0] <= CtrlData[15:8]; + 4'h8 : ShiftReg[7:0] <= CtrlData[7:0]; + default : ShiftReg[7:0] <= 8'h0; + endcase + end + else + begin + ShiftReg[7:0] <= {ShiftReg[6:0], Mdi}; + if(LatchByte[0]) + begin + Prsd[7:0] <= {ShiftReg[6:0], Mdi}; + if(Rgad == 5'h01) + LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet + end + else + begin + if(LatchByte[1]) + Prsd[15:8] <= {ShiftReg[6:0], Mdi}; + end + end + end + end +end + + +assign ShiftedBit = ShiftReg[7]; + + +endmodule diff --git a/usrp2/simple_gemac/rxmac_to_ll8.v b/usrp2/simple_gemac/rxmac_to_ll8.v new file mode 100644 index 000000000..5ec233d95 --- /dev/null +++ b/usrp2/simple_gemac/rxmac_to_ll8.v @@ -0,0 +1,54 @@ + +module rxmac_to_ll8 + (input clk, input reset, input clear, + input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack, + output [7:0] ll_data, output ll_sof, output ll_eof, output ll_error, output ll_src_rdy, input ll_dst_rdy ); + + reg [2:0] xfer_state; + + localparam XFER_IDLE = 0; + localparam XFER_ACTIVE = 1; + localparam XFER_ERROR = 2; + localparam XFER_ERROR2 = 3; + localparam XFER_OVERRUN = 4; + localparam XFER_OVERRUN2 = 5; + + assign ll_data = rx_data; + assign ll_src_rdy = ((rx_valid & (xfer_state != XFER_OVERRUN2) ) + | (xfer_state == XFER_ERROR) + | (xfer_state == XFER_OVERRUN)); + assign ll_sof = ((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN)); + assign ll_eof = (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN)); + assign ll_error = (xfer_state == XFER_ERROR)|(xfer_state==XFER_OVERRUN); + + always @(posedge clk) + if(reset | clear) + xfer_state <= XFER_IDLE; + else + case(xfer_state) + XFER_IDLE : + if(rx_valid) + xfer_state <= XFER_ACTIVE; + XFER_ACTIVE : + if(rx_error) + xfer_state <= XFER_ERROR; + else if(~rx_valid) + xfer_state <= XFER_IDLE; + else if(~ll_dst_rdy) + xfer_state <= XFER_OVERRUN; + XFER_ERROR : + if(ll_dst_rdy) + xfer_state <= XFER_ERROR2; + XFER_ERROR2 : + if(~rx_error) + xfer_state <= XFER_IDLE; + XFER_OVERRUN : + if(ll_dst_rdy) + xfer_state <= XFER_OVERRUN2; + XFER_OVERRUN2 : + if(~rx_valid) + xfer_state <= XFER_IDLE; + endcase // case (xfer_state) + + +endmodule // rxmac_to_ll8 diff --git a/usrp2/simple_gemac/simple_gemac.v b/usrp2/simple_gemac/simple_gemac.v new file mode 100644 index 000000000..e7f327358 --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac.v @@ -0,0 +1,61 @@ + +module simple_gemac + (input clk125, input reset, + // GMII + output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, + input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, + + // Flow Control Interface + input pause_req, input [15:0] pause_time_req, input pause_respect_en, + + // Settings + input [47:0] ucast_addr, input [47:0] mcast_addr, + input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all, + + // RX Client Interface + output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error, output rx_ack, + + // TX Client Interface + output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack + ); + + localparam SGE_IFG = 8'd12; // 12 should be the absolute minimum + + wire rst_rxclk, rst_txclk; + reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk)); + reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk)); + + wire [15:0] pause_quanta_rcvd; + wire pause_rcvd, pause_apply, paused; + + simple_gemac_tx simple_gemac_tx + (.clk125(clk125),.reset(rst_txclk), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack), + .ifg(SGE_IFG), .mac_addr(ucast_addr), + .pause_req(pause_req), .pause_time(pause_time_req), // We request flow control + .pause_apply(pause_apply), .paused(paused) // We respect flow control + ); + + simple_gemac_rx simple_gemac_rx + (.reset(rst_rxclk), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .rx_clk(rx_clk), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), + .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), + .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), + .pass_pause(pass_pause), .pass_all(pass_all), + .pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd) + ); + + flow_ctrl_tx flow_ctrl_tx + (.rst(rst_txclk), .tx_clk(tx_clk), + .tx_pause_en(pause_respect_en), + .pause_quanta(pause_quanta_rcvd), // 16 bit value + .pause_quanta_val(pause_rcvd), + .pause_apply(pause_apply), + .paused(paused) + ); + +endmodule // simple_gemac diff --git a/usrp2/simple_gemac/simple_gemac_rx.v b/usrp2/simple_gemac/simple_gemac_rx.v new file mode 100644 index 000000000..45ddd6dfa --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac_rx.v @@ -0,0 +1,174 @@ + + +module simple_gemac_rx + (input reset, + input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, + output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack, + input [47:0] ucast_addr, input [47:0] mcast_addr, + input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all, + output reg [15:0] pause_quanta_rcvd, output pause_rcvd ); + + localparam RX_IDLE = 0; + localparam RX_PREAMBLE = 1; + localparam RX_FRAME = 2; + localparam RX_GOODFRAME = 3; + localparam RX_DO_PAUSE = 4; + localparam RX_ERROR = 5; + localparam RX_DROP = 6; + + localparam RX_PAUSE = 16; + localparam RX_PAUSE_CHK88 = RX_PAUSE + 5; + localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1; + localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1; + localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1; + localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1; + localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1; + localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1; + + reg [7:0] rxd_d1; + reg rx_dv_d1, rx_er_d1; + assign rx_clk = GMII_RX_CLK; + + always @(posedge rx_clk) + begin + rx_dv_d1 <= GMII_RX_DV; + rx_er_d1 <= GMII_RX_ER; + rxd_d1 <= GMII_RXD; + end + + reg [7:0] rx_state; + wire [7:0] rxd_del; + wire rx_dv_del, rx_er_del; + reg go_filt; + + wire match_crc; + wire clear_crc = rx_state == RX_IDLE; + wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1; + + localparam DELAY = 6; + delay_line #(.WIDTH(10)) rx_delay + (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del})); + + always @(posedge rx_clk) + if(reset) + rx_ack <= 0; + else + rx_ack <= (rx_state == RX_GOODFRAME); + + wire is_ucast, is_bcast, is_mcast, is_pause; + wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | + (pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all; + + assign rx_data = rxd_del; + assign rx_error = (rx_state == RX_ERROR); + + always @(posedge rx_clk) + if(reset) + rx_valid <= 0; + else if(keep_packet) + rx_valid <= 1; + else if((rx_state == RX_IDLE)|(rx_state == RX_ERROR)) + rx_valid <= 0; + + address_filter af_ucast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), + .address(ucast_addr), .match(is_ucast), .done()); + address_filter af_mcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), + .address(mcast_addr), .match(is_mcast), .done()); + address_filter af_bcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), + .address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done()); + address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), + .address(48'h0180_c200_0001), .match(is_pause), .done()); + + always @(posedge rx_clk) + go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5); + + reg [15:0] pkt_len_ctr; + always @(posedge rx_clk) + if(reset |(rx_state == RX_IDLE)) + pkt_len_ctr <= 0; + else + pkt_len_ctr <= pkt_len_ctr + 1; + + localparam MIN_PAUSE_LEN = 71; // 6 + wire pkt_long_enough = (pkt_len_ctr >= MIN_PAUSE_LEN); + always @(posedge rx_clk) + if(reset) + rx_state <= RX_IDLE; + else + if(rx_er_d1) // | (~pkt_long_enough & ~rx_dv_d1) & (rx_state != RX_IDLE)) + rx_state <= RX_ERROR; + else + case(rx_state) + RX_IDLE : + if(rx_dv_d1) + if(rxd_d1 == 8'h55) + rx_state <= RX_PREAMBLE; + else + rx_state <= RX_ERROR; + RX_PREAMBLE : + if(~rx_dv_d1) + rx_state <= RX_ERROR; + else if(rxd_d1 == 8'hD5) + rx_state <= RX_FRAME; + else if(rxd_d1 != 8'h55) + rx_state <= RX_ERROR; + RX_FRAME : + if(is_pause) + rx_state <= RX_PAUSE; + else if(~rx_dv_d1) + if(match_crc) + rx_state <= RX_GOODFRAME; + else + rx_state <= RX_ERROR; + RX_PAUSE_CHK88 : + if(rxd_d1 != 8'h88) + rx_state <= RX_DROP; + else + rx_state <= RX_PAUSE_CHK08; + RX_PAUSE_CHK08 : + if(rxd_d1 != 8'h08) + rx_state <= RX_DROP; + else + rx_state <= RX_PAUSE_CHK00; + RX_PAUSE_CHK00 : + if(rxd_d1 != 8'h00) + rx_state <= RX_DROP; + else + rx_state <= RX_PAUSE_CHK01; + RX_PAUSE_CHK01 : + if(rxd_d1 != 8'h01) + rx_state <= RX_DROP; + else + rx_state <= RX_PAUSE_STORE_MSB; + RX_PAUSE_WAIT_CRC : + if(pkt_long_enough) + if(match_crc) + rx_state <= RX_DO_PAUSE; + else + rx_state <= RX_DROP; + RX_DO_PAUSE : + rx_state <= RX_IDLE; + RX_GOODFRAME : + rx_state <= RX_IDLE; + RX_DROP, RX_ERROR : + if(~rx_dv_d1) + rx_state <= RX_IDLE; + default + rx_state <= rx_state + 1; + endcase // case (rx_state) + + assign pause_rcvd = (rx_state == RX_DO_PAUSE); + crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc), + .data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc)); + + always @(posedge rx_clk) + if(reset) + pause_quanta_rcvd <= 0; + else if(rx_state == RX_PAUSE_STORE_MSB) + pause_quanta_rcvd[15:8] <= rxd_d1; + else if(rx_state == RX_PAUSE_STORE_LSB) + pause_quanta_rcvd[7:0] <= rxd_d1; + + assign rx_clk = GMII_RX_CLK; + +endmodule // simple_gemac_rx diff --git a/usrp2/simple_gemac/simple_gemac_tb.v b/usrp2/simple_gemac/simple_gemac_tb.v new file mode 100644 index 000000000..6091751a7 --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac_tb.v @@ -0,0 +1,200 @@ + + +module simple_gemac_tb; +`include "eth_tasks.v" + + reg clk = 0; + reg reset = 1; + + initial #1000 reset = 0; + always #50 clk = ~clk; + + wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; + wire [7:0] GMII_RXD, GMII_TXD; + + wire rx_valid, rx_error, rx_ack; + wire tx_ack, tx_valid, tx_error; + + wire [7:0] rx_data, tx_data; + + reg [15:0] pause_time; + reg pause_req = 0; + + wire GMII_RX_CLK = GMII_GTX_CLK; + + reg [7:0] FORCE_DAT_ERR = 0; + reg FORCE_ERR = 0; + + // Loopback + assign GMII_RX_DV = GMII_TX_EN; + assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; + assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; + + wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6; + wire [47:0] mcast_addr = 0; + wire pass_ucast =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0; + + simple_gemac simple_gemac + (.clk125(clk), .reset(reset), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .pause_req(pause_req), .pause_time(pause_time), .pause_en(1), + .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), + .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), + .pass_pause(pass_pause), .pass_all(pass_all), + .rx_clk(rx_clk), .rx_data(rx_data), + .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), + .tx_clk(tx_clk), .tx_data(tx_data), + .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack) + ); + + wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2; + reg rx_ll_dst_rdy2 = 1; + wire [7:0] rx_ll_data, rx_ll_data2; + wire rx_ll_error, rx_ll_error2; + + rxmac_to_ll8 rx_adapt + (.clk(clk), .reset(reset), .clear(0), + .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), + .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), + .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); + + ll8_shortfifo rx_sfifo + (.clk(clk), .reset(reset), .clear(0), + .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), + .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), + .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), + .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); + + wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; + reg tx_ll_sof2=0, tx_ll_eof2=0; + reg tx_ll_src_rdy2 = 0; + wire tx_ll_dst_rdy2; + wire [7:0] tx_ll_data; + reg [7:0] tx_ll_data2 = 0; + wire tx_ll_error; + wire tx_ll_error2 = 0; + + ll8_shortfifo tx_sfifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), + .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), + .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), + .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); + + ll8_to_txmac ll8_to_txmac + (.clk(clk), .reset(reset), .clear(clear), + .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), + .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), + .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); + + initial $dumpfile("simple_gemac_tb.vcd"); + initial $dumpvars(0,simple_gemac_tb); + + integer i; + reg [7:0] pkt_rom[0:65535]; + reg [1023:0] ROMFile; + + initial + for (i=0;i<65536;i=i+1) + pkt_rom[i] <= 8'h0; + + initial + begin + @(negedge reset); + repeat (10) + @(posedge clk); + SendFlowCtrl(16'h0007); // Send flow control + @(posedge clk); + #30000; + @(posedge clk); + SendFlowCtrl(16'h0009); // Increas flow control before it expires + #10000; + @(posedge clk); + SendFlowCtrl(16'h0000); // Cancel flow control before it expires + @(posedge clk); + + SendPacket_to_ll8(8'hAA,10); // This packet gets dropped by the filters + repeat (10) + @(posedge clk); + + SendPacketFromFile_ll8(60,0,0); // The rest are valid packets + repeat (10) + @(posedge clk); + + SendPacketFromFile_ll8(61,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_ll8(62,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_ll8(63,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_ll8(64,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_ll8(59,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_ll8(58,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_ll8(100,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_ll8(200,150,30); // waiting 14 empties the fifo, 15 underruns + repeat (1) + @(posedge clk); + SendPacketFromFile_ll8(100,0,30); + #10000 $finish; + end + + // Force a CRC error + initial + begin + #90000; + @(posedge clk); + FORCE_DAT_ERR <= 8'h10; + @(posedge clk); + FORCE_DAT_ERR <= 8'h00; + end + + // Force an RX_ER error (i.e. link loss) + initial + begin + #116000; + @(posedge clk); + FORCE_ERR <= 1; + @(posedge clk); + FORCE_ERR <= 0; + end + + // Cause receive fifo to fill, causing an RX overrun + initial + begin + #126000; + @(posedge clk); + rx_ll_dst_rdy2 <= 0; + repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows + @(posedge clk); + rx_ll_dst_rdy2 <= 1; + end + + // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun + // Still need to test: CRC errors on Pause Frames + + always @(posedge clk) + if(rx_ll_src_rdy2 & rx_ll_dst_rdy2) + begin + if(rx_ll_sof2 & ~rx_ll_eof2) + $display("RX-PKT-START %d",$time); + $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2); + if(rx_ll_eof2 & ~rx_ll_sof2) + $display("RX-PKT-END %d",$time); + end + +endmodule // simple_gemac_tb diff --git a/usrp2/simple_gemac/simple_gemac_tx.v b/usrp2/simple_gemac/simple_gemac_tx.v new file mode 100644 index 000000000..dd870d04d --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac_tx.v @@ -0,0 +1,254 @@ + +module simple_gemac_tx + (input clk125, input reset, + output GMII_GTX_CLK, output reg GMII_TX_EN, output reg GMII_TX_ER, output reg [7:0] GMII_TXD, + output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack, + input [7:0] ifg, input [47:0] mac_addr, + input pause_req, input [15:0] pause_time, + input pause_apply, output reg paused + ); + + reg tx_en_pre, tx_er_pre; + reg [7:0] txd_pre; + + assign GMII_GTX_CLK = clk125; + assign tx_clk = clk125; + + reg [7:0] tx_state; + reg [7:0] ifg_ctr; + reg [15:0] frame_len_ctr; + reg [7:0] pause_ctr, pause_dat; + + wire in_ifg = (ifg_ctr != 0); + + wire [31:0] crc_out; + + localparam TX_IDLE = 0; + localparam TX_PREAMBLE = 1; + localparam TX_SOF_DEL = TX_PREAMBLE + 7; + localparam TX_FIRSTBYTE = TX_SOF_DEL + 1; + localparam TX_IN_FRAME = TX_FIRSTBYTE + 1; + localparam TX_IN_FRAME_2 = TX_IN_FRAME + 1; + localparam TX_PAD = TX_IN_FRAME_2 + 1; + localparam TX_CRC_0 = 16; + localparam TX_CRC_1 = TX_CRC_0 + 1; + localparam TX_CRC_2 = TX_CRC_0 + 2; + localparam TX_CRC_3 = TX_CRC_0 + 3; + localparam TX_ERROR = 32; + localparam TX_PAUSE = 55; + localparam TX_PAUSE_SOF = TX_PAUSE + 7; + localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1; + localparam TX_PAUSE_END = TX_PAUSE_SOF + 18; + + localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes preamble but not CRC + localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we want to handle? + always @(posedge tx_clk) + if(reset |(tx_state == TX_IDLE)) + frame_len_ctr <= 0; + else + frame_len_ctr <= frame_len_ctr + 1; + + reg send_pause; + reg [15:0] pause_time_held; + + always @(posedge tx_clk) + if(reset) + send_pause <= 0; + else if(pause_req) + send_pause <= 1; + else if(tx_state == TX_PAUSE) + send_pause <= 0; + + always @(posedge tx_clk) + if(pause_req) + pause_time_held <= pause_time; + + always @(posedge tx_clk) + if(reset) + tx_state <= TX_IDLE; + else + case(tx_state) + TX_IDLE : + if(~in_ifg) + if(send_pause) + tx_state <= TX_PAUSE; + else if(tx_valid & ~pause_apply) + tx_state <= TX_PREAMBLE; + TX_FIRSTBYTE : + if(tx_error) + tx_state <= TX_ERROR; // underrun + else if(~tx_valid) + tx_state <= TX_PAD; + else + tx_state <= TX_IN_FRAME; + TX_IN_FRAME : + if(tx_error) + tx_state <= TX_ERROR; // underrun + else if(~tx_valid) + tx_state <= TX_PAD; + else if(frame_len_ctr == MIN_FRAME_LEN - 1) + tx_state <= TX_IN_FRAME_2; + TX_IN_FRAME_2 : + if(tx_error) + tx_state <= TX_ERROR; // underrun + else if(~tx_valid) + tx_state <= TX_CRC_0; + TX_PAD : + if(frame_len_ctr == MIN_FRAME_LEN) + tx_state <= TX_CRC_0; + TX_CRC_3 : + tx_state <= TX_IDLE; + TX_ERROR : + tx_state <= TX_IDLE; + TX_PAUSE_END : + tx_state <= TX_PAD; + default : + tx_state <= tx_state + 1; + endcase // case (tx_state) + + always @(posedge tx_clk) + if(reset) + begin + tx_en_pre <= 0; + tx_er_pre <= 0; + txd_pre <= 0; + end + else + casex(tx_state) + TX_IDLE : + begin + tx_en_pre <= 0; + tx_er_pre <= 0; + txd_pre <= 0; + end + TX_PREAMBLE, TX_PAUSE : + begin + txd_pre <= 8'h55; + tx_en_pre <= 1; + end + TX_SOF_DEL, TX_PAUSE_SOF : + txd_pre <= 8'hD5; + TX_FIRSTBYTE, TX_IN_FRAME, TX_IN_FRAME_2 : + txd_pre <= tx_valid ? tx_data : 0; + TX_ERROR : + begin + tx_er_pre <= 1; + txd_pre <= 0; + end + TX_CRC_3 : + tx_en_pre <= 0; + TX_PAD : + txd_pre <= 0; + TX_PAUSE_FIRST, 8'b01xx_xxxx : // In Pause Frame + txd_pre <= pause_dat; + endcase // case (tx_state) + + localparam SGE_FLOW_CTRL_ADDR = 48'h01_80_C2_00_00_01; + always @(posedge tx_clk) + case(tx_state) + TX_PAUSE_SOF : + pause_dat <= SGE_FLOW_CTRL_ADDR[47:40]; // Note everything must be 1 cycle early + TX_PAUSE_SOF + 1: + pause_dat <= SGE_FLOW_CTRL_ADDR[39:32]; + TX_PAUSE_SOF + 2: + pause_dat <= SGE_FLOW_CTRL_ADDR[31:24]; + TX_PAUSE_SOF + 3: + pause_dat <= SGE_FLOW_CTRL_ADDR[23:16]; + TX_PAUSE_SOF + 4: + pause_dat <= SGE_FLOW_CTRL_ADDR[15:8]; + TX_PAUSE_SOF + 5: + pause_dat <= SGE_FLOW_CTRL_ADDR[7:0]; + TX_PAUSE_SOF + 6: + pause_dat <= mac_addr[47:40]; + TX_PAUSE_SOF + 7: + pause_dat <= mac_addr[39:32]; + TX_PAUSE_SOF + 8: + pause_dat <= mac_addr[31:24]; + TX_PAUSE_SOF + 9: + pause_dat <= mac_addr[23:16]; + TX_PAUSE_SOF + 10: + pause_dat <= mac_addr[15:8]; + TX_PAUSE_SOF + 11: + pause_dat <= mac_addr[7:0]; + TX_PAUSE_SOF + 12: + pause_dat <= 8'h88; // Type = 8808 = MAC ctrl frame + TX_PAUSE_SOF + 13: + pause_dat <= 8'h08; + TX_PAUSE_SOF + 14: + pause_dat <= 8'h00; // Opcode = 0001 = PAUSE + TX_PAUSE_SOF + 15: + pause_dat <= 8'h01; + TX_PAUSE_SOF + 16: + pause_dat <= pause_time_held[15:8]; + TX_PAUSE_SOF + 17: + pause_dat <= pause_time_held[7:0]; + endcase // case (tx_state) + + wire start_ifg = (tx_state == TX_CRC_3); + always @(posedge tx_clk) + if(reset) + ifg_ctr <= 100; + else if(start_ifg) + ifg_ctr <= ifg; + else if(ifg_ctr != 0) + ifg_ctr <= ifg_ctr - 1; + + wire clear_crc = (tx_state == TX_IDLE); + + wire calc_crc = + (tx_state==TX_IN_FRAME) | + (tx_state==TX_IN_FRAME_2) | + (tx_state==TX_PAD) | + (tx_state[6]); + + crc crc(.clk(tx_clk), .reset(reset), .clear(clear_crc), + .data(txd_pre), .calc(calc_crc), .crc_out(crc_out)); + + assign tx_ack = (tx_state == TX_FIRSTBYTE); + + always @(posedge tx_clk) + begin + GMII_TX_EN <= tx_en_pre; + GMII_TX_ER <= tx_er_pre; + case(tx_state) + TX_CRC_0 : + GMII_TXD <= crc_out[31:24]; + TX_CRC_1 : + GMII_TXD <= crc_out[23:16]; + TX_CRC_2 : + GMII_TXD <= crc_out[15:8]; + TX_CRC_3 : + GMII_TXD <= crc_out[7:0]; + default : + GMII_TXD <= txd_pre; + endcase // case (tx_state) + end + + // report that we are paused only when we get back to IDLE + always @(posedge tx_clk) + if(reset) + paused <= 0; + else if(~pause_apply) + paused <= 0; + else if(tx_state == TX_IDLE) + paused <= 1; + +endmodule // simple_gemac_tx + +// Testing code +/* + reg [7:0] crc_ctr; + reg calc_crc_d1; + always @(posedge tx_clk) + calc_crc_d1 <= calc_crc; + + always @(posedge tx_clk) + if(reset) + crc_ctr <= 0; + else if(calc_crc) + crc_ctr <= crc_ctr+1; + else if(calc_crc_d1) + $display("CRC COUNT = %d",crc_ctr); + else + crc_ctr <= 0; +*/ diff --git a/usrp2/simple_gemac/simple_gemac_wb.v b/usrp2/simple_gemac/simple_gemac_wb.v new file mode 100644 index 000000000..6df277e3e --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac_wb.v @@ -0,0 +1,161 @@ + +module wb_reg + #(parameter ADDR=0, + parameter DEFAULT=0) + (input clk, input rst, + input [5:0] adr, input wr_acc, + input [31:0] dat_i, output reg [31:0] dat_o); + + always @(posedge clk) + if(rst) + dat_o <= DEFAULT; + else if(wr_acc & (adr == ADDR)) + dat_o <= dat_i; + +endmodule // wb_reg + + + +module simple_gemac_wb + (input wb_clk, input wb_rst, + input wb_cyc, input wb_stb, output reg wb_ack, input wb_we, + input [7:0] wb_adr, input [31:0] wb_dat_i, output reg [31:0] wb_dat_o, + + inout mdio, output mdc, + output [47:0] ucast_addr, output [47:0] mcast_addr, + output pass_ucast, output pass_mcast, output pass_bcast, + output pass_pause, output pass_all, + output pause_respect_en, output pause_request_en, + output [15:0] pause_time, output [15:0] pause_thresh ); + + wire acc = wb_cyc & wb_stb; + wire wr_acc = wb_cyc & wb_stb & wb_we; + wire rd_acc = wb_cyc & wb_stb & ~wb_we; + + always @(posedge wb_clk) + if(wb_rst) + wb_ack <= 0; + else + wb_ack <= acc & ~wb_ack; + + wire [6:0] misc_settings; + assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings; + + wb_reg #(.ADDR(0),.DEFAULT(7'b0111001)) + wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(misc_settings) ); + wb_reg #(.ADDR(1),.DEFAULT(0)) + wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) ); + wb_reg #(.ADDR(2),.DEFAULT(0)) + wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) ); + wb_reg #(.ADDR(3),.DEFAULT(0)) + wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) ); + wb_reg #(.ADDR(4),.DEFAULT(0)) + wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) ); + + //MII to CPU + wire [7:0] Divider; // Divider for the host clock + wire [15:0] CtrlData; // Control Data (to be written to the PHY reg.) + wire [4:0] Rgad; // Register Address (within the PHY) + wire [4:0] Fiad; // PHY Address + wire NoPre; // No Preamble (no 32-bit preamble) + wire WCtrlData; // Write Control Data operation + wire RStat; // Read Status operation + wire ScanStat; // Scan Status operation + wire Busy; // Busy Signal + wire LinkFail; // Link Integrity Signal + wire Nvalid; // Invalid Status (qualifier for the valid scan result) + wire [15:0] Prsd; // Read Status Data (data read from the PHY) + wire WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register + wire RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register + wire UpdateMIIRX_DATAReg; // Updates MII RX_DATA register with read data + + // registers for controlling the MII interface + reg [2:0] MIICOMMAND; + wire [12:0] MIIADDRESS; + reg [15:0] MIIRX_DATA; + wire [2:0] MIISTATUS; + + wb_reg #(.ADDR(5),.DEFAULT(0)) + wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) ); + + wb_reg #(.ADDR(6),.DEFAULT(0)) + wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(MIIADDRESS) ); + + wb_reg #(.ADDR(7),.DEFAULT(0)) + wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(CtrlData) ); + + // MIICOMMAND register - needs special treatment because of auto-resetting bits + always @ (posedge wb_clk) + if (wb_rst) + MIICOMMAND <= 0; + else + if (wr_acc & (wb_adr[7:2] == 6'd8)) + MIICOMMAND <= wb_dat_i; + else + begin + if ( WCtrlDataStart ) + MIICOMMAND[2] <= 0; + if ( RStatStart ) + MIICOMMAND[1] <= 0; + end + + // MIIRX_DATA register + always @(posedge wb_clk) + if (wb_rst) + MIIRX_DATA <= 0; + else + if (UpdateMIIRX_DATAReg ) + MIIRX_DATA <= Prsd; + + // MIICOMMAND + assign WCtrlData = MIICOMMAND[2]; + assign RStat = MIICOMMAND[1]; + assign ScanStat = MIICOMMAND[0]; + // MIIADDRESS + assign Rgad = MIIADDRESS[12:8]; + assign Fiad = MIIADDRESS[4:0]; + // MIISTATUS + assign MIISTATUS[2:0] = { Nvalid, Busy, LinkFail }; + + eth_miim eth_miim + (.Clk(wb_clk), .Reset(wb_rst), + .Divider(Divider), .NoPre(NoPre), .CtrlData(CtrlData), .Rgad(Rgad), .Fiad(Fiad), + .WCtrlData(WCtrlData), .RStat(RStat), .ScanStat(ScanStat), .Mdio(mdio), .Mdc(mdc), + .Busy(Busy), .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(Nvalid), + .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), + .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) ); + + wb_reg #(.ADDR(11),.DEFAULT(0)) + wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(pause_time) ); + + wb_reg #(.ADDR(12),.DEFAULT(0)) + wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(pause_thresh) ); + + always @(posedge wb_clk) + case(wb_adr[7:2]) + 0 : wb_dat_o <= misc_settings; + 1 : wb_dat_o <= ucast_addr[47:32]; + 2 : wb_dat_o <= ucast_addr[31:0]; + 3 : wb_dat_o <= mcast_addr[47:32]; + 4 : wb_dat_o <= mcast_addr[31:0]; + 5 : wb_dat_o <= {NoPre,Divider}; + 6 : wb_dat_o <= MIIADDRESS; + 7 : wb_dat_o <= CtrlData; + 8 : wb_dat_o <= MIICOMMAND; + 9 : wb_dat_o <= MIISTATUS; + 10: wb_dat_o <= MIIRX_DATA; + 11: wb_dat_o <= pause_time; + 12: wb_dat_o <= pause_thresh; + endcase // case (wb_adr[7:2]) + +endmodule // simple_gemac_wb diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.build b/usrp2/simple_gemac/simple_gemac_wrapper.build new file mode 100755 index 000000000..30f65ab17 --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac_wrapper.build @@ -0,0 +1 @@ +iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v new file mode 100644 index 000000000..efcf89276 --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -0,0 +1,165 @@ + +module simple_gemac_wrapper + #(parameter RXFIFOSIZE=9, + parameter TXFIFOSIZE=6) + (input clk125, input reset, + // GMII + output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, + input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, + + // Client FIFO Interfaces + input sys_clk, + output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, + input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, + + // Wishbone Interface + input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, + input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, + + // MIIM + inout mdio, output mdc, + output [31:0] debug); + + wire clear = 0; + wire [7:0] rx_data, tx_data; + wire tx_clk, tx_valid, tx_error, tx_ack; + wire rx_clk, rx_valid, rx_error, rx_ack; + + wire [47:0] ucast_addr, mcast_addr; + wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all; + wire pause_req; + wire pause_request_en, pause_respect_en; + wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; + + wire tx_reset, rx_reset; + reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset)); + reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset)); + + simple_gemac simple_gemac + (.clk125(clk125), .reset(reset), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .pause_req(pause_req), .pause_time_req(pause_time_req), + .pause_respect_en(pause_respect_en), + .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), + .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), + .pass_pause(pass_pause), .pass_all(pass_all), + .rx_clk(rx_clk), .rx_data(rx_data), + .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), + .tx_clk(tx_clk), .tx_data(tx_data), + .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack) + ); + + simple_gemac_wb simple_gemac_wb + (.wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we), + .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), + .mdio(mdio), .mdc(mdc), + .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), + .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), + .pass_pause(pass_pause), .pass_all(pass_all), + .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en), + .pause_time(pause_time), .pause_thresh(pause_thresh) ); + + // RX FIFO Chain + wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + + wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; + wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; + + wire [7:0] rx_ll_data, rx_ll_data2; + + wire [35:0] rx_f36_data_int1; + wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; + + rxmac_to_ll8 rx_adapt + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), + .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof + .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); + + ll8_shortfifo rx_sfifo + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), + .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), + .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), + .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); + + assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; + assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2; + assign rx_ll_sof2_n = ~rx_ll_sof2; + assign rx_ll_eof2_n = ~rx_ll_eof2; + + ll8_to_fifo36 ll8_to_fifo36 + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n), + .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), + .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1)); + + fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo + (.wclk(rx_clk), .datain(rx_f36_data_int1), + .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space), + .rclk(sys_clk), .dataout(rx_f36_data), + .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset)); + + // TX FIFO Chain + wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; + wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; + wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n; + wire [7:0] tx_ll_data, tx_ll_data2; + wire [35:0] tx_f36_data_int1; + wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; + + fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo + (.wclk(sys_clk), .datain(tx_f36_data), + .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), + .rclk(tx_clk), .dataout(tx_f36_data_int1), + .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset)); + + fifo36_to_ll8 fifo36_to_ll8 + (.clk(tx_clk), .reset(tx_reset), .clear(clear), + .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), + .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), + .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n)); + + assign tx_ll_sof2 = ~tx_ll_sof2_n; + assign tx_ll_eof2 = ~tx_ll_eof2_n; + assign tx_ll_src_rdy2 = ~tx_ll_src_rdy2_n; + assign tx_ll_dst_rdy2_n = ~tx_ll_dst_rdy2; + + ll8_shortfifo tx_sfifo + (.clk(tx_clk), .reset(tx_reset), .clear(clear), + .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), + .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), + .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), + .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); + + ll8_to_txmac ll8_to_txmac + (.clk(tx_clk), .reset(tx_reset), .clear(clear), + .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), + .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), + .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); + + flow_ctrl_rx flow_ctrl_rx + (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh), + .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space), + .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req)); + + wire [31:0] debug_tx, debug_rx; + + assign debug_tx = { { tx_ll_data }, + { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, + tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, + { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, + { tx_data} }; + assign debug_rx = { { rx_ll_data }, + { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, + rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 }, + { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]}, + { rx_data} }; + + assign debug = debug_rx; + +endmodule // simple_gemac_wrapper diff --git a/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v new file mode 100644 index 000000000..804fa8748 --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v @@ -0,0 +1,243 @@ + + +module simple_gemac_wrapper_f36_tb; +`include "eth_tasks_f36.v" + + reg clk = 0; + reg reset = 1; + + initial #1000 reset = 0; + always #50 clk = ~clk; + + reg wb_clk = 0; + wire wb_rst = reset; + always #173 wb_clk = ~wb_clk; + + wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; + wire [7:0] GMII_RXD, GMII_TXD; + + wire rx_valid, rx_error, rx_ack; + wire tx_ack, tx_valid, tx_error; + + wire [7:0] rx_data, tx_data; + + reg [15:0] pause_time; + reg pause_req = 0; + + wire GMII_RX_CLK = GMII_GTX_CLK; + + reg [7:0] FORCE_DAT_ERR = 0; + reg FORCE_ERR = 0; + + // Loopback + assign GMII_RX_DV = GMII_TX_EN; + assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; + assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; + + + wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2; + wire rx_ll_dst_rdy2; + wire [7:0] rx_ll_data, rx_ll_data2; + wire rx_ll_error, rx_ll_error2; + + wire [31:0] wb_dat_o; + reg [31:0] wb_dat_i; + reg [7:0] wb_adr; + reg wb_stb=0, wb_cyc=0, wb_we=0; + wire wb_ack; + + reg [35:0] tx_f36_dat; + reg tx_f36_src_rdy; + wire tx_f36_dst_rdy; + + wire [35:0] rx_f36_dat; + wire rx_f36_src_rdy; + reg rx_f36_dst_rdy = 1; + + simple_gemac_wrapper simple_gemac_wrapper + (.clk125(clk), .reset(reset), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .pause_req(pause_req), .pause_time(pause_time), + .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof), + .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), .rx_ll_dst_rdy(rx_ll_dst_rdy), + .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof), + .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), .tx_ll_dst_rdy(tx_ll_dst_rdy), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), + .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), + .mdio(mdio), .mdc(mdc) ); + + wire rx_ll_dst_rdy2_n; + assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; + + ll8_shortfifo rx_sfifo + (.clk(clk), .reset(reset), .clear(0), + .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), + .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), + .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), + .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); + + ll8_to_fifo36 ll8_to_fifo36 + (.clk(clk), .reset(reset), .clear(0), + .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2), + .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), + .f36_data(rx_f36_dat), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy)); + + wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; + wire tx_ll_sof2_n, tx_ll_eof2_n; + wire tx_ll_src_rdy2_n, tx_ll_dst_rdy2; + wire [7:0] tx_ll_data, tx_ll_data2; + wire tx_ll_error; + wire tx_ll_error2 = 0; + + fifo36_to_ll8 fifo36_to_ll8 + (.clk(clk), .reset(reset), .clear(clear), + .f36_data(tx_f36_dat), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), + .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2)); + + ll8_shortfifo tx_sfifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(tx_ll_data2), .sof_i(~tx_ll_sof2_n), .eof_i(~tx_ll_eof2_n), + .error_i(tx_ll_error2), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2), + .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), + .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); + + initial $dumpfile("simple_gemac_wrapper_f36_tb.vcd"); + initial $dumpvars(0,simple_gemac_wrapper_f36_tb); + + integer i; + reg [7:0] pkt_rom[0:65535]; + reg [1023:0] ROMFile; + + initial + for (i=0;i<65536;i=i+1) + pkt_rom[i] <= 8'h0; + + initial + begin + @(negedge reset); + repeat (10) + @(posedge clk); + WishboneWR(0,6'b111001); + WishboneWR(4,16'hF1F2); + WishboneWR(8,32'hF3F4_F5F6); + WishboneWR(12,16'h0000); + WishboneWR(16,32'h0000_0000); + + @(posedge clk); + SendFlowCtrl(16'h0007); // Send flow control + @(posedge clk); + #30000; + @(posedge clk); + SendFlowCtrl(16'h0009); // Increase flow control before it expires + #10000; + @(posedge clk); + SendFlowCtrl(16'h0000); // Cancel flow control before it expires + @(posedge clk); + + SendPacket_to_fifo36(8'hAA,10); // This packet gets dropped by the filters + repeat (10) + @(posedge clk); + + SendPacketFromFile_fifo36(60,0,0); // The rest are valid packets + repeat (10) + @(posedge clk); + + SendPacketFromFile_fifo36(61,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_fifo36(62,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_fifo36(63,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_fifo36(64,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_fifo36(59,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_fifo36(58,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_fifo36(100,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_fifo36(200,150,30); // waiting 14 empties the fifo, 15 underruns + repeat (1) + @(posedge clk); + SendPacketFromFile_fifo36(100,0,30); + #10000 $finish; + end +/* + // Force a CRC error + initial + begin + #90000; + @(posedge clk); + FORCE_DAT_ERR <= 8'h10; + @(posedge clk); + FORCE_DAT_ERR <= 8'h00; + end + + // Force an RX_ER error (i.e. link loss) + initial + begin + #116000; + @(posedge clk); + FORCE_ERR <= 1; + @(posedge clk); + FORCE_ERR <= 0; + end + + // Cause receive fifo to fill, causing an RX overrun + initial + begin + #126000; + @(posedge clk); + rx_f36_dst_rdy <= 0; + repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows + @(posedge clk); + rx_f36_dst_rdy <= 1; + end + */ + // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun + // Still need to test: CRC errors on Pause Frames, MDIO, wishbone + + task WishboneWR; + input [7:0] adr; + input [31:0] value; + begin + wb_adr <= adr; + wb_dat_i <= value; + wb_stb <= 1; + wb_cyc <= 1; + wb_we <= 1; + while (~wb_ack) + @(posedge wb_clk); + @(posedge wb_clk); + wb_stb <= 0; + wb_cyc <= 0; + wb_we <= 0; + end + endtask // WishboneWR + + always @(posedge clk) + if(rx_f36_src_rdy & rx_f36_dst_rdy) + begin + if(rx_f36_dat[32] & ~rx_f36_dat[33]) + $display("RX-PKT-START %d",$time); + $display("RX-PKT SOF %d EOF %d ERR %d OCC %d DAT %x",rx_f36_dat[32],rx_f36_dat[33], + &rx_f36_dat[33:32],rx_f36_dat[35:34],rx_f36_dat[31:0]); + if(rx_f36_dat[33] & ~rx_f36_dat[32]) + $display("RX-PKT-END %d",$time); + if(rx_f36_dat[33] & rx_f36_dat[32]) + $display("RX-PKT-ERROR %d",$time); + end + +endmodule // simple_gemac_wrapper_tb diff --git a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v new file mode 100644 index 000000000..26a471a49 --- /dev/null +++ b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v @@ -0,0 +1,209 @@ + + +module simple_gemac_wrapper_tb; +`include "eth_tasks_f36.v" + + reg reset = 1; + initial #1000 reset = 0; + wire wb_rst = reset; + + reg eth_clk = 0; + always #50 eth_clk = ~eth_clk; + + reg wb_clk = 0; + always #173 wb_clk = ~wb_clk; + + reg sys_clk = 0; + always #77 sys_clk = ~ sys_clk; + + wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK; + wire [7:0] GMII_RXD, GMII_TXD; + + wire rx_valid, rx_error, rx_ack; + wire tx_ack, tx_valid, tx_error; + + wire [7:0] rx_data, tx_data; + + reg [15:0] pause_time; + reg pause_req = 0; + + wire GMII_RX_CLK = GMII_GTX_CLK; + + reg [7:0] FORCE_DAT_ERR = 0; + reg FORCE_ERR = 0; + + // Loopback + assign GMII_RX_DV = GMII_TX_EN; + assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR; + assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR; + + + wire [31:0] wb_dat_o; + reg [31:0] wb_dat_i; + reg [7:0] wb_adr; + reg wb_stb=0, wb_cyc=0, wb_we=0; + wire wb_ack; + + reg [35:0] tx_f36_data=0; + reg tx_f36_src_rdy = 0; + wire tx_f36_dst_rdy; + wire rx_f36_data; + wire rx_f36_src_rdy; + wire rx_f36_dst_rdy = 1; + + simple_gemac_wrapper simple_gemac_wrapper + (.clk125(eth_clk), .reset(reset), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .pause_req(pause_req), .pause_time(pause_time), + + .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy), + .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy), + + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we), + .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), + + .mdio(), .mdc(), + .debug() ); + + initial $dumpfile("simple_gemac_wrapper_tb.vcd"); + initial $dumpvars(0,simple_gemac_wrapper_tb); + + integer i; + reg [7:0] pkt_rom[0:65535]; + reg [1023:0] ROMFile; + + initial + for (i=0;i<65536;i=i+1) + pkt_rom[i] <= 8'h0; + + initial + begin + @(negedge reset); + repeat (10) + @(posedge wb_clk); + WishboneWR(0,6'b111101); + WishboneWR(4,16'hA0B0); + WishboneWR(8,32'hC0D0_A1B1); + WishboneWR(12,16'h0000); + WishboneWR(16,32'h0000_0000); + + @(posedge eth_clk); + SendFlowCtrl(16'h0007); // Send flow control + @(posedge eth_clk); + #30000; + @(posedge eth_clk); + SendFlowCtrl(16'h0009); // Increase flow control before it expires + #10000; + @(posedge eth_clk); + SendFlowCtrl(16'h0000); // Cancel flow control before it expires + @(posedge eth_clk); + + repeat (1000) + @(posedge sys_clk); + SendPacket_to_fifo36(32'hA0B0C0D0,10); // This packet gets dropped by the filters + repeat (1000) + @(posedge sys_clk); + + SendPacket_to_fifo36(32'hAABBCCDD,100); // This packet gets dropped by the filters + repeat (10) + @(posedge sys_clk); +/* + SendPacketFromFile_f36(60,0,0); // The rest are valid packets + repeat (10) + @(posedge clk); + + SendPacketFromFile_f36(61,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_f36(62,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_f36(63,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_f36(64,0,0); + repeat (10) + @(posedge clk); + SendPacketFromFile_f36(59,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_f36(58,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_f36(100,0,0); + repeat (1) + @(posedge clk); + SendPacketFromFile_f36(200,150,30); // waiting 14 empties the fifo, 15 underruns + repeat (1) + @(posedge clk); + SendPacketFromFile_f36(100,0,30); + */ + #100000 $finish; + end + + // Force a CRC error + initial + begin + #90000; + @(posedge eth_clk); + FORCE_DAT_ERR <= 8'h10; + @(posedge eth_clk); + FORCE_DAT_ERR <= 8'h00; + end + + // Force an RX_ER error (i.e. link loss) + initial + begin + #116000; + @(posedge eth_clk); + FORCE_ERR <= 1; + @(posedge eth_clk); + FORCE_ERR <= 0; + end +/* + // Cause receive fifo to fill, causing an RX overrun + initial + begin + #126000; + @(posedge clk); + rx_ll_dst_rdy2 <= 0; + repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows + @(posedge clk); + rx_ll_dst_rdy2 <= 1; + end + */ + // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun + // Still need to test: CRC errors on Pause Frames, MDIO, wishbone + + task WishboneWR; + input [7:0] adr; + input [31:0] value; + begin + wb_adr <= adr; + wb_dat_i <= value; + wb_stb <= 1; + wb_cyc <= 1; + wb_we <= 1; + while (~wb_ack) + @(posedge wb_clk); + @(posedge wb_clk); + wb_stb <= 0; + wb_cyc <= 0; + wb_we <= 0; + end + endtask // WishboneWR + /* + always @(posedge clk) + if(rx_ll_src_rdy2 & rx_ll_dst_rdy2) + begin + if(rx_ll_sof2 & ~rx_ll_eof2) + $display("RX-PKT-START %d",$time); + $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2); + if(rx_ll_eof2 & ~rx_ll_sof2) + $display("RX-PKT-END %d",$time); + end + */ +endmodule // simple_gemac_wrapper_tb diff --git a/usrp2/simple_gemac/test_packet.mem b/usrp2/simple_gemac/test_packet.mem new file mode 100644 index 000000000..7f41d3e42 --- /dev/null +++ b/usrp2/simple_gemac/test_packet.mem @@ -0,0 +1,66 @@ +ff +ff +ff +ff +ff +ff +08 +00 +07 +5c +2e +e4 +08 +06 +00 +01 +08 +04 +06 +02 +00 +01 +08 +00 +07 +5c +2e +e4 +03 +64 +00 +00 +00 +00 +00 +00 +02 +64 +00 +3a +f3 +5c +4f +12 +01 +10 +00 +01 +00 +00 +00 +00 +00 +00 +20 +41 +42 +41 +08 +00 +AA +BB +CC +DD +EE +FF diff --git a/usrp2/testbench/.gitignore b/usrp2/testbench/.gitignore new file mode 100644 index 000000000..eedcf9652 --- /dev/null +++ b/usrp2/testbench/.gitignore @@ -0,0 +1,5 @@ +/single_u2_sim +/dual_u2_sim +/*.lxt +/*.vcd +/*.sav diff --git a/usrp2/testbench/Makefile b/usrp2/testbench/Makefile new file mode 100644 index 000000000..6032a0123 --- /dev/null +++ b/usrp2/testbench/Makefile @@ -0,0 +1,10 @@ +all: single dual + +single: + iverilog -Wimplicit -Wportbind -c cmdfile ../top/single_u2_sim/single_u2_sim.v -o single_u2_sim + +dual: + iverilog -Wimplicit -Wportbind -c cmdfile ../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim + +clean: + rm -f single_u2_sim dual_u2_sim *.vcd *.lxt diff --git a/usrp2/testbench/README b/usrp2/testbench/README new file mode 100644 index 000000000..14bbb68bb --- /dev/null +++ b/usrp2/testbench/README @@ -0,0 +1,5 @@ +The path to happiness: + +make clean +make +./u2_sim +rom=../../firmware/eth_test.rom -lxt2 diff --git a/usrp2/testbench/cmdfile b/usrp2/testbench/cmdfile new file mode 100644 index 000000000..8083eb92a --- /dev/null +++ b/usrp2/testbench/cmdfile @@ -0,0 +1,27 @@ + +# My stuff +-y . +-y ../top/u2_core +-y ../control_lib +-y ../control_lib/newfifo +-y ../serdes +-y ../sdr_lib +-y ../timing +-y ../coregen +-y ../extram +-y ../simple_gemac +-y ../simple_gemac/miim + +# Models +-y ../models +-y ../models/CY7C1356C + +# Open Cores +-y ../opencores/8b10b +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog +-y ../opencores/aemb/rtl/verilog +-y ../opencores/simple_pic/rtl + diff --git a/usrp2/timing/.gitignore b/usrp2/timing/.gitignore new file mode 100644 index 000000000..515552fdb --- /dev/null +++ b/usrp2/timing/.gitignore @@ -0,0 +1,2 @@ +/a.out +/*.vcd diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v new file mode 100644 index 000000000..c0a846e74 --- /dev/null +++ b/usrp2/timing/time_64bit.v @@ -0,0 +1,63 @@ + + +module time_64bit + #(parameter TICKS_PER_SEC = 32'd100000000, + parameter BASE = 0) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input pps, + output [63:0] vita_time + ); + + localparam NEXT_TICKS = 0; + localparam NEXT_SECS = 1; + localparam ROLLOVER = TICKS_PER_SEC - 1; + + assign vita_time = {seconds,ticks}; + + wire [31:0] next_ticks_preset; + wire [31:0] next_seconds_preset; + wire set_on_pps_trig; + reg set_on_next_pps; + + setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(next_ticks_preset),.changed()); + + setting_reg #(.my_addr(BASE+NEXT_SECS)) sr_next_secs + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig)); + + reg [31:0] seconds; + reg [31:0] ticks; + + wire end_of_second; + + always @(posedge clk) + if(rst) + set_on_next_pps <= 0; + else if(set_on_pps_trig) + set_on_next_pps <= 1; + else if(pps) + set_on_next_pps <= 0; + + always @(posedge clk) + if(rst) + begin + seconds <= 32'd0; + ticks <= 32'd0; + end + else if(pps & set_on_next_pps) + begin + seconds <= next_seconds_preset; + ticks <= next_ticks_preset; + end + else if(ticks == ROLLOVER) + begin + seconds <= seconds + 1; + ticks <= 0; + end + else + ticks <= ticks + 1; + +endmodule // time_64bit diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v new file mode 100644 index 000000000..8e7d3f1ea --- /dev/null +++ b/usrp2/timing/time_receiver.v @@ -0,0 +1,94 @@ + +module time_receiver + (input clk, input rst, + output [31:0] master_time, + output sync_rcvd, + input exp_pps_in); + + wire code_err, disp_err, dispout, complete_word; + reg disp_reg; + reg [9:0] shiftreg; + reg [3:0] bit_count; + wire [8:0] dataout; + reg [8:0] dataout_reg; + + always @(posedge clk) + shiftreg <= {exp_pps_in, shiftreg[9:1]}; + + localparam COMMA_0 = 10'h283; + localparam COMMA_1 = 10'h17c; + + wire found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1); + wire set_disp = (shiftreg == COMMA_1); + + always @(posedge clk) + if(rst) + bit_count <= 0; + else if(found_comma | complete_word) + bit_count <= 0; + else + bit_count <= bit_count + 1; + assign complete_word = (bit_count == 9); + + always @(posedge clk) + if(set_disp) + disp_reg <= 1; + else if(complete_word) + disp_reg <= dispout; + + always @(posedge clk) + if(complete_word) + dataout_reg <= dataout; + + decode_8b10b decode_8b10b + (.datain(shiftreg),.dispin(disp_reg), + .dataout(dataout),.dispout(dispout), + .code_err(code_err),.disp_err(disp_err) ); + + reg error; + always @(posedge clk) + if(complete_word) + error <= code_err | disp_err; + + localparam STATE_IDLE = 0; + localparam STATE_T0 = 1; + localparam STATE_T1 = 2; + localparam STATE_T2 = 3; + localparam STATE_T3 = 4; + + localparam HEAD = 9'h13c; + + reg [7:0] clock_a, clock_b, clock_c; + reg [2:0] state; + + always @(posedge clk) + if(rst) + state <= STATE_IDLE; + else if(complete_word) + case(state) + STATE_IDLE : + if(dataout_reg == HEAD) + state <= STATE_T0; + STATE_T0 : + begin + clock_a <= dataout_reg[7:0]; + state <= STATE_T1; + end + STATE_T1 : + begin + clock_b <= dataout_reg[7:0]; + state <= STATE_T2; + end + STATE_T2 : + begin + clock_c <= dataout_reg[7:0]; + state <= STATE_T3; + end + STATE_T3 : + state <= STATE_IDLE; + endcase // case(state) + + assign master_time = {clock_a, clock_b, clock_c, dataout_reg[7:0]}; + assign sync_rcvd = (complete_word & (state == STATE_T3)); + +endmodule // time_sender diff --git a/usrp2/timing/time_sender.v b/usrp2/timing/time_sender.v new file mode 100644 index 000000000..aa2fcbbdb --- /dev/null +++ b/usrp2/timing/time_sender.v @@ -0,0 +1,110 @@ + + +module time_sender + (input clk, input rst, + input [31:0] master_time, + input send_sync, + output exp_pps_out); + + reg [7:0] datain; + reg k; + wire [9:0] dataout; + reg [9:0] dataout_reg; + reg disp_reg; + wire disp, new_word; + + encode_8b10b encode_8b10b + (.datain({k,datain}),.dispin(disp_reg), + .dataout(dataout),.dispout(disp)); + + assign exp_pps_out = dataout_reg[0]; + + always @(posedge clk) + if(rst) + disp_reg <= 0; + else if(new_word) + disp_reg <= disp; + + always @(posedge clk) + if(rst) + dataout_reg <= 0; + else if(new_word) + dataout_reg <= dataout; + else + dataout_reg <= {1'b0,dataout_reg[9:1]}; + + reg [4:0] state; + reg [3:0] bit_count; + + assign new_word = (bit_count == 9); + + always @(posedge clk) + if(rst) + bit_count <= 0; + else if(new_word | send_sync) + bit_count <= 0; + else + bit_count <= bit_count + 1; + + localparam SEND_IDLE = 0; + localparam SEND_HEAD = 1; + localparam SEND_T0 = 2; + localparam SEND_T1 = 3; + localparam SEND_T2 = 4; + localparam SEND_T3 = 5; + + localparam COMMA = 8'hBC; + localparam HEAD = 8'h3C; + + reg [31:0] master_time_reg; + + always @(posedge clk) + if(rst) + master_time_reg <= 0; + else if(send_sync) + master_time_reg <= master_time; + + always @(posedge clk) + if(rst) + begin + {k,datain} <= 0; + state <= SEND_IDLE; + end + else + if(send_sync) + state <= SEND_HEAD; + else if(new_word) + case(state) + SEND_IDLE : + {k,datain} <= {1'b1,COMMA}; + SEND_HEAD : + begin + {k,datain} <= {1'b1, HEAD}; + state <= SEND_T0; + end + SEND_T0 : + begin + {k,datain} <= {1'b0, master_time_reg[31:24] }; + state <= SEND_T1; + end + SEND_T1 : + begin + {k,datain} <= {1'b0, master_time_reg[23:16]}; + state <= SEND_T2; + end + SEND_T2 : + begin + {k,datain} <= {1'b0, master_time_reg[15:8]}; + state <= SEND_T3; + end + SEND_T3 : + begin + {k,datain} <= {1'b0, master_time_reg[7:0]}; + state <= SEND_IDLE; + end + default : + state <= SEND_IDLE; + endcase // case(state) + + +endmodule // time_sender diff --git a/usrp2/timing/time_sync.v b/usrp2/timing/time_sync.v new file mode 100644 index 000000000..c0c8e195f --- /dev/null +++ b/usrp2/timing/time_sync.v @@ -0,0 +1,146 @@ + + +module time_sync + (input wb_clk_i, input rst_i, + input cyc_i, input stb_i, input [2:0] adr_i, + input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, + input sys_clk_i, output [31:0] master_time_o, + input pps_posedge, input pps_negedge, + input exp_pps_in, output exp_pps_out, + output reg int_o, + output reg epoch_o, + output reg pps_o ); + + wire [31:0] master_time_rcvd; + reg [31:0] master_time; + reg [31:0] delta_time; + + reg internal_tick; + wire sync_rcvd, pps_ext; + reg [31:0] tick_time, tick_time_wb; + wire tick_free_run; + reg tick_int_enable, tick_source, external_sync; + reg [31:0] tick_interval; + reg sync_on_next_pps; + reg sync_every_pps; + reg pps_edge; + + // Generate master time + always @(posedge sys_clk_i) + if(rst_i) + master_time <= 0; + else if(external_sync & sync_rcvd) + master_time <= master_time_rcvd + delta_time; + else if(pps_ext & (sync_on_next_pps|sync_every_pps)) + master_time <= 0; + else + master_time <= master_time + 1; + assign master_time_o = master_time; + + time_sender time_sender + (.clk(sys_clk_i),.rst(rst_i), + .master_time(master_time), + .send_sync(internal_tick), + .exp_pps_out(exp_pps_out) ); + + time_receiver time_receiver + (.clk(sys_clk_i),.rst(rst_i), + .master_time(master_time_rcvd), + .sync_rcvd(sync_rcvd), + .exp_pps_in(exp_pps_in) ); + + assign ack_o = stb_i; + wire wb_write = cyc_i & stb_i & we_i; + wire wb_read = cyc_i & stb_i & ~we_i; + wire wb_acc = cyc_i & stb_i; + + always @(posedge wb_clk_i) + if(rst_i) + begin + tick_source <= 0; + tick_int_enable <= 0; + external_sync <= 0; + tick_interval <= 100000-1; // default to 1K times per second + delta_time <= 0; + pps_edge <= 0; + sync_every_pps <= 0; + end + else if(wb_write) + case(adr_i[2:0]) + 3'd0 : + begin + tick_source <= dat_i[0]; + tick_int_enable <= dat_i[1]; + external_sync <= dat_i[2]; + pps_edge <= dat_i[3]; + sync_every_pps <= dat_i[4]; + end + 3'd1 : + tick_interval <= dat_i; + 3'd2 : + delta_time <= dat_i; + 3'd3 : + ; + // Do nothing here, this is to arm the sync_on_next + endcase // case(adr_i[2:0]) + + always @(posedge sys_clk_i) + if(rst_i) + sync_on_next_pps <= 0; + else if(pps_ext) + sync_on_next_pps <= 0; + else if(wb_write & (adr_i[2:0] == 3)) + sync_on_next_pps <= 1; + + always @(posedge sys_clk_i) + if(internal_tick) + tick_time <= master_time; + + always @(posedge wb_clk_i) + tick_time_wb <= tick_time; + + assign dat_o = tick_time_wb; + + always @(posedge sys_clk_i) + internal_tick <= (tick_source == 0) ? tick_free_run : pps_ext; + + reg [31:0] counter; + always @(posedge sys_clk_i) + if(rst_i) + counter <= 0; + else if(tick_free_run) + counter <= 0; + else + counter <= counter + 1; + assign tick_free_run = (counter >= tick_interval); + + // Properly Latch and edge detect External PPS input + reg pps_in_d1, pps_in_d2; + always @(posedge sys_clk_i) + begin + pps_in_d1 <= pps_edge ? pps_posedge : pps_negedge; + pps_in_d2 <= pps_in_d1; + end + assign pps_ext = pps_in_d1 & ~pps_in_d2; + + always @(posedge sys_clk_i) + pps_o <= pps_ext; + + // Need to register this? + reg internal_tick_d1; + always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick; + + always @(posedge wb_clk_i) + if(rst_i) + int_o <= 0; + else if(tick_int_enable & (internal_tick | internal_tick_d1)) + int_o <= 1; + else + int_o <= 0; + + always @(posedge sys_clk_i) + if(rst_i) + epoch_o <= 0; + else + epoch_o <= (master_time_o[27:0] == 0); +endmodule // time_sync diff --git a/usrp2/timing/time_transfer_tb.v b/usrp2/timing/time_transfer_tb.v new file mode 100644 index 000000000..2b75c60bd --- /dev/null +++ b/usrp2/timing/time_transfer_tb.v @@ -0,0 +1,50 @@ + +`timescale 1ns / 1ps + +module time_transfer_tb(); + + reg clk = 0, rst = 1; + always #5 clk = ~clk; + + initial + begin + @(negedge clk); + @(negedge clk); + rst <= 0; + end + + initial $dumpfile("time_transfer_tb.vcd"); + initial $dumpvars(0,time_transfer_tb); + + initial #100000000 $finish; + + wire exp_pps, pps, pps_rcv; + wire [31:0] master_clock_rcv; + reg [31:0] master_clock = 0; + reg [31:0] counter = 0; + + localparam PPS_PERIOD = 109; + always @(posedge clk) + if(counter == PPS_PERIOD) + counter <= 0; + else + counter <= counter + 1; + assign pps = (counter == (PPS_PERIOD-1)); + + always @(posedge clk) + master_clock <= master_clock + 1; + + time_sender time_sender + (.clk(clk),.rst(rst), + .master_clock(master_clock), + .pps(pps), + .exp_pps_out(exp_pps) ); + + time_receiver time_receiver + (.clk(clk),.rst(rst), + .master_clock(master_clock_rcv), + .pps(pps_rcv), + .exp_pps_in(exp_pps) ); + + wire [31:0] delta = master_clock - master_clock_rcv; +endmodule // time_transfer_tb diff --git a/usrp2/timing/timer.v b/usrp2/timing/timer.v new file mode 100644 index 000000000..70c9746be --- /dev/null +++ b/usrp2/timing/timer.v @@ -0,0 +1,40 @@ + + +module timer + (input wb_clk_i, input rst_i, + input cyc_i, input stb_i, input [2:0] adr_i, + input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, + input sys_clk_i, input [31:0] master_time_i, + output int_o ); + + reg [31:0] time_wb; + always @(posedge wb_clk_i) + time_wb <= master_time_i; + + assign ack_o = stb_i; + + reg [31:0] int_time; + reg int_reg; + + always @(posedge sys_clk_i) + if(rst_i) + begin + int_time <= 0; + int_reg <= 0; + end + else if(|int_time && (master_time_i == int_time)) + begin + int_time <= 0; + int_reg <= 1; + end + else if(stb_i & we_i) + begin + int_time <= dat_i; + int_reg <= 0; + end + + assign dat_o = time_wb; + assign int_o = int_reg; + +endmodule // timer + diff --git a/usrp2/top/.gitignore b/usrp2/top/.gitignore new file mode 100644 index 000000000..bf1b77066 --- /dev/null +++ b/usrp2/top/.gitignore @@ -0,0 +1 @@ +/*.sav diff --git a/usrp2/top/eth_test/.gitignore b/usrp2/top/eth_test/.gitignore new file mode 100644 index 000000000..b30397081 --- /dev/null +++ b/usrp2/top/eth_test/.gitignore @@ -0,0 +1,43 @@ +/xst +/_ngo +/_xmsgs +/*.stx +/*.tspec +/*.xml +/*.gyd +/*.ngr +/*.tim +/*.err +/*.lso +/*.bld +/*.cmd_log +/*.ise_ISE_Backup +/*.mfd +/*.vm6 +/*.syr +/*.xst +/*.csv +/*.html +/*.jed +/*.pad +/*.ng* +/*.pnx +/*.rpt +/*.prj +/*_html +/*_log +/*.lfp +/*.bit +/*.bin +/*.vcd +/*.unroutes +/*.drc +/*_map.* +/*_guide.* +/*.twr +/*.twx +/a.out +/*.xpi +/*_pad.txt +/*.bgn +/*.par diff --git a/usrp2/top/eth_test/eth_sim_top.v b/usrp2/top/eth_test/eth_sim_top.v new file mode 100644 index 000000000..640a4e60f --- /dev/null +++ b/usrp2/top/eth_test/eth_sim_top.v @@ -0,0 +1,437 @@ +////////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_basic +////////////////////////////////////////////////////////////////////////////////// + +module eth_sim_top + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output led1, + output led2, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + input PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] ser_debug; + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + parameter dw = 32; // Data bus width + parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i; + wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel; + wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack; + wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb; + wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc; + wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err; + wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty; + wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we; + + wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01), + .s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010), + .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty) + ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we; + wire [3:0] iram_wr_sel; + wire [aw-1:0] iram_wr_adr, iram_rd_adr; + wire [dw-1:0] iram_wr_dat, iram_rd_dat; + + wire bus_error, proc_int; + + assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0; + assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack; + + ram_loader #(.AWIDTH(16)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start), + .mode_o(cpld_mode), + .done_o(cpld_done), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr), + .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel), + .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack), + .ram_loader_done_o(ram_loader_done)); + + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr), + .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + assign proc_int = 1'b0; + + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + ram_wb_harvard #(.AWIDTH(14)) + ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat), + .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb), + .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel), + + .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel)); + + assign s0_err = 1'b0; + assign s0_rty = 1'b0; + + // Buffer Pool, slave #1 + wire rd0_read, rd0_ready, rd0_done, rd0_empty; + wire rd1_read, rd1_ready, rd1_done, rd1_empty; + wire rd2_read, rd2_ready, rd2_done, rd2_empty; + wire rd3_read, rd3_ready, rd3_done, rd3_empty; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_write, wr0_done, wr0_ready, wr0_full; + wire wr1_write, wr1_done, wr1_ready, wr1_full; + wire wr2_write, wr2_done, wr2_ready, wr2_full; + wire wr3_write, wr3_done, wr3_ready, wr3_full; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + +/* + buffer_pool buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), + + .stream_clk(dsp_clk),.stream_rst(dsp_rst), + // Write Interfaces + .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(), + .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(), + .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(), + .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(), + // Read Interfaces + .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty), + .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty), + .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty), + .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty) + ); +*/ + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i), + .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack), + + .wb_err_o(s2_err),.wb_int_o(s2_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + assign s2_rty = 1'b0; + + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(st_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_err = 1'b0; + assign s3_rty = 1'b0; + + // GPIOs -- Slave #4 + wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d; + assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d; + + simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a), + .gpio(/* io_tx[7:0]*/) ); + + simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b), + .gpio(/* io_tx[15:8] */) ); + + simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c), + .gpio(/* io_rx[7:0] */) ); + + simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d), + .gpio(/* io_rx[15:8]*/) ); + + assign s4_err = 1'b0; + assign s4_rty = 1'b0; + + // Output control lines, SLAVE #5 + wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0]; + assign {led2, led1} = misc_outs[1:0]; + + wb_output_pins32 control_lines + (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i), + .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc), + .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) ); + + assign s5_err = 1'b0; + assign s5_rty = 1'b0; + + // Ethernet slave, #6 + eth_wrapper eth_wrapper + (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(), + .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode + .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER), + .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL), + .Mdio(MDIO),.Mdc(MDC), + // FIFO Interfaces + .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(), + .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(), + // Wishbone + .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack) + ); + + assign s6_err = 1'b0; + assign s6_rty = 1'b0; + + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_err = 1'b0; + assign s7_rty = 1'b0; + assign s7_dat_i = 32'd0; + + /////////////////////////////////////////////////////////////////////////// + // DSP + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_a; + adc_a_reg2 <= adc_a_reg1; + adc_b_reg1 <= adc_b; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg1 <= adc_ovf_a; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg1 <= adc_ovf_b; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done), + .rx_ready_i(wr1_ready),.rx_full_i(wr1_full), + .overrun() ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done), + .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty), + .underrun() ); + + assign dsp_rst = wb_rst; + + ///////////////////////////////////////////////////////////////////////////////////// + // SERDES + serdes_tx serdes_tx + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done), + .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty) + ); + + serdes_rx serdes_rx + (.clk(dsp_clk),.rst(dsp_rst), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done) + ); + + // Debug Pins + wire [31:0] debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst}, + {1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached}, + {8'hAF}, + {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}}; + + wire [31:0] debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst}, + {iram_rd_adr[15:8]}, + {iram_rd_adr[7:0]}, + {serdes_outs}}; + + assign io_rx = ser_debug[31:16]; + assign io_tx = ser_debug[15:0]; + + assign debug = debug_wb; + + assign debug_clk[0] = wb_clk; + assign debug_clk[1] = dsp_clk; + +endmodule // eth_test + + +// Local Variables: +// verilog-library-directories:("." "subdir" "subdir2") +// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v") +// verilog-library-extensions:(".v" ".h") +// End: diff --git a/usrp2/top/eth_test/eth_tb.v b/usrp2/top/eth_test/eth_tb.v new file mode 100644 index 000000000..451ce1e7e --- /dev/null +++ b/usrp2/top/eth_test/eth_tb.v @@ -0,0 +1,257 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +// Nearly everything is an input + +module eth_tb(); + // Misc, debug + wire led1; + wire led2; + wire [31:0] debug; + wire [1:0] debug_clk; + + // Expansion + wire exp_pps_in; + wire exp_pps_out; + + // GMII + // GMII-CTRL + wire GMII_COL; + wire GMII_CRS; + + // GMII-TX + wire [7:0] GMII_TXD; + wire GMII_TX_EN; + wire GMII_TX_ER; + wire GMII_GTX_CLK; + wire GMII_TX_CLK; // 100mbps clk + + // GMII-RX + wire [7:0] GMII_RXD; + wire GMII_RX_CLK; + wire GMII_RX_DV; + wire GMII_RX_ER; + + // GMII-Management + wire MDIO; + wire MDC; + wire PHY_INTn; // open drain + wire PHY_RESETn; + wire PHY_CLK; // possibly use on-board osc + + // RAM + wire [17:0] RAM_D; + wire [18:0] RAM_A; + wire RAM_CE1n; + wire RAM_CENn; + wire RAM_CLK; + wire RAM_WEn; + wire RAM_OEn; + wire RAM_LDn; + + // SERDES + wire ser_enable; + wire ser_prbsen; + wire ser_loopen; + wire ser_rx_en; + + wire ser_tx_clk; + wire [15:0] ser_t; + wire ser_tklsb; + wire ser_tkmsb; + + wire ser_rx_clk; + wire [15:0] ser_r; + wire ser_rklsb; + wire ser_rkmsb; + + // CPLD interface + wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; + + // ADC + wire [13:0] adc_a; + wire adc_ovf_a; + wire adc_oen_a; + wire adc_pdn_a; + + wire [13:0] adc_b; + wire adc_ovf_b; + wire adc_oen_b; + wire adc_pdn_b; + + // DAC + wire [15:0] dac_a; + wire [15:0] dac_b; + + // I2C + wire SCL; + wire SDA; + + // Clock Gen Control + wire [1:0] clk_en; + wire [1:0] clk_sel; + wire clk_func; // FIXME is an input to control the 9510 + wire clk_status; + + // Clocks + reg clk_fpga; + wire clk_to_mac; + wire pps_in; + + // Generic SPI + wire sclk, mosi, miso; + wire sen_clk; + wire sen_dac; + wire sen_tx_db; + wire sen_tx_adc; + wire sen_tx_dac; + wire sen_rx_db; + wire sen_rx_adc; + wire sen_rx_dac; + + // GPIO to DBoards + wire [15:0] io_tx; + wire [15:0] io_rx; + + wire wb_clk, wb_rst; + wire start, clock_ready; + + reg aux_clk; + + initial aux_clk= 1'b0; + always #25 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #7 clk_fpga = ~clk_fpga; + + + wire div_clk; + reg [2:0] div_ctr = 0; + + always @(posedge clk_fpga or negedge clk_fpga) + if(div_ctr==5) + div_ctr = 0; + else + div_ctr = div_ctr + 1; + assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2); + + assign dsp_clk = clk_fpga; + assign wb_clk = clock_ready ? div_clk : aux_clk; + + initial + $monitor($time, ,clock_ready); + + initial begin + $dumpfile("eth_tb.vcd"); + $dumpvars(0,eth_tb); + end + + initial #10000000 $finish; + + cpld_model + cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), + .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); + + eth_sim_top eth_sim_top(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .led1 (led1), + .led2 (led2), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD[7:0]), + .GMII_TX_EN (GMII_TX_EN), + .GMII_TX_ER (GMII_TX_ER), + .GMII_GTX_CLK (GMII_GTX_CLK), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .PHY_CLK (PHY_CLK), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk), + .ser_t (ser_t[15:0]), + .ser_tklsb (ser_tklsb), + .ser_tkmsb (ser_tkmsb), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r[15:0]), + .ser_rklsb (ser_rklsb), + .ser_rkmsb (ser_rkmsb), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_oen_a (adc_oen_a), + .adc_pdn_a (adc_pdn_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_oen_b (adc_oen_b), + .adc_pdn_b (adc_pdn_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0])); + + // Experimental printf-like function + always @(posedge wb_clk) + begin + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000)) + $write("%x",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100)) + $display("%x",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004)) + $write("%c",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104)) + $display("%c",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008)) + $display(""); + end + + +endmodule // u2_sim_top + +// Local Variables: +// verilog-library-directories:("." "subdir" "subdir2") +// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v") +// verilog-library-extensions:(".v" ".h") +// End: diff --git a/usrp2/top/single_u2_sim/single_u2_sim.v b/usrp2/top/single_u2_sim/single_u2_sim.v new file mode 100644 index 000000000..2a7b24849 --- /dev/null +++ b/usrp2/top/single_u2_sim/single_u2_sim.v @@ -0,0 +1,324 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module single_u2_sim(); + // Misc, debug + wire [7:0] leds; + wire [31:0] debug; + wire [1:0] debug_clk; + + // Expansion + wire exp_pps_in; + wire exp_pps_out; + + // GMII + // GMII-CTRL + wire GMII_COL; + wire GMII_CRS; + + // GMII-TX + wire [7:0] GMII_TXD; + wire GMII_TX_EN; + wire GMII_TX_ER; + wire GMII_GTX_CLK; + wire GMII_TX_CLK; // 100mbps clk + + // GMII-RX + wire [7:0] GMII_RXD; + wire GMII_RX_CLK; + wire GMII_RX_DV; + wire GMII_RX_ER; + + // GMII-Management + wire MDIO; + wire MDC; + wire PHY_INTn; // open drain + wire PHY_RESETn; + wire PHY_CLK; // possibly use on-board osc + + // RAM + wire [17:0] RAM_D; + wire [18:0] RAM_A; + wire RAM_CE1n; + wire RAM_CENn; + wire RAM_CLK; + wire RAM_WEn; + wire RAM_OEn; + wire RAM_LDn; + + // SERDES + wire ser_enable; + wire ser_prbsen; + wire ser_loopen; + wire ser_rx_en; + + wire ser_tx_clk; + wire [15:0] ser_t; + wire ser_tklsb; + wire ser_tkmsb; + + wire ser_rx_clk; + wire [15:0] ser_r; + wire ser_rklsb; + wire ser_rkmsb; + + // CPLD interface + wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; + + // ADC + wire [13:0] adc_a; + wire adc_ovf_a; + wire adc_on_a, adc_oe_a; + + wire [13:0] adc_b; + wire adc_ovf_b; + wire adc_on_b, adc_oe_b; + + // DAC + wire [15:0] dac_a; + wire [15:0] dac_b; + + // I2C + wire SCL; + wire SDA; + + // Clock Gen Control + wire [1:0] clk_en; + wire [1:0] clk_sel; + wire clk_func; // FIXME is an input to control the 9510 + wire clk_status; + + // Clocks + reg clk_fpga; + reg clk_to_mac; + wire pps_in; + + // Generic SPI + wire sclk, mosi, miso; + wire sen_clk; + wire sen_dac; + wire sen_tx_db; + wire sen_tx_adc; + wire sen_tx_dac; + wire sen_rx_db; + wire sen_rx_adc; + wire sen_rx_dac; + + // GPIO to DBoards + wire [15:0] io_tx; + wire [15:0] io_rx; + + wire wb_clk; + wire start, clock_ready; + + reg aux_clk; + + initial aux_clk= 1'b0; + always #6 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #5 clk_fpga = ~clk_fpga; + + initial clk_to_mac = 0; + always #4 clk_to_mac = ~clk_to_mac; + + wire div_clk, dsp_clk; + reg [7:0] div_ctr = 0; + + assign dsp_clk = clock_ready ? clk_fpga : aux_clk; + assign wb_clk = div_clk; + +`define CLK_DIV_2 1 +//`define CLK_DIV_3 + +`ifdef CLK_DIV_2 + localparam clock_divider = 4'd2; + always @(posedge dsp_clk) + div_ctr <= div_ctr + 1; + assign div_clk = div_ctr[0]; +`endif + +`ifdef CLK_DIV_3 + localparam clock_divider = 2; + always @(posedge dsp_clk or negedge dsp_clk) + if(div_ctr == 5) + div_ctr <= 0; + else + div_ctr <= div_ctr + 1; + assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); +`endif + + initial + $monitor($time, ,clock_ready); + + always #1000000 $monitor("Time in ns ",$time); + + initial begin + @(negedge cpld_done); + @(posedge cpld_done); + $dumpfile("single_u2_sim.lxt"); + $dumpvars(0,single_u2_sim); + end + + initial #10000000 $finish; + + cpld_model + cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), + .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); + + serdes_model serdes_model + (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), + .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), + .even(0),.error(0) ); + + adc_model adc_model + (.clk(dsp_clk),.rst(0), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), + .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); + + wire [2:0] speed; + phy_sim phy_model + (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), + .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), + .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), + .Crs(GMII_CRS), .Col(GMII_COL), + .Speed(speed), .Done(0) ); + pullup p3(MDIO); + + miim_model miim_model + (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), + .phy_intn_o(PHY_INTn),.speed_o(speed) ); + + xlnx_glbl glbl (.GSR(),.GTS()); + + wire RAM_MODE = 1'b0; + cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), + .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), + .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), + .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); + + M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), + .SDA(SDA),.SCL(SCL),.RESET(0)); + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o; + wire sda_pad_i, sda_pad_o, sda_pad_oen_o; + + pullup p1(SCL); + pullup p2(SDA); + + assign scl_pad_i = SCL; + assign sda_pad_i = SDA; + + assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; + assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; + + // printf output + wire uart_baud_o, uart_tx_o, uart_rx_i; + assign uart_rx_i = 1'b1; + + uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); + + // End the simulation + always @(posedge wb_clk) + if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) + begin + $display($time, "Finish called.",); + $finish; + end + + u2_core #(.RAM_SIZE(32768)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD[7:0]), + .GMII_TX_EN (GMII_TX_EN), + .GMII_TX_ER (GMII_TX_ER), + .GMII_GTX_CLK (GMII_GTX_CLK), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk), + .ser_t (ser_t[15:0]), + .ser_tklsb (ser_tklsb), + .ser_tkmsb (ser_tkmsb), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r[15:0]), + .ser_rklsb (ser_rklsb), + .ser_rkmsb (ser_rkmsb), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_init_b (1), + .por (0), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (uart_baud_o), + .sim_mode (1'b1), + .clock_divider (clock_divider) + ); + +endmodule // single_u2_sim diff --git a/usrp2/top/tcl/ise_helper.tcl b/usrp2/top/tcl/ise_helper.tcl new file mode 100644 index 000000000..fe9db87af --- /dev/null +++ b/usrp2/top/tcl/ise_helper.tcl @@ -0,0 +1,89 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +proc set_props {process options} { + if ![string compare $options ""] { + return + } + set state 1 + foreach opt $options { + if $state { + set key $opt + set state 0 + } else { + puts ">>> Setting: $process\[$key\] = $opt" + if ![string compare $process "Project"] { + project set $key $opt + } else { + project set $key $opt -process $process + } + set state 1 + } + } +} + +if [file isfile $env(PROJ_FILE)] { + puts ">>> Opening project: $env(PROJ_FILE)" + project open $env(PROJ_FILE) +} else { + puts ">>> Creating project: $env(PROJ_FILE)" + project new $env(PROJ_FILE) + + ################################################## + # Set the project properties + ################################################## + set_props "Project" $env(PROJECT_PROPERTIES) + + ################################################## + # Add the sources + ################################################## + foreach source $env(SOURCES) { + set source $env(SOURCE_ROOT)$source + puts ">>> Adding source to project: $source" + xfile add $source + } + + ################################################## + # Set the top level module + ################################################## + project set top $env(TOP_MODULE) + + ################################################## + # Set the process properties + ################################################## + set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES) + set_props "Translate" $env(TRANSLATE_PROPERTIES) + set_props "Map" $env(MAP_PROPERTIES) + set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES) + set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES) + set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES) + set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES) +} + +if [string compare $env(PROCESS_RUN) ""] { + puts ">>> Running Process: $env(PROCESS_RUN)" + process run $env(PROCESS_RUN) +} + +project close +exit + + diff --git a/usrp2/top/u2_core/.gitignore b/usrp2/top/u2_core/.gitignore new file mode 100644 index 000000000..9728395c1 --- /dev/null +++ b/usrp2/top/u2_core/.gitignore @@ -0,0 +1,44 @@ +*~ +/xst +/_ngo +/_xmsgs +/*.stx +/*.tspec +/*.xml +/*.gyd +/*.ngr +/*.tim +/*.err +/*.lso +/*.bld +/*.cmd_log +/*.ise_ISE_Backup +/*.mfd +/*.vm6 +/*.syr +/*.xst +/*.csv +/*.html +/*.jed +/*.pad +/*.ng* +/*.pnx +/*.rpt +/*.prj +/*_html +/*_log +/*.lfp +/*.bit +/*.bin +/*.vcd +/*.unroutes +/*.drc +/*_map.* +/*_guide.* +/*.twr +/*.twx +/a.out +/*.xpi +/*_pad.txt +/*.bgn +/*.par diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v new file mode 100755 index 000000000..fd17a10a7 --- /dev/null +++ b/usrp2/top/u2_core/u2_core.v @@ -0,0 +1,761 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + #(parameter RAM_SIZE=32768) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), + // Read Interfaces + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + ); + + wire [31:0] status_enc; + priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), + .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {clk_status,serdes_link_up}; + + setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {8'b0}, + {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; + always @(negedge dsp_clk) pps_negedge <= pps_in; + always @(posedge dsp_clk) pps_posedge <= pps_in; + always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; + always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; + + wire pps_o; + time_sync time_sync + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), + .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), + .sys_clk_i(dsp_clk),.master_time_o(master_time), + .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), + .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), + .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + sd_spi_wb sd_spi_wb + (.clk(wb_clk),.rst(wb_rst), + .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), + .wb_ack_o(sd_ack) ); + + assign sd_dat_i[31:8] = 0; + + // ///////////////////////////////////////////////////////////////////////// + // DSP + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + + rx_control #(.FIFOSIZE(10)) rx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.overrun(overrun), + .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), + .debug_rx(debug_rx) ); + + // dummy_rx dsp_core_rx + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + tx_control #(.FIFOSIZE(10)) tx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.underrun(underrun), + .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), + .debug(debug_txc) ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // External RAM Interface + + localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes + + wire [15:0] bus2ram, ram2bus; + wire [15:0] bridge_adr; + wire [1:0] bridge_sel; + wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; + + wire [19:0] page; + wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; + setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(page),.changed()); + + wb_bridge_16_32 bridge + (.wb_clk(wb_clk),.wb_rst(wb_rst), + .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), + .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), + .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), + .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); + + wb_zbt16_b wb_zbt16_b + (.clk(wb_clk),.rst(wb_rst), + .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), + .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), + .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), + .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), + .sram_mode(),.sram_zz() ); + + assign RAM_CE1n = 0; + assign RAM_D[17:16] = 2'bzz; + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // FIFO Level Debugging + reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; + + always @(posedge dsp_clk) + serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, + {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; + + assign debug_clk[0] = 0; // wb_clk; + assign debug_clk[1] = clk_to_mac; +/* + + wire mdio_cpy = MDIO; + assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, + { s6_adr[15:8] }, + { s6_adr[7:0] }, + { 6'd0, mdio_cpy, MDC } }; +*/ +/* + assign debug = { { GMII_TXD }, + { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, + { wr2_flags, rd2_flags }, + { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + */ + assign debug = { { GMII_RXD }, + { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { wr2_flags, rd2_flags }, + { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + + assign debug_gpio_0 = debug_mac; //eth_mac_debug; + assign debug_gpio_1 = 0; + +endmodule // u2_core + +// wire debug_mux; +// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), +// .in(set_data),.out(debug_mux),.changed()); + +//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; +//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; + +//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, +// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; + +//assign debug = debug_tx_dsp; +//assign debug = debug_serdes0; + +//assign debug_gpio_0 = 0; //debug_serdes0; +//assign debug_gpio_1 = 0; //debug_serdes1; + +// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, +// {8'b0}, +// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, +// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; + +//assign debug = {dac_a,dac_b}; + +/* + assign debug = {{ram_loader_done, takeover, 6'd0}, + {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, + {8'd0}, + {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ + +/*assign debug = host_to_dsp_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; + */ +// Assign various commonly used debug buses. +/* + wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, + irq[7:0], + GMII_RXD, + GMII_TXD}; + + wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; + + wire [31:0] debug_time = {uart_tx_o, 7'b0, + irq[7:0], + 6'b0, GMII_RX_DV, GMII_TX_EN, + 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; + + wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, + irq[7:0], + proc_int, 7'b0 }; + + wire [31:0] debug_eth = + {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, + {8'd0}, + {8'd0}, + {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; + + assign debug_serdes0 = { { rd0_dat[7:0] }, + { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, + { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, + { ser_r[15:8] }, + { ser_r[7:0] } }; + + assign debug_gpio_1 = {uart_tx_o,7'd0, + 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, + debug_txc[15:0]}; + assign debug_gpio_1 = debug_rx; + assign debug_gpio_1 = debug_serdes1; + assign debug_gpio_1 = debug_eth; + + */ + diff --git a/usrp2/top/u2_rev1/.gitignore b/usrp2/top/u2_rev1/.gitignore new file mode 100644 index 000000000..de5b50277 --- /dev/null +++ b/usrp2/top/u2_rev1/.gitignore @@ -0,0 +1,52 @@ +/templates +/netgen +/_ngo +/_xmsgs +/_pace.ucf +/*.cmd +/*.ibs +/*.lfp +/*.mfp +/*.bit +/*.bin +/*.stx +/*.par +/*.unroutes +/*.ntrc_log +/*.ngr +/*.mrp +/*.html +/*.lso +/*.twr +/*.bld +/*.ncd +/*.txt +/*.cmd_log +/*.drc +/*.map +/*.twr +/*.xml +/*.syr +/*.ngm +/*.xst +/*.csv +/*.html +/*.lock +/*.ncd +/*.twx +/*.ise_ISE_Backup +/*.xml +/*.ut +/*.xpi +/*.ngd +/*.ncd +/*.pad +/*.bgn +/*.ngc +/*.pcf +/*.ngd +/xst +/*.log +/*.rpt +/*.cel +/*.restore diff --git a/usrp2/top/u2_rev1/Makefile b/usrp2/top/u2_rev1/Makefile new file mode 100644 index 000000000..b3245d883 --- /dev/null +++ b/usrp2/top/u2_rev1/Makefile @@ -0,0 +1,129 @@ +FILENAME=u2_fpga_top +PARTNUM=xc3s1500-5fg456 + +all: project command xst ngd ncd ncd2 bit + +xst: + xst -ifn ${FILENAME}.cmd -ofn xst.log + +ngd: + ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME} + +ncd: + rm -rf ${FILENAME}.ncd + map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf + +# Place and route ncd file into new ncd file +ncd2: + par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf + +bit: + bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit + +clean: + @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \ + *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \ + *.blc *.bld *.ise_ISE_Backup *~ \ + *.pad *.ngm *.ngd *.par *.pcf *.unroutes \ + *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \ + *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \ + output.dat coregen.log *.ngo *.log ${FILENAME}.map \ + ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr + +command: + rm -rf ${FILENAME}.cmd + @echo "identification" >> ${FILENAME}.cmd + @echo "status" >> ${FILENAME}.cmd + @echo "time short" >> ${FILENAME}.cmd + @echo "memory on" >> ${FILENAME}.cmd + @echo "run " >> ${FILENAME}.cmd + @echo "-top ${FILENAME}" >> ${FILENAME}.cmd + @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd + @echo "-ifmt Verilog " >> ${FILENAME}.cmd + @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd + @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd + @echo "-bufg 6" >> ${FILENAME}.cmd + @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd + +project: + rm -f ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/TECH/duram.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/sign_extend.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cordic_stage.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cic_int_shifter.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cic_dec_shifter.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/Reg_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/ram_2port.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cordic.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cic_interp.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cic_decim.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/eth_miim.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/RMON.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/Phy_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/strobe_gen.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/ss_rcvr.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/shortfifo.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/setting_reg.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/mux8.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/mux4.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/longfifo.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/decoder_3_8.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/buffer_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/CRC16_D16.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/tx_control.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/rx_control.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/dsp_core_tx.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/dsp_core_rx.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_top.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/mac_txfifo_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/mac_rxfifo_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/wb_readback_mux.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/wb_1master.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/timer.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/system_control.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/settings_bus.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/serdes_tx.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/serdes_rx.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/ram_wb_harvard.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/ram_loader.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/nsgpio.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/buffer_pool.v" ' >> ${FILENAME}.prj + @echo '`include "../u2_basic/u2_basic.v" ' >> ${FILENAME}.prj + @echo '`include "u2_fpga_top.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/elastic_buffer.v" ' >> ${FILENAME}.prj diff --git a/usrp2/top/u2_rev1/u2_fpga.ise b/usrp2/top/u2_rev1/u2_fpga.ise new file mode 100644 index 000000000..f90caf024 Binary files /dev/null and b/usrp2/top/u2_rev1/u2_fpga.ise differ diff --git a/usrp2/top/u2_rev1/u2_fpga.ucf b/usrp2/top/u2_rev1/u2_fpga.ucf new file mode 100755 index 000000000..5d2124819 --- /dev/null +++ b/usrp2/top/u2_rev1/u2_fpga.ucf @@ -0,0 +1,341 @@ +NET "adc_a[0]" LOC = "A14" ; +NET "adc_a[10]" LOC = "D20" ; +NET "adc_a[11]" LOC = "D19" ; +NET "adc_a[12]" LOC = "D21" ; +NET "adc_a[13]" LOC = "E18" ; +NET "adc_a[1]" LOC = "B14" ; +NET "adc_a[2]" LOC = "C13" ; +NET "adc_a[3]" LOC = "D13" ; +NET "adc_a[4]" LOC = "A13" ; +NET "adc_a[5]" LOC = "B13" ; +NET "adc_a[6]" LOC = "E12" ; +NET "adc_a[7]" LOC = "C22" ; +NET "adc_a[8]" LOC = "C20" ; +NET "adc_a[9]" LOC = "C21" ; +NET "adc_b[0]" LOC = "A12" ; +NET "adc_b[10]" LOC = "D18" ; +NET "adc_b[11]" LOC = "B18" ; +NET "adc_b[12]" LOC = "D17" ; +NET "adc_b[13]" LOC = "E17" ; +NET "adc_b[1]" LOC = "E16" ; +NET "adc_b[2]" LOC = "F12" ; +NET "adc_b[3]" LOC = "F13" ; +NET "adc_b[4]" LOC = "F16" ; +NET "adc_b[5]" LOC = "F17" ; +NET "adc_b[6]" LOC = "C19" ; +NET "adc_b[7]" LOC = "B20" ; +NET "adc_b[8]" LOC = "B19" ; +NET "adc_b[9]" LOC = "C18" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_TXD[0]" LOC = "W14" ; +NET "GMII_TXD[1]" LOC = "AA20" ; +NET "GMII_TXD[2]" LOC = "AB20" ; +NET "GMII_TXD[3]" LOC = "Y18" ; +NET "GMII_TXD[4]" LOC = "AA18" ; +NET "GMII_TXD[5]" LOC = "AB18" ; +NET "GMII_TXD[6]" LOC = "V17" ; +NET "GMII_TXD[7]" LOC = "W17" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "RAM_A[0]" LOC = "N22" ; +NET "RAM_A[10]" LOC = "P18" ; +NET "RAM_A[11]" LOC = "R19" ; +NET "RAM_A[12]" LOC = "P19" ; +NET "RAM_A[13]" LOC = "R21" ; +NET "RAM_A[14]" LOC = "R22" ; +NET "RAM_A[15]" LOC = "T19" ; +NET "RAM_A[16]" LOC = "T20" ; +NET "RAM_A[17]" LOC = "U20" ; +NET "RAM_A[18]" LOC = "W19" ; +NET "RAM_A[1]" LOC = "N20" ; +NET "RAM_A[2]" LOC = "T21" ; +NET "RAM_A[3]" LOC = "M22" ; +NET "RAM_A[4]" LOC = "N19" ; +NET "RAM_A[5]" LOC = "N17" ; +NET "RAM_A[6]" LOC = "N18" ; +NET "RAM_A[7]" LOC = "P21" ; +NET "RAM_A[8]" LOC = "P22" ; +NET "RAM_A[9]" LOC = "P17" ; +NET "RAM_D[0]" LOC = "Y21" ; +NET "RAM_D[10]" LOC = "V22" ; +NET "RAM_D[11]" LOC = "V21" ; +NET "RAM_D[12]" LOC = "T17" ; +NET "RAM_D[13]" LOC = "U18" ; +NET "RAM_D[14]" LOC = "U21" ; +NET "RAM_D[15]" LOC = "R18" ; +NET "RAM_D[16]" LOC = "T18" ; +NET "RAM_D[17]" LOC = "T22" ; +NET "RAM_D[1]" LOC = "Y20" ; +NET "RAM_D[2]" LOC = "Y19" ; +NET "RAM_D[3]" LOC = "W22" ; +NET "RAM_D[4]" LOC = "Y22" ; +NET "RAM_D[5]" LOC = "V19" ; +NET "RAM_D[6]" LOC = "W21" ; +NET "RAM_D[7]" LOC = "W20" ; +NET "RAM_D[8]" LOC = "U19" ; +NET "RAM_D[9]" LOC = "V20" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_t[0]" LOC = "V7" ; +NET "ser_t[10]" LOC = "AA6" ; +NET "ser_t[11]" LOC = "Y6" ; +NET "ser_t[12]" LOC = "W8" ; +NET "ser_t[13]" LOC = "V8" ; +NET "ser_t[14]" LOC = "AB8" ; +NET "ser_t[15]" LOC = "AA8" ; +NET "ser_t[1]" LOC = "V10" ; +NET "ser_t[2]" LOC = "AB4" ; +NET "ser_t[3]" LOC = "AA4" ; +NET "ser_t[4]" LOC = "Y5" ; +NET "ser_t[5]" LOC = "W5" ; +NET "ser_t[6]" LOC = "AB5" ; +NET "ser_t[7]" LOC = "AA5" ; +NET "ser_t[8]" LOC = "W6" ; +NET "ser_t[9]" LOC = "V6" ; +NET "clk_muxed" TNM_NET = "clk_muxed"; +TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %; +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; +#PACE: Start of Constraints generated by PACE + +#PACE: Start of PACE I/O Pin Assignments +NET "adc_oen_a" LOC = "E19" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_start" LOC = "AA9" ; +NET "exp_pps_in_n" LOC = "V4" ; +NET "exp_pps_in_p" LOC = "V3" ; +NET "exp_pps_out_n" LOC = "V2" ; +NET "exp_pps_out_p" LOC = "V1" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_GTX_CLK" LOC = "AA17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_RX_CLK" LOC = "W16" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_TX_EN" LOC = "Y17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "led1" LOC = "V11" ; +NET "led2" LOC = "Y12" ; +NET "MDC" LOC = "V18" ; +NET "MDIO" LOC = "Y16" | PULLUP ; +NET "PHY_CLK" LOC = "V15" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "pps_in" LOC = "Y11" ; +NET "RAM_CE1n" LOC = "N21" ; +NET "RAM_CENn" LOC = "M18" ; +NET "RAM_CLK" LOC = "M17" ; +NET "RAM_LDn" LOC = "M21" ; +NET "RAM_OEn" LOC = "M19" ; +NET "RAM_WEn" LOC = "M20" ; +NET "SCL" LOC = "A7" ; +NET "SCL_force" LOC = "E8" ; +NET "sclk" LOC = "K5" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "SDA" LOC = "D8" ; +NET "SDA_force" LOC = "C11" ; +NET "sdi" LOC = "J1" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sdo" LOC = "J2" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sen_tx_db" LOC = "C1" ; +NET "ser_enable" LOC = "W11" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tklsb" LOC = "U10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_tx_clk" LOC = "U7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<8>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<9>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<10>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<11>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<12>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<13>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<14>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<15>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +#PACE: Start of PACE Area Constraints + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE diff --git a/usrp2/top/u2_rev1/u2_fpga_top.prj b/usrp2/top/u2_rev1/u2_fpga_top.prj new file mode 100644 index 000000000..544415f4d --- /dev/null +++ b/usrp2/top/u2_rev1/u2_fpga_top.prj @@ -0,0 +1,102 @@ +verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v" +verilog work "../../control_lib/ram_2port.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v" +verilog work "../../coregen/fifo_generator_v4_1.v" +verilog work "../../control_lib/shortfifo.v" +verilog work "../../control_lib/longfifo.v" +verilog work "../../sdr_lib/sign_extend.v" +verilog work "../../sdr_lib/cordic_stage.v" +verilog work "../../sdr_lib/cic_int_shifter.v" +verilog work "../../sdr_lib/cic_dec_shifter.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v" +verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v" +verilog work "../../opencores/8b10b/encode_8b10b.v" +verilog work "../../opencores/8b10b/decode_8b10b.v" +verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v" +verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v" +verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v" +verilog work "../../eth/rtl/verilog/Reg_int.v" +verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v" +verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" +verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v" +verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" +verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" +verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" +verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" +verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" +verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" +verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" +verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" +verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" +verilog work "../../control_lib/ss_rcvr.v" +verilog work "../../control_lib/cascadefifo2.v" +verilog work "../../control_lib/CRC16_D16.v" +verilog work "../../timing/time_sender.v" +verilog work "../../timing/time_receiver.v" +verilog work "../../serdes/serdes_tx.v" +verilog work "../../serdes/serdes_rx.v" +verilog work "../../serdes/serdes_fc_tx.v" +verilog work "../../serdes/serdes_fc_rx.v" +verilog work "../../sdr_lib/round.v" +verilog work "../../sdr_lib/cordic.v" +verilog work "../../sdr_lib/cic_interp.v" +verilog work "../../sdr_lib/cic_decim.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v" +verilog work "../../opencores/spi/rtl/verilog/spi_shift.v" +verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v" +verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v" +verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v" +verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v" +verilog work "../../eth/rtl/verilog/eth_miim.v" +verilog work "../../eth/rtl/verilog/RMON.v" +verilog work "../../eth/rtl/verilog/Phy_int.v" +verilog work "../../eth/rtl/verilog/MAC_tx.v" +verilog work "../../eth/rtl/verilog/MAC_rx.v" +verilog work "../../eth/rtl/verilog/Clk_ctrl.v" +verilog work "../../control_lib/strobe_gen.v" +verilog work "../../control_lib/setting_reg.v" +verilog work "../../control_lib/mux8.v" +verilog work "../../control_lib/mux4.v" +verilog work "../../control_lib/icache.v" +verilog work "../../control_lib/dpram32.v" +verilog work "../../control_lib/decoder_3_8.v" +verilog work "../../control_lib/dcache.v" +verilog work "../../control_lib/buffer_int.v" +verilog work "../../timing/timer.v" +verilog work "../../timing/time_sync.v" +verilog work "../../serdes/serdes.v" +verilog work "../../sdr_lib/tx_control.v" +verilog work "../../sdr_lib/rx_control.v" +verilog work "../../sdr_lib/dsp_core_tx.v" +verilog work "../../sdr_lib/dsp_core_rx.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v" +verilog work "../../opencores/spi/rtl/verilog/spi_top.v" +verilog work "../../opencores/simple_pic/rtl/simple_pic.v" +verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" +verilog work "../../eth/rtl/verilog/MAC_top.v" +verilog work "../../eth/mac_txfifo_int.v" +verilog work "../../eth/mac_rxfifo_int.v" +verilog work "../../control_lib/wb_readback_mux.v" +verilog work "../../control_lib/wb_1master.v" +verilog work "../../control_lib/system_control.v" +verilog work "../../control_lib/settings_bus.v" +verilog work "../../control_lib/ram_loader.v" +verilog work "../../control_lib/ram_harv_cache.v" +verilog work "../../control_lib/nsgpio.v" +verilog work "../../control_lib/extram_interface.v" +verilog work "../../control_lib/buffer_pool.v" +verilog work "../../control_lib/atr_controller.v" +verilog work "../u2_basic/u2_basic.v" +verilog work "u2_fpga_top.v" diff --git a/usrp2/top/u2_rev1/u2_fpga_top.v b/usrp2/top/u2_rev1/u2_fpga_top.v new file mode 100644 index 000000000..63798a0c8 --- /dev/null +++ b/usrp2/top/u2_rev1/u2_fpga_top.v @@ -0,0 +1,393 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_fpga_top + ( + // Misc, debug + output led1, + output led2, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + inout SCL, + inout SDA, + input SCL_force, + input SDA_force, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + // FPGA-specific pins connections + wire aux_clk = PHY_CLK; + //wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire + wire cpld_detached = SDA_force; // FIXME Hacked on with Blue Wire + + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge aux_clk) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + wire clk_muxed = clock_ready ? clk_fpga : aux_clk; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_muxed), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire led1_int, led2_int; + assign led1 = ~led1_int; + assign led2 = ~led2_int; + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_basic u2_basic(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .led1 (led1_int), + .led2 (led2_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .PHY_CLK (PHY_CLK), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (), + .uart_rx_i (), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_fpga_top diff --git a/usrp2/top/u2_rev2/.gitignore b/usrp2/top/u2_rev2/.gitignore new file mode 100644 index 000000000..432f8fd58 --- /dev/null +++ b/usrp2/top/u2_rev2/.gitignore @@ -0,0 +1,57 @@ +/*.ptwx +/*.xrpt +/*.zip +/*_xdb +/templates +/netgen +/_ngo +/_xmsgs +/_pace.ucf +/*.cmd +/*.ibs +/*.lfp +/*.mfp +/*.bit +/*.bin +/*.stx +/*.par +/*.unroutes +/*.ntrc_log +/*.ngr +/*.mrp +/*.html +/*.lso +/*.twr +/*.bld +/*.ncd +/*.txt +/*.cmd_log +/*.drc +/*.map +/*.twr +/*.xml +/*.syr +/*.ngm +/*.xst +/*.csv +/*.html +/*.lock +/*.ncd +/*.twx +/*.ise_ISE_Backup +/*.xml +/*.ut +/*.xpi +/*.ngd +/*.ncd +/*.pad +/*.bgn +/*.ngc +/*.pcf +/*.ngd +/xst +/*.log +/*.rpt +/*.cel +/*.restore +/build diff --git a/usrp2/top/u2_rev2/Makefile b/usrp2/top/u2_rev2/Makefile new file mode 100644 index 000000000..275c24b02 --- /dev/null +++ b/usrp2/top/u2_rev2/Makefile @@ -0,0 +1,248 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2_rev2 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/buffer_int.v \ +control_lib/buffer_pool.v \ +control_lib/cascadefifo2.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/fifo_2clock.v \ +control_lib/fifo_2clock_casc.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/longfifo.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +eth/mac_rxfifo_int.v \ +eth/mac_txfifo_int.v \ +eth/rtl/verilog/Clk_ctrl.v \ +eth/rtl/verilog/MAC_rx.v \ +eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ +eth/rtl/verilog/MAC_rx/CRC_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ +eth/rtl/verilog/MAC_top.v \ +eth/rtl/verilog/MAC_tx.v \ +eth/rtl/verilog/MAC_tx/CRC_gen.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ +eth/rtl/verilog/MAC_tx/Random_gen.v \ +eth/rtl/verilog/Phy_int.v \ +eth/rtl/verilog/RMON.v \ +eth/rtl/verilog/RMON/RMON_addr_gen.v \ +eth/rtl/verilog/RMON/RMON_ctrl.v \ +eth/rtl/verilog/Reg_int.v \ +eth/rtl/verilog/eth_miim.v \ +eth/rtl/verilog/flow_ctrl_rx.v \ +eth/rtl/verilog/flow_ctrl_tx.v \ +eth/rtl/verilog/miim/eth_clockgen.v \ +eth/rtl/verilog/miim/eth_outputcontrol.v \ +eth/rtl/verilog/miim/eth_shiftreg.v \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2_rev2/u2_rev2.ucf \ +top/u2_rev2/u2_rev2.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u2_rev2/u2_rev2.ucf b/usrp2/top/u2_rev2/u2_rev2.ucf new file mode 100644 index 000000000..e18dc6f17 --- /dev/null +++ b/usrp2/top/u2_rev2/u2_rev2.ucf @@ -0,0 +1,337 @@ +NET "leds[0]" LOC = "F7" ; +NET "leds[1]" LOC = "E5" ; +NET "leds[2]" LOC = "B7" ; +NET "leds[3]" LOC = "C11" ; +NET "leds[4]" LOC = "AB19" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "uart_tx_o" LOC = "C7" ; +NET "uart_rx_i" LOC = "A3" ; +NET "exp_pps_in_p" LOC = "V3" ; +NET "exp_pps_in_n" LOC = "V4" ; +NET "exp_pps_out_p" LOC = "V1" ; +NET "exp_pps_out_n" LOC = "V2" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_RX_CLK" LOC = "W16" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "MDIO" LOC = "Y16" |PULLUP ; +NET "MDC" LOC = "V18" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "PHY_CLK" LOC = "V15" ; +NET "RAM_D[0]" LOC = "N20" ; +NET "RAM_D[1]" LOC = "N21" ; +NET "RAM_D[2]" LOC = "N22" ; +NET "RAM_D[3]" LOC = "M17" ; +NET "RAM_D[4]" LOC = "M18" ; +NET "RAM_D[5]" LOC = "M19" ; +NET "RAM_D[6]" LOC = "M20" ; +NET "RAM_D[7]" LOC = "M21" ; +NET "RAM_D[8]" LOC = "M22" ; +NET "RAM_D[9]" LOC = "Y22" ; +NET "RAM_D[10]" LOC = "Y21" ; +NET "RAM_D[11]" LOC = "Y20" ; +NET "RAM_D[12]" LOC = "Y19" ; +NET "RAM_D[13]" LOC = "W22" ; +NET "RAM_D[14]" LOC = "W21" ; +NET "RAM_D[15]" LOC = "W20" ; +NET "RAM_D[16]" LOC = "W19" ; +NET "RAM_D[17]" LOC = "V22" ; +NET "RAM_A[0]" LOC = "U21" ; +NET "RAM_A[1]" LOC = "T19" ; +NET "RAM_A[2]" LOC = "V21" ; +NET "RAM_A[3]" LOC = "V20" ; +NET "RAM_A[4]" LOC = "T20" ; +NET "RAM_A[5]" LOC = "T21" ; +NET "RAM_A[6]" LOC = "T22" ; +NET "RAM_A[7]" LOC = "T18" ; +NET "RAM_A[8]" LOC = "R18" ; +NET "RAM_A[9]" LOC = "P19" ; +NET "RAM_A[10]" LOC = "P21" ; +NET "RAM_A[11]" LOC = "P22" ; +NET "RAM_A[12]" LOC = "N19" ; +NET "RAM_A[13]" LOC = "N17" ; +NET "RAM_A[14]" LOC = "N18" ; +NET "RAM_A[15]" LOC = "T17" ; +NET "RAM_A[16]" LOC = "U19" ; +NET "RAM_A[17]" LOC = "U18" ; +NET "RAM_A[18]" LOC = "V19" ; +NET "RAM_CE1n" LOC = "U20" ; +NET "RAM_CENn" LOC = "P18" ; +NET "RAM_CLK" LOC = "P17" ; +NET "RAM_WEn" LOC = "R22" ; +NET "RAM_OEn" LOC = "R21" ; +NET "RAM_LDn" LOC = "R19" ; +NET "ser_enable" LOC = "W11" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "cpld_start" LOC = "AA9" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_detached" LOC = "V11" ; +NET "cpld_init_b" LOC = "W12" ; +NET "cpld_misc" LOC = "Y12" ; +NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; +NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; +NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; +NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; +NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; +NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; +NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; +NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; +NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; +NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; +NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; +NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; +NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; +NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_oen_a" LOC = "E19" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; +NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; +NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; +NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; +NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; +NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; +NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; +NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; +NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; +NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; +NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; +NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; +NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; +NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_lock" LOC = "D6" ; +NET "SCL" LOC = "A7" ; +NET "SDA" LOC = "D8" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "pps_in" LOC = "Y11" ; +NET "sclk" LOC = "K5" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sdi" LOC = "J1" ; +NET "sdo" LOC = "J2" ; +NET "sen_tx_db" LOC = "C1" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +#NET "dsp_clk" TNM_NET = "dsp_clk"; +#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +#NET "wb_clk" TNM_NET = "wb_clk"; +#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %; + +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/usrp2/top/u2_rev2/u2_rev2.v b/usrp2/top/u2_rev2/u2_rev2.v new file mode 100644 index 000000000..517285e52 --- /dev/null +++ b/usrp2/top/u2_rev2/u2_rev2.v @@ -0,0 +1,417 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_rev2 + ( + // Misc, debug + output [4:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + input cpld_detached,// V11 unused + output cpld_init_b, // W12 unused dual purpose + output cpld_misc, // Y12 + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output reg [15:0] dac_a, + output reg [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + assign cpld_init_b = 0; + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + wire clk90, clk180, clk270; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_a; + adc_b_reg1 <= adc_b; + adc_ovf_a_reg1 <= adc_ovf_a; + adc_ovf_b_reg1 <= adc_ovf_b; + end + + always @(posedge dsp_clk) + begin + adc_a_reg2 <= adc_a_reg1; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(clk90), + .CLK180(clk180), + .CLK270(clk270), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = 5'b01111 ^ leds_int; // all except eth are active-low + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + wire [15:0] dac_a_int, dac_b_int; + always @(negedge dsp_clk) dac_a <= dac_a_int; + always @(negedge dsp_clk) dac_b <= dac_b_int; + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_core #(.RAM_SIZE(32768)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_rev2 diff --git a/usrp2/top/u2_rev3/.gitignore b/usrp2/top/u2_rev3/.gitignore new file mode 100644 index 000000000..432f8fd58 --- /dev/null +++ b/usrp2/top/u2_rev3/.gitignore @@ -0,0 +1,57 @@ +/*.ptwx +/*.xrpt +/*.zip +/*_xdb +/templates +/netgen +/_ngo +/_xmsgs +/_pace.ucf +/*.cmd +/*.ibs +/*.lfp +/*.mfp +/*.bit +/*.bin +/*.stx +/*.par +/*.unroutes +/*.ntrc_log +/*.ngr +/*.mrp +/*.html +/*.lso +/*.twr +/*.bld +/*.ncd +/*.txt +/*.cmd_log +/*.drc +/*.map +/*.twr +/*.xml +/*.syr +/*.ngm +/*.xst +/*.csv +/*.html +/*.lock +/*.ncd +/*.twx +/*.ise_ISE_Backup +/*.xml +/*.ut +/*.xpi +/*.ngd +/*.ncd +/*.pad +/*.bgn +/*.ngc +/*.pcf +/*.ngd +/xst +/*.log +/*.rpt +/*.cel +/*.restore +/build diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile new file mode 100644 index 000000000..4358d7c56 --- /dev/null +++ b/usrp2/top/u2_rev3/Makefile @@ -0,0 +1,246 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2_rev3 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +control_lib/priority_enc.v \ +control_lib/pic.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2_rev3/u2_rev3.ucf \ +top/u2_rev3/u2_rev3.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf new file mode 100644 index 000000000..255a298ac --- /dev/null +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -0,0 +1,333 @@ +NET "leds[0]" LOC = "E8" ; +NET "leds[1]" LOC = "F7" ; +NET "leds[2]" LOC = "E5" ; +NET "leds[3]" LOC = "B7" ; +NET "leds[4]" LOC = "C11" ; +NET "leds[5]" LOC = "AB19" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "uart_tx_o" LOC = "C7" ; +NET "uart_rx_i" LOC = "A3" ; +NET "exp_pps_in_p" LOC = "V3" ; +NET "exp_pps_in_n" LOC = "V4" ; +NET "exp_pps_out_p" LOC = "V1" ; +NET "exp_pps_out_n" LOC = "V2" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_RX_CLK" LOC = "AA12" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "MDIO" LOC = "Y16" |PULLUP ; +NET "MDC" LOC = "V18" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "PHY_CLK" LOC = "V15" ; +NET "RAM_D[0]" LOC = "N20" ; +NET "RAM_D[1]" LOC = "N21" ; +NET "RAM_D[2]" LOC = "N22" ; +NET "RAM_D[3]" LOC = "M17" ; +NET "RAM_D[4]" LOC = "M18" ; +NET "RAM_D[5]" LOC = "M19" ; +NET "RAM_D[6]" LOC = "M20" ; +NET "RAM_D[7]" LOC = "M21" ; +NET "RAM_D[8]" LOC = "M22" ; +NET "RAM_D[9]" LOC = "Y22" ; +NET "RAM_D[10]" LOC = "Y21" ; +NET "RAM_D[11]" LOC = "Y20" ; +NET "RAM_D[12]" LOC = "Y19" ; +NET "RAM_D[13]" LOC = "W22" ; +NET "RAM_D[14]" LOC = "W21" ; +NET "RAM_D[15]" LOC = "W20" ; +NET "RAM_D[16]" LOC = "W19" ; +NET "RAM_D[17]" LOC = "V22" ; +NET "RAM_A[0]" LOC = "U21" ; +NET "RAM_A[1]" LOC = "T19" ; +NET "RAM_A[2]" LOC = "V21" ; +NET "RAM_A[3]" LOC = "V20" ; +NET "RAM_A[4]" LOC = "T20" ; +NET "RAM_A[5]" LOC = "T21" ; +NET "RAM_A[6]" LOC = "T22" ; +NET "RAM_A[7]" LOC = "T18" ; +NET "RAM_A[8]" LOC = "R18" ; +NET "RAM_A[9]" LOC = "P19" ; +NET "RAM_A[10]" LOC = "P21" ; +NET "RAM_A[11]" LOC = "P22" ; +NET "RAM_A[12]" LOC = "N19" ; +NET "RAM_A[13]" LOC = "N17" ; +NET "RAM_A[14]" LOC = "N18" ; +NET "RAM_A[15]" LOC = "T17" ; +NET "RAM_A[16]" LOC = "U19" ; +NET "RAM_A[17]" LOC = "U18" ; +NET "RAM_A[18]" LOC = "V19" ; +NET "RAM_CE1n" LOC = "U20" ; +NET "RAM_CENn" LOC = "P18" ; +NET "RAM_CLK" LOC = "P17" ; +NET "RAM_WEn" LOC = "R22" ; +NET "RAM_OEn" LOC = "R21" ; +NET "RAM_LDn" LOC = "R19" ; +NET "ser_enable" LOC = "W11" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "cpld_start" LOC = "AA9" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_detached" LOC = "V11" ; +NET "cpld_init_b" LOC = "W12" ; +NET "cpld_misc" LOC = "Y12" ; +NET "POR" LOC = "W18" ; +NET "WDI" LOC = "W15" ; +NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; +NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; +NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; +NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; +NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; +NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; +NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; +NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; +NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; +NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; +NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; +NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; +NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; +NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_oen_a" LOC = "E19" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; +NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; +NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; +NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; +NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; +NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; +NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; +NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; +NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; +NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; +NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; +NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; +NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; +NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_lock" LOC = "D6" ; +NET "SCL" LOC = "A7" ; +NET "SDA" LOC = "D8" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "pps_in" LOC = "K1" ; +NET "sclk" LOC = "K5" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sdi" LOC = "J1" ; +NET "sdo" LOC = "J2" ; +NET "sen_tx_db" LOC = "C1" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v new file mode 100644 index 000000000..23a825007 --- /dev/null +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -0,0 +1,432 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_rev3 + ( + // Misc, debug + output [5:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + input cpld_detached,// V11 unused + output cpld_init_b, // W12 unused dual purpose + output cpld_misc, // Y12 + + // Watchdog interface + input POR, + output WDI, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output reg [15:0] dac_a, + output reg [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + assign cpld_init_b = 0; + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + wire clk90, clk180, clk270; + + // reset the watchdog continuously + reg [15:0] wd; + wire config_success; + + always @(posedge wb_clk) + if(~config_success) + wd <= 0; + else + wd <= wd + 1; + assign WDI = wd[15]; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_a; + adc_b_reg1 <= adc_b; + adc_ovf_a_reg1 <= adc_ovf_a; + adc_ovf_b_reg1 <= adc_ovf_b; + end + + always @(posedge dsp_clk) + begin + adc_a_reg2 <= adc_a_reg1; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(clk90), + .CLK180(clk180), + .CLK270(clk270), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign leds = 6'b011111 ^ leds_int; // all except eth are active-low + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + wire [15:0] dac_a_int, dac_b_int; + always @(negedge dsp_clk) dac_a <= dac_a_int; + always @(negedge dsp_clk) dac_b <= dac_b_int; + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_core #(.RAM_SIZE(32768)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_rev2 diff --git a/usrp2/top/u2_rev3_2rx_iad/Makefile b/usrp2/top/u2_rev3_2rx_iad/Makefile new file mode 100644 index 000000000..5b7ed5a8e --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/Makefile @@ -0,0 +1,254 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2_rev3 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/buffer_int.v \ +control_lib/buffer_pool.v \ +control_lib/cascadefifo2.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/fifo_2clock.v \ +control_lib/fifo_2clock_casc.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/longfifo.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +eth/mac_rxfifo_int.v \ +eth/mac_txfifo_int.v \ +eth/rtl/verilog/Clk_ctrl.v \ +eth/rtl/verilog/MAC_rx.v \ +eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ +eth/rtl/verilog/MAC_rx/CRC_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ +eth/rtl/verilog/MAC_top.v \ +eth/rtl/verilog/MAC_tx.v \ +eth/rtl/verilog/MAC_tx/CRC_gen.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ +eth/rtl/verilog/MAC_tx/Random_gen.v \ +eth/rtl/verilog/Phy_int.v \ +eth/rtl/verilog/RMON.v \ +eth/rtl/verilog/RMON/RMON_addr_gen.v \ +eth/rtl/verilog/RMON/RMON_ctrl.v \ +eth/rtl/verilog/Reg_int.v \ +eth/rtl/verilog/eth_miim.v \ +eth/rtl/verilog/flow_ctrl_rx.v \ +eth/rtl/verilog/flow_ctrl_tx.v \ +eth/rtl/verilog/miim/eth_clockgen.v \ +eth/rtl/verilog/miim/eth_outputcontrol.v \ +eth/rtl/verilog/miim/eth_shiftreg.v \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/integrate.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_rev3/u2_rev3.ucf \ +top/u2_rev3/u2_rev3.v \ +top/u2_rev3_2rx_iad/u2_core.v \ +top/u2_rev3_2rx_iad/dsp_core_rx.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, testbench, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +testbench: + iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v + +clean: + rm -rf $(BUILD_DIR) + rm -f dsp_core_tb + rm -f *.lx2 + rm -f *.dat + rm -f *.vcd diff --git a/usrp2/top/u2_rev3_2rx_iad/README b/usrp2/top/u2_rev3_2rx_iad/README new file mode 100644 index 000000000..3efc5305b --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/README @@ -0,0 +1,32 @@ +This is a custom build for USRP2 FPGA. It allows using a BasicRX or +LFRX board and feed two independent, real signals. In addition, instead +of the CIC/HB decimator, which optimizes frequency response, it uses an +integrate and dump decimator, which optimizes for time-domain impulse +response. + +These changes have been made in dsp_core_rx.v: + +* A second DDC has been added, sharing a frequency register with + the existing DDC. + +* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... + into the receive FIFO. This limits the host configured decimation + to 8 intead of 4. Use gr.deinterleave to recover the streams. + +* The ADCs are hardcoded: + + RX_A ==> DDC #1 I-input + 0 ==> DDC #1 Q-input + RX_B ==> DDC #2 I-input + 0 ==> DDC #2 Q-input + + Thus, the input mux has been disabled. + +* The CIC/HB decimator has been replaced by an integrate and dump at + the decimation rate. + +* To assist with meeting timing, the external RAM has been disabled. + +The basic application is to coherently sample two real IF streams and +downconvert to baseband, while minimizing the impulse response duration +of the resampling filters. diff --git a/usrp2/top/u2_rev3_2rx_iad/cmdfile b/usrp2/top/u2_rev3_2rx_iad/cmdfile new file mode 100644 index 000000000..34373a676 --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/cmdfile @@ -0,0 +1,4 @@ +-y . +-y ../../sdr_lib +-y ../../control_lib +-y ../../models diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v b/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v new file mode 100644 index 000000000..4a945bd1a --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v @@ -0,0 +1,212 @@ +`define DSP_CORE_RX_BASE 160 +module dsp_core_rx + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [13:0] adc_a, input adc_ovf_a, + input [13:0] adc_b, input adc_ovf_b, + + input [15:0] io_rx, + + output reg [31:0] sample, + input run, + output strobe, + output [31:0] debug + ); + + wire [15:0] scale_i, scale_q; + wire [13:0] adc_a_ofs, adc_b_ofs; + reg [13:0] adc_i, adc_q; + wire [31:0] phase_inc; + reg [31:0] phase; + + wire [35:0] prod_i, prod_q; + wire [23:0] i_cordic_a, q_cordic_a, i_cordic_b, q_cordic_b; + wire [31:0] i_iad_a, q_iad_a, i_iad_b, q_iad_b; + wire [15:0] i_out_a, q_out_a, i_out_b, q_out_b; + + wire enable_hb1, enable_hb2; // Correspond to std firmware settings + wire [7:0] cic_decim; // for combined CIC/HB decimator + wire [9:0] decim_rate; // Reconstructed original decimation setting + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_a),.adc_out(adc_a_ofs)); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_b),.adc_out(adc_b_ofs)); + +`ifdef MUXCTRL + wire [3:0] muxctrl; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(muxctrl),.changed()); +`endif + + wire [1:0] gpio_ena; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(gpio_ena),.changed()); + + // The TVRX connects to what is called adc_b, thus A and B are + // swapped throughout the design. + // + // In the interest of expediency and keeping the s/w sane, we just remap them here. + // The I & Q fields are mapped the same: + // 0 -> "the real A" (as determined by the TVRX) + // 1 -> "the real B" + // 2 -> const zero + +`ifdef MUXCTRL + always @(posedge clk) + case(muxctrl[1:0]) // The I mapping + 0: adc_i <= adc_b_ofs; // "the real A" + 1: adc_i <= adc_a_ofs; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case(muxctrl[1:0]) + + always @(posedge clk) + case(muxctrl[3:2]) // The Q mapping + 0: adc_q <= adc_b_ofs; // "the real A" + 1: adc_q <= adc_a_ofs; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case(muxctrl[3:2]) +`else // !`ifdef MUXCTRL + always @(posedge clk) + begin + adc_i <= adc_a_ofs; + adc_q <= adc_b_ofs; + end +`endif // !`ifdef MUXCTRL + + always @(posedge clk) + if(rst) + phase <= 0; + else if(~run) + phase <= 0; + else + phase <= phase + phase_inc; + + MULT18X18S mult_i + (.P(prod_i), // 36-bit multiplier output + .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + MULT18X18S mult_q + (.P(prod_q), // 36-bit multiplier output + .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + + // Route I,0 to first CORDIC + cordic_z24 #(.bitwidth(24)) + cordic_a(.clock(clk), .reset(rst), .enable(run), + .xi(prod_i[24:1]),. yi(0), .zi(phase[31:8]), + .xo(i_cordic_a),.yo(q_cordic_a),.zo() ); + + // Route Q,0 to second CORDIC + cordic_z24 #(.bitwidth(24)) + cordic_b(.clock(clk), .reset(rst), .enable(run), + .xi(prod_q[24:1]),. yi(0), .zi(phase[31:8]), + .xo(i_cordic_b),.yo(q_cordic_b),.zo() ); + + // Reconstruct original decimation rate from standard firmware settings + assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : + {1'b0,cic_decim,1'b0 }) : + cic_decim; + + cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator + cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), + .strobe_fast(1),.strobe_slow(strobe_iad) ); + + wire strobe_iad_o; + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_a + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(i_cordic_a), + .stb_o(strobe_iad_o),.integ_o(i_iad_a) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_a + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(q_cordic_a), + .stb_o(),.integ_o(q_iad_a) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_b + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(i_cordic_b), + .stb_o(),.integ_o(i_iad_b) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_b + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(q_cordic_b), + .stb_o(),.integ_o(q_iad_b) ); + + round #(.bits_in(32),.bits_out(16)) round_iout_a (.in(i_iad_a),.out(i_out_a)); + round #(.bits_in(32),.bits_out(16)) round_qout_a (.in(q_iad_a),.out(q_out_a)); + round #(.bits_in(32),.bits_out(16)) round_iout_b (.in(i_iad_b),.out(i_out_b)); + round #(.bits_in(32),.bits_out(16)) round_qout_b (.in(q_iad_b),.out(q_out_b)); + + reg [31:0] sample_out_a, sample_out_b, sample_out; + reg stb_d1, stb_d2, stb_d3, stb_d4, stb_d5; + reg strobe_out; + + // Register samples on strobe_iad + // Output A on d1 + // Output B on d5 + always @(posedge clk) + begin + stb_d1 <= strobe_iad_o; + stb_d2 <= stb_d1; + stb_d3 <= stb_d2; + stb_d4 <= stb_d3; + stb_d5 <= stb_d4; + end + + always @(posedge clk) + if (strobe_iad_o) + begin + // Streaming GPIO + // io_rx[15] => I channel LSB if gpio_ena[0] high + // io_rx[14] => Q channel LSB if gpio_ena[1] high + sample_out_a <= {i_out_a[15:1], gpio_ena[0] ? io_rx[15] : i_out_a[0], + q_out_a[15:1], gpio_ena[1] ? io_rx[14] : q_out_a[0] }; + sample_out_b <= {i_out_b[15:1], gpio_ena[0] ? io_rx[15] : i_out_b[0], + q_out_b[15:1], gpio_ena[1] ? io_rx[14] : q_out_b[0] }; + end + + always @(posedge clk) + begin + if (stb_d1) + sample <= sample_out_a; + else if (stb_d5) + sample <= sample_out_b; + strobe_out <= stb_d1|stb_d5; + end + + assign strobe = strobe_out; + assign debug = 0; + +endmodule // dsp_core_rx diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav new file mode 100644 index 000000000..12f746860 --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav @@ -0,0 +1,106 @@ +[size] 1680 975 +[pos] -1 -1 +*-17.007835 70679400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] dsp_core_tb. +@200 +-SYSCON +@28 +dsp_core_tb.clk +dsp_core_tb.rst +dsp_core_tb.run +@200 +- +-Settings Bus +@22 +dsp_core_tb.set_addr[7:0] +@24 +dsp_core_tb.set_data[31:0] +@28 +dsp_core_tb.set_stb +@200 +- +-RX DSP CORE +@22 +dsp_core_tb.rx_path.adc_a[13:0] +dsp_core_tb.rx_path.adc_b[13:0] +@28 +dsp_core_tb.rx_path.adc_ovf_a +dsp_core_tb.rx_path.adc_ovf_b +@22 +dsp_core_tb.rx_path.io_rx[15:0] +@200 +- +@22 +dsp_core_tb.rx_path.sample[31:0] +@28 +dsp_core_tb.rx_path.strobe +@200 +- +@22 +dsp_core_tb.rx_path.phase_inc[31:0] +dsp_core_tb.rx_path.scale_i[15:0] +dsp_core_tb.rx_path.scale_q[15:0] +@28 +dsp_core_tb.rx_path.enable_hb1 +dsp_core_tb.rx_path.enable_hb2 +@22 +dsp_core_tb.rx_path.cic_decim[7:0] +dsp_core_tb.rx_path.adc_a_ofs[13:0] +dsp_core_tb.rx_path.adc_b_ofs[13:0] +dsp_core_tb.rx_path.muxctrl[3:0] +@200 +- +@22 +dsp_core_tb.rx_path.adc_i[13:0] +dsp_core_tb.rx_path.adc_q[13:0] +dsp_core_tb.rx_path.phase[31:0] +dsp_core_tb.rx_path.prod_i[35:0] +dsp_core_tb.rx_path.prod_q[35:0] +@8420 +dsp_core_tb.rx_path.i_cordic_a[23:0] +dsp_core_tb.rx_path.q_cordic_a[23:0] +dsp_core_tb.rx_path.i_cordic_b[23:0] +dsp_core_tb.rx_path.q_cordic_b[23:0] +@22 +dsp_core_tb.rx_path.decim_rate[9:0] +@28 +dsp_core_tb.rx_path.strobe_iad +@22 +dsp_core_tb.rx_path.i_iad_a[31:0] +dsp_core_tb.rx_path.q_iad_a[31:0] +@23 +dsp_core_tb.rx_path.i_iad_b[31:0] +@22 +dsp_core_tb.rx_path.q_iad_b[31:0] +@28 +dsp_core_tb.rx_path.strobe_iad_o +@8420 +dsp_core_tb.rx_path.i_out_a[15:0] +dsp_core_tb.rx_path.q_out_a[15:0] +dsp_core_tb.rx_path.i_out_b[15:0] +dsp_core_tb.rx_path.q_out_b[15:0] +@28 +dsp_core_tb.rx_path.gpio_ena[1:0] +@22 +dsp_core_tb.rx_path.sample_out_a[31:0] +dsp_core_tb.rx_path.sample_out_b[31:0] +dsp_core_tb.rx_path.sample[31:0] +@28 +dsp_core_tb.rx_path.strobe_out +dsp_core_tb.rx_path.stb_d1 +dsp_core_tb.rx_path.stb_d2 +dsp_core_tb.rx_path.stb_d3 +dsp_core_tb.rx_path.stb_d4 +dsp_core_tb.rx_path.stb_d5 +@200 +- +-FIFO Bus +@22 +dsp_core_tb.master_time[31:0] +dsp_core_tb.wr_dat[31:0] +@28 +dsp_core_tb.wr_done +dsp_core_tb.wr_error +dsp_core_tb.wr_full +dsp_core_tb.wr_ready +dsp_core_tb.wr_write diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v new file mode 100644 index 000000000..d947df40a --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v @@ -0,0 +1,233 @@ +`timescale 1ns / 100ps + +module dsp_core_tb; + +/////////////////////////////////////////////////////////////////////////////////// +// Sim-wide wires/busses // +/////////////////////////////////////////////////////////////////////////////////// + + // System control bus + reg clk = 0; + reg rst = 1; + + // Configuration bus + reg set_stb = 0; + reg [7:0] set_addr = 0; + reg [31:0] set_data = 0; + + // ADC input bus + wire signed [13:0] adc_a; + wire signed [13:0] adc_b; + wire adc_ovf_a; + wire adc_ovf_b; + + // RX sample bus + reg run = 1; + wire [31:0] sample; + wire stb; + +/////////////////////////////////////////////////////////////////////////////////// +// Simulation control // +/////////////////////////////////////////////////////////////////////////////////// + + // Set up output files + initial begin + $dumpfile("dsp_core_tb.vcd"); + $dumpvars(0,dsp_core_tb); + end + + // Update display every 10 us + always #1000 $monitor("Time in us ",$time/1000); + + // Generate master clock 50% @ 100 MHz + always + #5 clk = ~clk; + +/////////////////////////////////////////////////////////////////////////////////// +// Unit(s) under test // +/////////////////////////////////////////////////////////////////////////////////// + + reg [13:0] amplitude = 13'h1fff; + reg [15:0] impulse_len = 0; + reg [15:0] zero_len = 0; + reg adc_ena = 0; + + initial #500 @(posedge clk) adc_ena = 1; + + impulse adc + (.clk(clk),.rst(rst),.ena(adc_ena), + .dc_offset_a(0),.dc_offset_b(0), + .amplitude(amplitude), + .impulse_len(impulse_len),.zero_len(zero_len), + .adc_a(adc_a),.adc_b(adc_b), + .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); + + initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's + initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset + dsp_core_rx rx_path + (.clk(clk),.rst(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), + .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .io_rx(16'b0), + .run(adc_ena),.sample(sample),.strobe(stb), + .debug() ); + + reg [31:0] master_time = 0; + always @(posedge clk) + master_time <= master_time + 1; + + reg wr_ready = 1; + reg wr_full = 0; + + wire [31:0] wr_dat; + wire wr_write; + wire wr_done; + wire wr_error; + wire [15:0] fifo_occupied; + wire fifo_full; + wire fifo_empty; + + rx_control rx_buffer + (.clk(clk),.rst(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time), + .overrun(), // unconnected output + .wr_dat_o(wr_dat), + .wr_write_o(wr_write), + .wr_done_o(wr_done), + .wr_error_o(wr_error), + .wr_ready_i(wr_ready), + .wr_full_i(wr_full), + .sample(sample), + .run(), // unconnected output, supposed to drive 'run' + .strobe(stb), + .fifo_occupied(fifo_occupied), + .fifo_full(fifo_full), + .fifo_empty(fifo_empty), + .debug_rx() // unconnected output + ); + + + +/////////////////////////////////////////////////////////////////////////////////// +// Simulation output/checking // +/////////////////////////////////////////////////////////////////////////////////// + + integer rx_file; + + initial + rx_file = $fopen("rx.dat", "wb"); + + always @(posedge clk) + begin + // Write RX sample I&Q in format Octave can load + if (stb) + begin + $fwrite(rx_file, sample[31:16]); + $fputc(32, rx_file); + $fwrite(rx_file, sample[15:0]); + $fputc(13, rx_file); + end + end + +/////////////////////////////////////////////////////////////////////////////////// +// Tasks // +/////////////////////////////////////////////////////////////////////////////////// + + task power_on; + begin + @(posedge clk) + rst = #1 1'b1; + @(posedge clk) + rst = #1 1'b0; + end + endtask // power_on + + task set_impulse_len; + input [15:0] len; + @(posedge clk) impulse_len = len-1; + endtask + + task set_zero_len; + input [15:0] len; + @(posedge clk) zero_len = len-1; + endtask + + // Strobe configuration bus with addr, data + task write_cfg_register; + input [7:0] regno; + input [31:0] value; + + begin + @(posedge clk); + set_addr <= regno; + set_data <= value; + set_stb <= 1'b1; + @(posedge clk); + set_stb <= 1'b0; + end + endtask // write_cfg_register + + // Set RX DDC frequency + task set_ddc_freq; + input [31:0] freq; + + write_cfg_register(160, freq); + endtask // set_ddc_freq + + // Set RX IQ scaling registers + task set_rx_scale_iq; + input [15:0] scale_i; + input [15:0] scale_q; + + write_cfg_register(161, {scale_i,scale_q}); + endtask // set_rx_scale_iq + + // Set RX MUX control + task set_rx_muxctrl; + input [3:0] muxctrl; + + write_cfg_register(168, muxctrl); + endtask // set_rx_muxctrl + + // Set RX CIC decim and halfband enables + task set_decim; + input hb1_ena; + input hb2_ena; + input [7:0] decim; + + write_cfg_register(162, {hb1_ena,hb2_ena,decim}); + endtask // set_decim + + +/////////////////////////////////////////////////////////////////////////////////// +// Individual tests // +/////////////////////////////////////////////////////////////////////////////////// + + task test_rx; + begin + set_impulse_len(10); + set_zero_len(990); + set_rx_muxctrl(1); + set_ddc_freq(32'h10000000); + set_rx_scale_iq(1243, 1243); + set_decim(1, 1, 1); + + #100000 $finish; + end + endtask // test_rx + + +/////////////////////////////////////////////////////////////////////////////////// +// Top-level test // +/////////////////////////////////////////////////////////////////////////////////// + + // Execute tests + initial + begin + power_on(); + test_rx(); + end + +endmodule // dsp_core_tb diff --git a/usrp2/top/u2_rev3_2rx_iad/impulse.v b/usrp2/top/u2_rev3_2rx_iad/impulse.v new file mode 100644 index 000000000..fc5e3c1ed --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/impulse.v @@ -0,0 +1,68 @@ +module impulse + (input clk, + input rst, + input ena, + + input [13:0] dc_offset_a, + input [13:0] dc_offset_b, + input [13:0] amplitude, + input [15:0] impulse_len, + input [15:0] zero_len, + + output [13:0] adc_a, + output [13:0] adc_b, + output adc_ovf_a, + output adc_ovf_b + ); + + reg [13:0] adc_a_int = 0; + reg [13:0] adc_b_int = 0; + + reg [15:0] count; + + localparam ST_ZERO = 0; + localparam ST_HIGH = 1; + reg state; + + always @(posedge clk) + if (rst | ~ena) + begin + adc_a_int <= 0; + adc_b_int <= 0; + count <= 0; + state <= ST_ZERO; + end + else + case(state) + ST_ZERO: + if (count == zero_len) + begin + adc_a_int <= amplitude; + adc_b_int <= amplitude >> 2; + state <= ST_HIGH; + count <= 0; + end + else + count <= count + 1; + + ST_HIGH: + if (count == impulse_len) + begin + adc_a_int <= 0; + adc_b_int <= 0; + state <= ST_ZERO; + count <= 0; + end + else + count <= count + 1; + + endcase // case (state) + + assign adc_a = adc_a_int + dc_offset_a; + assign adc_b = adc_b_int + dc_offset_b; + + // Ignore for now + assign adc_ovf_a = 0; + assign adc_ovf_b = 0; + +endmodule // impulse diff --git a/usrp2/top/u2_rev3_2rx_iad/u2_core.v b/usrp2/top/u2_rev3_2rx_iad/u2_core.v new file mode 100755 index 000000000..3d96a4e0e --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/u2_core.v @@ -0,0 +1,789 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + #(parameter RAM_SIZE=32768) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, + s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc; + wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err; + wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we; + + wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), + .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10), + .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10), + .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10), + .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty), + .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb), + .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty), + .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb), + .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty), + .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb), + .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty), + .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb), + .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty), + .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb), + .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty), + .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + assign s0_err = 1'b0; + assign s0_rty = 1'b0; + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // Buffer Pool, slave #1 + wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop; + wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop; + wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop; + wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full; + wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full; + wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full; + wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done), + .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full), + .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done), + .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full), + .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done), + .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full), + .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done), + .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full), + // Read Interfaces + .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done), + .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop), + .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done), + .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop), + .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done), + .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop), + .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done), + .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop) + ); + + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + assign s2_rty = 1'b0; + + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + assign s3_err = 1'b0; + assign s3_rty = 1'b0; + + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + assign s4_err = 1'b0; + assign s4_rty = 1'b0; + + // Buffer Pool Status -- Slave #5 + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), + .wb_dat_o(s5_dat_i), + .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), + .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) + ); + + assign s5_err = 1'b0; + assign s5_rty = 1'b0; + + // Slave, #6 Ethernet MAC, see below + + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_err = 1'b0; + assign s7_rty = 1'b0; + assign s7_dat_i = 32'd0; + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {clk_status,serdes_link_up}; + + setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop; + wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err; + wire [31:0] Tx_mac_data, Rx_mac_data; + wire [1:0] Tx_mac_BE, Rx_mac_BE; + wire rst_mac; + + oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac)); + + MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11)) + MAC_top + (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk), + .rst_mac(rst_mac),.rst_user(dsp_rst), + .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]), + .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack), + .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE), + .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), + .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), + .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), + .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD), + .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD), + .Crs(GMII_CRS),.Col(GMII_COL), + .Mdio(MDIO),.Mdc(MDC), + .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2), + .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), + .debug0(debug_mac0),.debug1(debug_mac1) ); + + assign s6_err = 1'b0; + assign s6_rty = 1'b0; + + mac_rxfifo_int mac_rxfifo_int + (.clk(dsp_clk),.rst(dsp_rst), + .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), + .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop), + .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), + .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done), + .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full), + .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) ); + + mac_txfifo_int mac_txfifo_int + (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac), + .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), + .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), + .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done), + .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop), + .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) ); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; + + simple_pic #(.is(16),.dwidth(32)) simple_pic + (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + assign s8_err = 0; + assign s8_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + assign s9_err = 0; + assign s9_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack), + .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + assign s10_err = 0; + assign s10_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), + .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + assign s11_err = 0; + assign s11_rty = 0; + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; + always @(negedge dsp_clk) pps_negedge <= pps_in; + always @(posedge dsp_clk) pps_posedge <= pps_in; + always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; + always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; + + wire pps_o; + time_sync time_sync + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]), + .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack), + .sys_clk_i(dsp_clk),.master_time_o(master_time), + .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), + .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), + .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); + assign s12_err = 0; + assign s12_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + sd_spi_wb sd_spi_wb + (.clk(wb_clk),.rst(wb_rst), + .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we), + .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i), + .wb_ack_o(s13_ack) ); + assign s13_err = 0; + assign s13_rty = 0; + // ///////////////////////////////////////////////////////////////////////// + // DSP + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + + rx_control #(.FIFOSIZE(10)) rx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.overrun(overrun), + .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error), + .wr_ready_i(wr1_ready), .wr_full_i(wr1_full), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), + .debug_rx(debug_rx) ); + + // dummy_rx dsp_core_rx + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + tx_control #(.FIFOSIZE(10)) tx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.underrun(underrun), + .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop), + .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), + .debug(debug_txc) ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error), + .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error), + .wr_ready_i(wr0_ready),.wr_full_i(wr0_full), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + +`ifdef EXTRAM + // /////////////////////////////////////////////////////////////////////////////////// + // External RAM Interface + + localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes + + wire [15:0] bus2ram, ram2bus; + wire [15:0] bridge_adr; + wire [1:0] bridge_sel; + wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; + + wire [19:0] page; + wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; + setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(page),.changed()); + + wb_bridge_16_32 bridge + (.wb_clk(wb_clk),.wb_rst(wb_rst), + .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel), + .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack), + .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), + .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); + + wb_zbt16_b wb_zbt16_b + (.clk(wb_clk),.rst(wb_rst), + .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), + .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), + .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), + .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), + .sram_mode(),.sram_zz() ); + + assign s14_err = 0; assign s14_rty = 0; + assign RAM_CE1n = 0; + assign RAM_D[17:16] = 2'bzz; +`endif + +`ifdef DEBUG + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // FIFO Level Debugging + reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; + + always @(posedge dsp_clk) + serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, + {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; + + assign debug_clk[0] = 0; + assign debug_clk[1] = dsp_clk; + + assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; +`endif + +endmodule // u2_core + +// wire debug_mux; +// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), +// .in(set_data),.out(debug_mux),.changed()); + +//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; +//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; + +//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, +// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; + +//assign debug = debug_tx_dsp; +//assign debug = debug_serdes0; + +//assign debug_gpio_0 = 0; //debug_serdes0; +//assign debug_gpio_1 = 0; //debug_serdes1; + +// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, +// {8'b0}, +// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, +// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; + +//assign debug = {dac_a,dac_b}; + +/* + assign debug = {{ram_loader_done, takeover, 6'd0}, + {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, + {8'd0}, + {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ + +/*assign debug = host_to_dsp_fifo; + assign debug_gpio_0 = eth_mac_debug; + assign debug_gpio_1 = 0; + */ +// Assign various commonly used debug buses. +/* + wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, + irq[7:0], + GMII_RXD, + GMII_TXD}; + + wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; + + wire [31:0] debug_time = {uart_tx_o, 7'b0, + irq[7:0], + 6'b0, GMII_RX_DV, GMII_TX_EN, + 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; + + wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, + irq[7:0], + proc_int, 7'b0 }; + + wire [31:0] debug_eth = + {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, + {8'd0}, + {8'd0}, + {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; + + assign debug_serdes0 = { { rd0_dat[7:0] }, + { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, + { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, + { ser_r[15:8] }, + { ser_r[7:0] } }; + + assign debug_gpio_1 = {uart_tx_o,7'd0, + 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, + debug_txc[15:0]}; + assign debug_gpio_1 = debug_rx; + assign debug_gpio_1 = debug_serdes1; + assign debug_gpio_1 = debug_eth; + + */ + diff --git a/usrp2/top/u2_rev3_2rx_iad/wave.sh b/usrp2/top/u2_rev3_2rx_iad/wave.sh new file mode 100755 index 000000000..626f224e5 --- /dev/null +++ b/usrp2/top/u2_rev3_2rx_iad/wave.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/usrp2/top/u2_rev3_iad/.gitignore b/usrp2/top/u2_rev3_iad/.gitignore new file mode 100644 index 000000000..e4daaf1ea --- /dev/null +++ b/usrp2/top/u2_rev3_iad/.gitignore @@ -0,0 +1,4 @@ +/build +/*.vcd +/dsp_core_tb +/*.dat diff --git a/usrp2/top/u2_rev3_iad/Makefile b/usrp2/top/u2_rev3_iad/Makefile new file mode 100644 index 000000000..5ae8846dd --- /dev/null +++ b/usrp2/top/u2_rev3_iad/Makefile @@ -0,0 +1,254 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2_rev3 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/buffer_int.v \ +control_lib/buffer_pool.v \ +control_lib/cascadefifo2.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/fifo_2clock.v \ +control_lib/fifo_2clock_casc.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/longfifo.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +eth/mac_rxfifo_int.v \ +eth/mac_txfifo_int.v \ +eth/rtl/verilog/Clk_ctrl.v \ +eth/rtl/verilog/MAC_rx.v \ +eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ +eth/rtl/verilog/MAC_rx/CRC_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ +eth/rtl/verilog/MAC_top.v \ +eth/rtl/verilog/MAC_tx.v \ +eth/rtl/verilog/MAC_tx/CRC_gen.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ +eth/rtl/verilog/MAC_tx/Random_gen.v \ +eth/rtl/verilog/Phy_int.v \ +eth/rtl/verilog/RMON.v \ +eth/rtl/verilog/RMON/RMON_addr_gen.v \ +eth/rtl/verilog/RMON/RMON_ctrl.v \ +eth/rtl/verilog/Reg_int.v \ +eth/rtl/verilog/eth_miim.v \ +eth/rtl/verilog/flow_ctrl_rx.v \ +eth/rtl/verilog/flow_ctrl_tx.v \ +eth/rtl/verilog/miim/eth_clockgen.v \ +eth/rtl/verilog/miim/eth_outputcontrol.v \ +eth/rtl/verilog/miim/eth_shiftreg.v \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/integrate.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2_rev3/u2_rev3.ucf \ +top/u2_rev3/u2_rev3.v \ +top/u2_rev3_iad/dsp_core_rx.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, testbench, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +testbench: + iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v + +clean: + rm -rf $(BUILD_DIR) + rm -f dsp_core_tb + rm -f *.lx2 + rm -f *.dat + rm -f *.vcd diff --git a/usrp2/top/u2_rev3_iad/cmdfile b/usrp2/top/u2_rev3_iad/cmdfile new file mode 100644 index 000000000..34373a676 --- /dev/null +++ b/usrp2/top/u2_rev3_iad/cmdfile @@ -0,0 +1,4 @@ +-y . +-y ../../sdr_lib +-y ../../control_lib +-y ../../models diff --git a/usrp2/top/u2_rev3_iad/dsp_core_rx.v b/usrp2/top/u2_rev3_iad/dsp_core_rx.v new file mode 100644 index 000000000..2882464ba --- /dev/null +++ b/usrp2/top/u2_rev3_iad/dsp_core_rx.v @@ -0,0 +1,158 @@ +`define DSP_CORE_RX_BASE 160 +module dsp_core_rx + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [13:0] adc_a, input adc_ovf_a, + input [13:0] adc_b, input adc_ovf_b, + + input [15:0] io_rx, + + output [31:0] sample, + input run, + output strobe, + output [31:0] debug + ); + + wire [15:0] scale_i, scale_q; + wire [13:0] adc_a_ofs, adc_b_ofs; + reg [13:0] adc_i, adc_q; + wire [31:0] phase_inc; + reg [31:0] phase; + + wire [35:0] prod_i, prod_q; + wire [23:0] i_cordic, q_cordic; + wire [31:0] i_iad, q_iad; + wire [15:0] i_out, q_out; + + wire enable_hb1, enable_hb2; // Correspond to std firmware settings + wire [7:0] cic_decim; // for combined CIC/HB decimator + wire [9:0] decim_rate; // Reconstructed original decimation setting + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phase_inc),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({scale_i,scale_q}),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_a),.adc_out(adc_a_ofs)); + + rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_in(adc_b),.adc_out(adc_b_ofs)); + + wire [3:0] muxctrl; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(muxctrl),.changed()); + + wire [1:0] gpio_ena; + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(gpio_ena),.changed()); + + // The TVRX connects to what is called adc_b, thus A and B are + // swapped throughout the design. + // + // In the interest of expediency and keeping the s/w sane, we just remap them here. + // The I & Q fields are mapped the same: + // 0 -> "the real A" (as determined by the TVRX) + // 1 -> "the real B" + // 2 -> const zero + + always @(posedge clk) + case(muxctrl[1:0]) // The I mapping + 0: adc_i <= adc_b_ofs; // "the real A" + 1: adc_i <= adc_a_ofs; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case(muxctrl[1:0]) + + always @(posedge clk) + case(muxctrl[3:2]) // The Q mapping + 0: adc_q <= adc_b_ofs; // "the real A" + 1: adc_q <= adc_a_ofs; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case(muxctrl[3:2]) + + always @(posedge clk) + if(rst) + phase <= 0; + else if(~run) + phase <= 0; + else + phase <= phase + phase_inc; + + MULT18X18S mult_i + (.P(prod_i), // 36-bit multiplier output + .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + MULT18X18S mult_q + (.P(prod_q), // 36-bit multiplier output + .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input + .C(clk), // Clock input + .CE(1), // Clock enable input + .R(rst) // Synchronous reset input + ); + + + cordic_z24 #(.bitwidth(24)) + cordic(.clock(clk), .reset(rst), .enable(run), + .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]), + .xo(i_cordic),.yo(q_cordic),.zo() ); + + // Reconstruct original decimation rate from standard firmware settings + assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : + {1'b0,cic_decim,1'b0 }) : + cic_decim; + + cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator + cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), + .strobe_fast(1),.strobe_slow(strobe_iad) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(i_cordic), + .stb_o(strobe),.integ_o(i_iad) ); + + integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q + (.clk_i(clk),.rst_i(rst),.ena_i(run), + .dump_i(strobe_iad),.data_i(q_cordic), + .stb_o(),.integ_o(q_iad) ); + + round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out)); + round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out)); + + // Streaming GPIO + // + // io_rx[15] => I channel LSB if gpio_ena[0] high + // io_rx[14] => Q channel LSB if gpio_ena[1] high + + reg [31:0] sample_reg; + always @(posedge clk) + begin + sample_reg[31:17] <= i_out[15:1]; + sample_reg[15:1] <= q_out[15:1]; + sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; + sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; + end + + assign sample = sample_reg; + assign debug = {clk, rst, run, strobe}; + +endmodule // dsp_core_rx diff --git a/usrp2/top/u2_rev3_iad/dsp_core_tb.sav b/usrp2/top/u2_rev3_iad/dsp_core_tb.sav new file mode 100644 index 000000000..17c90cdd7 --- /dev/null +++ b/usrp2/top/u2_rev3_iad/dsp_core_tb.sav @@ -0,0 +1,61 @@ +[size] 1680 975 +[pos] -1 -1 +*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] dsp_core_tb. +@200 +-SYSCON +@28 +dsp_core_tb.clk +dsp_core_tb.rst +dsp_core_tb.run +@200 +- +-Settings Bus +@22 +dsp_core_tb.set_addr[7:0] +@24 +dsp_core_tb.set_data[31:0] +@28 +dsp_core_tb.set_stb +@200 +- +-RX DSP CORE +- +@24 +dsp_core_tb.rx_path.decim_rate[9:0] +@200 +- +@8420 +dsp_core_tb.adc_a[13:0] +@20000 +- +@200 +- +@8420 +dsp_core_tb.rx_path.adc_a_ofs[13:0] +@20000 +- +@200 +- +@8022 +dsp_core_tb.rx_path.i_cordic[23:0] +@20000 +- +@200 +- +@8022 +dsp_core_tb.rx_path.i_iad[31:0] +@20000 +- +@200 +- +@8420 +dsp_core_tb.rx_path.i_out[15:0] +@20000 +- +@200 +- +@28 +dsp_core_tb.stb +@200 +- diff --git a/usrp2/top/u2_rev3_iad/dsp_core_tb.v b/usrp2/top/u2_rev3_iad/dsp_core_tb.v new file mode 100644 index 000000000..4d5a5b537 --- /dev/null +++ b/usrp2/top/u2_rev3_iad/dsp_core_tb.v @@ -0,0 +1,196 @@ +`timescale 1ns / 100ps + +module dsp_core_tb; + +/////////////////////////////////////////////////////////////////////////////////// +// Sim-wide wires/busses // +/////////////////////////////////////////////////////////////////////////////////// + + // System control bus + reg clk = 0; + reg rst = 1; + + // Configuration bus + reg set_stb = 0; + reg [7:0] set_addr = 0; + reg [31:0] set_data = 0; + + // ADC input bus + wire signed [13:0] adc_a; + wire signed [13:0] adc_b; + wire adc_ovf_a; + wire adc_ovf_b; + + // RX sample bus + reg run = 1; + wire [31:0] sample; + wire stb; + +/////////////////////////////////////////////////////////////////////////////////// +// Simulation control // +/////////////////////////////////////////////////////////////////////////////////// + + // Set up output files + initial begin + $dumpfile("dsp_core_tb.vcd"); + $dumpvars(0,dsp_core_tb); + end + + // Update display every 10 us + always #1000 $monitor("Time in us ",$time/1000); + + // Generate master clock 50% @ 100 MHz + always + #5 clk = ~clk; + +/////////////////////////////////////////////////////////////////////////////////// +// Unit(s) under test // +/////////////////////////////////////////////////////////////////////////////////// + + reg [13:0] amplitude = 13'h1fff; + reg [15:0] impulse_len = 0; + reg [15:0] zero_len = 0; + reg adc_ena = 0; + + initial #500 @(posedge clk) adc_ena = 1; + + impulse adc + (.clk(clk),.rst(rst),.ena(adc_ena), + .dc_offset_a(0),.dc_offset_b(0), + .amplitude(amplitude), + .impulse_len(impulse_len),.zero_len(zero_len), + .adc_a(adc_a),.adc_b(adc_b), + .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); + + initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's + initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset + dsp_core_rx rx_path + (.clk(clk),.rst(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), + .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .io_rx(16'b0), + .run(adc_ena),.sample(sample),.strobe(stb), + .debug() ); + +/////////////////////////////////////////////////////////////////////////////////// +// Simulation output/checking // +/////////////////////////////////////////////////////////////////////////////////// + + integer rx_file; + + initial + rx_file = $fopen("rx.dat", "wb"); + + always @(posedge clk) + begin + // Write RX sample I&Q in format Octave can load + if (stb) + begin + $fwrite(rx_file, sample[31:16]); + $fputc(32, rx_file); + $fwrite(rx_file, sample[15:0]); + $fputc(13, rx_file); + end + end + +/////////////////////////////////////////////////////////////////////////////////// +// Tasks // +/////////////////////////////////////////////////////////////////////////////////// + + task power_on; + begin + @(posedge clk) + rst = #1 1'b1; + @(posedge clk) + rst = #1 1'b0; + end + endtask // power_on + + task set_impulse_len; + input [15:0] len; + @(posedge clk) impulse_len = len-1; + endtask + + task set_zero_len; + input [15:0] len; + @(posedge clk) zero_len = len-1; + endtask + + // Strobe configuration bus with addr, data + task write_cfg_register; + input [7:0] regno; + input [31:0] value; + + begin + @(posedge clk); + set_addr <= regno; + set_data <= value; + set_stb <= 1'b1; + @(posedge clk); + set_stb <= 1'b0; + end + endtask // write_cfg_register + + // Set RX DDC frequency + task set_ddc_freq; + input [31:0] freq; + + write_cfg_register(160, freq); + endtask // set_ddc_freq + + // Set RX IQ scaling registers + task set_rx_scale_iq; + input [15:0] scale_i; + input [15:0] scale_q; + + write_cfg_register(161, {scale_i,scale_q}); + endtask // set_rx_scale_iq + + // Set RX MUX control + task set_rx_muxctrl; + input [3:0] muxctrl; + + write_cfg_register(168, muxctrl); + endtask // set_rx_muxctrl + + // Set RX CIC decim and halfband enables + task set_decim; + input hb1_ena; + input hb2_ena; + input [7:0] decim; + + write_cfg_register(162, {hb1_ena,hb2_ena,decim}); + endtask // set_decim + + +/////////////////////////////////////////////////////////////////////////////////// +// Individual tests // +/////////////////////////////////////////////////////////////////////////////////// + + task test_rx; + begin + set_impulse_len(1); + set_zero_len(999); + set_rx_muxctrl(1); + set_ddc_freq(0); + set_rx_scale_iq(1243, 1243); + set_decim(0, 1, 3); + + #100000 $finish; + end + endtask // test_rx + + +/////////////////////////////////////////////////////////////////////////////////// +// Top-level test // +/////////////////////////////////////////////////////////////////////////////////// + + // Execute tests + initial + begin + power_on(); + test_rx(); + end + +endmodule // dsp_core_tb diff --git a/usrp2/top/u2_rev3_iad/impulse.v b/usrp2/top/u2_rev3_iad/impulse.v new file mode 100644 index 000000000..7f0cdc9be --- /dev/null +++ b/usrp2/top/u2_rev3_iad/impulse.v @@ -0,0 +1,63 @@ +module impulse + (input clk, + input rst, + input ena, + + input [13:0] dc_offset_a, + input [13:0] dc_offset_b, + input [13:0] amplitude, + input [15:0] impulse_len, + input [15:0] zero_len, + + output [13:0] adc_a, + output [13:0] adc_b, + output adc_ovf_a, + output adc_ovf_b + ); + + reg [13:0] adc_a_int = 0; + reg [15:0] count; + + localparam ST_ZERO = 0; + localparam ST_HIGH = 1; + reg state; + + always @(posedge clk) + if (rst | ~ena) + begin + adc_a_int <= 0; + count <= 0; + state <= ST_ZERO; + end + else + case(state) + ST_ZERO: + if (count == zero_len) + begin + adc_a_int <= amplitude; + state <= ST_HIGH; + count <= 0; + end + else + count <= count + 1; + + ST_HIGH: + if (count == impulse_len) + begin + adc_a_int <= 0; + state <= ST_ZERO; + count <= 0; + end + else + count <= count + 1; + + endcase // case (state) + + assign adc_a = adc_a_int + dc_offset_a; + + // Ignore for now + assign adc_b = dc_offset_b; + assign adc_ovf_a = 0; + assign adc_ovf_b = 0; + +endmodule // impulse diff --git a/usrp2/top/u2_rev3_iad/wave.sh b/usrp2/top/u2_rev3_iad/wave.sh new file mode 100755 index 000000000..626f224e5 --- /dev/null +++ b/usrp2/top/u2_rev3_iad/wave.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf new file mode 100755 index 000000000..091eb2005 --- /dev/null +++ b/usrp2/top/u2plus/u2plus.ucf @@ -0,0 +1,354 @@ +NET "DAC_LOCK" LOC = "P4" ; +NET "ADC_clkout_p" LOC = "P1" ; +NET "ADC_clkout_n" LOC = "P2" ; +NET "io_rx<15>" LOC = "AD1" ; +NET "io_rx<14>" LOC = "AD2" ; +NET "io_rx<13>" LOC = "AC2" ; +NET "io_rx<12>" LOC = "AC3" ; +NET "io_rx<11>" LOC = "W7" ; +NET "io_rx<10>" LOC = "W6" ; +NET "io_rx<09>" LOC = "U9" ; +NET "io_rx<08>" LOC = "V8" ; +NET "io_rx<07>" LOC = "AB1" ; +NET "io_rx<06>" LOC = "AC1" ; +NET "io_rx<05>" LOC = "V7" ; +NET "io_rx<04>" LOC = "V6" ; +NET "io_rx<03>" LOC = "Y5" ; +NET "ADCB_2_3_p" LOC = "U7" ; +NET "ADCB_2_3_n" LOC = "U8" ; +NET "ADCB_0_1_p" LOC = "AA2" ; +NET "ADCB_0_1_n" LOC = "AA3" ; +NET "ADCA_12_13_p" LOC = "Y1" ; +NET "ADCA_12_13_n" LOC = "Y2" ; +NET "ADCA_10_11_p" LOC = "W3" ; +NET "ADCA_10_11_n" LOC = "W4" ; +NET "ADCA_8_9_p" LOC = "T7" ; +NET "ADCA_8_9_n" LOC = "U6" ; +NET "ADCA_6_7_p" LOC = "U5" ; +NET "ADCA_6_7_n" LOC = "V5" ; +NET "ADCA_4_5_p" LOC = "T10" ; +NET "ADCA_4_5_n" LOC = "T9" ; +NET "ADCA_2_3_p" LOC = "V1" ; +NET "ADCA_2_3_n" LOC = "V2" ; +NET "ADCA_0_1_p" LOC = "R8" ; +NET "ADCA_0_1_n" LOC = "R7" ; +NET "TX00_A" LOC = "P8" ; +NET "TX01_A" LOC = "P9" ; +NET "TX02_A" LOC = "R5" ; +NET "TX03_A" LOC = "R6" ; +NET "TX04_A" LOC = "P7" ; +NET "TX05_A" LOC = "P6" ; +NET "TX06_A" LOC = "T3" ; +NET "TX07_A" LOC = "T4" ; +NET "TX08_A" LOC = "R3" ; +NET "TX09_A" LOC = "R4" ; +NET "TX10_A" LOC = "R2" ; +NET "TX11_A" LOC = "N1" ; +NET "TX12_A" LOC = "N2" ; +NET "TX13_A" LOC = "N5" ; +NET "TX14_A" LOC = "N4" ; +NET "TX15_A" LOC = "M2" ; +NET "TX00_B" LOC = "M5" ; +NET "TX01_B" LOC = "M6" ; +NET "TX02_B" LOC = "M4" ; +NET "TX03_B" LOC = "M3" ; +NET "TX04_B" LOC = "M8" ; +NET "TX05_B" LOC = "M7" ; +NET "TX06_B" LOC = "L4" ; +NET "TX07_B" LOC = "L3" ; +NET "TX08_B" LOC = "K3" ; +NET "TX09_B" LOC = "K2" ; +NET "TX10_B" LOC = "K5" ; +NET "TX11_B" LOC = "K4" ; +NET "TX12_B" LOC = "M10" ; +NET "TX13_B" LOC = "M9" ; +NET "TX14_B" LOC = "J5" ; +NET "TX15_B" LOC = "J4" ; +NET "io_tx<15>" LOC = "K6" ; +NET "io_tx<14>" LOC = "L7" ; +NET "io_tx<13>" LOC = "H2" ; +NET "io_tx<12>" LOC = "H1" ; +NET "io_tx<11>" LOC = "L10" ; +NET "io_tx<10>" LOC = "L9" ; +NET "io_tx<09>" LOC = "G3" ; +NET "io_tx<08>" LOC = "F3" ; +NET "io_tx<07>" LOC = "K7" ; +NET "io_tx<06>" LOC = "J6" ; +NET "io_tx<05>" LOC = "E1" ; +NET "io_tx<04>" LOC = "F2" ; +NET "io_tx<03>" LOC = "J7" ; +NET "io_tx<02>" LOC = "H6" ; +NET "io_tx<01>" LOC = "F5" ; +NET "io_tx<00>" LOC = "G4" ; +NET "MOSI_RX_ADC" LOC = "E3" ; +NET "SCLK_RX_ADC" LOC = "F4" ; +NET "SEN_RX_ADC" LOC = "D3" ; +NET "SCLK_RX_DAC" LOC = "E4" ; +NET "SEN_RX_DAC" LOC = "K9" ; +NET "MOSI_RX_DAC" LOC = "K8" ; +NET "SCLK_RX_DB" LOC = "G6" ; +NET "MOSI_RX_DB" LOC = "H7" ; +NET "SEN_RX_DB" LOC = "B2" ; +NET "SCLK_ADC" LOC = "B1" ; +NET "MOSI_ADC" LOC = "J8" ; +NET "SEN_ADC" LOC = "J9" ; +NET "ADCB_4_5_p" LOC = "AE1" ; +NET "ADCB_4_5_n" LOC = "AE2" ; +NET "ADCB_6_7_p" LOC = "W1" ; +NET "ADCB_6_7_n" LOC = "W2" ; +NET "ADCB_8_9_p" LOC = "U3" ; +NET "ADCB_8_9_n" LOC = "V4" ; +NET "ADCB_10_11_p" LOC = "J1" ; +NET "ADCB_10_11_n" LOC = "K1" ; +NET "ADCB_12_13_p" LOC = "J3" ; +NET "ADCB_12_13_n" LOC = "J2" ; +NET "MISO_RX_DB" LOC = "H4" ; +NET "MISO_RX_ADC" LOC = "C1" ; +NET "MISO_TX_DB" LOC = "AA5" ; +NET "MISO_DAC" LOC = "Y3" ; +NET "MISO_TX_ADC" LOC = "G1" ; +NET "io_rx<02>" LOC = "R10" ; +NET "io_rx<01>" LOC = "R1" ; +NET "io_rx<00>" LOC = "M1" ; +NET "exp_user_out_p" LOC = "AF14" ; +NET "exp_user_out_n" LOC = "AE14" ; +NET "exp_time_out_p" LOC = "Y14" ; +NET "exp_time_out_n" LOC = "AA14" ; +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +NET "SEN_CLK" LOC = "AA18" ; +NET "MOSI_CLK" LOC = "W17" ; +NET "SCLK_CLK" LOC = "V17" ; +NET "CLK_STATUS" LOC = "AD22" ; +NET "CLK_FUNC" LOC = "AC21" ; +NET "clk_sel<0>" LOC = "AE21" ; +NET "clk_sel<1>" LOC = "AD21" ; +NET "clk_en<1>" LOC = "AA17" ; +NET "clk_en<0>" LOC = "Y17" ; +NET "SDA" LOC = "V16" ; +NET "SCL" LOC = "U16" ; +NET "TXD3" LOC = "AD20" ; +NET "TXD2" LOC = "AC20" ; +NET "TXD1" LOC = "AD19" ; +NET "debug<00>" LOC = "AC19" ; +NET "debug<01>" LOC = "AF20" ; +NET "debug<02>" LOC = "AE20" ; +NET "debug<03>" LOC = "AC16" ; +NET "debug<04>" LOC = "AB16" ; +NET "debug<05>" LOC = "AF19" ; +NET "debug<06>" LOC = "AE19" ; +NET "debug<07>" LOC = "V15" ; +NET "debug<08>" LOC = "U15" ; +NET "debug<09>" LOC = "AE17" ; +NET "debug<10>" LOC = "AD17" ; +NET "debug<11>" LOC = "V14" ; +NET "debug<12>" LOC = "W15" ; +NET "debug<13>" LOC = "AC15" ; +NET "debug<14>" LOC = "AD14" ; +NET "debug<15>" LOC = "AC14" ; +NET "debug_clk<1>" LOC = "AD11" ; +NET "debug<16>" LOC = "AC11" ; +NET "debug<17>" LOC = "AB12" ; +NET "debug<18>" LOC = "AC12" ; +NET "debug<19>" LOC = "V13" ; +NET "debug<20>" LOC = "W13" ; +NET "debug<21>" LOC = "AE8" ; +NET "debug<22>" LOC = "AF8" ; +NET "debug<23>" LOC = "V12" ; +NET "debug<24>" LOC = "W12" ; +NET "debug<25>" LOC = "AB9" ; +NET "debug<26>" LOC = "AC9" ; +NET "debug<27>" LOC = "AC8" ; +NET "debug<28>" LOC = "AB7" ; +NET "debug<29>" LOC = "V11" ; +NET "debug<30>" LOC = "U11" ; +NET "debug<31>" LOC = "Y10" ; +NET "debug_clk<0>" LOC = "AA10" ; +NET "SEN_DAC" LOC = "AE7" ; +NET "SCLK_DAC" LOC = "AF5" ; +NET "MOSI_DAC" LOC = "AE6" ; +NET "MOSI_TX_ADC" LOC = "V10" ; +NET "SEN_TX_ADC" LOC = "W10" ; +NET "SCLK_TX_ADC" LOC = "AC6" ; +NET "MOSI_TX_DAC" LOC = "AD6" ; +NET "SEN_TX_DAC" LOC = "AE4" ; +NET "SCLK_TX_DAC" LOC = "AF4" ; +NET "SCLK_TX_DB" LOC = "AE3" ; +NET "MOSI_TX_DB" LOC = "AF3" ; +NET "SEN_TX_DB" LOC = "W9" ; +NET "RXD3" LOC = "AF17" ; +NET "RXD2" LOC = "AF15" ; +NET "RXD1" LOC = "AD12" ; +NET "MISO_CLK" LOC = "AC10" ; +NET "PPS_IN" LOC = "AB6" ; +NET "PPS2_IN" LOC = "AA20" ; +NET "ser_rx_clk" LOC = "P18" ; +NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +NET "CLK_TO_MAC" LOC = "P26" ; +NET "GMII_TX_CLK" LOC = "P25" ; +NET "GMII_RX_CLK" LOC = "P21" ; +NET "ETH_LED" LOC = "H20" ; +NET "GMII_TXD7" LOC = "G21" ; +NET "GMII_TXD6" LOC = "C26" ; +NET "GMII_TXD5" LOC = "C25" ; +NET "GMII_TXD4" LOC = "J21" ; +NET "GMII_TXD3" LOC = "H21" ; +NET "GMII_TXD2" LOC = "D25" ; +NET "GMII_TXD1" LOC = "D24" ; +NET "GMII_TXD0" LOC = "E26" ; +NET "GMII_TX_EN" LOC = "D26" ; +NET "GMII_TX_ER" LOC = "J19" ; +NET "GMII_GTX_CLK" LOC = "J20" ; +NET "GMII_RXD7" LOC = "G22" ; +NET "GMII_RXD6" LOC = "K19" ; +NET "GMII_RXD5" LOC = "K18" ; +NET "GMII_RXD4" LOC = "E24" ; +NET "GMII_RXD3" LOC = "F23" ; +NET "GMII_RXD2" LOC = "L18" ; +NET "GMII_RXD1" LOC = "L17" ; +NET "GMII_RXD0" LOC = "F25" ; +NET "GMII_RX_DV" LOC = "F24" ; +NET "GMII_RX_ER" LOC = "L20" ; +NET "GMII_CRS" LOC = "K20" ; +NET "GMII_COL" LOC = "G23" ; +NET "PHY_INTn" LOC = "L22" ; +NET "MDIO" LOC = "K21" ; +NET "MDC" LOC = "J23" ; +NET "PHY_RESET" LOC = "J22" ; +NET "exp_time_in_p" LOC = "N18" ; +NET "exp_time_in_n" LOC = "N17" ; +NET "exp_user_in_p" LOC = "L24" ; +NET "exp_user_in_n" LOC = "M23" ; +NET "ser_prbsen" LOC = "U23" ; +NET "ser_loopen" LOC = "R19" ; +NET "ser_enable" LOC = "R20" ; +NET "ser_t<15>" LOC = "V23" ; +NET "ser_t<14>" LOC = "U22" ; +NET "ser_t<13>" LOC = "V24" ; +NET "ser_t<12>" LOC = "V25" ; +NET "ser_t<11>" LOC = "W23" ; +NET "ser_t<10>" LOC = "V22" ; +NET "ser_t<09>" LOC = "T18" ; +NET "ser_t<08>" LOC = "T17" ; +NET "ser_t<07>" LOC = "Y24" ; +NET "ser_t<06>" LOC = "Y25" ; +NET "ser_t<05>" LOC = "U21" ; +NET "ser_t<04>" LOC = "T20" ; +NET "ser_t<03>" LOC = "Y22" ; +NET "ser_t<02>" LOC = "Y23" ; +NET "ser_t<01>" LOC = "U19" ; +NET "ser_t<00>" LOC = "U18" ; +NET "ser_tkmsb" LOC = "AA24" ; +NET "ser_tklsb" LOC = "AA25" ; +NET "ser_r<15>" LOC = "V21" ; +NET "ser_r<14>" LOC = "U20" ; +NET "ser_r<13>" LOC = "AA22" ; +NET "ser_r<12>" LOC = "AA23" ; +NET "ser_r<11>" LOC = "V18" ; +NET "ser_r<10>" LOC = "V19" ; +NET "ser_r<09>" LOC = "AB23" ; +NET "ser_r<08>" LOC = "AC26" ; +NET "ser_r<07>" LOC = "AB26" ; +NET "ser_r<06>" LOC = "AD26" ; +NET "ser_r<05>" LOC = "AC25" ; +NET "ser_r<04>" LOC = "W20" ; +NET "ser_r<03>" LOC = "W21" ; +NET "ser_r<02>" LOC = "AC23" ; +NET "ser_r<01>" LOC = "AC24" ; +NET "ser_r<00>" LOC = "AE26" ; +NET "ser_rkmsb" LOC = "AD25" ; +NET "ser_rklsb" LOC = "Y20" ; +NET "ser_rx_en" LOC = "Y21" ; +NET "FPGA_RESET" LOC = "K24" ; +NET "RAM_D<17>" LOC = "F7" ; +NET "RAM_D<16>" LOC = "E7" ; +NET "RAM_D<15>" LOC = "G9" ; +NET "RAM_D<14>" LOC = "H9" ; +NET "RAM_D<13>" LOC = "G10" ; +NET "RAM_D<12>" LOC = "H10" ; +NET "RAM_D<11>" LOC = "A4" ; +NET "RAM_D<10>" LOC = "B4" ; +NET "RAM_D<09>" LOC = "C5" ; +NET "RAM_D<08>" LOC = "D6" ; +NET "RAM_D<07>" LOC = "J11" ; +NET "RAM_D<06>" LOC = "K11" ; +NET "RAM_D<05>" LOC = "B7" ; +NET "RAM_D<04>" LOC = "C7" ; +NET "RAM_D<03>" LOC = "B6" ; +NET "RAM_D<02>" LOC = "C6" ; +NET "RAM_D<01>" LOC = "C8" ; +NET "RAM_D<00>" LOC = "D8" ; +NET "RAM_ZZ" LOC = "J12" ; +NET "RAM_BWn<3>" LOC = "D9" ; +NET "RAM_BWn<2>" LOC = "A9" ; +NET "RAM_BWn<1>" LOC = "B9" ; +NET "RAM_BWn<0>" LOC = "G12" ; +NET "RAM_LDn" LOC = "H12" ; +NET "RAM_OEn" LOC = "C10" ; +NET "RAM_WEn" LOC = "D10" ; +NET "RAM_CLK" LOC = "A10" ; +NET "RAM_CENn" LOC = "B10" ; +NET "RAM_A<00>" LOC = "C11" ; +NET "RAM_A<01>" LOC = "E12" ; +NET "RAM_A<02>" LOC = "F12" ; +NET "RAM_A<03>" LOC = "D13" ; +NET "RAM_A<04>" LOC = "C12" ; +NET "RAM_A<05>" LOC = "A12" ; +NET "RAM_A<06>" LOC = "B12" ; +NET "RAM_A<07>" LOC = "E14" ; +NET "RAM_A<08>" LOC = "F14" ; +NET "RAM_A<09>" LOC = "B15" ; +NET "RAM_A<10>" LOC = "A15" ; +NET "RAM_A<11>" LOC = "D16" ; +NET "RAM_A<12>" LOC = "C15" ; +NET "RAM_A<13>" LOC = "D17" ; +NET "RAM_A<14>" LOC = "C16" ; +NET "RAM_A<15>" LOC = "F15" ; +NET "RAM_A<16>" LOC = "C17" ; +NET "RAM_A<17>" LOC = "B17" ; +NET "RAM_A<18>" LOC = "B18" ; +NET "RAM_A<19>" LOC = "A18" ; +NET "RAM_A<20>" LOC = "D18" ; +NET "RAM_D<35>" LOC = "K16" ; +NET "RAM_D<34>" LOC = "D20" ; +NET "RAM_D<33>" LOC = "C20" ; +NET "RAM_D<32>" LOC = "E21" ; +NET "RAM_D<31>" LOC = "D21" ; +NET "RAM_D<30>" LOC = "C21" ; +NET "RAM_D<29>" LOC = "B21" ; +NET "RAM_D<28>" LOC = "H17" ; +NET "RAM_D<27>" LOC = "G17" ; +NET "RAM_D<26>" LOC = "B23" ; +NET "RAM_D<25>" LOC = "A22" ; +NET "RAM_D<24>" LOC = "D23" ; +NET "RAM_D<23>" LOC = "C23" ; +NET "RAM_D<22>" LOC = "D22" ; +NET "RAM_D<21>" LOC = "C22" ; +NET "RAM_D<20>" LOC = "F19" ; +NET "RAM_D<19>" LOC = "G20" ; +NET "RAM_D<18>" LOC = "F20" ; +#NET "unnamed_net20" LOC = "V20" ; # SUSPEND +NET "PROG_B" LOC = "A2" ; +NET "PUDC_B" LOC = "G8" ; +NET "DONE" LOC = "AB21" ; +NET "flash_miso" LOC = "AF24" ; +NET "flash_clk" LOC = "AE24" ; +NET "INIT_B" LOC = "AA15" ; +NET "flash_mosi" LOC = "AB15" ; +#NET "unnamed_net19" LOC = "AE9" ; # VS1 +#NET "unnamed_net18" LOC = "AF9" ; # VS0 +#NET "unnamed_net17" LOC = "AA12" ; # VS2 +#NET "unnamed_net16" LOC = "Y7" ; # M2 +NET "flash_cs" LOC = "AA7" ; +#NET "unnamed_net15" LOC = "AC4" ; # M1 +#NET "unnamed_net14" LOC = "AD4" ; # M0 +#NET "unnamed_net13" LOC = "D4" ; # TMS +#NET "unnamed_net12" LOC = "E23" ; # TDO +#NET "unnamed_net11" LOC = "G7" ; # TDI +#NET "unnamed_net10" LOC = "A25" ; # TCK + diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v new file mode 100644 index 000000000..e95445867 --- /dev/null +++ b/usrp2/top/u2plus/u2plus.v @@ -0,0 +1,377 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2plus + ( + // Misc, debug + output [4:0] leds, // LED4 is shared w/INIT_B + input [3:0] dipsw, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + input clk_to_mac, + output eth_led, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input pps_in, + input POR, + + // AD9510 SPI + output sclk, + output sen_clk, + output sdi, + input sdo, + + // TX side SPI -- tx_db, tx_adc, tx_dac, 9777 + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output mosi_tx, + input miso_dac, + input miso_tx_db, + input miso_tx_adc, + output sclk_tx, + + // RX side SPI + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + + // SPI Flash + output flash_cs, + output flash_clk, + output flash_mosi, + input flash_miso + ); + + // FPGA-specific pins connections + wire aux_clk = PHY_CLK; + + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge aux_clk) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + wire clk_muxed = clock_ready ? clk_fpga : aux_clk; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_muxed), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = ~leds_int; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_core u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .PHY_CLK (PHY_CLK), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + //.uart_rx_i (uart_rx_i), + .uart_rx_i (), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2plus -- cgit v1.2.3 From 023e573868c55a08b4b097ca2451945dbe546cec Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 8 Feb 2010 15:05:30 -0800 Subject: ignore emacs cruft --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..74c36c862 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +*~ +\#*\# -- cgit v1.2.3 From 904b35c689d38694913606c569a9d324533ff765 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 23 Feb 2010 19:56:09 -0800 Subject: proper initialization of the ram --- .gitignore | 1 + usrp2/control_lib/ram_2port.v | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 74c36c862..b275f0e49 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ *~ \#*\# +a.out diff --git a/usrp2/control_lib/ram_2port.v b/usrp2/control_lib/ram_2port.v index 6c8332b9c..3716a7c8a 100644 --- a/usrp2/control_lib/ram_2port.v +++ b/usrp2/control_lib/ram_2port.v @@ -21,7 +21,7 @@ module ram_2port integer i; initial for(i=0;i<(1<