From 0e3912767266473e08386c910954450d16d33664 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Wed, 27 Nov 2013 11:53:38 -0800 Subject: Squashed commit uhd/cleanup. --- CHANGELOG | 343 ++++++++++++ README.md | 71 +++ README.txt | 19 - firmware/README.md | 48 ++ firmware/README.txt | 31 -- firmware/fx2/AUTHORS | 4 - firmware/octoclock/Makefile | 16 +- firmware/octoclock/OctoClock-io.h | 70 --- firmware/octoclock/OctoClock.c | 1103 ++++++++++++++----------------------- firmware/zpu/AUTHORS | 4 - firmware/zpu/README | 16 - host/AUTHORS.txt | 40 -- host/LICENSE | 12 + host/LICENSE.txt | 12 - host/README.txt | 43 -- host/apps/omap_debug/README | 1 - host/cmake/Modules/FindUSB1.cmake | 3 +- host/docs/uhd_find_devices.1 | 3 - host/docs/uhd_images_downloader.1 | 3 - host/docs/uhd_usrp_probe.1 | 2 +- host/lib/usrp/README | 15 - images/Makefile | 16 +- images/README.md | 35 ++ images/README.txt | 25 - 24 files changed, 958 insertions(+), 977 deletions(-) create mode 100644 CHANGELOG create mode 100644 README.md delete mode 100644 README.txt create mode 100644 firmware/README.md delete mode 100644 firmware/README.txt delete mode 100644 firmware/fx2/AUTHORS delete mode 100644 firmware/octoclock/OctoClock-io.h delete mode 100644 firmware/zpu/AUTHORS delete mode 100644 firmware/zpu/README delete mode 100644 host/AUTHORS.txt create mode 100644 host/LICENSE delete mode 100644 host/LICENSE.txt delete mode 100644 host/README.txt delete mode 100644 host/apps/omap_debug/README delete mode 100644 host/lib/usrp/README create mode 100644 images/README.md delete mode 100644 images/README.txt diff --git a/CHANGELOG b/CHANGELOG new file mode 100644 index 000000000..8965ae3b4 --- /dev/null +++ b/CHANGELOG @@ -0,0 +1,343 @@ +Change Log for Releases +============================== + +## 003.005.003 + +* E110: +** Fix FPGA Makefile build typo +* UHD: +** Fixed timespec irrational rate rounding +** Multichan streamer CPU utilization + +## 003.005.002 + +* B100: +** Fix get send buffer timeout +* E1x0: +** Changes to bus timings for S issue +* USRP1: +** Restore broken EEPROM writing + + +## 003.005.001 + +* Misc: +** Fixes to images downloader +** Fixes to C++ net burner +** Added sleep(1) to query_gpsdo_sensors +* OSX: +** Fix for socket send code newer OS versions +* Changes from 3.4.5 + +## 003.005.000 + +* B100: +** Added timed commands feature +** Incremented FPGA compat number to 11.1 +** Incremented firmware compat number to 3 +* E1x0: +** Added timed commands feature +** Incremented FPGA compat number to 11.1 +* USRP2/N2x0: +** Alternative stream destination on TX +** Incremented FPGA compat number to 10 +* N2x0: +** Implemented timed-commands feature +** Implemented fast-commands feature +* SBX/WBX +** Tune with phase sync using timed-commands +* RFX series +** Added calibration utilities support +* General: +** SSE2 conversions for sc8 RX samples +** Added multi-threading to packet converters +** Added automatic images fetcher application + +## 003.004.005 + +* XCVR2450: +** Added XCVR2450 rev2 support +* WBX: +** Added WBX rev4 support +* Misc: +** Fix to rx_samples_to_udp byte count +** stream command enums easy on SWIG + +## 003.004.004 + +* Gen2 +** Fix RX and TX DSP scalar adjustments +* B100/E1x0 +** Fixed RX ADC IQ inversion swap +** Incremented FPGA compat number to 9.4 + +## 003.004.003 + +* USRP2/N2x0: +** Net burner parser fix (windows) +* XCVR2450: +** Fix to disable automatic LO offset on TX +* N2x0: +** Deal with misc exceptions in net burner +* E1x0: +** Changes to add reliability to bus state machine +* USRP1: +** Shutoff the DAC on transmit EOB flags +** Revert 1st nyquist zone DAC calculation + +## 003.004.002 + +* USRP2/N2x0: +** Card and net burner language fixes +** Net burner python v3 code fix +** Net burner IPv6 interface fix +* E1x0: +** Fix for FPGA timing issue with GPMC input +** Incremented FPGA compat number to 9.2 +* B100: +** Fix USB wrapper/buffer release race condition +* USRP1: +** Fix DAC calculation for tune out of 1st nyquist zone +* General: +** Fix for recv packet handler time error check +** SIMD conversion routines priority over table look-up +** Fix undefined GCC float conversion behaviour for sc8 + +## 003.004.001 + +* USRP2/N2x0: +** Filter out invalid broadcast replies +** Incremented FPGA compat number to 9.1 +* E1x0: +** Incremented FPGA compat number to 9.1 +* B100: +** FPGA fixes for USB slave FIFO interface +** Incremented FPGA compat number to 9.3 +* USRP1: +** Stop thread in deconstructor for race condition +** Fixed DBSRX + USRP1 i2c lockup condition +* Gen2: +** Fix for unintentional clear in deprecated recv() call +** Fix RX DC offset call to handle negative values +* FreeBSD: +** Fixed network relay example compilation + +## 003.004.000 + +* USRP2/N2x0: +** 50 Msps RX/TX with sc8 mode over the wire +* B100: +** 16 Msps RX/TX with sc8 mode over the wire +* SBX/WBX: +** Added self-calibration utilities +* Gen2: +** Control RX/TX DC offset correction via API +** Control RX/TX IQ balance correction via API +** Incremented FPGA compat number to 9 +* USRP1: +** Support 16Msps RX with sc8 mode over the wire +** Control RX DC offset correction via API +* Misc: +** Multiple streamers/heterogeneous rates +** Alternative host and wire data types +** Added API calls for DC offset correction +** Added API calls for IQ balance correction + +## Release 003.003.002 + +* N2x0: +** Fixed TX daughterboard clocking mode +* B100: +** Tweaks for ordering of FPGA resets +* Misc: +** Device adder can parse empty values +** Updated syntax in udev rules file +** Corrections to images documentation +** Performance tweak for tx_waveforms example +** Handle EINTR on select() w/ udp transport +** Minor fixes for compiling on FreeBSD + +## Release 003.003.001 + +* B100/E1x0: +** Fixed VCO bounds checking on flexible clocking +* B100: +** Fixed discovery throwing when device claimed + +## Release 003.003.000 + +* USRP2/N2x0: +** Incremented firmware image compat number to 11.0 +** Re-implement internal GPSDO UART control +* E1x0: +** New GPMC/FPGA bus implementation +** Incremented FPGA compat number to 6 +** Incremented module compat number to 3 +** Added support for E110 +** Added support for E100r4 +* B100: +** Added support for B100 +* USRP1: +** Re-implement LibUSB data transport +* Misc: +** Normalise time_spec for negative fractional seconds +* Gen2: +** Fix DSP rate selection clipping for very low rates + +## Release 003.002.004 + +* USRP2/N2x0: +** Resize all socket buffers (multi-channel) +* N2x0: +** Gracefully handle missing GPSDO +* USRP1: +** Fix bug with order of deconstructors +** Fix zero length send padding on commit +* XCVR2450: +** Fix LO locking at marginal frequencies +* WBX: +** Fix TX gain readback value on v3 board +* Gen2: +** Fix bounds checking on stream num samps +** Fix error using PPS_NEG in clock config + +## Release 003.002.003 + +* USRP2/N2x0: +** Fix uninitialized variable for multi-board case +** Fix deconstructor throwing on device disconnect +** Incremented FPGA image compat number to 7.3 +* TVRX: +** Populated sensors property (fixed error in init) +* FPGA (gen2): +** Adjust RX DC offset correction time constant +** Restore calibration path in RX/TX frontend +* Misc: +** MB EEPROM burner workaround for compiler bugs +** Clip the reported tune range to the dboard bandwidth +** Preserve bands when calculating overall tune range + +## Release 003.002.002 + +* USRP2/N2x0: +** Always resize socket send buffer to SRAM size +** Incremented FPGA image compat number to 7.2 +** Incremented firmware image compat number to 10.4 +* N2x0: +** GPSDO control tweak for some Firefly devices +** Fix for erasure logic in rare bricking cases +* E100: +** Fix RX run state for GPIOs controlled by ATR +* USRP1: +** Fix for multi-channel streaming +** Fix to support 0 RX or 0 TX DSPs +* SBX: +** Corrected lower limit on frequency range +* FPGA (gen2): +** Reset CIC decimator on start of burst +* Misc: +** Fix send to return zero on empty packets +** Perform version check on liborc + +## Release 003.002.001 + +* USRP2/N-Series: +** Firmware fix to shutoff streaming when socket unreachable +** Incremented firmware image compat number to 10.3 + +## Release 003.002.000 + +* USRP2/N-Series: +** Incremented FPGA image compat number to 7.1 +** Incremented firmware image compat number to 10.2 +** Removed mimo_mode device addr argument +** Support for rev4 N2XX motherboards +* USRP-E100: +** Removed the need for clock recovery +** Incremented FPGA image compat number to 5 +** Incremented kernel module compat number to 2 +** Added support for dual receive DSPs +** Async messages independent from RX path +* WBX: +** Support for rev3 daughterboards +* DBSRX2: +** Rounding fix for LO tuning error +* Packet handler: +** Overall performance improvements +** Timestamps for packet fragments +** Overflow message on dropped packets +* Conversion: +** Optional liborc conversion support +** SSE2 conversion alignment performance +** SSE2 conversion for complex doubles +* Windows: +** Performance improvements for UDP send +* Misc: +** Code reorganization with property tree +** Calibration support in gen2 FPGAs + +## Release 003.001.002 + +* N-Series: +** Fix UART communication for GPSDO +* XCVR2450: +** Fix for descontructor throwing on hardware disconnect + +## Release 003.001.001 + +* USRP1: +** Fixed lock up in logging facility under MSVC +* USRP2/N-Series: +** Handle exceptions thrown in device locker loop +** Connected internal GPSDO PPS signal in FPGA +* WBX +** Keep mixers on between bursts to maintain phase offsets + +## Release 003.001.000 + +* USRP2/N-Series: +** Incremented FPGA compat number to 6 +** Incremented firmware compat number to 10 +** Created all-in-one bootloader for N-series +** Lock open devices per process +** USRP N-Series internal GPSDO Support +** Discovery works with out-of-date images +** Net and card burner: python 3.0 support +** Net burner: tkinter + windows thread fix +** Card burner: device selection validation +* USRP-E100: +** Incremented FPGA compat number to 4 +** FPGA VRT packet framer correct length +** Fix auxiliary ADC read back for AD9862 +** Sync TX and RX daughterbord clocks +** Fix daughterboard clock rates after re-clock event +* USRP1: +** Fix TX under remainder conditions +** Fixed RX multi-channel mapping +* Daughterboards: +** Added support for TVRX2 daughterboard +** Added support for SBX daughterboard +** Added support for WBX granddaughterboards +** Application notes for sensors and IF +* Windows: +** MinGW and Cygwin support (thanks Don) +** Fix calling convention on libusb callbacks +* Misc: +** Added logging and messaging facilities +** Deprecated API in utils/warning.hpp +** Fixed race condition in device discovery/factory + +## Release 003.000.001 + +* RFX400: fix for transmit capability +* USRP1: fix for axillary ADC read +* Windows: statically link libusb +* Windows: install dll into runtime path +* Linux: automatically set LIB_SUFFIX on rh-64 systems +* USRP-E100: fix - set FPGA tick rate on re-clock event +* build: various work on build system +* build: include FPGA and firmware images in installers + +## Release 003.000.000 + +Initial (formal) release, no changes to mention. diff --git a/README.md b/README.md new file mode 100644 index 000000000..8d78c4f10 --- /dev/null +++ b/README.md @@ -0,0 +1,71 @@ +USRP Hardware Driver (UHDâ„¢) Software +======================================== + +Welcome to the UHDâ„¢ software distribution! UHD is the free & open-source +software driver and API for the Universal Software Radio Peripheral (USRPâ„¢) SDR +platform, created and sold by Ettus Research, LLC. + +UHD supports all Ettus Research USRPâ„¢ hardware, including all motherboards and +daughterboards, and the combinations thereof. + +## Documentation + +The [UHD Homepage](http://code.ettus.com/redmine/ettus/projects/uhd/wiki), +through which you can find installation instructions, documentation, and further +information, is the primary source of UHD documentation and "Getting +Started"-type guides. + +For technical documentation related to USRPâ„¢ hardware or UHD system +design, check out the [UHD Manual](http://files.ettus.com/uhd_docs/manual/html/). + +If you are looking for API documentation, check out the following resources: + +* [Doxygen](http://files.ettus.com/uhd_docs/doxygen/html/index.html) +* [Coding to the API](http://files.ettus.com/uhd_docs/manual/html/coding.html) +* [Device Streaming](http://files.ettus.com/uhd_docs/manual/html/stream.html) + +Additionally, be sure to check out the Ettus Research +[FAQ](http://www.ettus.com/kb/detail/frequently-asked-questions), and the +[Knowledge Base](http://www.ettus.com/kb) for useful application notes and +tutorials. + +## OS Support + +UHD is primarily developed on Linux, but we also test and support the following +operating systems. + +* Linux (any distribution) +* Mac OSX (PPC and Intel) +* Windows 7/Vista/XP/2000 + +## Applications + +UHD can be used to build stand-alone applications with USRPâ„¢ hardware, or with +third-party applications. Some common toolkits / frameworks are: + +* [GNURadio](http://code.ettus.com/redmine/ettus/projects/uhd/wiki/GNU_Radio_UHD) +* [LabVIEW](http://joule.ni.com/nidu/cds/view/p/id/2679/lang/en) +* [Simulink](http://www.mathworks.com/discovery/sdr/usrp.html) +* [OpenBTS](http://wush.net/trac/rangepublic/wiki/BuildInstallRun) +* [Iris](http://www.softwareradiosystems.com/redmine/projects/iris/wiki) +* [Redhawk](https://github.com/redhawksdr) +* [Amarisoft LTE eNodeB](http://www.amarisoft.com/?p=amarilte) + +## Directories + +__host/__ + +The source code for the user-space driver. + +__firmware/__ + +The source code for all microprocessors in USRP hardware. + +__fpga/__ + +The source code for the UHD FPGA images. + +__images/__ + +This contains the package builder for FPGA and firmware images. + diff --git a/README.txt b/README.txt deleted file mode 100644 index 64066d522..000000000 --- a/README.txt +++ /dev/null @@ -1,19 +0,0 @@ -######################################################################## -## Welcome to the USRP source code tree -######################################################################## - -host/ - - Description: source code for user-space driver - -firmware/ - - Description: source code for various micro processors - -fpga/ - - Description: source code for FPGA designs - -images/ - - Description: package builder for FPGA and firmware images diff --git a/firmware/README.md b/firmware/README.md new file mode 100644 index 000000000..08340603d --- /dev/null +++ b/firmware/README.md @@ -0,0 +1,48 @@ +Firmware for USRP Devices +======================================================== + +## fx2/ + +__Description:__ This is the firmware for the FX2 USB PHY. + +__Devices:__ USRP1 and B100 devices. + +__Tools:__ sdcc, cmake + +__Build Instructions:__ + +1. mkdir `` +2. cd `` +3. cmake `` +4. make + +## octoclock/ + +__Description:__ Firmware for the Octoclock device. + +__Devices:__ Octoclock. + +__Tools:__ avrtools, cmake + +__Build Instructions:__ Run `make` from the Octoclock source directory. + +## zpu/ + +__Description:__ Firmware for the soft CPUs in the UHD FPGA images. + +__Devices:__ USRP2 and N-Series devices. + +__Tools:__ zpu-gcc, cmake + +This code requires the gcc-zpu tool-chain which can be found here: + +http://opensource.zylin.com/zpudownload.html + +zpu-elf-gcc should be in your `$PATH` + +__Build Instructions:__ + +1. mkdir `` +2. cd `` +3. cmake `` +4. make diff --git a/firmware/README.txt b/firmware/README.txt deleted file mode 100644 index 1c233de1d..000000000 --- a/firmware/README.txt +++ /dev/null @@ -1,31 +0,0 @@ -######################################################################## -# Firmware for USRP devices -######################################################################## - -fx2/ - - Description: firmware for FX2 device - - Devices: USRP1 and B100 - - Tools: sdcc, cmake - - Build Instructions: - 1) mkdir - 2) cd - 3) cmake - 4) make - -zpu/ - - Description: firmware for soft CPU in FPGA - - Devices: USRP2 and N Series - - Tools: zpu-gcc, cmake - - Build Instructions: - 1) mkdir - 2) cd - 3) cmake - 4) make diff --git a/firmware/fx2/AUTHORS b/firmware/fx2/AUTHORS deleted file mode 100644 index c9cd35778..000000000 --- a/firmware/fx2/AUTHORS +++ /dev/null @@ -1,4 +0,0 @@ -Eric Blossom -Josh Blum -Thomas Tsou -Nick Foster diff --git a/firmware/octoclock/Makefile b/firmware/octoclock/Makefile index 517dee4c5..acf26f617 100644 --- a/firmware/octoclock/Makefile +++ b/firmware/octoclock/Makefile @@ -1,6 +1,19 @@ # # Copyright 2009 Ettus Research LLC # +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# ################################################## # Compiler @@ -19,7 +32,6 @@ CFLAGS = -std=gnu99 -O2 ################################################## # Files ################################################## -HDRS = OctoClock-io.h SRCS = OctoClock.c TARGET = octoclock_fw @@ -52,5 +64,5 @@ $(TARGET).hex: $(TARGET).elf $(TARGET).elf: $(SRCS:.c=.o) $(CC) -mmcu=$(MMCU) $^ -o $@ -%.o: %.c $(HDRS) Makefile +%.o: %.c Makefile $(CC) -mmcu=$(MMCU) -c $< -o $@ $(CFLAGS) diff --git a/firmware/octoclock/OctoClock-io.h b/firmware/octoclock/OctoClock-io.h deleted file mode 100644 index 88cd1499b..000000000 --- a/firmware/octoclock/OctoClock-io.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2009 Ettus Research LLC - */ - -#ifndef IO_H -#define IO_H - -#include -#include - - -typedef int8_t i8; -typedef int16_t i16; -typedef int32_t i32; -typedef int64_t i64; - - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -typedef uint64_t u64; - - -typedef float f32; -typedef double f64; -typedef long double f128; - -typedef int error_indicator; /* A type for functions, usually... */ -typedef unsigned int boolean; /* "natural" type */ - -typedef char c8; /* 8-bit character */ -typedef unsigned char uc8; /* 8-bit character, unsigned*/ -/* it is sometimes useful to*/ -/* make the distinction*/ - -#ifdef FALSE -#undef FALSE -#endif -#define FALSE (0) - -#ifdef TRUE -#undef TRUE -#endif -#define TRUE (!FALSE) - -#define is :{ -#define esac break;} - - -// This other crap can be deleted, below, between the #if 0 and #endif inclusive - -#if 0 - -#define IO_PX(port, pin) ((uint8_t)(((port - 'A') << 4) + pin)) -#define IO_PA(pin) IO_PX('A', pin) -#define IO_PB(pin) IO_PX('B', pin) -#define IO_PC(pin) IO_PX('C', pin) -#define IO_PD(pin) IO_PX('D', pin) - -typedef const uint8_t io_pin_t; - -void io_output_pin(io_pin_t pin); -void io_input_pin(io_pin_t pin); -void io_set_pin(io_pin_t pin); -void io_clear_pin(io_pin_t pin); -bool io_test_pin(io_pin_t pin); - -#endif //if 0 - -#endif /* IO_H */ diff --git a/firmware/octoclock/OctoClock.c b/firmware/octoclock/OctoClock.c index d81a93fc3..f73c30885 100644 --- a/firmware/octoclock/OctoClock.c +++ b/firmware/octoclock/OctoClock.c @@ -1,844 +1,589 @@ /* - * OctoClock.c - * - * V1.00 -- May 2013 - * - * - * V1.03 -- Correct the switch to be UP for Internal and DOWN for External - * This means that the bat handle "points at" (sort of) the lower-left LED, which - * is the "STATUS" LED, which gets lit up when the external 10 MHz is present - * The "10 MHz Signal Detect" code accepts a very wide range of "10 MHz" signals - * 23 April 2013 - * + * Copyright 2013 Ettus Research LLC * - * V1.02 -- Make LEDs consistent with Chassis - Top LED is INTERNAL; middle is EXTERNAL; bottom is STATUS + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. * - * STATUS is ON if the 10 MHz external input is present. 19 April 2013 + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Welcome to the firmware code for the USRP Octoclock accessory product! * - * V1.01: Modify TI chip initialization to be in differentail mode - * which allows 10 MHz input down to 0.1 Volts according to the datasheet. + * Notes regarding this firmware: + * NOT in M103 compatibility mode + * no WDT + * CKOPT full rail-to-rail + * xtal osc + * 16K CK (16K clock cycles) + * additional delay 65ms for Crystal Oscillator + * slowly rising power * + * These settings are very conservative. If a lower power oscillator is + * required, change CKOPT to '1' (UNPROGRAMMED). * - * New Version that supports CLOCK board Version 1.0 + * M103C = [ ] + * WDTON = [ ] + * OCDEN = [ ] + * JTAGEN = [X] + * SPIEN = [X] + * EESAVE = [ ] + * BOOTSZ = 4096W_F000 + * BOOTRST = [ ] + * CKOPT = [X] + * BODLEVEL = 2V7 + * BODEN = [ ] + * SUT_CKSEL = EXTHIFXTALRES_16KCK_64MS * - * Author: Michael@Cheponis.Com with code borrowed liberally from - * previous AVR projects + * EXTENDED = 0xFF (valid) + * HIGH = 0x89 (valid) + * LOW = 0xFF (valid) * */ -/* - * Copyright 2013 Ettus Research LLC - */ - - - - - - -/* CLKSEL0 = 1 SUT1..0 is 11 CKOPT = 0 CKSEL3..1 is 111 => big output swing, long time to start up */ -/* - -NOT in M103 compatibility mode, no WDT, CKOPT full rail-to-rail xtal osc, 16K CK (16K clock cycles), -additional delay 65ms for Crystal Oscillator, slowly rising power - -Very conservative settings; if lower power osc required, change CKOPT to '1' (UNPROGRAMMED) or, if you will, -CKOPT = [ ] - - - -M103C = [ ] -WDTON = [ ] -OCDEN = [ ] -JTAGEN = [X] -SPIEN = [X] -EESAVE = [ ] -BOOTSZ = 4096W_F000 -BOOTRST = [ ] -CKOPT = [X] -BODLEVEL = 2V7 -BODEN = [ ] -SUT_CKSEL = EXTHIFXTALRES_16KCK_64MS - -EXTENDED = 0xFF (valid) -HIGH = 0x89 (valid) -LOW = 0xFF (valid) - - -*/ - -// No interrupts are required - -#include "OctoClock-io.h" - +#include +#include #include #include - #ifdef On #undef On #endif #ifdef Off -#undef OFf +#undef Off #endif -#define Off (0) -#define On (!Off) - +#define Off (0) +#define On (!Off) -// Important for the Serial Port, not used at the moment -#define FOSC (7372800) -#define BAUD (115200) +#ifdef FALSE +#undef FALSE +#endif -#define MYUBRR FOSC/16/BAUD-1 +#ifdef TRUE +#undef TRUE +#endif +#define FALSE (0) +#define TRUE (!FALSE) -#define wait() for(u16 u=14000; u; u--) asm("nop"); +// Important for the Serial Port, not used at the moment +#define FOSC (7372800) +#define BAUD (115200) +#define MYUBRR FOSC/16/BAUD-1 -enum LEDs {Top,Middle,Bottom}; // Top is 0, Mid is 1, and Bottom is 2 +#define wait() for(uint16_t u=14000; u; u--) asm("nop"); -void -led(enum LEDs which, int turn_it_on){ - - u8 LED = 0x20 << which; // selects the proper bit - - if(turn_it_on) - PORTC |= LED; - else - PORTC &= ~LED; - -} +#define CLK (PA0) // Shift by 0 bits +#define CE_ (PA1) // Is really the "Chip Disable" signal, as Hi disables SPI +#define MOSI (PA2) +#define MISO (PA3) +#define PD_ (PA4) +#define SYNC_ (PA5) +// Top is 0, Mid is 1, and Bottom is 2 +enum LEDs {Top, Middle, Bottom}; enum TI_Input_10_MHz {Primary_GPS, Secondary_Ext}; -void setup_TI_CDCE18005(enum TI_Input_10_MHz); - - +enum Levels {Lo, Hi}; +void led(enum LEDs which, int turn_it_on) { -/***************************************************************************************** + // selects the proper bit + uint8_t LED = 0x20 << which; - SPI routines + if(turn_it_on) + PORTC |= LED; + else + PORTC &= ~LED; +} -******************************************************************************************/ +/******************************************************************************* +* SPI routines +*******************************************************************************/ +/* All macros evaluate to compile-time constants */ -/* All macros evaluate to compile-time constants */ - -/* *** helper macros * * */ - /* turn a numeric literal into a hex constant - (avoids problems with leading zeros) - 8-bit constants max value 0x11111111, always fits in unsigned long + * (avoids problems with leading zeros) + * 8-bit constants max value 0x11111111, always fits in unsigned long */ - #define HEX__(n) 0x##n##LU - +#define HEX__(n) 0x##n##LU + /* 8-bit conversion function */ - #define B8__(x) ((x&0x0000000FLU)?1:0) \ - +((x&0x000000F0LU)?2:0) \ - +((x&0x00000F00LU)?4:0) \ - +((x&0x0000F000LU)?8:0) \ - +((x&0x000F0000LU)?16:0) \ - +((x&0x00F00000LU)?32:0) \ - +((x&0x0F000000LU)?64:0) \ - +((x&0xF0000000LU)?128:0) - -// Damn, that is SERIOUS magic ... ;-) Yes, I know how it works -// but it's pretty cool.... - - -/* *** user macros *** */ - -/* for upto 8-bit binary constants */ - #define Bits_8(d) ((unsigned char)B8__(HEX__(d))) - -/* for upto 16-bit binary constants, MSB first */ - #define Bits_16(dmsb,dlsb) (((unsigned short)Bits_8(dmsb)<<8) \ - + Bits_8(dlsb)) - -/* for upto 32-bit binary constants, MSB first */ - #define Bits_32(dmsb,db2,db3,dlsb) (((unsigned long)Bits_8(dmsb)<<24) \ - + ((unsigned long)Bits_8(db2)<<16) \ - + ((unsigned long)Bits_8(db3)<<8) \ - + Bits_8(dlsb)) - +#define B8__(x) ((x&0x0000000FLU)?1:0) \ + +((x&0x000000F0LU)?2:0) \ + +((x&0x00000F00LU)?4:0) \ + +((x&0x0000F000LU)?8:0) \ + +((x&0x000F0000LU)?16:0) \ + +((x&0x00F00000LU)?32:0) \ + +((x&0x0F000000LU)?64:0) \ + +((x&0xF0000000LU)?128:0) + +/* for up to 8-bit binary constants */ +#define Bits_8(d) ((unsigned char)B8__(HEX__(d))) + +/* for up to 16-bit binary constants, MSB first */ +#define Bits_16(dmsb,dlsb) (((unsigned short)Bits_8(dmsb)<<8) \ + + Bits_8(dlsb)) + +/* for up to 32-bit binary constants, MSB first */ +#define Bits_32(dmsb,db2,db3,dlsb) (((unsigned long)Bits_8(dmsb)<<24) \ + + ((unsigned long)Bits_8(db2)<<16) \ + + ((unsigned long)Bits_8(db3)<<8) \ + + Bits_8(dlsb)) + /* Sample usage: - Bits_8(01010101) = 85 - Bits_16(10101010,01010101) = 43605 - Bits_32(10000000,11111111,10101010,01010101) = 2164238933 + * Bits_8(01010101) = 85 + * Bits_16(10101010,01010101) = 43605 + * Bits_32(10000000,11111111,10101010,01010101) = 2164238933 */ - - -enum CDCE18005 {Reg0, Reg1, Reg2, Reg3, Reg4, Reg5, Reg6, Reg7, Reg8_Status_Control, - Read_Command=0xE, RAM_EEPROM_Unlock=0x1F, RAM_EEPROM_Lock=0x3f} - TI_CDCE18005; - -// Table of 32-bit constants to be written to the TI chip's registers. - -// Damn, inconsistent data sheet! Special settigns see p35 of TI datasheet +enum CDCE18005 { + Reg0, Reg1, Reg2, Reg3, Reg4, Reg5, Reg6, Reg7, + Reg8_Status_Control, + Read_Command=0xE, + RAM_EEPROM_Unlock=0x1F, + RAM_EEPROM_Lock=0x3f +} TI_CDCE18005; +// Table of 32-bit constants to be written to the TI chip's registers. These are +// from the "Special Settings" on Page 35 of the datasheet. // For the GPS's 10 MHz output -u32 table_Pri_Ref[] = { - - Bits_32(1,01010100,0,0), // Reg 0 - Bits_32(1,01010100,0,0), // Outputs LVCMOS Positive&Negative Active - Non-inverted - Bits_32(1,01010100,0,0), - Bits_32(1,01010100,0,0), - Bits_32(1,01010100,0,0), // All have output divide ratio to be 1; Aux Output is OFF - - Bits_32(0,0,1001,11010100), // Reg 5 LVCMOS in; p31 of TI datasheet - - Bits_32(1,0,0010000,0), // Reg 6 // SCAS863A – NOVEMBER 2008 – REVISED JUNE 2011 - - Bits_32(1,01000000,0,0), // Reg 7 - // 76543210 - Bits_32(0,0,1,10000000) // Reg8 Status/Control +uint32_t table_Pri_Ref[] = { + Bits_32(1,01010100,0,0), // Reg 0 + Bits_32(1,01010100,0,0), // Outputs LVCMOS Positive&Negative Active - Non-inverted + Bits_32(1,01010100,0,0), + Bits_32(1,01010100,0,0), + Bits_32(1,01010100,0,0), // All have output divide ratio to be 1; Aux Output is OFF + Bits_32(0,0,1001,11010100), // Reg 5 LVCMOS in; p31 of TI datasheet + Bits_32(1,0,0010000,0), // Reg 6 // SCAS863A – NOVEMBER 2008 – REVISED JUNE 2011 + Bits_32(1,01000000,0,0), // Reg 7 + Bits_32(0,0,1,10000000) // Reg8 Status/Control }; - -// Looks like it's doing the correct thing re: SPI interface -// This is *definitely* AC coupled. I removed those resistors to +3.3 and ground -// signal looked no different with differential measurement. Added 240+470 to -// center tap of secondary side to bias up to approx 1.2V for proper LVDS -// -// For the External 10 MHz input LVDS with external termination -- Effectively DC coupled - -u32 table_Sec_Ref[] = { - Bits_32(0001,01010100,0,100000),// Reg 0 -- use Secondary Reference for all channels - Bits_32(0001,01010100,0,100000),// Outputs LVCMOS Positive&Negative Active - Non-inverted - Bits_32(0001,01010100,0,100000), - Bits_32(0001,01010100,0,100000), - Bits_32(0001,01010100,0,100000), - -// Bits_32(0,0,00001000,10010111), // Reg 5 LVDS with External Termination p32 of TI datasheet -// Bits_32(0,0,00001000,11010111), // Reg 5 LVDS with INTERNAL Termination p32 of TI datasheet - -// May 2013 -- Turn OFF the LVDS Safe Mode, as it supposedly causes input thresholds to be increased. - -// Bits_32(0,0,1001,10011011), // Reg 5, try again. Pretty soon, try new board... - - Bits_32(0,0,1,10011011), // Reg 5, Failsafe OFF b5.11 = 0 - - -// Bits_32(0,0,1001,11011011), // Reg 5, try again. Pretty soon, try new board... - // Try with DC input termination; bit 6 is a "1" 2013 March - // Seems to not work correctly. - - -// Bits_32(1,0,0000000,0), // Reg 6; note that 6.12 must be 1 for LVDS w/External Termination, 0 int -// Bits_32(1,0,0000000,0), // Reg 6; try Internal and DC coupling - Bits_32(1,0,10000,0), // Reg 6; try again - - Bits_32(1,01000000,0,0), - Bits_32(0,0,1,10000000) // Reg8 Status/Control +// For the External 10 MHz input LVDS with external termination, +// Effectively DC coupled +uint32_t table_Sec_Ref[] = { + Bits_32(0001,01010100,0,100000), // Reg 0 -- use Secondary Reference for all channels + Bits_32(0001,01010100,0,100000), // Outputs LVCMOS Positive&Negative Active - Non-inverted + Bits_32(0001,01010100,0,100000), + Bits_32(0001,01010100,0,100000), + Bits_32(0001,01010100,0,100000), + Bits_32(0,0,1,10011011), // Reg 5, Failsafe OFF b5.11 = 0 + Bits_32(1,0,10000,0), // Reg 6; try again + Bits_32(1,01000000,0,0), + Bits_32(0,0,1,10000000) // Reg8 Status/Control }; -//; Table 19 conflicts with Tables 5 thru 9 - in how LVCMOS outputs are defined +// Table 19 conflicts with Tables 5 thru 9 - in how LVCMOS outputs are defined // extra error in Table 9, for bits 24 and 25 -// -// Could combine these into just table[][] with 1st subscript being 0 or 1 for Primary or Secondary -// Maybe want to to that. +int table_size = sizeof (table_Pri_Ref) / sizeof(uint32_t); -int table_size = sizeof (table_Pri_Ref) / sizeof(u32); -//int table_size = 1; // Testing read and write of Register 0 -- don't want excess SPI transactions -//NOTE!!! Still need to shift left by 4 and OR in register, as defined in TI_CDCE18005 enum, above. +void set_bit(uint8_t bit_number, enum Levels bit_value) { - -enum Levels {Lo, Hi}; - -#define CLK (PA0) // Shift by 0 bits (PA.0) -#define CE_ (PA1) // Is really the "Chip Disable" signal, as Hi disables SPI -#define MOSI (PA2) -#define MISO (PA3) -#define PD_ (PA4) -#define SYNC_ (PA5) - -void -set_bit(u8 bit_number, enum Levels bit_value){ - - if(bit_value == Hi) - PORTA |= 1<> 4)], Control ); -// USART_Transmit( hex_table [0xf & portA], Control ); -// USART_Transmit(CR, Control); USART_Transmit(LF,Control); - - return (portA & 1<< bit_number) > 0 ? TRUE : FALSE; - //return (portA & 8) != 0; // It's always MISO, so nail it for the moment + uint8_t portA = PINA; + return (portA & 1<< bit_number) > 0 ? TRUE : FALSE; } - -void -send_SPI(u32 bits){ // Send 32 bits to TI chip, LSB first. -// Don't worry about reading any bits back at this -// time, although for production, may want to do that -// as an error-check / integrity check. +// Don't worry about reading any bits back at this time +void send_SPI(uint32_t bits) { + + // Basically, when the clock is low, one can set MOSI to anything, as it's + // ignored. + set_bit(CE_, Lo); // Start SPI transaction with TI chip + + // Send each bit, LSB first, add a bit of delay before the clock, and then + // toggle the clock line. + for (uint8_t i=0; i<32; i++) { + set_bit(MOSI, ((bits & (1UL<H on clock; (REALLY?) - set_bit(CLK, Hi); - set_bit(CLK, Lo); // Pulse the clock to clock in the bit - } -// USART_Transmit(CR, Control); USART_Transmit(LF,Control); - //set_bit(MOSI, Lo); // Not needed, but keeps all bits zeros except /CE when idle - set_bit(CE_, Hi); // OK, transaction is over -// USART_Transmit(CR, Control); USART_Transmit(LF,Control); + // OK, transaction is over + set_bit(CE_, Hi); } -// Takes about 7.6 ms to init all regs (as seen on scope) -// There is a very interesting phenomenon that is occurring --- The bit-to-bit time -// at the beginning of transmission is 15 usec. However, as the number of bits -// shifted to the left increases (as i increases in the for() loop ) -// the time between bits elongates. It's about 37 usec between bits -// 30 and 31 (the last 2 bits). It's kinda cool, because it's easy to -// know when the new word begins because the clock pulses will be -// closer together. - -// See if it checks: (15+37)/2 = 26 usec between average bits -// 32 bits * 9 words * 26 usec = 7.49 ms --- but have to add -// in the little bit of time that CE_ goes high; so 7.6 ms -// is a very reasonable number. (Assumes linear increase in -// time as the number of shifts goes up, which seems to -// work OK here.) -// -// Of course, using a table instead of doing those shifts all the -// time would fix this; but it (should not) doesn't matter for this -// SPI interface. -// -// So far, the first word looks good, and the beginning of writing -// Register 1 also looks good. -// +void reset_TI_CDCE18005() { + // First, reset the chip. Or, if you will, pull /SYNC low then high + set_bit(CE_, Hi); + set_bit(PD_, Lo); + wait(); + // Out of Power Down state + set_bit(PD_, Hi); + wait(); + set_bit(SYNC_, Lo); + wait(); + set_bit(SYNC_, Hi); - - - -// enum TI_Input_10_MHz {Primary_GPS, Secondary_Ext}; - -void -reset_TI_CDCE18005(){ -// First, reset the chip. Or, if you will, pull /SYNC low then high -set_bit(CE_, Hi); -set_bit(PD_, Lo); -wait(); // This should put the EEPROM bits into the RAM -- we don't care, but should init the chip - -set_bit(PD_, Hi); // Out of Power Down state -wait(); - -set_bit(SYNC_, Lo); -wait(); -set_bit(SYNC_, Hi); - -wait(); -// Now, by gosh, that darn chip ought to be fully enabled! -} - -void -setup_TI_CDCE18005(enum TI_Input_10_MHz which_input){ - // Send the table of data to init the clock distribution chip. Uses SPI. - u32 temp; - - //reset_TI_CDCE18005(); // This REALLY should not be necessary - - if(which_input == Primary_GPS){ - - for(u8 i=0; i>= 1; // get ready for next bit - NOTE: Only do this if we REALLY are putting in another bit - set_bit(CLK, Hi); // CPU is so slow, it easily meets setup & hold times - // 76543210 - if( get_bit(MISO) ) bits |= 0x80000000; // because we receive the LSB first - set_bit(CLK, Lo); // Pulse the clock to clock in the bit - } - set_bit(CE_, Hi); // OK, transaction is over - - return (u32)(bits >> 4); // Ditch the lower 4 bits, which only contain the address + wait(); } -u32 -get_TI_CDCE18005(enum CDCE18005 which_register){ - u32 get_reg_value; - - get_reg_value = 0; - get_reg_value = (0xf0 & which_register << 4) | Read_Command; - send_SPI(get_reg_value); // This tells the TI chip to send us the reg. value requested - return receive_SPI(); -}; +void setup_TI_CDCE18005(enum TI_Input_10_MHz which_input) { + // Send the table of data to init the clock distribution chip. Uses SPI. + uint32_t temp; + + if(which_input == Primary_GPS) { + for(uint8_t i=0; i>= 1; + set_bit(CLK, Hi); + if( get_bit(MISO) ) bits |= 0x80000000; + set_bit(CLK, Lo); + } + // OK, transaction is over + set_bit(CE_, Hi); + // Ditch the lower 4 bits, which only contain the address + return (uint32_t)(bits >> 4); +} +uint32_t get_TI_CDCE18005(enum CDCE18005 which_register){ + uint32_t get_reg_value = 0; + get_reg_value = (0xf0 & which_register << 4) | Read_Command; + // This tells the TI chip to send us the reg. value requested + send_SPI(get_reg_value); + return receive_SPI(); +} +bool check_TI_CDCE18005(enum TI_Input_10_MHz which_input, + enum CDCE18005 which_register) { + if(which_input == Primary_GPS){ + uint32_t read_value = get_TI_CDCE18005(which_register); + return read_value == table_Pri_Ref[which_register]; + } else { + uint32_t read_value = get_TI_CDCE18005(which_register); + return read_value == table_Sec_Ref[which_register]; + } +} -void -Setup_Atmel_IO_Ports(){ - - -///////////////////////////////////////////////////////////////////////////// +void Setup_Atmel_IO_Ports() { /* * PORT A - * - *pin# Sig Our Functional Name * - * p51 PA0 CLK_CDCE to U205 pin 24 -- L-->H edge latches MOSI and MISO in CDCE18005 - * p50 PA1 CE_CDCE Low = Chip Enabled for SPI comm to U205 pin 25 - * p49 PA2 MOSI_CDCE Goes to CDCE18005 - U205 pin 23 - * p48 PA3 MISO_CDCE Input Comes from U205 pin 22 - * p47 PA4 PD_CDCE Low = Chip is in Power-Down state; is Hi for normal operation U205 pin 12 - * p46 PA5 SYNC_CDCE Low = Chip is sync'd with interal dividers; Hi for normal operation U205 pin 14 - * p45 PA6 PPS_SEL Low --> PPS_EXT selected; Hi -> PPS_GPS selected; to U203 pin 1 - * p44 PA7 gps_lock Input Comes from M9107 - U206 pin 3 + * pin# Sig Our Functional Name + * + * p51 PA0 CLK_CDCE to U205 pin 24 -- L-->H edge latches MOSI and MISO in CDCE18005 + * p50 PA1 CE_CDCE Low = Chip Enabled for SPI comm to U205 pin 25 + * p49 PA2 MOSI_CDCE Goes to CDCE18005 - U205 pin 23 + * p48 PA3 MISO_CDCE Input Comes from U205 pin 22 + * p47 PA4 PD_CDCE Low = Chip is in Power-Down state; is Hi for normal operation U205 pin 12 + * p46 PA5 SYNC_CDCE Low = Chip is sync'd with interal dividers; Hi for normal operation U205 pin 14 + * p45 PA6 PPS_SEL Low --> PPS_EXT selected; Hi -> PPS_GPS selected; to U203 pin 1 + * p44 PA7 gps_lock Input Comes from M9107 - U206 pin 3 * */ -// Bit #: 76543210 -PORTA = Bits_8(00110010); // /pd_cdcd, /sync_code, /ce need to be 1 (disabled) to start -DDRA = 1< -Matt Ettus -Josh Blum -Nick Foster diff --git a/firmware/zpu/README b/firmware/zpu/README deleted file mode 100644 index ba0aa11eb..000000000 --- a/firmware/zpu/README +++ /dev/null @@ -1,16 +0,0 @@ -######################################################################## -# ZPU firmware code for USRP2 and N Series -######################################################################## -This code requires the gcc-zpu tool-chain which can be found here: - -http://opensource.zylin.com/zpudownload.html - -zpu-elf-gcc should be in your $PATH - -######################################################################## -# Run the following commands to build -######################################################################## -mkdir build -cd build -cmake ../ -make diff --git a/host/AUTHORS.txt b/host/AUTHORS.txt deleted file mode 100644 index 44b7516cd..000000000 --- a/host/AUTHORS.txt +++ /dev/null @@ -1,40 +0,0 @@ -Matt Ettus - matt@ettus.com - USRP1 FPGA code - USRP2/N200 FPGA code - USRP-E100 FPGA code - -Josh Blum - josh@ettus.com - driver framework - USRP2/N200 firmware - USRP2/N200 host code - USRP-E100 host code - Basic/LF host code - XCVR2450 host code - RFX Series host code - -Jason Abele - jason@ettus.com - RFX Series host code - WBX host code - DBSRX host code - DBSRX2 host code - -Eric Blossom - eb@comsec.com - USRP1 firmware - USRP2 firmware - -Tom Tsou - ttsou@vt.edu - UHD-USB framework - LIBUSB host code - USRP1 host code - USRP1 firmware - -Nick Foster - nick@ettus.com - LIBUSB host code - USRP1 host code - TVRX host code - USRP-N200 firmware - USRP-N200 host code - -Philip Balister - philip@opensdr.com - USRP-E100 kernel module - USRP-E100 utilities diff --git a/host/LICENSE b/host/LICENSE new file mode 100644 index 000000000..9aa03b39b --- /dev/null +++ b/host/LICENSE @@ -0,0 +1,12 @@ +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . diff --git a/host/LICENSE.txt b/host/LICENSE.txt deleted file mode 100644 index 9aa03b39b..000000000 --- a/host/LICENSE.txt +++ /dev/null @@ -1,12 +0,0 @@ -This program is free software: you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation, either version 3 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program. If not, see . diff --git a/host/README.txt b/host/README.txt deleted file mode 100644 index 0e8e62ac1..000000000 --- a/host/README.txt +++ /dev/null @@ -1,43 +0,0 @@ -############################################### -# Ettus Research - USRP Hardware Driver -############################################### -The hardware driver for Ettus Research products. - -############################################### -# Supported USRP Motherboards -############################################### -USRP1 -USRP2 -N200 -N210 -E100 -E110 -B100 -B200 - -############################################### -# Supported USRP Daughterboards -############################################### -Basic RX -Basic TX -LF RX -LF TX -RFX Series -XCVR 2450 -WBX + Simple GDB -DBSRX -DBSRX2 -TVRX -TVRX2 -SBX -CBX - -############################################### -# Documentation -############################################### -Online documentation available at: -http://code.ettus.com/redmine/ettus/projects/uhd/wiki - -The build system can generate the html for the manual and Doxygen. -Docutils and Doxygen are required to build the html docs. -See the docs directory for the manual source (reStructuredText). diff --git a/host/apps/omap_debug/README b/host/apps/omap_debug/README deleted file mode 100644 index bbe0c2cc4..000000000 --- a/host/apps/omap_debug/README +++ /dev/null @@ -1 +0,0 @@ -OMAP development tools go here diff --git a/host/cmake/Modules/FindUSB1.cmake b/host/cmake/Modules/FindUSB1.cmake index a494e1350..b2e4d118c 100644 --- a/host/cmake/Modules/FindUSB1.cmake +++ b/host/cmake/Modules/FindUSB1.cmake @@ -8,7 +8,8 @@ PKG_CHECK_MODULES(PC_LIBUSB QUIET libusb-1.0) FIND_PATH(LIBUSB_INCLUDE_DIRS NAMES libusb.h - HINTS $ENV{LIBUSB_DIR}/include ${PC_LIBUSB_INCLUDEDIR} + HINTS $ENV{LIBUSB_DIR}/include $ENV{LIBUSB_DIR}/include/libusb-1.0 + ${PC_LIBUSB_INCLUDEDIR} ${PC_LIBUSB_INCLUDEDIR}/libusb-1.0 PATHS /usr/local/include/libusb-1.0 /usr/local/include /usr/include/libusb-1.0 /usr/include /opt/local/include/libusb-1.0 diff --git a/host/docs/uhd_find_devices.1 b/host/docs/uhd_find_devices.1 index 7dc0dd470..08f9a789c 100644 --- a/host/docs/uhd_find_devices.1 +++ b/host/docs/uhd_find_devices.1 @@ -9,9 +9,6 @@ The UHD package is the universal hardware driver for Ettus Research products. The goal is to provide a host driver and API for current and future Ettus Research products. Users will be able to use the UHD driver standalone or with 3rd party applications. -.LP -Hardware supporting UHD drivers includes the Universal Software Radio -Peripheral, or USRP, available in several models. .SH SYNOPSIS .B uhd_find_devices [OPTIONS] .SH OPTIONS diff --git a/host/docs/uhd_images_downloader.1 b/host/docs/uhd_images_downloader.1 index ece826cb5..28310dd37 100644 --- a/host/docs/uhd_images_downloader.1 +++ b/host/docs/uhd_images_downloader.1 @@ -7,9 +7,6 @@ products. The goal of the UHD is to provide a host driver and API for current and future Ettus Research products. Users will be able to use the UHD driver standalone or with 3rd party applications. .LP -Hardware supporting UHD drivers includes the Universal Software Radio -Peripheral, or USRP, available in several models. -.LP This program installs the firmware and FPGA binaries from Ettus Research matching this UHD driver release onto the host system. If the uhd-images package is installed, there is no need to run this installer. diff --git a/host/docs/uhd_usrp_probe.1 b/host/docs/uhd_usrp_probe.1 index 7e82bf99a..a6c7150ee 100644 --- a/host/docs/uhd_usrp_probe.1 +++ b/host/docs/uhd_usrp_probe.1 @@ -1,6 +1,6 @@ .TH "uhd_usrp_probe" 1 "3.5.1" UHD "User Commands" .SH NAME -uhd_usrp_probe \- Universal Hardware Driver Peripheral Report Utility +uhd_usrp_probe \- USRP Hardware Driver Peripheral Report Utility .SH DESCRIPTION Report detailed information on UHD-supported Software Radio Peripherals attached by USB, network, or embedded configuration. diff --git a/host/lib/usrp/README b/host/lib/usrp/README deleted file mode 100644 index 344209179..000000000 --- a/host/lib/usrp/README +++ /dev/null @@ -1,15 +0,0 @@ -######################################################################## -# lib USRP directories: -######################################################################## - -dboard: - Daughterboard implementation code for all USRP daughterboards - -usrp1: - Implementation code for the USB-based USRP Classic motherboard. - -usrp2: - Implementation code for USRP2, USRP-N200, and USRP-N210. - -usrp_e100: - Implementation code for USRP-E100. diff --git a/images/Makefile b/images/Makefile index 2e3bcfd26..6b1cfcfc4 100644 --- a/images/Makefile +++ b/images/Makefile @@ -117,7 +117,7 @@ $(_usrp_b100_fpga_2rx_bin): $(GLOBAL_DEPS) endif ######################################################################## -# USRP2 and N Series firmware +# USRP2 and N-Series firmware ######################################################################## ifdef HAS_ZPU_GCC @@ -143,7 +143,7 @@ $(_usrp_n210_fw_bin): $(_usrp2_fw_bin) endif ######################################################################## -# USRP2 fpga +# USRP2 FPGA ######################################################################## ifdef HAS_XTCLSH @@ -159,7 +159,7 @@ $(_usrp2_fpga_bin): $(GLOBAL_DEPS) endif ######################################################################## -# USRP-N200 R2/R3 fpga +# USRP N200 R2/R3 FPGA ######################################################################## ifdef HAS_XTCLSH @@ -185,7 +185,7 @@ $(_usrp_n200_r2_fpga_bin): $(_usrp_n200_r3_fpga_bin) endif ######################################################################## -# USRP-N210 R2/R3 fpga +# USRP N210 R2/R3 FPGA ######################################################################## ifdef HAS_XTCLSH @@ -211,7 +211,7 @@ $(_usrp_n210_r2_fpga_bin): $(_usrp_n210_r3_fpga_bin) endif ######################################################################## -# USRP-N200 R4 fpga +# USRP N200 R4 FPGA ######################################################################## ifdef HAS_XTCLSH @@ -231,7 +231,7 @@ $(_usrp_n200_r4_fpga_bit): $(_usrp_n200_r4_fpga_bin) endif ######################################################################## -# USRP-N210 R4 fpga +# USRP N210 R4 FPGA ######################################################################## ifdef HAS_XTCLSH @@ -251,7 +251,7 @@ $(_usrp_n210_r4_fpga_bit): $(_usrp_n210_r4_fpga_bin) endif ######################################################################## -# USRP-E100 fpga +# USRP E100 FPGA ######################################################################## ifdef HAS_XTCLSH @@ -267,7 +267,7 @@ $(_usrp_e100_fpga_bin): $(GLOBAL_DEPS) endif ######################################################################## -# USRP-E110 fpga +# USRP E110 FPGA ######################################################################## ifdef HAS_XTCLSH diff --git a/images/README.md b/images/README.md new file mode 100644 index 000000000..b9e3232aa --- /dev/null +++ b/images/README.md @@ -0,0 +1,35 @@ +UHD Firmware and FPGA Images Builder +=============================================================== + +The images directory contains the following: +* A Makefile for building firmware and FPGA images +* A CMake file for building an images package + +This provides a clean and organized way to build all of the firmware and FPGA +images, the source code for which is in the `firmware` and `fpga` directories +one level above this. + +The Makefile and build systems for the images are *probably* Unix-specific. +It's best to build the images on a Unix system with standard build tools. The +CMake package target will create an installable images package for your system. + +__To build the images (unix):__ + +1. `make clean` +2. `make images` + +__To build the package (unix):__ + +1. `mkdir build` +2. `cd build` +3. `cmake -DCPACK_GENERATOR= ../` +4. `make package` + +The package generator types are described here: +http://www.cmake.org/Wiki/CMake:CPackPackageGenerators + +__Fedora note:__ + +The sdcc binaries are prefixed with "sdcc-" which breaks the build. +However, /usr/libexec/sdcc contains properly named sdcc binaries. +`export PATH=${PATH}:/usr/libexec/sdcc` diff --git a/images/README.txt b/images/README.txt deleted file mode 100644 index 2f9c6a95e..000000000 --- a/images/README.txt +++ /dev/null @@ -1,25 +0,0 @@ -The images directory contains the following: - - a Makefile for building firmware and fpga images - - a CMake file for building an images package - -The Makefile and build systems for the images are probably Unix specific. -Its best to build the images on a Unix system with standard build tools. -The CMake package target will create an images package for your system. - -To build the images (unix): - make clean - make images - -To build the package (unix): - mkdir build - cd build - cmake -DCPACK_GENERATOR= ../ - make package - -The package generator types are described here: - http://www.cmake.org/Wiki/CMake:CPackPackageGenerators - -Fedora note: - The sdcc binaries are prefixed with "sdcc-" which breaks the build. - However, /usr/libexec/sdcc contains properly named sdcc binaries. - export PATH=${PATH}:/usr/libexec/sdcc -- cgit v1.2.3